STM CMSIS
RCC Private macros to check input parameters

Macros

#define IS_RCC_OSCILLATORTYPE(OSCILLATOR)   ((OSCILLATOR) <= 15U)
 
#define IS_RCC_HSE(HSE)
 
#define IS_RCC_LSE(LSE)
 
#define IS_RCC_HSI(HSI)   (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
 
#define IS_RCC_LSI(LSI)   (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
 
#define IS_RCC_PLL(PLL)   (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
 
#define IS_RCC_PLLSOURCE(SOURCE)
 
#define IS_RCC_SYSCLKSOURCE(SOURCE)
 
#define IS_RCC_RTCCLKSOURCE(__SOURCE__)
 
#define IS_RCC_PLLM_VALUE(VALUE)   ((VALUE) <= 63U)
 
#define IS_RCC_PLLP_VALUE(VALUE)   (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
 
#define IS_RCC_PLLQ_VALUE(VALUE)   ((4U <= (VALUE)) && ((VALUE) <= 15U))
 
#define IS_RCC_HCLK(HCLK)
 
#define IS_RCC_CLOCKTYPE(CLK)   ((1U <= (CLK)) && ((CLK) <= 15U))
 
#define IS_RCC_PCLK(PCLK)
 
#define IS_RCC_MCO(MCOx)   (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
 
#define IS_RCC_MCO1SOURCE(SOURCE)
 
#define IS_RCC_MCODIV(DIV)
 
#define IS_RCC_CALIBRATION_VALUE(VALUE)   ((VALUE) <= 0x1FU)
 

Detailed Description

Macro Definition Documentation

◆ IS_RCC_HCLK

#define IS_RCC_HCLK (   HCLK)
Value:
(((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
((HCLK) == RCC_SYSCLK_DIV512))

◆ IS_RCC_HSE

#define IS_RCC_HSE (   HSE)
Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_BYPASS))

◆ IS_RCC_LSE

#define IS_RCC_LSE (   LSE)
Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_BYPASS))

◆ IS_RCC_MCO1SOURCE

#define IS_RCC_MCO1SOURCE (   SOURCE)
Value:
(((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))

◆ IS_RCC_MCODIV

#define IS_RCC_MCODIV (   DIV)
Value:
(((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
((DIV) == RCC_MCODIV_5))

◆ IS_RCC_PCLK

#define IS_RCC_PCLK (   PCLK)
Value:
(((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
((PCLK) == RCC_HCLK_DIV16))

◆ IS_RCC_PLLSOURCE

#define IS_RCC_PLLSOURCE (   SOURCE)
Value:
(((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_HSE))

◆ IS_RCC_SYSCLKSOURCE

#define IS_RCC_SYSCLKSOURCE (   SOURCE)
Value:
(((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))