Go to the documentation of this file. 40 #ifndef __STM32_HAL_LEGACY 41 #define __STM32_HAL_LEGACY 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 76 #define REGULAR_GROUP ADC_REGULAR_GROUP 77 #define INJECTED_GROUP ADC_INJECTED_GROUP 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 79 #define AWD_EVENT ADC_AWD_EVENT 80 #define AWD1_EVENT ADC_AWD1_EVENT 81 #define AWD2_EVENT ADC_AWD2_EVENT 82 #define AWD3_EVENT ADC_AWD3_EVENT 83 #define OVR_EVENT ADC_OVR_EVENT 84 #define JQOVF_EVENT ADC_JQOVF_EVENT 85 #define ALL_CHANNELS ADC_ALL_CHANNELS 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 91 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 92 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 93 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 94 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 95 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 96 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 97 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 98 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 99 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 100 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 101 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 102 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 103 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 104 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 106 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 108 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 109 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 110 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 111 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 112 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 113 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 114 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 141 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 142 #if defined(STM32F373xC) || defined(STM32F378xx) 143 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 144 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 147 #if defined(STM32L0) || defined(STM32L4) 148 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 150 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 151 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 152 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 154 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 155 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 156 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 157 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 158 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 159 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 160 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 161 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 162 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 163 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 164 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 165 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 166 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 168 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 169 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 173 #if defined(COMP_CSR_LOCK) 174 #define COMP_FLAG_LOCK COMP_CSR_LOCK 175 #elif defined(COMP_CSR_COMP1LOCK) 176 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 177 #elif defined(COMP_CSR_COMPxLOCK) 178 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 182 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 183 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 184 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 185 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 186 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 187 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 188 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 192 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 193 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 195 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 196 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 197 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 198 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 209 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 218 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 219 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 229 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 230 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 231 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 232 #define DAC_WAVE_NONE ((uint32_t)0x00000000U) 233 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) 234 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) 235 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 236 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 237 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 246 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 247 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 248 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 249 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 250 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 251 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 252 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 253 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 254 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 255 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 256 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 257 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 258 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 259 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 260 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 262 #define IS_HAL_REMAPDMA IS_DMA_REMAP 263 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 264 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 276 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 277 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 278 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 279 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 280 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 281 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 282 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 283 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 284 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 285 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 286 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 287 #define OBEX_PCROP OPTIONBYTE_PCROP 288 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 289 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 290 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 291 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 292 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 293 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 294 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 295 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 296 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 297 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 298 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 299 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 300 #define PAGESIZE FLASH_PAGE_SIZE 301 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 302 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 303 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 304 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 305 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 306 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 307 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 308 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 309 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 310 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 311 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 312 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 313 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 314 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 315 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 316 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 317 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 318 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 319 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 320 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 321 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 322 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 323 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 324 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 325 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 326 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 327 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 328 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 329 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 330 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 331 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 332 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 333 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 334 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 335 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 336 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 337 #define OB_WDG_SW OB_IWDG_SW 338 #define OB_WDG_HW OB_IWDG_HW 339 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 340 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 341 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 342 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 343 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 344 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 345 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 346 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 355 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 356 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 357 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 358 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 359 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 360 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 361 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 362 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 363 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 372 #if defined(STM32L4) || defined(STM32F7) 373 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 374 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 375 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 376 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 378 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 379 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 380 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 381 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 391 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 392 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 400 #define GET_GPIO_SOURCE GPIO_GET_INDEX 401 #define GET_GPIO_INDEX GPIO_GET_INDEX 404 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 405 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 409 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 410 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 414 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 415 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 418 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 419 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 420 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 422 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) 423 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 424 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 425 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 426 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 430 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 431 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 432 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 433 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 436 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 437 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 438 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 439 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 442 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 450 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 451 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 452 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 453 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 454 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 455 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 456 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 457 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 458 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 460 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 461 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 462 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 463 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 464 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 465 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 466 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 467 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 475 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 476 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 477 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 478 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 479 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 480 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 481 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 482 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 483 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 484 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 485 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 486 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 487 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 488 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 489 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 498 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 499 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 508 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 509 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 510 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 511 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 520 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 521 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 522 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 523 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 525 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 526 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 527 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 529 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 530 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 531 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 532 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 536 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 537 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 538 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 547 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 548 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 549 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 550 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 552 #define NAND_AddressTypedef NAND_AddressTypeDef 554 #define __ARRAY_ADDRESS ARRAY_ADDRESS 555 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 556 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 557 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 558 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 566 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 567 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 568 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 569 #define NOR_ERROR HAL_NOR_STATUS_ERROR 570 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 572 #define __NOR_WRITE NOR_WRITE 573 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 582 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 583 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 584 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 585 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 587 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 588 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 589 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 590 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 592 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 593 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 595 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 596 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 598 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 599 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 601 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 603 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 604 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 605 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 614 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 616 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 627 #define CF_DATA ATA_DATA 628 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 629 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 630 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 631 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 632 #define CF_CARD_HEAD ATA_CARD_HEAD 633 #define CF_STATUS_CMD ATA_STATUS_CMD 634 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 635 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 638 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 639 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 640 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 641 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 643 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 644 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 645 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 646 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 647 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 656 #define FORMAT_BIN RTC_FORMAT_BIN 657 #define FORMAT_BCD RTC_FORMAT_BCD 659 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 660 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 661 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 662 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 663 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 665 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 666 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 667 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 668 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 669 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 670 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 671 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 672 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 674 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 675 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 676 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 677 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 679 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 680 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 681 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 683 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 684 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 685 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 695 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 696 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 698 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 699 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 700 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 701 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 703 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 704 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 706 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 707 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 716 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 717 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 718 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 719 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 720 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 721 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 722 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 723 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 724 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 725 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 726 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 734 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 735 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 737 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 738 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 740 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 741 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 750 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 751 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 753 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 754 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 755 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 756 #define TIM_DMABase_DIER TIM_DMABASE_DIER 757 #define TIM_DMABase_SR TIM_DMABASE_SR 758 #define TIM_DMABase_EGR TIM_DMABASE_EGR 759 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 760 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 761 #define TIM_DMABase_CCER TIM_DMABASE_CCER 762 #define TIM_DMABase_CNT TIM_DMABASE_CNT 763 #define TIM_DMABase_PSC TIM_DMABASE_PSC 764 #define TIM_DMABase_ARR TIM_DMABASE_ARR 765 #define TIM_DMABase_RCR TIM_DMABASE_RCR 766 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 767 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 768 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 769 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 770 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 771 #define TIM_DMABase_DCR TIM_DMABASE_DCR 772 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 773 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 774 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 775 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 776 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 777 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 778 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 779 #define TIM_DMABase_OR TIM_DMABASE_OR 781 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 782 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 783 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 784 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 785 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 786 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 787 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 788 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 789 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 791 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 792 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 793 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 794 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 795 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 796 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 797 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 798 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 799 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 800 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 801 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 802 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 803 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 804 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 805 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 806 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 807 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 808 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 817 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 818 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 826 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 827 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 828 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 829 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 831 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 832 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 834 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 835 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 836 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 837 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 839 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 840 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 841 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 842 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 844 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 845 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 856 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 857 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 859 #define USARTNACK_ENABLED USART_NACK_ENABLE 860 #define USARTNACK_DISABLED USART_NACK_DISABLE 868 #define CFR_BASE WWDG_CFR_BASE 877 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 878 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 879 #define CAN_IT_RQCP0 CAN_IT_TME 880 #define CAN_IT_RQCP1 CAN_IT_TME 881 #define CAN_IT_RQCP2 CAN_IT_TME 882 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 883 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 884 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 885 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 886 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 896 #define VLAN_TAG ETH_VLAN_TAG 897 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 898 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 899 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 900 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 901 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 902 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 903 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 905 #define ETH_MMCCR ((uint32_t)0x00000100U) 906 #define ETH_MMCRIR ((uint32_t)0x00000104U) 907 #define ETH_MMCTIR ((uint32_t)0x00000108U) 908 #define ETH_MMCRIMR ((uint32_t)0x0000010CU) 909 #define ETH_MMCTIMR ((uint32_t)0x00000110U) 910 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) 911 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) 912 #define ETH_MMCTGFCR ((uint32_t)0x00000168U) 913 #define ETH_MMCRFCECR ((uint32_t)0x00000194U) 914 #define ETH_MMCRFAECR ((uint32_t)0x00000198U) 915 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) 917 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) 918 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) 919 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) 920 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) 921 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) 922 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) 923 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) 924 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) 925 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) 926 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) 927 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) 928 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) 929 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) 930 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) 931 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) 932 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) 933 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) 936 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) 937 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) 938 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) 940 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) 941 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) 942 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) 943 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) 944 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) 945 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) 946 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) 955 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 956 #define DCMI_IT_OVF DCMI_IT_OVR 957 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 958 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 960 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 961 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 962 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 968 #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ 969 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 973 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 974 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 975 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 976 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 977 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 979 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 980 #define CM_RGB888 DMA2D_INPUT_RGB888 981 #define CM_RGB565 DMA2D_INPUT_RGB565 982 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 983 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 984 #define CM_L8 DMA2D_INPUT_L8 985 #define CM_AL44 DMA2D_INPUT_AL44 986 #define CM_AL88 DMA2D_INPUT_AL88 987 #define CM_L4 DMA2D_INPUT_L4 988 #define CM_A8 DMA2D_INPUT_A8 989 #define CM_A4 DMA2D_INPUT_A4 1008 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1016 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1017 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1018 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1019 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1020 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1021 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1025 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1026 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1027 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1028 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1030 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1031 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1033 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1034 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1042 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1043 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1044 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1045 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1046 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1047 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1048 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1049 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1050 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1051 #if defined(STM32L0) 1053 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1055 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1056 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1064 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1065 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1066 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1067 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1068 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1069 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1070 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1079 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1080 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1081 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1082 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1084 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1092 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1093 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1094 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1095 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1096 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1097 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1098 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1099 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1100 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1101 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1102 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1103 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1104 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1105 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1106 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1107 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1109 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1110 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1111 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1112 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1113 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1114 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1115 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1117 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1118 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1120 #define DBP_BitNumber DBP_BIT_NUMBER 1121 #define PVDE_BitNumber PVDE_BIT_NUMBER 1122 #define PMODE_BitNumber PMODE_BIT_NUMBER 1123 #define EWUP_BitNumber EWUP_BIT_NUMBER 1124 #define FPDS_BitNumber FPDS_BIT_NUMBER 1125 #define ODEN_BitNumber ODEN_BIT_NUMBER 1126 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1127 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1128 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1129 #define BRE_BitNumber BRE_BIT_NUMBER 1131 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1140 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1141 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1142 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1150 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1158 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1159 #define HAL_TIM_DMAError TIM_DMAError 1160 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1161 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1169 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1177 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1196 #define AES_IT_CC CRYP_IT_CC 1197 #define AES_IT_ERR CRYP_IT_ERR 1198 #define AES_FLAG_CCF CRYP_FLAG_CCF 1206 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1207 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1208 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1209 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1210 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1211 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1212 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1213 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1214 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1215 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1216 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1217 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1218 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1220 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1221 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1222 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1223 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1224 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1234 #define __ADC_ENABLE __HAL_ADC_ENABLE 1235 #define __ADC_DISABLE __HAL_ADC_DISABLE 1236 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1237 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1238 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1239 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1240 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1241 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1242 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1243 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1244 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1245 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1246 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1248 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1249 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1250 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1251 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1252 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1253 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1254 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1255 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1256 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1257 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1258 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1259 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1260 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1261 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1262 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1263 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1264 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1265 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1266 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1267 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1269 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1270 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1271 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1272 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1273 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1274 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1275 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1276 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1277 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1278 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1280 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1281 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1282 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1283 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1284 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1285 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1286 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1287 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1289 #define __HAL_ADC_SQR1 ADC_SQR1 1290 #define __HAL_ADC_SMPR1 ADC_SMPR1 1291 #define __HAL_ADC_SMPR2 ADC_SMPR2 1292 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1293 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1294 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1295 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1296 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1297 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1298 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1299 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1300 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1301 #define __HAL_ADC_JSQR ADC_JSQR 1303 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1304 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1305 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1306 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1307 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1308 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1309 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1310 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1319 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1320 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 1321 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 1322 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 1331 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 1332 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 1333 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 1334 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 1335 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 1336 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 1337 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 1338 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 1339 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 1340 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 1341 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 1342 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 1343 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 1344 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 1345 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 1346 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 1348 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 1349 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 1350 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 1351 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 1352 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 1353 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 1354 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 1355 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 1356 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 1357 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 1358 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 1359 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 1360 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 1361 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 1364 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 1365 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 1366 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 1367 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 1368 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 1369 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 1370 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 1371 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 1372 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 1373 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 1374 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 1375 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 1376 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 1377 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 1378 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 1379 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 1380 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 1381 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 1382 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 1383 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 1384 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 1385 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 1386 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 1387 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 1396 #if defined(STM32F3) 1397 #define COMP_START __HAL_COMP_ENABLE 1398 #define COMP_STOP __HAL_COMP_DISABLE 1399 #define COMP_LOCK __HAL_COMP_LOCK 1401 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 1402 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1403 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1404 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1405 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1406 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1407 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1408 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1409 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1410 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1411 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1412 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1413 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1414 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1415 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1416 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 1417 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1418 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1419 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 1420 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1421 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1422 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 1423 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1424 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1425 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 1427 # if defined(STM32F302xE) || defined(STM32F302xC) 1428 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1429 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1430 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1431 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1432 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1433 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1434 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1435 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1436 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1437 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1438 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1439 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1440 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1441 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1442 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1443 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1444 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1445 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1446 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1447 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 1448 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1449 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1450 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1451 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 1452 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1453 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1454 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1455 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 1456 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1457 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1458 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1459 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 1461 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 1462 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1463 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1464 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 1465 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1466 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 1467 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 1468 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 1469 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1470 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1471 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 1472 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1473 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 1474 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 1475 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 1476 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1477 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1478 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 1479 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1480 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 1481 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 1482 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 1483 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1484 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1485 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 1486 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1487 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 1488 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 1489 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 1490 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1491 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1492 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 1493 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1494 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 1495 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 1496 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 1497 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1498 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1499 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 1500 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1501 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 1502 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 1503 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 1504 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1505 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1506 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 1507 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1508 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 1509 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 1510 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 1511 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1512 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1513 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 1514 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1515 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 1516 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 1517 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 1519 # if defined(STM32F373xC) ||defined(STM32F378xx) 1520 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1521 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 1522 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1523 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 1524 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1525 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 1526 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1527 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 1528 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1529 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 1530 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1531 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 1532 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1533 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 1534 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1535 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 1538 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1539 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 1540 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1541 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 1542 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1543 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 1544 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1545 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 1546 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1547 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 1548 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1549 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 1550 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1551 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 1552 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1553 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 1556 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 1558 #if defined(STM32L0) || defined(STM32L4) 1563 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 1569 #if defined(STM32L0) || defined(STM32L4) 1573 #define HAL_COMP_Start_IT HAL_COMP_Start 1574 #define HAL_COMP_Stop_IT HAL_COMP_Stop 1584 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 1585 ((WAVE) == DAC_WAVE_NOISE)|| \ 1586 ((WAVE) == DAC_WAVE_TRIANGLE)) 1596 #define IS_WRPAREA IS_OB_WRPAREA 1597 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 1598 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 1599 #define IS_TYPEERASE IS_FLASH_TYPEERASE 1600 #define IS_NBSECTORS IS_FLASH_NBSECTORS 1601 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 1611 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 1612 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 1613 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 1614 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 1615 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 1616 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 1617 #define __HAL_I2C_SPEED I2C_SPEED 1618 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 1619 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 1620 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 1621 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 1622 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 1623 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 1624 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 1625 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 1634 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 1635 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 1645 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 1646 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 1648 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 1649 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 1650 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 1651 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 1653 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 1664 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 1665 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 1675 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 1676 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 1677 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 1687 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 1688 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 1689 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 1690 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 1691 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 1692 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 1693 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 1694 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 1695 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 1696 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 1697 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 1698 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 1699 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 1709 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 1710 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 1711 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 1712 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 1713 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 1714 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 1715 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 1716 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 1717 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 1718 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 1719 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 1720 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 1721 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 1722 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 1723 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 1724 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 1725 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 1726 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 1727 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 1728 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 1729 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 1730 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 1731 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 1732 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 1733 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 1734 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 1735 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 1736 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 1737 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 1738 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 1739 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 1740 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 1741 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 1742 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 1743 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 1745 #if defined (STM32F4) 1746 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 1747 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 1748 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 1749 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 1750 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 1752 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 1753 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 1754 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 1755 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 1756 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 1767 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 1768 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 1770 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 1771 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 1773 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 1774 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 1775 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 1776 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 1777 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 1778 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 1779 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 1780 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 1781 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 1782 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 1783 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 1784 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 1785 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 1786 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 1787 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 1788 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 1789 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 1790 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 1791 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 1792 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 1793 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 1794 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 1795 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 1796 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 1797 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 1798 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 1799 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 1800 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 1801 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 1802 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 1803 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 1804 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 1805 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 1806 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 1807 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 1808 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 1809 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 1810 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 1811 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 1812 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 1813 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 1814 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 1815 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 1816 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 1817 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 1818 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 1819 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 1820 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 1821 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 1822 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 1823 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 1824 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 1825 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 1826 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 1827 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 1828 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 1829 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 1830 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 1831 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 1832 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 1833 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 1834 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 1835 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 1836 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 1837 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 1838 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 1839 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 1840 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 1841 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 1842 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 1843 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 1844 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 1845 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 1846 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 1847 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 1848 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 1849 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 1850 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 1851 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 1852 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 1853 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 1854 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 1855 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 1856 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 1857 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 1858 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 1859 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 1860 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 1861 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 1862 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 1863 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 1864 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 1865 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 1866 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 1867 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 1868 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 1869 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 1870 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 1871 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 1872 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 1873 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 1874 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 1875 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 1876 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 1877 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 1878 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 1879 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 1880 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 1881 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 1882 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 1883 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 1884 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 1885 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 1886 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 1887 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 1888 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 1889 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 1890 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 1891 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 1892 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 1893 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 1894 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 1895 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 1896 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 1897 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 1898 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 1899 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 1900 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 1901 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 1902 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 1903 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 1904 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 1905 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 1906 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 1907 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 1908 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 1909 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 1910 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 1911 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 1912 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 1913 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 1914 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 1915 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 1916 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 1917 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 1918 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 1919 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 1920 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 1921 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 1922 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 1923 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 1924 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 1925 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 1926 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 1927 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 1928 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 1929 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 1930 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 1931 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 1932 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 1933 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 1934 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 1935 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 1936 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 1937 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 1938 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 1939 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 1940 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 1941 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 1942 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 1943 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 1944 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 1945 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 1946 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 1947 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 1948 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 1949 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 1950 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 1951 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 1952 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 1953 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 1954 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 1955 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 1956 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 1957 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 1958 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 1959 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 1960 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 1961 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 1962 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 1963 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 1964 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 1965 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 1966 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 1967 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 1968 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 1969 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 1970 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 1971 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 1972 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 1973 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 1974 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 1975 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 1976 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 1977 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 1978 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 1979 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 1980 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 1981 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 1982 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 1983 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 1984 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 1985 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 1986 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 1987 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 1988 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 1989 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 1990 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 1991 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 1992 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 1993 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 1994 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 1995 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 1996 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 1997 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 1998 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 1999 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2000 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2001 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2002 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2003 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2004 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2005 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2006 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2007 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2008 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2009 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2010 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2011 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2012 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2013 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2014 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2015 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2016 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2017 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2018 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2019 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2020 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2021 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2022 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2023 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2024 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2025 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2026 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2027 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2028 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2029 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2030 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2031 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2032 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2033 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2034 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2035 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2036 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2037 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2038 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2039 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2040 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2041 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2042 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2043 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2044 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2045 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2046 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2047 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2048 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2049 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2050 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2051 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2052 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2053 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2054 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2055 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2056 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2057 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2058 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2059 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2060 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2061 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2062 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2063 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2064 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2065 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2066 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2067 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2068 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2069 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2070 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2071 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2072 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2073 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2074 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2075 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2076 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2077 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2078 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2079 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2080 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2081 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2082 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2083 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2084 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2085 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2086 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2087 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2088 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2089 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2090 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2091 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2092 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2093 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2094 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2095 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2096 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2097 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2098 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2099 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2100 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2101 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2102 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2103 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2104 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2105 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2106 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2107 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2108 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2109 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2110 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2111 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2112 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2113 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2114 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2115 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2116 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2117 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2118 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2119 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2120 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2121 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2122 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2123 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2124 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2125 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2126 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2127 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2128 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2129 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2130 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2131 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2132 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2133 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2134 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2135 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2136 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2137 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2138 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2139 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2140 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2141 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2142 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2143 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2144 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2145 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2146 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2147 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2148 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2149 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2150 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2151 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2152 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2153 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2154 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2155 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2156 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2157 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2158 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2159 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2160 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2161 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2162 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2163 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2164 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2165 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2166 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2167 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2168 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2169 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2170 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2171 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2172 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2173 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2174 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2175 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2176 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2177 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2178 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2179 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2180 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2181 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2182 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2183 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2184 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2185 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2186 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2187 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2188 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2189 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2190 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2191 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2192 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2193 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2194 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2195 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2196 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2197 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2198 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2199 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2200 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2201 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2202 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2203 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2204 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2205 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2206 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2207 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2208 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2209 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2210 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2211 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2212 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2213 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2214 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2215 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2216 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2217 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2218 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2219 #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE 2220 #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE 2221 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE 2222 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE 2223 #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET 2224 #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET 2225 #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE 2226 #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE 2227 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE 2228 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE 2229 #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET 2230 #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET 2231 #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE 2232 #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE 2233 #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET 2234 #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET 2235 #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE 2236 #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE 2237 #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET 2238 #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET 2239 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2240 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2241 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2242 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2243 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2244 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2245 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2246 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2247 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2248 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2249 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2250 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2251 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2252 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2253 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2254 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2255 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2256 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2257 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2258 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2259 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2260 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2261 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2262 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2263 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2264 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2265 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2266 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2267 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2268 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 2269 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 2270 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 2271 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 2272 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 2274 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2275 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2276 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 2277 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 2278 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 2279 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 2280 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 2281 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 2282 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 2283 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 2284 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 2285 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 2286 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 2287 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 2288 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 2289 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 2290 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 2291 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 2292 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 2293 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 2294 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 2295 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 2296 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 2297 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 2298 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 2299 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 2300 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 2301 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 2302 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 2303 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 2304 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 2305 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 2306 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 2307 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 2308 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 2309 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 2310 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 2311 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 2312 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 2313 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 2314 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 2315 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 2316 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 2317 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 2318 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 2319 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 2320 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 2321 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 2322 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 2323 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 2324 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 2325 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 2326 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 2327 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 2328 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 2329 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 2330 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 2331 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 2332 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 2333 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 2334 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 2335 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 2336 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 2337 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 2338 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 2339 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 2340 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 2341 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 2342 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 2343 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 2344 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 2345 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 2346 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 2347 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 2348 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 2349 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 2350 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 2351 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 2352 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 2353 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 2354 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 2355 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 2356 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 2357 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 2358 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 2359 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 2360 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 2361 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 2362 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 2363 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 2364 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 2365 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 2366 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 2367 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 2368 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 2369 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 2370 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2371 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2372 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2373 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2374 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 2375 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 2376 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2377 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2378 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2379 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2380 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 2381 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 2382 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 2383 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 2384 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 2385 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 2386 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 2387 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 2388 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 2389 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 2390 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 2391 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 2392 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 2393 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 2394 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 2395 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 2396 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 2397 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 2398 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2399 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 2400 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 2401 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 2402 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 2403 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 2404 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 2405 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 2406 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 2407 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 2408 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 2409 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 2410 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 2411 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 2412 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 2413 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 2414 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 2415 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 2416 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 2417 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 2418 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 2419 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 2420 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 2421 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 2424 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2425 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2427 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 2428 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 2429 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 2430 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 2431 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 2432 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 2433 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 2434 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 2435 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 2436 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 2437 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 2438 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 2439 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 2440 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 2441 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 2442 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 2443 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 2444 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 2445 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 2446 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 2447 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 2448 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 2450 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 2451 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 2452 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 2453 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 2454 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 2455 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 2456 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 2457 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 2458 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 2459 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 2460 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 2461 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 2462 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 2463 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 2464 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 2465 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 2466 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 2467 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 2468 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 2469 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 2470 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 2471 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 2473 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 2474 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 2475 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 2476 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 2477 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 2478 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 2479 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 2480 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 2481 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 2482 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 2483 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 2484 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 2485 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 2486 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 2487 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 2488 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 2489 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 2490 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 2491 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 2492 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 2493 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 2494 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 2495 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 2496 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 2497 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 2498 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 2499 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 2500 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 2501 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 2502 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 2503 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 2504 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 2505 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 2506 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 2507 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 2508 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 2509 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 2510 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 2511 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 2512 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 2513 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 2514 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 2515 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 2516 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 2517 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 2518 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 2519 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 2520 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 2521 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 2522 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 2523 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 2524 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 2525 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 2526 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 2527 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 2528 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 2529 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 2530 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 2531 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 2532 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 2533 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 2534 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 2535 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 2536 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 2537 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 2538 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 2539 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 2540 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 2541 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 2542 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 2543 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 2544 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 2545 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 2546 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 2547 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 2548 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 2549 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 2550 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 2551 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 2552 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 2553 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 2554 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 2555 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 2556 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 2557 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 2558 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 2559 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 2560 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 2561 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 2562 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 2563 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 2564 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 2565 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 2566 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 2567 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 2568 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 2569 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 2570 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 2571 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 2572 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 2573 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 2574 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 2575 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 2576 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 2577 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 2578 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 2579 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 2580 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 2581 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 2582 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 2583 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 2584 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 2585 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 2586 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 2587 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 2588 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 2590 #if defined(STM32F4) 2591 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 2592 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 2593 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 2594 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 2595 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2596 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2597 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 2598 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 2599 #define Sdmmc1ClockSelection SdioClockSelection 2600 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 2601 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 2602 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 2603 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 2604 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 2607 #if defined(STM32F7) || defined(STM32L4) 2608 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 2609 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 2610 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 2611 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 2612 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 2613 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 2614 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 2615 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 2616 #define SdioClockSelection Sdmmc1ClockSelection 2617 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 2618 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 2619 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 2622 #if defined(STM32F7) 2623 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 2624 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 2627 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 2628 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 2630 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 2632 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 2633 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 2634 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 2635 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 2636 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 2638 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 2640 #if defined(STM32L0) 2641 #define RCC_IT_LSECSS RCC_IT_CSSLSE 2642 #define RCC_IT_CSS RCC_IT_CSSHSE 2645 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 2646 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 2647 #define RCC_MCO_NODIV RCC_MCODIV_1 2648 #define RCC_MCO_DIV1 RCC_MCODIV_1 2649 #define RCC_MCO_DIV2 RCC_MCODIV_2 2650 #define RCC_MCO_DIV4 RCC_MCODIV_4 2651 #define RCC_MCO_DIV8 RCC_MCODIV_8 2652 #define RCC_MCO_DIV16 RCC_MCODIV_16 2653 #define RCC_MCO_DIV32 RCC_MCODIV_32 2654 #define RCC_MCO_DIV64 RCC_MCODIV_64 2655 #define RCC_MCO_DIV128 RCC_MCODIV_128 2656 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 2657 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 2658 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 2659 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 2660 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 2661 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 2662 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 2663 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 2664 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 2665 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 2666 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 2668 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 2670 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 2671 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 2672 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 2673 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 2674 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 2675 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 2676 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 2677 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 2679 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 2680 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 2681 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 2682 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 2683 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 2684 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 2685 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 2686 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 2687 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 2688 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 2689 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 2690 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 2691 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 2692 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 2693 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 2694 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 2695 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 2696 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 2697 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 2698 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 2699 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 2700 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 2701 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 2702 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 2703 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 2704 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 2705 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 2706 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 2707 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 2708 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 2709 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 2710 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 2712 #define CR_HSION_BB RCC_CR_HSION_BB 2713 #define CR_CSSON_BB RCC_CR_CSSON_BB 2714 #define CR_PLLON_BB RCC_CR_PLLON_BB 2715 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 2716 #define CR_MSION_BB RCC_CR_MSION_BB 2717 #define CSR_LSION_BB RCC_CSR_LSION_BB 2718 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 2719 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 2720 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 2721 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 2722 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 2723 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 2724 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 2725 #define CR_HSEON_BB RCC_CR_HSEON_BB 2726 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 2727 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 2728 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 2730 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 2731 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 2732 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 2733 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 2734 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 2736 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 2738 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 2739 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 2741 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 2742 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 2743 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 2744 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 2745 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 2746 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 2748 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 2749 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 2750 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 2751 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 2752 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 2753 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 2754 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 2755 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 2756 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 2757 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 2758 #define DfsdmClockSelection Dfsdm1ClockSelection 2759 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 2760 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK 2761 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 2762 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 2763 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 2772 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 2782 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 2783 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 2784 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 2786 #if defined (STM32F1) 2787 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 2789 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 2791 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 2793 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 2795 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 2797 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 2798 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 2799 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 2800 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 2801 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 2802 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 2803 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 2804 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 2805 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 2806 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 2807 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 2808 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 2809 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 2810 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 2811 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 2814 #define IS_ALARM IS_RTC_ALARM 2815 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 2816 #define IS_TAMPER IS_RTC_TAMPER 2817 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 2818 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 2819 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 2820 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 2821 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 2822 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 2823 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 2824 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 2825 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 2826 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 2827 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 2829 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 2830 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 2840 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 2841 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 2843 #if defined(STM32F4) 2844 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 2845 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 2846 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 2847 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 2848 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 2849 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 2850 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 2851 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 2852 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 2853 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 2854 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 2855 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 2856 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 2857 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 2858 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 2859 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 2860 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 2861 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 2862 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 2863 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 2865 #define SDMMC1_IRQn SDIO_IRQn 2866 #define SDMMC1_IRQHandler SDIO_IRQHandler 2869 #if defined(STM32F7) || defined(STM32L4) 2870 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 2871 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 2872 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 2873 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 2874 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 2875 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 2876 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 2877 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 2878 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 2879 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 2880 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 2881 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 2882 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 2883 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 2884 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 2885 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 2886 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 2887 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 2888 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 2889 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 2891 #define SDIO_IRQn SDMMC1_IRQn 2892 #define SDIO_IRQHandler SDMMC1_IRQHandler 2902 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 2903 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 2904 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 2905 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 2906 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 2907 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 2909 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 2910 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 2912 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 2921 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 2922 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 2923 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 2924 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 2925 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 2926 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 2927 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 2928 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 2937 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 2938 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 2939 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 2949 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 2950 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 2951 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 2952 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 2954 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 2956 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 2957 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 2968 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 2969 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 2970 #define __USART_ENABLE __HAL_USART_ENABLE 2971 #define __USART_DISABLE __HAL_USART_DISABLE 2973 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 2974 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 2983 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 2985 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 2986 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 2987 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 2988 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 2990 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 2991 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 2992 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 2993 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 2995 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 2996 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 2997 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 2998 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 2999 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3000 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3001 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3003 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3004 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3005 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3006 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3007 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3008 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3009 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3010 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3012 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3013 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3014 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3015 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3016 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3017 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3018 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3019 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3021 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3022 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3024 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3025 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3033 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3034 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3036 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3037 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3039 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3041 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3042 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3043 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3044 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3045 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3046 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3047 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3048 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3049 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3050 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3051 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3052 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3054 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3063 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3064 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3065 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3066 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3067 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3068 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3069 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3071 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3072 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3073 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3081 #define __HAL_LTDC_LAYER LTDC_LAYER 3089 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3090 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3091 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3092 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3093 #define SAI_STREOMODE SAI_STEREOMODE 3094 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3095 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3096 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3097 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3098 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3099 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3100 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3101 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3102 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
1.8.13