STM CMSIS
stm32f4xx_hal_cec.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_CEC_H
40 #define __STM32F4xx_HAL_CEC_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if defined(STM32F446xx)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f4xx_hal_def.h"
49 
58 /* Exported types ------------------------------------------------------------*/
66 typedef struct
67 {
68  uint32_t SignalFreeTime;
74  uint32_t Tolerance;
78  uint32_t BRERxStop;
82  uint32_t BREErrorBitGen;
87  uint32_t LBPEErrorBitGen;
92  uint32_t BroadcastMsgNoErrorBitGen;
108  uint32_t SignalFreeTimeOption;
112  uint32_t ListenMode;
122  uint16_t OwnAddress;
125  uint8_t *RxBuffer;
128 }CEC_InitTypeDef;
129 
169 typedef enum
170 {
171  HAL_CEC_STATE_RESET = 0x00U,
173  HAL_CEC_STATE_READY = 0x20U,
175  HAL_CEC_STATE_BUSY = 0x24U,
177  HAL_CEC_STATE_BUSY_RX = 0x22U,
179  HAL_CEC_STATE_BUSY_TX = 0x21U,
181  HAL_CEC_STATE_ERROR = 0x60U
182 }HAL_CEC_StateTypeDef;
183 
187 typedef struct
188 {
189  CEC_TypeDef *Instance;
191  CEC_InitTypeDef Init;
193  uint8_t *pTxBuffPtr;
195  uint16_t TxXferCount;
197  uint16_t RxXferSize;
199  HAL_LockTypeDef Lock;
201  HAL_CEC_StateTypeDef gState;
205  HAL_CEC_StateTypeDef RxState;
208  uint32_t ErrorCode;
210 }CEC_HandleTypeDef;
215 /* Exported constants --------------------------------------------------------*/
223 #define HAL_CEC_ERROR_NONE ((uint32_t)0x00000000U)
224 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
225 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE
226 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
227 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
228 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
229 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
230 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
231 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
232 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
240 #define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
241 #define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
242 #define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
243 #define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
244 #define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
245 #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
246 #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
247 #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
248 
255 #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
256 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
257 
264 #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
265 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
266 
273 #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
274 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
275 
282 #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
283 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
284 
291 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
292 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
293 
300 #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
301 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
302 
309 #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
310 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
311 
318 #define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
319 
326 #define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
327 
334 #define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
335 #define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
336 #define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
337 #define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
338 #define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
339 #define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
340 #define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
341 #define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
342 #define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
343 #define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
344 #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
345 #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
346 #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
347 #define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
348 #define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
349 #define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
350 
357 #define CEC_IT_TXACKE CEC_IER_TXACKEIE
358 #define CEC_IT_TXERR CEC_IER_TXERRIE
359 #define CEC_IT_TXUDR CEC_IER_TXUDRIE
360 #define CEC_IT_TXEND CEC_IER_TXENDIE
361 #define CEC_IT_TXBR CEC_IER_TXBRIE
362 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE
363 #define CEC_IT_RXACKE CEC_IER_RXACKEIE
364 #define CEC_IT_LBPE CEC_IER_LBPEIE
365 #define CEC_IT_SBPE CEC_IER_SBPEIE
366 #define CEC_IT_BRE CEC_IER_BREIE
367 #define CEC_IT_RXOVR CEC_IER_RXOVRIE
368 #define CEC_IT_RXEND CEC_IER_RXENDIE
369 #define CEC_IT_RXBR CEC_IER_RXBRIE
370 
377 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE
378 #define CEC_FLAG_TXERR CEC_ISR_TXERR
379 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR
380 #define CEC_FLAG_TXEND CEC_ISR_TXEND
381 #define CEC_FLAG_TXBR CEC_ISR_TXBR
382 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST
383 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE
384 #define CEC_FLAG_LBPE CEC_ISR_LBPE
385 #define CEC_FLAG_SBPE CEC_ISR_SBPE
386 #define CEC_FLAG_BRE CEC_ISR_BRE
387 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR
388 #define CEC_FLAG_RXEND CEC_ISR_RXEND
389 #define CEC_FLAG_RXBR CEC_ISR_RXBR
390 
397 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
398  CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
399 
406 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
407 
414 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
415 
423 /* Exported macros -----------------------------------------------------------*/
432 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
433  (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
434  (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
435  } while(0)
436 
455 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
456 
476 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
477 
497 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
498 
518 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
519 
539 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
540 
545 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
546 
551 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
552 
557 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
558 
564 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
565 
570 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
571 
576 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
577 
582 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
583 
590 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
591 
596 /* Exported functions --------------------------------------------------------*/
604 /* Initialization and de-initialization functions ****************************/
605 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
606 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
607 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
608 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
609 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
617 /* I/O operation functions ***************************************************/
618 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
619 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
620 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
621 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
622 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
623 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
624 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
632 /* Peripheral State functions ************************************************/
633 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
634 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
643 /* Private types -------------------------------------------------------------*/
652 /* Private variables ---------------------------------------------------------*/
661 /* Private constants ---------------------------------------------------------*/
670 /* Private macros ------------------------------------------------------------*/
675 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
676 
677 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
678  ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
679 
680 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
681  ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
682 
683 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
684  ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
685 
686 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
687  ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
688 
689 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
690  ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
691 
692 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
693  ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
694 
695 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
696  ((__MODE__) == CEC_FULL_LISTENING_MODE))
697 
705 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
706 
712 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
713 
719 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
720 
723 /* Private functions ---------------------------------------------------------*/
739 #endif /* STM32F446xx */
740 
741 #ifdef __cplusplus
742 }
743 #endif
744 
745 #endif /* __STM32F4xx_HAL_CEC_H */
746 
747 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
CEC_TypeDef
Consumer Electronics Control.
Definition: stm32f446xx.h:301
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:68