STM CMSIS
stm32f4xx_hal_dfsdm.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_DFSDM_H
40 #define __STM32F4xx_HAL_DFSDM_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f4xx_hal_def.h"
49 
58 /* Exported types ------------------------------------------------------------*/
66 typedef enum
67 {
68  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U,
69  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U,
70  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU
71 }HAL_DFSDM_Channel_StateTypeDef;
72 
76 typedef struct
77 {
78  FunctionalState Activation;
79  uint32_t Selection;
81  uint32_t Divider;
83 }DFSDM_Channel_OutputClockTypeDef;
84 
88 typedef struct
89 {
90  uint32_t Multiplexer;
92  uint32_t DataPacking;
94  uint32_t Pins;
96 }DFSDM_Channel_InputTypeDef;
97 
101 typedef struct
102 {
103  uint32_t Type;
105  uint32_t SpiClock;
107 }DFSDM_Channel_SerialInterfaceTypeDef;
108 
112 typedef struct
113 {
114  uint32_t FilterOrder;
116  uint32_t Oversampling;
118 }DFSDM_Channel_AwdTypeDef;
119 
123 typedef struct
124 {
125  DFSDM_Channel_OutputClockTypeDef OutputClock;
126  DFSDM_Channel_InputTypeDef Input;
127  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface;
128  DFSDM_Channel_AwdTypeDef Awd;
129  int32_t Offset;
131  uint32_t RightBitShift;
133 }DFSDM_Channel_InitTypeDef;
134 
138 typedef struct
139 {
140  DFSDM_Channel_TypeDef *Instance;
141  DFSDM_Channel_InitTypeDef Init;
142  HAL_DFSDM_Channel_StateTypeDef State;
143 }DFSDM_Channel_HandleTypeDef;
144 
148 typedef enum
149 {
150  HAL_DFSDM_FILTER_STATE_RESET = 0x00U,
151  HAL_DFSDM_FILTER_STATE_READY = 0x01U,
152  HAL_DFSDM_FILTER_STATE_REG = 0x02U,
153  HAL_DFSDM_FILTER_STATE_INJ = 0x03U,
154  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U,
155  HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU
156 }HAL_DFSDM_Filter_StateTypeDef;
157 
161 typedef struct
162 {
163  uint32_t Trigger;
165  FunctionalState FastMode;
166  FunctionalState DmaMode;
167 }DFSDM_Filter_RegularParamTypeDef;
168 
172 typedef struct
173 {
174  uint32_t Trigger;
176  FunctionalState ScanMode;
177  FunctionalState DmaMode;
178  uint32_t ExtTrigger;
180  uint32_t ExtTriggerEdge;
182 }DFSDM_Filter_InjectedParamTypeDef;
183 
187 typedef struct
188 {
189  uint32_t SincOrder;
191  uint32_t Oversampling;
193  uint32_t IntOversampling;
195 }DFSDM_Filter_FilterParamTypeDef;
196 
200 typedef struct
201 {
202  DFSDM_Filter_RegularParamTypeDef RegularParam;
203  DFSDM_Filter_InjectedParamTypeDef InjectedParam;
204  DFSDM_Filter_FilterParamTypeDef FilterParam;
205 }DFSDM_Filter_InitTypeDef;
206 
210 typedef struct
211 {
212  DFSDM_Filter_TypeDef *Instance;
213  DFSDM_Filter_InitTypeDef Init;
214  DMA_HandleTypeDef *hdmaReg;
215  DMA_HandleTypeDef *hdmaInj;
216  uint32_t RegularContMode;
217  uint32_t RegularTrigger;
218  uint32_t InjectedTrigger;
219  uint32_t ExtTriggerEdge;
220  FunctionalState InjectedScanMode;
221  uint32_t InjectedChannelsNbr;
222  uint32_t InjConvRemaining;
223  HAL_DFSDM_Filter_StateTypeDef State;
224  uint32_t ErrorCode;
225 }DFSDM_Filter_HandleTypeDef;
226 
230 typedef struct
231 {
232  uint32_t DataSource;
234  uint32_t Channel;
236  int32_t HighThreshold;
238  int32_t LowThreshold;
240  uint32_t HighBreakSignal;
242  uint32_t LowBreakSignal;
244 }DFSDM_Filter_AwdParamTypeDef;
245 
249 /* End of exported types -----------------------------------------------------*/
250 
251 /* Exported constants --------------------------------------------------------*/
259 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U)
260 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC
268 #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U)
269 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1
277 #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U)
278 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
279 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1
287 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U)
288 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL
296 #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U)
297 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
298 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
299 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP
307 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U)
308 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
309 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
310 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL
318 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U)
319 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
320 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
321 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD
329 #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U)
330 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U)
331 #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U)
339 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U)
340 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0
341 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
342 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
343 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2
344 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
345 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)
346 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL
354 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
355 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
356 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN
364 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)
365 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
366 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
367 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
368 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
369 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)
377 #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U)
378 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL
386 #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U)
387 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U)
388 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U)
389 #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U)
397 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U)
398 #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U)
399 #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U)
400 #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U)
401 #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U)
409 /* DFSDM Channels ------------------------------------------------------------*/
410 /* The DFSDM channels are defined as follows:
411  - in 16-bit LSB the channel mask is set
412  - in 16-bit MSB the channel number is set
413  e.g. for channel 3 definition:
414  - the channel mask is 0x00000008U (bit 3 is set)
415  - the channel number 3 is 0x00030000
416  --> Consequently, channel 3 definition is 0x00000008U | 0x00030000 = 0x00030008 */
417 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
418 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
419 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
420 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
421 
428 #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U)
429 #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U)
437 #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U)
438 #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U)
446 /* End of exported constants -------------------------------------------------*/
447 
448 /* Exported macros -----------------------------------------------------------*/
457 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
458 
463 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
464 
468 /* End of exported macros ----------------------------------------------------*/
469 
470 /* Exported functions --------------------------------------------------------*/
478 /* Channel initialization and de-initialization functions *********************/
479 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
480 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
481 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
482 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
490 /* Channel operation functions ************************************************/
491 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
492 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
493 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
494 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
495 
496 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
497 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
498 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
499 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
500 
501 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
502 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
503 
504 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
505 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
506 
507 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
508 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
516 /* Channel state function *****************************************************/
517 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
525 /* Filter initialization and de-initialization functions *********************/
526 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
527 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
528 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
529 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
537 /* Filter control functions *********************/
538 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
539  uint32_t Channel,
540  uint32_t ContinuousMode);
541 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
542  uint32_t Channel);
550 /* Filter operation functions *********************/
551 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
552 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
553 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
554 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
555 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
556 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
557 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
558 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
559 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
560 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
561 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
562 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
563 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
564 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
565 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
566  DFSDM_Filter_AwdParamTypeDef* awdParam);
567 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
568 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
569 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
570 
571 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
572 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
573 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
574 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
575 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
576 
577 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
578 
579 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
580 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
581 
582 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
583 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
584 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
585 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
586 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
587 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
595 /* Filter state functions *****************************************************/
596 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
597 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
605 /* End of exported functions -------------------------------------------------*/
606 
607 /* Private macros ------------------------------------------------------------*/
611 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
612  ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
613 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
614 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
615  ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
616 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
617  ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
618  ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
619 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
620  ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
621 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
622  ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
623  ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
624  ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
625 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
626  ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
627  ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
628  ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
629 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
630  ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
631  ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
632  ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
633 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
634 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
635 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
636 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
637 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
638  ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
639 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
640  ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
641  ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
642 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
643  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
644  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
645  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
646  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
647  ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
648  ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
649  ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
650 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
651  ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
652  ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
653 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
654  ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
655  ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
656  ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
657  ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
658  ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
659 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
660 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
661 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
662  ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
663 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
664 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU)
665 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
666  ((CHANNEL) == DFSDM_CHANNEL_1) || \
667  ((CHANNEL) == DFSDM_CHANNEL_2) || \
668  ((CHANNEL) == DFSDM_CHANNEL_3))
669 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
670 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
671  ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
672 
675 /* End of private macros -----------------------------------------------------*/
676 
684 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
685 #ifdef __cplusplus
686 }
687 #endif
688 
689 #endif /* __STM32F4xx_HAL_DFSDM_H */
690 
691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32f412cx.h:299
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32f412cx.h:321
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:157