STM CMSIS
stm32f4xx_hal_dma2d.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_DMA2D_H
40 #define __STM32F4xx_HAL_DMA2D_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
47  defined(STM32F469xx) || defined(STM32F479xx)
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f4xx_hal_def.h"
50 
60 /* Exported types ------------------------------------------------------------*/
64 #define MAX_DMA2D_LAYER 2U
65 
69 typedef struct
70 {
71  uint32_t Blue;
74  uint32_t Green;
77  uint32_t Red;
79 } DMA2D_ColorTypeDef;
80 
84 typedef struct
85 {
86  uint32_t *pCLUT;
88  uint32_t CLUTColorMode;
91  uint32_t Size;
93 } DMA2D_CLUTCfgTypeDef;
94 
98 typedef struct
99 {
100  uint32_t Mode;
103  uint32_t ColorMode;
106  uint32_t OutputOffset;
109 } DMA2D_InitTypeDef;
110 
114 typedef struct
115 {
116  uint32_t InputOffset;
119  uint32_t InputColorMode;
122  uint32_t AlphaMode;
125  uint32_t InputAlpha;
134 } DMA2D_LayerCfgTypeDef;
135 
139 typedef enum
140 {
141  HAL_DMA2D_STATE_RESET = 0x00U,
142  HAL_DMA2D_STATE_READY = 0x01U,
143  HAL_DMA2D_STATE_BUSY = 0x02U,
144  HAL_DMA2D_STATE_TIMEOUT = 0x03U,
145  HAL_DMA2D_STATE_ERROR = 0x04U,
146  HAL_DMA2D_STATE_SUSPEND = 0x05U
147 }HAL_DMA2D_StateTypeDef;
148 
152 typedef struct __DMA2D_HandleTypeDef
153 {
154  DMA2D_TypeDef *Instance;
156  DMA2D_InitTypeDef Init;
158  void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);
160  void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d);
162  DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER];
164  HAL_LockTypeDef Lock;
166  __IO HAL_DMA2D_StateTypeDef State;
168  __IO uint32_t ErrorCode;
169 } DMA2D_HandleTypeDef;
174 /* Exported constants --------------------------------------------------------*/
182 #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U)
183 #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U)
184 #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U)
185 #define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U)
186 #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U)
194 #define DMA2D_M2M ((uint32_t)0x00000000U)
195 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0
196 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1
197 #define DMA2D_R2M DMA2D_CR_MODE
205 #define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U)
206 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
207 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
208 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
209 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2
217 #define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U)
218 #define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U)
219 #define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U)
220 #define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U)
221 #define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U)
222 #define DMA2D_INPUT_L8 ((uint32_t)0x00000005U)
223 #define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U)
224 #define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U)
225 #define DMA2D_INPUT_L4 ((uint32_t)0x00000008U)
226 #define DMA2D_INPUT_A8 ((uint32_t)0x00000009U)
227 #define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU)
235 #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U)
236 #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U)
237 #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U)
246 #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U)
247 #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U)
255 #define DMA2D_IT_CE DMA2D_CR_CEIE
256 #define DMA2D_IT_CTC DMA2D_CR_CTCIE
257 #define DMA2D_IT_CAE DMA2D_CR_CAEIE
258 #define DMA2D_IT_TW DMA2D_CR_TWIE
259 #define DMA2D_IT_TC DMA2D_CR_TCIE
260 #define DMA2D_IT_TE DMA2D_CR_TEIE
268 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF
269 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
270 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
271 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF
272 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF
273 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF
281 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort
289 /* Exported macros ------------------------------------------------------------*/
290 
298 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
299 
305 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
306 
307 /* Interrupt & Flag management */
321 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
322 
336 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
337 
351 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
352 
366 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
367 
381 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
382 
387 /* Exported functions --------------------------------------------------------*/
396 /* Initialization and de-initialization functions *******************************/
397 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
398 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
399 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
400 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
401 
410 /* IO operation functions *******************************************************/
411 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
412 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
413 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
414 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
415 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
416 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
417 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
418 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
419 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
420 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
421 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
422 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
423 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
424 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
425 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
426 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
427 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
428 
437 /* Peripheral Control functions *************************************************/
438 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
439 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
440 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
441 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
442 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
443 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
444 
453 /* Peripheral State functions ***************************************************/
454 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
455 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
456 
465 /* Private constants ---------------------------------------------------------*/
466 
474 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW
482 #define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU)
490 #define DMA2D_MAX_LAYER 2U
498 #define DMA2D_OFFSET DMA2D_FGOR_LO
506 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
507 #define DMA2D_LINE DMA2D_NLR_NL
515 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U)
524 /* Private macros ------------------------------------------------------------*/
525 
528 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
529 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
530  ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
531 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
532  ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
533  ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
534 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
535 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
536 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
537 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
538 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
539  ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
540  ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
541  ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
542  ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
543  ((INPUT_CM) == DMA2D_INPUT_A4))
544 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
545  ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
546  ((AlphaMode) == DMA2D_COMBINE_ALPHA))
547 
548 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
549 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
550 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
551 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
552  ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
553  ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
554 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
555  ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
556  ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
557 
569 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
570 
571 #ifdef __cplusplus
572 }
573 #endif
574 
575 #endif /* __STM32F4xx_HAL_DMA2D_H */
576 
577 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f427xx.h:391
__IO
#define __IO
Definition: core_cm0.h:213
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:68