STM CMSIS
stm32f4xx_hal_eth.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_ETH_H
40 #define __STM32F4xx_HAL_ETH_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
47  defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f4xx_hal_def.h"
50 
62 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
63 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
64  ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
65 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
66  ((SPEED) == ETH_SPEED_100M))
67 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
68  ((MODE) == ETH_MODE_HALFDUPLEX))
69 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
70  ((MODE) == ETH_RXINTERRUPT_MODE))
71 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
72  ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
73 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
74  ((MODE) == ETH_MEDIA_INTERFACE_RMII))
75 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
76  ((CMD) == ETH_WATCHDOG_DISABLE))
77 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
78  ((CMD) == ETH_JABBER_DISABLE))
79 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
80  ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
81  ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
82  ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
83  ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
84  ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
85  ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
86  ((GAP) == ETH_INTERFRAMEGAP_40BIT))
87 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
88  ((CMD) == ETH_CARRIERSENCE_DISABLE))
89 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
90  ((CMD) == ETH_RECEIVEOWN_DISABLE))
91 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
92  ((CMD) == ETH_LOOPBACKMODE_DISABLE))
93 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
94  ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
95 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
96  ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
97 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
98  ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
99 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
100  ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
101  ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
102  ((LIMIT) == ETH_BACKOFFLIMIT_1))
103 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
104  ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
105 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
106  ((CMD) == ETH_RECEIVEAll_DISABLE))
107 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
108  ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
109  ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
110 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
111  ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
112  ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
113 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
114  ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
115 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
116  ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
117 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
118  ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
119 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
120  ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
121  ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
122  ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
123 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
124  ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
125  ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
126 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
127 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
128  ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
129 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
130  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
131  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
132  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
133 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
134  ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
135 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
136  ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
137 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
138  ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
139 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
140  ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
141 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
142 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
143  ((ADDRESS) == ETH_MAC_ADDRESS1) || \
144  ((ADDRESS) == ETH_MAC_ADDRESS2) || \
145  ((ADDRESS) == ETH_MAC_ADDRESS3))
146 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
147  ((ADDRESS) == ETH_MAC_ADDRESS2) || \
148  ((ADDRESS) == ETH_MAC_ADDRESS3))
149 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
150  ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
151 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
152  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
153  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
154  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
155  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
156  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
157 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
158  ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
159 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
160  ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
161 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
162  ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
163 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
164  ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
165 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
166  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
167  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
168  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
169  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
170  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
171  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
172  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
173 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
174  ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
175 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
176  ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
177 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
178  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
179  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
180  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
181 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
182  ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
183 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
184  ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
185 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
186  ((CMD) == ETH_FIXEDBURST_DISABLE))
187 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
188  ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
189  ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
190  ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
191  ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
192  ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
193  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
194  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
195  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
196  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
197  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
198  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
199 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
200  ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
201  ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
202  ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
203  ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
204  ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
205  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
206  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
207  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
208  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
209  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
210  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
211 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
212 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
213  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
214  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
215  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
216  ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
217 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
218  ((FLAG) == ETH_DMATXDESC_IC) || \
219  ((FLAG) == ETH_DMATXDESC_LS) || \
220  ((FLAG) == ETH_DMATXDESC_FS) || \
221  ((FLAG) == ETH_DMATXDESC_DC) || \
222  ((FLAG) == ETH_DMATXDESC_DP) || \
223  ((FLAG) == ETH_DMATXDESC_TTSE) || \
224  ((FLAG) == ETH_DMATXDESC_TER) || \
225  ((FLAG) == ETH_DMATXDESC_TCH) || \
226  ((FLAG) == ETH_DMATXDESC_TTSS) || \
227  ((FLAG) == ETH_DMATXDESC_IHE) || \
228  ((FLAG) == ETH_DMATXDESC_ES) || \
229  ((FLAG) == ETH_DMATXDESC_JT) || \
230  ((FLAG) == ETH_DMATXDESC_FF) || \
231  ((FLAG) == ETH_DMATXDESC_PCE) || \
232  ((FLAG) == ETH_DMATXDESC_LCA) || \
233  ((FLAG) == ETH_DMATXDESC_NC) || \
234  ((FLAG) == ETH_DMATXDESC_LCO) || \
235  ((FLAG) == ETH_DMATXDESC_EC) || \
236  ((FLAG) == ETH_DMATXDESC_VF) || \
237  ((FLAG) == ETH_DMATXDESC_CC) || \
238  ((FLAG) == ETH_DMATXDESC_ED) || \
239  ((FLAG) == ETH_DMATXDESC_UF) || \
240  ((FLAG) == ETH_DMATXDESC_DB))
241 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
242  ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
243 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
244  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
245  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
246  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
247 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
248 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
249  ((FLAG) == ETH_DMARXDESC_AFM) || \
250  ((FLAG) == ETH_DMARXDESC_ES) || \
251  ((FLAG) == ETH_DMARXDESC_DE) || \
252  ((FLAG) == ETH_DMARXDESC_SAF) || \
253  ((FLAG) == ETH_DMARXDESC_LE) || \
254  ((FLAG) == ETH_DMARXDESC_OE) || \
255  ((FLAG) == ETH_DMARXDESC_VLAN) || \
256  ((FLAG) == ETH_DMARXDESC_FS) || \
257  ((FLAG) == ETH_DMARXDESC_LS) || \
258  ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
259  ((FLAG) == ETH_DMARXDESC_LC) || \
260  ((FLAG) == ETH_DMARXDESC_FT) || \
261  ((FLAG) == ETH_DMARXDESC_RWT) || \
262  ((FLAG) == ETH_DMARXDESC_RE) || \
263  ((FLAG) == ETH_DMARXDESC_DBE) || \
264  ((FLAG) == ETH_DMARXDESC_CE) || \
265  ((FLAG) == ETH_DMARXDESC_MAMPCE))
266 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
267  ((BUFFER) == ETH_DMARXDESC_BUFFER2))
268 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
269  ((FLAG) == ETH_PMT_FLAG_MPR))
270 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
271 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
272  ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
273  ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
274  ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
275  ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
276  ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
277  ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
278  ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
279  ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
280  ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
281  ((FLAG) == ETH_DMA_FLAG_T))
282 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
283 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
284  ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
285  ((IT) == ETH_MAC_IT_PMT))
286 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
287  ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
288  ((FLAG) == ETH_MAC_FLAG_PMT))
289 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
290 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
291  ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
292  ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
293  ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
294  ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
295  ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
296  ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
297  ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
298  ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
299 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
300  ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
301 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFFU) == 0x00U) || (((IT) & (uint32_t)0xEFFDFF9FU) == 0x00U)) && \
302  ((IT) != 0x00U))
303 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
304  ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
305  ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
306 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
307  ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
308 
316 /* Delay to wait when writing to some Ethernet registers */
317 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)
318 
319 /* ETHERNET Errors */
320 #define ETH_SUCCESS ((uint32_t)0U)
321 #define ETH_ERROR ((uint32_t)1U)
322 
323 /* ETHERNET DMA Tx descriptors Collision Count Shift */
324 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U)
325 
326 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
327 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)
328 
329 /* ETHERNET DMA Rx descriptors Frame Length Shift */
330 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U)
331 
332 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
333 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)
334 
335 /* ETHERNET DMA Rx descriptors Frame length Shift */
336 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16U)
337 
338 /* ETHERNET MAC address offsets */
339 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* ETHERNET MAC address high offset */
340 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* ETHERNET MAC address low offset */
341 
342 /* ETHERNET MACMIIAR register Mask */
343 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U)
344 
345 /* ETHERNET MACCR register Mask */
346 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU)
347 
348 /* ETHERNET MACFCR register Mask */
349 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U)
350 
351 /* ETHERNET DMAOMR register Mask */
352 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U)
353 
354 /* ETHERNET Remote Wake-up frame register length */
355 #define ETH_WAKEUP_REGISTER_LENGTH 8
356 
357 /* ETHERNET Missed frames counter Shift */
358 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
359 
363 /* Exported types ------------------------------------------------------------*/
371 typedef enum
372 {
373  HAL_ETH_STATE_RESET = 0x00U,
374  HAL_ETH_STATE_READY = 0x01U,
375  HAL_ETH_STATE_BUSY = 0x02U,
376  HAL_ETH_STATE_BUSY_TX = 0x12U,
377  HAL_ETH_STATE_BUSY_RX = 0x22U,
378  HAL_ETH_STATE_BUSY_TX_RX = 0x32U,
379  HAL_ETH_STATE_BUSY_WR = 0x42U,
380  HAL_ETH_STATE_BUSY_RD = 0x82U,
381  HAL_ETH_STATE_TIMEOUT = 0x03U,
382  HAL_ETH_STATE_ERROR = 0x04U
383 }HAL_ETH_StateTypeDef;
384 
389 typedef struct
390 {
391  uint32_t AutoNegotiation;
396  uint32_t Speed;
399  uint32_t DuplexMode;
402  uint16_t PhyAddress;
405  uint8_t *MACAddr;
407  uint32_t RxMode;
410  uint32_t ChecksumMode;
413  uint32_t MediaInterface;
416 } ETH_InitTypeDef;
417 
418 
423 typedef struct
424 {
425  uint32_t Watchdog;
430  uint32_t Jabber;
435  uint32_t InterFrameGap;
438  uint32_t CarrierSense;
441  uint32_t ReceiveOwn;
446  uint32_t LoopbackMode;
449  uint32_t ChecksumOffload;
452  uint32_t RetryTransmission;
456  uint32_t AutomaticPadCRCStrip;
459  uint32_t BackOffLimit;
462  uint32_t DeferralCheck;
465  uint32_t ReceiveAll;
468  uint32_t SourceAddrFilter;
471  uint32_t PassControlFrames;
474  uint32_t BroadcastFramesReception;
477  uint32_t DestinationAddrFilter;
480  uint32_t PromiscuousMode;
483  uint32_t MulticastFramesFilter;
486  uint32_t UnicastFramesFilter;
489  uint32_t HashTableHigh;
492  uint32_t HashTableLow;
495  uint32_t PauseTime;
498  uint32_t ZeroQuantaPause;
501  uint32_t PauseLowThreshold;
505  uint32_t UnicastPauseFrameDetect;
509  uint32_t ReceiveFlowControl;
513  uint32_t TransmitFlowControl;
517  uint32_t VLANTagComparison;
521  uint32_t VLANTagIdentifier;
523 } ETH_MACInitTypeDef;
524 
529 typedef struct
530 {
531  uint32_t DropTCPIPChecksumErrorFrame;
534  uint32_t ReceiveStoreForward;
537  uint32_t FlushReceivedFrame;
540  uint32_t TransmitStoreForward;
543  uint32_t TransmitThresholdControl;
546  uint32_t ForwardErrorFrames;
549  uint32_t ForwardUndersizedGoodFrames;
553  uint32_t ReceiveThresholdControl;
556  uint32_t SecondFrameOperate;
560  uint32_t AddressAlignedBeats;
563  uint32_t FixedBurst;
566  uint32_t RxDMABurstLength;
569  uint32_t TxDMABurstLength;
572  uint32_t EnhancedDescriptorFormat;
575  uint32_t DescriptorSkipLength;
578  uint32_t DMAArbitration;
580 } ETH_DMAInitTypeDef;
581 
582 
587 typedef struct
588 {
589  __IO uint32_t Status;
591  uint32_t ControlBufferSize;
593  uint32_t Buffer1Addr;
595  uint32_t Buffer2NextDescAddr;
598  uint32_t ExtendedStatus;
600  uint32_t Reserved1;
602  uint32_t TimeStampLow;
604  uint32_t TimeStampHigh;
606 } ETH_DMADescTypeDef;
607 
611 typedef struct
612 {
613  ETH_DMADescTypeDef *FSRxDesc;
615  ETH_DMADescTypeDef *LSRxDesc;
617  uint32_t SegCount;
619  uint32_t length;
621  uint32_t buffer;
623 } ETH_DMARxFrameInfos;
624 
629 typedef struct
630 {
631  ETH_TypeDef *Instance;
633  ETH_InitTypeDef Init;
635  uint32_t LinkStatus;
637  ETH_DMADescTypeDef *RxDesc;
639  ETH_DMADescTypeDef *TxDesc;
641  ETH_DMARxFrameInfos RxFrameInfos;
643  __IO HAL_ETH_StateTypeDef State;
645  HAL_LockTypeDef Lock;
647 } ETH_HandleTypeDef;
648 
653 /* Exported constants --------------------------------------------------------*/
661 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524U)
662 #define ETH_HEADER ((uint32_t)14U)
663 #define ETH_CRC ((uint32_t)4U)
664 #define ETH_EXTRA ((uint32_t)2U)
665 #define ETH_VLAN_TAG ((uint32_t)4U)
666 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U)
667 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U)
668 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U)
670  /* Ethernet driver receive buffers are organized in a chained linked-list, when
671  an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
672  to the driver receive buffers memory.
673 
674  Depending on the size of the received ethernet packet and the size of
675  each ethernet driver receive buffer, the received packet can take one or more
676  ethernet driver receive buffer.
677 
678  In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
679  and the total count of the driver receive buffers ETH_RXBUFNB.
680 
681  The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
682  example, they can be reconfigured in the application layer to fit the application
683  needs */
684 
685 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
686  packet */
687 #ifndef ETH_RX_BUF_SIZE
688  #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
689 #endif
690 
691 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
692 #ifndef ETH_RXBUFNB
693  #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
694 #endif
695 
696 
697  /* Ethernet driver transmit buffers are organized in a chained linked-list, when
698  an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
699  driver transmit buffers memory to the TxFIFO.
700 
701  Depending on the size of the Ethernet packet to be transmitted and the size of
702  each ethernet driver transmit buffer, the packet to be transmitted can take
703  one or more ethernet driver transmit buffer.
704 
705  In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
706  and the total count of the driver transmit buffers ETH_TXBUFNB.
707 
708  The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
709  example, they can be reconfigured in the application layer to fit the application
710  needs */
711 
712 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
713  packet */
714 #ifndef ETH_TX_BUF_SIZE
715  #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
716 #endif
717 
718 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
719 #ifndef ETH_TXBUFNB
720  #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
721 #endif
722 
731 /*
732  DMA Tx Descriptor
733  -----------------------------------------------------------------------------------------------
734  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
735  -----------------------------------------------------------------------------------------------
736  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
737  -----------------------------------------------------------------------------------------------
738  TDES2 | Buffer1 Address [31:0] |
739  -----------------------------------------------------------------------------------------------
740  TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
741  -----------------------------------------------------------------------------------------------
742 */
743 
747 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U)
748 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000U)
749 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000U)
750 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000U)
751 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000U)
752 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000U)
753 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U)
754 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U)
755 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U)
756 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U)
757 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U)
758 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U)
759 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000U)
760 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U)
761 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U)
762 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U)
763 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000U)
764 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000U)
765 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000U)
766 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U)
767 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U)
768 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400U)
769 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U)
770 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100U)
771 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080U)
772 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078U)
773 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004U)
774 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002U)
775 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001U)
780 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U)
781 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU)
786 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU)
791 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU)
793  /*---------------------------------------------------------------------------------------------
794  TDES6 | Transmit Time Stamp Low [31:0] |
795  -----------------------------------------------------------------------------------------------
796  TDES7 | Transmit Time Stamp High [31:0] |
797  ----------------------------------------------------------------------------------------------*/
798 
799 /* Bit definition of TDES6 register */
800  #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */
801 
802 /* Bit definition of TDES7 register */
803  #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */
804 
812 /*
813  DMA Rx Descriptor
814  --------------------------------------------------------------------------------------------------------------------
815  RDES0 | OWN(31) | Status [30:0] |
816  ---------------------------------------------------------------------------------------------------------------------
817  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
818  ---------------------------------------------------------------------------------------------------------------------
819  RDES2 | Buffer1 Address [31:0] |
820  ---------------------------------------------------------------------------------------------------------------------
821  RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
822  ---------------------------------------------------------------------------------------------------------------------
823 */
824 
828 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U)
829 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U)
830 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U)
831 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000U)
832 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000U)
833 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U)
834 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000U)
835 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800U)
836 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U)
837 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200U)
838 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100U)
839 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U)
840 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040U)
841 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020U)
842 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U)
843 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008U)
844 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U)
845 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002U)
846 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U)
851 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U)
852 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U)
853 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000U)
854 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U)
855 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU)
860 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU)
865 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU)
867 /*---------------------------------------------------------------------------------------------------------------------
868  RDES4 | Reserved[31:15] | Extended Status [14:0] |
869  ---------------------------------------------------------------------------------------------------------------------
870  RDES5 | Reserved[31:0] |
871  ---------------------------------------------------------------------------------------------------------------------
872  RDES6 | Receive Time Stamp Low [31:0] |
873  ---------------------------------------------------------------------------------------------------------------------
874  RDES7 | Receive Time Stamp High [31:0] |
875  --------------------------------------------------------------------------------------------------------------------*/
876 
877 /* Bit definition of RDES4 register */
878 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */
879 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */
880 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */
881  #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */
882  #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */
883  #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */
884  #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */
885  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
886  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
887  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
888 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */
889 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */
890 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */
891 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */
892 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */
893 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */
894  #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */
895  #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */
896  #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */
897 
898 /* Bit definition of RDES6 register */
899 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */
900 
901 /* Bit definition of RDES7 register */
902 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */
903 
909 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U)
910 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U)
911 
918 #define ETH_SPEED_10M ((uint32_t)0x00000000U)
919 #define ETH_SPEED_100M ((uint32_t)0x00004000U)
920 
927 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U)
928 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U)
929 
935 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U)
936 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U)
937 
944 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U)
945 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U)
946 
953 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U)
954 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
955 
962 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U)
963 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U)
964 
971 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000U)
972 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000U)
973 
980 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U)
981 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U)
982 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U)
983 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U)
984 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U)
985 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U)
986 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U)
987 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U)
995 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U)
996 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U)
997 
1004 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)
1005 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U)
1006 
1013 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U)
1014 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)
1015 
1022 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U)
1023 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U)
1024 
1031 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)
1032 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U)
1033 
1040 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U)
1041 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U)
1042 
1049 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U)
1050 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U)
1051 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U)
1052 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U)
1053 
1060 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U)
1061 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U)
1062 
1069 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U)
1070 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U)
1071 
1078 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U)
1079 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U)
1080 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U)
1081 
1088 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U)
1089 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U)
1090 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U)
1098 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U)
1099 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U)
1100 
1107 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U)
1108 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U)
1109 
1116 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U)
1117 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U)
1118 
1125 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U)
1126 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U)
1127 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)
1128 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U)
1129 
1136 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)
1137 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U)
1138 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)
1139 
1146 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U)
1147 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U)
1148 
1155 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U)
1156 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U)
1157 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U)
1158 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U)
1166 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U)
1167 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)
1168 
1175 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U)
1176 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
1177 
1184 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U)
1185 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
1186 
1193 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U)
1194 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
1195 
1202 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
1203 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
1204 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
1205 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
1206 
1213 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U)
1214 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U)
1215 
1222 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U)
1223 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U)
1224 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U)
1225 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U)
1226 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U)
1227 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U)
1235 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U)
1236 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U)
1237 
1244 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U)
1245 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U)
1246 
1253 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U)
1254 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U)
1255 
1262 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U)
1263 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U)
1264 
1271 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U)
1272 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U)
1273 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U)
1274 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U)
1275 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U)
1276 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U)
1277 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U)
1278 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U)
1286 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U)
1287 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U)
1288 
1295 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U)
1296 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U)
1297 
1304 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U)
1305 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U)
1306 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U)
1307 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U)
1315 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U)
1316 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U)
1317 
1324 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U)
1325 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U)
1326 
1333 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U)
1334 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U)
1335 
1342 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U)
1343 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U)
1344 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U)
1345 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U)
1346 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U)
1347 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U)
1348 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U)
1349 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U)
1350 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U)
1351 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U)
1352 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U)
1353 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U)
1361 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U)
1362 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U)
1363 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U)
1364 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U)
1365 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U)
1366 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U)
1367 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U)
1368 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U)
1369 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U)
1370 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U)
1371 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U)
1372 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U)
1380 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U)
1381 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U)
1382 
1389 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U)
1390 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U)
1391 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U)
1392 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U)
1393 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U)
1394 
1401 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U)
1402 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U)
1410 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U)
1411 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U)
1412 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U)
1413 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U)
1421 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U)
1422 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U)
1430 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U)
1431 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U)
1432 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U)
1440 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000U)
1441 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U)
1442 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U)
1450 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U)
1451 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U)
1452 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U)
1460 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U)
1461 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U)
1462 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U)
1463 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U)
1464 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U)
1472 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U)
1473 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U)
1474 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U)
1475 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U)
1476 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U)
1477 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U)
1478 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U)
1479 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U)
1480 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U)
1481 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U)
1482 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U)
1483 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U)
1484 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U)
1485 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U)
1486 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040U)
1487 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U)
1488 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U)
1489 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U)
1490 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U)
1491 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U)
1492 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001U)
1500 #define ETH_MAC_IT_TST ((uint32_t)0x00000200U)
1501 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U)
1502 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U)
1503 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010U)
1504 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008U)
1512 #define ETH_DMA_IT_TST ((uint32_t)0x20000000U)
1513 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000U)
1514 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000U)
1515 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000U)
1516 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000U)
1517 #define ETH_DMA_IT_ER ((uint32_t)0x00004000U)
1518 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000U)
1519 #define ETH_DMA_IT_ET ((uint32_t)0x00000400U)
1520 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200U)
1521 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100U)
1522 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080U)
1523 #define ETH_DMA_IT_R ((uint32_t)0x00000040U)
1524 #define ETH_DMA_IT_TU ((uint32_t)0x00000020U)
1525 #define ETH_DMA_IT_RO ((uint32_t)0x00000010U)
1526 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008U)
1527 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004U)
1528 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002U)
1529 #define ETH_DMA_IT_T ((uint32_t)0x00000001U)
1537 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U)
1538 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U)
1539 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U)
1540 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U)
1541 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U)
1542 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U)
1552 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U)
1553 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U)
1554 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U)
1555 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U)
1556 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U)
1557 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U)
1566 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U)
1567 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U)
1575 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U)
1585 /* Exported macro ------------------------------------------------------------*/
1586 
1595 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1596 
1603 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1604 
1611 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1612 
1618 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1619 
1625 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1626 
1632 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1633 
1639 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1640 
1646 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1647 
1653 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1654 
1660 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1661 
1673 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1674 
1680 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1681 
1687 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1688 
1694 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1695 
1701 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1702 
1713 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1714 
1725 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1726 
1732 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1733 
1739 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1740 
1746 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1747 
1753 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1754 
1767 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1768 
1776 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1777 
1785 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1786 
1793 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1794 
1801 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1802 
1809 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1810 
1820 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1821 
1828 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1829 
1836 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1837 
1844 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1845 
1851 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1852 
1858 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1859 
1865 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1866 
1872 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1873 
1879 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1880 
1886 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1887 
1898 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1899 
1905 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1906 
1912 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1913  (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
1914 
1920 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1921 
1927 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1928 
1934 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1935 
1941 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1942 
1948 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1949 
1955 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1956 
1962 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
1963 
1974 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
1975 
1985 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
1986 
1996 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
1997 
2008 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
2009 
2014 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
2015 
2020 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
2021 
2026 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
2027 
2032 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
2033 
2038 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
2039 
2044 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
2045 
2050 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2051 
2056 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2057 
2062 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
2063 
2068 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2069 
2074 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2075  EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
2076  }while(0)
2077 
2082 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2083  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2084  }while(0)
2085 
2090 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2091 
2095 /* Exported functions --------------------------------------------------------*/
2096 
2101 /* Initialization and de-initialization functions ****************************/
2102 
2106 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2107 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2108 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2109 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2110 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2111 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2112 
2116 /* IO operation functions ****************************************************/
2117 
2121 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2122 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2123 /* Communication with PHY functions*/
2124 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2125 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2126 /* Non-Blocking mode: Interrupt */
2127 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2128 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2129 /* Callback in non blocking modes (Interrupt) */
2130 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2131 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2132 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2137 /* Peripheral Control functions **********************************************/
2138 
2143 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2144 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2145 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2146 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2151 /* Peripheral State functions ************************************************/
2152 
2156 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2173 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
2174  STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
2175 
2176 #ifdef __cplusplus
2177 }
2178 #endif
2179 
2180 #endif /* __STM32F4xx_HAL_ETH_H */
2181 
2182 
2183 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
__IO
#define __IO
Definition: core_cm0.h:213
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:386
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:68