39 #ifndef __STM32F4xx_HAL_NOR_H 40 #define __STM32F4xx_HAL_NOR_H 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ 52 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 53 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 65 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 66 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 67 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 80 HAL_NOR_STATE_RESET = 0x00U,
81 HAL_NOR_STATE_READY = 0x01U,
82 HAL_NOR_STATE_BUSY = 0x02U,
83 HAL_NOR_STATE_ERROR = 0x03U,
84 HAL_NOR_STATE_PROTECTED = 0x04U
85 }HAL_NOR_StateTypeDef;
92 HAL_NOR_STATUS_SUCCESS = 0U,
93 HAL_NOR_STATUS_ONGOING,
95 HAL_NOR_STATUS_TIMEOUT
96 }HAL_NOR_StatusTypeDef;
103 uint16_t Manufacturer_Code;
105 uint16_t Device_Code1;
107 uint16_t Device_Code2;
109 uint16_t Device_Code3;
138 FMC_NORSRAM_TypeDef *Instance;
140 FMC_NORSRAM_EXTENDED_TypeDef *Extended;
142 FMC_NORSRAM_InitTypeDef Init;
146 __IO HAL_NOR_StateTypeDef State;
162 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) 176 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
178 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
179 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
180 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
189 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
191 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
192 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
194 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
195 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
197 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
199 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
218 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
219 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
235 #define MC_ADDRESS ((uint16_t)0x0000U) 236 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) 237 #define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) 238 #define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) 241 #define CFI1_ADDRESS ((uint16_t)0x0061U) 242 #define CFI2_ADDRESS ((uint16_t)0x0062U) 243 #define CFI3_ADDRESS ((uint16_t)0x0063U) 244 #define CFI4_ADDRESS ((uint16_t)0x0064U) 247 #define NOR_TMEOUT ((uint16_t)0xFFFFU) 250 #define NOR_MEMORY_8B ((uint8_t)0x00U) 251 #define NOR_MEMORY_16B ((uint8_t)0x01U) 254 #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) 255 #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) 256 #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) 257 #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) 273 #define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\ 274 ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS)))) 282 #define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA)) HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
Header file of FSMC HAL module.
#define __IO
Definition: core_cm0.h:213
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:68
Header file of FMC HAL module.