STM CMSIS
stm32f4xx_hal_qspi.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_QSPI_H
40 #define __STM32F4xx_HAL_QSPI_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
47  defined(STM32F412Rx)
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f4xx_hal_def.h"
50 
59 /* Exported types ------------------------------------------------------------*/
68 typedef struct
69 {
70  uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
71  This parameter can be a number between 0 and 255 */
72 
73  uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
74  This parameter can be a value between 1 and 32 */
75 
76  uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
77  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
78  This parameter can be a value of @ref QSPI_SampleShifting */
79 
80  uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
81  required to address the flash memory. The flash capacity can be up to 4GB
82  (addressed using 32 bits) in indirect mode, but the addressable space in
83  memory-mapped mode is limited to 256MB
84  This parameter can be a number between 0 and 31 */
85 
86  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
87  of clock cycles which the chip select must remain high between commands.
88  This parameter can be a value of @ref QSPI_ChipSelectHighTime */
89 
90  uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
91  This parameter can be a value of @ref QSPI_ClockMode */
92 
93  uint32_t FlashID; /* Specifies the Flash which will be used,
94  This parameter can be a value of @ref QSPI_Flash_Select */
95 
96  uint32_t DualFlash; /* Specifies the Dual Flash Mode State
97  This parameter can be a value of @ref QSPI_DualFlash_Mode */
98 }QSPI_InitTypeDef;
99 
103 typedef enum
104 {
105  HAL_QSPI_STATE_RESET = 0x00U,
106  HAL_QSPI_STATE_READY = 0x01U,
107  HAL_QSPI_STATE_BUSY = 0x02U,
108  HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U,
109  HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U,
110  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,
111  HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U,
112  HAL_QSPI_STATE_ABORT = 0x08U,
113  HAL_QSPI_STATE_ERROR = 0x04U
114 }HAL_QSPI_StateTypeDef;
115 
119 typedef struct
120 {
121  QUADSPI_TypeDef *Instance; /* QSPI registers base address */
122  QSPI_InitTypeDef Init; /* QSPI communication parameters */
123  uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
124  __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
125  __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
126  uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
127  __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
128  __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
129  DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
130  __IO HAL_LockTypeDef Lock; /* Locking object */
131  __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
132  __IO uint32_t ErrorCode; /* QSPI Error code */
133  uint32_t Timeout; /* Timeout for the QSPI memory access */
134 }QSPI_HandleTypeDef;
135 
139 typedef struct
140 {
141  uint32_t Instruction; /* Specifies the Instruction to be sent
142  This parameter can be a value (8-bit) between 0x00 and 0xFF */
143  uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
144  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
145  uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
146  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
147  uint32_t AddressSize; /* Specifies the Address Size
148  This parameter can be a value of @ref QSPI_AddressSize */
149  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
150  This parameter can be a value of @ref QSPI_AlternateBytesSize */
151  uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
152  This parameter can be a number between 0 and 31 */
153  uint32_t InstructionMode; /* Specifies the Instruction Mode
154  This parameter can be a value of @ref QSPI_InstructionMode */
155  uint32_t AddressMode; /* Specifies the Address Mode
156  This parameter can be a value of @ref QSPI_AddressMode */
157  uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
158  This parameter can be a value of @ref QSPI_AlternateBytesMode */
159  uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
160  This parameter can be a value of @ref QSPI_DataMode */
161  uint32_t NbData; /* Specifies the number of data to transfer.
162  This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
163  until end of memory)*/
164  uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
165  This parameter can be a value of @ref QSPI_DdrMode */
166  uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
167  system clock in DDR mode.
168  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
169  uint32_t SIOOMode; /* Specifies the send instruction only once mode
170  This parameter can be a value of @ref QSPI_SIOOMode */
171 }QSPI_CommandTypeDef;
172 
176 typedef struct
177 {
178  uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
179  This parameter can be any value between 0 and 0xFFFFFFFFU */
180  uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
181  This parameter can be any value between 0 and 0xFFFFFFFFU */
182  uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
183  This parameter can be any value between 0 and 0xFFFFU */
184  uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
185  This parameter can be any value between 1 and 4 */
186  uint32_t MatchMode; /* Specifies the method used for determining a match.
187  This parameter can be a value of @ref QSPI_MatchMode */
188  uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
189  This parameter can be a value of @ref QSPI_AutomaticStop */
190 }QSPI_AutoPollingTypeDef;
191 
195 typedef struct
196 {
197  uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
198  This parameter can be any value between 0 and 0xFFFFU */
199  uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
200  This parameter can be a value of @ref QSPI_TimeOutActivation */
201 }QSPI_MemoryMappedTypeDef;
206 /* Exported constants --------------------------------------------------------*/
213 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U)
214 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)
215 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)
216 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U)
217 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)
225 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)
226 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)
234 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U)
235 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
236 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
237 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
238 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
239 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
240 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
241 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)
249 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U)
250 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)
258 #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
259 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
260 
267 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
268 #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U)
269 
276 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U)
277 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
278 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
279 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)
287 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U)
288 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
289 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
290 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)
298 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U)
299 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
300 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
301 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)
309 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U)
310 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
311 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
312 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)
320 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U)
321 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
322 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
323 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)
331 #define QSPI_DATA_NONE ((uint32_t)0x00000000U)
332 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
333 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
334 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)
342 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U)
343 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)
351 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U)
352 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)
360 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U)
361 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)
369 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U)
370 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)
378 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U)
379 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)
387 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U)
388 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)
396 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY
397 #define QSPI_FLAG_TO QUADSPI_SR_TOF
398 #define QSPI_FLAG_SM QUADSPI_SR_SMF
399 #define QSPI_FLAG_FT QUADSPI_SR_FTF
400 #define QSPI_FLAG_TC QUADSPI_SR_TCF
401 #define QSPI_FLAG_TE QUADSPI_SR_TEF
409 #define QSPI_IT_TO QUADSPI_CR_TOIE
410 #define QSPI_IT_SM QUADSPI_CR_SMIE
411 #define QSPI_IT_FT QUADSPI_CR_FTIE
412 #define QSPI_IT_TC QUADSPI_CR_TCIE
413 #define QSPI_IT_TE QUADSPI_CR_TEIE
421 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U)/* 5 s */
422 
430 /* Exported macros -----------------------------------------------------------*/
439 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
440 
445 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
446 
451 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
452 
464 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
465 
466 
478 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
479 
491 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
492 
506 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
507 
518 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
519 
523 /* Exported functions --------------------------------------------------------*/
531 /* Initialization/de-initialization functions ********************************/
532 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
533 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
534 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
535 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
543 /* IO operation functions *****************************************************/
544 /* QSPI IRQ handler method */
545 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
546 
547 /* QSPI indirect mode */
548 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
549 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
550 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
551 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
552 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
553 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
554 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
555 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
556 
557 /* QSPI status flag polling mode */
558 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
559 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
560 
561 /* QSPI memory-mapped mode */
562 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
570 /* Callback functions in non-blocking modes ***********************************/
571 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
572 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
573 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
574 
575 /* QSPI indirect mode */
576 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
577 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
578 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
579 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
580 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
581 
582 /* QSPI status flag polling mode */
583 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
584 
585 /* QSPI memory-mapped mode */
586 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
594 /* Peripheral Control and State functions ************************************/
595 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
596 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
597 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
598 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
599 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
600 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
601 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
606 /* Private macros ------------------------------------------------------------*/
613 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
614 
621 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
622 
626 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
627  ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
628 
632 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
633 
637 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
638  ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
639  ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
640  ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
641  ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
642  ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
643  ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
644  ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
645 
646 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
647  ((CLKMODE) == QSPI_CLOCK_MODE_3))
648 
649 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
650  ((FLA) == QSPI_FLASH_ID_2))
651 
652 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
653  ((MODE) == QSPI_DUALFLASH_DISABLE))
654 
655 
659 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
660 
664 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
665  ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
666  ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
667  ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
668 
669 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
670  ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
671  ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
672  ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
673 
674 
678 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
679 
683 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
684  ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
685  ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
686  ((MODE) == QSPI_INSTRUCTION_4_LINES))
687 
688 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
689  ((MODE) == QSPI_ADDRESS_1_LINE) || \
690  ((MODE) == QSPI_ADDRESS_2_LINES) || \
691  ((MODE) == QSPI_ADDRESS_4_LINES))
692 
693 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
694  ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
695  ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
696  ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
697 
698 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
699  ((MODE) == QSPI_DATA_1_LINE) || \
700  ((MODE) == QSPI_DATA_2_LINES) || \
701  ((MODE) == QSPI_DATA_4_LINES))
702 
703 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
704  ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
705 
706 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
707  ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
708 
709 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
710  ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
711 
715 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
716 
723 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
724 
727 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
728  ((MODE) == QSPI_MATCH_MODE_OR))
729 
730 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
731  ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
732 
733 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
734  ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
735 
739 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
740 
744 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
745  ((FLAG) == QSPI_FLAG_TO) || \
746  ((FLAG) == QSPI_FLAG_SM) || \
747  ((FLAG) == QSPI_FLAG_FT) || \
748  ((FLAG) == QSPI_FLAG_TC) || \
749  ((FLAG) == QSPI_FLAG_TE))
750 
751 #define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
752 
756 /* Private functions ---------------------------------------------------------*/
776 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx */
777 
778 #ifdef __cplusplus
779 }
780 #endif
781 
782 #endif /* __STM32F4xx_HAL_QSPI_H */
783 
784 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f412rx.h:645
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
__IO
#define __IO
Definition: core_cm0.h:213
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:68
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:157