STM CMSIS
stm32f4xx_hal_rcc_ex.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_RCC_EX_H
40 #define __STM32F4xx_HAL_RCC_EX_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48 
57 /* Exported types ------------------------------------------------------------*/
65 typedef struct
66 {
67  uint32_t PLLState;
70  uint32_t PLLSource;
73  uint32_t PLLM;
76  uint32_t PLLN;
80  uint32_t PLLP;
83  uint32_t PLLQ;
85 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
86  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
87  uint32_t PLLR;
91 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
92 }RCC_PLLInitTypeDef;
93 
94 #if defined(STM32F446xx)
95 
98 typedef struct
99 {
100  uint32_t PLLI2SM;
103  uint32_t PLLI2SN;
106  uint32_t PLLI2SP;
109  uint32_t PLLI2SQ;
113  uint32_t PLLI2SR;
116 }RCC_PLLI2SInitTypeDef;
117 
121 typedef struct
122 {
123  uint32_t PLLSAIM;
126  uint32_t PLLSAIN;
129  uint32_t PLLSAIP;
132  uint32_t PLLSAIQ;
135 }RCC_PLLSAIInitTypeDef;
136 
140 typedef struct
141 {
142  uint32_t PeriphClockSelection;
145  RCC_PLLI2SInitTypeDef PLLI2S;
148  RCC_PLLSAIInitTypeDef PLLSAI;
151  uint32_t PLLI2SDivQ;
155  uint32_t PLLSAIDivQ;
159  uint32_t Sai1ClockSelection;
162  uint32_t Sai2ClockSelection;
165  uint32_t I2sApb1ClockSelection;
168  uint32_t I2sApb2ClockSelection;
171  uint32_t RTCClockSelection;
174  uint32_t SdioClockSelection;
177  uint32_t CecClockSelection;
180  uint32_t Fmpi2c1ClockSelection;
183  uint32_t SpdifClockSelection;
186  uint32_t Clk48ClockSelection;
189  uint8_t TIMPresSelection;
191 }RCC_PeriphCLKInitTypeDef;
192 #endif /* STM32F446xx */
193 
194 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
195 
198 typedef struct
199 {
200  uint32_t PeriphClockSelection;
203  uint32_t I2SClockSelection;
206  uint32_t RTCClockSelection;
209  uint32_t Lptim1ClockSelection;
212  uint32_t Fmpi2c1ClockSelection;
215  uint8_t TIMPresSelection;
217 }RCC_PeriphCLKInitTypeDef;
218 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
219 
220 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
221 
224 typedef struct
225 {
226  uint32_t PLLI2SM;
229  uint32_t PLLI2SN;
232  uint32_t PLLI2SQ;
236  uint32_t PLLI2SR;
239 }RCC_PLLI2SInitTypeDef;
240 
244 typedef struct
245 {
246  uint32_t PeriphClockSelection;
249  RCC_PLLI2SInitTypeDef PLLI2S;
252  uint32_t I2sApb1ClockSelection;
255  uint32_t I2sApb2ClockSelection;
258  uint32_t RTCClockSelection;
261  uint32_t SdioClockSelection;
264  uint32_t Fmpi2c1ClockSelection;
267  uint32_t Clk48ClockSelection;
270  uint32_t Dfsdm1ClockSelection;
273  uint32_t Dfsdm1AudioClockSelection;
276  uint32_t PLLI2SSelection;
279  uint8_t TIMPresSelection;
281 }RCC_PeriphCLKInitTypeDef;
282 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
283 
284 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
285 
289 typedef struct
290 {
291  uint32_t PLLI2SN;
295  uint32_t PLLI2SR;
299  uint32_t PLLI2SQ;
302 }RCC_PLLI2SInitTypeDef;
303 
307 typedef struct
308 {
309  uint32_t PLLSAIN;
312 #if defined(STM32F469xx) || defined(STM32F479xx)
313  uint32_t PLLSAIP;
316 #endif /* STM32F469xx || STM32F479xx */
317 
318  uint32_t PLLSAIQ;
322  uint32_t PLLSAIR;
326 }RCC_PLLSAIInitTypeDef;
327 
331 typedef struct
332 {
333  uint32_t PeriphClockSelection;
336  RCC_PLLI2SInitTypeDef PLLI2S;
339  RCC_PLLSAIInitTypeDef PLLSAI;
342  uint32_t PLLI2SDivQ;
346  uint32_t PLLSAIDivQ;
350  uint32_t PLLSAIDivR;
353  uint32_t RTCClockSelection;
356  uint8_t TIMPresSelection;
358 #if defined(STM32F469xx) || defined(STM32F479xx)
359  uint32_t Clk48ClockSelection;
362  uint32_t SdioClockSelection;
364 #endif /* STM32F469xx || STM32F479xx */
365 }RCC_PeriphCLKInitTypeDef;
366 
367 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
368 
369 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
370  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
371 
374 typedef struct
375 {
376 #if defined(STM32F411xE)
377  uint32_t PLLI2SM;
379 #endif /* STM32F411xE */
380 
381  uint32_t PLLI2SN;
386  uint32_t PLLI2SR;
390 }RCC_PLLI2SInitTypeDef;
391 
395 typedef struct
396 {
397  uint32_t PeriphClockSelection;
400  RCC_PLLI2SInitTypeDef PLLI2S;
403  uint32_t RTCClockSelection;
405 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
406  uint8_t TIMPresSelection;
408 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
409 }RCC_PeriphCLKInitTypeDef;
410 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
411 
415 /* Exported constants --------------------------------------------------------*/
423 /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
424 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
425 #define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001U)
426 #define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002U)
427 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000004U)
428 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000008U)
429 #define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000010U)
430 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000020U)
431 #define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000040U)
432 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000080U)
433 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00000100U)
434 #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x00000200U)
435 #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
436 /*----------------------------------------------------------------------------*/
437 
438 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/
439 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
440 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
441 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002U)
442 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004U)
443 #define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008U)
444 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010U)
445 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
446 /*----------------------------------------------------------------------------*/
447 
448 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/
449 #if defined(STM32F446xx)
450 #define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001U)
451 #define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002U)
452 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004U)
453 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008U)
454 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
455 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
456 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040U)
457 #define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080U)
458 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000100U)
459 #define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200U)
460 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400U)
461 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800U)
462 #endif /* STM32F446xx */
463 /*-----------------------------------------------------------------------------*/
464 
465 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
466 #if defined(STM32F469xx) || defined(STM32F479xx)
467 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
468 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002U)
469 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004U)
470 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
471 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
472 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
473 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040U)
474 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000080U)
475 #define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000100U)
476 #endif /* STM32F469xx || STM32F479xx */
477 /*----------------------------------------------------------------------------*/
478 
479 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
480 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
481 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
482 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002U)
483 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004U)
484 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
485 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
486 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
487 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040U)
488 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
489 /*----------------------------------------------------------------------------*/
490 
491 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
492 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
493  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
494 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
495 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002U)
496 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004U)
497 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
498 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
499 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000008U)
500 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
501 /*----------------------------------------------------------------------------*/
505 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
506  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
507  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
508  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
509  defined(STM32F412Rx) || defined(STM32F412Cx)
510 
513 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
514 #define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001U)
515 
518 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
519  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
520  STM32F412Rx || STM32F412Cx */
521 
525 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
526  defined(STM32F469xx) || defined(STM32F479xx)
527 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
528 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000U)
529 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000U)
530 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000U)
531 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
532 
539 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
540  defined(STM32F412Rx) || defined(STM32F412Cx)
541 #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002U)
542 #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004U)
543 #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006U)
544 #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008U)
545 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
546 
553 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
554 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002U)
555 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004U)
556 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006U)
557 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008U)
558 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
559 
563 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
564 
567 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
568 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000U)
569 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000U)
570 
577 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
578 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000U)
579 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000U)
580 
583 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
584 
585 #if defined(STM32F469xx) || defined(STM32F479xx)
586 
589 #define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
590 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
591 
598 #define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
599 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
600 
607 #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
608 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
609 
612 #endif /* STM32F469xx || STM32F479xx */
613 
614 #if defined(STM32F446xx)
615 
618 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
619 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
620 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
621 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
622 
629 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
630 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
631 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
632 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
633 
640 #define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
641 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
642 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
643 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
644 
651 #define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
652 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
653 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
654 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
655 
662 #define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
663 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
664 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
665 
672 #define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000U)
673 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
674 
681 #define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
682 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
683 
690 #define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
691 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
692 
699 #define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000U)
700 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
701 
705 #endif /* STM32F446xx */
706 
707 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
708 
711 #define RCC_PLLI2SCLKSOURCE_PLLSRC ((uint32_t)0x00000000U)
712 #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
713 
720 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000U)
721 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
722 
729 #define RCC_DFSDM1CLKSOURCE_APB2 ((uint32_t)0x00000000U)
730 #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
731 
738 #define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
739 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
740 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
741 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
742 
749 #define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
750 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
751 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
752 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
753 
760 #define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
761 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
762 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
763 
770 #define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
771 #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
772 
779 #define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
780 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
781 
784 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
785 
786 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
787 
791 #define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000U)
792 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
793 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
794 
801 #define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
802 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
803 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
804 
811 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
812 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
813 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
814 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
815 
818 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
819 
820 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
821  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
822  defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
823  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
824  defined(STM32F412Cx)
825 
828 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U)
829 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U)
830 
833 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
834  STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
835  STM32F412Vx || STM32F412Rx || STM32F412Cx */
836 
837 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
838  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
839  defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
840 
843 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00U)
844 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01U)
845 
848 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
849  STM32F412Rx || STM32F412Cx */
850 
851 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
852  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
853  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
854  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
855  defined(STM32F412Rx)
856 
859 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
860 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
861 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
862 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
863 
866 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
867  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
868  STM32F412Rx */
869 
870 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
871 
874 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
875 #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
876 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
877 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
878 
881 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
882 
887 /* Exported macro ------------------------------------------------------------*/
891 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
892 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
893 
900 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
901  __IO uint32_t tmpreg = 0x00U; \
902  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
903  /* Delay after an RCC peripheral clock enabling */ \
904  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
905  UNUSED(tmpreg); \
906  } while(0)
907 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
908  __IO uint32_t tmpreg = 0x00U; \
909  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
910  /* Delay after an RCC peripheral clock enabling */ \
911  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
912  UNUSED(tmpreg); \
913  } while(0)
914 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
915  __IO uint32_t tmpreg = 0x00U; \
916  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
917  /* Delay after an RCC peripheral clock enabling */ \
918  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
919  UNUSED(tmpreg); \
920  } while(0)
921 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
922  __IO uint32_t tmpreg = 0x00U; \
923  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
924  /* Delay after an RCC peripheral clock enabling */ \
925  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
926  UNUSED(tmpreg); \
927  } while(0)
928 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
929  __IO uint32_t tmpreg = 0x00U; \
930  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
931  /* Delay after an RCC peripheral clock enabling */ \
932  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
933  UNUSED(tmpreg); \
934  } while(0)
935 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
936  __IO uint32_t tmpreg = 0x00U; \
937  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
938  /* Delay after an RCC peripheral clock enabling */ \
939  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
940  UNUSED(tmpreg); \
941  } while(0)
942 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
943  __IO uint32_t tmpreg = 0x00U; \
944  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
945  /* Delay after an RCC peripheral clock enabling */ \
946  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
947  UNUSED(tmpreg); \
948  } while(0)
949 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
950  __IO uint32_t tmpreg = 0x00U; \
951  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
952  /* Delay after an RCC peripheral clock enabling */ \
953  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
954  UNUSED(tmpreg); \
955  } while(0)
956 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
957  __IO uint32_t tmpreg = 0x00U; \
958  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
959  /* Delay after an RCC peripheral clock enabling */ \
960  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
961  UNUSED(tmpreg); \
962  } while(0)
963 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
964  __IO uint32_t tmpreg = 0x00U; \
965  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
966  /* Delay after an RCC peripheral clock enabling */ \
967  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
968  UNUSED(tmpreg); \
969  } while(0)
970 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
971  __IO uint32_t tmpreg = 0x00U; \
972  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
973  /* Delay after an RCC peripheral clock enabling */ \
974  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
975  UNUSED(tmpreg); \
976  } while(0)
977 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
978  __IO uint32_t tmpreg = 0x00U; \
979  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
980  /* Delay after an RCC peripheral clock enabling */ \
981  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
982  UNUSED(tmpreg); \
983  } while(0)
984 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
985  __IO uint32_t tmpreg = 0x00U; \
986  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
987  /* Delay after an RCC peripheral clock enabling */ \
988  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
989  UNUSED(tmpreg); \
990  } while(0)
991 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
992  __IO uint32_t tmpreg = 0x00U; \
993  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
994  /* Delay after an RCC peripheral clock enabling */ \
995  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
996  UNUSED(tmpreg); \
997  } while(0)
998 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
999  __IO uint32_t tmpreg = 0x00U; \
1000  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
1001  /* Delay after an RCC peripheral clock enabling */ \
1002  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
1003  UNUSED(tmpreg); \
1004  } while(0)
1005 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
1006  __IO uint32_t tmpreg = 0x00U; \
1007  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
1008  /* Delay after an RCC peripheral clock enabling */ \
1009  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
1010  UNUSED(tmpreg); \
1011  } while(0)
1012 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
1013  __IO uint32_t tmpreg = 0x00U; \
1014  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
1015  /* Delay after an RCC peripheral clock enabling */ \
1016  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
1017  UNUSED(tmpreg); \
1018  } while(0)
1019 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
1020 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
1021 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
1022 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
1023 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
1024 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
1025 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
1026 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
1027 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
1028 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
1029 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
1030 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
1031 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
1032 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
1033 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
1034 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
1035 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
1036 
1040 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
1041  __HAL_RCC_ETHMAC_CLK_ENABLE(); \
1042  __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
1043  __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
1044  } while(0)
1045 
1048 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
1049  __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
1050  __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
1051  __HAL_RCC_ETHMAC_CLK_DISABLE(); \
1052  } while(0)
1053 
1064 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
1065 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
1066 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
1067 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
1068 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
1069 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
1070 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
1071 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
1072 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
1073 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
1074 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
1075 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
1076 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
1077 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
1078 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
1079 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
1080 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
1081 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
1082  __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
1083  __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
1084 
1085 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
1086 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
1087 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
1088 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
1089 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
1090 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
1091 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
1092 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
1093 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
1094 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
1095 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
1096 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
1097 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
1098 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
1099 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
1100 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
1101 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
1102 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
1103  __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
1104  __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
1105 
1116  #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
1117  __IO uint32_t tmpreg = 0x00U; \
1118  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1119  /* Delay after an RCC peripheral clock enabling */ \
1120  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1121  UNUSED(tmpreg); \
1122  } while(0)
1123 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
1124 
1125 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1126 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
1127  __IO uint32_t tmpreg = 0x00U; \
1128  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1129  /* Delay after an RCC peripheral clock enabling */ \
1130  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1131  UNUSED(tmpreg); \
1132  } while(0)
1133 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
1134  __IO uint32_t tmpreg = 0x00U; \
1135  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1136  /* Delay after an RCC peripheral clock enabling */ \
1137  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1138  UNUSED(tmpreg); \
1139  } while(0)
1140 
1141 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
1142 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
1143 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1144 
1145 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
1146  __HAL_RCC_SYSCFG_CLK_ENABLE();\
1147  }while(0)
1148 
1149 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
1150 
1151 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
1152  __IO uint32_t tmpreg = 0x00U; \
1153  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1154  /* Delay after an RCC peripheral clock enabling */ \
1155  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1156  UNUSED(tmpreg); \
1157  } while(0)
1158 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
1159 
1170 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
1171 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
1172 
1173 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1174 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
1175 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
1176 
1177 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
1178 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
1179 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1180 
1181 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
1182 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
1183 
1184 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
1185 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
1186 
1197 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
1198  __IO uint32_t tmpreg = 0x00U; \
1199  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1200  /* Delay after an RCC peripheral clock enabling */ \
1201  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1202  UNUSED(tmpreg); \
1203  } while(0)
1204 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
1205 #if defined(STM32F469xx) || defined(STM32F479xx)
1206 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
1207  __IO uint32_t tmpreg = 0x00U; \
1208  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1209  /* Delay after an RCC peripheral clock enabling */ \
1210  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
1211  UNUSED(tmpreg); \
1212  } while(0)
1213 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
1214 #endif /* STM32F469xx || STM32F479xx */
1215 
1227 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1228 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
1229 #if defined(STM32F469xx) || defined(STM32F479xx)
1230 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
1231 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
1232 #endif /* STM32F469xx || STM32F479xx */
1233 
1244 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
1245  __IO uint32_t tmpreg = 0x00U; \
1246  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
1247  /* Delay after an RCC peripheral clock enabling */ \
1248  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
1249  UNUSED(tmpreg); \
1250  } while(0)
1251 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
1252  __IO uint32_t tmpreg = 0x00U; \
1253  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
1254  /* Delay after an RCC peripheral clock enabling */ \
1255  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
1256  UNUSED(tmpreg); \
1257  } while(0)
1258 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
1259  __IO uint32_t tmpreg = 0x00U; \
1260  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1261  /* Delay after an RCC peripheral clock enabling */ \
1262  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1263  UNUSED(tmpreg); \
1264  } while(0)
1265 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
1266  __IO uint32_t tmpreg = 0x00U; \
1267  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1268  /* Delay after an RCC peripheral clock enabling */ \
1269  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1270  UNUSED(tmpreg); \
1271  } while(0)
1272 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1273  __IO uint32_t tmpreg = 0x00U; \
1274  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1275  /* Delay after an RCC peripheral clock enabling */ \
1276  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1277  UNUSED(tmpreg); \
1278  } while(0)
1279 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1280  __IO uint32_t tmpreg = 0x00U; \
1281  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1282  /* Delay after an RCC peripheral clock enabling */ \
1283  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1284  UNUSED(tmpreg); \
1285  } while(0)
1286 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
1287  __IO uint32_t tmpreg = 0x00U; \
1288  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1289  /* Delay after an RCC peripheral clock enabling */ \
1290  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
1291  UNUSED(tmpreg); \
1292  } while(0)
1293 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
1294  __IO uint32_t tmpreg = 0x00U; \
1295  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1296  /* Delay after an RCC peripheral clock enabling */ \
1297  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1298  UNUSED(tmpreg); \
1299  } while(0)
1300 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1301  __IO uint32_t tmpreg = 0x00U; \
1302  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1303  /* Delay after an RCC peripheral clock enabling */ \
1304  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1305  UNUSED(tmpreg); \
1306  } while(0)
1307 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
1308  __IO uint32_t tmpreg = 0x00U; \
1309  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1310  /* Delay after an RCC peripheral clock enabling */ \
1311  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
1312  UNUSED(tmpreg); \
1313  } while(0)
1314 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1315  __IO uint32_t tmpreg = 0x00U; \
1316  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1317  /* Delay after an RCC peripheral clock enabling */ \
1318  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1319  UNUSED(tmpreg); \
1320  } while(0)
1321 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
1322  __IO uint32_t tmpreg = 0x00U; \
1323  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1324  /* Delay after an RCC peripheral clock enabling */ \
1325  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
1326  UNUSED(tmpreg); \
1327  } while(0)
1328 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
1329  __IO uint32_t tmpreg = 0x00U; \
1330  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1331  /* Delay after an RCC peripheral clock enabling */ \
1332  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
1333  UNUSED(tmpreg); \
1334  } while(0)
1335 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
1336  __IO uint32_t tmpreg = 0x00U; \
1337  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1338  /* Delay after an RCC peripheral clock enabling */ \
1339  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
1340  UNUSED(tmpreg); \
1341  } while(0)
1342 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
1343  __IO uint32_t tmpreg = 0x00U; \
1344  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
1345  /* Delay after an RCC peripheral clock enabling */ \
1346  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
1347  UNUSED(tmpreg); \
1348  } while(0)
1349 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
1350  __IO uint32_t tmpreg = 0x00U; \
1351  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
1352  /* Delay after an RCC peripheral clock enabling */ \
1353  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
1354  UNUSED(tmpreg); \
1355  } while(0)
1356 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
1357  __IO uint32_t tmpreg = 0x00U; \
1358  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
1359  /* Delay after an RCC peripheral clock enabling */ \
1360  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
1361  UNUSED(tmpreg); \
1362  } while(0)
1363 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
1364  __IO uint32_t tmpreg = 0x00U; \
1365  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1366  /* Delay after an RCC peripheral clock enabling */ \
1367  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1368  UNUSED(tmpreg); \
1369  } while(0)
1370 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1371  __IO uint32_t tmpreg = 0x00U; \
1372  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1373  /* Delay after an RCC peripheral clock enabling */ \
1374  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
1375  UNUSED(tmpreg); \
1376  } while(0)
1377 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1378 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
1379 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
1380 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1381 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
1382 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
1383 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
1384 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1385 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1386 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1387 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
1388 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
1389 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
1390 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
1391 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1392 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
1393 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
1394 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
1395 
1406 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
1407 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
1408 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
1409 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1410 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
1411 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1412 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1413 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1414 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1415 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1416 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
1417 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1418 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1419 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
1420 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1421 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1422 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
1423 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
1424 
1425 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
1426 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
1427 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
1428 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1429 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
1430 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1431 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1432 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1433 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1434 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1435 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
1436 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1437 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1438 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
1439 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
1440 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1441 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
1442 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
1443 
1454 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1455  __IO uint32_t tmpreg = 0x00U; \
1456  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1457  /* Delay after an RCC peripheral clock enabling */ \
1458  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1459  UNUSED(tmpreg); \
1460  } while(0)
1461 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
1462  __IO uint32_t tmpreg = 0x00U; \
1463  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1464  /* Delay after an RCC peripheral clock enabling */ \
1465  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1466  UNUSED(tmpreg); \
1467  } while(0)
1468 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1469  __IO uint32_t tmpreg = 0x00U; \
1470  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1471  /* Delay after an RCC peripheral clock enabling */ \
1472  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1473  UNUSED(tmpreg); \
1474  } while(0)
1475 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
1476  __IO uint32_t tmpreg = 0x00U; \
1477  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1478  /* Delay after an RCC peripheral clock enabling */ \
1479  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1480  UNUSED(tmpreg); \
1481  } while(0)
1482 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
1483  __IO uint32_t tmpreg = 0x00U; \
1484  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1485  /* Delay after an RCC peripheral clock enabling */ \
1486  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
1487  UNUSED(tmpreg); \
1488  } while(0)
1489 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
1490  __IO uint32_t tmpreg = 0x00U; \
1491  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1492  /* Delay after an RCC peripheral clock enabling */ \
1493  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1494  UNUSED(tmpreg); \
1495  } while(0)
1496 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
1497  __IO uint32_t tmpreg = 0x00U; \
1498  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
1499  /* Delay after an RCC peripheral clock enabling */ \
1500  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
1501  UNUSED(tmpreg); \
1502  } while(0)
1503 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
1504  __IO uint32_t tmpreg = 0x00U; \
1505  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1506  /* Delay after an RCC peripheral clock enabling */ \
1507  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1508  UNUSED(tmpreg); \
1509  } while(0)
1510 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
1511  __IO uint32_t tmpreg = 0x00U; \
1512  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1513  /* Delay after an RCC peripheral clock enabling */ \
1514  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1515  UNUSED(tmpreg); \
1516  } while(0)
1517 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
1518 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
1519 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1520 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1521 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1522 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1523 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
1524 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
1525 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
1526 
1527 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1528 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
1529  __IO uint32_t tmpreg = 0x00U; \
1530  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1531  /* Delay after an RCC peripheral clock enabling */ \
1532  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
1533  UNUSED(tmpreg); \
1534  } while(0)
1535 
1536 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
1537 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1538 
1539 #if defined(STM32F469xx) || defined(STM32F479xx)
1540 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
1541  __IO uint32_t tmpreg = 0x00U; \
1542  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1543  /* Delay after an RCC peripheral clock enabling */ \
1544  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
1545  UNUSED(tmpreg); \
1546  } while(0)
1547 
1548 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
1549 #endif /* STM32F469xx || STM32F479xx */
1550 
1561 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
1562 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
1563 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
1564 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
1565 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
1566 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
1567 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
1568 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
1569 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
1570 
1571 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
1572 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
1573 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
1574 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
1575 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
1576 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
1577 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
1578 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
1579 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
1580 
1581 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1582 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
1583 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
1584 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1585 
1586 #if defined(STM32F469xx) || defined(STM32F479xx)
1587 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
1588 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
1589 #endif /* STM32F469xx || STM32F479xx */
1590 
1598 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
1599 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
1600 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
1601 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
1602 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
1603 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
1604 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
1605 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
1606 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
1607 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
1608 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
1609 
1610 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
1611 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
1612 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
1613 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
1614 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
1615 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
1616 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
1617 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
1618 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
1619 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
1620 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
1621 
1629 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
1630 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
1631 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
1632 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
1633 
1634 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
1635 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
1636 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
1637 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
1638 
1639 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1640 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
1641 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
1642 
1643 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
1644 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
1645 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1646 
1654 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
1655 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
1656 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
1657 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
1658 
1659 #if defined(STM32F469xx) || defined(STM32F479xx)
1660 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
1661 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
1662 #endif /* STM32F469xx || STM32F479xx */
1663 
1671 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1672 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1673 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1674 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1675 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1676 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1677 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1678 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1679 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1680 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1681 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1682 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
1683 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
1684 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1685 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
1686 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1687 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1688 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
1689 
1690 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1691 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
1692 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1693 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1694 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
1695 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1696 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1697 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1698 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1699 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1700 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1701 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1702 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1703 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1704 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1705 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1706 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
1707 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
1708 
1716 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1717 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
1718 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
1719 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
1720 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
1721 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
1722 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1723 
1724 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
1725 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
1726 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1727 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1728 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
1729 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
1730 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
1731 
1732 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1733 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
1734 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
1735 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
1736 
1737 #if defined(STM32F469xx) || defined(STM32F479xx)
1738 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
1739 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
1740 #endif /* STM32F469xx || STM32F479xx */
1741 
1753 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
1754 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
1755 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
1756 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
1757 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
1758 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
1759 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
1760 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
1761 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
1762 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
1763 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
1764 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
1765 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
1766 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
1767 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
1768 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
1769 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
1770 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
1771 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
1772 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
1773 
1774 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
1775 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
1776 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
1777 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
1778 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
1779 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
1780 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
1781 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
1782 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
1783 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
1784 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
1785 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
1786 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
1787 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
1788 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
1789 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
1790 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
1791 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
1792 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
1793 
1805 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
1806 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
1807 
1808 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
1809 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
1810 
1811 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
1812 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
1813 
1814 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
1815 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
1816 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
1817 
1818 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
1819 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
1820 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */
1821 
1833 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
1834 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
1835 
1836 #if defined(STM32F469xx) || defined(STM32F479xx)
1837 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
1838 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
1839 #endif /* STM32F469xx || STM32F479xx */
1840 
1852 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
1853 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
1854 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
1855 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
1856 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
1857 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
1858 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
1859 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
1860 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
1861 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
1862 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
1863 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
1864 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
1865 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
1866 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
1867 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
1868 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
1869 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
1870 
1871 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
1872 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
1873 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
1874 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
1875 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
1876 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
1877 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
1878 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
1879 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
1880 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
1881 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
1882 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
1883 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
1884 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
1885 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
1886 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
1887 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
1888 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
1889 
1901 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
1902 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
1903 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
1904 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
1905 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
1906 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
1907 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
1908 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
1909 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
1910 
1911 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
1912 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
1913 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
1914 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
1915 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
1916 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
1917 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
1918 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
1919 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
1920 
1921 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
1922 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
1923 
1924 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
1925 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
1926 
1927 #if defined(STM32F469xx) || defined(STM32F479xx)
1928 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
1929 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
1930 #endif /* STM32F469xx || STM32F479xx */
1931 
1934 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
1935 /*----------------------------------------------------------------------------*/
1936 
1937 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
1938 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
1939 
1946 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
1947  __IO uint32_t tmpreg = 0x00U; \
1948  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
1949  /* Delay after an RCC peripheral clock enabling */ \
1950  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
1951  UNUSED(tmpreg); \
1952  } while(0)
1953 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
1954  __IO uint32_t tmpreg = 0x00U; \
1955  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
1956  /* Delay after an RCC peripheral clock enabling */ \
1957  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
1958  UNUSED(tmpreg); \
1959  } while(0)
1960 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
1961  __IO uint32_t tmpreg = 0x00U; \
1962  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1963  /* Delay after an RCC peripheral clock enabling */ \
1964  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1965  UNUSED(tmpreg); \
1966  } while(0)
1967 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
1968  __IO uint32_t tmpreg = 0x00U; \
1969  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
1970  /* Delay after an RCC peripheral clock enabling */ \
1971  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
1972  UNUSED(tmpreg); \
1973  } while(0)
1974 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1975  __IO uint32_t tmpreg = 0x00U; \
1976  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
1977  /* Delay after an RCC peripheral clock enabling */ \
1978  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
1979  UNUSED(tmpreg); \
1980  } while(0)
1981 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
1982  __IO uint32_t tmpreg = 0x00U; \
1983  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
1984  /* Delay after an RCC peripheral clock enabling */ \
1985  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
1986  UNUSED(tmpreg); \
1987  } while(0)
1988 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1989  __IO uint32_t tmpreg = 0x00U; \
1990  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
1991  /* Delay after an RCC peripheral clock enabling */ \
1992  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
1993  UNUSED(tmpreg); \
1994  } while(0)
1995 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1996  __IO uint32_t tmpreg = 0x00U; \
1997  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
1998  /* Delay after an RCC peripheral clock enabling */ \
1999  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
2000  UNUSED(tmpreg); \
2001  } while(0)
2002 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
2003  __IO uint32_t tmpreg = 0x00U; \
2004  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
2005  /* Delay after an RCC peripheral clock enabling */ \
2006  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
2007  UNUSED(tmpreg); \
2008  } while(0)
2009 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
2010  __IO uint32_t tmpreg = 0x00U; \
2011  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
2012  /* Delay after an RCC peripheral clock enabling */ \
2013  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
2014  UNUSED(tmpreg); \
2015  } while(0)
2016 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
2017 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
2018 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
2019 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
2020 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
2021 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
2022 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
2023 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
2024 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
2025 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
2026 #if defined(STM32F407xx)|| defined(STM32F417xx)
2027 
2030 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
2031  __IO uint32_t tmpreg = 0x00U; \
2032  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
2033  /* Delay after an RCC peripheral clock enabling */ \
2034  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
2035  UNUSED(tmpreg); \
2036  } while(0)
2037 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
2038  __IO uint32_t tmpreg = 0x00U; \
2039  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
2040  /* Delay after an RCC peripheral clock enabling */ \
2041  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
2042  UNUSED(tmpreg); \
2043  } while(0)
2044 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
2045  __IO uint32_t tmpreg = 0x00U; \
2046  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
2047  /* Delay after an RCC peripheral clock enabling */ \
2048  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
2049  UNUSED(tmpreg); \
2050  } while(0)
2051 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
2052  __IO uint32_t tmpreg = 0x00U; \
2053  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
2054  /* Delay after an RCC peripheral clock enabling */ \
2055  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
2056  UNUSED(tmpreg); \
2057  } while(0)
2058 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
2059  __HAL_RCC_ETHMAC_CLK_ENABLE(); \
2060  __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
2061  __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
2062  } while(0)
2063 
2067 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
2068 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
2069 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
2070 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
2071 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
2072  __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
2073  __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
2074  __HAL_RCC_ETHMAC_CLK_DISABLE(); \
2075  } while(0)
2076 #endif /* STM32F407xx || STM32F417xx */
2077 
2088 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
2089 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
2090 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
2091 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
2092 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
2093 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
2094 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
2095 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
2096 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
2097 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
2098 
2099 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
2100 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
2101 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
2102 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
2103 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
2104 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
2105 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
2106 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
2107 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
2108 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
2109 #if defined(STM32F407xx)|| defined(STM32F417xx)
2110 
2113 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
2114 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
2115 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
2116 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
2117 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
2118  __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
2119  __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
2120 
2123 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
2124 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
2125 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
2126 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
2127 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
2128  __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
2129  __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
2130 #endif /* STM32F407xx || STM32F417xx */
2131 
2142 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
2143  __HAL_RCC_SYSCFG_CLK_ENABLE();\
2144  }while(0)
2145 
2146 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
2147 
2148 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
2149  __IO uint32_t tmpreg = 0x00U; \
2150  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2151  /* Delay after an RCC peripheral clock enabling */ \
2152  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2153  UNUSED(tmpreg); \
2154  } while(0)
2155 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
2156 
2157 #if defined(STM32F407xx)|| defined(STM32F417xx)
2158 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
2159  __IO uint32_t tmpreg = 0x00U; \
2160  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2161  /* Delay after an RCC peripheral clock enabling */ \
2162  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2163  UNUSED(tmpreg); \
2164  } while(0)
2165 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
2166 #endif /* STM32F407xx || STM32F417xx */
2167 
2168 #if defined(STM32F415xx) || defined(STM32F417xx)
2169 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
2170  __IO uint32_t tmpreg = 0x00U; \
2171  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2172  /* Delay after an RCC peripheral clock enabling */ \
2173  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2174  UNUSED(tmpreg); \
2175  } while(0)
2176 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
2177  __IO uint32_t tmpreg = 0x00U; \
2178  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2179  /* Delay after an RCC peripheral clock enabling */ \
2180  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2181  UNUSED(tmpreg); \
2182  } while(0)
2183 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
2184 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
2185 #endif /* STM32F415xx || STM32F417xx */
2186 
2198 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
2199 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
2200 
2201 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
2202 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
2203 
2204 #if defined(STM32F407xx)|| defined(STM32F417xx)
2205 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
2206 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
2207 #endif /* STM32F407xx || STM32F417xx */
2208 
2209 #if defined(STM32F415xx) || defined(STM32F417xx)
2210 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
2211 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
2212 
2213 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
2214 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
2215 #endif /* STM32F415xx || STM32F417xx */
2216 
2227 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
2228  __IO uint32_t tmpreg = 0x00U; \
2229  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
2230  /* Delay after an RCC peripheral clock enabling */ \
2231  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
2232  UNUSED(tmpreg); \
2233  } while(0)
2234 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
2235 
2246 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
2247 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
2248 
2259 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
2260  __IO uint32_t tmpreg = 0x00U; \
2261  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
2262  /* Delay after an RCC peripheral clock enabling */ \
2263  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
2264  UNUSED(tmpreg); \
2265  } while(0)
2266 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
2267  __IO uint32_t tmpreg = 0x00U; \
2268  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
2269  /* Delay after an RCC peripheral clock enabling */ \
2270  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
2271  UNUSED(tmpreg); \
2272  } while(0)
2273 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
2274  __IO uint32_t tmpreg = 0x00U; \
2275  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
2276  /* Delay after an RCC peripheral clock enabling */ \
2277  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
2278  UNUSED(tmpreg); \
2279  } while(0)
2280 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
2281  __IO uint32_t tmpreg = 0x00U; \
2282  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
2283  /* Delay after an RCC peripheral clock enabling */ \
2284  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
2285  UNUSED(tmpreg); \
2286  } while(0)
2287 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
2288  __IO uint32_t tmpreg = 0x00U; \
2289  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
2290  /* Delay after an RCC peripheral clock enabling */ \
2291  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
2292  UNUSED(tmpreg); \
2293  } while(0)
2294 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
2295  __IO uint32_t tmpreg = 0x00U; \
2296  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
2297  /* Delay after an RCC peripheral clock enabling */ \
2298  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
2299  UNUSED(tmpreg); \
2300  } while(0)
2301 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
2302  __IO uint32_t tmpreg = 0x00U; \
2303  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
2304  /* Delay after an RCC peripheral clock enabling */ \
2305  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
2306  UNUSED(tmpreg); \
2307  } while(0)
2308 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
2309  __IO uint32_t tmpreg = 0x00U; \
2310  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
2311  /* Delay after an RCC peripheral clock enabling */ \
2312  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
2313  UNUSED(tmpreg); \
2314  } while(0)
2315 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
2316  __IO uint32_t tmpreg = 0x00U; \
2317  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
2318  /* Delay after an RCC peripheral clock enabling */ \
2319  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
2320  UNUSED(tmpreg); \
2321  } while(0)
2322 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
2323  __IO uint32_t tmpreg = 0x00U; \
2324  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
2325  /* Delay after an RCC peripheral clock enabling */ \
2326  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
2327  UNUSED(tmpreg); \
2328  } while(0)
2329 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
2330  __IO uint32_t tmpreg = 0x00U; \
2331  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
2332  /* Delay after an RCC peripheral clock enabling */ \
2333  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
2334  UNUSED(tmpreg); \
2335  } while(0)
2336 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
2337  __IO uint32_t tmpreg = 0x00U; \
2338  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2339  /* Delay after an RCC peripheral clock enabling */ \
2340  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2341  UNUSED(tmpreg); \
2342  } while(0)
2343 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
2344  __IO uint32_t tmpreg = 0x00U; \
2345  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2346  /* Delay after an RCC peripheral clock enabling */ \
2347  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2348  UNUSED(tmpreg); \
2349  } while(0)
2350 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
2351  __IO uint32_t tmpreg = 0x00U; \
2352  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2353  /* Delay after an RCC peripheral clock enabling */ \
2354  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2355  UNUSED(tmpreg); \
2356  } while(0)
2357 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
2358  __IO uint32_t tmpreg = 0x00U; \
2359  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2360  /* Delay after an RCC peripheral clock enabling */ \
2361  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2362  UNUSED(tmpreg); \
2363  } while(0)
2364 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
2365  __IO uint32_t tmpreg = 0x00U; \
2366  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2367  /* Delay after an RCC peripheral clock enabling */ \
2368  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2369  UNUSED(tmpreg); \
2370  } while(0)
2371 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
2372 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2373 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
2374 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2375 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2376 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
2377 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
2378 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
2379 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
2380 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
2381 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
2382 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
2383 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
2384 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
2385 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
2386 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
2387 
2398 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
2399 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
2400 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
2401 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
2402 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2403 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
2404 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
2405 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
2406 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
2407 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
2408 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
2409 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
2410 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
2411 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
2412 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
2413 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
2414 
2415 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
2416 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
2417 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
2418 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
2419 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
2420 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
2421 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
2422 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
2423 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
2424 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
2425 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
2426 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
2427 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
2428 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
2429 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
2430 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
2431 
2442 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
2443  __IO uint32_t tmpreg = 0x00U; \
2444  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2445  /* Delay after an RCC peripheral clock enabling */ \
2446  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2447  UNUSED(tmpreg); \
2448  } while(0)
2449 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
2450  __IO uint32_t tmpreg = 0x00U; \
2451  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
2452  /* Delay after an RCC peripheral clock enabling */ \
2453  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
2454  UNUSED(tmpreg); \
2455  } while(0)
2456 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
2457  __IO uint32_t tmpreg = 0x00U; \
2458  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
2459  /* Delay after an RCC peripheral clock enabling */ \
2460  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
2461  UNUSED(tmpreg); \
2462  } while(0)
2463 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
2464  __IO uint32_t tmpreg = 0x00U; \
2465  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
2466  /* Delay after an RCC peripheral clock enabling */ \
2467  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
2468  UNUSED(tmpreg); \
2469  } while(0)
2470 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
2471  __IO uint32_t tmpreg = 0x00U; \
2472  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2473  /* Delay after an RCC peripheral clock enabling */ \
2474  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2475  UNUSED(tmpreg); \
2476  } while(0)
2477 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
2478  __IO uint32_t tmpreg = 0x00U; \
2479  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
2480  /* Delay after an RCC peripheral clock enabling */ \
2481  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
2482  UNUSED(tmpreg); \
2483  } while(0)
2484 
2485 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
2486 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
2487 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
2488 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
2489 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
2490 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
2491 
2502 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
2503 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
2504 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
2505 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
2506 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
2507 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
2508 
2509 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
2510 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
2511 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
2512 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
2513 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
2514 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
2515 
2523 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
2524 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
2525 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
2526 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
2527 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
2528 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
2529 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
2530 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
2531 
2532 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
2533 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
2534 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
2535 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
2536 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
2537 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
2538 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
2539 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
2540 
2548 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
2549 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
2550 
2551 #if defined(STM32F407xx)|| defined(STM32F417xx)
2552 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
2553 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
2554 #endif /* STM32F407xx || STM32F417xx */
2555 
2556 #if defined(STM32F415xx) || defined(STM32F417xx)
2557 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
2558 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
2559 
2560 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
2561 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
2562 #endif /* STM32F415xx || STM32F417xx */
2563 
2564 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
2565 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
2566 
2567 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
2568 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
2569 
2577 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
2578 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
2579 
2580 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
2581 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
2582 
2590 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
2591 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
2592 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
2593 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
2594 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
2595 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
2596 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
2597 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
2598 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
2599 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
2600 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
2601 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
2602 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2603 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
2604 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2605 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
2606 
2607 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
2608 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2609 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
2610 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2611 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
2612 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
2613 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
2614 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
2615 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
2616 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
2617 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
2618 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
2619 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
2620 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
2621 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
2622 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
2623 
2631 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
2632 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
2633 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
2634 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
2635 
2636 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
2637 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
2638 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
2639 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
2640 
2652 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
2653 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
2654 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
2655 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
2656 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
2657 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
2658 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
2659 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
2660 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
2661 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
2662 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
2663 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
2664 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
2665 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
2666 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
2667 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
2668 
2669 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
2670 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
2671 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
2672 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
2673 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
2674 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
2675 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
2676 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
2677 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
2678 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
2679 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
2680 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
2681 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
2682 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
2683 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
2684 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
2685 
2697 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
2698 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
2699 
2700 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
2701 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
2702 
2703 #if defined(STM32F407xx)|| defined(STM32F417xx)
2704 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
2705 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
2706 #endif /* STM32F407xx || STM32F417xx */
2707 
2708 #if defined(STM32F415xx) || defined(STM32F417xx)
2709 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
2710 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
2711 
2712 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
2713 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
2714 #endif /* STM32F415xx || STM32F417xx */
2715 
2727 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
2728 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
2729 
2741 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
2742 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
2743 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
2744 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
2745 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
2746 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
2747 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
2748 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
2749 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
2750 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
2751 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
2752 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
2753 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
2754 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
2755 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
2756 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
2757 
2758 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
2759 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
2760 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
2761 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
2762 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
2763 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
2764 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
2765 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
2766 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
2767 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
2768 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
2769 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
2770 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
2771 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
2772 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
2773 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
2774 
2786 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
2787 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
2788 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
2789 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
2790 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
2791 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
2792 
2793 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
2794 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
2795 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
2796 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
2797 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
2798 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
2799 
2802 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
2803 /*----------------------------------------------------------------------------*/
2804 
2805 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/
2806 #if defined(STM32F401xC) || defined(STM32F401xE)
2807 
2814 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
2815  __IO uint32_t tmpreg = 0x00U; \
2816  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2817  /* Delay after an RCC peripheral clock enabling */ \
2818  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2819  UNUSED(tmpreg); \
2820  } while(0)
2821 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
2822  __IO uint32_t tmpreg = 0x00U; \
2823  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2824  /* Delay after an RCC peripheral clock enabling */ \
2825  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
2826  UNUSED(tmpreg); \
2827  } while(0)
2828 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
2829  __IO uint32_t tmpreg = 0x00U; \
2830  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2831  /* Delay after an RCC peripheral clock enabling */ \
2832  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
2833  UNUSED(tmpreg); \
2834  } while(0)
2835 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
2836  __IO uint32_t tmpreg = 0x00U; \
2837  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
2838  /* Delay after an RCC peripheral clock enabling */ \
2839  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
2840  UNUSED(tmpreg); \
2841  } while(0)
2842 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
2843  __IO uint32_t tmpreg = 0x00U; \
2844  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2845  /* Delay after an RCC peripheral clock enabling */ \
2846  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
2847  UNUSED(tmpreg); \
2848  } while(0)
2849 
2850 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
2851 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
2852 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
2853 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
2854 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
2855 
2866 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
2867 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
2868 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
2869 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
2870 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
2871 
2872 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
2873 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
2874 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
2875 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
2876 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
2877 
2888 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
2889  __HAL_RCC_SYSCFG_CLK_ENABLE();\
2890  }while(0)
2891 
2892 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
2893 
2904 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
2905 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
2906 
2917 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
2918  __IO uint32_t tmpreg = 0x00U; \
2919  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2920  /* Delay after an RCC peripheral clock enabling */ \
2921  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
2922  UNUSED(tmpreg); \
2923  } while(0)
2924 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
2925  __IO uint32_t tmpreg = 0x00U; \
2926  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2927  /* Delay after an RCC peripheral clock enabling */ \
2928  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2929  UNUSED(tmpreg); \
2930  } while(0)
2931 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
2932  __IO uint32_t tmpreg = 0x00U; \
2933  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2934  /* Delay after an RCC peripheral clock enabling */ \
2935  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2936  UNUSED(tmpreg); \
2937  } while(0)
2938 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
2939  __IO uint32_t tmpreg = 0x00U; \
2940  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2941  /* Delay after an RCC peripheral clock enabling */ \
2942  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2943  UNUSED(tmpreg); \
2944  } while(0)
2945 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
2946  __IO uint32_t tmpreg = 0x00U; \
2947  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2948  /* Delay after an RCC peripheral clock enabling */ \
2949  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2950  UNUSED(tmpreg); \
2951  } while(0)
2952 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
2953 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2954 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
2955 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2956 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2957 
2968 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
2969 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
2970 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
2971 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
2972 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2973 
2974 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
2975 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
2976 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
2977 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
2978 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
2979 
2990 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
2991  __IO uint32_t tmpreg = 0x00U; \
2992  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
2993  /* Delay after an RCC peripheral clock enabling */ \
2994  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
2995  UNUSED(tmpreg); \
2996  } while(0)
2997 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
2998  __IO uint32_t tmpreg = 0x00U; \
2999  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3000  /* Delay after an RCC peripheral clock enabling */ \
3001  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3002  UNUSED(tmpreg); \
3003  } while(0)
3004 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
3005  __IO uint32_t tmpreg = 0x00U; \
3006  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3007  /* Delay after an RCC peripheral clock enabling */ \
3008  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3009  UNUSED(tmpreg); \
3010  } while(0)
3011 
3012 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
3013 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
3014 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
3015 
3026 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
3027 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
3028 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
3029 
3036 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
3037 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
3038 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
3039 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3040 
3041 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
3042 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
3043 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
3044 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3045 
3053 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
3054 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
3055 
3056 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
3057 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
3058 
3066 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
3067 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
3068 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
3069 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
3070 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
3071 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
3072 
3073 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
3074 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
3075 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
3076 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
3077 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
3078 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
3079 
3087 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
3088 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
3089 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
3090 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
3091 
3092 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
3093 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
3094 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
3095 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
3096 
3104 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
3105 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
3106 
3118 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
3119 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
3120 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3121 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3122 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3123 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
3124 
3125 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
3126 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
3127 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3128 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3129 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3130 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
3131 
3143 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
3144 
3145 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
3146 
3158 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
3159 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
3160 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
3161 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
3162 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
3163 
3164 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
3165 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
3166 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
3167 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
3168 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
3169 
3181 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
3182 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
3183 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
3184 
3185 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
3186 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
3187 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
3188 
3191 #endif /* STM32F401xC || STM32F401xE*/
3192 /*----------------------------------------------------------------------------*/
3193 
3194 /*-------------------------------- STM32F410xx -------------------------------*/
3195 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
3196 
3203 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3204  __IO uint32_t tmpreg = 0x00U; \
3205  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3206  /* Delay after an RCC peripheral clock enabling */ \
3207  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3208  UNUSED(tmpreg); \
3209  } while(0)
3210 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
3211  __IO uint32_t tmpreg = 0x00U; \
3212  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
3213  /* Delay after an RCC peripheral clock enabling */ \
3214  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
3215  UNUSED(tmpreg); \
3216  } while(0)
3217 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
3218 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
3219 
3230 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
3231 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
3232 
3240 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
3241  __IO uint32_t tmpreg = 0x00U; \
3242  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
3243  /* Delay after an RCC peripheral clock enabling */ \
3244  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
3245  UNUSED(tmpreg); \
3246  } while(0)
3247 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
3248  __IO uint32_t tmpreg = 0x00U; \
3249  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
3250  /* Delay after an RCC peripheral clock enabling */ \
3251  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
3252  UNUSED(tmpreg); \
3253  } while(0)
3254 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
3255  __IO uint32_t tmpreg = 0x00U; \
3256  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
3257  /* Delay after an RCC peripheral clock enabling */ \
3258  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
3259  UNUSED(tmpreg); \
3260  } while(0)
3261 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
3262  __IO uint32_t tmpreg = 0x00U; \
3263  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
3264  /* Delay after an RCC peripheral clock enabling */ \
3265  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
3266  UNUSED(tmpreg); \
3267  } while(0)
3268 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
3269  __IO uint32_t tmpreg = 0x00U; \
3270  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
3271  /* Delay after an RCC peripheral clock enabling */ \
3272  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
3273  UNUSED(tmpreg); \
3274  } while(0)
3275 
3276 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
3277 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
3278 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
3279 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
3280 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
3281 
3292 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
3293 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
3294 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
3295 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
3296 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
3297 
3298 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
3299 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
3300 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
3301 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
3302 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
3303 
3311 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
3312  __IO uint32_t tmpreg = 0x00U; \
3313  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3314  /* Delay after an RCC peripheral clock enabling */ \
3315  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3316  UNUSED(tmpreg); \
3317  } while(0)
3318 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
3319  __IO uint32_t tmpreg = 0x00U; \
3320  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
3321  /* Delay after an RCC peripheral clock enabling */ \
3322  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
3323  UNUSED(tmpreg); \
3324  } while(0)
3325 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
3326 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
3327 
3338 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
3339 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
3340 
3341 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
3342 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
3343 
3351 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3352 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
3353 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3354 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
3355 
3363 #define __HAL_RCC_AHB2_FORCE_RESET()
3364 #define __HAL_RCC_AHB2_RELEASE_RESET()
3365 
3373 #define __HAL_RCC_AHB3_FORCE_RESET()
3374 #define __HAL_RCC_AHB3_RELEASE_RESET()
3375 
3383 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
3384 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
3385 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
3386 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
3387 
3388 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
3389 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
3390 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
3391 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
3392 
3400 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
3401 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
3402 
3414 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
3415 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3416 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3417 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3418 
3419 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
3420 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3421 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3422 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3423 
3431 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
3432 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
3433 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
3434 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
3435 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
3436 
3437 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
3438 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
3439 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
3440 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
3441 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
3442 
3450 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
3451 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
3452 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
3453 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
3454 
3458 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
3459 /*----------------------------------------------------------------------------*/
3460 
3461 /*-------------------------------- STM32F411xx -------------------------------*/
3462 #if defined(STM32F411xE)
3463 
3470 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
3471  __IO uint32_t tmpreg = 0x00U; \
3472  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
3473  /* Delay after an RCC peripheral clock enabling */ \
3474  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
3475  UNUSED(tmpreg); \
3476  } while(0)
3477 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
3478  __IO uint32_t tmpreg = 0x00U; \
3479  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3480  /* Delay after an RCC peripheral clock enabling */ \
3481  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3482  UNUSED(tmpreg); \
3483  } while(0)
3484 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
3485  __IO uint32_t tmpreg = 0x00U; \
3486  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3487  /* Delay after an RCC peripheral clock enabling */ \
3488  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3489  UNUSED(tmpreg); \
3490  } while(0)
3491 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
3492  __IO uint32_t tmpreg = 0x00U; \
3493  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3494  /* Delay after an RCC peripheral clock enabling */ \
3495  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3496  UNUSED(tmpreg); \
3497  } while(0)
3498 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3499  __IO uint32_t tmpreg = 0x00U; \
3500  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3501  /* Delay after an RCC peripheral clock enabling */ \
3502  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3503  UNUSED(tmpreg); \
3504  } while(0)
3505 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
3506 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
3507 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
3508 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
3509 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
3510 
3521 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
3522 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
3523 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
3524 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
3525 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
3526 
3527 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
3528 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
3529 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
3530 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
3531 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
3532 
3543 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
3544  __HAL_RCC_SYSCFG_CLK_ENABLE();\
3545  }while(0)
3546 
3547 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
3548 
3559 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
3560 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
3561 
3572 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
3573  __IO uint32_t tmpreg = 0x00U; \
3574  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
3575  /* Delay after an RCC peripheral clock enabling */ \
3576  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
3577  UNUSED(tmpreg); \
3578  } while(0)
3579 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
3580  __IO uint32_t tmpreg = 0x00U; \
3581  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
3582  /* Delay after an RCC peripheral clock enabling */ \
3583  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
3584  UNUSED(tmpreg); \
3585  } while(0)
3586 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
3587  __IO uint32_t tmpreg = 0x00U; \
3588  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
3589  /* Delay after an RCC peripheral clock enabling */ \
3590  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
3591  UNUSED(tmpreg); \
3592  } while(0)
3593 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
3594  __IO uint32_t tmpreg = 0x00U; \
3595  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3596  /* Delay after an RCC peripheral clock enabling */ \
3597  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
3598  UNUSED(tmpreg); \
3599  } while(0)
3600 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
3601  __IO uint32_t tmpreg = 0x00U; \
3602  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3603  /* Delay after an RCC peripheral clock enabling */ \
3604  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
3605  UNUSED(tmpreg); \
3606  } while(0)
3607 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
3608 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
3609 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
3610 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
3611 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
3612 
3623 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
3624 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
3625 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
3626 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
3627 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
3628 
3629 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
3630 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
3631 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
3632 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
3633 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
3634 
3642 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
3643  __IO uint32_t tmpreg = 0x00U; \
3644  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3645  /* Delay after an RCC peripheral clock enabling */ \
3646  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3647  UNUSED(tmpreg); \
3648  } while(0)
3649 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
3650  __IO uint32_t tmpreg = 0x00U; \
3651  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3652  /* Delay after an RCC peripheral clock enabling */ \
3653  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
3654  UNUSED(tmpreg); \
3655  } while(0)
3656 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
3657  __IO uint32_t tmpreg = 0x00U; \
3658  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3659  /* Delay after an RCC peripheral clock enabling */ \
3660  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
3661  UNUSED(tmpreg); \
3662  } while(0)
3663 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
3664  __IO uint32_t tmpreg = 0x00U; \
3665  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3666  /* Delay after an RCC peripheral clock enabling */ \
3667  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
3668  UNUSED(tmpreg); \
3669  } while(0)
3670 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
3671 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
3672 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
3673 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
3674 
3685 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
3686 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
3687 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
3688 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
3689 
3690 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
3691 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
3692 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
3693 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
3694 
3702 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
3703 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
3704 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
3705 
3706 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
3707 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
3708 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
3709 
3717 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
3718 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
3719 
3720 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
3721 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
3722 
3730 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
3731 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
3732 
3740 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
3741 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
3742 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
3743 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
3744 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
3745 
3746 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
3747 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
3748 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
3749 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
3750 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
3751 
3759 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
3760 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
3761 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
3762 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
3763 
3764 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
3765 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
3766 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
3767 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
3768 
3780 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
3781 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
3782 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
3783 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
3784 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
3785 
3786 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
3787 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
3788 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
3789 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
3790 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
3791 
3803 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
3804 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
3805 
3813 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
3814 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
3815 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
3816 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
3817 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
3818 
3819 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
3820 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
3821 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
3822 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
3823 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
3824 
3832 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
3833 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
3834 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
3835 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
3836 
3837 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
3838 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
3839 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
3840 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
3841 
3844 #endif /* STM32F411xE */
3845 /*----------------------------------------------------------------------------*/
3846 
3847 /*---------------------------------- STM32F446xx -----------------------------*/
3848 #if defined(STM32F446xx)
3849 
3856 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
3857  __IO uint32_t tmpreg = 0x00U; \
3858  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
3859  /* Delay after an RCC peripheral clock enabling */ \
3860  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
3861  UNUSED(tmpreg); \
3862  } while(0)
3863 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
3864  __IO uint32_t tmpreg = 0x00U; \
3865  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3866  /* Delay after an RCC peripheral clock enabling */ \
3867  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
3868  UNUSED(tmpreg); \
3869  } while(0)
3870 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
3871  __IO uint32_t tmpreg = 0x00U; \
3872  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3873  /* Delay after an RCC peripheral clock enabling */ \
3874  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
3875  UNUSED(tmpreg); \
3876  } while(0)
3877 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
3878  __IO uint32_t tmpreg = 0x00U; \
3879  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3880  /* Delay after an RCC peripheral clock enabling */ \
3881  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
3882  UNUSED(tmpreg); \
3883  } while(0)
3884 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
3885  __IO uint32_t tmpreg = 0x00U; \
3886  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3887  /* Delay after an RCC peripheral clock enabling */ \
3888  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
3889  UNUSED(tmpreg); \
3890  } while(0)
3891 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
3892  __IO uint32_t tmpreg = 0x00U; \
3893  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
3894  /* Delay after an RCC peripheral clock enabling */ \
3895  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
3896  UNUSED(tmpreg); \
3897  } while(0)
3898 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
3899  __IO uint32_t tmpreg = 0x00U; \
3900  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
3901  /* Delay after an RCC peripheral clock enabling */ \
3902  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
3903  UNUSED(tmpreg); \
3904  } while(0)
3905 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
3906  __IO uint32_t tmpreg = 0x00U; \
3907  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
3908  /* Delay after an RCC peripheral clock enabling */ \
3909  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
3910  UNUSED(tmpreg); \
3911  } while(0)
3912 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
3913  __IO uint32_t tmpreg = 0x00U; \
3914  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
3915  /* Delay after an RCC peripheral clock enabling */ \
3916  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
3917  UNUSED(tmpreg); \
3918  } while(0)
3919 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
3920 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
3921 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
3922 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
3923 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
3924 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
3925 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
3926 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
3927 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
3928 
3939 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
3940 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
3941 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
3942 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
3943 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
3944 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
3945 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
3946 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
3947 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
3948 
3949 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
3950 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
3951 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
3952 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
3953 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
3954 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
3955 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
3956 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
3957 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
3958 
3969 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
3970  __IO uint32_t tmpreg = 0x00U; \
3971  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
3972  /* Delay after an RCC peripheral clock enabling */ \
3973  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
3974  UNUSED(tmpreg); \
3975  } while(0)
3976 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
3977 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
3978  __HAL_RCC_SYSCFG_CLK_ENABLE();\
3979  }while(0)
3980 
3981 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
3982 
3983 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
3984  __IO uint32_t tmpreg = 0x00U; \
3985  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
3986  /* Delay after an RCC peripheral clock enabling */ \
3987  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
3988  UNUSED(tmpreg); \
3989  } while(0)
3990 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
3991 
4002 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
4003 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
4004 
4005 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
4006 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
4007 
4008 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
4009 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
4010 
4021 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
4022  __IO uint32_t tmpreg = 0x00U; \
4023  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
4024  /* Delay after an RCC peripheral clock enabling */ \
4025  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
4026  UNUSED(tmpreg); \
4027  } while(0)
4028 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
4029  __IO uint32_t tmpreg = 0x00U; \
4030  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4031  /* Delay after an RCC peripheral clock enabling */ \
4032  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4033  UNUSED(tmpreg); \
4034  } while(0)
4035 
4036 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
4037 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
4038 
4049 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
4050 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
4051 
4052 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
4053 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
4054 
4065 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
4066  __IO uint32_t tmpreg = 0x00U; \
4067  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4068  /* Delay after an RCC peripheral clock enabling */ \
4069  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4070  UNUSED(tmpreg); \
4071  } while(0)
4072 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
4073  __IO uint32_t tmpreg = 0x00U; \
4074  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4075  /* Delay after an RCC peripheral clock enabling */ \
4076  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4077  UNUSED(tmpreg); \
4078  } while(0)
4079 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
4080  __IO uint32_t tmpreg = 0x00U; \
4081  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4082  /* Delay after an RCC peripheral clock enabling */ \
4083  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4084  UNUSED(tmpreg); \
4085  } while(0)
4086 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
4087  __IO uint32_t tmpreg = 0x00U; \
4088  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4089  /* Delay after an RCC peripheral clock enabling */ \
4090  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4091  UNUSED(tmpreg); \
4092  } while(0)
4093 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
4094  __IO uint32_t tmpreg = 0x00U; \
4095  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4096  /* Delay after an RCC peripheral clock enabling */ \
4097  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4098  UNUSED(tmpreg); \
4099  } while(0)
4100 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
4101  __IO uint32_t tmpreg = 0x00U; \
4102  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
4103  /* Delay after an RCC peripheral clock enabling */ \
4104  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
4105  UNUSED(tmpreg); \
4106  } while(0)
4107 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
4108  __IO uint32_t tmpreg = 0x00U; \
4109  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4110  /* Delay after an RCC peripheral clock enabling */ \
4111  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4112  UNUSED(tmpreg); \
4113  } while(0)
4114 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
4115  __IO uint32_t tmpreg = 0x00U; \
4116  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4117  /* Delay after an RCC peripheral clock enabling */ \
4118  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
4119  UNUSED(tmpreg); \
4120  } while(0)
4121 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
4122  __IO uint32_t tmpreg = 0x00U; \
4123  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4124  /* Delay after an RCC peripheral clock enabling */ \
4125  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
4126  UNUSED(tmpreg); \
4127  } while(0)
4128 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
4129  __IO uint32_t tmpreg = 0x00U; \
4130  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4131  /* Delay after an RCC peripheral clock enabling */ \
4132  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4133  UNUSED(tmpreg); \
4134  } while(0)
4135 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
4136  __IO uint32_t tmpreg = 0x00U; \
4137  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
4138  /* Delay after an RCC peripheral clock enabling */ \
4139  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
4140  UNUSED(tmpreg); \
4141  } while(0)
4142 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
4143  __IO uint32_t tmpreg = 0x00U; \
4144  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
4145  /* Delay after an RCC peripheral clock enabling */ \
4146  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
4147  UNUSED(tmpreg); \
4148  } while(0)
4149 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
4150  __IO uint32_t tmpreg = 0x00U; \
4151  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
4152  /* Delay after an RCC peripheral clock enabling */ \
4153  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
4154  UNUSED(tmpreg); \
4155  } while(0)
4156 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
4157  __IO uint32_t tmpreg = 0x00U; \
4158  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
4159  /* Delay after an RCC peripheral clock enabling */ \
4160  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
4161  UNUSED(tmpreg); \
4162  } while(0)
4163 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
4164  __IO uint32_t tmpreg = 0x00U; \
4165  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
4166  /* Delay after an RCC peripheral clock enabling */ \
4167  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
4168  UNUSED(tmpreg); \
4169  } while(0)
4170 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
4171  __IO uint32_t tmpreg = 0x00U; \
4172  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
4173  /* Delay after an RCC peripheral clock enabling */ \
4174  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
4175  UNUSED(tmpreg); \
4176  } while(0)
4177 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
4178  __IO uint32_t tmpreg = 0x00U; \
4179  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
4180  /* Delay after an RCC peripheral clock enabling */ \
4181  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
4182  UNUSED(tmpreg); \
4183  } while(0)
4184 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
4185  __IO uint32_t tmpreg = 0x00U; \
4186  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
4187  /* Delay after an RCC peripheral clock enabling */ \
4188  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
4189  UNUSED(tmpreg); \
4190  } while(0)
4191 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
4192  __IO uint32_t tmpreg = 0x00U; \
4193  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
4194  /* Delay after an RCC peripheral clock enabling */ \
4195  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
4196  UNUSED(tmpreg); \
4197  } while(0)
4198 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
4199 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
4200 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
4201 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
4202 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
4203 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
4204 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
4205 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
4206 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
4207 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
4208 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
4209 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
4210 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
4211 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
4212 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
4213 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
4214 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
4215 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
4216 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
4217 
4228 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
4229 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
4230 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
4231 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
4232 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
4233 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
4234 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
4235 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
4236 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
4237 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
4238 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
4239 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
4240 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
4241 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
4242 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
4243 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
4244 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
4245 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
4246 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
4247 
4248 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
4249 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
4250 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
4251 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
4252 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
4253 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
4254 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
4255 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
4256 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
4257 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
4258 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
4259 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
4260 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
4261 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
4262 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
4263 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
4264 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
4265 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
4266 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
4267 
4278 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
4279  __IO uint32_t tmpreg = 0x00U; \
4280  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
4281  /* Delay after an RCC peripheral clock enabling */ \
4282  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
4283  UNUSED(tmpreg); \
4284  } while(0)
4285 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
4286  __IO uint32_t tmpreg = 0x00U; \
4287  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
4288  /* Delay after an RCC peripheral clock enabling */ \
4289  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
4290  UNUSED(tmpreg); \
4291  } while(0)
4292 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
4293  __IO uint32_t tmpreg = 0x00U; \
4294  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
4295  /* Delay after an RCC peripheral clock enabling */ \
4296  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
4297  UNUSED(tmpreg); \
4298  } while(0)
4299 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
4300  __IO uint32_t tmpreg = 0x00U; \
4301  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
4302  /* Delay after an RCC peripheral clock enabling */ \
4303  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
4304  UNUSED(tmpreg); \
4305  } while(0)
4306 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
4307  __IO uint32_t tmpreg = 0x00U; \
4308  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
4309  /* Delay after an RCC peripheral clock enabling */ \
4310  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
4311  UNUSED(tmpreg); \
4312  } while(0)
4313 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
4314  __IO uint32_t tmpreg = 0x00U; \
4315  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
4316  /* Delay after an RCC peripheral clock enabling */ \
4317  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
4318  UNUSED(tmpreg); \
4319  } while(0)
4320 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
4321  __IO uint32_t tmpreg = 0x00U; \
4322  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
4323  /* Delay after an RCC peripheral clock enabling */ \
4324  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
4325  UNUSED(tmpreg); \
4326  } while(0)
4327 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
4328  __IO uint32_t tmpreg = 0x00U; \
4329  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
4330  /* Delay after an RCC peripheral clock enabling */ \
4331  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
4332  UNUSED(tmpreg); \
4333  } while(0)
4334 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
4335 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
4336 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
4337 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
4338 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
4339 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
4340 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
4341 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
4342 
4353 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
4354 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
4355 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
4356 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
4357 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
4358 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
4359 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
4360 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
4361 
4362 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
4363 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
4364 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
4365 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
4366 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
4367 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
4368 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
4369 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
4370 
4378 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
4379 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
4380 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
4381 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
4382 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
4383 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
4384 
4385 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
4386 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
4387 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
4388 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
4389 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
4390 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
4391 
4399 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
4400 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
4401 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
4402 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
4403 
4404 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
4405 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
4406 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
4407 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
4408 
4416 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
4417 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
4418 
4419 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
4420 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
4421 
4422 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
4423 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
4424 
4432 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
4433 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
4434 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
4435 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
4436 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
4437 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
4438 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
4439 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
4440 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
4441 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
4442 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
4443 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
4444 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
4445 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
4446 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
4447 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
4448 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
4449 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
4450 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
4451 
4452 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
4453 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
4454 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
4455 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
4456 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
4457 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
4458 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
4459 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
4460 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
4461 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
4462 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
4463 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
4464 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
4465 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
4466 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
4467 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
4468 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
4469 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
4470 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
4471 
4479 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
4480 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
4481 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
4482 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
4483 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
4484 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
4485 
4486 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
4487 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
4488 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
4489 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
4490 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
4491 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
4492 
4504 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
4505 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
4506 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
4507 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
4508 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
4509 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
4510 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
4511 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
4512 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
4513 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
4514 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
4515 
4516 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
4517 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
4518 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
4519 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
4520 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
4521 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
4522 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
4523 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
4524 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
4525 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
4526 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
4527 
4539 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
4540 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
4541 
4542 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
4543 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
4544 
4545 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
4546 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
4547 
4559 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
4560 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
4561 
4562 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
4563 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
4564 
4576 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
4577 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
4578 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
4579 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
4580 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
4581 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
4582 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
4583 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
4584 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
4585 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
4586 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
4587 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
4588 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
4589 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
4590 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
4591 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
4592 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
4593 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
4594 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
4595 
4596 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
4597 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
4598 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
4599 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
4600 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
4601 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
4602 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
4603 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
4604 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
4605 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
4606 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
4607 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
4608 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
4609 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
4610 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
4611 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
4612 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
4613 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
4614 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
4615 
4627 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
4628 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
4629 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
4630 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
4631 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
4632 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
4633 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
4634 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
4635 
4636 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
4637 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
4638 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
4639 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
4640 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
4641 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
4642 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
4643 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
4644 
4648 #endif /* STM32F446xx */
4649 /*----------------------------------------------------------------------------*/
4650 
4651 /*----------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx----------*/
4652 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
4653 
4660 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
4661  __IO uint32_t tmpreg = 0x00U; \
4662  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
4663  /* Delay after an RCC peripheral clock enabling */ \
4664  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
4665  UNUSED(tmpreg); \
4666  } while(0)
4667 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
4668  __IO uint32_t tmpreg = 0x00U; \
4669  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
4670  /* Delay after an RCC peripheral clock enabling */ \
4671  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
4672  UNUSED(tmpreg); \
4673  } while(0)
4674 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
4675  __IO uint32_t tmpreg = 0x00U; \
4676  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
4677  /* Delay after an RCC peripheral clock enabling */ \
4678  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
4679  UNUSED(tmpreg); \
4680  } while(0)
4681 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
4682  __IO uint32_t tmpreg = 0x00U; \
4683  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
4684  /* Delay after an RCC peripheral clock enabling */ \
4685  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
4686  UNUSED(tmpreg); \
4687  } while(0)
4688 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
4689  __IO uint32_t tmpreg = 0x00U; \
4690  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
4691  /* Delay after an RCC peripheral clock enabling */ \
4692  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
4693  UNUSED(tmpreg); \
4694  } while(0)
4695 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
4696  __IO uint32_t tmpreg = 0x00U; \
4697  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
4698  /* Delay after an RCC peripheral clock enabling */ \
4699  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
4700  UNUSED(tmpreg); \
4701  } while(0)
4702 
4703 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
4704 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
4705 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
4706 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
4707 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
4708 
4719 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
4720 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
4721 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
4722 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
4723 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
4724 
4725 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
4726 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
4727 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
4728 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
4729 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
4730 
4741 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
4742  __HAL_RCC_SYSCFG_CLK_ENABLE();\
4743  }while(0)
4744 
4745 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
4746 
4747 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
4748  __IO uint32_t tmpreg = 0x00U; \
4749  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4750  /* Delay after an RCC peripheral clock enabling */ \
4751  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
4752  UNUSED(tmpreg); \
4753  } while(0)
4754 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
4755 
4766 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
4767 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
4768 
4769 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
4770 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
4771 
4782 #if defined(STM32F412Zx) || defined(STM32F412Vx)
4783 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
4784  __IO uint32_t tmpreg = 0x00U; \
4785  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
4786  /* Delay after an RCC peripheral clock enabling */ \
4787  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
4788  UNUSED(tmpreg); \
4789  } while(0)
4790 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
4791  __IO uint32_t tmpreg = 0x00U; \
4792  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4793  /* Delay after an RCC peripheral clock enabling */ \
4794  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4795  UNUSED(tmpreg); \
4796  } while(0)
4797 
4798 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
4799 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
4800 #endif /* STM32F412Zx || STM32F412Vx */
4801 #if defined(STM32F412Rx)
4802 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
4803  __IO uint32_t tmpreg = 0x00U; \
4804  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4805  /* Delay after an RCC peripheral clock enabling */ \
4806  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
4807  UNUSED(tmpreg); \
4808  } while(0)
4809 
4810 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
4811 #endif /* STM32F412Rx */
4812 
4823 #if defined(STM32F412Zx) || defined(STM32F412Vx)
4824 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
4825 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
4826 
4827 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
4828 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
4829 #endif /* STM32F412Zx || STM32F412Vx */
4830 #if defined(STM32F412Rx)
4831 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
4832 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
4833 #endif /* STM32F412Rx */
4834 
4845 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
4846  __IO uint32_t tmpreg = 0x00U; \
4847  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4848  /* Delay after an RCC peripheral clock enabling */ \
4849  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
4850  UNUSED(tmpreg); \
4851  } while(0)
4852 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
4853  __IO uint32_t tmpreg = 0x00U; \
4854  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4855  /* Delay after an RCC peripheral clock enabling */ \
4856  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
4857  UNUSED(tmpreg); \
4858  } while(0)
4859 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
4860  __IO uint32_t tmpreg = 0x00U; \
4861  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4862  /* Delay after an RCC peripheral clock enabling */ \
4863  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
4864  UNUSED(tmpreg); \
4865  } while(0)
4866 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
4867  __IO uint32_t tmpreg = 0x00U; \
4868  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4869  /* Delay after an RCC peripheral clock enabling */ \
4870  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
4871  UNUSED(tmpreg); \
4872  } while(0)
4873 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
4874  __IO uint32_t tmpreg = 0x00U; \
4875  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4876  /* Delay after an RCC peripheral clock enabling */ \
4877  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
4878  UNUSED(tmpreg); \
4879  } while(0)
4880 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
4881  __IO uint32_t tmpreg = 0x00U; \
4882  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
4883  /* Delay after an RCC peripheral clock enabling */ \
4884  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
4885  UNUSED(tmpreg); \
4886  } while(0)
4887 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
4888 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
4889  __IO uint32_t tmpreg = 0x00U; \
4890  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4891  /* Delay after an RCC peripheral clock enabling */ \
4892  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
4893  UNUSED(tmpreg); \
4894  } while(0)
4895 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
4896 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
4897  __IO uint32_t tmpreg = 0x00U; \
4898  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4899  /* Delay after an RCC peripheral clock enabling */ \
4900  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
4901  UNUSED(tmpreg); \
4902  } while(0)
4903 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
4904  __IO uint32_t tmpreg = 0x00U; \
4905  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
4906  /* Delay after an RCC peripheral clock enabling */ \
4907  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
4908  UNUSED(tmpreg); \
4909  } while(0)
4910 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
4911  __IO uint32_t tmpreg = 0x00U; \
4912  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
4913  /* Delay after an RCC peripheral clock enabling */ \
4914  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
4915  UNUSED(tmpreg); \
4916  } while(0)
4917 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
4918  __IO uint32_t tmpreg = 0x00U; \
4919  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
4920  /* Delay after an RCC peripheral clock enabling */ \
4921  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
4922  UNUSED(tmpreg); \
4923  } while(0)
4924 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
4925  __IO uint32_t tmpreg = 0x00U; \
4926  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
4927  /* Delay after an RCC peripheral clock enabling */ \
4928  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
4929  UNUSED(tmpreg); \
4930  } while(0)
4931 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
4932  __IO uint32_t tmpreg = 0x00U; \
4933  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
4934  /* Delay after an RCC peripheral clock enabling */ \
4935  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
4936  UNUSED(tmpreg); \
4937  } while(0)
4938 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
4939  __IO uint32_t tmpreg = 0x00U; \
4940  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
4941  /* Delay after an RCC peripheral clock enabling */ \
4942  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
4943  UNUSED(tmpreg); \
4944  } while(0)
4945 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
4946  __IO uint32_t tmpreg = 0x00U; \
4947  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
4948  /* Delay after an RCC peripheral clock enabling */ \
4949  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
4950  UNUSED(tmpreg); \
4951  } while(0)
4952 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
4953 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
4954 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
4955 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
4956 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
4957 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
4958 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
4959 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
4960 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
4961 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
4962 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
4963 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
4964 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
4965 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
4966 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
4967 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
4968 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
4969 
4980 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
4981 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
4982 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
4983 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
4984 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
4985 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
4986 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
4987 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
4988 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
4989 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
4990 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
4991 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
4992 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
4993 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
4994 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
4995 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
4996 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
4997 
4998 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
4999 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
5000 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
5001 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
5002 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
5003 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
5004 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
5005 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
5006 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
5007 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
5008 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
5009 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
5010 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
5011 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
5012 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
5013 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
5014 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
5015 
5025 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
5026  __IO uint32_t tmpreg = 0x00U; \
5027  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
5028  /* Delay after an RCC peripheral clock enabling */ \
5029  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
5030  UNUSED(tmpreg); \
5031  } while(0)
5032 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
5033  __IO uint32_t tmpreg = 0x00U; \
5034  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
5035  /* Delay after an RCC peripheral clock enabling */ \
5036  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
5037  UNUSED(tmpreg); \
5038  } while(0)
5039 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
5040  __IO uint32_t tmpreg = 0x00U; \
5041  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
5042  /* Delay after an RCC peripheral clock enabling */ \
5043  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
5044  UNUSED(tmpreg); \
5045  } while(0)
5046 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
5047  __IO uint32_t tmpreg = 0x00U; \
5048  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
5049  /* Delay after an RCC peripheral clock enabling */ \
5050  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
5051  UNUSED(tmpreg); \
5052  } while(0)
5053 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
5054  __IO uint32_t tmpreg = 0x00U; \
5055  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
5056  /* Delay after an RCC peripheral clock enabling */ \
5057  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
5058  UNUSED(tmpreg); \
5059  } while(0)
5060 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
5061  __IO uint32_t tmpreg = 0x00U; \
5062  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
5063  /* Delay after an RCC peripheral clock enabling */ \
5064  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
5065  UNUSED(tmpreg); \
5066  } while(0)
5067 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
5068  __IO uint32_t tmpreg = 0x00U; \
5069  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
5070  /* Delay after an RCC peripheral clock enabling */ \
5071  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
5072  UNUSED(tmpreg); \
5073  } while(0)
5074 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
5075 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
5076 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
5077 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
5078 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
5079 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
5080 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
5081 
5092 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
5093 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
5094 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
5095 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
5096 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
5097 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
5098 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
5099 
5100 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
5101 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
5102 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
5103 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
5104 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
5105 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
5106 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
5107 
5115 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
5116 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
5117 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
5118 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
5119 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
5120 
5121 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
5122 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
5123 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
5124 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
5125 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
5126 
5134 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
5135 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
5136 
5137 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
5138 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
5139 
5140 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
5141 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
5142 
5150 #if defined(STM32F412Zx) || defined(STM32F412Vx)
5151 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
5152 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
5153 
5154 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
5155 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
5156 
5157 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
5158 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
5159 #endif /* STM32F412Zx || STM32F412Vx */
5160 #if defined(STM32F412Cx)
5161 #define __HAL_RCC_AHB3_FORCE_RESET()
5162 #define __HAL_RCC_AHB3_RELEASE_RESET()
5163 
5164 #define __HAL_RCC_FSMC_FORCE_RESET()
5165 #define __HAL_RCC_QSPI_FORCE_RESET()
5166 
5167 #define __HAL_RCC_FSMC_RELEASE_RESET()
5168 #define __HAL_RCC_QSPI_RELEASE_RESET()
5169 #endif /* STM32F412Cx */
5170 #if defined(STM32F412Rx)
5171 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
5172 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
5173 
5174 #define __HAL_RCC_FSMC_FORCE_RESET()
5175 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
5176 
5177 #define __HAL_RCC_FSMC_RELEASE_RESET()
5178 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
5179 #endif /* STM32F412Rx */
5180 
5188 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
5189 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
5190 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
5191 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
5192 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
5193 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
5194 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
5195 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
5196 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
5197 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
5198 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
5199 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
5200 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
5201 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
5202 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
5203 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
5204 
5205 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
5206 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
5207 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
5208 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
5209 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
5210 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
5211 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
5212 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
5213 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
5214 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
5215 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
5216 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
5217 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
5218 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
5219 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
5220 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
5221 
5229 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
5230 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
5231 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
5232 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
5233 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
5234 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
5235 
5236 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
5237 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
5238 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
5239 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
5240 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
5241 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
5242 
5254 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
5255 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
5256 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
5257 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
5258 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
5259 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
5260 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
5261 
5262 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
5263 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
5264 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
5265 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
5266 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
5267 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
5268 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
5269 
5281 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
5282 
5283 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
5284 
5285 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
5286 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
5287 
5299 #if defined(STM32F412Zx) || defined(STM32F412Vx)
5300 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
5301 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
5302 
5303 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
5304 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
5305 #endif /* STM32F412Zx || STM32F412Vx */
5306 
5307 #if defined(STM32F412Rx)
5308 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
5309 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
5310 #endif /* STM32F412Rx */
5311 
5323 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
5324 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
5325 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
5326 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
5327 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
5328 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
5329 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
5330 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
5331 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
5332 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
5333 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
5334 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
5335 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
5336 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
5337 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
5338 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
5339 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
5340 
5341 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
5342 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
5343 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
5344 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
5345 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
5346 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
5347 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
5348 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
5349 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
5350 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
5351 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
5352 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
5353 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
5354 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
5355 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
5356 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
5357 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
5358 
5370 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
5371 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
5372 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))
5373 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
5374 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
5375 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
5376 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
5377 
5378 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
5379 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
5380 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
5381 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
5382 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
5383 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
5384 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
5385 
5388 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
5389 /*----------------------------------------------------------------------------*/
5390 
5391 /*------------------------------- PLL Configuration --------------------------*/
5392 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
5393  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
5394  defined(STM32F412Rx) || defined(STM32F412Cx)
5395 
5428 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
5429  (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
5430  ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
5431  ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
5432  ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
5433  ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
5434 #else
5435 
5464 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
5465  (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
5466  ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
5467  ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
5468  ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
5469  #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
5470 /*----------------------------------------------------------------------------*/
5471 
5472 /*----------------------------PLLI2S Configuration ---------------------------*/
5473 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
5474  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
5475  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
5476  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
5477  defined(STM32F412Rx) || defined(STM32F412Cx)
5478 
5482 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
5483 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
5484 
5485 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
5486  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
5487  STM32F412Rx || STM32F412Cx */
5488 #if defined(STM32F446xx)
5489 
5516 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
5517  (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5518  ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
5519  ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
5520  ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
5521  ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
5522 #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
5523 
5546 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
5547  (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5548  ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
5549  ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
5550  ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
5551 #else
5552 
5567 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
5568  (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
5569  ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
5570 #endif /* STM32F446xx */
5571 
5572 #if defined(STM32F411xE)
5573 
5593 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
5594  ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
5595  ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
5596 #endif /* STM32F411xE */
5597 
5598 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
5599 
5616 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) |\
5617  ((__PLLI2SQ__) << 24) |\
5618  ((__PLLI2SR__) << 28))
5619 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
5620 /*----------------------------------------------------------------------------*/
5621 
5622 /*------------------------------ PLLSAI Configuration ------------------------*/
5623 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
5624 
5628 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
5629 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
5630 
5631 #if defined(STM32F446xx)
5632 
5657 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
5658  (RCC->PLLSAICFGR = ((__PLLSAIM__) | \
5659  ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
5660  ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \
5661  ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
5662 #endif /* STM32F446xx */
5663 
5664 #if defined(STM32F469xx) || defined(STM32F479xx)
5665 
5681 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
5682  (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
5683  ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
5684  ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
5685  ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
5686 #endif /* STM32F469xx || STM32F479xx */
5687 
5688 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
5689 
5703 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
5704  (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
5705  ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) | \
5706  ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
5707 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
5708 
5709 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
5710 /*----------------------------------------------------------------------------*/
5711 
5712 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
5713 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
5714  defined(STM32F469xx) || defined(STM32F479xx)
5715 
5721 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
5722 
5729 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
5730 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
5731 
5732 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
5733 
5741 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
5742 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
5743 /*----------------------------------------------------------------------------*/
5744 
5745 /*------------------------- Peripheral Clock selection -----------------------*/
5746 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
5747  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
5748  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
5749  defined(STM32F479xx)
5750 
5758 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
5759 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
5760 
5761 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
5762 
5776 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
5777 
5791 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
5792 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
5793 
5794 #if defined(STM32F446xx)
5795 
5806 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
5807 
5816 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
5817 
5829 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
5830 
5839 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
5840 
5850 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
5851 
5859 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
5860 
5870 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
5871 
5879 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
5880 
5887 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
5888 
5894 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
5895 
5903 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
5904 
5911 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
5912 
5919 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
5920 
5926 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
5927 
5934 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
5935 
5941 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
5942 
5949 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
5950 
5956 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
5957 #endif /* STM32F446xx */
5958 
5959 #if defined(STM32F469xx) || defined(STM32F479xx)
5960 
5967 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
5968 
5974 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
5975 
5982 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
5983 
5989 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
5990 
5997 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
5998 
6004 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
6005 
6006 #endif /* STM32F469xx || STM32F479xx */
6007 
6008 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
6009 
6016 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
6017 
6023 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
6024 
6032 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
6033 
6040 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
6041 
6050 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
6051 
6059 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
6060 
6069 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
6070 
6078 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
6079 
6088 #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
6089 
6097 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
6098 
6105 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
6106 
6113 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
6114 
6120 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
6121 
6128 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
6129 
6135 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
6136 
6137 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6138 
6139 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6140 
6147 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
6148 
6155 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
6156 
6164 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
6165 
6172 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
6173 
6182 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
6183 
6191 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
6192 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6193 
6194 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6195  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
6196  defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
6197  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
6198  defined(STM32F412Cx)
6199 
6212 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
6213 
6214 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
6215  STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6216 
6217 /*----------------------------------------------------------------------------*/
6218 
6219 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6220 
6222 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
6223 
6226 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
6227 
6230 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
6231 
6235 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
6236 
6240 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
6241 
6242 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6243 
6244 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6245 
6247 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
6248 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
6249 
6252 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
6253 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
6254 
6255 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6256 
6261 /* Exported functions --------------------------------------------------------*/
6269 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
6270 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
6271 
6272 #if defined(STM32F446xx)
6273 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
6274 #endif /* STM32F446xx */
6275 
6276 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
6277  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
6278  defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
6279 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
6280 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6281 
6288 /* Private types -------------------------------------------------------------*/
6289 /* Private variables ---------------------------------------------------------*/
6290 /* Private constants ---------------------------------------------------------*/
6299 /* --- CR Register ---*/
6300 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6301  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6302 /* Alias word address of PLLSAION bit */
6303 #define RCC_PLLSAION_BIT_NUMBER 0x1C
6304 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
6305 
6306 #define PLLSAI_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
6307 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6308 
6309 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
6310  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
6311  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
6312  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
6313  defined(STM32F412Rx) || defined(STM32F412Cx)
6314 /* Alias word address of PLLI2SON bit */
6315 #define RCC_PLLI2SON_BIT_NUMBER 0x1A
6316 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
6317 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
6318  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
6319  STM32F412Rx || STM32F412Cx */
6320 
6321 /* --- DCKCFGR Register ---*/
6322 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
6323  defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
6324  defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
6325  defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
6326  defined(STM32F412Cx)
6327 /* Alias word address of TIMPRE bit */
6328 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
6329 #define RCC_TIMPRE_BIT_NUMBER 0x18
6330 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
6331 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
6332  STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
6333  STM32F412Vx || STM32F412Rx || STM32F412Cx */
6334 
6335 /* --- CFGR Register ---*/
6336 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
6337 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
6338  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
6339  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
6340  defined(STM32F469xx) || defined(STM32F479xx)
6341 /* Alias word address of I2SSRC bit */
6342 #define RCC_I2SSRC_BIT_NUMBER 0x17
6343 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
6344 
6345 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
6346 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
6347  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
6348 
6349 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
6350 /* --- PLLI2SCFGR Register ---*/
6351 #define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
6352 /* Alias word address of PLLI2SSRC bit */
6353 #define RCC_PLLI2SSRC_BIT_NUMBER 0x16
6354 #define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32) + (RCC_PLLI2SSRC_BIT_NUMBER * 4))
6355 
6356 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
6357 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6358 
6359 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6360 /* Alias word address of MCO1EN bit */
6361 #define RCC_MCO1EN_BIT_NUMBER 0x8
6362 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
6363 
6364 /* Alias word address of MCO2EN bit */
6365 #define RCC_MCO2EN_BIT_NUMBER 0x9
6366 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
6367 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6368 
6369 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
6370 
6378 /* Private macros ------------------------------------------------------------*/
6385 #if defined(STM32F411xE)
6386 #define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
6387 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
6388 #else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
6389  STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx ||
6390  STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx ||
6391  STM32F412Vx || STM32F412Zx */
6392 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6393 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6394 #endif /* STM32F411xE */
6395 
6396 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
6397 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
6398 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
6399 
6400 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
6401 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
6402 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
6403 
6404 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
6405 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
6406 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
6407 
6408 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6409 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
6410 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6411 
6412 #if defined(STM32F446xx)
6413 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
6414 #endif /* STM32F446xx */
6415 
6416 #if defined(STM32F469xx) || defined(STM32F479xx)
6417 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
6418 #endif /* STM32F469xx || STM32F479xx */
6419 
6420 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
6421 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
6422 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6423 
6424 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6425 
6426 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
6427  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
6428 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
6429 
6430 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
6431 
6432 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
6433 
6434 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6435 
6436 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
6437 
6438 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
6439 
6440 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
6441  ((VALUE) == RCC_PLLSAIDIVR_4) ||\
6442  ((VALUE) == RCC_PLLSAIDIVR_8) ||\
6443  ((VALUE) == RCC_PLLSAIDIVR_16))
6444 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
6445 
6446 #if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
6447  defined(STM32F412Rx) || defined(STM32F412Cx)
6448 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63U)
6449 
6450 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
6451  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
6452 #endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6453 
6454 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6455 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6456 
6457 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
6458  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
6459 
6460 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) ||\
6461  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
6462  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
6463 
6464 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) ||\
6465  ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
6466  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
6467  ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
6468 
6469 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\
6470  ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\
6471  ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
6472 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6473 
6474 #if defined(STM32F446xx)
6475 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6476 
6477 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
6478  ((VALUE) == RCC_PLLI2SP_DIV4) ||\
6479  ((VALUE) == RCC_PLLI2SP_DIV6) ||\
6480  ((VALUE) == RCC_PLLI2SP_DIV8))
6481 
6482 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
6483 
6484 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
6485  ((VALUE) == RCC_PLLSAIP_DIV4) ||\
6486  ((VALUE) == RCC_PLLSAIP_DIV6) ||\
6487  ((VALUE) == RCC_PLLSAIP_DIV8))
6488 
6489 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
6490  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
6491  ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\
6492  ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
6493 
6494 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
6495  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
6496  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\
6497  ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
6498 
6499 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
6500  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
6501  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
6502  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
6503 
6504  #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
6505  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
6506  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
6507  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
6508 
6509 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) ||\
6510  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
6511  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
6512 
6513 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\
6514  ((SOURCE) == RCC_CECCLKSOURCE_LSE))
6515 
6516 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
6517  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
6518 
6519 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
6520  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
6521 
6522 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
6523  ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
6524 #endif /* STM32F446xx */
6525 
6526 #if defined(STM32F469xx) || defined(STM32F479xx)
6527 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6528 
6529 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
6530  ((VALUE) == RCC_PLLSAIP_DIV4) ||\
6531  ((VALUE) == RCC_PLLSAIP_DIV6) ||\
6532  ((VALUE) == RCC_PLLSAIP_DIV8))
6533 
6534 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
6535  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
6536 
6537 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
6538  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
6539 
6540 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
6541  ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
6542 
6543 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
6544  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
6545 #endif /* STM32F469xx || STM32F479xx */
6546 
6547 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
6548 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
6549 
6550 #define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
6551  ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
6552 
6553 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
6554  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
6555  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
6556  ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
6557 
6558  #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
6559  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
6560  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
6561  ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
6562 
6563 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) ||\
6564  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
6565  ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
6566 
6567 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
6568  ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
6569 
6570 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
6571  ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
6572 
6573 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_APB2) || \
6574  ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
6575 
6576 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || \
6577  ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
6578 
6579 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
6580 
6581 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
6582  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
6583  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
6584  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
6585  defined(STM32F412Rx)
6586 
6587 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
6588  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
6589 
6590 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
6591  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
6592  STM32F412Rx */
6593 
6594 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
6595 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
6596  ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
6597 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
6598 
6613 #ifdef __cplusplus
6614 }
6615 #endif
6616 
6617 #endif /* __STM32F4xx_HAL_RCC_EX_H */
6618 
6619 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_PLLInitTypeDef::PLLState
uint32_t PLLState
Definition: stm32f4xx_hal_rcc_ex.h:67
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
RCC_PLLInitTypeDef::PLLP
uint32_t PLLP
Definition: stm32f4xx_hal_rcc_ex.h:80
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f4xx_hal_rcc_ex.h:65
RCC_PLLInitTypeDef::PLLM
uint32_t PLLM
Definition: stm32f4xx_hal_rcc_ex.h:73
RCC_PLLInitTypeDef::PLLQ
uint32_t PLLQ
Definition: stm32f4xx_hal_rcc_ex.h:83
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
RCC_PLLInitTypeDef::PLLN
uint32_t PLLN
Definition: stm32f4xx_hal_rcc_ex.h:76
RCC_PLLInitTypeDef::PLLSource
uint32_t PLLSource
Definition: stm32f4xx_hal_rcc_ex.h:70