39 #ifndef __STM32F4xx_HAL_UART_H 40 #define __STM32F4xx_HAL_UART_H 207 #define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) 208 #define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) 209 #define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) 210 #define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) 211 #define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) 212 #define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) 220 #define UART_WORDLENGTH_8B ((uint32_t)0x00000000U) 221 #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) 229 #define UART_STOPBITS_1 ((uint32_t)0x00000000U) 230 #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) 238 #define UART_PARITY_NONE ((uint32_t)0x00000000U) 239 #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) 240 #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 248 #define UART_HWCONTROL_NONE ((uint32_t)0x00000000U) 249 #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) 250 #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) 251 #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) 259 #define UART_MODE_RX ((uint32_t)USART_CR1_RE) 260 #define UART_MODE_TX ((uint32_t)USART_CR1_TE) 261 #define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) 269 #define UART_STATE_DISABLE ((uint32_t)0x00000000U) 270 #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) 278 #define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U) 279 #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) 287 #define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000U) 288 #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020U) 296 #define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000U) 297 #define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)0x00000800U) 307 #define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) 308 #define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) 309 #define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) 310 #define UART_FLAG_TC ((uint32_t)USART_SR_TC) 311 #define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) 312 #define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) 313 #define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) 314 #define UART_FLAG_NE ((uint32_t)USART_SR_NE) 315 #define UART_FLAG_FE ((uint32_t)USART_SR_FE) 316 #define UART_FLAG_PE ((uint32_t)USART_SR_PE) 332 #define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) 333 #define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) 334 #define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) 335 #define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) 336 #define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) 338 #define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) 340 #define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) 341 #define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) 361 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ 362 (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ 363 (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ 369 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) 390 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) 414 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 422 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ 424 __IO uint32_t tmpreg = 0x00U; \ 425 tmpreg = (__HANDLE__)->Instance->SR; \ 426 tmpreg = (__HANDLE__)->Instance->DR; \ 436 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) 444 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) 452 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) 460 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) 478 #define UART_IT_MASK ((uint32_t)0x0000FFFFU) 479 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ 480 (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ 481 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) 498 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ 499 (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ 500 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) 517 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \ 518 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) 533 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ 535 SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ 536 (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ 552 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ 554 CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ 555 (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ 571 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ 573 SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ 574 (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ 590 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ 592 CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ 593 (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ 600 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) 606 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) 612 #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) 618 #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) 702 #define UART_CR1_REG_INDEX 1U 703 #define UART_CR2_REG_INDEX 2U 704 #define UART_CR3_REG_INDEX 3U 713 #define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ 714 ((LENGTH) == UART_WORDLENGTH_9B)) 715 #define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) 716 #define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ 717 ((STOPBITS) == UART_STOPBITS_2)) 718 #define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ 719 ((PARITY) == UART_PARITY_EVEN) || \ 720 ((PARITY) == UART_PARITY_ODD)) 721 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ 722 (((CONTROL) == UART_HWCONTROL_NONE) || \ 723 ((CONTROL) == UART_HWCONTROL_RTS) || \ 724 ((CONTROL) == UART_HWCONTROL_CTS) || \ 725 ((CONTROL) == UART_HWCONTROL_RTS_CTS)) 726 #define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3U) == 0x00U) && ((MODE) != (uint32_t)0x00U)) 727 #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ 728 ((STATE) == UART_STATE_ENABLE)) 729 #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ 730 ((SAMPLING) == UART_OVERSAMPLING_8)) 731 #define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) 732 #define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ 733 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) 734 #define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ 735 ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) 736 #define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U) 737 #define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) 739 #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) 740 #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) 741 #define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) 744 #define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ 745 (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \ 746 (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) 748 #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) 749 #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) 750 #define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U) 753 #define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ 754 ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ 755 (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) uint32_t OverSampling
Definition: stm32f4xx_hal_uart.h:93
uint8_t * pRxBuffPtr
Definition: stm32f4xx_hal_uart.h:172
uint32_t WordLength
Definition: stm32f4xx_hal_uart.h:73
Definition: stm32f4xx_hal_uart.h:148
uint16_t RxXferSize
Definition: stm32f4xx_hal_uart.h:174
This file contains HAL common defines, enumeration, macros and structures definitions.
DMA_HandleTypeDef * hdmatx
Definition: stm32f4xx_hal_uart.h:178
uint32_t HwFlowCtl
Definition: stm32f4xx_hal_uart.h:89
uint16_t TxXferSize
Definition: stm32f4xx_hal_uart.h:168
__IO HAL_UART_StateTypeDef gState
Definition: stm32f4xx_hal_uart.h:184
uint16_t RxXferCount
Definition: stm32f4xx_hal_uart.h:176
DMA_HandleTypeDef * hdmarx
Definition: stm32f4xx_hal_uart.h:180
UART_InitTypeDef Init
Definition: stm32f4xx_hal_uart.h:164
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
#define __IO
Definition: core_cm0.h:213
USART_TypeDef * Instance
Definition: stm32f4xx_hal_uart.h:162
Definition: stm32f4xx_hal_uart.h:140
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
__IO HAL_UART_StateTypeDef RxState
Definition: stm32f4xx_hal_uart.h:188
Definition: stm32f4xx_hal_uart.h:153
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:68
uint32_t StopBits
Definition: stm32f4xx_hal_uart.h:76
Definition: stm32f4xx_hal_uart.h:144
uint32_t Parity
Definition: stm32f4xx_hal_uart.h:79
uint32_t Mode
Definition: stm32f4xx_hal_uart.h:86
Definition: stm32f4xx_hal_uart.h:142
HAL_UART_StateTypeDef
HAL UART State structures definition.
Definition: stm32f4xx_hal_uart.h:136
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:157
uint8_t * pTxBuffPtr
Definition: stm32f4xx_hal_uart.h:166
Definition: stm32f4xx_hal_uart.h:151
__IO uint32_t ErrorCode
Definition: stm32f4xx_hal_uart.h:191
Definition: stm32f4xx_hal_uart.h:138
UART Init Structure definition.
Definition: stm32f4xx_hal_uart.h:65
HAL_LockTypeDef Lock
Definition: stm32f4xx_hal_uart.h:182
uint16_t TxXferCount
Definition: stm32f4xx_hal_uart.h:170
Definition: stm32f4xx_hal_uart.h:146
UART handle Structure definition.
Definition: stm32f4xx_hal_uart.h:160
uint32_t BaudRate
Definition: stm32f4xx_hal_uart.h:67