STM CMSIS
stm32f4xx_ll_fmc.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_FMC_H
40 #define __STM32F4xx_LL_FMC_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48 
56 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
57  defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
58 /* Private types -------------------------------------------------------------*/
66 typedef struct
67 {
68  uint32_t NSBank;
71  uint32_t DataAddressMux;
75  uint32_t MemoryType;
79  uint32_t MemoryDataWidth;
82  uint32_t BurstAccessMode;
86  uint32_t WaitSignalPolarity;
90  uint32_t WrapMode;
95  uint32_t WaitSignalActive;
100  uint32_t WriteOperation;
103  uint32_t WaitSignal;
107  uint32_t ExtendedMode;
110  uint32_t AsynchronousWait;
114  uint32_t WriteBurst;
117  uint32_t ContinuousClock;
122  uint32_t WriteFifo;
128  uint32_t PageSize;
130 }FMC_NORSRAM_InitTypeDef;
131 
135 typedef struct
136 {
137  uint32_t AddressSetupTime;
142  uint32_t AddressHoldTime;
147  uint32_t DataSetupTime;
153  uint32_t BusTurnAroundDuration;
158  uint32_t CLKDivision;
163  uint32_t DataLatency;
171  uint32_t AccessMode;
173 }FMC_NORSRAM_TimingTypeDef;
174 
178 typedef struct
179 {
180  uint32_t NandBank;
183  uint32_t Waitfeature;
186  uint32_t MemoryDataWidth;
189  uint32_t EccComputation;
192  uint32_t ECCPageSize;
195  uint32_t TCLRSetupTime;
199  uint32_t TARSetupTime;
202 }FMC_NAND_InitTypeDef;
203 
207 typedef struct
208 {
209  uint32_t SetupTime;
215  uint32_t WaitSetupTime;
221  uint32_t HoldSetupTime;
228  uint32_t HiZSetupTime;
233 }FMC_NAND_PCC_TimingTypeDef;
234 
238 typedef struct
239 {
240  uint32_t Waitfeature;
243  uint32_t TCLRSetupTime;
247  uint32_t TARSetupTime;
250 }FMC_PCCARD_InitTypeDef;
251 
255 typedef struct
256 {
257  uint32_t SDBank;
260  uint32_t ColumnBitsNumber;
263  uint32_t RowBitsNumber;
266  uint32_t MemoryDataWidth;
269  uint32_t InternalBankNumber;
272  uint32_t CASLatency;
275  uint32_t WriteProtection;
278  uint32_t SDClockPeriod;
282  uint32_t ReadBurst;
286  uint32_t ReadPipeDelay;
288 }FMC_SDRAM_InitTypeDef;
289 
293 typedef struct
294 {
295  uint32_t LoadToActiveDelay;
299  uint32_t ExitSelfRefreshDelay;
303  uint32_t SelfRefreshTime;
307  uint32_t RowCycleDelay;
312  uint32_t WriteRecoveryTime;
315  uint32_t RPDelay;
319  uint32_t RCDDelay;
322 }FMC_SDRAM_TimingTypeDef;
323 
327 typedef struct
328 {
329  uint32_t CommandMode;
332  uint32_t CommandTarget;
335  uint32_t AutoRefreshNumber;
338  uint32_t ModeRegisterDefinition;
339 }FMC_SDRAM_CommandTypeDef;
344 /* Private constants ---------------------------------------------------------*/
355 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
356 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
357 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
358 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
359 
366 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
367 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
368 
375 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
376 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
377 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
378 
385 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
386 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
387 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
388 
395 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
396 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
397 
404 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
405 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
406 
413 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
414 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
415 
424 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
425 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
426 
433 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
434 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
435 
442 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
443 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
444 
451 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
452 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
453 
460 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
461 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
462 
469 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
470 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
471 
478 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
479 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
480 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
481 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
482 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
483 
491 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
492 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
493 
500 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
501 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
502 
509 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
510 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
511 
518 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
519 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
520 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
521 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
522 
536 #define FMC_NAND_BANK2 ((uint32_t)0x00000010U)
537 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
538 
545 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
546 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
547 
554 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
555 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
556 
563 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
564 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
565 
572 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
573 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
574 
581 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
582 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
583 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
584 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
585 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
586 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
587 
601 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
602 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
603 
610 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
611 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
612 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
613 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
614 
621 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
622 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
623 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
624 
631 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
632 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
633 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
634 
641 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
642 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
643 
650 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
651 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
652 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U)
653 
660 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
661 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
662 
670 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
671 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
672 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U)
673 
680 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
681 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
682 
689 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
690 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
691 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
692 
699 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
700 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
701 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
702 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
703 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
704 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
705 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
706 
713 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
714 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
715 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
716 
723 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
724 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
725 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
726 
737 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
738 #define FMC_IT_LEVEL ((uint32_t)0x00000010U)
739 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
740 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
741 
748 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
749 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
750 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
751 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
752 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
753 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
754 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
755 
762 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
763  #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
764 #else
765  #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
766  #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
767 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
768  #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
769  #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
770  #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
771 
772 
773 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
774  #define FMC_NAND_DEVICE FMC_Bank3
775 #else
776  #define FMC_NAND_DEVICE FMC_Bank2_3
777  #define FMC_PCCARD_DEVICE FMC_Bank4
778 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
779  #define FMC_NORSRAM_DEVICE FMC_Bank1
780  #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
781  #define FMC_SDRAM_DEVICE FMC_Bank5_6
782 
790 /* Private macro -------------------------------------------------------------*/
805 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
806 
813 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
814 
822 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
823 
829 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
830 
837 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
838 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
839 
845 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
846  ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
847 
854 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
855  ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
856 
857 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
858 
861 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
862 
871 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
872 
878 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
879 
882 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
883 
888 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
889 
900 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
901 
913 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
914 
927 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
928 
940 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
941 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
942 
953 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
954  ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
955 
967 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
968  ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
969 
982 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
983  (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
984 
996 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
997  ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
998 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
999 
1000 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1001 
1011 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
1012 
1023 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
1024 
1036 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
1037 
1049 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
1050 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
1051 
1060 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1061 
1070 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1071 
1082 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1083 
1092 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1093 
1100 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
1101  ((BANK) == FMC_NORSRAM_BANK2) || \
1102  ((BANK) == FMC_NORSRAM_BANK3) || \
1103  ((BANK) == FMC_NORSRAM_BANK4))
1104 
1105 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
1106  ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
1107 
1108 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
1109  ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
1110  ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
1111 
1112 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
1113  ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
1114  ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
1115 
1116 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
1117  ((__MODE__) == FMC_ACCESS_MODE_B) || \
1118  ((__MODE__) == FMC_ACCESS_MODE_C) || \
1119  ((__MODE__) == FMC_ACCESS_MODE_D))
1120 
1121 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
1122  ((BANK) == FMC_NAND_BANK3))
1123 
1124 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
1125  ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
1126 
1127 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
1128  ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
1129 
1130 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
1131  ((STATE) == FMC_NAND_ECC_ENABLE))
1132 
1133 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
1134  ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
1135  ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
1136  ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
1137  ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
1138  ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
1139 
1140 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
1141 
1142 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
1143 
1144 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
1145 
1146 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
1147 
1148 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
1149 
1150 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
1151 
1152 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
1153 
1154 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
1155 
1156 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
1157 
1158 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
1159 
1160 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
1161  ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
1162 
1163 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
1164  ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
1165 
1166 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1167 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
1168  ((__MODE__) == FMC_WRAP_MODE_ENABLE))
1169 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1170 
1171 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
1172  ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
1173 
1174 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
1175  ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
1176 
1177 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
1178  ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
1179 
1180 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
1181  ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
1182 
1183 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
1184  ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
1185 
1186 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
1187  ((__BURST__) == FMC_WRITE_BURST_ENABLE))
1188 
1189 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
1190  ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
1191 
1192 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
1193 
1194 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
1195 
1196 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
1197 
1198 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
1199 
1200 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
1201 
1202 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
1203 
1204 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
1205  ((BANK) == FMC_SDRAM_BANK2))
1206 
1207 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
1208  ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
1209  ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
1210  ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
1211 
1212 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
1213  ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
1214  ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
1215 
1216 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
1217  ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
1218  ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
1219 
1220 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
1221  ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
1222 
1223 
1224 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
1225  ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
1226  ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
1227 
1228 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
1229  ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
1230  ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
1231 
1232 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
1233  ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
1234 
1235 
1236 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
1237  ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
1238  ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
1239 
1240 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1241 
1242 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1243 
1244 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
1245 
1246 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1247 
1248 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
1249 
1250 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1251 
1252 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
1253 
1254 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
1255  ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
1256  ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
1257  ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
1258  ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
1259  ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
1260  ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
1261 
1262 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
1263  ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
1264  ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
1265 
1266 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
1267 
1268 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
1269 
1270 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
1271 
1272 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
1273 
1274 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
1275  ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
1276 
1277 #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
1278  ((SIZE) == FMC_PAGE_SIZE_128) || \
1279  ((SIZE) == FMC_PAGE_SIZE_256) || \
1280  ((SIZE) == FMC_PAGE_SIZE_512) || \
1281  ((SIZE) == FMC_PAGE_SIZE_1024))
1282 
1283 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
1284 #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
1285  ((FIFO) == FMC_WRITE_FIFO_ENABLE))
1286 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
1287 
1296 /* Private functions ---------------------------------------------------------*/
1307 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1308 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1309 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1310 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1318 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1319 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1333 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1334 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1335 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1336 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1344 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1345 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1346 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1347 
1354 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1355 
1361 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
1362 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1363 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1364 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1365 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1372 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1373 
1380 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1381 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1382 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1390 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1391 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1392 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1393 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1394 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1395 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1407 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
1408 
1415 #ifdef __cplusplus
1416 }
1417 #endif
1418 
1419 #endif /* __STM32F4xx_LL_FMC_H */
1420 
1421 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57