STM CMSIS
stm32f4xx_ll_fsmc.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_FSMC_H
40 #define __STM32F4xx_LL_FSMC_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48 
57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
58 /* Private types -------------------------------------------------------------*/
66 typedef struct
67 {
68  uint32_t NSBank;
71  uint32_t DataAddressMux;
75  uint32_t MemoryType;
79  uint32_t MemoryDataWidth;
82  uint32_t BurstAccessMode;
86  uint32_t WaitSignalPolarity;
90  uint32_t WrapMode;
95  uint32_t WaitSignalActive;
100  uint32_t WriteOperation;
103  uint32_t WaitSignal;
107  uint32_t ExtendedMode;
110  uint32_t AsynchronousWait;
114  uint32_t WriteBurst;
117  uint32_t ContinuousClock;
123  uint32_t WriteFifo;
129  uint32_t PageSize;
131 }FSMC_NORSRAM_InitTypeDef;
132 
136 typedef struct
137 {
138  uint32_t AddressSetupTime;
143  uint32_t AddressHoldTime;
148  uint32_t DataSetupTime;
154  uint32_t BusTurnAroundDuration;
159  uint32_t CLKDivision;
164  uint32_t DataLatency;
172  uint32_t AccessMode;
175 }FSMC_NORSRAM_TimingTypeDef;
176 
177 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
178 
181 typedef struct
182 {
183  uint32_t NandBank;
186  uint32_t Waitfeature;
189  uint32_t MemoryDataWidth;
192  uint32_t EccComputation;
195  uint32_t ECCPageSize;
198  uint32_t TCLRSetupTime;
202  uint32_t TARSetupTime;
206 }FSMC_NAND_InitTypeDef;
207 
211 typedef struct
212 {
213  uint32_t SetupTime;
219  uint32_t WaitSetupTime;
225  uint32_t HoldSetupTime;
232  uint32_t HiZSetupTime;
238 }FSMC_NAND_PCC_TimingTypeDef;
239 
243 typedef struct
244 {
245  uint32_t Waitfeature;
248  uint32_t TCLRSetupTime;
252  uint32_t TARSetupTime;
256 }FSMC_PCCARD_InitTypeDef;
260 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
261 
262 /* Private constants ---------------------------------------------------------*/
273 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
274 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
275 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
276 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
277 
284 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
285 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
286 
293 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
294 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
295 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
296 
303 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
306 
313 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
314 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
315 
322 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
323 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
324 
331 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
332 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
333 
341 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
342 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
343 
350 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
351 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
352 
359 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
360 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
361 
368 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
369 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
370 
377 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
378 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
379 
386 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
387 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
388 
395 #define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
396 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
397 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
398 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
399 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
400 
408 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
409 #define FSMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
410 
417 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
418 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
419 
427 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
428 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
429 
436 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
437 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
438 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
439 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
440 
447 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
448 
454 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010U)
455 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100U)
456 
463 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
464 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
465 
472 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
473 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
474 
481 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
482 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
483 
490 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
491 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
492 
499 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
500 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
501 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
502 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
503 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
504 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
505 
511 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
512 
516 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
517 #define FSMC_IT_LEVEL ((uint32_t)0x00000010U)
518 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
519 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
520 
527 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
528 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U)
529 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
530 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U)
531 
538 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
539 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
540 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
541 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
542 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
543 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
544 
545 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
546 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
547 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
548 #define FSMC_NAND_DEVICE FSMC_Bank2_3
549 #define FSMC_PCCARD_DEVICE FSMC_Bank4
550 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
551 
552 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
553 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
554 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
555 
556 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
557 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
558 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
559 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
560 
561 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
562 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
563 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
564 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
565 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
566 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
567 
568 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
569 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
570 
571 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
572 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
573 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
574 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
575 
576 #define FMC_NAND_Init FSMC_NAND_Init
577 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
578 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
579 #define FMC_NAND_DeInit FSMC_NAND_DeInit
580 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
581 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
582 #define FMC_NAND_GetECC FSMC_NAND_GetECC
583 #define FMC_PCCARD_Init FSMC_PCCARD_Init
584 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
585 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
586 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
587 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
588 
589 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
590 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
591 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
592 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
593 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
594 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
595 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
596 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
597 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
598 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
599 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
600 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
601 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
602 
603 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
604 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
605 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
606 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
607 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
608 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
609 
610 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
611 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
612 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
613 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
614 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
615 
616 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
617 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
618 
619 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
620 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
621 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
622 
623 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
624 #define FMC_IT_LEVEL FSMC_IT_LEVEL
625 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
626 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
627 
628 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
629 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
630 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
631 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
632 
640 /* Private macro -------------------------------------------------------------*/
655 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
656 
663 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
664 
672 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
673 
679 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
680  ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
681 
688 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
689  ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
690 
703 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
704 
710 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
711 
730 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
731  ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
732 
744 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
745  ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
746 
759 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
760  (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
761 
774 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
775  ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
776 
787 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
788 
799 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
800 
812 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
813 
825 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
826 
829 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
830 
834 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
835  ((__BANK__) == FSMC_NORSRAM_BANK2) || \
836  ((__BANK__) == FSMC_NORSRAM_BANK3) || \
837  ((__BANK__) == FSMC_NORSRAM_BANK4))
838 
839 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
840  ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
841 
842 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
843  ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
844  ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
845 
846 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
847  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
848  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
849 
850 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
851  ((__MODE__) == FSMC_ACCESS_MODE_B) || \
852  ((__MODE__) == FSMC_ACCESS_MODE_C) || \
853  ((__MODE__) == FSMC_ACCESS_MODE_D))
854 
855 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
856  ((BANK) == FSMC_NAND_BANK3))
857 
858 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
859  ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
860 
861 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
862  ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
863 
864 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
865  ((STATE) == FSMC_NAND_ECC_ENABLE))
866 
867 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
868  ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
869  ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
870  ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
871  ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
872  ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
873 
874 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
875 
876 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
877 
878 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
879 
880 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
881 
882 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
883 
884 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
885 
886 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
887 
888 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
889 
890 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
891 
892 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
893 
894 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
895  ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
896 
897 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
898  ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
899 
900 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
901  ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
902 
903 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
904  ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
905 
906 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
907  ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
908 
909 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
910  ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
911 
912 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
913  ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
914 
915 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
916  ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
917 
918 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
919 
920 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
921  ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
922 
923 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
924 
925 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
926 
927 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
928 
929 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
930 
931 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
932  ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
933 
934 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
935 
936 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
937  ((SIZE) == FSMC_PAGE_SIZE_128) || \
938  ((SIZE) == FSMC_PAGE_SIZE_256) || \
939  ((SIZE) == FSMC_PAGE_SIZE_1024))
940 
941 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
942  ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
943 
951 /* Private functions ---------------------------------------------------------*/
963 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
964 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
965 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
966 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
974 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
975 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
983 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
984 
990 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
991 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
992 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
993 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1001 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1002 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1003 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1017 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
1018 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1019 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1020 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1021 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
1028 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
1029 
1033 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
1034 
1043 #ifdef __cplusplus
1044 }
1045 #endif
1046 
1047 #endif /* __STM32F4xx_LL_FSMC_H */
1048 
1049 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57