STM CMSIS
stm32f4xx_ll_sdmmc.h
Go to the documentation of this file.
1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_SDMMC_H
40 #define __STM32F4xx_LL_SDMMC_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
46  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
47  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
48  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
49  defined(STM32F412Rx) || defined(STM32F412Cx)
50 /* Includes ------------------------------------------------------------------*/
51 #include "stm32f4xx_hal_def.h"
52 
61 /* Exported types ------------------------------------------------------------*/
69 typedef struct
70 {
71  uint32_t ClockEdge;
74  uint32_t ClockBypass;
78  uint32_t ClockPowerSave;
82  uint32_t BusWide;
85  uint32_t HardwareFlowControl;
88  uint32_t ClockDiv;
91 }SDIO_InitTypeDef;
92 
93 
97 typedef struct
98 {
99  uint32_t Argument;
104  uint32_t CmdIndex;
107  uint32_t Response;
110  uint32_t WaitForInterrupt;
114  uint32_t CPSM;
117 }SDIO_CmdInitTypeDef;
118 
119 
123 typedef struct
124 {
125  uint32_t DataTimeOut;
127  uint32_t DataLength;
129  uint32_t DataBlockSize;
132  uint32_t TransferDir;
136  uint32_t TransferMode;
139  uint32_t DPSM;
142 }SDIO_DataInitTypeDef;
143 
148 /* Exported constants --------------------------------------------------------*/
156 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
157 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
158 
159 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
160  ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
161 
168 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
169 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
170 
171 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
172  ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
173 
180 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
181 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
182 
183 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
184  ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
185 
192 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000U)
193 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
194 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
195 
196 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
197  ((WIDE) == SDIO_BUS_WIDE_4B) || \
198  ((WIDE) == SDIO_BUS_WIDE_8B))
199 
206 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
207 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
208 
209 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
210  ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
211 
218 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
219 
226 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
227 
234 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000U)
235 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
236 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
237 
238 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
239  ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
240  ((RESPONSE) == SDIO_RESPONSE_LONG))
241 
248 #define SDIO_WAIT_NO ((uint32_t)0x00000000U)
249 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
250 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
251 
252 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
253  ((WAIT) == SDIO_WAIT_IT) || \
254  ((WAIT) == SDIO_WAIT_PEND))
255 
262 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000U)
263 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
264 
265 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
266  ((CPSM) == SDIO_CPSM_ENABLE))
267 
274 #define SDIO_RESP1 ((uint32_t)0x00000000U)
275 #define SDIO_RESP2 ((uint32_t)0x00000004U)
276 #define SDIO_RESP3 ((uint32_t)0x00000008U)
277 #define SDIO_RESP4 ((uint32_t)0x0000000CU)
278 
279 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
280  ((RESP) == SDIO_RESP2) || \
281  ((RESP) == SDIO_RESP3) || \
282  ((RESP) == SDIO_RESP4))
283 
290 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
291 
298 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
299 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
300 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
301 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030U)
302 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
303 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050U)
304 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060U)
305 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070U)
306 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
307 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090U)
308 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0U)
309 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0U)
310 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0U)
311 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0U)
312 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0U)
313 
314 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
315  ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
316  ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
317  ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
318  ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
319  ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
320  ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
321  ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
322  ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
323  ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
324  ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
325  ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
326  ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
327  ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
328  ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
329 
336 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
337 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
338 
339 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
340  ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
341 
348 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
349 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
350 
351 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
352  ((MODE) == SDIO_TRANSFER_MODE_STREAM))
353 
360 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000U)
361 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
362 
363 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
364  ((DPSM) == SDIO_DPSM_ENABLE))
365 
372 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
373 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001U)
374 
375 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
376  ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
377 
384 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
385 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
386 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
387 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
388 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
389 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
390 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
391 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
392 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
393 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
394 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
395 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
396 #define SDIO_IT_TXACT SDIO_STA_TXACT
397 #define SDIO_IT_RXACT SDIO_STA_RXACT
398 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
399 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
400 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
401 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
402 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
403 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
404 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
405 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
406 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
407 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
408 
415 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
416 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
417 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
418 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
419 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
420 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
421 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
422 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
423 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
424 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
425 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
426 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
427 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
428 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
429 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
430 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
431 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
432 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
433 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
434 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
435 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
436 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
437 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
438 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
439 
446 /* Exported macro ------------------------------------------------------------*/
454 /* ------------ SDIO registers bit address in the alias region -------------- */
455 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
456 
457 /* --- CLKCR Register ---*/
458 /* Alias word address of CLKEN bit */
459 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
460 #define CLKEN_BITNUMBER 0x08U
461 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
462 
463 /* --- CMD Register ---*/
464 /* Alias word address of SDIOSUSPEND bit */
465 #define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
466 #define SDIOSUSPEND_BITNUMBER 0x0BU
467 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
468 
469 /* Alias word address of ENCMDCOMPL bit */
470 #define ENCMDCOMPL_BITNUMBER 0x0CU
471 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
472 
473 /* Alias word address of NIEN bit */
474 #define NIEN_BITNUMBER 0x0DU
475 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
476 
477 /* Alias word address of ATACMD bit */
478 #define ATACMD_BITNUMBER 0x0EU
479 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
480 
481 /* --- DCTRL Register ---*/
482 /* Alias word address of DMAEN bit */
483 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
484 #define DMAEN_BITNUMBER 0x03U
485 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
486 
487 /* Alias word address of RWSTART bit */
488 #define RWSTART_BITNUMBER 0x08U
489 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
490 
491 /* Alias word address of RWSTOP bit */
492 #define RWSTOP_BITNUMBER 0x09U
493 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
494 
495 /* Alias word address of RWMOD bit */
496 #define RWMOD_BITNUMBER 0x0AU
497 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
498 
499 /* Alias word address of SDIOEN bit */
500 #define SDIOEN_BITNUMBER 0x0BU
501 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
502 
511 /* ---------------------- SDIO registers bit mask --------------------------- */
512 /* --- CLKCR Register ---*/
513 /* CLKCR register clear mask */
514 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
515  SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
516  SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
517 
518 /* --- PWRCTRL Register ---*/
519 /* --- DCTRL Register ---*/
520 /* SDIO DCTRL Clear Mask */
521 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
522  SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
523 
524 /* --- CMD Register ---*/
525 /* CMD Register clear mask */
526 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
527  SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
528  SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
529 
530 /* SDIO RESP Registers Address */
531 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14U))
532 
533 /* SDIO Initialization Frequency (400KHz max) */
534 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76U)
535 
536 /* SDIO Data Transfer Frequency (25MHz max) */
537 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x00U)
538 
551 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
552 
557 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
558 
563 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
564 
569 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
570 
603 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
604 
637 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
638 
670 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
671 
672 
693 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
694 
727 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
728 
749 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
750 
755 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
756 
761 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
762 
767 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
768 
773 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
774 
779 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
780 
785 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
786 
791 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
792 
797 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
798 
799 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
800  defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
801  defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) ||\
802  defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
803 
807 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
808 
813 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
814 
819 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
820 
825 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
826 
831 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
832 
837 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
838 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
839  STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
840  STM32F412Cx */
841 
849 /* Exported functions --------------------------------------------------------*/
854 /* Initialization/de-initialization functions **********************************/
858 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
863 /* I/O operation functions *****************************************************/
867 /* Blocking mode: Polling */
868 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
869 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
874 /* Peripheral Control functions ************************************************/
878 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
879 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
880 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
881 
882 /* Command path state machine (CPSM) management functions */
883 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
884 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
885 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
886 
887 /* Data path state machine (DPSM) management functions */
888 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
889 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
890 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
891 
892 /* SDIO IO Cards mode management functions */
893 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
894 
910 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
911  STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
912  STM32F412Rx || STM32F412Cx */
913 #ifdef __cplusplus
914 }
915 #endif
916 
917 #endif /* __STM32F4xx_LL_SDMMC_H */
918 
919 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444