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STM CMSIS
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Macros | |
| #define | ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00U) |
| ACR register byte 0 (Bits[7:0]) base address. | |
| #define | OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14U) |
| OPTCR register byte 0 (Bits[7:0]) base address. | |
| #define | OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15U) |
| OPTCR register byte 1 (Bits[15:8]) base address. | |
| #define | OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16U) |
| OPTCR register byte 2 (Bits[23:16]) base address. | |
| #define | OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17U) |
| OPTCR register byte 3 (Bits[31:24]) base address. | |