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STM CMSIS
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RCC registers bit address in the alias region. More...
Macros | |
| #define | RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
| #define | RCC_CR_OFFSET (RCC_OFFSET + 0x00U) |
| #define | RCC_HSION_BIT_NUMBER 0x00U |
| #define | RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) |
| #define | RCC_CSSON_BIT_NUMBER 0x13U |
| #define | RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) |
| #define | RCC_PLLON_BIT_NUMBER 0x18U |
| #define | RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) |
| #define | RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) |
| #define | RCC_RTCEN_BIT_NUMBER 0x0FU |
| #define | RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) |
| #define | RCC_BDRST_BIT_NUMBER 0x10U |
| #define | RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) |
| #define | RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) |
| #define | RCC_LSION_BIT_NUMBER 0x00U |
| #define | RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) |
| #define | RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U) |
| #define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) |
| #define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) |
| #define | RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) |
| #define | RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) |
| #define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
| #define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
| #define | HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */ |
| #define | LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */ |
RCC registers bit address in the alias region.