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stm32f4xx_hal_dma.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_DMA_H
40 #define __STM32F4xx_HAL_DMA_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48 
57 /* Exported types ------------------------------------------------------------*/
58 
67 typedef struct
68 {
69  uint32_t Channel;
72  uint32_t Direction;
76  uint32_t PeriphInc;
79  uint32_t MemInc;
82  uint32_t PeriphDataAlignment;
85  uint32_t MemDataAlignment;
88  uint32_t Mode;
93  uint32_t Priority;
96  uint32_t FIFOMode;
101  uint32_t FIFOThreshold;
104  uint32_t MemBurst;
110  uint32_t PeriphBurst;
115 }DMA_InitTypeDef;
116 
117 
121 typedef enum
122 {
123  HAL_DMA_STATE_RESET = 0x00U,
124  HAL_DMA_STATE_READY = 0x01U,
125  HAL_DMA_STATE_BUSY = 0x02U,
126  HAL_DMA_STATE_TIMEOUT = 0x03U,
127  HAL_DMA_STATE_ERROR = 0x04U,
128  HAL_DMA_STATE_ABORT = 0x05U,
129 }HAL_DMA_StateTypeDef;
130 
134 typedef enum
135 {
136  HAL_DMA_FULL_TRANSFER = 0x00U,
137  HAL_DMA_HALF_TRANSFER = 0x01U
138 }HAL_DMA_LevelCompleteTypeDef;
139 
143 typedef enum
144 {
145  HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
146  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
147  HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
148  HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
149  HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
150  HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
151  HAL_DMA_XFER_ALL_CB_ID = 0x06U
152 }HAL_DMA_CallbackIDTypeDef;
153 
157 typedef struct __DMA_HandleTypeDef
158 {
159  DMA_Stream_TypeDef *Instance;
161  DMA_InitTypeDef Init;
163  HAL_LockTypeDef Lock;
165  __IO HAL_DMA_StateTypeDef State;
167  void *Parent;
169  void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);
171  void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
173  void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);
175  void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
177  void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);
179  void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);
181  __IO uint32_t ErrorCode;
183  uint32_t StreamBaseAddress;
185  uint32_t StreamIndex;
187 }DMA_HandleTypeDef;
188 
193 /* Exported constants --------------------------------------------------------*/
194 
204 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U)
205 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U)
206 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U)
207 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U)
208 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U)
209 #define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U)
210 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U)
211 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U)
220 #define DMA_CHANNEL_0 ((uint32_t)0x00000000U)
221 #define DMA_CHANNEL_1 ((uint32_t)0x02000000U)
222 #define DMA_CHANNEL_2 ((uint32_t)0x04000000U)
223 #define DMA_CHANNEL_3 ((uint32_t)0x06000000U)
224 #define DMA_CHANNEL_4 ((uint32_t)0x08000000U)
225 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000U)
226 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000U)
227 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000U)
236 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
237 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
238 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
247 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
248 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U)
257 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
258 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U)
267 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
268 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
269 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
278 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
279 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
280 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
289 #define DMA_NORMAL ((uint32_t)0x00000000U)
290 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
291 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
300 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
301 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
302 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
303 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
312 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
313 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
322 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
323 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
324 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
325 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
334 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
335 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
336 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
337 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
338 
346 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
347 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
348 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
349 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
350 
358 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
359 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
360 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
361 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
362 #define DMA_IT_FE ((uint32_t)0x00000080U)
363 
371 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
372 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
373 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
374 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
375 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
376 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
377 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
378 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
379 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
380 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
381 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
382 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
383 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
384 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
385 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
386 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
387 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
388 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
389 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
390 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
391 
399 /* Exported macro ------------------------------------------------------------*/
400 
405 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
406 
419 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
420 
426 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
427 
433 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
434 
435 /* Interrupt & Flag management */
436 
442 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
444  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
445  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
446  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
447  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
448  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
449  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
450  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
451  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
452  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
453  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
454  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
455  DMA_FLAG_TCIF3_7)
456 
462 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
464  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
465  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
466  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
467  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
468  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
469  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
470  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
471  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
472  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
473  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
474  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
475  DMA_FLAG_HTIF3_7)
476 
482 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
483 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
484  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
485  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
486  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
487  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
488  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
489  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
490  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
491  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
492  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
493  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
494  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
495  DMA_FLAG_TEIF3_7)
496 
502 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
503 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
504  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
505  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
506  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
507  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
508  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
509  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
510  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
511  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
512  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
513  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
514  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
515  DMA_FLAG_FEIF3_7)
516 
522 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
523 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
524  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
525  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
526  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
527  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
528  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
529  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
530  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
531  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
532  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
533  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
534  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
535  DMA_FLAG_DMEIF3_7)
536 
550 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
551 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
552  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
553  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
554 
568 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
569 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
570  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
571  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
572 
585 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
586 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
587 
600 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
601 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
602 
615 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
616  ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
617  ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
618 
636 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
637 
644 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
645 
646 
647 /* Include DMA HAL Extension module */
648 #include "stm32f4xx_hal_dma_ex.h"
649 
650 /* Exported functions --------------------------------------------------------*/
651 
661 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
662 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
671 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
672 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
673 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
674 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
675 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
676 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
677 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
678 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
679 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
680 
689 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
690 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
697 /* Private Constants -------------------------------------------------------------*/
706 /* Private macros ------------------------------------------------------------*/
711 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
712  ((CHANNEL) == DMA_CHANNEL_1) || \
713  ((CHANNEL) == DMA_CHANNEL_2) || \
714  ((CHANNEL) == DMA_CHANNEL_3) || \
715  ((CHANNEL) == DMA_CHANNEL_4) || \
716  ((CHANNEL) == DMA_CHANNEL_5) || \
717  ((CHANNEL) == DMA_CHANNEL_6) || \
718  ((CHANNEL) == DMA_CHANNEL_7))
719 
720 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
721  ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
722  ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
723 
724 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
725 
726 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
727  ((STATE) == DMA_PINC_DISABLE))
728 
729 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
730  ((STATE) == DMA_MINC_DISABLE))
731 
732 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
733  ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
734  ((SIZE) == DMA_PDATAALIGN_WORD))
735 
736 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
737  ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
738  ((SIZE) == DMA_MDATAALIGN_WORD ))
739 
740 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
741  ((MODE) == DMA_CIRCULAR) || \
742  ((MODE) == DMA_PFCTRL))
743 
744 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
745  ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
746  ((PRIORITY) == DMA_PRIORITY_HIGH) || \
747  ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
748 
749 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
750  ((STATE) == DMA_FIFOMODE_ENABLE))
751 
752 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
753  ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
754  ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
755  ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
756 
757 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
758  ((BURST) == DMA_MBURST_INC4) || \
759  ((BURST) == DMA_MBURST_INC8) || \
760  ((BURST) == DMA_MBURST_INC16))
761 
762 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
763  ((BURST) == DMA_PBURST_INC4) || \
764  ((BURST) == DMA_PBURST_INC8) || \
765  ((BURST) == DMA_PBURST_INC16))
766 
770 /* Private functions ---------------------------------------------------------*/
787 #ifdef __cplusplus
788 }
789 #endif
790 
791 #endif /* __STM32F4xx_HAL_DMA_H */
792 
793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_DMA_STATE_TIMEOUT
Definition: stm32f4xx_hal_dma.h:126
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
DMA_InitTypeDef::FIFOThreshold
uint32_t FIFOThreshold
Definition: stm32f4xx_hal_dma.h:101
HAL_DMA_XFER_ABORT_CB_ID
Definition: stm32f4xx_hal_dma.h:150
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
__DMA_HandleTypeDef::StreamIndex
uint32_t StreamIndex
Definition: stm32f4xx_hal_dma.h:185
DMA_InitTypeDef::PeriphBurst
uint32_t PeriphBurst
Definition: stm32f4xx_hal_dma.h:110
HAL_DMA_StateTypeDef
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
Definition: stm32f4xx_hal_dma.h:121
__DMA_HandleTypeDef::Parent
void * Parent
Definition: stm32f4xx_hal_dma.h:167
__DMA_HandleTypeDef::XferM1HalfCpltCallback
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f4xx_hal_dma.h:175
HAL_DMA_CallbackIDTypeDef
HAL_DMA_CallbackIDTypeDef
HAL DMA Error Code structure definition.
Definition: stm32f4xx_hal_dma.h:143
__DMA_HandleTypeDef::Instance
DMA_Stream_TypeDef * Instance
Definition: stm32f4xx_hal_dma.h:159
DMA_InitTypeDef::Direction
uint32_t Direction
Definition: stm32f4xx_hal_dma.h:72
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f4xx_hal_dma.h:177
HAL_DMA_STATE_BUSY
Definition: stm32f4xx_hal_dma.h:125
HAL_DMA_STATE_ERROR
Definition: stm32f4xx_hal_dma.h:127
HAL_DMA_XFER_ALL_CB_ID
Definition: stm32f4xx_hal_dma.h:151
DMA_InitTypeDef::Priority
uint32_t Priority
Definition: stm32f4xx_hal_dma.h:93
__DMA_HandleTypeDef::XferHalfCpltCallback
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f4xx_hal_dma.h:171
HAL_DMA_FULL_TRANSFER
Definition: stm32f4xx_hal_dma.h:136
__DMA_HandleTypeDef::State
__IO HAL_DMA_StateTypeDef State
Definition: stm32f4xx_hal_dma.h:165
DMA_InitTypeDef::MemInc
uint32_t MemInc
Definition: stm32f4xx_hal_dma.h:79
__DMA_HandleTypeDef::Init
DMA_InitTypeDef Init
Definition: stm32f4xx_hal_dma.h:161
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
DMA_InitTypeDef
DMA Configuration Structure definition.
Definition: stm32f4xx_hal_dma.h:67
HAL_DMA_HALF_TRANSFER
Definition: stm32f4xx_hal_dma.h:137
__IO
#define __IO
Definition: core_cm0.h:213
HAL_DMA_XFER_HALFCPLT_CB_ID
Definition: stm32f4xx_hal_dma.h:146
HAL_DMA_XFER_M1CPLT_CB_ID
Definition: stm32f4xx_hal_dma.h:147
DMA_InitTypeDef::Mode
uint32_t Mode
Definition: stm32f4xx_hal_dma.h:88
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
__DMA_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f4xx_hal_dma.h:181
DMA_InitTypeDef::Channel
uint32_t Channel
Definition: stm32f4xx_hal_dma.h:69
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f4xx_hal_dma.h:169
HAL_DMA_STATE_READY
Definition: stm32f4xx_hal_dma.h:124
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:68
DMA_InitTypeDef::MemBurst
uint32_t MemBurst
Definition: stm32f4xx_hal_dma.h:104
HAL_DMA_XFER_M1HALFCPLT_CB_ID
Definition: stm32f4xx_hal_dma.h:148
HAL_DMA_STATE_RESET
Definition: stm32f4xx_hal_dma.h:123
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:157
stm32f4xx_hal_dma_ex.h
Header file of DMA HAL extension module.
HAL_DMA_XFER_ERROR_CB_ID
Definition: stm32f4xx_hal_dma.h:149
HAL_DMA_XFER_CPLT_CB_ID
Definition: stm32f4xx_hal_dma.h:145
__DMA_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f4xx_hal_dma.h:163
__DMA_HandleTypeDef::XferM1CpltCallback
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f4xx_hal_dma.h:173
HAL_DMA_STATE_ABORT
Definition: stm32f4xx_hal_dma.h:128
__DMA_HandleTypeDef::XferAbortCallback
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f4xx_hal_dma.h:179
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_LevelCompleteTypeDef
HAL DMA Error Code structure definition.
Definition: stm32f4xx_hal_dma.h:134
DMA_InitTypeDef::MemDataAlignment
uint32_t MemDataAlignment
Definition: stm32f4xx_hal_dma.h:85
DMA_InitTypeDef::PeriphInc
uint32_t PeriphInc
Definition: stm32f4xx_hal_dma.h:76
DMA_InitTypeDef::FIFOMode
uint32_t FIFOMode
Definition: stm32f4xx_hal_dma.h:96
DMA_InitTypeDef::PeriphDataAlignment
uint32_t PeriphDataAlignment
Definition: stm32f4xx_hal_dma.h:82
__DMA_HandleTypeDef::StreamBaseAddress
uint32_t StreamBaseAddress
Definition: stm32f4xx_hal_dma.h:183