STM CMSIS
stm32f4xx_hal_rcc.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_RCC_H
40 #define __STM32F4xx_HAL_RCC_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48 
49 /* Include RCC HAL Extended module */
50 /* (include on top of file since RCC structures are defined in extended file) */
51 #include "stm32f4xx_hal_rcc_ex.h"
52 
61 /* Exported types ------------------------------------------------------------*/
69 typedef struct
70 {
71  uint32_t OscillatorType;
74  uint32_t HSEState;
77  uint32_t LSEState;
80  uint32_t HSIState;
83  uint32_t HSICalibrationValue;
86  uint32_t LSIState;
89  RCC_PLLInitTypeDef PLL;
90 }RCC_OscInitTypeDef;
91 
95 typedef struct
96 {
97  uint32_t ClockType;
100  uint32_t SYSCLKSource;
103  uint32_t AHBCLKDivider;
106  uint32_t APB1CLKDivider;
109  uint32_t APB2CLKDivider;
112 }RCC_ClkInitTypeDef;
113 
118 /* Exported constants --------------------------------------------------------*/
126 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
127 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
128 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
129 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
130 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
131 
138 #define RCC_HSE_OFF ((uint8_t)0x00U)
139 #define RCC_HSE_ON ((uint8_t)0x01U)
140 #define RCC_HSE_BYPASS ((uint8_t)0x05U)
141 
148 #define RCC_LSE_OFF ((uint8_t)0x00U)
149 #define RCC_LSE_ON ((uint8_t)0x01U)
150 #define RCC_LSE_BYPASS ((uint8_t)0x05U)
151 
158 #define RCC_HSI_OFF ((uint8_t)0x00U)
159 #define RCC_HSI_ON ((uint8_t)0x01U)
160 
161 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
162 
169 #define RCC_LSI_OFF ((uint8_t)0x00U)
170 #define RCC_LSI_ON ((uint8_t)0x01U)
171 
178 #define RCC_PLL_NONE ((uint8_t)0x00U)
179 #define RCC_PLL_OFF ((uint8_t)0x01U)
180 #define RCC_PLL_ON ((uint8_t)0x02U)
181 
188 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
189 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
190 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
191 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
192 
199 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
200 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
201 
208 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
209 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
210 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
211 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
212 
219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
223 
230 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
231 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
232 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
233 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))
241 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
242 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
243 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
244 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
245 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
246 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
247 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
248 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
249 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
250 
257 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
258 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
259 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
260 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
261 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
262 
269 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
270 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
271 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
272 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
273 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
274 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
275 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
276 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
277 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
278 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
279 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
280 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
281 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
282 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
283 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
284 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
285 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
286 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
287 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
288 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
289 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
290 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
291 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
292 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
293 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
294 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
295 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
296 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
297 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
298 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
299 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
300 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
301 
308 #define RCC_MCO1 ((uint32_t)0x00000000U)
309 #define RCC_MCO2 ((uint32_t)0x00000001U)
310 
317 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
318 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
319 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
320 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
321 
328 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
329 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
330 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
331 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
332 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
333 
340 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
341 #define RCC_IT_LSERDY ((uint8_t)0x02U)
342 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
343 #define RCC_IT_HSERDY ((uint8_t)0x08U)
344 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
345 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
346 #define RCC_IT_CSS ((uint8_t)0x80U)
347 
360 /* Flags in the CR register */
361 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
362 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
363 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
364 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
365 
366 /* Flags in the BDCR register */
367 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
368 
369 /* Flags in the CSR register */
370 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
371 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
372 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
373 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
374 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
375 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
376 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
377 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
378 
386 /* Exported macro ------------------------------------------------------------*/
398 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
399  __IO uint32_t tmpreg = 0x00U; \
400  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
401  /* Delay after an RCC peripheral clock enabling */ \
402  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
403  UNUSED(tmpreg); \
404  } while(0)
405 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
406  __IO uint32_t tmpreg = 0x00U; \
407  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
408  /* Delay after an RCC peripheral clock enabling */ \
409  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
410  UNUSED(tmpreg); \
411  } while(0)
412 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
413  __IO uint32_t tmpreg = 0x00U; \
414  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
415  /* Delay after an RCC peripheral clock enabling */ \
416  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
417  UNUSED(tmpreg); \
418  } while(0)
419 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
420  __IO uint32_t tmpreg = 0x00U; \
421  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
422  /* Delay after an RCC peripheral clock enabling */ \
423  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
424  UNUSED(tmpreg); \
425  } while(0)
426 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
427  __IO uint32_t tmpreg = 0x00U; \
428  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
429  /* Delay after an RCC peripheral clock enabling */ \
430  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
431  UNUSED(tmpreg); \
432  } while(0)
433 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
434  __IO uint32_t tmpreg = 0x00U; \
435  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
436  /* Delay after an RCC peripheral clock enabling */ \
437  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
438  UNUSED(tmpreg); \
439  } while(0)
440 
441 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
442 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
443 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
444 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
445 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
446 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
447 
458 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
459 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
460 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
461 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
462 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
463 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
464 
465 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
466 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
467 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
468 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
469 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
470 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
471 
482 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
483  __IO uint32_t tmpreg = 0x00U; \
484  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
485  /* Delay after an RCC peripheral clock enabling */ \
486  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
487  UNUSED(tmpreg); \
488  } while(0)
489 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
490  __IO uint32_t tmpreg = 0x00U; \
491  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
492  /* Delay after an RCC peripheral clock enabling */ \
493  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
494  UNUSED(tmpreg); \
495  } while(0)
496 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
497  __IO uint32_t tmpreg = 0x00U; \
498  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
499  /* Delay after an RCC peripheral clock enabling */ \
500  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
501  UNUSED(tmpreg); \
502  } while(0)
503 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
504  __IO uint32_t tmpreg = 0x00U; \
505  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
506  /* Delay after an RCC peripheral clock enabling */ \
507  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
508  UNUSED(tmpreg); \
509  } while(0)
510 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
511  __IO uint32_t tmpreg = 0x00U; \
512  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
513  /* Delay after an RCC peripheral clock enabling */ \
514  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
515  UNUSED(tmpreg); \
516  } while(0)
517 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
518  __IO uint32_t tmpreg = 0x00U; \
519  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
520  /* Delay after an RCC peripheral clock enabling */ \
521  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
522  UNUSED(tmpreg); \
523  } while(0)
524 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
525  __IO uint32_t tmpreg = 0x00U; \
526  SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
527  /* Delay after an RCC peripheral clock enabling */ \
528  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
529  UNUSED(tmpreg); \
530  } while(0)
531 
532 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
533 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
534 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
535 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
536 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
537 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
538 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
539 
550 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
551 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
552 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
553 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
554 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
555 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
556 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
557 
558 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
559 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
560 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
561 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
562 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
563 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
564 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
565 
576 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
577  __IO uint32_t tmpreg = 0x00U; \
578  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
579  /* Delay after an RCC peripheral clock enabling */ \
580  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
581  UNUSED(tmpreg); \
582  } while(0)
583 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
584  __IO uint32_t tmpreg = 0x00U; \
585  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
586  /* Delay after an RCC peripheral clock enabling */ \
587  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
588  UNUSED(tmpreg); \
589  } while(0)
590 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
591  __IO uint32_t tmpreg = 0x00U; \
592  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
593  /* Delay after an RCC peripheral clock enabling */ \
594  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
595  UNUSED(tmpreg); \
596  } while(0)
597 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
598  __IO uint32_t tmpreg = 0x00U; \
599  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
600  /* Delay after an RCC peripheral clock enabling */ \
601  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
602  UNUSED(tmpreg); \
603  } while(0)
604 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
605  __IO uint32_t tmpreg = 0x00U; \
606  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
607  /* Delay after an RCC peripheral clock enabling */ \
608  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
609  UNUSED(tmpreg); \
610  } while(0)
611 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
612  __IO uint32_t tmpreg = 0x00U; \
613  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
614  /* Delay after an RCC peripheral clock enabling */ \
615  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
616  UNUSED(tmpreg); \
617  } while(0)
618 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
619  __IO uint32_t tmpreg = 0x00U; \
620  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
621  /* Delay after an RCC peripheral clock enabling */ \
622  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
623  UNUSED(tmpreg); \
624  } while(0)
625 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
626  __IO uint32_t tmpreg = 0x00U; \
627  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
628  /* Delay after an RCC peripheral clock enabling */ \
629  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
630  UNUSED(tmpreg); \
631  } while(0)
632 
633 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
634 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
635 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
636 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
637 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
638 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
639 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
640 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
641 
652 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
653 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
654 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
655 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
656 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
657 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
658 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
659 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
660 
661 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
662 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
663 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
664 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
665 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
666 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
667 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
668 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
669 
677 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
678 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
679 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
680 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
681 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
682 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
683 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
684 
685 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
686 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
687 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
688 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
689 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
690 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
691 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
692 
700 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
701 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
702 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
703 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
704 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
705 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
706 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
707 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
708 
709 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
710 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
711 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
712 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
713 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
714 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
715 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
716 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
717 
725 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
726 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
727 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
728 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
729 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
730 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
731 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
732 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
733 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
734 
735 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
736 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
737 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
738 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
739 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
740 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
741 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
742 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
743 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
744 
756 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
757 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
758 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
759 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
760 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
761 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
762 
763 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
764 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
765 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
766 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
767 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
768 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
769 
781 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
782 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
783 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
784 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
785 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
786 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
787 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
788 
789 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
790 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
791 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
792 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
793 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
794 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
795 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
796 
808 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
809 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
810 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
811 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
812 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
813 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
814 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
815 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
816 
817 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
818 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
819 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
820 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
821 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
822 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
823 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
824 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
825 
848 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
849 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
850 
858 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
859  RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
860 
876 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
877 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
878 
907 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
908 
934 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
935 
947 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
948 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
949 
971 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
972  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
973 
974 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
975  RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
976  } while (0)
977 
983 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
984 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
985 
1000 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
1001 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
1002 
1011 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
1012 
1022 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
1023 
1039 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
1040 
1049 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
1050 
1057 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
1058 
1081 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1082  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1083 
1102 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1103  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
1104 
1124 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1125 
1137 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1138 
1151 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1152 
1165 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1166 
1170 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1171 
1190 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
1191 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
1192 
1201 /* Exported functions --------------------------------------------------------*/
1209 /* Initialization and de-initialization functions ******************************/
1210 void HAL_RCC_DeInit(void);
1211 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1212 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1220 /* Peripheral Control functions ************************************************/
1221 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1222 void HAL_RCC_EnableCSS(void);
1223 void HAL_RCC_DisableCSS(void);
1224 uint32_t HAL_RCC_GetSysClockFreq(void);
1225 uint32_t HAL_RCC_GetHCLKFreq(void);
1226 uint32_t HAL_RCC_GetPCLK1Freq(void);
1227 uint32_t HAL_RCC_GetPCLK2Freq(void);
1228 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1229 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1230 
1231 /* CSS NMI IRQ handler */
1232 void HAL_RCC_NMI_IRQHandler(void);
1233 
1234 /* User Callbacks in non blocking mode (IT mode) */
1235 void HAL_RCC_CSSCallback(void);
1236 
1245 /* Private types -------------------------------------------------------------*/
1246 /* Private variables ---------------------------------------------------------*/
1247 /* Private constants ---------------------------------------------------------*/
1256 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1257 /* --- CR Register ---*/
1258 /* Alias word address of HSION bit */
1259 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
1260 #define RCC_HSION_BIT_NUMBER 0x00U
1261 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
1262 /* Alias word address of CSSON bit */
1263 #define RCC_CSSON_BIT_NUMBER 0x13U
1264 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
1265 /* Alias word address of PLLON bit */
1266 #define RCC_PLLON_BIT_NUMBER 0x18U
1267 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
1268 
1269 /* --- BDCR Register ---*/
1270 /* Alias word address of RTCEN bit */
1271 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
1272 #define RCC_RTCEN_BIT_NUMBER 0x0FU
1273 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
1274 /* Alias word address of BDRST bit */
1275 #define RCC_BDRST_BIT_NUMBER 0x10U
1276 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
1277 
1278 /* --- CSR Register ---*/
1279 /* Alias word address of LSION bit */
1280 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
1281 #define RCC_LSION_BIT_NUMBER 0x00U
1282 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
1283 
1284 /* CR register byte 3 (Bits[23:16]) base address */
1285 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
1286 
1287 /* CIR register byte 2 (Bits[15:8]) base address */
1288 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
1289 
1290 /* CIR register byte 3 (Bits[23:16]) base address */
1291 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
1292 
1293 /* BDCR register base address */
1294 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
1295 
1296 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
1297 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1298 
1299 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1300 #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
1301 #define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
1302 
1311 /* Private macros ------------------------------------------------------------*/
1319 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
1320 
1321 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1322  ((HSE) == RCC_HSE_BYPASS))
1323 
1324 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1325  ((LSE) == RCC_LSE_BYPASS))
1326 
1327 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1328 
1329 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1330 
1331 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1332 
1333 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1334  ((SOURCE) == RCC_PLLSOURCE_HSE))
1335 
1336 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1337  ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1338  ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
1339  ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
1340 
1341 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
1342  ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
1343  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
1344  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
1345  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
1346  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
1347  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
1348  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
1349  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
1350  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
1351  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
1352  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
1353  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
1354  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
1355  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
1356  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
1357  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
1358  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
1359  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
1360  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
1361  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
1362  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
1363  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
1364  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
1365  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
1366  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
1367  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
1368  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
1369  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
1370  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
1371  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
1372  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
1373 
1374 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
1375 
1376 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
1377 
1378 #define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
1379 
1380 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
1381  ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
1382  ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
1383  ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
1384  ((HCLK) == RCC_SYSCLK_DIV512))
1385 
1386 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
1387 
1388 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
1389  ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
1390  ((PCLK) == RCC_HCLK_DIV16))
1391 
1392 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
1393 
1394 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
1395  ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1396 
1397 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
1398  ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1399  ((DIV) == RCC_MCODIV_5))
1400 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
1401 
1418 #ifdef __cplusplus
1419 }
1420 #endif
1421 
1422 #endif /* __STM32F4xx_HAL_RCC_H */
1423 
1424 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition: stm32f4xx_hal_rcc.h:89
stm32f4xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32f4xx_hal_rcc.h:95
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition: stm32f4xx_hal_rcc.h:77
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition: stm32f4xx_hal_rcc.h:103
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition: stm32f4xx_hal_rcc.h:97
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32f4xx_hal_rcc_ex.h:65
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition: stm32f4xx_hal_rcc.h:71
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition: stm32f4xx_hal_rcc.h:109
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition: stm32f4xx_hal_rcc.h:100
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition: stm32f4xx_hal_rcc.h:83
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition: stm32f4xx_hal_rcc.h:86
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition: stm32f4xx_hal_rcc.h:69
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition: stm32f4xx_hal_rcc.h:80
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition: stm32f4xx_hal_rcc.h:106
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition: stm32f4xx_hal_rcc.h:74