STM CMSIS
stm32f4xx_hal_tim.h
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1 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_TIM_H
40 #define __STM32F4xx_HAL_TIM_H
41 
42 #ifdef __cplusplus
43  extern "C" {
44 #endif
45 
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx_hal_def.h"
48 
57 /* Exported types ------------------------------------------------------------*/
65 typedef struct
66 {
67  uint32_t Prescaler;
70  uint32_t CounterMode;
73  uint32_t Period;
77  uint32_t ClockDivision;
80  uint32_t RepetitionCounter;
88 } TIM_Base_InitTypeDef;
89 
94 typedef struct
95 {
96  uint32_t OCMode;
99  uint32_t Pulse;
102  uint32_t OCPolarity;
105  uint32_t OCNPolarity;
109  uint32_t OCFastMode;
114  uint32_t OCIdleState;
118  uint32_t OCNIdleState;
121 } TIM_OC_InitTypeDef;
122 
126 typedef struct
127 {
128  uint32_t OCMode;
131  uint32_t Pulse;
134  uint32_t OCPolarity;
137  uint32_t OCNPolarity;
141  uint32_t OCIdleState;
145  uint32_t OCNIdleState;
149  uint32_t ICPolarity;
152  uint32_t ICSelection;
155  uint32_t ICFilter;
157 } TIM_OnePulse_InitTypeDef;
158 
159 
164 typedef struct
165 {
166  uint32_t ICPolarity;
169  uint32_t ICSelection;
172  uint32_t ICPrescaler;
175  uint32_t ICFilter;
177 } TIM_IC_InitTypeDef;
178 
183 typedef struct
184 {
185  uint32_t EncoderMode;
188  uint32_t IC1Polarity;
191  uint32_t IC1Selection;
194  uint32_t IC1Prescaler;
197  uint32_t IC1Filter;
200  uint32_t IC2Polarity;
203  uint32_t IC2Selection;
206  uint32_t IC2Prescaler;
209  uint32_t IC2Filter;
211 } TIM_Encoder_InitTypeDef;
212 
216 typedef struct
217 {
218  uint32_t ClockSource;
220  uint32_t ClockPolarity;
222  uint32_t ClockPrescaler;
224  uint32_t ClockFilter;
226 }TIM_ClockConfigTypeDef;
227 
231 typedef struct
232 {
233  uint32_t ClearInputState;
235  uint32_t ClearInputSource;
237  uint32_t ClearInputPolarity;
239  uint32_t ClearInputPrescaler;
241  uint32_t ClearInputFilter;
243 }TIM_ClearInputConfigTypeDef;
244 
248 typedef struct {
249  uint32_t SlaveMode;
251  uint32_t InputTrigger;
253  uint32_t TriggerPolarity;
255  uint32_t TriggerPrescaler;
257  uint32_t TriggerFilter;
260 }TIM_SlaveConfigTypeDef;
261 
265 typedef enum
266 {
267  HAL_TIM_STATE_RESET = 0x00U,
268  HAL_TIM_STATE_READY = 0x01U,
269  HAL_TIM_STATE_BUSY = 0x02U,
270  HAL_TIM_STATE_TIMEOUT = 0x03U,
271  HAL_TIM_STATE_ERROR = 0x04U
272 }HAL_TIM_StateTypeDef;
273 
277 typedef enum
278 {
279  HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
280  HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
281  HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
282  HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
283  HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
284 }HAL_TIM_ActiveChannel;
285 
289 typedef struct
290 {
291  TIM_TypeDef *Instance;
292  TIM_Base_InitTypeDef Init;
293  HAL_TIM_ActiveChannel Channel;
294  DMA_HandleTypeDef *hdma[7];
296  HAL_LockTypeDef Lock;
297  __IO HAL_TIM_StateTypeDef State;
298 }TIM_HandleTypeDef;
303 /* Exported constants --------------------------------------------------------*/
311 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U)
312 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
313 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
321 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
322 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x00000000U)
330 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x00000000U)
331 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
332 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
333 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)
341 #define TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)
342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
346 
353 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)
354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
356 
363 #define TIM_OCMODE_TIMING ((uint32_t)0x00000000U)
364 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
365 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
366 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
367 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
368 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
369 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
370 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
371 
379 #define TIM_OCFAST_DISABLE ((uint32_t)0x00000000U)
380 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
381 
388 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)
389 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
390 
397 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x00000000U)
398 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
399 
406 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
407 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x00000000U)
408 
415 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
416 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x00000000U)
417 
424 #define TIM_CHANNEL_1 ((uint32_t)0x00000000U)
425 #define TIM_CHANNEL_2 ((uint32_t)0x00000004U)
426 #define TIM_CHANNEL_3 ((uint32_t)0x00000008U)
427 #define TIM_CHANNEL_4 ((uint32_t)0x0000000CU)
428 #define TIM_CHANNEL_ALL ((uint32_t)0x00000018U)
429 
437 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
438 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
439 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
440 
447 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
449 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
451 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)
460 #define TIM_ICPSC_DIV1 ((uint32_t)0x00000000U)
461 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
462 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
463 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)
471 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
472 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x00000000U)
473 
480 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
481 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
482 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
483 
491 #define TIM_IT_UPDATE (TIM_DIER_UIE)
492 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
493 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
494 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
495 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
496 #define TIM_IT_COM (TIM_DIER_COMIE)
497 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
498 #define TIM_IT_BREAK (TIM_DIER_BIE)
499 
506 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
507 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x00000000U)
508 
515 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
516 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
517 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
518 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
519 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
520 #define TIM_DMA_COM (TIM_DIER_COMDE)
521 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
522 
529 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
530 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
531 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
532 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
533 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
534 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
535 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
536 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
537 
545 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
546 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
547 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
548 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
549 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
550 #define TIM_FLAG_COM (TIM_SR_COMIF)
551 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
552 #define TIM_FLAG_BREAK (TIM_SR_BIF)
553 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
554 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
555 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
556 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
557 
564 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
565 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
566 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x00000000U)
567 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
568 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
569 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
570 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
571 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
572 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
573 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
574 
581 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
582 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
583 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
584 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
585 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
593 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
594 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
595 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
596 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
604 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x00000001U)
605 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x00000000U)
606 
613 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
614 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
622 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
623 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
624 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
625 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
633 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
634 #define TIM_OSSR_DISABLE ((uint32_t)0x00000000U)
635 
642 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
643 #define TIM_OSSI_DISABLE ((uint32_t)0x00000000U)
644 
651 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)
652 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
653 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
654 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
655 
661 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
662 #define TIM_BREAK_DISABLE ((uint32_t)0x00000000U)
663 
670 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x00000000U)
671 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
672 
679 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
680 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U)
681 
688 #define TIM_TRGO_RESET ((uint32_t)0x00000000U)
689 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
690 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
691 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
692 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
693 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
694 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
695 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
696 
703 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)
704 #define TIM_SLAVEMODE_RESET ((uint32_t)0x00000004U)
705 #define TIM_SLAVEMODE_GATED ((uint32_t)0x00000005U)
706 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x00000006U)
707 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x00000007U)
708 
715 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x00000080U)
716 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x00000000U)
717 
724 #define TIM_TS_ITR0 ((uint32_t)0x00000000U)
725 #define TIM_TS_ITR1 ((uint32_t)0x00000010U)
726 #define TIM_TS_ITR2 ((uint32_t)0x00000020U)
727 #define TIM_TS_ITR3 ((uint32_t)0x00000030U)
728 #define TIM_TS_TI1F_ED ((uint32_t)0x00000040U)
729 #define TIM_TS_TI1FP1 ((uint32_t)0x00000050U)
730 #define TIM_TS_TI2FP2 ((uint32_t)0x00000060U)
731 #define TIM_TS_ETRF ((uint32_t)0x00000070U)
732 #define TIM_TS_NONE ((uint32_t)0x0000FFFFU)
733 
740 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
741 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
742 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
743 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
744 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
752 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
753 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
754 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
755 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
764 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x00000000U)
765 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
766 
773 #define TIM_DMABASE_CR1 (0x00000000U)
774 #define TIM_DMABASE_CR2 (0x00000001U)
775 #define TIM_DMABASE_SMCR (0x00000002U)
776 #define TIM_DMABASE_DIER (0x00000003U)
777 #define TIM_DMABASE_SR (0x00000004U)
778 #define TIM_DMABASE_EGR (0x00000005U)
779 #define TIM_DMABASE_CCMR1 (0x00000006U)
780 #define TIM_DMABASE_CCMR2 (0x00000007U)
781 #define TIM_DMABASE_CCER (0x00000008U)
782 #define TIM_DMABASE_CNT (0x00000009U)
783 #define TIM_DMABASE_PSC (0x0000000AU)
784 #define TIM_DMABASE_ARR (0x0000000BU)
785 #define TIM_DMABASE_RCR (0x0000000CU)
786 #define TIM_DMABASE_CCR1 (0x0000000DU)
787 #define TIM_DMABASE_CCR2 (0x0000000EU)
788 #define TIM_DMABASE_CCR3 (0x0000000FU)
789 #define TIM_DMABASE_CCR4 (0x00000010U)
790 #define TIM_DMABASE_BDTR (0x00000011U)
791 #define TIM_DMABASE_DCR (0x00000012U)
792 #define TIM_DMABASE_OR (0x00000013U)
793 
800 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
801 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
802 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
803 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
804 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
805 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
806 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
807 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
808 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
809 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
810 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
811 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
812 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
813 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
814 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
815 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
816 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
817 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
818 
825 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000U)
826 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001U)
827 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002U)
828 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003U)
829 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004U)
830 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005U)
831 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006U)
839 #define TIM_CCx_ENABLE ((uint32_t)0x00000001U)
840 #define TIM_CCx_DISABLE ((uint32_t)0x00000000U)
841 #define TIM_CCxN_ENABLE ((uint32_t)0x00000004U)
842 #define TIM_CCxN_DISABLE ((uint32_t)0x00000000U)
843 
851 /* Exported macro ------------------------------------------------------------*/
859 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
860 
866 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
867 
873 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
874 
875 
881 #define __HAL_TIM_DISABLE(__HANDLE__) \
882  do { \
883  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
884  { \
885  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
886  { \
887  (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
888  } \
889  } \
890  } while(0)
891 
892 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
893  channels have been disabled */
899 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
900  do { \
901  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
902  { \
903  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
904  { \
905  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
906  } \
907  } \
908  } while(0)
909 
910 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
911 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
912 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
913 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
914 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
915 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
916 
917 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
918 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
919 
920 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
921 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
922 
923 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
924 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
925  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
926  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
927  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
928 
929 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
930 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
931  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
932  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
933  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
934 
935 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
936 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
937  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
938  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
939  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
940 
941 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
942 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
943  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
944  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
945  ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
946 
960 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
961 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
962 
974 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
975  (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
976 
983 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
984 
990 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
991 
999 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1000  do{ \
1001  (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1002  (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1003  } while(0)
1004 
1009 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1010 
1022 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1023  do{ \
1024  (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1025  (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1026  (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1027  } while(0)
1028 
1033 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1034 
1053 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1054  do{ \
1055  TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1056  TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1057  } while(0)
1058 
1070 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1071  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1072  ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1073  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1074  (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1075 
1084 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1085  ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1086 
1098 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1099  ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1100 
1117 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1118  do{ \
1119  TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1120  TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1121  }while(0)
1122 
1126 /* Include TIM HAL Extension module */
1127 #include "stm32f4xx_hal_tim_ex.h"
1128 
1129 /* Exported functions --------------------------------------------------------*/
1138 /* Time Base functions ********************************************************/
1139 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1140 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1141 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1142 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1143 /* Blocking mode: Polling */
1144 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1145 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1146 /* Non-Blocking mode: Interrupt */
1147 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1148 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1149 /* Non-Blocking mode: DMA */
1150 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1151 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1159 /* Timer Output Compare functions **********************************************/
1160 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1161 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1162 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1163 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1164 /* Blocking mode: Polling */
1165 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1166 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1167 /* Non-Blocking mode: Interrupt */
1168 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1169 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1170 /* Non-Blocking mode: DMA */
1171 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1172 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1173 
1181 /* Timer PWM functions *********************************************************/
1182 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1183 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1184 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1185 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1186 /* Blocking mode: Polling */
1187 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1188 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1189 /* Non-Blocking mode: Interrupt */
1190 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1191 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1192 /* Non-Blocking mode: DMA */
1193 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1194 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1195 
1203 /* Timer Input Capture functions ***********************************************/
1204 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1205 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1206 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1207 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1208 /* Blocking mode: Polling */
1209 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1210 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1211 /* Non-Blocking mode: Interrupt */
1212 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1213 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1214 /* Non-Blocking mode: DMA */
1215 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1216 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1217 
1225 /* Timer One Pulse functions ***************************************************/
1226 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1227 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1228 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1229 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1230 /* Blocking mode: Polling */
1231 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1232 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1233 
1234 /* Non-Blocking mode: Interrupt */
1235 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1236 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1237 
1245 /* Timer Encoder functions *****************************************************/
1246 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1247 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1248 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1249 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1250  /* Blocking mode: Polling */
1251 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1252 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1253 /* Non-Blocking mode: Interrupt */
1254 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1255 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1256 /* Non-Blocking mode: DMA */
1257 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1258 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1259 
1267 /* Interrupt Handler functions **********************************************/
1268 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1269 
1277 /* Control functions *********************************************************/
1278 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1279 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1280 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1281 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1282 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1283 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1284 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1285 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1286 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1287 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1288  uint32_t *BurstBuffer, uint32_t BurstLength);
1289 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1290 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1291  uint32_t *BurstBuffer, uint32_t BurstLength);
1292 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1293 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1294 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1295 
1303 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1304 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1305 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1306 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1307 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1308 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1309 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1310 
1318 /* Peripheral State functions **************************************************/
1319 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1320 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1321 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1322 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1323 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1324 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1325 
1334 /* Private macros ------------------------------------------------------------*/
1342 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
1343  ((MODE) == TIM_COUNTERMODE_DOWN) || \
1344  ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1345  ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1346  ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
1347 
1348 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
1349  ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
1350  ((DIV) == TIM_CLOCKDIVISION_DIV4))
1351 
1352 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
1353  ((MODE) == TIM_OCMODE_PWM2))
1354 
1355 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
1356  ((MODE) == TIM_OCMODE_ACTIVE) || \
1357  ((MODE) == TIM_OCMODE_INACTIVE) || \
1358  ((MODE) == TIM_OCMODE_TOGGLE) || \
1359  ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
1360  ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
1361 
1362 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
1363  ((STATE) == TIM_OCFAST_ENABLE))
1364 
1365 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
1366  ((POLARITY) == TIM_OCPOLARITY_LOW))
1367 
1368 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
1369  ((POLARITY) == TIM_OCNPOLARITY_LOW))
1370 
1371 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
1372  ((STATE) == TIM_OCIDLESTATE_RESET))
1373 
1374 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
1375  ((STATE) == TIM_OCNIDLESTATE_RESET))
1376 
1377 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
1378  ((CHANNEL) == TIM_CHANNEL_2) || \
1379  ((CHANNEL) == TIM_CHANNEL_3) || \
1380  ((CHANNEL) == TIM_CHANNEL_4) || \
1381  ((CHANNEL) == TIM_CHANNEL_ALL))
1382 
1383 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
1384  ((CHANNEL) == TIM_CHANNEL_2))
1385 
1386 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
1387  ((CHANNEL) == TIM_CHANNEL_2) || \
1388  ((CHANNEL) == TIM_CHANNEL_3))
1389 
1390 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
1391  ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
1392  ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
1393 
1394 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
1395  ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
1396  ((SELECTION) == TIM_ICSELECTION_TRC))
1397 
1398 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
1399  ((PRESCALER) == TIM_ICPSC_DIV2) || \
1400  ((PRESCALER) == TIM_ICPSC_DIV4) || \
1401  ((PRESCALER) == TIM_ICPSC_DIV8))
1402 
1403 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
1404  ((MODE) == TIM_OPMODE_REPETITIVE))
1405 
1406 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
1407 
1408 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
1409  ((MODE) == TIM_ENCODERMODE_TI2) || \
1410  ((MODE) == TIM_ENCODERMODE_TI12))
1411 
1412 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
1413 
1414 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
1415  ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
1416  ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
1417  ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
1418  ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
1419  ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
1420  ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
1421  ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
1422  ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
1423  ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
1424 
1425 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
1426  ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1427  ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
1428  ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
1429  ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
1430 
1431 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
1432  ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
1433  ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
1434  ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
1435 
1436 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1437 
1438 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
1439  ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
1440 
1441 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1442  ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1443 
1444 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1445  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1446  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1447  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
1448 
1449 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1450 
1451 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
1452  ((STATE) == TIM_OSSR_DISABLE))
1453 
1454 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
1455  ((STATE) == TIM_OSSI_DISABLE))
1456 
1457 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
1458  ((LEVEL) == TIM_LOCKLEVEL_1) || \
1459  ((LEVEL) == TIM_LOCKLEVEL_2) || \
1460  ((LEVEL) == TIM_LOCKLEVEL_3))
1461 
1462 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
1463  ((STATE) == TIM_BREAK_DISABLE))
1464 
1465 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
1466  ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
1467 
1468 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1469  ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
1470 
1471 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
1472  ((SOURCE) == TIM_TRGO_ENABLE) || \
1473  ((SOURCE) == TIM_TRGO_UPDATE) || \
1474  ((SOURCE) == TIM_TRGO_OC1) || \
1475  ((SOURCE) == TIM_TRGO_OC1REF) || \
1476  ((SOURCE) == TIM_TRGO_OC2REF) || \
1477  ((SOURCE) == TIM_TRGO_OC3REF) || \
1478  ((SOURCE) == TIM_TRGO_OC4REF))
1479 
1480 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
1481  ((MODE) == TIM_SLAVEMODE_GATED) || \
1482  ((MODE) == TIM_SLAVEMODE_RESET) || \
1483  ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
1484  ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
1485 
1486 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
1487  ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
1488 
1489 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1490  ((SELECTION) == TIM_TS_ITR1) || \
1491  ((SELECTION) == TIM_TS_ITR2) || \
1492  ((SELECTION) == TIM_TS_ITR3) || \
1493  ((SELECTION) == TIM_TS_TI1F_ED) || \
1494  ((SELECTION) == TIM_TS_TI1FP1) || \
1495  ((SELECTION) == TIM_TS_TI2FP2) || \
1496  ((SELECTION) == TIM_TS_ETRF))
1497 
1498 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1499  ((SELECTION) == TIM_TS_ITR1) || \
1500  ((SELECTION) == TIM_TS_ITR2) || \
1501  ((SELECTION) == TIM_TS_ITR3) || \
1502  ((SELECTION) == TIM_TS_NONE))
1503 
1504 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1505  ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1506  ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
1507  ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
1508  ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1509 
1510 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
1511  ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
1512  ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
1513  ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
1514 
1515 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
1516 
1517 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
1518  ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
1519 
1520 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
1521  ((BASE) == TIM_DMABASE_CR2) || \
1522  ((BASE) == TIM_DMABASE_SMCR) || \
1523  ((BASE) == TIM_DMABASE_DIER) || \
1524  ((BASE) == TIM_DMABASE_SR) || \
1525  ((BASE) == TIM_DMABASE_EGR) || \
1526  ((BASE) == TIM_DMABASE_CCMR1) || \
1527  ((BASE) == TIM_DMABASE_CCMR2) || \
1528  ((BASE) == TIM_DMABASE_CCER) || \
1529  ((BASE) == TIM_DMABASE_CNT) || \
1530  ((BASE) == TIM_DMABASE_PSC) || \
1531  ((BASE) == TIM_DMABASE_ARR) || \
1532  ((BASE) == TIM_DMABASE_RCR) || \
1533  ((BASE) == TIM_DMABASE_CCR1) || \
1534  ((BASE) == TIM_DMABASE_CCR2) || \
1535  ((BASE) == TIM_DMABASE_CCR3) || \
1536  ((BASE) == TIM_DMABASE_CCR4) || \
1537  ((BASE) == TIM_DMABASE_BDTR) || \
1538  ((BASE) == TIM_DMABASE_DCR) || \
1539  ((BASE) == TIM_DMABASE_OR))
1540 
1541 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1542  ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1543  ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1544  ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1545  ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1546  ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1547  ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1548  ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1549  ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1550  ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1551  ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1552  ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1553  ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1554  ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1555  ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1556  ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1557  ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1558  ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
1559 
1560 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
1561 
1568 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1569  channels have been disabled */
1570 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1571 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1572 
1580 /* Private functions ---------------------------------------------------------*/
1584 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1585 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1586 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1587 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1588 void TIM_DMAError(DMA_HandleTypeDef *hdma);
1589 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1590 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1603 #ifdef __cplusplus
1604 }
1605 #endif
1606 
1607 #endif /* __STM32F4xx_HAL_TIM_H */
1608 
1609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_TIM_StateTypeDef
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition: stm32f4xx_hal_tim.h:265
TIM_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f4xx_hal_tim.h:296
TIM_Encoder_InitTypeDef::IC2Filter
uint32_t IC2Filter
Definition: stm32f4xx_hal_tim.h:209
TIM_Base_InitTypeDef::RepetitionCounter
uint32_t RepetitionCounter
Definition: stm32f4xx_hal_tim.h:80
HAL_TIM_STATE_BUSY
Definition: stm32f4xx_hal_tim.h:269
TIM_IC_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32f4xx_hal_tim.h:175
TIM_IC_InitTypeDef::ICPrescaler
uint32_t ICPrescaler
Definition: stm32f4xx_hal_tim.h:172
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
TIM_Base_InitTypeDef::ClockDivision
uint32_t ClockDivision
Definition: stm32f4xx_hal_tim.h:77
TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition.
Definition: stm32f4xx_hal_tim.h:216
TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition.
Definition: stm32f4xx_hal_tim.h:94
TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition.
Definition: stm32f4xx_hal_tim.h:183
TIM_HandleTypeDef::Instance
TIM_TypeDef * Instance
Definition: stm32f4xx_hal_tim.h:291
TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition.
Definition: stm32f4xx_hal_tim.h:248
HAL_TIM_STATE_READY
Definition: stm32f4xx_hal_tim.h:268
TIM_HandleTypeDef::State
__IO HAL_TIM_StateTypeDef State
Definition: stm32f4xx_hal_tim.h:297
TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition.
Definition: stm32f4xx_hal_tim.h:65
HAL_TIM_ACTIVE_CHANNEL_3
Definition: stm32f4xx_hal_tim.h:281
TIM_Encoder_InitTypeDef::EncoderMode
uint32_t EncoderMode
Definition: stm32f4xx_hal_tim.h:185
TIM_SlaveConfigTypeDef::TriggerPrescaler
uint32_t TriggerPrescaler
Definition: stm32f4xx_hal_tim.h:255
TIM_OnePulse_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32f4xx_hal_tim.h:137
TIM_ClearInputConfigTypeDef::ClearInputSource
uint32_t ClearInputSource
Definition: stm32f4xx_hal_tim.h:235
TIM_OnePulse_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32f4xx_hal_tim.h:152
TIM_Encoder_InitTypeDef::IC2Selection
uint32_t IC2Selection
Definition: stm32f4xx_hal_tim.h:203
TIM_SlaveConfigTypeDef::TriggerPolarity
uint32_t TriggerPolarity
Definition: stm32f4xx_hal_tim.h:253
TIM_OnePulse_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32f4xx_hal_tim.h:145
TIM_OnePulse_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32f4xx_hal_tim.h:141
TIM_Encoder_InitTypeDef::IC1Filter
uint32_t IC1Filter
Definition: stm32f4xx_hal_tim.h:197
TIM_ClearInputConfigTypeDef::ClearInputPrescaler
uint32_t ClearInputPrescaler
Definition: stm32f4xx_hal_tim.h:239
TIM_HandleTypeDef::Init
TIM_Base_InitTypeDef Init
Definition: stm32f4xx_hal_tim.h:292
HAL_TIM_ACTIVE_CHANNEL_4
Definition: stm32f4xx_hal_tim.h:282
HAL_TIM_ACTIVE_CHANNEL_CLEARED
Definition: stm32f4xx_hal_tim.h:283
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f4xx_hal_def.h:57
__IO
#define __IO
Definition: core_cm0.h:213
TIM_ClockConfigTypeDef::ClockFilter
uint32_t ClockFilter
Definition: stm32f4xx_hal_tim.h:224
TIM_ClearInputConfigTypeDef
Clear Input Configuration Handle Structure definition.
Definition: stm32f4xx_hal_tim.h:231
TIM_OC_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32f4xx_hal_tim.h:102
TIM_OC_InitTypeDef::OCFastMode
uint32_t OCFastMode
Definition: stm32f4xx_hal_tim.h:109
TIM_SlaveConfigTypeDef::TriggerFilter
uint32_t TriggerFilter
Definition: stm32f4xx_hal_tim.h:257
TIM_Encoder_InitTypeDef::IC2Polarity
uint32_t IC2Polarity
Definition: stm32f4xx_hal_tim.h:200
HAL_TIM_STATE_ERROR
Definition: stm32f4xx_hal_tim.h:271
TIM_Encoder_InitTypeDef::IC1Selection
uint32_t IC1Selection
Definition: stm32f4xx_hal_tim.h:191
TIM_Encoder_InitTypeDef::IC1Prescaler
uint32_t IC1Prescaler
Definition: stm32f4xx_hal_tim.h:194
HAL_TIM_ActiveChannel
HAL_TIM_ActiveChannel
HAL Active channel structures definition.
Definition: stm32f4xx_hal_tim.h:277
TIM_Encoder_InitTypeDef::IC2Prescaler
uint32_t IC2Prescaler
Definition: stm32f4xx_hal_tim.h:206
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
TIM_ClearInputConfigTypeDef::ClearInputPolarity
uint32_t ClearInputPolarity
Definition: stm32f4xx_hal_tim.h:237
TIM_Base_InitTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32f4xx_hal_tim.h:67
TIM_OnePulse_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32f4xx_hal_tim.h:155
TIM_ClockConfigTypeDef::ClockPolarity
uint32_t ClockPolarity
Definition: stm32f4xx_hal_tim.h:220
TIM_OnePulse_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32f4xx_hal_tim.h:131
TIM_OnePulse_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32f4xx_hal_tim.h:128
TIM_HandleTypeDef::Channel
HAL_TIM_ActiveChannel Channel
Definition: stm32f4xx_hal_tim.h:293
TIM_IC_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32f4xx_hal_tim.h:166
HAL_TIM_STATE_TIMEOUT
Definition: stm32f4xx_hal_tim.h:270
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f4xx_hal_def.h:68
TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
Definition: stm32f4xx_hal_tim.h:289
TIM_OnePulse_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32f4xx_hal_tim.h:149
TIM_OC_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32f4xx_hal_tim.h:96
TIM_ClearInputConfigTypeDef::ClearInputFilter
uint32_t ClearInputFilter
Definition: stm32f4xx_hal_tim.h:241
TIM_ClockConfigTypeDef::ClockSource
uint32_t ClockSource
Definition: stm32f4xx_hal_tim.h:218
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:157
TIM_Encoder_InitTypeDef::IC1Polarity
uint32_t IC1Polarity
Definition: stm32f4xx_hal_tim.h:188
TIM_OnePulse_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32f4xx_hal_tim.h:134
TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition.
Definition: stm32f4xx_hal_tim.h:164
TIM_ClockConfigTypeDef::ClockPrescaler
uint32_t ClockPrescaler
Definition: stm32f4xx_hal_tim.h:222
TIM_OC_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32f4xx_hal_tim.h:118
TIM_IC_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32f4xx_hal_tim.h:169
TIM_OC_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32f4xx_hal_tim.h:114
HAL_TIM_ACTIVE_CHANNEL_1
Definition: stm32f4xx_hal_tim.h:279
HAL_TIM_STATE_RESET
Definition: stm32f4xx_hal_tim.h:267
TIM_OC_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32f4xx_hal_tim.h:99
HAL_TIM_ACTIVE_CHANNEL_2
Definition: stm32f4xx_hal_tim.h:280
TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition.
Definition: stm32f4xx_hal_tim.h:126
TIM_SlaveConfigTypeDef::InputTrigger
uint32_t InputTrigger
Definition: stm32f4xx_hal_tim.h:251
TIM_OC_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32f4xx_hal_tim.h:105
TIM_ClearInputConfigTypeDef::ClearInputState
uint32_t ClearInputState
Definition: stm32f4xx_hal_tim.h:233
TIM_Base_InitTypeDef::CounterMode
uint32_t CounterMode
Definition: stm32f4xx_hal_tim.h:70
TIM_Base_InitTypeDef::Period
uint32_t Period
Definition: stm32f4xx_hal_tim.h:73
HAL_TIM_PeriodElapsedCallback
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
Definition: stm32f4xx_hal_timebase_tim_template.c:163
TIM_SlaveConfigTypeDef::SlaveMode
uint32_t SlaveMode
Definition: stm32f4xx_hal_tim.h:249
stm32f4xx_hal_tim_ex.h
Header file of TIM HAL Extension module.