NVIC_Type Struct Reference

Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...

#include <core_cm0.h>

Public Attributes
__IOM uint32_t	ISER [1U]
uint32_t	RESERVED0 [31U]
__IOM uint32_t	ICER [1U]
uint32_t	RSERVED1 [31U]
__IOM uint32_t	ISPR [1U]
uint32_t	RESERVED2 [31U]
__IOM uint32_t	ICPR [1U]
uint32_t	RESERVED3 [31U]
uint32_t	RESERVED4 [64U]
__IOM uint32_t	IP [8U]
__IOM uint32_t	IABR [8U]
__IOM uint8_t	IP [240U]
uint32_t	RESERVED5 [644U]
__OM uint32_t	STIR

Detailed Description

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

Member Data Documentation

IABR

__IOM uint32_t NVIC_Type::IABR

Offset: 0x200 (R/W) Interrupt Active bit Register

ICER

__IOM uint32_t NVIC_Type::ICER

Offset: 0x080 (R/W) Interrupt Clear Enable Register

ICPR

__IOM uint32_t NVIC_Type::ICPR

Offset: 0x180 (R/W) Interrupt Clear Pending Register

IP [1/2]

__IOM uint8_t NVIC_Type::IP

Offset: 0x300 (R/W) Interrupt Priority Register

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

IP [2/2]

__IOM uint8_t NVIC_Type::IP[240U]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

ISER

__IOM uint32_t NVIC_Type::ISER

Offset: 0x000 (R/W) Interrupt Set Enable Register

ISPR

__IOM uint32_t NVIC_Type::ISPR

Offset: 0x100 (R/W) Interrupt Set Pending Register

STIR

__OM uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

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The documentation for this struct was generated from the following files:

• CMSIS/Include/core_cm0.h
• CMSIS/Include/core_cm0plus.h
• CMSIS/Include/core_cm3.h
• CMSIS/Include/core_cm4.h
• CMSIS/Include/core_cm7.h
• CMSIS/Include/core_sc000.h
• CMSIS/Include/core_sc300.h