|
STM CMSIS
|
CMSIS Cortex-M Core Function/Instruction Header File. More...
Go to the source code of this file.
Macros | |
| #define | __CMSIS_GCC_OUT_REG(r) "=r" (r) |
| #define | __CMSIS_GCC_USE_REG(r) "r" (r) |
| #define | __NOP __builtin_arm_nop |
| No Operation. More... | |
| #define | __WFI __builtin_arm_wfi |
| Wait For Interrupt. More... | |
| #define | __WFE __builtin_arm_wfe |
| Wait For Event. More... | |
| #define | __SEV __builtin_arm_sev |
| Send Event. More... | |
| #define | __ISB() __builtin_arm_isb(0xF); |
| Instruction Synchronization Barrier. More... | |
| #define | __DSB() __builtin_arm_dsb(0xF); |
| Data Synchronization Barrier. More... | |
| #define | __DMB() __builtin_arm_dmb(0xF); |
| Data Memory Barrier. More... | |
| #define | __REV __builtin_bswap32 |
| Reverse byte order (32 bit) More... | |
| #define | __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ |
| Reverse byte order (16 bit) More... | |
| #define | __BKPT(value) __ASM volatile ("bkpt "#value) |
| Breakpoint. More... | |
| #define | __CLZ __builtin_clz |
| Count leading zeros. More... | |
Functions | |
| __attribute__ ((always_inline)) __STATIC_INLINE void __enable_irq(void) | |
| Enable IRQ Interrupts. More... | |
| __attribute__ ((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) | |
| Reverse bit order of value. More... | |
Variables | |
| uint32_t | op2 |
CMSIS Cortex-M Core Function/Instruction Header File.