Classes
struct	ADC_TypeDef
	Analog to Digital Converter. More...

struct	ADC_Common_TypeDef

struct	CRC_TypeDef
	CRC calculation unit. More...

struct	DBGMCU_TypeDef
	Debug MCU. More...

struct	DMA_Stream_TypeDef
	DMA Controller. More...

struct	DMA_TypeDef

struct	EXTI_TypeDef
	External Interrupt/Event Controller. More...

struct	FLASH_TypeDef
	FLASH Registers. More...

struct	GPIO_TypeDef
	General Purpose I/O. More...

struct	SYSCFG_TypeDef
	System configuration controller. More...

struct	I2C_TypeDef
	Inter-integrated Circuit Interface. More...

struct	IWDG_TypeDef
	Independent WATCHDOG. More...

struct	PWR_TypeDef
	Power Control. More...

struct	RCC_TypeDef
	Reset and Clock Control. More...

struct	RTC_TypeDef
	Real-Time Clock. More...

struct	SDIO_TypeDef
	SD host Interface. More...

struct	SPI_TypeDef
	Serial Peripheral Interface. More...

struct	TIM_TypeDef
	TIM. More...

struct	USART_TypeDef
	Universal Synchronous Asynchronous Receiver Transmitter. More...

struct	WWDG_TypeDef
	Window WATCHDOG. More...

struct	USB_OTG_GlobalTypeDef
	__USB_OTG_Core_register More...

struct	USB_OTG_DeviceTypeDef
	__device_Registers More...

struct	USB_OTG_INEndpointTypeDef
	__IN_Endpoint-Specific_Register More...

struct	USB_OTG_OUTEndpointTypeDef
	__OUT_Endpoint-Specific_Registers More...

struct	USB_OTG_HostTypeDef
	__Host_Mode_Register_Structures More...

struct	USB_OTG_HostChannelTypeDef
	__Host_Channel_Specific_Registers More...

struct	CAN_TxMailBox_TypeDef
	Controller Area Network TxMailBox. More...

struct	CAN_FIFOMailBox_TypeDef
	Controller Area Network FIFOMailBox. More...

struct	CAN_FilterRegister_TypeDef
	Controller Area Network FilterRegister. More...

struct	CAN_TypeDef
	Controller Area Network. More...

struct	DAC_TypeDef
	Digital to Analog Converter. More...

struct	FSMC_Bank1_TypeDef
	Flexible Static Memory Controller. More...

struct	FSMC_Bank1E_TypeDef
	Flexible Static Memory Controller Bank1E. More...

struct	FSMC_Bank2_3_TypeDef
	Flexible Static Memory Controller Bank2. More...

struct	FSMC_Bank4_TypeDef
	Flexible Static Memory Controller Bank4. More...

struct	RNG_TypeDef
	RNG. More...

struct	DCMI_TypeDef
	DCMI. More...

struct	ETH_TypeDef
	Ethernet MAC. More...

struct	FMPI2C_TypeDef
	Inter-integrated Circuit Interface. More...

struct	LPTIM_TypeDef
	LPTIMER. More...

struct	DFSDM_Filter_TypeDef
	DFSDM module registers. More...

struct	DFSDM_Channel_TypeDef
	DFSDM channel configuration registers. More...

struct	QUADSPI_TypeDef
	QUAD Serial Peripheral Interface. More...

struct	CRYP_TypeDef
	Crypto Processor. More...

struct	HASH_TypeDef
	HASH. More...

struct	HASH_DIGEST_TypeDef
	HASH_DIGEST. More...

struct	DMA2D_TypeDef
	DMA2D Controller. More...

struct	FMC_Bank1_TypeDef
	Flexible Memory Controller. More...

struct	FMC_Bank1E_TypeDef
	Flexible Memory Controller Bank1E. More...

struct	FMC_Bank2_3_TypeDef
	Flexible Memory Controller Bank2. More...

struct	FMC_Bank4_TypeDef
	Flexible Memory Controller Bank4. More...

struct	FMC_Bank5_6_TypeDef
	Flexible Memory Controller Bank5_6. More...

struct	SAI_TypeDef
	Serial Audio Interface. More...

struct	SAI_Block_TypeDef

struct	LTDC_TypeDef
	LCD-TFT Display Controller. More...

struct	LTDC_Layer_TypeDef
	LCD-TFT Display layer x Controller. More...

struct	CEC_TypeDef
	Consumer Electronics Control. More...

struct	FMC_Bank3_TypeDef
	Flexible Memory Controller Bank3. More...

struct	SPDIFRX_TypeDef
	SPDIFRX Interface. More...

struct	DSI_TypeDef
	DSI Controller. More...

Macros
#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	BKPSRAM_BASE 0x40024000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	BKPSRAM_BB_BASE 0x42480000U

#define	FLASH_END 0x0803FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x3400U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	BKPSRAM_BASE 0x40024000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	BKPSRAM_BB_BASE 0x42480000U

#define	FLASH_END 0x0807FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x3400U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	CCMDATARAM_BASE 0x10000000U

#define	SRAM1_BASE 0x20000000U

#define	SRAM2_BASE 0x2001C000U

#define	PERIPH_BASE 0x40000000U

#define	BKPSRAM_BASE 0x40024000U

#define	FSMC_R_BASE 0xA0000000U

#define	SRAM1_BB_BASE 0x22000000U

#define	SRAM2_BB_BASE 0x22380000U

#define	PERIPH_BB_BASE 0x42000000U

#define	BKPSRAM_BB_BASE 0x42480000U

#define	FLASH_END 0x080FFFFFU

#define	CCMDATARAM_END 0x1000FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	USART3_BASE (APB1PERIPH_BASE + 0x4800U)

#define	UART4_BASE (APB1PERIPH_BASE + 0x4C00U)

#define	UART5_BASE (APB1PERIPH_BASE + 0x5000U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	DAC_BASE (APB1PERIPH_BASE + 0x7400U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC2_BASE (APB2PERIPH_BASE + 0x2100U)

#define	ADC3_BASE (APB2PERIPH_BASE + 0x2200U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)

#define	FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)

#define	FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)

#define	FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_HS_PERIPH_BASE 0x40040000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	CCMDATARAM_BASE 0x10000000U

#define	SRAM1_BASE 0x20000000U

#define	SRAM2_BASE 0x2001C000U

#define	PERIPH_BASE 0x40000000U

#define	BKPSRAM_BASE 0x40024000U

#define	FSMC_R_BASE 0xA0000000U

#define	SRAM1_BB_BASE 0x22000000U

#define	SRAM2_BB_BASE 0x22380000U

#define	PERIPH_BB_BASE 0x42000000U

#define	BKPSRAM_BB_BASE 0x42480000U

#define	FLASH_END 0x080FFFFFU

#define	CCMDATARAM_END 0x1000FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	USART3_BASE (APB1PERIPH_BASE + 0x4800U)

#define	UART4_BASE (APB1PERIPH_BASE + 0x4C00U)

#define	UART5_BASE (APB1PERIPH_BASE + 0x5000U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	DAC_BASE (APB1PERIPH_BASE + 0x7400U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC2_BASE (APB2PERIPH_BASE + 0x2100U)

#define	ADC3_BASE (APB2PERIPH_BASE + 0x2200U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	ETH_BASE (AHB1PERIPH_BASE + 0x8000U)

#define	ETH_MAC_BASE (ETH_BASE)

#define	ETH_MMC_BASE (ETH_BASE + 0x0100U)

#define	ETH_PTP_BASE (ETH_BASE + 0x0700U)

#define	ETH_DMA_BASE (ETH_BASE + 0x1000U)

#define	DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)

#define	FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)

#define	FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)

#define	FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_HS_PERIPH_BASE 0x40040000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	FLASH_END 0x0801FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	DAC_BASE (APB1PERIPH_BASE + 0x7400U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	SPI5_BASE (APB2PERIPH_BASE + 0x5000U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	RNG_BASE (PERIPH_BASE + 0x80000U)

#define	DBGMCU_BASE 0xE0042000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	FLASH_END 0x0801FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	DAC_BASE (APB1PERIPH_BASE + 0x7400U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	SPI5_BASE (APB2PERIPH_BASE + 0x5000U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	RNG_BASE (PERIPH_BASE + 0x80000U)

#define	DBGMCU_BASE 0xE0042000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	FLASH_END 0x0801FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	DAC_BASE (APB1PERIPH_BASE + 0x7400U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	RNG_BASE (PERIPH_BASE + 0x80000U)

#define	DBGMCU_BASE 0xE0042000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	BKPSRAM_BASE 0x40024000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	BKPSRAM_BB_BASE 0x42480000U

#define	FLASH_END 0x0807FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x3400U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	SPI5_BASE (APB2PERIPH_BASE + 0x5000U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	FLASH_END 0x080FFFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x3400U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	SPI5_BASE (APB2PERIPH_BASE + 0x5000U)

#define	DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)

#define	DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)

#define	DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)

#define	DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)

#define	DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)

#define	DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)

#define	DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	FSMC_R_BASE 0xA0000000U

#define	QSPI_R_BASE 0xA0001000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	FLASH_END 0x080FFFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	USART3_BASE (APB1PERIPH_BASE + 0x4800U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x3400U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	SPI5_BASE (APB2PERIPH_BASE + 0x5000U)

#define	DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)

#define	DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)

#define	DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)

#define	DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)

#define	DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)

#define	DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)

#define	DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)

#define	FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	FSMC_R_BASE 0xA0000000U

#define	QSPI_R_BASE 0xA0001000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	FLASH_END 0x080FFFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	USART3_BASE (APB1PERIPH_BASE + 0x4800U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x3400U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	SPI5_BASE (APB2PERIPH_BASE + 0x5000U)

#define	DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)

#define	DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)

#define	DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)

#define	DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)

#define	DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)

#define	DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)

#define	DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)

#define	FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	SRAM1_BASE 0x20000000U

#define	PERIPH_BASE 0x40000000U

#define	FSMC_R_BASE 0xA0000000U

#define	QSPI_R_BASE 0xA0001000U

#define	SRAM1_BB_BASE 0x22000000U

#define	PERIPH_BB_BASE 0x42000000U

#define	FLASH_END 0x080FFFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	USART3_BASE (APB1PERIPH_BASE + 0x4800U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x3400U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	SPI5_BASE (APB2PERIPH_BASE + 0x5000U)

#define	DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)

#define	DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)

#define	DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)

#define	DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)

#define	DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)

#define	DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)

#define	DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)

#define	FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	CCMDATARAM_BASE 0x10000000U

#define	SRAM1_BASE 0x20000000U

#define	SRAM2_BASE 0x2001C000U

#define	PERIPH_BASE 0x40000000U

#define	BKPSRAM_BASE 0x40024000U

#define	FSMC_R_BASE 0xA0000000U

#define	SRAM1_BB_BASE 0x22000000U

#define	SRAM2_BB_BASE 0x22380000U

#define	PERIPH_BB_BASE 0x42000000U

#define	BKPSRAM_BB_BASE 0x42480000U

#define	FLASH_END 0x080FFFFFU

#define	CCMDATARAM_END 0x1000FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	USART3_BASE (APB1PERIPH_BASE + 0x4800U)

#define	UART4_BASE (APB1PERIPH_BASE + 0x4C00U)

#define	UART5_BASE (APB1PERIPH_BASE + 0x5000U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	DAC_BASE (APB1PERIPH_BASE + 0x7400U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC2_BASE (APB2PERIPH_BASE + 0x2100U)

#define	ADC3_BASE (APB2PERIPH_BASE + 0x2200U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)

#define	HASH_BASE (AHB2PERIPH_BASE + 0x60400U)

#define	HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)

#define	FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)

#define	FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)

#define	FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_HS_PERIPH_BASE 0x40040000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

#define	FLASH_BASE 0x08000000U
	Peripheral_memory_map. More...

#define	CCMDATARAM_BASE 0x10000000U

#define	SRAM1_BASE 0x20000000U

#define	SRAM2_BASE 0x2001C000U

#define	PERIPH_BASE 0x40000000U

#define	BKPSRAM_BASE 0x40024000U

#define	FSMC_R_BASE 0xA0000000U

#define	SRAM1_BB_BASE 0x22000000U

#define	SRAM2_BB_BASE 0x22380000U

#define	PERIPH_BB_BASE 0x42000000U

#define	BKPSRAM_BB_BASE 0x42480000U

#define	FLASH_END 0x080FFFFFU

#define	CCMDATARAM_END 0x1000FFFFU

#define	SRAM_BASE SRAM1_BASE

#define	SRAM_BB_BASE SRAM1_BB_BASE

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x0000U)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x0400U)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x0800U)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x1400U)

#define	TIM12_BASE (APB1PERIPH_BASE + 0x1800U)

#define	TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)

#define	TIM14_BASE (APB1PERIPH_BASE + 0x2000U)

#define	RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x3800U)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)

#define	USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define	USART3_BASE (APB1PERIPH_BASE + 0x4800U)

#define	UART4_BASE (APB1PERIPH_BASE + 0x4C00U)

#define	UART5_BASE (APB1PERIPH_BASE + 0x5000U)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define	I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x6400U)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x6800U)

#define	PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define	DAC_BASE (APB1PERIPH_BASE + 0x7400U)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x0400U)

#define	USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define	USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define	ADC2_BASE (APB2PERIPH_BASE + 0x2100U)

#define	ADC3_BASE (APB2PERIPH_BASE + 0x2200U)

#define	ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define	SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define	TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define	TIM10_BASE (APB2PERIPH_BASE + 0x4400U)

#define	TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

#define	GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define	GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define	GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define	GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)

#define	GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)

#define	GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)

#define	GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)

#define	GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define	GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)

#define	CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define	DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define	DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define	DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define	DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define	DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define	DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define	DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define	DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define	DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define	DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define	DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define	DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define	DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define	DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define	DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define	DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define	ETH_BASE (AHB1PERIPH_BASE + 0x8000U)

#define	ETH_MAC_BASE (ETH_BASE)

#define	ETH_MMC_BASE (ETH_BASE + 0x0100U)

#define	ETH_PTP_BASE (ETH_BASE + 0x0700U)

#define	ETH_DMA_BASE (ETH_BASE + 0x1000U)

#define	DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)

#define	CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)

#define	HASH_BASE (AHB2PERIPH_BASE + 0x60400U)

#define	HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)

#define	RNG_BASE (AHB2PERIPH_BASE + 0x60800U)

#define	FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)

#define	FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)

#define	FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)

#define	FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)

#define	DBGMCU_BASE 0xE0042000U

#define	USB_OTG_HS_PERIPH_BASE 0x40040000U

#define	USB_OTG_FS_PERIPH_BASE 0x50000000U

#define	USB_OTG_GLOBAL_BASE 0x000U

#define	USB_OTG_DEVICE_BASE 0x800U

#define	USB_OTG_IN_ENDPOINT_BASE 0x900U

#define	USB_OTG_OUT_ENDPOINT_BASE 0xB00U

#define	USB_OTG_EP_REG_SIZE 0x20U

#define	USB_OTG_HOST_BASE 0x400U

#define	USB_OTG_HOST_PORT_BASE 0x440U

#define	USB_OTG_HOST_CHANNEL_BASE 0x500U

#define	USB_OTG_HOST_CHANNEL_SIZE 0x20U

#define	USB_OTG_PCGCCTL_BASE 0xE00U

#define	USB_OTG_FIFO_BASE 0x1000U

#define	USB_OTG_FIFO_SIZE 0x1000U

Detailed Description

Macro Definition Documentation

◆ AHB1PERIPH_BASE [1/3]

#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

APB1 peripherals

◆ AHB1PERIPH_BASE [2/3]

#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

APB1 peripherals

◆ AHB1PERIPH_BASE [3/3]

#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [1/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [2/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [3/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [4/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [5/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [6/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [7/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [8/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [9/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [10/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ AHB2PERIPH_BASE [11/11]

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)

APB1 peripherals

◆ BKPSRAM_BASE [1/7]

#define BKPSRAM_BASE 0x40024000U

Backup SRAM(4 KB) base address in the alias region

◆ BKPSRAM_BASE [2/7]

#define BKPSRAM_BASE 0x40024000U

Backup SRAM(4 KB) base address in the alias region

◆ BKPSRAM_BASE [3/7]

#define BKPSRAM_BASE 0x40024000U

Backup SRAM(4 KB) base address in the alias region

◆ BKPSRAM_BASE [4/7]

#define BKPSRAM_BASE 0x40024000U

Backup SRAM(4 KB) base address in the alias region

◆ BKPSRAM_BASE [5/7]

#define BKPSRAM_BASE 0x40024000U

Backup SRAM(4 KB) base address in the alias region

◆ BKPSRAM_BASE [6/7]

#define BKPSRAM_BASE 0x40024000U

Backup SRAM(4 KB) base address in the alias region

◆ BKPSRAM_BASE [7/7]

#define BKPSRAM_BASE 0x40024000U

Backup SRAM(4 KB) base address in the alias region

◆ BKPSRAM_BB_BASE [1/7]

#define BKPSRAM_BB_BASE 0x42480000U

Backup SRAM(4 KB) base address in the bit-band region

◆ BKPSRAM_BB_BASE [2/7]

#define BKPSRAM_BB_BASE 0x42480000U

Backup SRAM(4 KB) base address in the bit-band region

◆ BKPSRAM_BB_BASE [3/7]

#define BKPSRAM_BB_BASE 0x42480000U

Backup SRAM(4 KB) base address in the bit-band region

◆ BKPSRAM_BB_BASE [4/7]

#define BKPSRAM_BB_BASE 0x42480000U

Backup SRAM(4 KB) base address in the bit-band region

◆ BKPSRAM_BB_BASE [5/7]

#define BKPSRAM_BB_BASE 0x42480000U

Backup SRAM(4 KB) base address in the bit-band region

◆ BKPSRAM_BB_BASE [6/7]

#define BKPSRAM_BB_BASE 0x42480000U

Backup SRAM(4 KB) base address in the bit-band region

◆ BKPSRAM_BB_BASE [7/7]

#define BKPSRAM_BB_BASE 0x42480000U

Backup SRAM(4 KB) base address in the bit-band region

◆ CCMDATARAM_BASE [1/4]

#define CCMDATARAM_BASE 0x10000000U

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

◆ CCMDATARAM_BASE [2/4]

#define CCMDATARAM_BASE 0x10000000U

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

◆ CCMDATARAM_BASE [3/4]

#define CCMDATARAM_BASE 0x10000000U

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

◆ CCMDATARAM_BASE [4/4]

#define CCMDATARAM_BASE 0x10000000U

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

◆ CCMDATARAM_END [1/4]

#define CCMDATARAM_END 0x1000FFFFU

CCM data RAM end address

◆ CCMDATARAM_END [2/4]

#define CCMDATARAM_END 0x1000FFFFU

CCM data RAM end address

◆ CCMDATARAM_END [3/4]

#define CCMDATARAM_END 0x1000FFFFU

CCM data RAM end address

◆ CCMDATARAM_END [4/4]

#define CCMDATARAM_END 0x1000FFFFU

CCM data RAM end address

◆ DAC_BASE [1/7]

#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)

APB2 peripherals

◆ DAC_BASE [2/7]

#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)

APB2 peripherals

◆ DAC_BASE [3/7]

#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)

APB2 peripherals

◆ DAC_BASE [4/7]

#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)

APB2 peripherals

◆ DAC_BASE [5/7]

#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)

APB2 peripherals

◆ DAC_BASE [6/7]

#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)

APB2 peripherals

◆ DAC_BASE [7/7]

#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)

APB2 peripherals

◆ DBGMCU_BASE [1/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [2/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [3/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [4/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [5/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [6/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [7/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [8/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [9/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [10/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DBGMCU_BASE [11/11]

#define DBGMCU_BASE 0xE0042000U

USB registers base address

◆ DFSDM1_Filter1_BASE [1/4]

#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)

AHB1 peripherals

◆ DFSDM1_Filter1_BASE [2/4]

#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)

AHB1 peripherals

◆ DFSDM1_Filter1_BASE [3/4]

#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)

AHB1 peripherals

◆ DFSDM1_Filter1_BASE [4/4]

#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)

AHB1 peripherals

◆ DMA2_Stream7_BASE [1/6]

#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

AHB2 peripherals

◆ DMA2_Stream7_BASE [2/6]

#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

AHB2 peripherals

◆ DMA2_Stream7_BASE [3/6]

#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

AHB2 peripherals

◆ DMA2_Stream7_BASE [4/6]

#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

AHB2 peripherals

◆ DMA2_Stream7_BASE [5/6]

#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

AHB2 peripherals

◆ DMA2_Stream7_BASE [6/6]

#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

AHB2 peripherals

◆ ETH_DMA_BASE [1/2]

#define ETH_DMA_BASE (ETH_BASE + 0x1000U)

AHB2 peripherals

◆ ETH_DMA_BASE [2/2]

#define ETH_DMA_BASE (ETH_BASE + 0x1000U)

AHB2 peripherals

◆ FLASH_BASE [1/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [2/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [3/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [4/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [5/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [6/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [7/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [8/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [9/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [10/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [11/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [12/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [13/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_BASE [14/14]

#define FLASH_BASE 0x08000000U

Peripheral_memory_map.

FLASH(up to 1 MB) base address in the alias region

◆ FLASH_END [1/14]

#define FLASH_END 0x0801FFFFU

FLASH end address

◆ FLASH_END [2/14]

#define FLASH_END 0x0801FFFFU

FLASH end address

◆ FLASH_END [3/14]

#define FLASH_END 0x0801FFFFU

FLASH end address

◆ FLASH_END [4/14]

#define FLASH_END 0x0807FFFFU

FLASH end address

◆ FLASH_END [5/14]

#define FLASH_END 0x0803FFFFU

FLASH end address

◆ FLASH_END [6/14]

#define FLASH_END 0x0807FFFFU

FLASH end address

◆ FLASH_END [7/14]

#define FLASH_END 0x080FFFFFU

FLASH end address

◆ FLASH_END [8/14]

#define FLASH_END 0x080FFFFFU

FLASH end address

◆ FLASH_END [9/14]

#define FLASH_END 0x080FFFFFU

FLASH end address

◆ FLASH_END [10/14]

#define FLASH_END 0x080FFFFFU

FLASH end address

◆ FLASH_END [11/14]

#define FLASH_END 0x080FFFFFU

FLASH end address

◆ FLASH_END [12/14]

#define FLASH_END 0x080FFFFFU

FLASH end address

◆ FLASH_END [13/14]

#define FLASH_END 0x080FFFFFU

FLASH end address

◆ FLASH_END [14/14]

#define FLASH_END 0x080FFFFFU

FLASH end address

◆ FSMC_R_BASE [1/7]

#define FSMC_R_BASE 0xA0000000U

FSMC registers base address

◆ FSMC_R_BASE [2/7]

#define FSMC_R_BASE 0xA0000000U

FSMC registers base address

◆ FSMC_R_BASE [3/7]

#define FSMC_R_BASE 0xA0000000U

FSMC registers base address

◆ FSMC_R_BASE [4/7]

#define FSMC_R_BASE 0xA0000000U

FSMC registers base address

◆ FSMC_R_BASE [5/7]

#define FSMC_R_BASE 0xA0000000U

FSMC registers base address

◆ FSMC_R_BASE [6/7]

#define FSMC_R_BASE 0xA0000000U

FSMC registers base address

◆ FSMC_R_BASE [7/7]

#define FSMC_R_BASE 0xA0000000U

FSMC registers base address

◆ PERIPH_BASE [1/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [2/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [3/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [4/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [5/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [6/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [7/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [8/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [9/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [10/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [11/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [12/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region

◆ PERIPH_BASE [13/14]

#define PERIPH_BASE 0x40000000U

Peripheral base address in the alias region