- Generated by
1.8.13
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STM CMSIS
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Analog to Digital Converter. More...
#include <stm32f401xc.h>
Public Attributes | |
| __IO uint32_t | SR |
| __IO uint32_t | CR1 |
| __IO uint32_t | CR2 |
| __IO uint32_t | SMPR1 |
| __IO uint32_t | SMPR2 |
| __IO uint32_t | JOFR1 |
| __IO uint32_t | JOFR2 |
| __IO uint32_t | JOFR3 |
| __IO uint32_t | JOFR4 |
| __IO uint32_t | HTR |
| __IO uint32_t | LTR |
| __IO uint32_t | SQR1 |
| __IO uint32_t | SQR2 |
| __IO uint32_t | SQR3 |
| __IO uint32_t | JSQR |
| __IO uint32_t | JDR1 |
| __IO uint32_t | JDR2 |
| __IO uint32_t | JDR3 |
| __IO uint32_t | JDR4 |
| __IO uint32_t | DR |
Analog to Digital Converter.
| __IO uint32_t ADC_TypeDef::CR1 |
ADC control register 1, Address offset: 0x04
| __IO uint32_t ADC_TypeDef::CR2 |
ADC control register 2, Address offset: 0x08
| __IO uint32_t ADC_TypeDef::DR |
ADC regular data register, Address offset: 0x4C
| __IO uint32_t ADC_TypeDef::HTR |
ADC watchdog higher threshold register, Address offset: 0x24
| __IO uint32_t ADC_TypeDef::JDR1 |
ADC injected data register 1, Address offset: 0x3C
| __IO uint32_t ADC_TypeDef::JDR2 |
ADC injected data register 2, Address offset: 0x40
| __IO uint32_t ADC_TypeDef::JDR3 |
ADC injected data register 3, Address offset: 0x44
| __IO uint32_t ADC_TypeDef::JDR4 |
ADC injected data register 4, Address offset: 0x48
| __IO uint32_t ADC_TypeDef::JOFR1 |
ADC injected channel data offset register 1, Address offset: 0x14
| __IO uint32_t ADC_TypeDef::JOFR2 |
ADC injected channel data offset register 2, Address offset: 0x18
| __IO uint32_t ADC_TypeDef::JOFR3 |
ADC injected channel data offset register 3, Address offset: 0x1C
| __IO uint32_t ADC_TypeDef::JOFR4 |
ADC injected channel data offset register 4, Address offset: 0x20
| __IO uint32_t ADC_TypeDef::JSQR |
ADC injected sequence register, Address offset: 0x38
| __IO uint32_t ADC_TypeDef::LTR |
ADC watchdog lower threshold register, Address offset: 0x28
| __IO uint32_t ADC_TypeDef::SMPR1 |
ADC sample time register 1, Address offset: 0x0C
| __IO uint32_t ADC_TypeDef::SMPR2 |
ADC sample time register 2, Address offset: 0x10
| __IO uint32_t ADC_TypeDef::SQR1 |
ADC regular sequence register 1, Address offset: 0x2C
| __IO uint32_t ADC_TypeDef::SQR2 |
ADC regular sequence register 2, Address offset: 0x30
| __IO uint32_t ADC_TypeDef::SQR3 |
ADC regular sequence register 3, Address offset: 0x34
| __IO uint32_t ADC_TypeDef::SR |
ADC status register, Address offset: 0x00
1.8.13