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RCC_TypeDef Struct Reference
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Reset and Clock Control. More...

#include <stm32f401xc.h>

Public Attributes

__IO uint32_t CR
 
__IO uint32_t PLLCFGR
 
__IO uint32_t CFGR
 
__IO uint32_t CIR
 
__IO uint32_t AHB1RSTR
 
__IO uint32_t AHB2RSTR
 
__IO uint32_t AHB3RSTR
 
uint32_t RESERVED0
 
__IO uint32_t APB1RSTR
 
__IO uint32_t APB2RSTR
 
uint32_t RESERVED1 [2]
 
__IO uint32_t AHB1ENR
 
__IO uint32_t AHB2ENR
 
__IO uint32_t AHB3ENR
 
uint32_t RESERVED2
 
__IO uint32_t APB1ENR
 
__IO uint32_t APB2ENR
 
uint32_t RESERVED3 [2]
 
__IO uint32_t AHB1LPENR
 
__IO uint32_t AHB2LPENR
 
__IO uint32_t AHB3LPENR
 
uint32_t RESERVED4
 
__IO uint32_t APB1LPENR
 
__IO uint32_t APB2LPENR
 
uint32_t RESERVED5 [2]
 
__IO uint32_t BDCR
 
__IO uint32_t CSR
 
uint32_t RESERVED6 [2]
 
__IO uint32_t SSCGR
 
__IO uint32_t PLLI2SCFGR
 
uint32_t RESERVED7 [1]
 
__IO uint32_t DCKCFGR
 
__IO uint32_t CKGATENR
 
__IO uint32_t DCKCFGR2
 
__IO uint32_t PLLSAICFGR
 

Detailed Description

Reset and Clock Control.

Member Data Documentation

◆ AHB1ENR

__IO uint32_t RCC_TypeDef::AHB1ENR

RCC AHB1 peripheral clock register, Address offset: 0x30

◆ AHB1LPENR

__IO uint32_t RCC_TypeDef::AHB1LPENR

RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50

◆ AHB1RSTR

__IO uint32_t RCC_TypeDef::AHB1RSTR

RCC AHB1 peripheral reset register, Address offset: 0x10

◆ AHB2ENR

__IO uint32_t RCC_TypeDef::AHB2ENR

RCC AHB2 peripheral clock register, Address offset: 0x34

◆ AHB2LPENR

__IO uint32_t RCC_TypeDef::AHB2LPENR

RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54

◆ AHB2RSTR

__IO uint32_t RCC_TypeDef::AHB2RSTR

RCC AHB2 peripheral reset register, Address offset: 0x14

◆ AHB3ENR

__IO uint32_t RCC_TypeDef::AHB3ENR

RCC AHB3 peripheral clock register, Address offset: 0x38

◆ AHB3LPENR

__IO uint32_t RCC_TypeDef::AHB3LPENR

RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58

◆ AHB3RSTR

__IO uint32_t RCC_TypeDef::AHB3RSTR

RCC AHB3 peripheral reset register, Address offset: 0x18

◆ APB1ENR

__IO uint32_t RCC_TypeDef::APB1ENR

RCC APB1 peripheral clock enable register, Address offset: 0x40

◆ APB1LPENR

__IO uint32_t RCC_TypeDef::APB1LPENR

RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60

◆ APB1RSTR

__IO uint32_t RCC_TypeDef::APB1RSTR

RCC APB1 peripheral reset register, Address offset: 0x20

◆ APB2ENR

__IO uint32_t RCC_TypeDef::APB2ENR

RCC APB2 peripheral clock enable register, Address offset: 0x44

◆ APB2LPENR

__IO uint32_t RCC_TypeDef::APB2LPENR

RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64

◆ APB2RSTR

__IO uint32_t RCC_TypeDef::APB2RSTR

RCC APB2 peripheral reset register, Address offset: 0x24

◆ BDCR

__IO uint32_t RCC_TypeDef::BDCR

RCC Backup domain control register, Address offset: 0x70

◆ CFGR

__IO uint32_t RCC_TypeDef::CFGR

RCC clock configuration register, Address offset: 0x08

◆ CIR

__IO uint32_t RCC_TypeDef::CIR

RCC clock interrupt register, Address offset: 0x0C

◆ CKGATENR

__IO uint32_t RCC_TypeDef::CKGATENR

RCC Clocks Gated ENable Register, Address offset: 0x90

◆ CR

__IO uint32_t RCC_TypeDef::CR

RCC clock control register, Address offset: 0x00

◆ CSR

__IO uint32_t RCC_TypeDef::CSR

RCC clock control & status register, Address offset: 0x74

◆ DCKCFGR

__IO uint32_t RCC_TypeDef::DCKCFGR

RCC DCKCFGR configuration register, Address offset: 0x8C

RCC Dedicated Clocks configuration register, Address offset: 0x8C

◆ DCKCFGR2

__IO uint32_t RCC_TypeDef::DCKCFGR2

RCC Dedicated Clocks configuration register 2, Address offset: 0x94

◆ PLLCFGR

__IO uint32_t RCC_TypeDef::PLLCFGR

RCC PLL configuration register, Address offset: 0x04

◆ PLLI2SCFGR

__IO uint32_t RCC_TypeDef::PLLI2SCFGR

RCC PLLI2S configuration register, Address offset: 0x84

◆ PLLSAICFGR

__IO uint32_t RCC_TypeDef::PLLSAICFGR

RCC PLLSAI configuration register, Address offset: 0x88

◆ RESERVED0

uint32_t RCC_TypeDef::RESERVED0

Reserved, 0x1C

Reserved, 0x14-0x1C

Reserved, 0x18-0x1C

◆ RESERVED1

uint32_t RCC_TypeDef::RESERVED1

Reserved, 0x28-0x2C

◆ RESERVED2

uint32_t RCC_TypeDef::RESERVED2

Reserved, 0x3C

Reserved, 0x34-0x3C

Reserved, 0x38-0x3C

◆ RESERVED3

uint32_t RCC_TypeDef::RESERVED3

Reserved, 0x48-0x4C

◆ RESERVED4

uint32_t RCC_TypeDef::RESERVED4

Reserved, 0x5C

Reserved, 0x54-0x5C

Reserved, 0x58-0x5C

◆ RESERVED5

uint32_t RCC_TypeDef::RESERVED5

Reserved, 0x68-0x6C

◆ RESERVED6

uint32_t RCC_TypeDef::RESERVED6

Reserved, 0x78-0x7C

◆ RESERVED7

uint32_t RCC_TypeDef::RESERVED7

Reserved, 0x88

Reserved, 0x84-0x88

Reserved, 0x84

◆ SSCGR

__IO uint32_t RCC_TypeDef::SSCGR

RCC spread spectrum clock generation register, Address offset: 0x80

The documentation for this struct was generated from the following files: