STM CMSIS
stm32f401xe.h
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1 
52 #ifndef __STM32F401xE_H
53 #define __STM32F401xE_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  EXTI9_5_IRQn = 23,
117  TIM1_BRK_TIM9_IRQn = 24,
118  TIM1_UP_TIM10_IRQn = 25,
119  TIM1_TRG_COM_TIM11_IRQn = 26,
120  TIM1_CC_IRQn = 27,
121  TIM2_IRQn = 28,
122  TIM3_IRQn = 29,
123  TIM4_IRQn = 30,
124  I2C1_EV_IRQn = 31,
125  I2C1_ER_IRQn = 32,
126  I2C2_EV_IRQn = 33,
127  I2C2_ER_IRQn = 34,
128  SPI1_IRQn = 35,
129  SPI2_IRQn = 36,
130  USART1_IRQn = 37,
131  USART2_IRQn = 38,
132  EXTI15_10_IRQn = 40,
133  RTC_Alarm_IRQn = 41,
134  OTG_FS_WKUP_IRQn = 42,
135  DMA1_Stream7_IRQn = 47,
136  SDIO_IRQn = 49,
137  TIM5_IRQn = 50,
138  SPI3_IRQn = 51,
139  DMA2_Stream0_IRQn = 56,
140  DMA2_Stream1_IRQn = 57,
141  DMA2_Stream2_IRQn = 58,
142  DMA2_Stream3_IRQn = 59,
143  DMA2_Stream4_IRQn = 60,
144  OTG_FS_IRQn = 67,
145  DMA2_Stream5_IRQn = 68,
146  DMA2_Stream6_IRQn = 69,
147  DMA2_Stream7_IRQn = 70,
148  USART6_IRQn = 71,
149  I2C3_EV_IRQn = 72,
150  I2C3_ER_IRQn = 73,
151  FPU_IRQn = 81,
152  SPI4_IRQn = 84
153 } IRQn_Type;
154 
159 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
160 #include "system_stm32f4xx.h"
161 #include <stdint.h>
162 
171 typedef struct
172 {
173  __IO uint32_t SR;
174  __IO uint32_t CR1;
175  __IO uint32_t CR2;
176  __IO uint32_t SMPR1;
177  __IO uint32_t SMPR2;
178  __IO uint32_t JOFR1;
179  __IO uint32_t JOFR2;
180  __IO uint32_t JOFR3;
181  __IO uint32_t JOFR4;
182  __IO uint32_t HTR;
183  __IO uint32_t LTR;
184  __IO uint32_t SQR1;
185  __IO uint32_t SQR2;
186  __IO uint32_t SQR3;
187  __IO uint32_t JSQR;
188  __IO uint32_t JDR1;
189  __IO uint32_t JDR2;
190  __IO uint32_t JDR3;
191  __IO uint32_t JDR4;
192  __IO uint32_t DR;
193 } ADC_TypeDef;
194 
195 typedef struct
196 {
197  __IO uint32_t CSR;
198  __IO uint32_t CCR;
199  __IO uint32_t CDR;
201 } ADC_Common_TypeDef;
202 
207 typedef struct
208 {
209  __IO uint32_t DR;
210  __IO uint8_t IDR;
211  uint8_t RESERVED0;
212  uint16_t RESERVED1;
213  __IO uint32_t CR;
214 } CRC_TypeDef;
215 
220 typedef struct
221 {
222  __IO uint32_t IDCODE;
223  __IO uint32_t CR;
224  __IO uint32_t APB1FZ;
225  __IO uint32_t APB2FZ;
226 }DBGMCU_TypeDef;
227 
228 
233 typedef struct
234 {
235  __IO uint32_t CR;
236  __IO uint32_t NDTR;
237  __IO uint32_t PAR;
238  __IO uint32_t M0AR;
239  __IO uint32_t M1AR;
240  __IO uint32_t FCR;
241 } DMA_Stream_TypeDef;
242 
243 typedef struct
244 {
245  __IO uint32_t LISR;
246  __IO uint32_t HISR;
247  __IO uint32_t LIFCR;
248  __IO uint32_t HIFCR;
249 } DMA_TypeDef;
250 
251 
256 typedef struct
257 {
258  __IO uint32_t IMR;
259  __IO uint32_t EMR;
260  __IO uint32_t RTSR;
261  __IO uint32_t FTSR;
262  __IO uint32_t SWIER;
263  __IO uint32_t PR;
264 } EXTI_TypeDef;
265 
270 typedef struct
271 {
272  __IO uint32_t ACR;
273  __IO uint32_t KEYR;
274  __IO uint32_t OPTKEYR;
275  __IO uint32_t SR;
276  __IO uint32_t CR;
277  __IO uint32_t OPTCR;
278  __IO uint32_t OPTCR1;
279 } FLASH_TypeDef;
280 
285 typedef struct
286 {
287  __IO uint32_t MODER;
288  __IO uint32_t OTYPER;
289  __IO uint32_t OSPEEDR;
290  __IO uint32_t PUPDR;
291  __IO uint32_t IDR;
292  __IO uint32_t ODR;
293  __IO uint32_t BSRR;
294  __IO uint32_t LCKR;
295  __IO uint32_t AFR[2];
296 } GPIO_TypeDef;
297 
302 typedef struct
303 {
304  __IO uint32_t MEMRMP;
305  __IO uint32_t PMC;
306  __IO uint32_t EXTICR[4];
307  uint32_t RESERVED[2];
308  __IO uint32_t CMPCR;
309 } SYSCFG_TypeDef;
310 
315 typedef struct
316 {
317  __IO uint32_t CR1;
318  __IO uint32_t CR2;
319  __IO uint32_t OAR1;
320  __IO uint32_t OAR2;
321  __IO uint32_t DR;
322  __IO uint32_t SR1;
323  __IO uint32_t SR2;
324  __IO uint32_t CCR;
325  __IO uint32_t TRISE;
326  __IO uint32_t FLTR;
327 } I2C_TypeDef;
328 
333 typedef struct
334 {
335  __IO uint32_t KR;
336  __IO uint32_t PR;
337  __IO uint32_t RLR;
338  __IO uint32_t SR;
339 } IWDG_TypeDef;
340 
345 typedef struct
346 {
347  __IO uint32_t CR;
348  __IO uint32_t CSR;
349 } PWR_TypeDef;
350 
355 typedef struct
356 {
357  __IO uint32_t CR;
358  __IO uint32_t PLLCFGR;
359  __IO uint32_t CFGR;
360  __IO uint32_t CIR;
361  __IO uint32_t AHB1RSTR;
362  __IO uint32_t AHB2RSTR;
363  __IO uint32_t AHB3RSTR;
364  uint32_t RESERVED0;
365  __IO uint32_t APB1RSTR;
366  __IO uint32_t APB2RSTR;
367  uint32_t RESERVED1[2];
368  __IO uint32_t AHB1ENR;
369  __IO uint32_t AHB2ENR;
370  __IO uint32_t AHB3ENR;
371  uint32_t RESERVED2;
372  __IO uint32_t APB1ENR;
373  __IO uint32_t APB2ENR;
374  uint32_t RESERVED3[2];
375  __IO uint32_t AHB1LPENR;
376  __IO uint32_t AHB2LPENR;
377  __IO uint32_t AHB3LPENR;
378  uint32_t RESERVED4;
379  __IO uint32_t APB1LPENR;
380  __IO uint32_t APB2LPENR;
381  uint32_t RESERVED5[2];
382  __IO uint32_t BDCR;
383  __IO uint32_t CSR;
384  uint32_t RESERVED6[2];
385  __IO uint32_t SSCGR;
386  __IO uint32_t PLLI2SCFGR;
387  uint32_t RESERVED7[1];
388  __IO uint32_t DCKCFGR;
389 } RCC_TypeDef;
390 
395 typedef struct
396 {
397  __IO uint32_t TR;
398  __IO uint32_t DR;
399  __IO uint32_t CR;
400  __IO uint32_t ISR;
401  __IO uint32_t PRER;
402  __IO uint32_t WUTR;
403  __IO uint32_t CALIBR;
404  __IO uint32_t ALRMAR;
405  __IO uint32_t ALRMBR;
406  __IO uint32_t WPR;
407  __IO uint32_t SSR;
408  __IO uint32_t SHIFTR;
409  __IO uint32_t TSTR;
410  __IO uint32_t TSDR;
411  __IO uint32_t TSSSR;
412  __IO uint32_t CALR;
413  __IO uint32_t TAFCR;
414  __IO uint32_t ALRMASSR;
415  __IO uint32_t ALRMBSSR;
416  uint32_t RESERVED7;
417  __IO uint32_t BKP0R;
418  __IO uint32_t BKP1R;
419  __IO uint32_t BKP2R;
420  __IO uint32_t BKP3R;
421  __IO uint32_t BKP4R;
422  __IO uint32_t BKP5R;
423  __IO uint32_t BKP6R;
424  __IO uint32_t BKP7R;
425  __IO uint32_t BKP8R;
426  __IO uint32_t BKP9R;
427  __IO uint32_t BKP10R;
428  __IO uint32_t BKP11R;
429  __IO uint32_t BKP12R;
430  __IO uint32_t BKP13R;
431  __IO uint32_t BKP14R;
432  __IO uint32_t BKP15R;
433  __IO uint32_t BKP16R;
434  __IO uint32_t BKP17R;
435  __IO uint32_t BKP18R;
436  __IO uint32_t BKP19R;
437 } RTC_TypeDef;
438 
439 
444 typedef struct
445 {
446  __IO uint32_t POWER;
447  __IO uint32_t CLKCR;
448  __IO uint32_t ARG;
449  __IO uint32_t CMD;
450  __I uint32_t RESPCMD;
451  __I uint32_t RESP1;
452  __I uint32_t RESP2;
453  __I uint32_t RESP3;
454  __I uint32_t RESP4;
455  __IO uint32_t DTIMER;
456  __IO uint32_t DLEN;
457  __IO uint32_t DCTRL;
458  __I uint32_t DCOUNT;
459  __I uint32_t STA;
460  __IO uint32_t ICR;
461  __IO uint32_t MASK;
462  uint32_t RESERVED0[2];
463  __I uint32_t FIFOCNT;
464  uint32_t RESERVED1[13];
465  __IO uint32_t FIFO;
466 } SDIO_TypeDef;
467 
472 typedef struct
473 {
474  __IO uint32_t CR1;
475  __IO uint32_t CR2;
476  __IO uint32_t SR;
477  __IO uint32_t DR;
478  __IO uint32_t CRCPR;
479  __IO uint32_t RXCRCR;
480  __IO uint32_t TXCRCR;
481  __IO uint32_t I2SCFGR;
482  __IO uint32_t I2SPR;
483 } SPI_TypeDef;
484 
489 typedef struct
490 {
491  __IO uint32_t CR1;
492  __IO uint32_t CR2;
493  __IO uint32_t SMCR;
494  __IO uint32_t DIER;
495  __IO uint32_t SR;
496  __IO uint32_t EGR;
497  __IO uint32_t CCMR1;
498  __IO uint32_t CCMR2;
499  __IO uint32_t CCER;
500  __IO uint32_t CNT;
501  __IO uint32_t PSC;
502  __IO uint32_t ARR;
503  __IO uint32_t RCR;
504  __IO uint32_t CCR1;
505  __IO uint32_t CCR2;
506  __IO uint32_t CCR3;
507  __IO uint32_t CCR4;
508  __IO uint32_t BDTR;
509  __IO uint32_t DCR;
510  __IO uint32_t DMAR;
511  __IO uint32_t OR;
512 } TIM_TypeDef;
513 
518 typedef struct
519 {
520  __IO uint32_t SR;
521  __IO uint32_t DR;
522  __IO uint32_t BRR;
523  __IO uint32_t CR1;
524  __IO uint32_t CR2;
525  __IO uint32_t CR3;
526  __IO uint32_t GTPR;
527 } USART_TypeDef;
528 
533 typedef struct
534 {
535  __IO uint32_t CR;
536  __IO uint32_t CFR;
537  __IO uint32_t SR;
538 } WWDG_TypeDef;
539 
543 typedef struct
544 {
545  __IO uint32_t GOTGCTL;
546  __IO uint32_t GOTGINT;
547  __IO uint32_t GAHBCFG;
548  __IO uint32_t GUSBCFG;
549  __IO uint32_t GRSTCTL;
550  __IO uint32_t GINTSTS;
551  __IO uint32_t GINTMSK;
552  __IO uint32_t GRXSTSR;
553  __IO uint32_t GRXSTSP;
554  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
555  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
556  __IO uint32_t HNPTXSTS;
557  uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
558  __IO uint32_t GCCFG;
559  __IO uint32_t CID;
560  uint32_t Reserved40[48];
561  __IO uint32_t HPTXFSIZ;
562  __IO uint32_t DIEPTXF[0x0F];
563 }
564 USB_OTG_GlobalTypeDef;
565 
566 
567 
571 typedef struct
572 {
573  __IO uint32_t DCFG;
574  __IO uint32_t DCTL;
575  __IO uint32_t DSTS;
576  uint32_t Reserved0C;
577  __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
578  __IO uint32_t DOEPMSK;
579  __IO uint32_t DAINT;
580  __IO uint32_t DAINTMSK;
581  uint32_t Reserved20;
582  uint32_t Reserved9;
583  __IO uint32_t DVBUSDIS;
584  __IO uint32_t DVBUSPULSE;
585  __IO uint32_t DTHRCTL;
586  __IO uint32_t DIEPEMPMSK;
587  __IO uint32_t DEACHINT;
588  __IO uint32_t DEACHMSK;
589  uint32_t Reserved40;
590  __IO uint32_t DINEP1MSK;
591  uint32_t Reserved44[15];
592  __IO uint32_t DOUTEP1MSK;
593 }
594 USB_OTG_DeviceTypeDef;
595 
596 
600 typedef struct
601 {
602  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
603  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
604  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
605  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
606  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
607  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
608  __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
609  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
610 }
611 USB_OTG_INEndpointTypeDef;
612 
613 
617 typedef struct
618 {
619  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
620  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
621  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
622  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
623  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
624  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
625  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
626 }
627 USB_OTG_OUTEndpointTypeDef;
628 
629 
633 typedef struct
634 {
635  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
636  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
637  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
638  uint32_t Reserved40C; /* Reserved 40Ch*/
639  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
640  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
641  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
642 }
643 USB_OTG_HostTypeDef;
644 
645 
649 typedef struct
650 {
651  __IO uint32_t HCCHAR;
652  __IO uint32_t HCSPLT;
653  __IO uint32_t HCINT;
654  __IO uint32_t HCINTMSK;
655  __IO uint32_t HCTSIZ;
656  __IO uint32_t HCDMA;
657  uint32_t Reserved[2];
658 }
659 USB_OTG_HostChannelTypeDef;
660 
664 #define FLASH_BASE 0x08000000U
665 #define SRAM1_BASE 0x20000000U
666 #define PERIPH_BASE 0x40000000U
667 #define BKPSRAM_BASE 0x40024000U
668 #define SRAM1_BB_BASE 0x22000000U
669 #define PERIPH_BB_BASE 0x42000000U
670 #define BKPSRAM_BB_BASE 0x42480000U
671 #define FLASH_END 0x0807FFFFU
673 /* Legacy defines */
674 #define SRAM_BASE SRAM1_BASE
675 #define SRAM_BB_BASE SRAM1_BB_BASE
676 
677 
679 #define APB1PERIPH_BASE PERIPH_BASE
680 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
681 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
682 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
683 
685 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
686 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
687 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
688 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
689 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
690 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
691 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
692 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
693 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
694 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
695 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
696 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
697 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
698 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
699 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
700 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
701 
703 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
704 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
705 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
706 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
707 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
708 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
709 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
710 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
711 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
712 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
713 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
714 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
715 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
716 
718 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
719 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
720 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
721 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
722 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
723 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
724 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
725 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
726 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
727 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
728 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
729 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
730 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
731 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
732 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
733 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
734 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
735 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
736 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
737 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
738 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
739 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
740 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
741 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
742 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
743 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
744 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
745 
746 /* Debug MCU registers base address */
747 #define DBGMCU_BASE 0xE0042000U
748 
750 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
751 
752 #define USB_OTG_GLOBAL_BASE 0x000U
753 #define USB_OTG_DEVICE_BASE 0x800U
754 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
755 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
756 #define USB_OTG_EP_REG_SIZE 0x20U
757 #define USB_OTG_HOST_BASE 0x400U
758 #define USB_OTG_HOST_PORT_BASE 0x440U
759 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
760 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
761 #define USB_OTG_PCGCCTL_BASE 0xE00U
762 #define USB_OTG_FIFO_BASE 0x1000U
763 #define USB_OTG_FIFO_SIZE 0x1000U
764 
772 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
773 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
774 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
775 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
776 #define RTC ((RTC_TypeDef *) RTC_BASE)
777 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
778 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
779 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
780 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
781 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
782 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
783 #define USART2 ((USART_TypeDef *) USART2_BASE)
784 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
785 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
786 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
787 #define PWR ((PWR_TypeDef *) PWR_BASE)
788 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
789 #define USART1 ((USART_TypeDef *) USART1_BASE)
790 #define USART6 ((USART_TypeDef *) USART6_BASE)
791 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
792 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
793 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
794 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
795 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
796 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
797 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
798 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
799 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
800 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
801 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
802 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
803 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
804 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
805 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
806 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
807 #define CRC ((CRC_TypeDef *) CRC_BASE)
808 #define RCC ((RCC_TypeDef *) RCC_BASE)
809 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
810 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
811 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
812 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
813 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
814 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
815 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
816 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
817 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
818 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
819 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
820 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
821 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
822 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
823 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
824 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
825 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
826 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
827 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
828 
829 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
830 
831 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
832 
845 /******************************************************************************/
846 /* Peripheral Registers_Bits_Definition */
847 /******************************************************************************/
848 
849 /******************************************************************************/
850 /* */
851 /* Analog to Digital Converter */
852 /* */
853 /******************************************************************************/
854 /******************** Bit definition for ADC_SR register ********************/
855 #define ADC_SR_AWD 0x00000001U
856 #define ADC_SR_EOC 0x00000002U
857 #define ADC_SR_JEOC 0x00000004U
858 #define ADC_SR_JSTRT 0x00000008U
859 #define ADC_SR_STRT 0x00000010U
860 #define ADC_SR_OVR 0x00000020U
862 /******************* Bit definition for ADC_CR1 register ********************/
863 #define ADC_CR1_AWDCH 0x0000001FU
864 #define ADC_CR1_AWDCH_0 0x00000001U
865 #define ADC_CR1_AWDCH_1 0x00000002U
866 #define ADC_CR1_AWDCH_2 0x00000004U
867 #define ADC_CR1_AWDCH_3 0x00000008U
868 #define ADC_CR1_AWDCH_4 0x00000010U
869 #define ADC_CR1_EOCIE 0x00000020U
870 #define ADC_CR1_AWDIE 0x00000040U
871 #define ADC_CR1_JEOCIE 0x00000080U
872 #define ADC_CR1_SCAN 0x00000100U
873 #define ADC_CR1_AWDSGL 0x00000200U
874 #define ADC_CR1_JAUTO 0x00000400U
875 #define ADC_CR1_DISCEN 0x00000800U
876 #define ADC_CR1_JDISCEN 0x00001000U
877 #define ADC_CR1_DISCNUM 0x0000E000U
878 #define ADC_CR1_DISCNUM_0 0x00002000U
879 #define ADC_CR1_DISCNUM_1 0x00004000U
880 #define ADC_CR1_DISCNUM_2 0x00008000U
881 #define ADC_CR1_JAWDEN 0x00400000U
882 #define ADC_CR1_AWDEN 0x00800000U
883 #define ADC_CR1_RES 0x03000000U
884 #define ADC_CR1_RES_0 0x01000000U
885 #define ADC_CR1_RES_1 0x02000000U
886 #define ADC_CR1_OVRIE 0x04000000U
888 /******************* Bit definition for ADC_CR2 register ********************/
889 #define ADC_CR2_ADON 0x00000001U
890 #define ADC_CR2_CONT 0x00000002U
891 #define ADC_CR2_DMA 0x00000100U
892 #define ADC_CR2_DDS 0x00000200U
893 #define ADC_CR2_EOCS 0x00000400U
894 #define ADC_CR2_ALIGN 0x00000800U
895 #define ADC_CR2_JEXTSEL 0x000F0000U
896 #define ADC_CR2_JEXTSEL_0 0x00010000U
897 #define ADC_CR2_JEXTSEL_1 0x00020000U
898 #define ADC_CR2_JEXTSEL_2 0x00040000U
899 #define ADC_CR2_JEXTSEL_3 0x00080000U
900 #define ADC_CR2_JEXTEN 0x00300000U
901 #define ADC_CR2_JEXTEN_0 0x00100000U
902 #define ADC_CR2_JEXTEN_1 0x00200000U
903 #define ADC_CR2_JSWSTART 0x00400000U
904 #define ADC_CR2_EXTSEL 0x0F000000U
905 #define ADC_CR2_EXTSEL_0 0x01000000U
906 #define ADC_CR2_EXTSEL_1 0x02000000U
907 #define ADC_CR2_EXTSEL_2 0x04000000U
908 #define ADC_CR2_EXTSEL_3 0x08000000U
909 #define ADC_CR2_EXTEN 0x30000000U
910 #define ADC_CR2_EXTEN_0 0x10000000U
911 #define ADC_CR2_EXTEN_1 0x20000000U
912 #define ADC_CR2_SWSTART 0x40000000U
914 /****************** Bit definition for ADC_SMPR1 register *******************/
915 #define ADC_SMPR1_SMP10 0x00000007U
916 #define ADC_SMPR1_SMP10_0 0x00000001U
917 #define ADC_SMPR1_SMP10_1 0x00000002U
918 #define ADC_SMPR1_SMP10_2 0x00000004U
919 #define ADC_SMPR1_SMP11 0x00000038U
920 #define ADC_SMPR1_SMP11_0 0x00000008U
921 #define ADC_SMPR1_SMP11_1 0x00000010U
922 #define ADC_SMPR1_SMP11_2 0x00000020U
923 #define ADC_SMPR1_SMP12 0x000001C0U
924 #define ADC_SMPR1_SMP12_0 0x00000040U
925 #define ADC_SMPR1_SMP12_1 0x00000080U
926 #define ADC_SMPR1_SMP12_2 0x00000100U
927 #define ADC_SMPR1_SMP13 0x00000E00U
928 #define ADC_SMPR1_SMP13_0 0x00000200U
929 #define ADC_SMPR1_SMP13_1 0x00000400U
930 #define ADC_SMPR1_SMP13_2 0x00000800U
931 #define ADC_SMPR1_SMP14 0x00007000U
932 #define ADC_SMPR1_SMP14_0 0x00001000U
933 #define ADC_SMPR1_SMP14_1 0x00002000U
934 #define ADC_SMPR1_SMP14_2 0x00004000U
935 #define ADC_SMPR1_SMP15 0x00038000U
936 #define ADC_SMPR1_SMP15_0 0x00008000U
937 #define ADC_SMPR1_SMP15_1 0x00010000U
938 #define ADC_SMPR1_SMP15_2 0x00020000U
939 #define ADC_SMPR1_SMP16 0x001C0000U
940 #define ADC_SMPR1_SMP16_0 0x00040000U
941 #define ADC_SMPR1_SMP16_1 0x00080000U
942 #define ADC_SMPR1_SMP16_2 0x00100000U
943 #define ADC_SMPR1_SMP17 0x00E00000U
944 #define ADC_SMPR1_SMP17_0 0x00200000U
945 #define ADC_SMPR1_SMP17_1 0x00400000U
946 #define ADC_SMPR1_SMP17_2 0x00800000U
947 #define ADC_SMPR1_SMP18 0x07000000U
948 #define ADC_SMPR1_SMP18_0 0x01000000U
949 #define ADC_SMPR1_SMP18_1 0x02000000U
950 #define ADC_SMPR1_SMP18_2 0x04000000U
952 /****************** Bit definition for ADC_SMPR2 register *******************/
953 #define ADC_SMPR2_SMP0 0x00000007U
954 #define ADC_SMPR2_SMP0_0 0x00000001U
955 #define ADC_SMPR2_SMP0_1 0x00000002U
956 #define ADC_SMPR2_SMP0_2 0x00000004U
957 #define ADC_SMPR2_SMP1 0x00000038U
958 #define ADC_SMPR2_SMP1_0 0x00000008U
959 #define ADC_SMPR2_SMP1_1 0x00000010U
960 #define ADC_SMPR2_SMP1_2 0x00000020U
961 #define ADC_SMPR2_SMP2 0x000001C0U
962 #define ADC_SMPR2_SMP2_0 0x00000040U
963 #define ADC_SMPR2_SMP2_1 0x00000080U
964 #define ADC_SMPR2_SMP2_2 0x00000100U
965 #define ADC_SMPR2_SMP3 0x00000E00U
966 #define ADC_SMPR2_SMP3_0 0x00000200U
967 #define ADC_SMPR2_SMP3_1 0x00000400U
968 #define ADC_SMPR2_SMP3_2 0x00000800U
969 #define ADC_SMPR2_SMP4 0x00007000U
970 #define ADC_SMPR2_SMP4_0 0x00001000U
971 #define ADC_SMPR2_SMP4_1 0x00002000U
972 #define ADC_SMPR2_SMP4_2 0x00004000U
973 #define ADC_SMPR2_SMP5 0x00038000U
974 #define ADC_SMPR2_SMP5_0 0x00008000U
975 #define ADC_SMPR2_SMP5_1 0x00010000U
976 #define ADC_SMPR2_SMP5_2 0x00020000U
977 #define ADC_SMPR2_SMP6 0x001C0000U
978 #define ADC_SMPR2_SMP6_0 0x00040000U
979 #define ADC_SMPR2_SMP6_1 0x00080000U
980 #define ADC_SMPR2_SMP6_2 0x00100000U
981 #define ADC_SMPR2_SMP7 0x00E00000U
982 #define ADC_SMPR2_SMP7_0 0x00200000U
983 #define ADC_SMPR2_SMP7_1 0x00400000U
984 #define ADC_SMPR2_SMP7_2 0x00800000U
985 #define ADC_SMPR2_SMP8 0x07000000U
986 #define ADC_SMPR2_SMP8_0 0x01000000U
987 #define ADC_SMPR2_SMP8_1 0x02000000U
988 #define ADC_SMPR2_SMP8_2 0x04000000U
989 #define ADC_SMPR2_SMP9 0x38000000U
990 #define ADC_SMPR2_SMP9_0 0x08000000U
991 #define ADC_SMPR2_SMP9_1 0x10000000U
992 #define ADC_SMPR2_SMP9_2 0x20000000U
994 /****************** Bit definition for ADC_JOFR1 register *******************/
995 #define ADC_JOFR1_JOFFSET1 0x0FFFU
997 /****************** Bit definition for ADC_JOFR2 register *******************/
998 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1000 /****************** Bit definition for ADC_JOFR3 register *******************/
1001 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1003 /****************** Bit definition for ADC_JOFR4 register *******************/
1004 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1006 /******************* Bit definition for ADC_HTR register ********************/
1007 #define ADC_HTR_HT 0x0FFFU
1009 /******************* Bit definition for ADC_LTR register ********************/
1010 #define ADC_LTR_LT 0x0FFFU
1012 /******************* Bit definition for ADC_SQR1 register *******************/
1013 #define ADC_SQR1_SQ13 0x0000001FU
1014 #define ADC_SQR1_SQ13_0 0x00000001U
1015 #define ADC_SQR1_SQ13_1 0x00000002U
1016 #define ADC_SQR1_SQ13_2 0x00000004U
1017 #define ADC_SQR1_SQ13_3 0x00000008U
1018 #define ADC_SQR1_SQ13_4 0x00000010U
1019 #define ADC_SQR1_SQ14 0x000003E0U
1020 #define ADC_SQR1_SQ14_0 0x00000020U
1021 #define ADC_SQR1_SQ14_1 0x00000040U
1022 #define ADC_SQR1_SQ14_2 0x00000080U
1023 #define ADC_SQR1_SQ14_3 0x00000100U
1024 #define ADC_SQR1_SQ14_4 0x00000200U
1025 #define ADC_SQR1_SQ15 0x00007C00U
1026 #define ADC_SQR1_SQ15_0 0x00000400U
1027 #define ADC_SQR1_SQ15_1 0x00000800U
1028 #define ADC_SQR1_SQ15_2 0x00001000U
1029 #define ADC_SQR1_SQ15_3 0x00002000U
1030 #define ADC_SQR1_SQ15_4 0x00004000U
1031 #define ADC_SQR1_SQ16 0x000F8000U
1032 #define ADC_SQR1_SQ16_0 0x00008000U
1033 #define ADC_SQR1_SQ16_1 0x00010000U
1034 #define ADC_SQR1_SQ16_2 0x00020000U
1035 #define ADC_SQR1_SQ16_3 0x00040000U
1036 #define ADC_SQR1_SQ16_4 0x00080000U
1037 #define ADC_SQR1_L 0x00F00000U
1038 #define ADC_SQR1_L_0 0x00100000U
1039 #define ADC_SQR1_L_1 0x00200000U
1040 #define ADC_SQR1_L_2 0x00400000U
1041 #define ADC_SQR1_L_3 0x00800000U
1043 /******************* Bit definition for ADC_SQR2 register *******************/
1044 #define ADC_SQR2_SQ7 0x0000001FU
1045 #define ADC_SQR2_SQ7_0 0x00000001U
1046 #define ADC_SQR2_SQ7_1 0x00000002U
1047 #define ADC_SQR2_SQ7_2 0x00000004U
1048 #define ADC_SQR2_SQ7_3 0x00000008U
1049 #define ADC_SQR2_SQ7_4 0x00000010U
1050 #define ADC_SQR2_SQ8 0x000003E0U
1051 #define ADC_SQR2_SQ8_0 0x00000020U
1052 #define ADC_SQR2_SQ8_1 0x00000040U
1053 #define ADC_SQR2_SQ8_2 0x00000080U
1054 #define ADC_SQR2_SQ8_3 0x00000100U
1055 #define ADC_SQR2_SQ8_4 0x00000200U
1056 #define ADC_SQR2_SQ9 0x00007C00U
1057 #define ADC_SQR2_SQ9_0 0x00000400U
1058 #define ADC_SQR2_SQ9_1 0x00000800U
1059 #define ADC_SQR2_SQ9_2 0x00001000U
1060 #define ADC_SQR2_SQ9_3 0x00002000U
1061 #define ADC_SQR2_SQ9_4 0x00004000U
1062 #define ADC_SQR2_SQ10 0x000F8000U
1063 #define ADC_SQR2_SQ10_0 0x00008000U
1064 #define ADC_SQR2_SQ10_1 0x00010000U
1065 #define ADC_SQR2_SQ10_2 0x00020000U
1066 #define ADC_SQR2_SQ10_3 0x00040000U
1067 #define ADC_SQR2_SQ10_4 0x00080000U
1068 #define ADC_SQR2_SQ11 0x01F00000U
1069 #define ADC_SQR2_SQ11_0 0x00100000U
1070 #define ADC_SQR2_SQ11_1 0x00200000U
1071 #define ADC_SQR2_SQ11_2 0x00400000U
1072 #define ADC_SQR2_SQ11_3 0x00800000U
1073 #define ADC_SQR2_SQ11_4 0x01000000U
1074 #define ADC_SQR2_SQ12 0x3E000000U
1075 #define ADC_SQR2_SQ12_0 0x02000000U
1076 #define ADC_SQR2_SQ12_1 0x04000000U
1077 #define ADC_SQR2_SQ12_2 0x08000000U
1078 #define ADC_SQR2_SQ12_3 0x10000000U
1079 #define ADC_SQR2_SQ12_4 0x20000000U
1081 /******************* Bit definition for ADC_SQR3 register *******************/
1082 #define ADC_SQR3_SQ1 0x0000001FU
1083 #define ADC_SQR3_SQ1_0 0x00000001U
1084 #define ADC_SQR3_SQ1_1 0x00000002U
1085 #define ADC_SQR3_SQ1_2 0x00000004U
1086 #define ADC_SQR3_SQ1_3 0x00000008U
1087 #define ADC_SQR3_SQ1_4 0x00000010U
1088 #define ADC_SQR3_SQ2 0x000003E0U
1089 #define ADC_SQR3_SQ2_0 0x00000020U
1090 #define ADC_SQR3_SQ2_1 0x00000040U
1091 #define ADC_SQR3_SQ2_2 0x00000080U
1092 #define ADC_SQR3_SQ2_3 0x00000100U
1093 #define ADC_SQR3_SQ2_4 0x00000200U
1094 #define ADC_SQR3_SQ3 0x00007C00U
1095 #define ADC_SQR3_SQ3_0 0x00000400U
1096 #define ADC_SQR3_SQ3_1 0x00000800U
1097 #define ADC_SQR3_SQ3_2 0x00001000U
1098 #define ADC_SQR3_SQ3_3 0x00002000U
1099 #define ADC_SQR3_SQ3_4 0x00004000U
1100 #define ADC_SQR3_SQ4 0x000F8000U
1101 #define ADC_SQR3_SQ4_0 0x00008000U
1102 #define ADC_SQR3_SQ4_1 0x00010000U
1103 #define ADC_SQR3_SQ4_2 0x00020000U
1104 #define ADC_SQR3_SQ4_3 0x00040000U
1105 #define ADC_SQR3_SQ4_4 0x00080000U
1106 #define ADC_SQR3_SQ5 0x01F00000U
1107 #define ADC_SQR3_SQ5_0 0x00100000U
1108 #define ADC_SQR3_SQ5_1 0x00200000U
1109 #define ADC_SQR3_SQ5_2 0x00400000U
1110 #define ADC_SQR3_SQ5_3 0x00800000U
1111 #define ADC_SQR3_SQ5_4 0x01000000U
1112 #define ADC_SQR3_SQ6 0x3E000000U
1113 #define ADC_SQR3_SQ6_0 0x02000000U
1114 #define ADC_SQR3_SQ6_1 0x04000000U
1115 #define ADC_SQR3_SQ6_2 0x08000000U
1116 #define ADC_SQR3_SQ6_3 0x10000000U
1117 #define ADC_SQR3_SQ6_4 0x20000000U
1119 /******************* Bit definition for ADC_JSQR register *******************/
1120 #define ADC_JSQR_JSQ1 0x0000001FU
1121 #define ADC_JSQR_JSQ1_0 0x00000001U
1122 #define ADC_JSQR_JSQ1_1 0x00000002U
1123 #define ADC_JSQR_JSQ1_2 0x00000004U
1124 #define ADC_JSQR_JSQ1_3 0x00000008U
1125 #define ADC_JSQR_JSQ1_4 0x00000010U
1126 #define ADC_JSQR_JSQ2 0x000003E0U
1127 #define ADC_JSQR_JSQ2_0 0x00000020U
1128 #define ADC_JSQR_JSQ2_1 0x00000040U
1129 #define ADC_JSQR_JSQ2_2 0x00000080U
1130 #define ADC_JSQR_JSQ2_3 0x00000100U
1131 #define ADC_JSQR_JSQ2_4 0x00000200U
1132 #define ADC_JSQR_JSQ3 0x00007C00U
1133 #define ADC_JSQR_JSQ3_0 0x00000400U
1134 #define ADC_JSQR_JSQ3_1 0x00000800U
1135 #define ADC_JSQR_JSQ3_2 0x00001000U
1136 #define ADC_JSQR_JSQ3_3 0x00002000U
1137 #define ADC_JSQR_JSQ3_4 0x00004000U
1138 #define ADC_JSQR_JSQ4 0x000F8000U
1139 #define ADC_JSQR_JSQ4_0 0x00008000U
1140 #define ADC_JSQR_JSQ4_1 0x00010000U
1141 #define ADC_JSQR_JSQ4_2 0x00020000U
1142 #define ADC_JSQR_JSQ4_3 0x00040000U
1143 #define ADC_JSQR_JSQ4_4 0x00080000U
1144 #define ADC_JSQR_JL 0x00300000U
1145 #define ADC_JSQR_JL_0 0x00100000U
1146 #define ADC_JSQR_JL_1 0x00200000U
1148 /******************* Bit definition for ADC_JDR1 register *******************/
1149 #define ADC_JDR1_JDATA 0xFFFFU
1151 /******************* Bit definition for ADC_JDR2 register *******************/
1152 #define ADC_JDR2_JDATA 0xFFFFU
1154 /******************* Bit definition for ADC_JDR3 register *******************/
1155 #define ADC_JDR3_JDATA 0xFFFFU
1157 /******************* Bit definition for ADC_JDR4 register *******************/
1158 #define ADC_JDR4_JDATA 0xFFFFU
1160 /******************** Bit definition for ADC_DR register ********************/
1161 #define ADC_DR_DATA 0x0000FFFFU
1162 #define ADC_DR_ADC2DATA 0xFFFF0000U
1164 /******************* Bit definition for ADC_CSR register ********************/
1165 #define ADC_CSR_AWD1 0x00000001U
1166 #define ADC_CSR_EOC1 0x00000002U
1167 #define ADC_CSR_JEOC1 0x00000004U
1168 #define ADC_CSR_JSTRT1 0x00000008U
1169 #define ADC_CSR_STRT1 0x00000010U
1170 #define ADC_CSR_OVR1 0x00000020U
1171 #define ADC_CSR_AWD2 0x00000100U
1172 #define ADC_CSR_EOC2 0x00000200U
1173 #define ADC_CSR_JEOC2 0x00000400U
1174 #define ADC_CSR_JSTRT2 0x00000800U
1175 #define ADC_CSR_STRT2 0x00001000U
1176 #define ADC_CSR_OVR2 0x00002000U
1177 #define ADC_CSR_AWD3 0x00010000U
1178 #define ADC_CSR_EOC3 0x00020000U
1179 #define ADC_CSR_JEOC3 0x00040000U
1180 #define ADC_CSR_JSTRT3 0x00080000U
1181 #define ADC_CSR_STRT3 0x00100000U
1182 #define ADC_CSR_OVR3 0x00200000U
1184 /* Legacy defines */
1185 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1186 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1187 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1188 
1189 /******************* Bit definition for ADC_CCR register ********************/
1190 #define ADC_CCR_MULTI 0x0000001FU
1191 #define ADC_CCR_MULTI_0 0x00000001U
1192 #define ADC_CCR_MULTI_1 0x00000002U
1193 #define ADC_CCR_MULTI_2 0x00000004U
1194 #define ADC_CCR_MULTI_3 0x00000008U
1195 #define ADC_CCR_MULTI_4 0x00000010U
1196 #define ADC_CCR_DELAY 0x00000F00U
1197 #define ADC_CCR_DELAY_0 0x00000100U
1198 #define ADC_CCR_DELAY_1 0x00000200U
1199 #define ADC_CCR_DELAY_2 0x00000400U
1200 #define ADC_CCR_DELAY_3 0x00000800U
1201 #define ADC_CCR_DDS 0x00002000U
1202 #define ADC_CCR_DMA 0x0000C000U
1203 #define ADC_CCR_DMA_0 0x00004000U
1204 #define ADC_CCR_DMA_1 0x00008000U
1205 #define ADC_CCR_ADCPRE 0x00030000U
1206 #define ADC_CCR_ADCPRE_0 0x00010000U
1207 #define ADC_CCR_ADCPRE_1 0x00020000U
1208 #define ADC_CCR_VBATE 0x00400000U
1209 #define ADC_CCR_TSVREFE 0x00800000U
1211 /******************* Bit definition for ADC_CDR register ********************/
1212 #define ADC_CDR_DATA1 0x0000FFFFU
1213 #define ADC_CDR_DATA2 0xFFFF0000U
1215 /******************************************************************************/
1216 /* */
1217 /* CRC calculation unit */
1218 /* */
1219 /******************************************************************************/
1220 /******************* Bit definition for CRC_DR register *********************/
1221 #define CRC_DR_DR 0xFFFFFFFFU
1224 /******************* Bit definition for CRC_IDR register ********************/
1225 #define CRC_IDR_IDR 0xFFU
1228 /******************** Bit definition for CRC_CR register ********************/
1229 #define CRC_CR_RESET 0x01U
1231 /******************************************************************************/
1232 /* */
1233 /* Debug MCU */
1234 /* */
1235 /******************************************************************************/
1236 
1237 /******************************************************************************/
1238 /* */
1239 /* DMA Controller */
1240 /* */
1241 /******************************************************************************/
1242 /******************** Bits definition for DMA_SxCR register *****************/
1243 #define DMA_SxCR_CHSEL 0x0E000000U
1244 #define DMA_SxCR_CHSEL_0 0x02000000U
1245 #define DMA_SxCR_CHSEL_1 0x04000000U
1246 #define DMA_SxCR_CHSEL_2 0x08000000U
1247 #define DMA_SxCR_MBURST 0x01800000U
1248 #define DMA_SxCR_MBURST_0 0x00800000U
1249 #define DMA_SxCR_MBURST_1 0x01000000U
1250 #define DMA_SxCR_PBURST 0x00600000U
1251 #define DMA_SxCR_PBURST_0 0x00200000U
1252 #define DMA_SxCR_PBURST_1 0x00400000U
1253 #define DMA_SxCR_CT 0x00080000U
1254 #define DMA_SxCR_DBM 0x00040000U
1255 #define DMA_SxCR_PL 0x00030000U
1256 #define DMA_SxCR_PL_0 0x00010000U
1257 #define DMA_SxCR_PL_1 0x00020000U
1258 #define DMA_SxCR_PINCOS 0x00008000U
1259 #define DMA_SxCR_MSIZE 0x00006000U
1260 #define DMA_SxCR_MSIZE_0 0x00002000U
1261 #define DMA_SxCR_MSIZE_1 0x00004000U
1262 #define DMA_SxCR_PSIZE 0x00001800U
1263 #define DMA_SxCR_PSIZE_0 0x00000800U
1264 #define DMA_SxCR_PSIZE_1 0x00001000U
1265 #define DMA_SxCR_MINC 0x00000400U
1266 #define DMA_SxCR_PINC 0x00000200U
1267 #define DMA_SxCR_CIRC 0x00000100U
1268 #define DMA_SxCR_DIR 0x000000C0U
1269 #define DMA_SxCR_DIR_0 0x00000040U
1270 #define DMA_SxCR_DIR_1 0x00000080U
1271 #define DMA_SxCR_PFCTRL 0x00000020U
1272 #define DMA_SxCR_TCIE 0x00000010U
1273 #define DMA_SxCR_HTIE 0x00000008U
1274 #define DMA_SxCR_TEIE 0x00000004U
1275 #define DMA_SxCR_DMEIE 0x00000002U
1276 #define DMA_SxCR_EN 0x00000001U
1277 
1278 /* Legacy defines */
1279 #define DMA_SxCR_ACK 0x00100000U
1280 
1281 /******************** Bits definition for DMA_SxCNDTR register **************/
1282 #define DMA_SxNDT 0x0000FFFFU
1283 #define DMA_SxNDT_0 0x00000001U
1284 #define DMA_SxNDT_1 0x00000002U
1285 #define DMA_SxNDT_2 0x00000004U
1286 #define DMA_SxNDT_3 0x00000008U
1287 #define DMA_SxNDT_4 0x00000010U
1288 #define DMA_SxNDT_5 0x00000020U
1289 #define DMA_SxNDT_6 0x00000040U
1290 #define DMA_SxNDT_7 0x00000080U
1291 #define DMA_SxNDT_8 0x00000100U
1292 #define DMA_SxNDT_9 0x00000200U
1293 #define DMA_SxNDT_10 0x00000400U
1294 #define DMA_SxNDT_11 0x00000800U
1295 #define DMA_SxNDT_12 0x00001000U
1296 #define DMA_SxNDT_13 0x00002000U
1297 #define DMA_SxNDT_14 0x00004000U
1298 #define DMA_SxNDT_15 0x00008000U
1299 
1300 /******************** Bits definition for DMA_SxFCR register ****************/
1301 #define DMA_SxFCR_FEIE 0x00000080U
1302 #define DMA_SxFCR_FS 0x00000038U
1303 #define DMA_SxFCR_FS_0 0x00000008U
1304 #define DMA_SxFCR_FS_1 0x00000010U
1305 #define DMA_SxFCR_FS_2 0x00000020U
1306 #define DMA_SxFCR_DMDIS 0x00000004U
1307 #define DMA_SxFCR_FTH 0x00000003U
1308 #define DMA_SxFCR_FTH_0 0x00000001U
1309 #define DMA_SxFCR_FTH_1 0x00000002U
1310 
1311 /******************** Bits definition for DMA_LISR register *****************/
1312 #define DMA_LISR_TCIF3 0x08000000U
1313 #define DMA_LISR_HTIF3 0x04000000U
1314 #define DMA_LISR_TEIF3 0x02000000U
1315 #define DMA_LISR_DMEIF3 0x01000000U
1316 #define DMA_LISR_FEIF3 0x00400000U
1317 #define DMA_LISR_TCIF2 0x00200000U
1318 #define DMA_LISR_HTIF2 0x00100000U
1319 #define DMA_LISR_TEIF2 0x00080000U
1320 #define DMA_LISR_DMEIF2 0x00040000U
1321 #define DMA_LISR_FEIF2 0x00010000U
1322 #define DMA_LISR_TCIF1 0x00000800U
1323 #define DMA_LISR_HTIF1 0x00000400U
1324 #define DMA_LISR_TEIF1 0x00000200U
1325 #define DMA_LISR_DMEIF1 0x00000100U
1326 #define DMA_LISR_FEIF1 0x00000040U
1327 #define DMA_LISR_TCIF0 0x00000020U
1328 #define DMA_LISR_HTIF0 0x00000010U
1329 #define DMA_LISR_TEIF0 0x00000008U
1330 #define DMA_LISR_DMEIF0 0x00000004U
1331 #define DMA_LISR_FEIF0 0x00000001U
1332 
1333 /******************** Bits definition for DMA_HISR register *****************/
1334 #define DMA_HISR_TCIF7 0x08000000U
1335 #define DMA_HISR_HTIF7 0x04000000U
1336 #define DMA_HISR_TEIF7 0x02000000U
1337 #define DMA_HISR_DMEIF7 0x01000000U
1338 #define DMA_HISR_FEIF7 0x00400000U
1339 #define DMA_HISR_TCIF6 0x00200000U
1340 #define DMA_HISR_HTIF6 0x00100000U
1341 #define DMA_HISR_TEIF6 0x00080000U
1342 #define DMA_HISR_DMEIF6 0x00040000U
1343 #define DMA_HISR_FEIF6 0x00010000U
1344 #define DMA_HISR_TCIF5 0x00000800U
1345 #define DMA_HISR_HTIF5 0x00000400U
1346 #define DMA_HISR_TEIF5 0x00000200U
1347 #define DMA_HISR_DMEIF5 0x00000100U
1348 #define DMA_HISR_FEIF5 0x00000040U
1349 #define DMA_HISR_TCIF4 0x00000020U
1350 #define DMA_HISR_HTIF4 0x00000010U
1351 #define DMA_HISR_TEIF4 0x00000008U
1352 #define DMA_HISR_DMEIF4 0x00000004U
1353 #define DMA_HISR_FEIF4 0x00000001U
1354 
1355 /******************** Bits definition for DMA_LIFCR register ****************/
1356 #define DMA_LIFCR_CTCIF3 0x08000000U
1357 #define DMA_LIFCR_CHTIF3 0x04000000U
1358 #define DMA_LIFCR_CTEIF3 0x02000000U
1359 #define DMA_LIFCR_CDMEIF3 0x01000000U
1360 #define DMA_LIFCR_CFEIF3 0x00400000U
1361 #define DMA_LIFCR_CTCIF2 0x00200000U
1362 #define DMA_LIFCR_CHTIF2 0x00100000U
1363 #define DMA_LIFCR_CTEIF2 0x00080000U
1364 #define DMA_LIFCR_CDMEIF2 0x00040000U
1365 #define DMA_LIFCR_CFEIF2 0x00010000U
1366 #define DMA_LIFCR_CTCIF1 0x00000800U
1367 #define DMA_LIFCR_CHTIF1 0x00000400U
1368 #define DMA_LIFCR_CTEIF1 0x00000200U
1369 #define DMA_LIFCR_CDMEIF1 0x00000100U
1370 #define DMA_LIFCR_CFEIF1 0x00000040U
1371 #define DMA_LIFCR_CTCIF0 0x00000020U
1372 #define DMA_LIFCR_CHTIF0 0x00000010U
1373 #define DMA_LIFCR_CTEIF0 0x00000008U
1374 #define DMA_LIFCR_CDMEIF0 0x00000004U
1375 #define DMA_LIFCR_CFEIF0 0x00000001U
1376 
1377 /******************** Bits definition for DMA_HIFCR register ****************/
1378 #define DMA_HIFCR_CTCIF7 0x08000000U
1379 #define DMA_HIFCR_CHTIF7 0x04000000U
1380 #define DMA_HIFCR_CTEIF7 0x02000000U
1381 #define DMA_HIFCR_CDMEIF7 0x01000000U
1382 #define DMA_HIFCR_CFEIF7 0x00400000U
1383 #define DMA_HIFCR_CTCIF6 0x00200000U
1384 #define DMA_HIFCR_CHTIF6 0x00100000U
1385 #define DMA_HIFCR_CTEIF6 0x00080000U
1386 #define DMA_HIFCR_CDMEIF6 0x00040000U
1387 #define DMA_HIFCR_CFEIF6 0x00010000U
1388 #define DMA_HIFCR_CTCIF5 0x00000800U
1389 #define DMA_HIFCR_CHTIF5 0x00000400U
1390 #define DMA_HIFCR_CTEIF5 0x00000200U
1391 #define DMA_HIFCR_CDMEIF5 0x00000100U
1392 #define DMA_HIFCR_CFEIF5 0x00000040U
1393 #define DMA_HIFCR_CTCIF4 0x00000020U
1394 #define DMA_HIFCR_CHTIF4 0x00000010U
1395 #define DMA_HIFCR_CTEIF4 0x00000008U
1396 #define DMA_HIFCR_CDMEIF4 0x00000004U
1397 #define DMA_HIFCR_CFEIF4 0x00000001U
1398 
1399 
1400 /******************************************************************************/
1401 /* */
1402 /* External Interrupt/Event Controller */
1403 /* */
1404 /******************************************************************************/
1405 /******************* Bit definition for EXTI_IMR register *******************/
1406 #define EXTI_IMR_MR0 0x00000001U
1407 #define EXTI_IMR_MR1 0x00000002U
1408 #define EXTI_IMR_MR2 0x00000004U
1409 #define EXTI_IMR_MR3 0x00000008U
1410 #define EXTI_IMR_MR4 0x00000010U
1411 #define EXTI_IMR_MR5 0x00000020U
1412 #define EXTI_IMR_MR6 0x00000040U
1413 #define EXTI_IMR_MR7 0x00000080U
1414 #define EXTI_IMR_MR8 0x00000100U
1415 #define EXTI_IMR_MR9 0x00000200U
1416 #define EXTI_IMR_MR10 0x00000400U
1417 #define EXTI_IMR_MR11 0x00000800U
1418 #define EXTI_IMR_MR12 0x00001000U
1419 #define EXTI_IMR_MR13 0x00002000U
1420 #define EXTI_IMR_MR14 0x00004000U
1421 #define EXTI_IMR_MR15 0x00008000U
1422 #define EXTI_IMR_MR16 0x00010000U
1423 #define EXTI_IMR_MR17 0x00020000U
1424 #define EXTI_IMR_MR18 0x00040000U
1425 #define EXTI_IMR_MR19 0x00080000U
1426 #define EXTI_IMR_MR20 0x00100000U
1427 #define EXTI_IMR_MR21 0x00200000U
1428 #define EXTI_IMR_MR22 0x00400000U
1430 /******************* Bit definition for EXTI_EMR register *******************/
1431 #define EXTI_EMR_MR0 0x00000001U
1432 #define EXTI_EMR_MR1 0x00000002U
1433 #define EXTI_EMR_MR2 0x00000004U
1434 #define EXTI_EMR_MR3 0x00000008U
1435 #define EXTI_EMR_MR4 0x00000010U
1436 #define EXTI_EMR_MR5 0x00000020U
1437 #define EXTI_EMR_MR6 0x00000040U
1438 #define EXTI_EMR_MR7 0x00000080U
1439 #define EXTI_EMR_MR8 0x00000100U
1440 #define EXTI_EMR_MR9 0x00000200U
1441 #define EXTI_EMR_MR10 0x00000400U
1442 #define EXTI_EMR_MR11 0x00000800U
1443 #define EXTI_EMR_MR12 0x00001000U
1444 #define EXTI_EMR_MR13 0x00002000U
1445 #define EXTI_EMR_MR14 0x00004000U
1446 #define EXTI_EMR_MR15 0x00008000U
1447 #define EXTI_EMR_MR16 0x00010000U
1448 #define EXTI_EMR_MR17 0x00020000U
1449 #define EXTI_EMR_MR18 0x00040000U
1450 #define EXTI_EMR_MR19 0x00080000U
1451 #define EXTI_EMR_MR20 0x00100000U
1452 #define EXTI_EMR_MR21 0x00200000U
1453 #define EXTI_EMR_MR22 0x00400000U
1455 /****************** Bit definition for EXTI_RTSR register *******************/
1456 #define EXTI_RTSR_TR0 0x00000001U
1457 #define EXTI_RTSR_TR1 0x00000002U
1458 #define EXTI_RTSR_TR2 0x00000004U
1459 #define EXTI_RTSR_TR3 0x00000008U
1460 #define EXTI_RTSR_TR4 0x00000010U
1461 #define EXTI_RTSR_TR5 0x00000020U
1462 #define EXTI_RTSR_TR6 0x00000040U
1463 #define EXTI_RTSR_TR7 0x00000080U
1464 #define EXTI_RTSR_TR8 0x00000100U
1465 #define EXTI_RTSR_TR9 0x00000200U
1466 #define EXTI_RTSR_TR10 0x00000400U
1467 #define EXTI_RTSR_TR11 0x00000800U
1468 #define EXTI_RTSR_TR12 0x00001000U
1469 #define EXTI_RTSR_TR13 0x00002000U
1470 #define EXTI_RTSR_TR14 0x00004000U
1471 #define EXTI_RTSR_TR15 0x00008000U
1472 #define EXTI_RTSR_TR16 0x00010000U
1473 #define EXTI_RTSR_TR17 0x00020000U
1474 #define EXTI_RTSR_TR18 0x00040000U
1475 #define EXTI_RTSR_TR19 0x00080000U
1476 #define EXTI_RTSR_TR20 0x00100000U
1477 #define EXTI_RTSR_TR21 0x00200000U
1478 #define EXTI_RTSR_TR22 0x00400000U
1480 /****************** Bit definition for EXTI_FTSR register *******************/
1481 #define EXTI_FTSR_TR0 0x00000001U
1482 #define EXTI_FTSR_TR1 0x00000002U
1483 #define EXTI_FTSR_TR2 0x00000004U
1484 #define EXTI_FTSR_TR3 0x00000008U
1485 #define EXTI_FTSR_TR4 0x00000010U
1486 #define EXTI_FTSR_TR5 0x00000020U
1487 #define EXTI_FTSR_TR6 0x00000040U
1488 #define EXTI_FTSR_TR7 0x00000080U
1489 #define EXTI_FTSR_TR8 0x00000100U
1490 #define EXTI_FTSR_TR9 0x00000200U
1491 #define EXTI_FTSR_TR10 0x00000400U
1492 #define EXTI_FTSR_TR11 0x00000800U
1493 #define EXTI_FTSR_TR12 0x00001000U
1494 #define EXTI_FTSR_TR13 0x00002000U
1495 #define EXTI_FTSR_TR14 0x00004000U
1496 #define EXTI_FTSR_TR15 0x00008000U
1497 #define EXTI_FTSR_TR16 0x00010000U
1498 #define EXTI_FTSR_TR17 0x00020000U
1499 #define EXTI_FTSR_TR18 0x00040000U
1500 #define EXTI_FTSR_TR19 0x00080000U
1501 #define EXTI_FTSR_TR20 0x00100000U
1502 #define EXTI_FTSR_TR21 0x00200000U
1503 #define EXTI_FTSR_TR22 0x00400000U
1505 /****************** Bit definition for EXTI_SWIER register ******************/
1506 #define EXTI_SWIER_SWIER0 0x00000001U
1507 #define EXTI_SWIER_SWIER1 0x00000002U
1508 #define EXTI_SWIER_SWIER2 0x00000004U
1509 #define EXTI_SWIER_SWIER3 0x00000008U
1510 #define EXTI_SWIER_SWIER4 0x00000010U
1511 #define EXTI_SWIER_SWIER5 0x00000020U
1512 #define EXTI_SWIER_SWIER6 0x00000040U
1513 #define EXTI_SWIER_SWIER7 0x00000080U
1514 #define EXTI_SWIER_SWIER8 0x00000100U
1515 #define EXTI_SWIER_SWIER9 0x00000200U
1516 #define EXTI_SWIER_SWIER10 0x00000400U
1517 #define EXTI_SWIER_SWIER11 0x00000800U
1518 #define EXTI_SWIER_SWIER12 0x00001000U
1519 #define EXTI_SWIER_SWIER13 0x00002000U
1520 #define EXTI_SWIER_SWIER14 0x00004000U
1521 #define EXTI_SWIER_SWIER15 0x00008000U
1522 #define EXTI_SWIER_SWIER16 0x00010000U
1523 #define EXTI_SWIER_SWIER17 0x00020000U
1524 #define EXTI_SWIER_SWIER18 0x00040000U
1525 #define EXTI_SWIER_SWIER19 0x00080000U
1526 #define EXTI_SWIER_SWIER20 0x00100000U
1527 #define EXTI_SWIER_SWIER21 0x00200000U
1528 #define EXTI_SWIER_SWIER22 0x00400000U
1530 /******************* Bit definition for EXTI_PR register ********************/
1531 #define EXTI_PR_PR0 0x00000001U
1532 #define EXTI_PR_PR1 0x00000002U
1533 #define EXTI_PR_PR2 0x00000004U
1534 #define EXTI_PR_PR3 0x00000008U
1535 #define EXTI_PR_PR4 0x00000010U
1536 #define EXTI_PR_PR5 0x00000020U
1537 #define EXTI_PR_PR6 0x00000040U
1538 #define EXTI_PR_PR7 0x00000080U
1539 #define EXTI_PR_PR8 0x00000100U
1540 #define EXTI_PR_PR9 0x00000200U
1541 #define EXTI_PR_PR10 0x00000400U
1542 #define EXTI_PR_PR11 0x00000800U
1543 #define EXTI_PR_PR12 0x00001000U
1544 #define EXTI_PR_PR13 0x00002000U
1545 #define EXTI_PR_PR14 0x00004000U
1546 #define EXTI_PR_PR15 0x00008000U
1547 #define EXTI_PR_PR16 0x00010000U
1548 #define EXTI_PR_PR17 0x00020000U
1549 #define EXTI_PR_PR18 0x00040000U
1550 #define EXTI_PR_PR19 0x00080000U
1551 #define EXTI_PR_PR20 0x00100000U
1552 #define EXTI_PR_PR21 0x00200000U
1553 #define EXTI_PR_PR22 0x00400000U
1555 /******************************************************************************/
1556 /* */
1557 /* FLASH */
1558 /* */
1559 /******************************************************************************/
1560 /******************* Bits definition for FLASH_ACR register *****************/
1561 #define FLASH_ACR_LATENCY 0x0000000FU
1562 #define FLASH_ACR_LATENCY_0WS 0x00000000U
1563 #define FLASH_ACR_LATENCY_1WS 0x00000001U
1564 #define FLASH_ACR_LATENCY_2WS 0x00000002U
1565 #define FLASH_ACR_LATENCY_3WS 0x00000003U
1566 #define FLASH_ACR_LATENCY_4WS 0x00000004U
1567 #define FLASH_ACR_LATENCY_5WS 0x00000005U
1568 #define FLASH_ACR_LATENCY_6WS 0x00000006U
1569 #define FLASH_ACR_LATENCY_7WS 0x00000007U
1570 
1571 #define FLASH_ACR_PRFTEN 0x00000100U
1572 #define FLASH_ACR_ICEN 0x00000200U
1573 #define FLASH_ACR_DCEN 0x00000400U
1574 #define FLASH_ACR_ICRST 0x00000800U
1575 #define FLASH_ACR_DCRST 0x00001000U
1576 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
1577 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
1578 
1579 /******************* Bits definition for FLASH_SR register ******************/
1580 #define FLASH_SR_EOP 0x00000001U
1581 #define FLASH_SR_SOP 0x00000002U
1582 #define FLASH_SR_WRPERR 0x00000010U
1583 #define FLASH_SR_PGAERR 0x00000020U
1584 #define FLASH_SR_PGPERR 0x00000040U
1585 #define FLASH_SR_PGSERR 0x00000080U
1586 #define FLASH_SR_BSY 0x00010000U
1587 
1588 /******************* Bits definition for FLASH_CR register ******************/
1589 #define FLASH_CR_PG 0x00000001U
1590 #define FLASH_CR_SER 0x00000002U
1591 #define FLASH_CR_MER 0x00000004U
1592 #define FLASH_CR_SNB 0x000000F8U
1593 #define FLASH_CR_SNB_0 0x00000008U
1594 #define FLASH_CR_SNB_1 0x00000010U
1595 #define FLASH_CR_SNB_2 0x00000020U
1596 #define FLASH_CR_SNB_3 0x00000040U
1597 #define FLASH_CR_SNB_4 0x00000080U
1598 #define FLASH_CR_PSIZE 0x00000300U
1599 #define FLASH_CR_PSIZE_0 0x00000100U
1600 #define FLASH_CR_PSIZE_1 0x00000200U
1601 #define FLASH_CR_STRT 0x00010000U
1602 #define FLASH_CR_EOPIE 0x01000000U
1603 #define FLASH_CR_LOCK 0x80000000U
1604 
1605 /******************* Bits definition for FLASH_OPTCR register ***************/
1606 #define FLASH_OPTCR_OPTLOCK 0x00000001U
1607 #define FLASH_OPTCR_OPTSTRT 0x00000002U
1608 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
1609 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
1610 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
1611 
1612 #define FLASH_OPTCR_WDG_SW 0x00000020U
1613 #define FLASH_OPTCR_nRST_STOP 0x00000040U
1614 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
1615 #define FLASH_OPTCR_RDP 0x0000FF00U
1616 #define FLASH_OPTCR_RDP_0 0x00000100U
1617 #define FLASH_OPTCR_RDP_1 0x00000200U
1618 #define FLASH_OPTCR_RDP_2 0x00000400U
1619 #define FLASH_OPTCR_RDP_3 0x00000800U
1620 #define FLASH_OPTCR_RDP_4 0x00001000U
1621 #define FLASH_OPTCR_RDP_5 0x00002000U
1622 #define FLASH_OPTCR_RDP_6 0x00004000U
1623 #define FLASH_OPTCR_RDP_7 0x00008000U
1624 #define FLASH_OPTCR_nWRP 0x0FFF0000U
1625 #define FLASH_OPTCR_nWRP_0 0x00010000U
1626 #define FLASH_OPTCR_nWRP_1 0x00020000U
1627 #define FLASH_OPTCR_nWRP_2 0x00040000U
1628 #define FLASH_OPTCR_nWRP_3 0x00080000U
1629 #define FLASH_OPTCR_nWRP_4 0x00100000U
1630 #define FLASH_OPTCR_nWRP_5 0x00200000U
1631 #define FLASH_OPTCR_nWRP_6 0x00400000U
1632 #define FLASH_OPTCR_nWRP_7 0x00800000U
1633 #define FLASH_OPTCR_nWRP_8 0x01000000U
1634 #define FLASH_OPTCR_nWRP_9 0x02000000U
1635 #define FLASH_OPTCR_nWRP_10 0x04000000U
1636 #define FLASH_OPTCR_nWRP_11 0x08000000U
1637 
1638 /****************** Bits definition for FLASH_OPTCR1 register ***************/
1639 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
1640 #define FLASH_OPTCR1_nWRP_0 0x00010000U
1641 #define FLASH_OPTCR1_nWRP_1 0x00020000U
1642 #define FLASH_OPTCR1_nWRP_2 0x00040000U
1643 #define FLASH_OPTCR1_nWRP_3 0x00080000U
1644 #define FLASH_OPTCR1_nWRP_4 0x00100000U
1645 #define FLASH_OPTCR1_nWRP_5 0x00200000U
1646 #define FLASH_OPTCR1_nWRP_6 0x00400000U
1647 #define FLASH_OPTCR1_nWRP_7 0x00800000U
1648 #define FLASH_OPTCR1_nWRP_8 0x01000000U
1649 #define FLASH_OPTCR1_nWRP_9 0x02000000U
1650 #define FLASH_OPTCR1_nWRP_10 0x04000000U
1651 #define FLASH_OPTCR1_nWRP_11 0x08000000U
1652 
1653 /******************************************************************************/
1654 /* */
1655 /* General Purpose I/O */
1656 /* */
1657 /******************************************************************************/
1658 /****************** Bits definition for GPIO_MODER register *****************/
1659 #define GPIO_MODER_MODER0 0x00000003U
1660 #define GPIO_MODER_MODER0_0 0x00000001U
1661 #define GPIO_MODER_MODER0_1 0x00000002U
1662 
1663 #define GPIO_MODER_MODER1 0x0000000CU
1664 #define GPIO_MODER_MODER1_0 0x00000004U
1665 #define GPIO_MODER_MODER1_1 0x00000008U
1666 
1667 #define GPIO_MODER_MODER2 0x00000030U
1668 #define GPIO_MODER_MODER2_0 0x00000010U
1669 #define GPIO_MODER_MODER2_1 0x00000020U
1670 
1671 #define GPIO_MODER_MODER3 0x000000C0U
1672 #define GPIO_MODER_MODER3_0 0x00000040U
1673 #define GPIO_MODER_MODER3_1 0x00000080U
1674 
1675 #define GPIO_MODER_MODER4 0x00000300U
1676 #define GPIO_MODER_MODER4_0 0x00000100U
1677 #define GPIO_MODER_MODER4_1 0x00000200U
1678 
1679 #define GPIO_MODER_MODER5 0x00000C00U
1680 #define GPIO_MODER_MODER5_0 0x00000400U
1681 #define GPIO_MODER_MODER5_1 0x00000800U
1682 
1683 #define GPIO_MODER_MODER6 0x00003000U
1684 #define GPIO_MODER_MODER6_0 0x00001000U
1685 #define GPIO_MODER_MODER6_1 0x00002000U
1686 
1687 #define GPIO_MODER_MODER7 0x0000C000U
1688 #define GPIO_MODER_MODER7_0 0x00004000U
1689 #define GPIO_MODER_MODER7_1 0x00008000U
1690 
1691 #define GPIO_MODER_MODER8 0x00030000U
1692 #define GPIO_MODER_MODER8_0 0x00010000U
1693 #define GPIO_MODER_MODER8_1 0x00020000U
1694 
1695 #define GPIO_MODER_MODER9 0x000C0000U
1696 #define GPIO_MODER_MODER9_0 0x00040000U
1697 #define GPIO_MODER_MODER9_1 0x00080000U
1698 
1699 #define GPIO_MODER_MODER10 0x00300000U
1700 #define GPIO_MODER_MODER10_0 0x00100000U
1701 #define GPIO_MODER_MODER10_1 0x00200000U
1702 
1703 #define GPIO_MODER_MODER11 0x00C00000U
1704 #define GPIO_MODER_MODER11_0 0x00400000U
1705 #define GPIO_MODER_MODER11_1 0x00800000U
1706 
1707 #define GPIO_MODER_MODER12 0x03000000U
1708 #define GPIO_MODER_MODER12_0 0x01000000U
1709 #define GPIO_MODER_MODER12_1 0x02000000U
1710 
1711 #define GPIO_MODER_MODER13 0x0C000000U
1712 #define GPIO_MODER_MODER13_0 0x04000000U
1713 #define GPIO_MODER_MODER13_1 0x08000000U
1714 
1715 #define GPIO_MODER_MODER14 0x30000000U
1716 #define GPIO_MODER_MODER14_0 0x10000000U
1717 #define GPIO_MODER_MODER14_1 0x20000000U
1718 
1719 #define GPIO_MODER_MODER15 0xC0000000U
1720 #define GPIO_MODER_MODER15_0 0x40000000U
1721 #define GPIO_MODER_MODER15_1 0x80000000U
1722 
1723 /****************** Bits definition for GPIO_OTYPER register ****************/
1724 #define GPIO_OTYPER_OT_0 0x00000001U
1725 #define GPIO_OTYPER_OT_1 0x00000002U
1726 #define GPIO_OTYPER_OT_2 0x00000004U
1727 #define GPIO_OTYPER_OT_3 0x00000008U
1728 #define GPIO_OTYPER_OT_4 0x00000010U
1729 #define GPIO_OTYPER_OT_5 0x00000020U
1730 #define GPIO_OTYPER_OT_6 0x00000040U
1731 #define GPIO_OTYPER_OT_7 0x00000080U
1732 #define GPIO_OTYPER_OT_8 0x00000100U
1733 #define GPIO_OTYPER_OT_9 0x00000200U
1734 #define GPIO_OTYPER_OT_10 0x00000400U
1735 #define GPIO_OTYPER_OT_11 0x00000800U
1736 #define GPIO_OTYPER_OT_12 0x00001000U
1737 #define GPIO_OTYPER_OT_13 0x00002000U
1738 #define GPIO_OTYPER_OT_14 0x00004000U
1739 #define GPIO_OTYPER_OT_15 0x00008000U
1740 
1741 /****************** Bits definition for GPIO_OSPEEDR register ***************/
1742 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
1743 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
1744 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
1745 
1746 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
1747 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
1748 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
1749 
1750 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
1751 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
1752 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
1753 
1754 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
1755 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
1756 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
1757 
1758 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
1759 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
1760 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
1761 
1762 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
1763 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
1764 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
1765 
1766 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
1767 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
1768 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
1769 
1770 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
1771 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
1772 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
1773 
1774 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
1775 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
1776 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
1777 
1778 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
1779 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
1780 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
1781 
1782 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
1783 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
1784 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
1785 
1786 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
1787 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
1788 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
1789 
1790 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
1791 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
1792 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
1793 
1794 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
1795 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
1796 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
1797 
1798 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
1799 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
1800 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
1801 
1802 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
1803 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
1804 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
1805 
1806 /****************** Bits definition for GPIO_PUPDR register *****************/
1807 #define GPIO_PUPDR_PUPDR0 0x00000003U
1808 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
1809 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
1810 
1811 #define GPIO_PUPDR_PUPDR1 0x0000000CU
1812 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
1813 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
1814 
1815 #define GPIO_PUPDR_PUPDR2 0x00000030U
1816 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
1817 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
1818 
1819 #define GPIO_PUPDR_PUPDR3 0x000000C0U
1820 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
1821 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
1822 
1823 #define GPIO_PUPDR_PUPDR4 0x00000300U
1824 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
1825 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
1826 
1827 #define GPIO_PUPDR_PUPDR5 0x00000C00U
1828 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
1829 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
1830 
1831 #define GPIO_PUPDR_PUPDR6 0x00003000U
1832 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
1833 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
1834 
1835 #define GPIO_PUPDR_PUPDR7 0x0000C000U
1836 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
1837 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
1838 
1839 #define GPIO_PUPDR_PUPDR8 0x00030000U
1840 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
1841 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
1842 
1843 #define GPIO_PUPDR_PUPDR9 0x000C0000U
1844 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
1845 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
1846 
1847 #define GPIO_PUPDR_PUPDR10 0x00300000U
1848 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
1849 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
1850 
1851 #define GPIO_PUPDR_PUPDR11 0x00C00000U
1852 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
1853 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
1854 
1855 #define GPIO_PUPDR_PUPDR12 0x03000000U
1856 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
1857 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
1858 
1859 #define GPIO_PUPDR_PUPDR13 0x0C000000U
1860 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
1861 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
1862 
1863 #define GPIO_PUPDR_PUPDR14 0x30000000U
1864 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
1865 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
1866 
1867 #define GPIO_PUPDR_PUPDR15 0xC0000000U
1868 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
1869 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
1870 
1871 /****************** Bits definition for GPIO_IDR register *******************/
1872 #define GPIO_IDR_IDR_0 0x00000001U
1873 #define GPIO_IDR_IDR_1 0x00000002U
1874 #define GPIO_IDR_IDR_2 0x00000004U
1875 #define GPIO_IDR_IDR_3 0x00000008U
1876 #define GPIO_IDR_IDR_4 0x00000010U
1877 #define GPIO_IDR_IDR_5 0x00000020U
1878 #define GPIO_IDR_IDR_6 0x00000040U
1879 #define GPIO_IDR_IDR_7 0x00000080U
1880 #define GPIO_IDR_IDR_8 0x00000100U
1881 #define GPIO_IDR_IDR_9 0x00000200U
1882 #define GPIO_IDR_IDR_10 0x00000400U
1883 #define GPIO_IDR_IDR_11 0x00000800U
1884 #define GPIO_IDR_IDR_12 0x00001000U
1885 #define GPIO_IDR_IDR_13 0x00002000U
1886 #define GPIO_IDR_IDR_14 0x00004000U
1887 #define GPIO_IDR_IDR_15 0x00008000U
1888 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
1889 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
1890 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
1891 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
1892 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
1893 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
1894 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
1895 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
1896 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
1897 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
1898 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
1899 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
1900 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
1901 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
1902 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
1903 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
1904 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
1905 
1906 /****************** Bits definition for GPIO_ODR register *******************/
1907 #define GPIO_ODR_ODR_0 0x00000001U
1908 #define GPIO_ODR_ODR_1 0x00000002U
1909 #define GPIO_ODR_ODR_2 0x00000004U
1910 #define GPIO_ODR_ODR_3 0x00000008U
1911 #define GPIO_ODR_ODR_4 0x00000010U
1912 #define GPIO_ODR_ODR_5 0x00000020U
1913 #define GPIO_ODR_ODR_6 0x00000040U
1914 #define GPIO_ODR_ODR_7 0x00000080U
1915 #define GPIO_ODR_ODR_8 0x00000100U
1916 #define GPIO_ODR_ODR_9 0x00000200U
1917 #define GPIO_ODR_ODR_10 0x00000400U
1918 #define GPIO_ODR_ODR_11 0x00000800U
1919 #define GPIO_ODR_ODR_12 0x00001000U
1920 #define GPIO_ODR_ODR_13 0x00002000U
1921 #define GPIO_ODR_ODR_14 0x00004000U
1922 #define GPIO_ODR_ODR_15 0x00008000U
1923 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
1924 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
1925 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
1926 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
1927 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
1928 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
1929 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
1930 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
1931 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
1932 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
1933 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
1934 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
1935 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
1936 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
1937 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
1938 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
1939 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
1940 
1941 /****************** Bits definition for GPIO_BSRR register ******************/
1942 #define GPIO_BSRR_BS_0 0x00000001U
1943 #define GPIO_BSRR_BS_1 0x00000002U
1944 #define GPIO_BSRR_BS_2 0x00000004U
1945 #define GPIO_BSRR_BS_3 0x00000008U
1946 #define GPIO_BSRR_BS_4 0x00000010U
1947 #define GPIO_BSRR_BS_5 0x00000020U
1948 #define GPIO_BSRR_BS_6 0x00000040U
1949 #define GPIO_BSRR_BS_7 0x00000080U
1950 #define GPIO_BSRR_BS_8 0x00000100U
1951 #define GPIO_BSRR_BS_9 0x00000200U
1952 #define GPIO_BSRR_BS_10 0x00000400U
1953 #define GPIO_BSRR_BS_11 0x00000800U
1954 #define GPIO_BSRR_BS_12 0x00001000U
1955 #define GPIO_BSRR_BS_13 0x00002000U
1956 #define GPIO_BSRR_BS_14 0x00004000U
1957 #define GPIO_BSRR_BS_15 0x00008000U
1958 #define GPIO_BSRR_BR_0 0x00010000U
1959 #define GPIO_BSRR_BR_1 0x00020000U
1960 #define GPIO_BSRR_BR_2 0x00040000U
1961 #define GPIO_BSRR_BR_3 0x00080000U
1962 #define GPIO_BSRR_BR_4 0x00100000U
1963 #define GPIO_BSRR_BR_5 0x00200000U
1964 #define GPIO_BSRR_BR_6 0x00400000U
1965 #define GPIO_BSRR_BR_7 0x00800000U
1966 #define GPIO_BSRR_BR_8 0x01000000U
1967 #define GPIO_BSRR_BR_9 0x02000000U
1968 #define GPIO_BSRR_BR_10 0x04000000U
1969 #define GPIO_BSRR_BR_11 0x08000000U
1970 #define GPIO_BSRR_BR_12 0x10000000U
1971 #define GPIO_BSRR_BR_13 0x20000000U
1972 #define GPIO_BSRR_BR_14 0x40000000U
1973 #define GPIO_BSRR_BR_15 0x80000000U
1974 
1975 /****************** Bit definition for GPIO_LCKR register ********************/
1976 #define GPIO_LCKR_LCK0 0x00000001U
1977 #define GPIO_LCKR_LCK1 0x00000002U
1978 #define GPIO_LCKR_LCK2 0x00000004U
1979 #define GPIO_LCKR_LCK3 0x00000008U
1980 #define GPIO_LCKR_LCK4 0x00000010U
1981 #define GPIO_LCKR_LCK5 0x00000020U
1982 #define GPIO_LCKR_LCK6 0x00000040U
1983 #define GPIO_LCKR_LCK7 0x00000080U
1984 #define GPIO_LCKR_LCK8 0x00000100U
1985 #define GPIO_LCKR_LCK9 0x00000200U
1986 #define GPIO_LCKR_LCK10 0x00000400U
1987 #define GPIO_LCKR_LCK11 0x00000800U
1988 #define GPIO_LCKR_LCK12 0x00001000U
1989 #define GPIO_LCKR_LCK13 0x00002000U
1990 #define GPIO_LCKR_LCK14 0x00004000U
1991 #define GPIO_LCKR_LCK15 0x00008000U
1992 #define GPIO_LCKR_LCKK 0x00010000U
1993 
1994 /******************************************************************************/
1995 /* */
1996 /* Inter-integrated Circuit Interface */
1997 /* */
1998 /******************************************************************************/
1999 /******************* Bit definition for I2C_CR1 register ********************/
2000 #define I2C_CR1_PE 0x00000001U
2001 #define I2C_CR1_SMBUS 0x00000002U
2002 #define I2C_CR1_SMBTYPE 0x00000008U
2003 #define I2C_CR1_ENARP 0x00000010U
2004 #define I2C_CR1_ENPEC 0x00000020U
2005 #define I2C_CR1_ENGC 0x00000040U
2006 #define I2C_CR1_NOSTRETCH 0x00000080U
2007 #define I2C_CR1_START 0x00000100U
2008 #define I2C_CR1_STOP 0x00000200U
2009 #define I2C_CR1_ACK 0x00000400U
2010 #define I2C_CR1_POS 0x00000800U
2011 #define I2C_CR1_PEC 0x00001000U
2012 #define I2C_CR1_ALERT 0x00002000U
2013 #define I2C_CR1_SWRST 0x00008000U
2015 /******************* Bit definition for I2C_CR2 register ********************/
2016 #define I2C_CR2_FREQ 0x0000003FU
2017 #define I2C_CR2_FREQ_0 0x00000001U
2018 #define I2C_CR2_FREQ_1 0x00000002U
2019 #define I2C_CR2_FREQ_2 0x00000004U
2020 #define I2C_CR2_FREQ_3 0x00000008U
2021 #define I2C_CR2_FREQ_4 0x00000010U
2022 #define I2C_CR2_FREQ_5 0x00000020U
2024 #define I2C_CR2_ITERREN 0x00000100U
2025 #define I2C_CR2_ITEVTEN 0x00000200U
2026 #define I2C_CR2_ITBUFEN 0x00000400U
2027 #define I2C_CR2_DMAEN 0x00000800U
2028 #define I2C_CR2_LAST 0x00001000U
2030 /******************* Bit definition for I2C_OAR1 register *******************/
2031 #define I2C_OAR1_ADD1_7 0x000000FEU
2032 #define I2C_OAR1_ADD8_9 0x00000300U
2034 #define I2C_OAR1_ADD0 0x00000001U
2035 #define I2C_OAR1_ADD1 0x00000002U
2036 #define I2C_OAR1_ADD2 0x00000004U
2037 #define I2C_OAR1_ADD3 0x00000008U
2038 #define I2C_OAR1_ADD4 0x00000010U
2039 #define I2C_OAR1_ADD5 0x00000020U
2040 #define I2C_OAR1_ADD6 0x00000040U
2041 #define I2C_OAR1_ADD7 0x00000080U
2042 #define I2C_OAR1_ADD8 0x00000100U
2043 #define I2C_OAR1_ADD9 0x00000200U
2045 #define I2C_OAR1_ADDMODE 0x00008000U
2047 /******************* Bit definition for I2C_OAR2 register *******************/
2048 #define I2C_OAR2_ENDUAL 0x00000001U
2049 #define I2C_OAR2_ADD2 0x000000FEU
2051 /******************** Bit definition for I2C_DR register ********************/
2052 #define I2C_DR_DR 0x000000FFU
2054 /******************* Bit definition for I2C_SR1 register ********************/
2055 #define I2C_SR1_SB 0x00000001U
2056 #define I2C_SR1_ADDR 0x00000002U
2057 #define I2C_SR1_BTF 0x00000004U
2058 #define I2C_SR1_ADD10 0x00000008U
2059 #define I2C_SR1_STOPF 0x00000010U
2060 #define I2C_SR1_RXNE 0x00000040U
2061 #define I2C_SR1_TXE 0x00000080U
2062 #define I2C_SR1_BERR 0x00000100U
2063 #define I2C_SR1_ARLO 0x00000200U
2064 #define I2C_SR1_AF 0x00000400U
2065 #define I2C_SR1_OVR 0x00000800U
2066 #define I2C_SR1_PECERR 0x00001000U
2067 #define I2C_SR1_TIMEOUT 0x00004000U
2068 #define I2C_SR1_SMBALERT 0x00008000U
2070 /******************* Bit definition for I2C_SR2 register ********************/
2071 #define I2C_SR2_MSL 0x00000001U
2072 #define I2C_SR2_BUSY 0x00000002U
2073 #define I2C_SR2_TRA 0x00000004U
2074 #define I2C_SR2_GENCALL 0x00000010U
2075 #define I2C_SR2_SMBDEFAULT 0x00000020U
2076 #define I2C_SR2_SMBHOST 0x00000040U
2077 #define I2C_SR2_DUALF 0x00000080U
2078 #define I2C_SR2_PEC 0x0000FF00U
2080 /******************* Bit definition for I2C_CCR register ********************/
2081 #define I2C_CCR_CCR 0x00000FFFU
2082 #define I2C_CCR_DUTY 0x00004000U
2083 #define I2C_CCR_FS 0x00008000U
2085 /****************** Bit definition for I2C_TRISE register *******************/
2086 #define I2C_TRISE_TRISE 0x0000003FU
2088 /****************** Bit definition for I2C_FLTR register *******************/
2089 #define I2C_FLTR_DNF 0x0000000FU
2090 #define I2C_FLTR_ANOFF 0x00000010U
2092 /******************************************************************************/
2093 /* */
2094 /* Independent WATCHDOG */
2095 /* */
2096 /******************************************************************************/
2097 /******************* Bit definition for IWDG_KR register ********************/
2098 #define IWDG_KR_KEY 0xFFFFU
2100 /******************* Bit definition for IWDG_PR register ********************/
2101 #define IWDG_PR_PR 0x07U
2102 #define IWDG_PR_PR_0 0x01U
2103 #define IWDG_PR_PR_1 0x02U
2104 #define IWDG_PR_PR_2 0x04U
2106 /******************* Bit definition for IWDG_RLR register *******************/
2107 #define IWDG_RLR_RL 0x0FFFU
2109 /******************* Bit definition for IWDG_SR register ********************/
2110 #define IWDG_SR_PVU 0x01U
2111 #define IWDG_SR_RVU 0x02U
2114 /******************************************************************************/
2115 /* */
2116 /* Power Control */
2117 /* */
2118 /******************************************************************************/
2119 /******************** Bit definition for PWR_CR register ********************/
2120 #define PWR_CR_LPDS 0x00000001U
2121 #define PWR_CR_PDDS 0x00000002U
2122 #define PWR_CR_CWUF 0x00000004U
2123 #define PWR_CR_CSBF 0x00000008U
2124 #define PWR_CR_PVDE 0x00000010U
2126 #define PWR_CR_PLS 0x000000E0U
2127 #define PWR_CR_PLS_0 0x00000020U
2128 #define PWR_CR_PLS_1 0x00000040U
2129 #define PWR_CR_PLS_2 0x00000080U
2132 #define PWR_CR_PLS_LEV0 0x00000000U
2133 #define PWR_CR_PLS_LEV1 0x00000020U
2134 #define PWR_CR_PLS_LEV2 0x00000040U
2135 #define PWR_CR_PLS_LEV3 0x00000060U
2136 #define PWR_CR_PLS_LEV4 0x00000080U
2137 #define PWR_CR_PLS_LEV5 0x000000A0U
2138 #define PWR_CR_PLS_LEV6 0x000000C0U
2139 #define PWR_CR_PLS_LEV7 0x000000E0U
2141 #define PWR_CR_DBP 0x00000100U
2142 #define PWR_CR_FPDS 0x00000200U
2143 #define PWR_CR_LPLVDS 0x00000400U
2144 #define PWR_CR_MRLVDS 0x00000800U
2145 #define PWR_CR_ADCDC1 0x00002000U
2146 #define PWR_CR_VOS 0x0000C000U
2147 #define PWR_CR_VOS_0 0x00004000U
2148 #define PWR_CR_VOS_1 0x00008000U
2150 /* Legacy define */
2151 #define PWR_CR_PMODE PWR_CR_VOS
2152 
2153 /******************* Bit definition for PWR_CSR register ********************/
2154 #define PWR_CSR_WUF 0x00000001U
2155 #define PWR_CSR_SBF 0x00000002U
2156 #define PWR_CSR_PVDO 0x00000004U
2157 #define PWR_CSR_BRR 0x00000008U
2158 #define PWR_CSR_EWUP 0x00000100U
2159 #define PWR_CSR_BRE 0x00000200U
2160 #define PWR_CSR_VOSRDY 0x00004000U
2162 /* Legacy define */
2163 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
2164 
2165 /******************************************************************************/
2166 /* */
2167 /* Reset and Clock Control */
2168 /* */
2169 /******************************************************************************/
2170 /******************** Bit definition for RCC_CR register ********************/
2171 #define RCC_CR_HSION 0x00000001U
2172 #define RCC_CR_HSIRDY 0x00000002U
2173 
2174 #define RCC_CR_HSITRIM 0x000000F8U
2175 #define RCC_CR_HSITRIM_0 0x00000008U
2176 #define RCC_CR_HSITRIM_1 0x00000010U
2177 #define RCC_CR_HSITRIM_2 0x00000020U
2178 #define RCC_CR_HSITRIM_3 0x00000040U
2179 #define RCC_CR_HSITRIM_4 0x00000080U
2181 #define RCC_CR_HSICAL 0x0000FF00U
2182 #define RCC_CR_HSICAL_0 0x00000100U
2183 #define RCC_CR_HSICAL_1 0x00000200U
2184 #define RCC_CR_HSICAL_2 0x00000400U
2185 #define RCC_CR_HSICAL_3 0x00000800U
2186 #define RCC_CR_HSICAL_4 0x00001000U
2187 #define RCC_CR_HSICAL_5 0x00002000U
2188 #define RCC_CR_HSICAL_6 0x00004000U
2189 #define RCC_CR_HSICAL_7 0x00008000U
2191 #define RCC_CR_HSEON 0x00010000U
2192 #define RCC_CR_HSERDY 0x00020000U
2193 #define RCC_CR_HSEBYP 0x00040000U
2194 #define RCC_CR_CSSON 0x00080000U
2195 #define RCC_CR_PLLON 0x01000000U
2196 #define RCC_CR_PLLRDY 0x02000000U
2197 #define RCC_CR_PLLI2SON 0x04000000U
2198 #define RCC_CR_PLLI2SRDY 0x08000000U
2199 
2200 /******************** Bit definition for RCC_PLLCFGR register ***************/
2201 #define RCC_PLLCFGR_PLLM 0x0000003FU
2202 #define RCC_PLLCFGR_PLLM_0 0x00000001U
2203 #define RCC_PLLCFGR_PLLM_1 0x00000002U
2204 #define RCC_PLLCFGR_PLLM_2 0x00000004U
2205 #define RCC_PLLCFGR_PLLM_3 0x00000008U
2206 #define RCC_PLLCFGR_PLLM_4 0x00000010U
2207 #define RCC_PLLCFGR_PLLM_5 0x00000020U
2208 
2209 #define RCC_PLLCFGR_PLLN 0x00007FC0U
2210 #define RCC_PLLCFGR_PLLN_0 0x00000040U
2211 #define RCC_PLLCFGR_PLLN_1 0x00000080U
2212 #define RCC_PLLCFGR_PLLN_2 0x00000100U
2213 #define RCC_PLLCFGR_PLLN_3 0x00000200U
2214 #define RCC_PLLCFGR_PLLN_4 0x00000400U
2215 #define RCC_PLLCFGR_PLLN_5 0x00000800U
2216 #define RCC_PLLCFGR_PLLN_6 0x00001000U
2217 #define RCC_PLLCFGR_PLLN_7 0x00002000U
2218 #define RCC_PLLCFGR_PLLN_8 0x00004000U
2219 
2220 #define RCC_PLLCFGR_PLLP 0x00030000U
2221 #define RCC_PLLCFGR_PLLP_0 0x00010000U
2222 #define RCC_PLLCFGR_PLLP_1 0x00020000U
2223 
2224 #define RCC_PLLCFGR_PLLSRC 0x00400000U
2225 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
2226 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
2227 
2228 #define RCC_PLLCFGR_PLLQ 0x0F000000U
2229 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
2230 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
2231 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
2232 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
2233 
2234 /******************** Bit definition for RCC_CFGR register ******************/
2236 #define RCC_CFGR_SW 0x00000003U
2237 #define RCC_CFGR_SW_0 0x00000001U
2238 #define RCC_CFGR_SW_1 0x00000002U
2240 #define RCC_CFGR_SW_HSI 0x00000000U
2241 #define RCC_CFGR_SW_HSE 0x00000001U
2242 #define RCC_CFGR_SW_PLL 0x00000002U
2245 #define RCC_CFGR_SWS 0x0000000CU
2246 #define RCC_CFGR_SWS_0 0x00000004U
2247 #define RCC_CFGR_SWS_1 0x00000008U
2249 #define RCC_CFGR_SWS_HSI 0x00000000U
2250 #define RCC_CFGR_SWS_HSE 0x00000004U
2251 #define RCC_CFGR_SWS_PLL 0x00000008U
2254 #define RCC_CFGR_HPRE 0x000000F0U
2255 #define RCC_CFGR_HPRE_0 0x00000010U
2256 #define RCC_CFGR_HPRE_1 0x00000020U
2257 #define RCC_CFGR_HPRE_2 0x00000040U
2258 #define RCC_CFGR_HPRE_3 0x00000080U
2260 #define RCC_CFGR_HPRE_DIV1 0x00000000U
2261 #define RCC_CFGR_HPRE_DIV2 0x00000080U
2262 #define RCC_CFGR_HPRE_DIV4 0x00000090U
2263 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
2264 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
2265 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
2266 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
2267 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
2268 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
2271 #define RCC_CFGR_PPRE1 0x00001C00U
2272 #define RCC_CFGR_PPRE1_0 0x00000400U
2273 #define RCC_CFGR_PPRE1_1 0x00000800U
2274 #define RCC_CFGR_PPRE1_2 0x00001000U
2276 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
2277 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
2278 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
2279 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
2280 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
2283 #define RCC_CFGR_PPRE2 0x0000E000U
2284 #define RCC_CFGR_PPRE2_0 0x00002000U
2285 #define RCC_CFGR_PPRE2_1 0x00004000U
2286 #define RCC_CFGR_PPRE2_2 0x00008000U
2288 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
2289 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
2290 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
2291 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
2292 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
2295 #define RCC_CFGR_RTCPRE 0x001F0000U
2296 #define RCC_CFGR_RTCPRE_0 0x00010000U
2297 #define RCC_CFGR_RTCPRE_1 0x00020000U
2298 #define RCC_CFGR_RTCPRE_2 0x00040000U
2299 #define RCC_CFGR_RTCPRE_3 0x00080000U
2300 #define RCC_CFGR_RTCPRE_4 0x00100000U
2301 
2303 #define RCC_CFGR_MCO1 0x00600000U
2304 #define RCC_CFGR_MCO1_0 0x00200000U
2305 #define RCC_CFGR_MCO1_1 0x00400000U
2306 
2307 #define RCC_CFGR_I2SSRC 0x00800000U
2308 
2309 #define RCC_CFGR_MCO1PRE 0x07000000U
2310 #define RCC_CFGR_MCO1PRE_0 0x01000000U
2311 #define RCC_CFGR_MCO1PRE_1 0x02000000U
2312 #define RCC_CFGR_MCO1PRE_2 0x04000000U
2313 
2314 #define RCC_CFGR_MCO2PRE 0x38000000U
2315 #define RCC_CFGR_MCO2PRE_0 0x08000000U
2316 #define RCC_CFGR_MCO2PRE_1 0x10000000U
2317 #define RCC_CFGR_MCO2PRE_2 0x20000000U
2318 
2319 #define RCC_CFGR_MCO2 0xC0000000U
2320 #define RCC_CFGR_MCO2_0 0x40000000U
2321 #define RCC_CFGR_MCO2_1 0x80000000U
2322 
2323 /******************** Bit definition for RCC_CIR register *******************/
2324 #define RCC_CIR_LSIRDYF 0x00000001U
2325 #define RCC_CIR_LSERDYF 0x00000002U
2326 #define RCC_CIR_HSIRDYF 0x00000004U
2327 #define RCC_CIR_HSERDYF 0x00000008U
2328 #define RCC_CIR_PLLRDYF 0x00000010U
2329 #define RCC_CIR_PLLI2SRDYF 0x00000020U
2330 
2331 #define RCC_CIR_CSSF 0x00000080U
2332 #define RCC_CIR_LSIRDYIE 0x00000100U
2333 #define RCC_CIR_LSERDYIE 0x00000200U
2334 #define RCC_CIR_HSIRDYIE 0x00000400U
2335 #define RCC_CIR_HSERDYIE 0x00000800U
2336 #define RCC_CIR_PLLRDYIE 0x00001000U
2337 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
2338 
2339 #define RCC_CIR_LSIRDYC 0x00010000U
2340 #define RCC_CIR_LSERDYC 0x00020000U
2341 #define RCC_CIR_HSIRDYC 0x00040000U
2342 #define RCC_CIR_HSERDYC 0x00080000U
2343 #define RCC_CIR_PLLRDYC 0x00100000U
2344 #define RCC_CIR_PLLI2SRDYC 0x00200000U
2345 
2346 #define RCC_CIR_CSSC 0x00800000U
2347 
2348 /******************** Bit definition for RCC_AHB1RSTR register **************/
2349 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
2350 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
2351 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
2352 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
2353 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
2354 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
2355 #define RCC_AHB1RSTR_CRCRST 0x00001000U
2356 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
2357 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
2358 
2359 /******************** Bit definition for RCC_AHB2RSTR register **************/
2360 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
2361 
2362 /******************** Bit definition for RCC_AHB3RSTR register **************/
2363 
2364 /******************** Bit definition for RCC_APB1RSTR register **************/
2365 #define RCC_APB1RSTR_TIM2RST 0x00000001U
2366 #define RCC_APB1RSTR_TIM3RST 0x00000002U
2367 #define RCC_APB1RSTR_TIM4RST 0x00000004U
2368 #define RCC_APB1RSTR_TIM5RST 0x00000008U
2369 #define RCC_APB1RSTR_WWDGRST 0x00000800U
2370 #define RCC_APB1RSTR_SPI2RST 0x00004000U
2371 #define RCC_APB1RSTR_SPI3RST 0x00008000U
2372 #define RCC_APB1RSTR_USART2RST 0x00020000U
2373 #define RCC_APB1RSTR_I2C1RST 0x00200000U
2374 #define RCC_APB1RSTR_I2C2RST 0x00400000U
2375 #define RCC_APB1RSTR_I2C3RST 0x00800000U
2376 #define RCC_APB1RSTR_PWRRST 0x10000000U
2377 
2378 /******************** Bit definition for RCC_APB2RSTR register **************/
2379 #define RCC_APB2RSTR_TIM1RST 0x00000001U
2380 #define RCC_APB2RSTR_USART1RST 0x00000010U
2381 #define RCC_APB2RSTR_USART6RST 0x00000020U
2382 #define RCC_APB2RSTR_ADCRST 0x00000100U
2383 #define RCC_APB2RSTR_SDIORST 0x00000800U
2384 #define RCC_APB2RSTR_SPI1RST 0x00001000U
2385 #define RCC_APB2RSTR_SPI4RST 0x00002000U
2386 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
2387 #define RCC_APB2RSTR_TIM9RST 0x00010000U
2388 #define RCC_APB2RSTR_TIM10RST 0x00020000U
2389 #define RCC_APB2RSTR_TIM11RST 0x00040000U
2390 
2391 /* Old SPI1RST bit definition, maintained for legacy purpose */
2392 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
2393 
2394 /******************** Bit definition for RCC_AHB1ENR register ***************/
2395 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
2396 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
2397 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
2398 #define RCC_AHB1ENR_GPIODEN 0x00000008U
2399 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
2400 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
2401 #define RCC_AHB1ENR_CRCEN 0x00001000U
2402 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
2403 #define RCC_AHB1ENR_DMA1EN 0x00200000U
2404 #define RCC_AHB1ENR_DMA2EN 0x00400000U
2405 
2406 /******************** Bit definition for RCC_AHB2ENR register ***************/
2407 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
2408 
2409 /******************** Bit definition for RCC_AHB3ENR register ***************/
2410 
2411 /******************** Bit definition for RCC_APB1ENR register ***************/
2412 #define RCC_APB1ENR_TIM2EN 0x00000001U
2413 #define RCC_APB1ENR_TIM3EN 0x00000002U
2414 #define RCC_APB1ENR_TIM4EN 0x00000004U
2415 #define RCC_APB1ENR_TIM5EN 0x00000008U
2416 #define RCC_APB1ENR_WWDGEN 0x00000800U
2417 #define RCC_APB1ENR_SPI2EN 0x00004000U
2418 #define RCC_APB1ENR_SPI3EN 0x00008000U
2419 #define RCC_APB1ENR_USART2EN 0x00020000U
2420 #define RCC_APB1ENR_I2C1EN 0x00200000U
2421 #define RCC_APB1ENR_I2C2EN 0x00400000U
2422 #define RCC_APB1ENR_I2C3EN 0x00800000U
2423 #define RCC_APB1ENR_PWREN 0x10000000U
2424 
2425 /******************** Bit definition for RCC_APB2ENR register ***************/
2426 #define RCC_APB2ENR_TIM1EN 0x00000001U
2427 #define RCC_APB2ENR_USART1EN 0x00000010U
2428 #define RCC_APB2ENR_USART6EN 0x00000020U
2429 #define RCC_APB2ENR_ADC1EN 0x00000100U
2430 #define RCC_APB2ENR_SDIOEN 0x00000800U
2431 #define RCC_APB2ENR_SPI1EN 0x00001000U
2432 #define RCC_APB2ENR_SPI4EN 0x00002000U
2433 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
2434 #define RCC_APB2ENR_TIM9EN 0x00010000U
2435 #define RCC_APB2ENR_TIM10EN 0x00020000U
2436 #define RCC_APB2ENR_TIM11EN 0x00040000U
2437 
2438 /******************** Bit definition for RCC_AHB1LPENR register *************/
2439 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
2440 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
2441 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
2442 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
2443 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
2444 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
2445 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
2446 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
2447 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
2448 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
2449 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
2450 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
2451 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
2452 
2453 /******************** Bit definition for RCC_AHB2LPENR register *************/
2454 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
2455 
2456 /******************** Bit definition for RCC_AHB3LPENR register *************/
2457 
2458 /******************** Bit definition for RCC_APB1LPENR register *************/
2459 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
2460 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
2461 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
2462 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
2463 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
2464 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
2465 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
2466 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
2467 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
2468 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
2469 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
2470 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
2471 #define RCC_APB1LPENR_DACLPEN 0x20000000U
2472 
2473 /******************** Bit definition for RCC_APB2LPENR register *************/
2474 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
2475 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
2476 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
2477 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
2478 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
2479 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
2480 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
2481 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
2482 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
2483 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
2484 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
2485 
2486 /******************** Bit definition for RCC_BDCR register ******************/
2487 #define RCC_BDCR_LSEON 0x00000001U
2488 #define RCC_BDCR_LSERDY 0x00000002U
2489 #define RCC_BDCR_LSEBYP 0x00000004U
2490 
2491 #define RCC_BDCR_RTCSEL 0x00000300U
2492 #define RCC_BDCR_RTCSEL_0 0x00000100U
2493 #define RCC_BDCR_RTCSEL_1 0x00000200U
2494 
2495 #define RCC_BDCR_RTCEN 0x00008000U
2496 #define RCC_BDCR_BDRST 0x00010000U
2497 
2498 /******************** Bit definition for RCC_CSR register *******************/
2499 #define RCC_CSR_LSION 0x00000001U
2500 #define RCC_CSR_LSIRDY 0x00000002U
2501 #define RCC_CSR_RMVF 0x01000000U
2502 #define RCC_CSR_BORRSTF 0x02000000U
2503 #define RCC_CSR_PADRSTF 0x04000000U
2504 #define RCC_CSR_PORRSTF 0x08000000U
2505 #define RCC_CSR_SFTRSTF 0x10000000U
2506 #define RCC_CSR_WDGRSTF 0x20000000U
2507 #define RCC_CSR_WWDGRSTF 0x40000000U
2508 #define RCC_CSR_LPWRRSTF 0x80000000U
2509 
2510 /******************** Bit definition for RCC_SSCGR register *****************/
2511 #define RCC_SSCGR_MODPER 0x00001FFFU
2512 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
2513 #define RCC_SSCGR_SPREADSEL 0x40000000U
2514 #define RCC_SSCGR_SSCGEN 0x80000000U
2515 
2516 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
2517 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
2518 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
2519 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
2520 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
2521 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
2522 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
2523 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
2524 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
2525 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
2526 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
2527 
2528 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
2529 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
2530 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
2531 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
2532 
2533 /******************** Bit definition for RCC_DCKCFGR register ***************/
2534 #define RCC_DCKCFGR_TIMPRE 0x01000000U
2535 
2536 /******************************************************************************/
2537 /* */
2538 /* Real-Time Clock (RTC) */
2539 /* */
2540 /******************************************************************************/
2541 /******************** Bits definition for RTC_TR register *******************/
2542 #define RTC_TR_PM 0x00400000U
2543 #define RTC_TR_HT 0x00300000U
2544 #define RTC_TR_HT_0 0x00100000U
2545 #define RTC_TR_HT_1 0x00200000U
2546 #define RTC_TR_HU 0x000F0000U
2547 #define RTC_TR_HU_0 0x00010000U
2548 #define RTC_TR_HU_1 0x00020000U
2549 #define RTC_TR_HU_2 0x00040000U
2550 #define RTC_TR_HU_3 0x00080000U
2551 #define RTC_TR_MNT 0x00007000U
2552 #define RTC_TR_MNT_0 0x00001000U
2553 #define RTC_TR_MNT_1 0x00002000U
2554 #define RTC_TR_MNT_2 0x00004000U
2555 #define RTC_TR_MNU 0x00000F00U
2556 #define RTC_TR_MNU_0 0x00000100U
2557 #define RTC_TR_MNU_1 0x00000200U
2558 #define RTC_TR_MNU_2 0x00000400U
2559 #define RTC_TR_MNU_3 0x00000800U
2560 #define RTC_TR_ST 0x00000070U
2561 #define RTC_TR_ST_0 0x00000010U
2562 #define RTC_TR_ST_1 0x00000020U
2563 #define RTC_TR_ST_2 0x00000040U
2564 #define RTC_TR_SU 0x0000000FU
2565 #define RTC_TR_SU_0 0x00000001U
2566 #define RTC_TR_SU_1 0x00000002U
2567 #define RTC_TR_SU_2 0x00000004U
2568 #define RTC_TR_SU_3 0x00000008U
2569 
2570 /******************** Bits definition for RTC_DR register *******************/
2571 #define RTC_DR_YT 0x00F00000U
2572 #define RTC_DR_YT_0 0x00100000U
2573 #define RTC_DR_YT_1 0x00200000U
2574 #define RTC_DR_YT_2 0x00400000U
2575 #define RTC_DR_YT_3 0x00800000U
2576 #define RTC_DR_YU 0x000F0000U
2577 #define RTC_DR_YU_0 0x00010000U
2578 #define RTC_DR_YU_1 0x00020000U
2579 #define RTC_DR_YU_2 0x00040000U
2580 #define RTC_DR_YU_3 0x00080000U
2581 #define RTC_DR_WDU 0x0000E000U
2582 #define RTC_DR_WDU_0 0x00002000U
2583 #define RTC_DR_WDU_1 0x00004000U
2584 #define RTC_DR_WDU_2 0x00008000U
2585 #define RTC_DR_MT 0x00001000U
2586 #define RTC_DR_MU 0x00000F00U
2587 #define RTC_DR_MU_0 0x00000100U
2588 #define RTC_DR_MU_1 0x00000200U
2589 #define RTC_DR_MU_2 0x00000400U
2590 #define RTC_DR_MU_3 0x00000800U
2591 #define RTC_DR_DT 0x00000030U
2592 #define RTC_DR_DT_0 0x00000010U
2593 #define RTC_DR_DT_1 0x00000020U
2594 #define RTC_DR_DU 0x0000000FU
2595 #define RTC_DR_DU_0 0x00000001U
2596 #define RTC_DR_DU_1 0x00000002U
2597 #define RTC_DR_DU_2 0x00000004U
2598 #define RTC_DR_DU_3 0x00000008U
2599 
2600 /******************** Bits definition for RTC_CR register *******************/
2601 #define RTC_CR_COE 0x00800000U
2602 #define RTC_CR_OSEL 0x00600000U
2603 #define RTC_CR_OSEL_0 0x00200000U
2604 #define RTC_CR_OSEL_1 0x00400000U
2605 #define RTC_CR_POL 0x00100000U
2606 #define RTC_CR_COSEL 0x00080000U
2607 #define RTC_CR_BCK 0x00040000U
2608 #define RTC_CR_SUB1H 0x00020000U
2609 #define RTC_CR_ADD1H 0x00010000U
2610 #define RTC_CR_TSIE 0x00008000U
2611 #define RTC_CR_WUTIE 0x00004000U
2612 #define RTC_CR_ALRBIE 0x00002000U
2613 #define RTC_CR_ALRAIE 0x00001000U
2614 #define RTC_CR_TSE 0x00000800U
2615 #define RTC_CR_WUTE 0x00000400U
2616 #define RTC_CR_ALRBE 0x00000200U
2617 #define RTC_CR_ALRAE 0x00000100U
2618 #define RTC_CR_DCE 0x00000080U
2619 #define RTC_CR_FMT 0x00000040U
2620 #define RTC_CR_BYPSHAD 0x00000020U
2621 #define RTC_CR_REFCKON 0x00000010U
2622 #define RTC_CR_TSEDGE 0x00000008U
2623 #define RTC_CR_WUCKSEL 0x00000007U
2624 #define RTC_CR_WUCKSEL_0 0x00000001U
2625 #define RTC_CR_WUCKSEL_1 0x00000002U
2626 #define RTC_CR_WUCKSEL_2 0x00000004U
2627 
2628 /******************** Bits definition for RTC_ISR register ******************/
2629 #define RTC_ISR_RECALPF 0x00010000U
2630 #define RTC_ISR_TAMP1F 0x00002000U
2631 #define RTC_ISR_TAMP2F 0x00004000U
2632 #define RTC_ISR_TSOVF 0x00001000U
2633 #define RTC_ISR_TSF 0x00000800U
2634 #define RTC_ISR_WUTF 0x00000400U
2635 #define RTC_ISR_ALRBF 0x00000200U
2636 #define RTC_ISR_ALRAF 0x00000100U
2637 #define RTC_ISR_INIT 0x00000080U
2638 #define RTC_ISR_INITF 0x00000040U
2639 #define RTC_ISR_RSF 0x00000020U
2640 #define RTC_ISR_INITS 0x00000010U
2641 #define RTC_ISR_SHPF 0x00000008U
2642 #define RTC_ISR_WUTWF 0x00000004U
2643 #define RTC_ISR_ALRBWF 0x00000002U
2644 #define RTC_ISR_ALRAWF 0x00000001U
2645 
2646 /******************** Bits definition for RTC_PRER register *****************/
2647 #define RTC_PRER_PREDIV_A 0x007F0000U
2648 #define RTC_PRER_PREDIV_S 0x00007FFFU
2649 
2650 /******************** Bits definition for RTC_WUTR register *****************/
2651 #define RTC_WUTR_WUT 0x0000FFFFU
2652 
2653 /******************** Bits definition for RTC_CALIBR register ***************/
2654 #define RTC_CALIBR_DCS 0x00000080U
2655 #define RTC_CALIBR_DC 0x0000001FU
2656 
2657 /******************** Bits definition for RTC_ALRMAR register ***************/
2658 #define RTC_ALRMAR_MSK4 0x80000000U
2659 #define RTC_ALRMAR_WDSEL 0x40000000U
2660 #define RTC_ALRMAR_DT 0x30000000U
2661 #define RTC_ALRMAR_DT_0 0x10000000U
2662 #define RTC_ALRMAR_DT_1 0x20000000U
2663 #define RTC_ALRMAR_DU 0x0F000000U
2664 #define RTC_ALRMAR_DU_0 0x01000000U
2665 #define RTC_ALRMAR_DU_1 0x02000000U
2666 #define RTC_ALRMAR_DU_2 0x04000000U
2667 #define RTC_ALRMAR_DU_3 0x08000000U
2668 #define RTC_ALRMAR_MSK3 0x00800000U
2669 #define RTC_ALRMAR_PM 0x00400000U
2670 #define RTC_ALRMAR_HT 0x00300000U
2671 #define RTC_ALRMAR_HT_0 0x00100000U
2672 #define RTC_ALRMAR_HT_1 0x00200000U
2673 #define RTC_ALRMAR_HU 0x000F0000U
2674 #define RTC_ALRMAR_HU_0 0x00010000U
2675 #define RTC_ALRMAR_HU_1 0x00020000U
2676 #define RTC_ALRMAR_HU_2 0x00040000U
2677 #define RTC_ALRMAR_HU_3 0x00080000U
2678 #define RTC_ALRMAR_MSK2 0x00008000U
2679 #define RTC_ALRMAR_MNT 0x00007000U
2680 #define RTC_ALRMAR_MNT_0 0x00001000U
2681 #define RTC_ALRMAR_MNT_1 0x00002000U
2682 #define RTC_ALRMAR_MNT_2 0x00004000U
2683 #define RTC_ALRMAR_MNU 0x00000F00U
2684 #define RTC_ALRMAR_MNU_0 0x00000100U
2685 #define RTC_ALRMAR_MNU_1 0x00000200U
2686 #define RTC_ALRMAR_MNU_2 0x00000400U
2687 #define RTC_ALRMAR_MNU_3 0x00000800U
2688 #define RTC_ALRMAR_MSK1 0x00000080U
2689 #define RTC_ALRMAR_ST 0x00000070U
2690 #define RTC_ALRMAR_ST_0 0x00000010U
2691 #define RTC_ALRMAR_ST_1 0x00000020U
2692 #define RTC_ALRMAR_ST_2 0x00000040U
2693 #define RTC_ALRMAR_SU 0x0000000FU
2694 #define RTC_ALRMAR_SU_0 0x00000001U
2695 #define RTC_ALRMAR_SU_1 0x00000002U
2696 #define RTC_ALRMAR_SU_2 0x00000004U
2697 #define RTC_ALRMAR_SU_3 0x00000008U
2698 
2699 /******************** Bits definition for RTC_ALRMBR register ***************/
2700 #define RTC_ALRMBR_MSK4 0x80000000U
2701 #define RTC_ALRMBR_WDSEL 0x40000000U
2702 #define RTC_ALRMBR_DT 0x30000000U
2703 #define RTC_ALRMBR_DT_0 0x10000000U
2704 #define RTC_ALRMBR_DT_1 0x20000000U
2705 #define RTC_ALRMBR_DU 0x0F000000U
2706 #define RTC_ALRMBR_DU_0 0x01000000U
2707 #define RTC_ALRMBR_DU_1 0x02000000U
2708 #define RTC_ALRMBR_DU_2 0x04000000U
2709 #define RTC_ALRMBR_DU_3 0x08000000U
2710 #define RTC_ALRMBR_MSK3 0x00800000U
2711 #define RTC_ALRMBR_PM 0x00400000U
2712 #define RTC_ALRMBR_HT 0x00300000U
2713 #define RTC_ALRMBR_HT_0 0x00100000U
2714 #define RTC_ALRMBR_HT_1 0x00200000U
2715 #define RTC_ALRMBR_HU 0x000F0000U
2716 #define RTC_ALRMBR_HU_0 0x00010000U
2717 #define RTC_ALRMBR_HU_1 0x00020000U
2718 #define RTC_ALRMBR_HU_2 0x00040000U
2719 #define RTC_ALRMBR_HU_3 0x00080000U
2720 #define RTC_ALRMBR_MSK2 0x00008000U
2721 #define RTC_ALRMBR_MNT 0x00007000U
2722 #define RTC_ALRMBR_MNT_0 0x00001000U
2723 #define RTC_ALRMBR_MNT_1 0x00002000U
2724 #define RTC_ALRMBR_MNT_2 0x00004000U
2725 #define RTC_ALRMBR_MNU 0x00000F00U
2726 #define RTC_ALRMBR_MNU_0 0x00000100U
2727 #define RTC_ALRMBR_MNU_1 0x00000200U
2728 #define RTC_ALRMBR_MNU_2 0x00000400U
2729 #define RTC_ALRMBR_MNU_3 0x00000800U
2730 #define RTC_ALRMBR_MSK1 0x00000080U
2731 #define RTC_ALRMBR_ST 0x00000070U
2732 #define RTC_ALRMBR_ST_0 0x00000010U
2733 #define RTC_ALRMBR_ST_1 0x00000020U
2734 #define RTC_ALRMBR_ST_2 0x00000040U
2735 #define RTC_ALRMBR_SU 0x0000000FU
2736 #define RTC_ALRMBR_SU_0 0x00000001U
2737 #define RTC_ALRMBR_SU_1 0x00000002U
2738 #define RTC_ALRMBR_SU_2 0x00000004U
2739 #define RTC_ALRMBR_SU_3 0x00000008U
2740 
2741 /******************** Bits definition for RTC_WPR register ******************/
2742 #define RTC_WPR_KEY 0x000000FFU
2743 
2744 /******************** Bits definition for RTC_SSR register ******************/
2745 #define RTC_SSR_SS 0x0000FFFFU
2746 
2747 /******************** Bits definition for RTC_SHIFTR register ***************/
2748 #define RTC_SHIFTR_SUBFS 0x00007FFFU
2749 #define RTC_SHIFTR_ADD1S 0x80000000U
2750 
2751 /******************** Bits definition for RTC_TSTR register *****************/
2752 #define RTC_TSTR_PM 0x00400000U
2753 #define RTC_TSTR_HT 0x00300000U
2754 #define RTC_TSTR_HT_0 0x00100000U
2755 #define RTC_TSTR_HT_1 0x00200000U
2756 #define RTC_TSTR_HU 0x000F0000U
2757 #define RTC_TSTR_HU_0 0x00010000U
2758 #define RTC_TSTR_HU_1 0x00020000U
2759 #define RTC_TSTR_HU_2 0x00040000U
2760 #define RTC_TSTR_HU_3 0x00080000U
2761 #define RTC_TSTR_MNT 0x00007000U
2762 #define RTC_TSTR_MNT_0 0x00001000U
2763 #define RTC_TSTR_MNT_1 0x00002000U
2764 #define RTC_TSTR_MNT_2 0x00004000U
2765 #define RTC_TSTR_MNU 0x00000F00U
2766 #define RTC_TSTR_MNU_0 0x00000100U
2767 #define RTC_TSTR_MNU_1 0x00000200U
2768 #define RTC_TSTR_MNU_2 0x00000400U
2769 #define RTC_TSTR_MNU_3 0x00000800U
2770 #define RTC_TSTR_ST 0x00000070U
2771 #define RTC_TSTR_ST_0 0x00000010U
2772 #define RTC_TSTR_ST_1 0x00000020U
2773 #define RTC_TSTR_ST_2 0x00000040U
2774 #define RTC_TSTR_SU 0x0000000FU
2775 #define RTC_TSTR_SU_0 0x00000001U
2776 #define RTC_TSTR_SU_1 0x00000002U
2777 #define RTC_TSTR_SU_2 0x00000004U
2778 #define RTC_TSTR_SU_3 0x00000008U
2779 
2780 /******************** Bits definition for RTC_TSDR register *****************/
2781 #define RTC_TSDR_WDU 0x0000E000U
2782 #define RTC_TSDR_WDU_0 0x00002000U
2783 #define RTC_TSDR_WDU_1 0x00004000U
2784 #define RTC_TSDR_WDU_2 0x00008000U
2785 #define RTC_TSDR_MT 0x00001000U
2786 #define RTC_TSDR_MU 0x00000F00U
2787 #define RTC_TSDR_MU_0 0x00000100U
2788 #define RTC_TSDR_MU_1 0x00000200U
2789 #define RTC_TSDR_MU_2 0x00000400U
2790 #define RTC_TSDR_MU_3 0x00000800U
2791 #define RTC_TSDR_DT 0x00000030U
2792 #define RTC_TSDR_DT_0 0x00000010U
2793 #define RTC_TSDR_DT_1 0x00000020U
2794 #define RTC_TSDR_DU 0x0000000FU
2795 #define RTC_TSDR_DU_0 0x00000001U
2796 #define RTC_TSDR_DU_1 0x00000002U
2797 #define RTC_TSDR_DU_2 0x00000004U
2798 #define RTC_TSDR_DU_3 0x00000008U
2799 
2800 /******************** Bits definition for RTC_TSSSR register ****************/
2801 #define RTC_TSSSR_SS 0x0000FFFFU
2802 
2803 /******************** Bits definition for RTC_CAL register *****************/
2804 #define RTC_CALR_CALP 0x00008000U
2805 #define RTC_CALR_CALW8 0x00004000U
2806 #define RTC_CALR_CALW16 0x00002000U
2807 #define RTC_CALR_CALM 0x000001FFU
2808 #define RTC_CALR_CALM_0 0x00000001U
2809 #define RTC_CALR_CALM_1 0x00000002U
2810 #define RTC_CALR_CALM_2 0x00000004U
2811 #define RTC_CALR_CALM_3 0x00000008U
2812 #define RTC_CALR_CALM_4 0x00000010U
2813 #define RTC_CALR_CALM_5 0x00000020U
2814 #define RTC_CALR_CALM_6 0x00000040U
2815 #define RTC_CALR_CALM_7 0x00000080U
2816 #define RTC_CALR_CALM_8 0x00000100U
2817 
2818 /******************** Bits definition for RTC_TAFCR register ****************/
2819 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
2820 #define RTC_TAFCR_TSINSEL 0x00020000U
2821 #define RTC_TAFCR_TAMPINSEL 0x00010000U
2822 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
2823 #define RTC_TAFCR_TAMPPRCH 0x00006000U
2824 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
2825 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
2826 #define RTC_TAFCR_TAMPFLT 0x00001800U
2827 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
2828 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
2829 #define RTC_TAFCR_TAMPFREQ 0x00000700U
2830 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
2831 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
2832 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
2833 #define RTC_TAFCR_TAMPTS 0x00000080U
2834 #define RTC_TAFCR_TAMP2TRG 0x00000010U
2835 #define RTC_TAFCR_TAMP2E 0x00000008U
2836 #define RTC_TAFCR_TAMPIE 0x00000004U
2837 #define RTC_TAFCR_TAMP1TRG 0x00000002U
2838 #define RTC_TAFCR_TAMP1E 0x00000001U
2839 
2840 /******************** Bits definition for RTC_ALRMASSR register *************/
2841 #define RTC_ALRMASSR_MASKSS 0x0F000000U
2842 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
2843 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
2844 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
2845 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
2846 #define RTC_ALRMASSR_SS 0x00007FFFU
2847 
2848 /******************** Bits definition for RTC_ALRMBSSR register *************/
2849 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
2850 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
2851 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
2852 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
2853 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
2854 #define RTC_ALRMBSSR_SS 0x00007FFFU
2855 
2856 /******************** Bits definition for RTC_BKP0R register ****************/
2857 #define RTC_BKP0R 0xFFFFFFFFU
2858 
2859 /******************** Bits definition for RTC_BKP1R register ****************/
2860 #define RTC_BKP1R 0xFFFFFFFFU
2861 
2862 /******************** Bits definition for RTC_BKP2R register ****************/
2863 #define RTC_BKP2R 0xFFFFFFFFU
2864 
2865 /******************** Bits definition for RTC_BKP3R register ****************/
2866 #define RTC_BKP3R 0xFFFFFFFFU
2867 
2868 /******************** Bits definition for RTC_BKP4R register ****************/
2869 #define RTC_BKP4R 0xFFFFFFFFU
2870 
2871 /******************** Bits definition for RTC_BKP5R register ****************/
2872 #define RTC_BKP5R 0xFFFFFFFFU
2873 
2874 /******************** Bits definition for RTC_BKP6R register ****************/
2875 #define RTC_BKP6R 0xFFFFFFFFU
2876 
2877 /******************** Bits definition for RTC_BKP7R register ****************/
2878 #define RTC_BKP7R 0xFFFFFFFFU
2879 
2880 /******************** Bits definition for RTC_BKP8R register ****************/
2881 #define RTC_BKP8R 0xFFFFFFFFU
2882 
2883 /******************** Bits definition for RTC_BKP9R register ****************/
2884 #define RTC_BKP9R 0xFFFFFFFFU
2885 
2886 /******************** Bits definition for RTC_BKP10R register ***************/
2887 #define RTC_BKP10R 0xFFFFFFFFU
2888 
2889 /******************** Bits definition for RTC_BKP11R register ***************/
2890 #define RTC_BKP11R 0xFFFFFFFFU
2891 
2892 /******************** Bits definition for RTC_BKP12R register ***************/
2893 #define RTC_BKP12R 0xFFFFFFFFU
2894 
2895 /******************** Bits definition for RTC_BKP13R register ***************/
2896 #define RTC_BKP13R 0xFFFFFFFFU
2897 
2898 /******************** Bits definition for RTC_BKP14R register ***************/
2899 #define RTC_BKP14R 0xFFFFFFFFU
2900 
2901 /******************** Bits definition for RTC_BKP15R register ***************/
2902 #define RTC_BKP15R 0xFFFFFFFFU
2903 
2904 /******************** Bits definition for RTC_BKP16R register ***************/
2905 #define RTC_BKP16R 0xFFFFFFFFU
2906 
2907 /******************** Bits definition for RTC_BKP17R register ***************/
2908 #define RTC_BKP17R 0xFFFFFFFFU
2909 
2910 /******************** Bits definition for RTC_BKP18R register ***************/
2911 #define RTC_BKP18R 0xFFFFFFFFU
2912 
2913 /******************** Bits definition for RTC_BKP19R register ***************/
2914 #define RTC_BKP19R 0xFFFFFFFFU
2915 
2916 
2917 
2918 /******************************************************************************/
2919 /* */
2920 /* SD host Interface */
2921 /* */
2922 /******************************************************************************/
2923 /****************** Bit definition for SDIO_POWER register ******************/
2924 #define SDIO_POWER_PWRCTRL 0x03U
2925 #define SDIO_POWER_PWRCTRL_0 0x01U
2926 #define SDIO_POWER_PWRCTRL_1 0x02U
2928 /****************** Bit definition for SDIO_CLKCR register ******************/
2929 #define SDIO_CLKCR_CLKDIV 0x00FFU
2930 #define SDIO_CLKCR_CLKEN 0x0100U
2931 #define SDIO_CLKCR_PWRSAV 0x0200U
2932 #define SDIO_CLKCR_BYPASS 0x0400U
2934 #define SDIO_CLKCR_WIDBUS 0x1800U
2935 #define SDIO_CLKCR_WIDBUS_0 0x0800U
2936 #define SDIO_CLKCR_WIDBUS_1 0x1000U
2938 #define SDIO_CLKCR_NEGEDGE 0x2000U
2939 #define SDIO_CLKCR_HWFC_EN 0x4000U
2941 /******************* Bit definition for SDIO_ARG register *******************/
2942 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
2944 /******************* Bit definition for SDIO_CMD register *******************/
2945 #define SDIO_CMD_CMDINDEX 0x003FU
2947 #define SDIO_CMD_WAITRESP 0x00C0U
2948 #define SDIO_CMD_WAITRESP_0 0x0040U
2949 #define SDIO_CMD_WAITRESP_1 0x0080U
2951 #define SDIO_CMD_WAITINT 0x0100U
2952 #define SDIO_CMD_WAITPEND 0x0200U
2953 #define SDIO_CMD_CPSMEN 0x0400U
2954 #define SDIO_CMD_SDIOSUSPEND 0x0800U
2955 #define SDIO_CMD_ENCMDCOMPL 0x1000U
2956 #define SDIO_CMD_NIEN 0x2000U
2957 #define SDIO_CMD_CEATACMD 0x4000U
2959 /***************** Bit definition for SDIO_RESPCMD register *****************/
2960 #define SDIO_RESPCMD_RESPCMD 0x3FU
2962 /****************** Bit definition for SDIO_RESP0 register ******************/
2963 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
2965 /****************** Bit definition for SDIO_RESP1 register ******************/
2966 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
2968 /****************** Bit definition for SDIO_RESP2 register ******************/
2969 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
2971 /****************** Bit definition for SDIO_RESP3 register ******************/
2972 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
2974 /****************** Bit definition for SDIO_RESP4 register ******************/
2975 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
2977 /****************** Bit definition for SDIO_DTIMER register *****************/
2978 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
2980 /****************** Bit definition for SDIO_DLEN register *******************/
2981 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
2983 /****************** Bit definition for SDIO_DCTRL register ******************/
2984 #define SDIO_DCTRL_DTEN 0x0001U
2985 #define SDIO_DCTRL_DTDIR 0x0002U
2986 #define SDIO_DCTRL_DTMODE 0x0004U
2987 #define SDIO_DCTRL_DMAEN 0x0008U
2989 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
2990 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
2991 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
2992 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
2993 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
2995 #define SDIO_DCTRL_RWSTART 0x0100U
2996 #define SDIO_DCTRL_RWSTOP 0x0200U
2997 #define SDIO_DCTRL_RWMOD 0x0400U
2998 #define SDIO_DCTRL_SDIOEN 0x0800U
3000 /****************** Bit definition for SDIO_DCOUNT register *****************/
3001 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
3003 /****************** Bit definition for SDIO_STA register ********************/
3004 #define SDIO_STA_CCRCFAIL 0x00000001U
3005 #define SDIO_STA_DCRCFAIL 0x00000002U
3006 #define SDIO_STA_CTIMEOUT 0x00000004U
3007 #define SDIO_STA_DTIMEOUT 0x00000008U
3008 #define SDIO_STA_TXUNDERR 0x00000010U
3009 #define SDIO_STA_RXOVERR 0x00000020U
3010 #define SDIO_STA_CMDREND 0x00000040U
3011 #define SDIO_STA_CMDSENT 0x00000080U
3012 #define SDIO_STA_DATAEND 0x00000100U
3013 #define SDIO_STA_STBITERR 0x00000200U
3014 #define SDIO_STA_DBCKEND 0x00000400U
3015 #define SDIO_STA_CMDACT 0x00000800U
3016 #define SDIO_STA_TXACT 0x00001000U
3017 #define SDIO_STA_RXACT 0x00002000U
3018 #define SDIO_STA_TXFIFOHE 0x00004000U
3019 #define SDIO_STA_RXFIFOHF 0x00008000U
3020 #define SDIO_STA_TXFIFOF 0x00010000U
3021 #define SDIO_STA_RXFIFOF 0x00020000U
3022 #define SDIO_STA_TXFIFOE 0x00040000U
3023 #define SDIO_STA_RXFIFOE 0x00080000U
3024 #define SDIO_STA_TXDAVL 0x00100000U
3025 #define SDIO_STA_RXDAVL 0x00200000U
3026 #define SDIO_STA_SDIOIT 0x00400000U
3027 #define SDIO_STA_CEATAEND 0x00800000U
3029 /******************* Bit definition for SDIO_ICR register *******************/
3030 #define SDIO_ICR_CCRCFAILC 0x00000001U
3031 #define SDIO_ICR_DCRCFAILC 0x00000002U
3032 #define SDIO_ICR_CTIMEOUTC 0x00000004U
3033 #define SDIO_ICR_DTIMEOUTC 0x00000008U
3034 #define SDIO_ICR_TXUNDERRC 0x00000010U
3035 #define SDIO_ICR_RXOVERRC 0x00000020U
3036 #define SDIO_ICR_CMDRENDC 0x00000040U
3037 #define SDIO_ICR_CMDSENTC 0x00000080U
3038 #define SDIO_ICR_DATAENDC 0x00000100U
3039 #define SDIO_ICR_STBITERRC 0x00000200U
3040 #define SDIO_ICR_DBCKENDC 0x00000400U
3041 #define SDIO_ICR_SDIOITC 0x00400000U
3042 #define SDIO_ICR_CEATAENDC 0x00800000U
3044 /****************** Bit definition for SDIO_MASK register *******************/
3045 #define SDIO_MASK_CCRCFAILIE 0x00000001U
3046 #define SDIO_MASK_DCRCFAILIE 0x00000002U
3047 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
3048 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
3049 #define SDIO_MASK_TXUNDERRIE 0x00000010U
3050 #define SDIO_MASK_RXOVERRIE 0x00000020U
3051 #define SDIO_MASK_CMDRENDIE 0x00000040U
3052 #define SDIO_MASK_CMDSENTIE 0x00000080U
3053 #define SDIO_MASK_DATAENDIE 0x00000100U
3054 #define SDIO_MASK_STBITERRIE 0x00000200U
3055 #define SDIO_MASK_DBCKENDIE 0x00000400U
3056 #define SDIO_MASK_CMDACTIE 0x00000800U
3057 #define SDIO_MASK_TXACTIE 0x00001000U
3058 #define SDIO_MASK_RXACTIE 0x00002000U
3059 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
3060 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
3061 #define SDIO_MASK_TXFIFOFIE 0x00010000U
3062 #define SDIO_MASK_RXFIFOFIE 0x00020000U
3063 #define SDIO_MASK_TXFIFOEIE 0x00040000U
3064 #define SDIO_MASK_RXFIFOEIE 0x00080000U
3065 #define SDIO_MASK_TXDAVLIE 0x00100000U
3066 #define SDIO_MASK_RXDAVLIE 0x00200000U
3067 #define SDIO_MASK_SDIOITIE 0x00400000U
3068 #define SDIO_MASK_CEATAENDIE 0x00800000U
3070 /***************** Bit definition for SDIO_FIFOCNT register *****************/
3071 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
3073 /****************** Bit definition for SDIO_FIFO register *******************/
3074 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
3076 /******************************************************************************/
3077 /* */
3078 /* Serial Peripheral Interface */
3079 /* */
3080 /******************************************************************************/
3081 /******************* Bit definition for SPI_CR1 register ********************/
3082 #define SPI_CR1_CPHA 0x00000001U
3083 #define SPI_CR1_CPOL 0x00000002U
3084 #define SPI_CR1_MSTR 0x00000004U
3086 #define SPI_CR1_BR 0x00000038U
3087 #define SPI_CR1_BR_0 0x00000008U
3088 #define SPI_CR1_BR_1 0x00000010U
3089 #define SPI_CR1_BR_2 0x00000020U
3091 #define SPI_CR1_SPE 0x00000040U
3092 #define SPI_CR1_LSBFIRST 0x00000080U
3093 #define SPI_CR1_SSI 0x00000100U
3094 #define SPI_CR1_SSM 0x00000200U
3095 #define SPI_CR1_RXONLY 0x00000400U
3096 #define SPI_CR1_DFF 0x00000800U
3097 #define SPI_CR1_CRCNEXT 0x00001000U
3098 #define SPI_CR1_CRCEN 0x00002000U
3099 #define SPI_CR1_BIDIOE 0x00004000U
3100 #define SPI_CR1_BIDIMODE 0x00008000U
3102 /******************* Bit definition for SPI_CR2 register ********************/
3103 #define SPI_CR2_RXDMAEN 0x00000001U
3104 #define SPI_CR2_TXDMAEN 0x00000002U
3105 #define SPI_CR2_SSOE 0x00000004U
3106 #define SPI_CR2_FRF 0x00000010U
3107 #define SPI_CR2_ERRIE 0x00000020U
3108 #define SPI_CR2_RXNEIE 0x00000040U
3109 #define SPI_CR2_TXEIE 0x00000080U
3111 /******************** Bit definition for SPI_SR register ********************/
3112 #define SPI_SR_RXNE 0x00000001U
3113 #define SPI_SR_TXE 0x00000002U
3114 #define SPI_SR_CHSIDE 0x00000004U
3115 #define SPI_SR_UDR 0x00000008U
3116 #define SPI_SR_CRCERR 0x00000010U
3117 #define SPI_SR_MODF 0x00000020U
3118 #define SPI_SR_OVR 0x00000040U
3119 #define SPI_SR_BSY 0x00000080U
3120 #define SPI_SR_FRE 0x00000100U
3122 /******************** Bit definition for SPI_DR register ********************/
3123 #define SPI_DR_DR 0x0000FFFFU
3125 /******************* Bit definition for SPI_CRCPR register ******************/
3126 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
3128 /****************** Bit definition for SPI_RXCRCR register ******************/
3129 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
3131 /****************** Bit definition for SPI_TXCRCR register ******************/
3132 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
3134 /****************** Bit definition for SPI_I2SCFGR register *****************/
3135 #define SPI_I2SCFGR_CHLEN 0x00000001U
3137 #define SPI_I2SCFGR_DATLEN 0x00000006U
3138 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
3139 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
3141 #define SPI_I2SCFGR_CKPOL 0x00000008U
3143 #define SPI_I2SCFGR_I2SSTD 0x00000030U
3144 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
3145 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
3147 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
3149 #define SPI_I2SCFGR_I2SCFG 0x00000300U
3150 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
3151 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
3153 #define SPI_I2SCFGR_I2SE 0x00000400U
3154 #define SPI_I2SCFGR_I2SMOD 0x00000800U
3156 /****************** Bit definition for SPI_I2SPR register *******************/
3157 #define SPI_I2SPR_I2SDIV 0x000000FFU
3158 #define SPI_I2SPR_ODD 0x00000100U
3159 #define SPI_I2SPR_MCKOE 0x00000200U
3161 /******************************************************************************/
3162 /* */
3163 /* SYSCFG */
3164 /* */
3165 /******************************************************************************/
3166 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
3167 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
3168 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
3169 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
3170 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
3171 
3172 /****************** Bit definition for SYSCFG_PMC register ******************/
3173 #define SYSCFG_PMC_ADC1DC2 0x00010000U
3175 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
3176 #define SYSCFG_EXTICR1_EXTI0 0x000FU
3177 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
3178 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
3179 #define SYSCFG_EXTICR1_EXTI3 0xF000U
3183 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
3184 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
3185 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
3186 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
3187 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
3188 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
3193 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
3194 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
3195 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
3196 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
3197 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
3198 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
3203 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
3204 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
3205 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
3206 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
3207 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
3208 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
3213 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
3214 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
3215 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
3216 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
3217 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
3218 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
3220 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
3221 #define SYSCFG_EXTICR2_EXTI4 0x000FU
3222 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
3223 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
3224 #define SYSCFG_EXTICR2_EXTI7 0xF000U
3228 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
3229 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
3230 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
3231 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
3232 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
3233 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
3238 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
3239 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
3240 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
3241 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
3242 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
3243 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
3248 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
3249 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
3250 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
3251 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
3252 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
3253 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
3258 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
3259 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
3260 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
3261 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
3262 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
3263 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
3266 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
3267 #define SYSCFG_EXTICR3_EXTI8 0x000FU
3268 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
3269 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
3270 #define SYSCFG_EXTICR3_EXTI11 0xF000U
3275 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
3276 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
3277 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
3278 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
3279 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
3280 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
3285 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
3286 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
3287 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
3288 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
3289 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
3290 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
3295 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
3296 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
3297 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
3298 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
3299 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
3300 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
3305 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
3306 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
3307 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
3308 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
3309 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
3310 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
3312 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
3313 #define SYSCFG_EXTICR4_EXTI12 0x000FU
3314 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
3315 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
3316 #define SYSCFG_EXTICR4_EXTI15 0xF000U
3320 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
3321 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
3322 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
3323 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
3324 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
3325 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
3330 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
3331 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
3332 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
3333 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
3334 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
3335 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
3340 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
3341 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
3342 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
3343 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
3344 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
3345 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
3350 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
3351 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
3352 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
3353 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
3354 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
3355 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
3357 /****************** Bit definition for SYSCFG_CMPCR register ****************/
3358 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
3359 #define SYSCFG_CMPCR_READY 0x00000100U
3361 /******************************************************************************/
3362 /* */
3363 /* TIM */
3364 /* */
3365 /******************************************************************************/
3366 /******************* Bit definition for TIM_CR1 register ********************/
3367 #define TIM_CR1_CEN 0x0001U
3368 #define TIM_CR1_UDIS 0x0002U
3369 #define TIM_CR1_URS 0x0004U
3370 #define TIM_CR1_OPM 0x0008U
3371 #define TIM_CR1_DIR 0x0010U
3373 #define TIM_CR1_CMS 0x0060U
3374 #define TIM_CR1_CMS_0 0x0020U
3375 #define TIM_CR1_CMS_1 0x0040U
3377 #define TIM_CR1_ARPE 0x0080U
3379 #define TIM_CR1_CKD 0x0300U
3380 #define TIM_CR1_CKD_0 0x0100U
3381 #define TIM_CR1_CKD_1 0x0200U
3383 /******************* Bit definition for TIM_CR2 register ********************/
3384 #define TIM_CR2_CCPC 0x0001U
3385 #define TIM_CR2_CCUS 0x0004U
3386 #define TIM_CR2_CCDS 0x0008U
3388 #define TIM_CR2_MMS 0x0070U
3389 #define TIM_CR2_MMS_0 0x0010U
3390 #define TIM_CR2_MMS_1 0x0020U
3391 #define TIM_CR2_MMS_2 0x0040U
3393 #define TIM_CR2_TI1S 0x0080U
3394 #define TIM_CR2_OIS1 0x0100U
3395 #define TIM_CR2_OIS1N 0x0200U
3396 #define TIM_CR2_OIS2 0x0400U
3397 #define TIM_CR2_OIS2N 0x0800U
3398 #define TIM_CR2_OIS3 0x1000U
3399 #define TIM_CR2_OIS3N 0x2000U
3400 #define TIM_CR2_OIS4 0x4000U
3402 /******************* Bit definition for TIM_SMCR register *******************/
3403 #define TIM_SMCR_SMS 0x0007U
3404 #define TIM_SMCR_SMS_0 0x0001U
3405 #define TIM_SMCR_SMS_1 0x0002U
3406 #define TIM_SMCR_SMS_2 0x0004U
3408 #define TIM_SMCR_TS 0x0070U
3409 #define TIM_SMCR_TS_0 0x0010U
3410 #define TIM_SMCR_TS_1 0x0020U
3411 #define TIM_SMCR_TS_2 0x0040U
3413 #define TIM_SMCR_MSM 0x0080U
3415 #define TIM_SMCR_ETF 0x0F00U
3416 #define TIM_SMCR_ETF_0 0x0100U
3417 #define TIM_SMCR_ETF_1 0x0200U
3418 #define TIM_SMCR_ETF_2 0x0400U
3419 #define TIM_SMCR_ETF_3 0x0800U
3421 #define TIM_SMCR_ETPS 0x3000U
3422 #define TIM_SMCR_ETPS_0 0x1000U
3423 #define TIM_SMCR_ETPS_1 0x2000U
3425 #define TIM_SMCR_ECE 0x4000U
3426 #define TIM_SMCR_ETP 0x8000U
3428 /******************* Bit definition for TIM_DIER register *******************/
3429 #define TIM_DIER_UIE 0x0001U
3430 #define TIM_DIER_CC1IE 0x0002U
3431 #define TIM_DIER_CC2IE 0x0004U
3432 #define TIM_DIER_CC3IE 0x0008U
3433 #define TIM_DIER_CC4IE 0x0010U
3434 #define TIM_DIER_COMIE 0x0020U
3435 #define TIM_DIER_TIE 0x0040U
3436 #define TIM_DIER_BIE 0x0080U
3437 #define TIM_DIER_UDE 0x0100U
3438 #define TIM_DIER_CC1DE 0x0200U
3439 #define TIM_DIER_CC2DE 0x0400U
3440 #define TIM_DIER_CC3DE 0x0800U
3441 #define TIM_DIER_CC4DE 0x1000U
3442 #define TIM_DIER_COMDE 0x2000U
3443 #define TIM_DIER_TDE 0x4000U
3445 /******************** Bit definition for TIM_SR register ********************/
3446 #define TIM_SR_UIF 0x0001U
3447 #define TIM_SR_CC1IF 0x0002U
3448 #define TIM_SR_CC2IF 0x0004U
3449 #define TIM_SR_CC3IF 0x0008U
3450 #define TIM_SR_CC4IF 0x0010U
3451 #define TIM_SR_COMIF 0x0020U
3452 #define TIM_SR_TIF 0x0040U
3453 #define TIM_SR_BIF 0x0080U
3454 #define TIM_SR_CC1OF 0x0200U
3455 #define TIM_SR_CC2OF 0x0400U
3456 #define TIM_SR_CC3OF 0x0800U
3457 #define TIM_SR_CC4OF 0x1000U
3459 /******************* Bit definition for TIM_EGR register ********************/
3460 #define TIM_EGR_UG 0x01U
3461 #define TIM_EGR_CC1G 0x02U
3462 #define TIM_EGR_CC2G 0x04U
3463 #define TIM_EGR_CC3G 0x08U
3464 #define TIM_EGR_CC4G 0x10U
3465 #define TIM_EGR_COMG 0x20U
3466 #define TIM_EGR_TG 0x40U
3467 #define TIM_EGR_BG 0x80U
3469 /****************** Bit definition for TIM_CCMR1 register *******************/
3470 #define TIM_CCMR1_CC1S 0x0003U
3471 #define TIM_CCMR1_CC1S_0 0x0001U
3472 #define TIM_CCMR1_CC1S_1 0x0002U
3474 #define TIM_CCMR1_OC1FE 0x0004U
3475 #define TIM_CCMR1_OC1PE 0x0008U
3477 #define TIM_CCMR1_OC1M 0x0070U
3478 #define TIM_CCMR1_OC1M_0 0x0010U
3479 #define TIM_CCMR1_OC1M_1 0x0020U
3480 #define TIM_CCMR1_OC1M_2 0x0040U
3482 #define TIM_CCMR1_OC1CE 0x0080U
3484 #define TIM_CCMR1_CC2S 0x0300U
3485 #define TIM_CCMR1_CC2S_0 0x0100U
3486 #define TIM_CCMR1_CC2S_1 0x0200U
3488 #define TIM_CCMR1_OC2FE 0x0400U
3489 #define TIM_CCMR1_OC2PE 0x0800U
3491 #define TIM_CCMR1_OC2M 0x7000U
3492 #define TIM_CCMR1_OC2M_0 0x1000U
3493 #define TIM_CCMR1_OC2M_1 0x2000U
3494 #define TIM_CCMR1_OC2M_2 0x4000U
3496 #define TIM_CCMR1_OC2CE 0x8000U
3498 /*----------------------------------------------------------------------------*/
3499 
3500 #define TIM_CCMR1_IC1PSC 0x000CU
3501 #define TIM_CCMR1_IC1PSC_0 0x0004U
3502 #define TIM_CCMR1_IC1PSC_1 0x0008U
3504 #define TIM_CCMR1_IC1F 0x00F0U
3505 #define TIM_CCMR1_IC1F_0 0x0010U
3506 #define TIM_CCMR1_IC1F_1 0x0020U
3507 #define TIM_CCMR1_IC1F_2 0x0040U
3508 #define TIM_CCMR1_IC1F_3 0x0080U
3510 #define TIM_CCMR1_IC2PSC 0x0C00U
3511 #define TIM_CCMR1_IC2PSC_0 0x0400U
3512 #define TIM_CCMR1_IC2PSC_1 0x0800U
3514 #define TIM_CCMR1_IC2F 0xF000U
3515 #define TIM_CCMR1_IC2F_0 0x1000U
3516 #define TIM_CCMR1_IC2F_1 0x2000U
3517 #define TIM_CCMR1_IC2F_2 0x4000U
3518 #define TIM_CCMR1_IC2F_3 0x8000U
3520 /****************** Bit definition for TIM_CCMR2 register *******************/
3521 #define TIM_CCMR2_CC3S 0x0003U
3522 #define TIM_CCMR2_CC3S_0 0x0001U
3523 #define TIM_CCMR2_CC3S_1 0x0002U
3525 #define TIM_CCMR2_OC3FE 0x0004U
3526 #define TIM_CCMR2_OC3PE 0x0008U
3528 #define TIM_CCMR2_OC3M 0x0070U
3529 #define TIM_CCMR2_OC3M_0 0x0010U
3530 #define TIM_CCMR2_OC3M_1 0x0020U
3531 #define TIM_CCMR2_OC3M_2 0x0040U
3533 #define TIM_CCMR2_OC3CE 0x0080U
3535 #define TIM_CCMR2_CC4S 0x0300U
3536 #define TIM_CCMR2_CC4S_0 0x0100U
3537 #define TIM_CCMR2_CC4S_1 0x0200U
3539 #define TIM_CCMR2_OC4FE 0x0400U
3540 #define TIM_CCMR2_OC4PE 0x0800U
3542 #define TIM_CCMR2_OC4M 0x7000U
3543 #define TIM_CCMR2_OC4M_0 0x1000U
3544 #define TIM_CCMR2_OC4M_1 0x2000U
3545 #define TIM_CCMR2_OC4M_2 0x4000U
3547 #define TIM_CCMR2_OC4CE 0x8000U
3549 /*----------------------------------------------------------------------------*/
3550 
3551 #define TIM_CCMR2_IC3PSC 0x000CU
3552 #define TIM_CCMR2_IC3PSC_0 0x0004U
3553 #define TIM_CCMR2_IC3PSC_1 0x0008U
3555 #define TIM_CCMR2_IC3F 0x00F0U
3556 #define TIM_CCMR2_IC3F_0 0x0010U
3557 #define TIM_CCMR2_IC3F_1 0x0020U
3558 #define TIM_CCMR2_IC3F_2 0x0040U
3559 #define TIM_CCMR2_IC3F_3 0x0080U
3561 #define TIM_CCMR2_IC4PSC 0x0C00U
3562 #define TIM_CCMR2_IC4PSC_0 0x0400U
3563 #define TIM_CCMR2_IC4PSC_1 0x0800U
3565 #define TIM_CCMR2_IC4F 0xF000U
3566 #define TIM_CCMR2_IC4F_0 0x1000U
3567 #define TIM_CCMR2_IC4F_1 0x2000U
3568 #define TIM_CCMR2_IC4F_2 0x4000U
3569 #define TIM_CCMR2_IC4F_3 0x8000U
3571 /******************* Bit definition for TIM_CCER register *******************/
3572 #define TIM_CCER_CC1E 0x0001U
3573 #define TIM_CCER_CC1P 0x0002U
3574 #define TIM_CCER_CC1NE 0x0004U
3575 #define TIM_CCER_CC1NP 0x0008U
3576 #define TIM_CCER_CC2E 0x0010U
3577 #define TIM_CCER_CC2P 0x0020U
3578 #define TIM_CCER_CC2NE 0x0040U
3579 #define TIM_CCER_CC2NP 0x0080U
3580 #define TIM_CCER_CC3E 0x0100U
3581 #define TIM_CCER_CC3P 0x0200U
3582 #define TIM_CCER_CC3NE 0x0400U
3583 #define TIM_CCER_CC3NP 0x0800U
3584 #define TIM_CCER_CC4E 0x1000U
3585 #define TIM_CCER_CC4P 0x2000U
3586 #define TIM_CCER_CC4NP 0x8000U
3588 /******************* Bit definition for TIM_CNT register ********************/
3589 #define TIM_CNT_CNT 0xFFFFU
3591 /******************* Bit definition for TIM_PSC register ********************/
3592 #define TIM_PSC_PSC 0xFFFFU
3594 /******************* Bit definition for TIM_ARR register ********************/
3595 #define TIM_ARR_ARR 0xFFFFU
3597 /******************* Bit definition for TIM_RCR register ********************/
3598 #define TIM_RCR_REP 0xFFU
3600 /******************* Bit definition for TIM_CCR1 register *******************/
3601 #define TIM_CCR1_CCR1 0xFFFFU
3603 /******************* Bit definition for TIM_CCR2 register *******************/
3604 #define TIM_CCR2_CCR2 0xFFFFU
3606 /******************* Bit definition for TIM_CCR3 register *******************/
3607 #define TIM_CCR3_CCR3 0xFFFFU
3609 /******************* Bit definition for TIM_CCR4 register *******************/
3610 #define TIM_CCR4_CCR4 0xFFFFU
3612 /******************* Bit definition for TIM_BDTR register *******************/
3613 #define TIM_BDTR_DTG 0x00FFU
3614 #define TIM_BDTR_DTG_0 0x0001U
3615 #define TIM_BDTR_DTG_1 0x0002U
3616 #define TIM_BDTR_DTG_2 0x0004U
3617 #define TIM_BDTR_DTG_3 0x0008U
3618 #define TIM_BDTR_DTG_4 0x0010U
3619 #define TIM_BDTR_DTG_5 0x0020U
3620 #define TIM_BDTR_DTG_6 0x0040U
3621 #define TIM_BDTR_DTG_7 0x0080U
3623 #define TIM_BDTR_LOCK 0x0300U
3624 #define TIM_BDTR_LOCK_0 0x0100U
3625 #define TIM_BDTR_LOCK_1 0x0200U
3627 #define TIM_BDTR_OSSI 0x0400U
3628 #define TIM_BDTR_OSSR 0x0800U
3629 #define TIM_BDTR_BKE 0x1000U
3630 #define TIM_BDTR_BKP 0x2000U
3631 #define TIM_BDTR_AOE 0x4000U
3632 #define TIM_BDTR_MOE 0x8000U
3634 /******************* Bit definition for TIM_DCR register ********************/
3635 #define TIM_DCR_DBA 0x001FU
3636 #define TIM_DCR_DBA_0 0x0001U
3637 #define TIM_DCR_DBA_1 0x0002U
3638 #define TIM_DCR_DBA_2 0x0004U
3639 #define TIM_DCR_DBA_3 0x0008U
3640 #define TIM_DCR_DBA_4 0x0010U
3642 #define TIM_DCR_DBL 0x1F00U
3643 #define TIM_DCR_DBL_0 0x0100U
3644 #define TIM_DCR_DBL_1 0x0200U
3645 #define TIM_DCR_DBL_2 0x0400U
3646 #define TIM_DCR_DBL_3 0x0800U
3647 #define TIM_DCR_DBL_4 0x1000U
3649 /******************* Bit definition for TIM_DMAR register *******************/
3650 #define TIM_DMAR_DMAB 0xFFFFU
3652 /******************* Bit definition for TIM_OR register *********************/
3653 #define TIM_OR_TI4_RMP 0x00C0U
3654 #define TIM_OR_TI4_RMP_0 0x0040U
3655 #define TIM_OR_TI4_RMP_1 0x0080U
3656 #define TIM_OR_ITR1_RMP 0x0C00U
3657 #define TIM_OR_ITR1_RMP_0 0x0400U
3658 #define TIM_OR_ITR1_RMP_1 0x0800U
3661 /******************************************************************************/
3662 /* */
3663 /* Universal Synchronous Asynchronous Receiver Transmitter */
3664 /* */
3665 /******************************************************************************/
3666 /******************* Bit definition for USART_SR register *******************/
3667 #define USART_SR_PE 0x0001U
3668 #define USART_SR_FE 0x0002U
3669 #define USART_SR_NE 0x0004U
3670 #define USART_SR_ORE 0x0008U
3671 #define USART_SR_IDLE 0x0010U
3672 #define USART_SR_RXNE 0x0020U
3673 #define USART_SR_TC 0x0040U
3674 #define USART_SR_TXE 0x0080U
3675 #define USART_SR_LBD 0x0100U
3676 #define USART_SR_CTS 0x0200U
3678 /******************* Bit definition for USART_DR register *******************/
3679 #define USART_DR_DR 0x01FFU
3681 /****************** Bit definition for USART_BRR register *******************/
3682 #define USART_BRR_DIV_Fraction 0x000FU
3683 #define USART_BRR_DIV_Mantissa 0xFFF0U
3685 /****************** Bit definition for USART_CR1 register *******************/
3686 #define USART_CR1_SBK 0x0001U
3687 #define USART_CR1_RWU 0x0002U
3688 #define USART_CR1_RE 0x0004U
3689 #define USART_CR1_TE 0x0008U
3690 #define USART_CR1_IDLEIE 0x0010U
3691 #define USART_CR1_RXNEIE 0x0020U
3692 #define USART_CR1_TCIE 0x0040U
3693 #define USART_CR1_TXEIE 0x0080U
3694 #define USART_CR1_PEIE 0x0100U
3695 #define USART_CR1_PS 0x0200U
3696 #define USART_CR1_PCE 0x0400U
3697 #define USART_CR1_WAKE 0x0800U
3698 #define USART_CR1_M 0x1000U
3699 #define USART_CR1_UE 0x2000U
3700 #define USART_CR1_OVER8 0x8000U
3702 /****************** Bit definition for USART_CR2 register *******************/
3703 #define USART_CR2_ADD 0x000FU
3704 #define USART_CR2_LBDL 0x0020U
3705 #define USART_CR2_LBDIE 0x0040U
3706 #define USART_CR2_LBCL 0x0100U
3707 #define USART_CR2_CPHA 0x0200U
3708 #define USART_CR2_CPOL 0x0400U
3709 #define USART_CR2_CLKEN 0x0800U
3711 #define USART_CR2_STOP 0x3000U
3712 #define USART_CR2_STOP_0 0x1000U
3713 #define USART_CR2_STOP_1 0x2000U
3715 #define USART_CR2_LINEN 0x4000U
3717 /****************** Bit definition for USART_CR3 register *******************/
3718 #define USART_CR3_EIE 0x0001U
3719 #define USART_CR3_IREN 0x0002U
3720 #define USART_CR3_IRLP 0x0004U
3721 #define USART_CR3_HDSEL 0x0008U
3722 #define USART_CR3_NACK 0x0010U
3723 #define USART_CR3_SCEN 0x0020U
3724 #define USART_CR3_DMAR 0x0040U
3725 #define USART_CR3_DMAT 0x0080U
3726 #define USART_CR3_RTSE 0x0100U
3727 #define USART_CR3_CTSE 0x0200U
3728 #define USART_CR3_CTSIE 0x0400U
3729 #define USART_CR3_ONEBIT 0x0800U
3731 /****************** Bit definition for USART_GTPR register ******************/
3732 #define USART_GTPR_PSC 0x00FFU
3733 #define USART_GTPR_PSC_0 0x0001U
3734 #define USART_GTPR_PSC_1 0x0002U
3735 #define USART_GTPR_PSC_2 0x0004U
3736 #define USART_GTPR_PSC_3 0x0008U
3737 #define USART_GTPR_PSC_4 0x0010U
3738 #define USART_GTPR_PSC_5 0x0020U
3739 #define USART_GTPR_PSC_6 0x0040U
3740 #define USART_GTPR_PSC_7 0x0080U
3742 #define USART_GTPR_GT 0xFF00U
3744 /******************************************************************************/
3745 /* */
3746 /* Window WATCHDOG */
3747 /* */
3748 /******************************************************************************/
3749 /******************* Bit definition for WWDG_CR register ********************/
3750 #define WWDG_CR_T 0x7FU
3751 #define WWDG_CR_T_0 0x01U
3752 #define WWDG_CR_T_1 0x02U
3753 #define WWDG_CR_T_2 0x04U
3754 #define WWDG_CR_T_3 0x08U
3755 #define WWDG_CR_T_4 0x10U
3756 #define WWDG_CR_T_5 0x20U
3757 #define WWDG_CR_T_6 0x40U
3758 /* Legacy defines */
3759 #define WWDG_CR_T0 WWDG_CR_T_0
3760 #define WWDG_CR_T1 WWDG_CR_T_1
3761 #define WWDG_CR_T2 WWDG_CR_T_2
3762 #define WWDG_CR_T3 WWDG_CR_T_3
3763 #define WWDG_CR_T4 WWDG_CR_T_4
3764 #define WWDG_CR_T5 WWDG_CR_T_5
3765 #define WWDG_CR_T6 WWDG_CR_T_6
3766 
3767 #define WWDG_CR_WDGA 0x80U
3769 /******************* Bit definition for WWDG_CFR register *******************/
3770 #define WWDG_CFR_W 0x007FU
3771 #define WWDG_CFR_W_0 0x0001U
3772 #define WWDG_CFR_W_1 0x0002U
3773 #define WWDG_CFR_W_2 0x0004U
3774 #define WWDG_CFR_W_3 0x0008U
3775 #define WWDG_CFR_W_4 0x0010U
3776 #define WWDG_CFR_W_5 0x0020U
3777 #define WWDG_CFR_W_6 0x0040U
3778 /* Legacy defines */
3779 #define WWDG_CFR_W0 WWDG_CFR_W_0
3780 #define WWDG_CFR_W1 WWDG_CFR_W_1
3781 #define WWDG_CFR_W2 WWDG_CFR_W_2
3782 #define WWDG_CFR_W3 WWDG_CFR_W_3
3783 #define WWDG_CFR_W4 WWDG_CFR_W_4
3784 #define WWDG_CFR_W5 WWDG_CFR_W_5
3785 #define WWDG_CFR_W6 WWDG_CFR_W_6
3786 
3787 #define WWDG_CFR_WDGTB 0x0180U
3788 #define WWDG_CFR_WDGTB_0 0x0080U
3789 #define WWDG_CFR_WDGTB_1 0x0100U
3790 /* Legacy defines */
3791 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
3792 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
3793 
3794 #define WWDG_CFR_EWI 0x0200U
3796 /******************* Bit definition for WWDG_SR register ********************/
3797 #define WWDG_SR_EWIF 0x01U
3800 /******************************************************************************/
3801 /* */
3802 /* DBG */
3803 /* */
3804 /******************************************************************************/
3805 /******************** Bit definition for DBGMCU_IDCODE register *************/
3806 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
3807 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
3808 
3809 /******************** Bit definition for DBGMCU_CR register *****************/
3810 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
3811 #define DBGMCU_CR_DBG_STOP 0x00000002U
3812 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
3813 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
3814 
3815 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
3816 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
3817 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
3819 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
3820 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
3821 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
3822 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
3823 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
3824 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
3825 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
3826 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
3827 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
3828 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
3829 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
3830 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
3831 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
3832 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
3833 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
3834 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
3835 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
3836 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
3837 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
3838 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
3839 
3840 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
3841 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
3842 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
3843 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
3844 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
3845 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
3846 
3847 /******************************************************************************/
3848 /* */
3849 /* USB_OTG */
3850 /* */
3851 /******************************************************************************/
3852 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
3853 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
3854 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
3855 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
3856 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
3857 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
3858 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
3859 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
3860 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
3861 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
3862 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
3864 /******************** Bit definition forUSB_OTG_HCFG register ********************/
3865 
3866 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
3867 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
3868 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
3869 #define USB_OTG_HCFG_FSLSS 0x00000004U
3871 /******************** Bit definition forUSB_OTG_DCFG register ********************/
3872 
3873 #define USB_OTG_DCFG_DSPD 0x00000003U
3874 #define USB_OTG_DCFG_DSPD_0 0x00000001U
3875 #define USB_OTG_DCFG_DSPD_1 0x00000002U
3876 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
3878 #define USB_OTG_DCFG_DAD 0x000007F0U
3879 #define USB_OTG_DCFG_DAD_0 0x00000010U
3880 #define USB_OTG_DCFG_DAD_1 0x00000020U
3881 #define USB_OTG_DCFG_DAD_2 0x00000040U
3882 #define USB_OTG_DCFG_DAD_3 0x00000080U
3883 #define USB_OTG_DCFG_DAD_4 0x00000100U
3884 #define USB_OTG_DCFG_DAD_5 0x00000200U
3885 #define USB_OTG_DCFG_DAD_6 0x00000400U
3887 #define USB_OTG_DCFG_PFIVL 0x00001800U
3888 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
3889 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
3891 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
3892 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
3893 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
3895 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
3896 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
3897 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
3898 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
3900 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
3901 #define USB_OTG_GOTGINT_SEDET 0x00000004U
3902 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
3903 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
3904 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
3905 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
3906 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
3908 /******************** Bit definition forUSB_OTG_DCTL register ********************/
3909 #define USB_OTG_DCTL_RWUSIG 0x00000001U
3910 #define USB_OTG_DCTL_SDIS 0x00000002U
3911 #define USB_OTG_DCTL_GINSTS 0x00000004U
3912 #define USB_OTG_DCTL_GONSTS 0x00000008U
3914 #define USB_OTG_DCTL_TCTL 0x00000070U
3915 #define USB_OTG_DCTL_TCTL_0 0x00000010U
3916 #define USB_OTG_DCTL_TCTL_1 0x00000020U
3917 #define USB_OTG_DCTL_TCTL_2 0x00000040U
3918 #define USB_OTG_DCTL_SGINAK 0x00000080U
3919 #define USB_OTG_DCTL_CGINAK 0x00000100U
3920 #define USB_OTG_DCTL_SGONAK 0x00000200U
3921 #define USB_OTG_DCTL_CGONAK 0x00000400U
3922 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
3924 /******************** Bit definition forUSB_OTG_HFIR register ********************/
3925 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
3927 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
3928 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
3929 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
3931 /******************** Bit definition forUSB_OTG_DSTS register ********************/
3932 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
3934 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
3935 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
3936 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
3937 #define USB_OTG_DSTS_EERR 0x00000008U
3938 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
3940 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
3941 #define USB_OTG_GAHBCFG_GINT 0x00000001U
3943 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
3944 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
3945 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
3946 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
3947 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
3948 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
3949 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
3950 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
3952 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
3953 
3954 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
3955 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
3956 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
3957 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
3958 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
3959 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
3960 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
3962 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
3963 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
3964 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
3965 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
3966 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
3967 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
3968 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
3969 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
3970 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
3971 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
3972 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
3973 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
3974 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
3975 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
3976 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
3977 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
3978 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
3979 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
3981 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
3982 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
3983 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
3984 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
3985 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
3986 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
3988 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
3989 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
3990 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
3991 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
3992 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
3993 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
3994 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
3995 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
3997 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
3998 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
3999 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
4000 #define USB_OTG_DIEPMSK_TOM 0x00000008U
4001 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
4002 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
4003 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
4004 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
4005 #define USB_OTG_DIEPMSK_BIM 0x00000200U
4007 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
4008 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
4010 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
4011 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
4012 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
4013 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
4014 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
4015 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
4016 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
4017 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
4018 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
4020 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
4021 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
4022 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
4023 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
4024 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
4025 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
4026 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
4027 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
4028 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
4030 /******************** Bit definition forUSB_OTG_HAINT register ********************/
4031 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
4033 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
4034 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
4035 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
4036 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
4037 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
4038 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
4039 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
4040 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
4042 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
4043 #define USB_OTG_GINTSTS_CMOD 0x00000001U
4044 #define USB_OTG_GINTSTS_MMIS 0x00000002U
4045 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
4046 #define USB_OTG_GINTSTS_SOF 0x00000008U
4047 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
4048 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
4049 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
4050 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
4051 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
4052 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
4053 #define USB_OTG_GINTSTS_USBRST 0x00001000U
4054 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
4055 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
4056 #define USB_OTG_GINTSTS_EOPF 0x00008000U
4057 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
4058 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
4059 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
4060 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
4061 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
4062 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
4063 #define USB_OTG_GINTSTS_HCINT 0x02000000U
4064 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
4065 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
4066 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
4067 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
4068 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
4070 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
4071 #define USB_OTG_GINTMSK_MMISM 0x00000002U
4072 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
4073 #define USB_OTG_GINTMSK_SOFM 0x00000008U
4074 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
4075 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
4076 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
4077 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
4078 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
4079 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
4080 #define USB_OTG_GINTMSK_USBRST 0x00001000U
4081 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
4082 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
4083 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
4084 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
4085 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
4086 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
4087 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
4088 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
4089 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
4090 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
4091 #define USB_OTG_GINTMSK_HCIM 0x02000000U
4092 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
4093 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
4094 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
4095 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
4096 #define USB_OTG_GINTMSK_WUIM 0x80000000U
4098 /******************** Bit definition forUSB_OTG_DAINT register ********************/
4099 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
4100 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
4102 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
4103 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
4105 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
4106 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
4107 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
4108 #define USB_OTG_GRXSTSP_DPID 0x00018000U
4109 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
4111 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
4112 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
4113 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
4115 /******************** Bit definition for OTG register ********************/
4116 
4117 #define USB_OTG_CHNUM 0x0000000FU
4118 #define USB_OTG_CHNUM_0 0x00000001U
4119 #define USB_OTG_CHNUM_1 0x00000002U
4120 #define USB_OTG_CHNUM_2 0x00000004U
4121 #define USB_OTG_CHNUM_3 0x00000008U
4122 #define USB_OTG_BCNT 0x00007FF0U
4124 #define USB_OTG_DPID 0x00018000U
4125 #define USB_OTG_DPID_0 0x00008000U
4126 #define USB_OTG_DPID_1 0x00010000U
4128 #define USB_OTG_PKTSTS 0x001E0000U
4129 #define USB_OTG_PKTSTS_0 0x00020000U
4130 #define USB_OTG_PKTSTS_1 0x00040000U
4131 #define USB_OTG_PKTSTS_2 0x00080000U
4132 #define USB_OTG_PKTSTS_3 0x00100000U
4134 #define USB_OTG_EPNUM 0x0000000FU
4135 #define USB_OTG_EPNUM_0 0x00000001U
4136 #define USB_OTG_EPNUM_1 0x00000002U
4137 #define USB_OTG_EPNUM_2 0x00000004U
4138 #define USB_OTG_EPNUM_3 0x00000008U
4140 #define USB_OTG_FRMNUM 0x01E00000U
4141 #define USB_OTG_FRMNUM_0 0x00200000U
4142 #define USB_OTG_FRMNUM_1 0x00400000U
4143 #define USB_OTG_FRMNUM_2 0x00800000U
4144 #define USB_OTG_FRMNUM_3 0x01000000U
4146 /******************** Bit definition for OTG register ********************/
4147 
4148 #define USB_OTG_CHNUM 0x0000000FU
4149 #define USB_OTG_CHNUM_0 0x00000001U
4150 #define USB_OTG_CHNUM_1 0x00000002U
4151 #define USB_OTG_CHNUM_2 0x00000004U
4152 #define USB_OTG_CHNUM_3 0x00000008U
4153 #define USB_OTG_BCNT 0x00007FF0U
4155 #define USB_OTG_DPID 0x00018000U
4156 #define USB_OTG_DPID_0 0x00008000U
4157 #define USB_OTG_DPID_1 0x00010000U
4159 #define USB_OTG_PKTSTS 0x001E0000U
4160 #define USB_OTG_PKTSTS_0 0x00020000U
4161 #define USB_OTG_PKTSTS_1 0x00040000U
4162 #define USB_OTG_PKTSTS_2 0x00080000U
4163 #define USB_OTG_PKTSTS_3 0x00100000U
4165 #define USB_OTG_EPNUM 0x0000000FU
4166 #define USB_OTG_EPNUM_0 0x00000001U
4167 #define USB_OTG_EPNUM_1 0x00000002U
4168 #define USB_OTG_EPNUM_2 0x00000004U
4169 #define USB_OTG_EPNUM_3 0x00000008U
4171 #define USB_OTG_FRMNUM 0x01E00000U
4172 #define USB_OTG_FRMNUM_0 0x00200000U
4173 #define USB_OTG_FRMNUM_1 0x00400000U
4174 #define USB_OTG_FRMNUM_2 0x00800000U
4175 #define USB_OTG_FRMNUM_3 0x01000000U
4177 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
4178 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
4180 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
4181 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
4183 /******************** Bit definition for OTG register ********************/
4184 #define USB_OTG_NPTXFSA 0x0000FFFFU
4185 #define USB_OTG_NPTXFD 0xFFFF0000U
4186 #define USB_OTG_TX0FSA 0x0000FFFFU
4187 #define USB_OTG_TX0FD 0xFFFF0000U
4189 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
4190 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
4192 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
4193 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
4195 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
4196 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
4197 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
4198 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
4199 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
4200 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
4201 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
4202 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
4203 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
4205 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
4206 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
4207 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
4208 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
4209 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
4210 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
4211 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
4212 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
4214 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
4215 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
4216 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
4218 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
4219 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
4220 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
4221 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
4222 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
4223 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
4224 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
4225 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
4226 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
4227 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
4228 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
4230 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
4231 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
4232 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
4233 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
4234 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
4235 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
4236 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
4237 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
4238 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
4239 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
4240 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
4242 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
4243 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
4245 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
4246 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
4247 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
4249 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
4250 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
4251 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
4252 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
4253 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
4254 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
4255 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
4257 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
4258 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
4259 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
4261 /******************** Bit definition forUSB_OTG_CID register ********************/
4262 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
4264 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
4265 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
4266 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
4267 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
4268 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
4269 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
4270 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
4271 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
4272 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
4273 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
4275 /******************** Bit definition forUSB_OTG_HPRT register ********************/
4276 #define USB_OTG_HPRT_PCSTS 0x00000001U
4277 #define USB_OTG_HPRT_PCDET 0x00000002U
4278 #define USB_OTG_HPRT_PENA 0x00000004U
4279 #define USB_OTG_HPRT_PENCHNG 0x00000008U
4280 #define USB_OTG_HPRT_POCA 0x00000010U
4281 #define USB_OTG_HPRT_POCCHNG 0x00000020U
4282 #define USB_OTG_HPRT_PRES 0x00000040U
4283 #define USB_OTG_HPRT_PSUSP 0x00000080U
4284 #define USB_OTG_HPRT_PRST 0x00000100U
4286 #define USB_OTG_HPRT_PLSTS 0x00000C00U
4287 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
4288 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
4289 #define USB_OTG_HPRT_PPWR 0x00001000U
4291 #define USB_OTG_HPRT_PTCTL 0x0001E000U
4292 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
4293 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
4294 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
4295 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
4297 #define USB_OTG_HPRT_PSPD 0x00060000U
4298 #define USB_OTG_HPRT_PSPD_0 0x00020000U
4299 #define USB_OTG_HPRT_PSPD_1 0x00040000U
4301 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
4302 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
4303 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
4304 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
4305 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
4306 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
4307 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
4308 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
4309 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
4310 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
4311 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
4312 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
4314 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
4315 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
4316 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
4318 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
4319 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
4320 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
4321 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
4322 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
4324 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
4325 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
4326 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
4327 #define USB_OTG_DIEPCTL_STALL 0x00200000U
4329 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
4330 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
4331 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
4332 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
4333 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
4334 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
4335 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
4336 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
4337 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
4338 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
4339 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
4341 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
4342 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
4344 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
4345 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
4346 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
4347 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
4348 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
4349 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
4350 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
4352 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
4353 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
4354 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
4356 #define USB_OTG_HCCHAR_MC 0x00300000U
4357 #define USB_OTG_HCCHAR_MC_0 0x00100000U
4358 #define USB_OTG_HCCHAR_MC_1 0x00200000U
4360 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
4361 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
4362 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
4363 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
4364 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
4365 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
4366 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
4367 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
4368 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
4369 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
4370 #define USB_OTG_HCCHAR_CHENA 0x80000000U
4372 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
4373 
4374 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
4375 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
4376 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
4377 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
4378 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
4379 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
4380 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
4381 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
4383 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
4384 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
4385 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
4386 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
4387 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
4388 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
4389 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
4390 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
4392 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
4393 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
4394 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
4395 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
4396 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
4398 /******************** Bit definition forUSB_OTG_HCINT register ********************/
4399 #define USB_OTG_HCINT_XFRC 0x00000001U
4400 #define USB_OTG_HCINT_CHH 0x00000002U
4401 #define USB_OTG_HCINT_AHBERR 0x00000004U
4402 #define USB_OTG_HCINT_STALL 0x00000008U
4403 #define USB_OTG_HCINT_NAK 0x00000010U
4404 #define USB_OTG_HCINT_ACK 0x00000020U
4405 #define USB_OTG_HCINT_NYET 0x00000040U
4406 #define USB_OTG_HCINT_TXERR 0x00000080U
4407 #define USB_OTG_HCINT_BBERR 0x00000100U
4408 #define USB_OTG_HCINT_FRMOR 0x00000200U
4409 #define USB_OTG_HCINT_DTERR 0x00000400U
4411 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
4412 #define USB_OTG_DIEPINT_XFRC 0x00000001U
4413 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
4414 #define USB_OTG_DIEPINT_TOC 0x00000008U
4415 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
4416 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
4417 #define USB_OTG_DIEPINT_TXFE 0x00000080U
4418 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
4419 #define USB_OTG_DIEPINT_BNA 0x00000200U
4420 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
4421 #define USB_OTG_DIEPINT_BERR 0x00001000U
4422 #define USB_OTG_DIEPINT_NAK 0x00002000U
4424 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
4425 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
4426 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
4427 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
4428 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
4429 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
4430 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
4431 #define USB_OTG_HCINTMSK_NYET 0x00000040U
4432 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
4433 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
4434 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
4435 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
4437 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
4438 
4439 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
4440 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
4441 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
4442 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
4443 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
4444 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
4445 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
4446 #define USB_OTG_HCTSIZ_DPID 0x60000000U
4447 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
4448 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
4450 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
4451 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
4453 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
4454 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
4456 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
4457 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
4459 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
4460 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
4461 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
4463 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
4464 
4465 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
4466 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
4467 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
4468 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
4469 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
4470 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
4471 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
4472 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
4473 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
4474 #define USB_OTG_DOEPCTL_STALL 0x00200000U
4475 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
4476 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
4477 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
4478 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
4480 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
4481 #define USB_OTG_DOEPINT_XFRC 0x00000001U
4482 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
4483 #define USB_OTG_DOEPINT_STUP 0x00000008U
4484 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
4485 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
4486 #define USB_OTG_DOEPINT_NYET 0x00004000U
4488 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
4489 
4490 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
4491 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
4493 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
4494 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
4495 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
4497 /******************** Bit definition for PCGCCTL register ********************/
4498 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
4499 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
4500 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
4514 /******************************* ADC Instances ********************************/
4515 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
4516 
4517 /******************************* CRC Instances ********************************/
4518 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
4519 
4520 /******************************** DMA Instances *******************************/
4521 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
4522  ((INSTANCE) == DMA1_Stream1) || \
4523  ((INSTANCE) == DMA1_Stream2) || \
4524  ((INSTANCE) == DMA1_Stream3) || \
4525  ((INSTANCE) == DMA1_Stream4) || \
4526  ((INSTANCE) == DMA1_Stream5) || \
4527  ((INSTANCE) == DMA1_Stream6) || \
4528  ((INSTANCE) == DMA1_Stream7) || \
4529  ((INSTANCE) == DMA2_Stream0) || \
4530  ((INSTANCE) == DMA2_Stream1) || \
4531  ((INSTANCE) == DMA2_Stream2) || \
4532  ((INSTANCE) == DMA2_Stream3) || \
4533  ((INSTANCE) == DMA2_Stream4) || \
4534  ((INSTANCE) == DMA2_Stream5) || \
4535  ((INSTANCE) == DMA2_Stream6) || \
4536  ((INSTANCE) == DMA2_Stream7))
4537 
4538 /******************************* GPIO Instances *******************************/
4539 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
4540  ((INSTANCE) == GPIOB) || \
4541  ((INSTANCE) == GPIOC) || \
4542  ((INSTANCE) == GPIOD) || \
4543  ((INSTANCE) == GPIOE) || \
4544  ((INSTANCE) == GPIOH))
4545 
4546 /******************************** I2C Instances *******************************/
4547 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
4548  ((INSTANCE) == I2C2) || \
4549  ((INSTANCE) == I2C3))
4550 
4551 /******************************** I2S Instances *******************************/
4552 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
4553  ((INSTANCE) == SPI3))
4554 
4555 /*************************** I2S Extended Instances ***************************/
4556 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
4557  ((INSTANCE) == SPI3) || \
4558  ((INSTANCE) == I2S2ext) || \
4559  ((INSTANCE) == I2S3ext))
4560 
4561 /****************************** RTC Instances *********************************/
4562 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
4563 
4564 /******************************** SPI Instances *******************************/
4565 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
4566  ((INSTANCE) == SPI2) || \
4567  ((INSTANCE) == SPI3) || \
4568  ((INSTANCE) == SPI4))
4569 
4570 /*************************** SPI Extended Instances ***************************/
4571 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
4572  ((INSTANCE) == SPI2) || \
4573  ((INSTANCE) == SPI3) || \
4574  ((INSTANCE) == I2S2ext) || \
4575  ((INSTANCE) == I2S3ext))
4576 
4577 /****************** TIM Instances : All supported instances *******************/
4578 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4579  ((INSTANCE) == TIM2) || \
4580  ((INSTANCE) == TIM3) || \
4581  ((INSTANCE) == TIM4) || \
4582  ((INSTANCE) == TIM5) || \
4583  ((INSTANCE) == TIM9) || \
4584  ((INSTANCE) == TIM10) || \
4585  ((INSTANCE) == TIM11))
4586 
4587 /************* TIM Instances : at least 1 capture/compare channel *************/
4588 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4589  ((INSTANCE) == TIM2) || \
4590  ((INSTANCE) == TIM3) || \
4591  ((INSTANCE) == TIM4) || \
4592  ((INSTANCE) == TIM5) || \
4593  ((INSTANCE) == TIM9) || \
4594  ((INSTANCE) == TIM10) || \
4595  ((INSTANCE) == TIM11))
4596 
4597 /************ TIM Instances : at least 2 capture/compare channels *************/
4598 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4599  ((INSTANCE) == TIM2) || \
4600  ((INSTANCE) == TIM3) || \
4601  ((INSTANCE) == TIM4) || \
4602  ((INSTANCE) == TIM5) || \
4603  ((INSTANCE) == TIM9))
4604 
4605 /************ TIM Instances : at least 3 capture/compare channels *************/
4606 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4607  ((INSTANCE) == TIM2) || \
4608  ((INSTANCE) == TIM3) || \
4609  ((INSTANCE) == TIM4) || \
4610  ((INSTANCE) == TIM5))
4611 
4612 /************ TIM Instances : at least 4 capture/compare channels *************/
4613 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4614  ((INSTANCE) == TIM2) || \
4615  ((INSTANCE) == TIM3) || \
4616  ((INSTANCE) == TIM4) || \
4617  ((INSTANCE) == TIM5))
4618 
4619 /******************** TIM Instances : Advanced-control timers *****************/
4620 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
4621 
4622 /******************* TIM Instances : Timer input XOR function *****************/
4623 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4624  ((INSTANCE) == TIM2) || \
4625  ((INSTANCE) == TIM3) || \
4626  ((INSTANCE) == TIM4) || \
4627  ((INSTANCE) == TIM5))
4628 
4629 /****************** TIM Instances : DMA requests generation (UDE) *************/
4630 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4631  ((INSTANCE) == TIM2) || \
4632  ((INSTANCE) == TIM3) || \
4633  ((INSTANCE) == TIM4) || \
4634  ((INSTANCE) == TIM5))
4635 
4636 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
4637 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4638  ((INSTANCE) == TIM2) || \
4639  ((INSTANCE) == TIM3) || \
4640  ((INSTANCE) == TIM4) || \
4641  ((INSTANCE) == TIM5))
4642 
4643 /************ TIM Instances : DMA requests generation (COMDE) *****************/
4644 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4645  ((INSTANCE) == TIM2) || \
4646  ((INSTANCE) == TIM3) || \
4647  ((INSTANCE) == TIM4) || \
4648  ((INSTANCE) == TIM5))
4649 
4650 /******************** TIM Instances : DMA burst feature ***********************/
4651 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4652  ((INSTANCE) == TIM2) || \
4653  ((INSTANCE) == TIM3) || \
4654  ((INSTANCE) == TIM4) || \
4655  ((INSTANCE) == TIM5))
4656 
4657 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
4658 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4659  ((INSTANCE) == TIM2) || \
4660  ((INSTANCE) == TIM3) || \
4661  ((INSTANCE) == TIM4) || \
4662  ((INSTANCE) == TIM5) || \
4663  ((INSTANCE) == TIM9))
4664 
4665 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
4666 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4667  ((INSTANCE) == TIM2) || \
4668  ((INSTANCE) == TIM3) || \
4669  ((INSTANCE) == TIM4) || \
4670  ((INSTANCE) == TIM5) || \
4671  ((INSTANCE) == TIM9))
4672 
4673 /********************** TIM Instances : 32 bit Counter ************************/
4674 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
4675  ((INSTANCE) == TIM5))
4676 
4677 /***************** TIM Instances : external trigger input availabe ************/
4678 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4679  ((INSTANCE) == TIM2) || \
4680  ((INSTANCE) == TIM3) || \
4681  ((INSTANCE) == TIM4) || \
4682  ((INSTANCE) == TIM5))
4683 
4684 /****************** TIM Instances : remapping capability **********************/
4685 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4686  ((INSTANCE) == TIM5) || \
4687  ((INSTANCE) == TIM11))
4688 
4689 /******************* TIM Instances : output(s) available **********************/
4690 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
4691  ((((INSTANCE) == TIM1) && \
4692  (((CHANNEL) == TIM_CHANNEL_1) || \
4693  ((CHANNEL) == TIM_CHANNEL_2) || \
4694  ((CHANNEL) == TIM_CHANNEL_3) || \
4695  ((CHANNEL) == TIM_CHANNEL_4))) \
4696  || \
4697  (((INSTANCE) == TIM2) && \
4698  (((CHANNEL) == TIM_CHANNEL_1) || \
4699  ((CHANNEL) == TIM_CHANNEL_2) || \
4700  ((CHANNEL) == TIM_CHANNEL_3) || \
4701  ((CHANNEL) == TIM_CHANNEL_4))) \
4702  || \
4703  (((INSTANCE) == TIM3) && \
4704  (((CHANNEL) == TIM_CHANNEL_1) || \
4705  ((CHANNEL) == TIM_CHANNEL_2) || \
4706  ((CHANNEL) == TIM_CHANNEL_3) || \
4707  ((CHANNEL) == TIM_CHANNEL_4))) \
4708  || \
4709  (((INSTANCE) == TIM4) && \
4710  (((CHANNEL) == TIM_CHANNEL_1) || \
4711  ((CHANNEL) == TIM_CHANNEL_2) || \
4712  ((CHANNEL) == TIM_CHANNEL_3) || \
4713  ((CHANNEL) == TIM_CHANNEL_4))) \
4714  || \
4715  (((INSTANCE) == TIM5) && \
4716  (((CHANNEL) == TIM_CHANNEL_1) || \
4717  ((CHANNEL) == TIM_CHANNEL_2) || \
4718  ((CHANNEL) == TIM_CHANNEL_3) || \
4719  ((CHANNEL) == TIM_CHANNEL_4))) \
4720  || \
4721  (((INSTANCE) == TIM9) && \
4722  (((CHANNEL) == TIM_CHANNEL_1) || \
4723  ((CHANNEL) == TIM_CHANNEL_2))) \
4724  || \
4725  (((INSTANCE) == TIM10) && \
4726  (((CHANNEL) == TIM_CHANNEL_1))) \
4727  || \
4728  (((INSTANCE) == TIM11) && \
4729  (((CHANNEL) == TIM_CHANNEL_1))))
4730 
4731 /************ TIM Instances : complementary output(s) available ***************/
4732 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
4733  ((((INSTANCE) == TIM1) && \
4734  (((CHANNEL) == TIM_CHANNEL_1) || \
4735  ((CHANNEL) == TIM_CHANNEL_2) || \
4736  ((CHANNEL) == TIM_CHANNEL_3))))
4737 
4738 /******************** USART Instances : Synchronous mode **********************/
4739 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4740  ((INSTANCE) == USART2) || \
4741  ((INSTANCE) == USART6))
4742 
4743 /******************** UART Instances : Asynchronous mode **********************/
4744 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4745  ((INSTANCE) == USART2) || \
4746  ((INSTANCE) == USART6))
4747 
4748 /****************** UART Instances : Hardware Flow control ********************/
4749 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4750  ((INSTANCE) == USART2) || \
4751  ((INSTANCE) == USART6))
4752 
4753 /********************* UART Instances : Smard card mode ***********************/
4754 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4755  ((INSTANCE) == USART2) || \
4756  ((INSTANCE) == USART6))
4757 
4758 /*********************** UART Instances : IRDA mode ***************************/
4759 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4760  ((INSTANCE) == USART2) || \
4761  ((INSTANCE) == USART6))
4762 
4763 
4764 /*********************** PCD Instances ****************************************/
4765 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
4766 
4767 /*********************** HCD Instances ****************************************/
4768 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
4769 
4770 /****************************** IWDG Instances ********************************/
4771 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
4772 
4773 /****************************** WWDG Instances ********************************/
4774 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
4775 
4776 /****************************** SDIO Instances ********************************/
4777 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
4778 
4779 /****************************** USB Exported Constants ************************/
4780 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
4781 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
4782 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
4783 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
4784 
4797 #ifdef __cplusplus
4798 }
4799 #endif /* __cplusplus */
4800 
4801 #endif /* __STM32F401xE_H */
4802 
4803 
4804 
4805 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
TAMP_STAMP_IRQn
Definition: stm32f401xe.h:99
TIM2_IRQn
Definition: stm32f401xe.h:121
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f401xe.h:119
EXTI2_IRQn
Definition: stm32f401xe.h:105
EXTI4_IRQn
Definition: stm32f401xe.h:107
USART1_IRQn
Definition: stm32f401xe.h:130
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
TIM4_IRQn
Definition: stm32f401xe.h:123
RTC_Alarm_IRQn
Definition: stm32f401xe.h:133
PendSV_IRQn
Definition: stm32f401xe.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f401xe.h:100
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f401xe.h:128
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
OTG_FS_WKUP_IRQn
Definition: stm32f401xe.h:134
DMA_TypeDef
Definition: stm32f401xc.h:243
DMA1_Stream2_IRQn
Definition: stm32f401xe.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f401xe.h:129
__I
#define __I
Definition: core_cm0.h:210
DMA2_Stream5_IRQn
Definition: stm32f401xe.h:145
ADC_IRQn
Definition: stm32f401xe.h:115
RCC_IRQn
Definition: stm32f401xe.h:102
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f401xe.h:93
DMA2_Stream3_IRQn
Definition: stm32f401xe.h:142
NonMaskableInt_IRQn
Definition: stm32f401xe.h:88
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f401xe.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
DMA1_Stream1_IRQn
Definition: stm32f401xe.h:109
DMA2_Stream7_IRQn
Definition: stm32f401xe.h:147
DMA2_Stream6_IRQn
Definition: stm32f401xe.h:146
BusFault_IRQn
Definition: stm32f401xe.h:90
I2C3_ER_IRQn
Definition: stm32f401xe.h:150
USART6_IRQn
Definition: stm32f401xe.h:148
PVD_IRQn
Definition: stm32f401xe.h:98
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f401xe.h:112
DMA1_Stream0_IRQn
Definition: stm32f401xe.h:108
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f401xe.h:152
DMA1_Stream3_IRQn
Definition: stm32f401xe.h:111
FPU_IRQn
Definition: stm32f401xe.h:151
OTG_FS_IRQn
Definition: stm32f401xe.h:144
DMA2_Stream2_IRQn
Definition: stm32f401xe.h:141
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f401xe.h:136
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f401xe.h:149
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f401xe.h:131
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
I2C2_EV_IRQn
Definition: stm32f401xe.h:126
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f401xe.h:122
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f401xe.h:104
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f401xe.h:92
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f401xe.h:120
FLASH_IRQn
Definition: stm32f401xe.h:101
DMA1_Stream5_IRQn
Definition: stm32f401xe.h:113
SysTick_IRQn
Definition: stm32f401xe.h:95
TIM1_UP_TIM10_IRQn
Definition: stm32f401xe.h:118
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f401xe.h:127
UsageFault_IRQn
Definition: stm32f401xe.h:91
SPI3_IRQn
Definition: stm32f401xe.h:138
DMA2_Stream1_IRQn
Definition: stm32f401xe.h:140
EXTI9_5_IRQn
Definition: stm32f401xe.h:116
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f401xe.h:124
DMA1_Stream6_IRQn
Definition: stm32f401xe.h:114
I2C1_ER_IRQn
Definition: stm32f401xe.h:125
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
DMA2_Stream4_IRQn
Definition: stm32f401xe.h:143
WWDG_IRQn
Definition: stm32f401xe.h:97
DMA1_Stream7_IRQn
Definition: stm32f401xe.h:135
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
EXTI15_10_IRQn
Definition: stm32f401xe.h:132
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f401xe.h:103
DMA2_Stream0_IRQn
Definition: stm32f401xe.h:139
TIM1_BRK_TIM9_IRQn
Definition: stm32f401xe.h:117
TIM5_IRQn
Definition: stm32f401xe.h:137
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f401xe.h:106
MemoryManagement_IRQn
Definition: stm32f401xe.h:89