STM CMSIS
stm32f405xx.h
Go to the documentation of this file.
1 
52 #ifndef __STM32F405xx_H
53 #define __STM32F405xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  CAN1_TX_IRQn = 19,
117  CAN1_RX0_IRQn = 20,
118  CAN1_RX1_IRQn = 21,
119  CAN1_SCE_IRQn = 22,
120  EXTI9_5_IRQn = 23,
121  TIM1_BRK_TIM9_IRQn = 24,
122  TIM1_UP_TIM10_IRQn = 25,
123  TIM1_TRG_COM_TIM11_IRQn = 26,
124  TIM1_CC_IRQn = 27,
125  TIM2_IRQn = 28,
126  TIM3_IRQn = 29,
127  TIM4_IRQn = 30,
128  I2C1_EV_IRQn = 31,
129  I2C1_ER_IRQn = 32,
130  I2C2_EV_IRQn = 33,
131  I2C2_ER_IRQn = 34,
132  SPI1_IRQn = 35,
133  SPI2_IRQn = 36,
134  USART1_IRQn = 37,
135  USART2_IRQn = 38,
136  USART3_IRQn = 39,
137  EXTI15_10_IRQn = 40,
138  RTC_Alarm_IRQn = 41,
139  OTG_FS_WKUP_IRQn = 42,
140  TIM8_BRK_TIM12_IRQn = 43,
141  TIM8_UP_TIM13_IRQn = 44,
142  TIM8_TRG_COM_TIM14_IRQn = 45,
143  TIM8_CC_IRQn = 46,
144  DMA1_Stream7_IRQn = 47,
145  FSMC_IRQn = 48,
146  SDIO_IRQn = 49,
147  TIM5_IRQn = 50,
148  SPI3_IRQn = 51,
149  UART4_IRQn = 52,
150  UART5_IRQn = 53,
151  TIM6_DAC_IRQn = 54,
152  TIM7_IRQn = 55,
153  DMA2_Stream0_IRQn = 56,
154  DMA2_Stream1_IRQn = 57,
155  DMA2_Stream2_IRQn = 58,
156  DMA2_Stream3_IRQn = 59,
157  DMA2_Stream4_IRQn = 60,
158  CAN2_TX_IRQn = 63,
159  CAN2_RX0_IRQn = 64,
160  CAN2_RX1_IRQn = 65,
161  CAN2_SCE_IRQn = 66,
162  OTG_FS_IRQn = 67,
163  DMA2_Stream5_IRQn = 68,
164  DMA2_Stream6_IRQn = 69,
165  DMA2_Stream7_IRQn = 70,
166  USART6_IRQn = 71,
167  I2C3_EV_IRQn = 72,
168  I2C3_ER_IRQn = 73,
169  OTG_HS_EP1_OUT_IRQn = 74,
170  OTG_HS_EP1_IN_IRQn = 75,
171  OTG_HS_WKUP_IRQn = 76,
172  OTG_HS_IRQn = 77,
173  HASH_RNG_IRQn = 80,
174  FPU_IRQn = 81
175 } IRQn_Type;
176 
181 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
182 #include "system_stm32f4xx.h"
183 #include <stdint.h>
184 
193 typedef struct
194 {
195  __IO uint32_t SR;
196  __IO uint32_t CR1;
197  __IO uint32_t CR2;
198  __IO uint32_t SMPR1;
199  __IO uint32_t SMPR2;
200  __IO uint32_t JOFR1;
201  __IO uint32_t JOFR2;
202  __IO uint32_t JOFR3;
203  __IO uint32_t JOFR4;
204  __IO uint32_t HTR;
205  __IO uint32_t LTR;
206  __IO uint32_t SQR1;
207  __IO uint32_t SQR2;
208  __IO uint32_t SQR3;
209  __IO uint32_t JSQR;
210  __IO uint32_t JDR1;
211  __IO uint32_t JDR2;
212  __IO uint32_t JDR3;
213  __IO uint32_t JDR4;
214  __IO uint32_t DR;
215 } ADC_TypeDef;
216 
217 typedef struct
218 {
219  __IO uint32_t CSR;
220  __IO uint32_t CCR;
221  __IO uint32_t CDR;
223 } ADC_Common_TypeDef;
224 
225 
230 typedef struct
231 {
232  __IO uint32_t TIR;
233  __IO uint32_t TDTR;
234  __IO uint32_t TDLR;
235  __IO uint32_t TDHR;
236 } CAN_TxMailBox_TypeDef;
237 
242 typedef struct
243 {
244  __IO uint32_t RIR;
245  __IO uint32_t RDTR;
246  __IO uint32_t RDLR;
247  __IO uint32_t RDHR;
248 } CAN_FIFOMailBox_TypeDef;
249 
254 typedef struct
255 {
256  __IO uint32_t FR1;
257  __IO uint32_t FR2;
258 } CAN_FilterRegister_TypeDef;
259 
264 typedef struct
265 {
266  __IO uint32_t MCR;
267  __IO uint32_t MSR;
268  __IO uint32_t TSR;
269  __IO uint32_t RF0R;
270  __IO uint32_t RF1R;
271  __IO uint32_t IER;
272  __IO uint32_t ESR;
273  __IO uint32_t BTR;
274  uint32_t RESERVED0[88];
275  CAN_TxMailBox_TypeDef sTxMailBox[3];
276  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
277  uint32_t RESERVED1[12];
278  __IO uint32_t FMR;
279  __IO uint32_t FM1R;
280  uint32_t RESERVED2;
281  __IO uint32_t FS1R;
282  uint32_t RESERVED3;
283  __IO uint32_t FFA1R;
284  uint32_t RESERVED4;
285  __IO uint32_t FA1R;
286  uint32_t RESERVED5[8];
287  CAN_FilterRegister_TypeDef sFilterRegister[28];
288 } CAN_TypeDef;
289 
294 typedef struct
295 {
296  __IO uint32_t DR;
297  __IO uint8_t IDR;
298  uint8_t RESERVED0;
299  uint16_t RESERVED1;
300  __IO uint32_t CR;
301 } CRC_TypeDef;
302 
307 typedef struct
308 {
309  __IO uint32_t CR;
310  __IO uint32_t SWTRIGR;
311  __IO uint32_t DHR12R1;
312  __IO uint32_t DHR12L1;
313  __IO uint32_t DHR8R1;
314  __IO uint32_t DHR12R2;
315  __IO uint32_t DHR12L2;
316  __IO uint32_t DHR8R2;
317  __IO uint32_t DHR12RD;
318  __IO uint32_t DHR12LD;
319  __IO uint32_t DHR8RD;
320  __IO uint32_t DOR1;
321  __IO uint32_t DOR2;
322  __IO uint32_t SR;
323 } DAC_TypeDef;
324 
329 typedef struct
330 {
331  __IO uint32_t IDCODE;
332  __IO uint32_t CR;
333  __IO uint32_t APB1FZ;
334  __IO uint32_t APB2FZ;
335 }DBGMCU_TypeDef;
336 
337 
342 typedef struct
343 {
344  __IO uint32_t CR;
345  __IO uint32_t NDTR;
346  __IO uint32_t PAR;
347  __IO uint32_t M0AR;
348  __IO uint32_t M1AR;
349  __IO uint32_t FCR;
350 } DMA_Stream_TypeDef;
351 
352 typedef struct
353 {
354  __IO uint32_t LISR;
355  __IO uint32_t HISR;
356  __IO uint32_t LIFCR;
357  __IO uint32_t HIFCR;
358 } DMA_TypeDef;
359 
360 
365 typedef struct
366 {
367  __IO uint32_t IMR;
368  __IO uint32_t EMR;
369  __IO uint32_t RTSR;
370  __IO uint32_t FTSR;
371  __IO uint32_t SWIER;
372  __IO uint32_t PR;
373 } EXTI_TypeDef;
374 
379 typedef struct
380 {
381  __IO uint32_t ACR;
382  __IO uint32_t KEYR;
383  __IO uint32_t OPTKEYR;
384  __IO uint32_t SR;
385  __IO uint32_t CR;
386  __IO uint32_t OPTCR;
387  __IO uint32_t OPTCR1;
388 } FLASH_TypeDef;
389 
390 
395 typedef struct
396 {
397  __IO uint32_t BTCR[8];
398 } FSMC_Bank1_TypeDef;
399 
404 typedef struct
405 {
406  __IO uint32_t BWTR[7];
407 } FSMC_Bank1E_TypeDef;
408 
413 typedef struct
414 {
415  __IO uint32_t PCR2;
416  __IO uint32_t SR2;
417  __IO uint32_t PMEM2;
418  __IO uint32_t PATT2;
419  uint32_t RESERVED0;
420  __IO uint32_t ECCR2;
421  uint32_t RESERVED1;
422  uint32_t RESERVED2;
423  __IO uint32_t PCR3;
424  __IO uint32_t SR3;
425  __IO uint32_t PMEM3;
426  __IO uint32_t PATT3;
427  uint32_t RESERVED3;
428  __IO uint32_t ECCR3;
429 } FSMC_Bank2_3_TypeDef;
430 
435 typedef struct
436 {
437  __IO uint32_t PCR4;
438  __IO uint32_t SR4;
439  __IO uint32_t PMEM4;
440  __IO uint32_t PATT4;
441  __IO uint32_t PIO4;
442 } FSMC_Bank4_TypeDef;
443 
444 
449 typedef struct
450 {
451  __IO uint32_t MODER;
452  __IO uint32_t OTYPER;
453  __IO uint32_t OSPEEDR;
454  __IO uint32_t PUPDR;
455  __IO uint32_t IDR;
456  __IO uint32_t ODR;
457  __IO uint32_t BSRR;
458  __IO uint32_t LCKR;
459  __IO uint32_t AFR[2];
460 } GPIO_TypeDef;
461 
466 typedef struct
467 {
468  __IO uint32_t MEMRMP;
469  __IO uint32_t PMC;
470  __IO uint32_t EXTICR[4];
471  uint32_t RESERVED[2];
472  __IO uint32_t CMPCR;
473 } SYSCFG_TypeDef;
474 
479 typedef struct
480 {
481  __IO uint32_t CR1;
482  __IO uint32_t CR2;
483  __IO uint32_t OAR1;
484  __IO uint32_t OAR2;
485  __IO uint32_t DR;
486  __IO uint32_t SR1;
487  __IO uint32_t SR2;
488  __IO uint32_t CCR;
489  __IO uint32_t TRISE;
490  __IO uint32_t FLTR;
491 } I2C_TypeDef;
492 
497 typedef struct
498 {
499  __IO uint32_t KR;
500  __IO uint32_t PR;
501  __IO uint32_t RLR;
502  __IO uint32_t SR;
503 } IWDG_TypeDef;
504 
509 typedef struct
510 {
511  __IO uint32_t CR;
512  __IO uint32_t CSR;
513 } PWR_TypeDef;
514 
519 typedef struct
520 {
521  __IO uint32_t CR;
522  __IO uint32_t PLLCFGR;
523  __IO uint32_t CFGR;
524  __IO uint32_t CIR;
525  __IO uint32_t AHB1RSTR;
526  __IO uint32_t AHB2RSTR;
527  __IO uint32_t AHB3RSTR;
528  uint32_t RESERVED0;
529  __IO uint32_t APB1RSTR;
530  __IO uint32_t APB2RSTR;
531  uint32_t RESERVED1[2];
532  __IO uint32_t AHB1ENR;
533  __IO uint32_t AHB2ENR;
534  __IO uint32_t AHB3ENR;
535  uint32_t RESERVED2;
536  __IO uint32_t APB1ENR;
537  __IO uint32_t APB2ENR;
538  uint32_t RESERVED3[2];
539  __IO uint32_t AHB1LPENR;
540  __IO uint32_t AHB2LPENR;
541  __IO uint32_t AHB3LPENR;
542  uint32_t RESERVED4;
543  __IO uint32_t APB1LPENR;
544  __IO uint32_t APB2LPENR;
545  uint32_t RESERVED5[2];
546  __IO uint32_t BDCR;
547  __IO uint32_t CSR;
548  uint32_t RESERVED6[2];
549  __IO uint32_t SSCGR;
550  __IO uint32_t PLLI2SCFGR;
552 } RCC_TypeDef;
553 
558 typedef struct
559 {
560  __IO uint32_t TR;
561  __IO uint32_t DR;
562  __IO uint32_t CR;
563  __IO uint32_t ISR;
564  __IO uint32_t PRER;
565  __IO uint32_t WUTR;
566  __IO uint32_t CALIBR;
567  __IO uint32_t ALRMAR;
568  __IO uint32_t ALRMBR;
569  __IO uint32_t WPR;
570  __IO uint32_t SSR;
571  __IO uint32_t SHIFTR;
572  __IO uint32_t TSTR;
573  __IO uint32_t TSDR;
574  __IO uint32_t TSSSR;
575  __IO uint32_t CALR;
576  __IO uint32_t TAFCR;
577  __IO uint32_t ALRMASSR;
578  __IO uint32_t ALRMBSSR;
579  uint32_t RESERVED7;
580  __IO uint32_t BKP0R;
581  __IO uint32_t BKP1R;
582  __IO uint32_t BKP2R;
583  __IO uint32_t BKP3R;
584  __IO uint32_t BKP4R;
585  __IO uint32_t BKP5R;
586  __IO uint32_t BKP6R;
587  __IO uint32_t BKP7R;
588  __IO uint32_t BKP8R;
589  __IO uint32_t BKP9R;
590  __IO uint32_t BKP10R;
591  __IO uint32_t BKP11R;
592  __IO uint32_t BKP12R;
593  __IO uint32_t BKP13R;
594  __IO uint32_t BKP14R;
595  __IO uint32_t BKP15R;
596  __IO uint32_t BKP16R;
597  __IO uint32_t BKP17R;
598  __IO uint32_t BKP18R;
599  __IO uint32_t BKP19R;
600 } RTC_TypeDef;
601 
602 
607 typedef struct
608 {
609  __IO uint32_t POWER;
610  __IO uint32_t CLKCR;
611  __IO uint32_t ARG;
612  __IO uint32_t CMD;
613  __I uint32_t RESPCMD;
614  __I uint32_t RESP1;
615  __I uint32_t RESP2;
616  __I uint32_t RESP3;
617  __I uint32_t RESP4;
618  __IO uint32_t DTIMER;
619  __IO uint32_t DLEN;
620  __IO uint32_t DCTRL;
621  __I uint32_t DCOUNT;
622  __I uint32_t STA;
623  __IO uint32_t ICR;
624  __IO uint32_t MASK;
625  uint32_t RESERVED0[2];
626  __I uint32_t FIFOCNT;
627  uint32_t RESERVED1[13];
628  __IO uint32_t FIFO;
629 } SDIO_TypeDef;
630 
635 typedef struct
636 {
637  __IO uint32_t CR1;
638  __IO uint32_t CR2;
639  __IO uint32_t SR;
640  __IO uint32_t DR;
641  __IO uint32_t CRCPR;
642  __IO uint32_t RXCRCR;
643  __IO uint32_t TXCRCR;
644  __IO uint32_t I2SCFGR;
645  __IO uint32_t I2SPR;
646 } SPI_TypeDef;
647 
652 typedef struct
653 {
654  __IO uint32_t CR1;
655  __IO uint32_t CR2;
656  __IO uint32_t SMCR;
657  __IO uint32_t DIER;
658  __IO uint32_t SR;
659  __IO uint32_t EGR;
660  __IO uint32_t CCMR1;
661  __IO uint32_t CCMR2;
662  __IO uint32_t CCER;
663  __IO uint32_t CNT;
664  __IO uint32_t PSC;
665  __IO uint32_t ARR;
666  __IO uint32_t RCR;
667  __IO uint32_t CCR1;
668  __IO uint32_t CCR2;
669  __IO uint32_t CCR3;
670  __IO uint32_t CCR4;
671  __IO uint32_t BDTR;
672  __IO uint32_t DCR;
673  __IO uint32_t DMAR;
674  __IO uint32_t OR;
675 } TIM_TypeDef;
676 
681 typedef struct
682 {
683  __IO uint32_t SR;
684  __IO uint32_t DR;
685  __IO uint32_t BRR;
686  __IO uint32_t CR1;
687  __IO uint32_t CR2;
688  __IO uint32_t CR3;
689  __IO uint32_t GTPR;
690 } USART_TypeDef;
691 
696 typedef struct
697 {
698  __IO uint32_t CR;
699  __IO uint32_t CFR;
700  __IO uint32_t SR;
701 } WWDG_TypeDef;
702 
703 
708 typedef struct
709 {
710  __IO uint32_t CR;
711  __IO uint32_t SR;
712  __IO uint32_t DR;
713 } RNG_TypeDef;
714 
715 
716 
720 typedef struct
721 {
722  __IO uint32_t GOTGCTL;
723  __IO uint32_t GOTGINT;
724  __IO uint32_t GAHBCFG;
725  __IO uint32_t GUSBCFG;
726  __IO uint32_t GRSTCTL;
727  __IO uint32_t GINTSTS;
728  __IO uint32_t GINTMSK;
729  __IO uint32_t GRXSTSR;
730  __IO uint32_t GRXSTSP;
731  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
732  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
733  __IO uint32_t HNPTXSTS;
734  uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
735  __IO uint32_t GCCFG;
736  __IO uint32_t CID;
737  uint32_t Reserved40[48];
738  __IO uint32_t HPTXFSIZ;
739  __IO uint32_t DIEPTXF[0x0F];
740 }
741 USB_OTG_GlobalTypeDef;
742 
743 
744 
748 typedef struct
749 {
750  __IO uint32_t DCFG;
751  __IO uint32_t DCTL;
752  __IO uint32_t DSTS;
753  uint32_t Reserved0C;
754  __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
755  __IO uint32_t DOEPMSK;
756  __IO uint32_t DAINT;
757  __IO uint32_t DAINTMSK;
758  uint32_t Reserved20;
759  uint32_t Reserved9;
760  __IO uint32_t DVBUSDIS;
761  __IO uint32_t DVBUSPULSE;
762  __IO uint32_t DTHRCTL;
763  __IO uint32_t DIEPEMPMSK;
764  __IO uint32_t DEACHINT;
765  __IO uint32_t DEACHMSK;
766  uint32_t Reserved40;
767  __IO uint32_t DINEP1MSK;
768  uint32_t Reserved44[15];
769  __IO uint32_t DOUTEP1MSK;
770 }
771 USB_OTG_DeviceTypeDef;
772 
773 
777 typedef struct
778 {
779  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
780  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
781  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
782  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
783  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
784  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
785  __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
786  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
787 }
788 USB_OTG_INEndpointTypeDef;
789 
790 
794 typedef struct
795 {
796  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
797  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
798  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
799  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
800  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
801  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
802  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
803 }
804 USB_OTG_OUTEndpointTypeDef;
805 
806 
810 typedef struct
811 {
812  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
813  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
814  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
815  uint32_t Reserved40C; /* Reserved 40Ch*/
816  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
817  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
818  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
819 }
820 USB_OTG_HostTypeDef;
821 
822 
826 typedef struct
827 {
828  __IO uint32_t HCCHAR;
829  __IO uint32_t HCSPLT;
830  __IO uint32_t HCINT;
831  __IO uint32_t HCINTMSK;
832  __IO uint32_t HCTSIZ;
833  __IO uint32_t HCDMA;
834  uint32_t Reserved[2];
835 }
836 USB_OTG_HostChannelTypeDef;
837 
838 
842 #define FLASH_BASE 0x08000000U
843 #define CCMDATARAM_BASE 0x10000000U
844 #define SRAM1_BASE 0x20000000U
845 #define SRAM2_BASE 0x2001C000U
846 #define PERIPH_BASE 0x40000000U
847 #define BKPSRAM_BASE 0x40024000U
848 #define FSMC_R_BASE 0xA0000000U
849 #define SRAM1_BB_BASE 0x22000000U
850 #define SRAM2_BB_BASE 0x22380000U
851 #define PERIPH_BB_BASE 0x42000000U
852 #define BKPSRAM_BB_BASE 0x42480000U
853 #define FLASH_END 0x080FFFFFU
854 #define CCMDATARAM_END 0x1000FFFFU
856 /* Legacy defines */
857 #define SRAM_BASE SRAM1_BASE
858 #define SRAM_BB_BASE SRAM1_BB_BASE
859 
860 
862 #define APB1PERIPH_BASE PERIPH_BASE
863 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
864 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
865 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
866 
868 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
869 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
870 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
871 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
872 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
873 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
874 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
875 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
876 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
877 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
878 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
879 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
880 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
881 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
882 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
883 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
884 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
885 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
886 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
887 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
888 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
889 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
890 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
891 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
892 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
893 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
894 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
895 
897 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
898 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
899 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
900 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
901 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
902 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
903 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
904 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
905 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
906 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
907 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
908 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
909 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
910 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
911 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
912 
914 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
915 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
916 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
917 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
918 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
919 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
920 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
921 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
922 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
923 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
924 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
925 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
926 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
927 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
928 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
929 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
930 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
931 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
932 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
933 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
934 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
935 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
936 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
937 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
938 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
939 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
940 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
941 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
942 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
943 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
944 
946 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
947 
949 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
950 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
951 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
952 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
953 
954 /* Debug MCU registers base address */
955 #define DBGMCU_BASE 0xE0042000U
956 
958 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
959 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
960 
961 #define USB_OTG_GLOBAL_BASE 0x000U
962 #define USB_OTG_DEVICE_BASE 0x800U
963 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
964 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
965 #define USB_OTG_EP_REG_SIZE 0x20U
966 #define USB_OTG_HOST_BASE 0x400U
967 #define USB_OTG_HOST_PORT_BASE 0x440U
968 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
969 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
970 #define USB_OTG_PCGCCTL_BASE 0xE00U
971 #define USB_OTG_FIFO_BASE 0x1000U
972 #define USB_OTG_FIFO_SIZE 0x1000U
973 
981 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
982 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
983 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
984 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
985 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
986 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
987 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
988 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
989 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
990 #define RTC ((RTC_TypeDef *) RTC_BASE)
991 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
992 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
993 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
994 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
995 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
996 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
997 #define USART2 ((USART_TypeDef *) USART2_BASE)
998 #define USART3 ((USART_TypeDef *) USART3_BASE)
999 #define UART4 ((USART_TypeDef *) UART4_BASE)
1000 #define UART5 ((USART_TypeDef *) UART5_BASE)
1001 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1002 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1003 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1004 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1005 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1006 #define PWR ((PWR_TypeDef *) PWR_BASE)
1007 #define DAC ((DAC_TypeDef *) DAC_BASE)
1008 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1009 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1010 #define USART1 ((USART_TypeDef *) USART1_BASE)
1011 #define USART6 ((USART_TypeDef *) USART6_BASE)
1012 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1013 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1014 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1015 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1016 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1017 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1018 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1019 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1020 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1021 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1022 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1023 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1024 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1025 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1026 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1027 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1028 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1029 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1030 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1031 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1032 #define CRC ((CRC_TypeDef *) CRC_BASE)
1033 #define RCC ((RCC_TypeDef *) RCC_BASE)
1034 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1035 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1036 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1037 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1038 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1039 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1040 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1041 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1042 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1043 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1044 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1045 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1046 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1047 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1048 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1049 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1050 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1051 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1052 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1053 #define RNG ((RNG_TypeDef *) RNG_BASE)
1054 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1055 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1056 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1057 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1058 
1059 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1060 
1061 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1062 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1063 
1076 /******************************************************************************/
1077 /* Peripheral Registers_Bits_Definition */
1078 /******************************************************************************/
1079 
1080 /******************************************************************************/
1081 /* */
1082 /* Analog to Digital Converter */
1083 /* */
1084 /******************************************************************************/
1085 /******************** Bit definition for ADC_SR register ********************/
1086 #define ADC_SR_AWD 0x00000001U
1087 #define ADC_SR_EOC 0x00000002U
1088 #define ADC_SR_JEOC 0x00000004U
1089 #define ADC_SR_JSTRT 0x00000008U
1090 #define ADC_SR_STRT 0x00000010U
1091 #define ADC_SR_OVR 0x00000020U
1093 /******************* Bit definition for ADC_CR1 register ********************/
1094 #define ADC_CR1_AWDCH 0x0000001FU
1095 #define ADC_CR1_AWDCH_0 0x00000001U
1096 #define ADC_CR1_AWDCH_1 0x00000002U
1097 #define ADC_CR1_AWDCH_2 0x00000004U
1098 #define ADC_CR1_AWDCH_3 0x00000008U
1099 #define ADC_CR1_AWDCH_4 0x00000010U
1100 #define ADC_CR1_EOCIE 0x00000020U
1101 #define ADC_CR1_AWDIE 0x00000040U
1102 #define ADC_CR1_JEOCIE 0x00000080U
1103 #define ADC_CR1_SCAN 0x00000100U
1104 #define ADC_CR1_AWDSGL 0x00000200U
1105 #define ADC_CR1_JAUTO 0x00000400U
1106 #define ADC_CR1_DISCEN 0x00000800U
1107 #define ADC_CR1_JDISCEN 0x00001000U
1108 #define ADC_CR1_DISCNUM 0x0000E000U
1109 #define ADC_CR1_DISCNUM_0 0x00002000U
1110 #define ADC_CR1_DISCNUM_1 0x00004000U
1111 #define ADC_CR1_DISCNUM_2 0x00008000U
1112 #define ADC_CR1_JAWDEN 0x00400000U
1113 #define ADC_CR1_AWDEN 0x00800000U
1114 #define ADC_CR1_RES 0x03000000U
1115 #define ADC_CR1_RES_0 0x01000000U
1116 #define ADC_CR1_RES_1 0x02000000U
1117 #define ADC_CR1_OVRIE 0x04000000U
1119 /******************* Bit definition for ADC_CR2 register ********************/
1120 #define ADC_CR2_ADON 0x00000001U
1121 #define ADC_CR2_CONT 0x00000002U
1122 #define ADC_CR2_DMA 0x00000100U
1123 #define ADC_CR2_DDS 0x00000200U
1124 #define ADC_CR2_EOCS 0x00000400U
1125 #define ADC_CR2_ALIGN 0x00000800U
1126 #define ADC_CR2_JEXTSEL 0x000F0000U
1127 #define ADC_CR2_JEXTSEL_0 0x00010000U
1128 #define ADC_CR2_JEXTSEL_1 0x00020000U
1129 #define ADC_CR2_JEXTSEL_2 0x00040000U
1130 #define ADC_CR2_JEXTSEL_3 0x00080000U
1131 #define ADC_CR2_JEXTEN 0x00300000U
1132 #define ADC_CR2_JEXTEN_0 0x00100000U
1133 #define ADC_CR2_JEXTEN_1 0x00200000U
1134 #define ADC_CR2_JSWSTART 0x00400000U
1135 #define ADC_CR2_EXTSEL 0x0F000000U
1136 #define ADC_CR2_EXTSEL_0 0x01000000U
1137 #define ADC_CR2_EXTSEL_1 0x02000000U
1138 #define ADC_CR2_EXTSEL_2 0x04000000U
1139 #define ADC_CR2_EXTSEL_3 0x08000000U
1140 #define ADC_CR2_EXTEN 0x30000000U
1141 #define ADC_CR2_EXTEN_0 0x10000000U
1142 #define ADC_CR2_EXTEN_1 0x20000000U
1143 #define ADC_CR2_SWSTART 0x40000000U
1145 /****************** Bit definition for ADC_SMPR1 register *******************/
1146 #define ADC_SMPR1_SMP10 0x00000007U
1147 #define ADC_SMPR1_SMP10_0 0x00000001U
1148 #define ADC_SMPR1_SMP10_1 0x00000002U
1149 #define ADC_SMPR1_SMP10_2 0x00000004U
1150 #define ADC_SMPR1_SMP11 0x00000038U
1151 #define ADC_SMPR1_SMP11_0 0x00000008U
1152 #define ADC_SMPR1_SMP11_1 0x00000010U
1153 #define ADC_SMPR1_SMP11_2 0x00000020U
1154 #define ADC_SMPR1_SMP12 0x000001C0U
1155 #define ADC_SMPR1_SMP12_0 0x00000040U
1156 #define ADC_SMPR1_SMP12_1 0x00000080U
1157 #define ADC_SMPR1_SMP12_2 0x00000100U
1158 #define ADC_SMPR1_SMP13 0x00000E00U
1159 #define ADC_SMPR1_SMP13_0 0x00000200U
1160 #define ADC_SMPR1_SMP13_1 0x00000400U
1161 #define ADC_SMPR1_SMP13_2 0x00000800U
1162 #define ADC_SMPR1_SMP14 0x00007000U
1163 #define ADC_SMPR1_SMP14_0 0x00001000U
1164 #define ADC_SMPR1_SMP14_1 0x00002000U
1165 #define ADC_SMPR1_SMP14_2 0x00004000U
1166 #define ADC_SMPR1_SMP15 0x00038000U
1167 #define ADC_SMPR1_SMP15_0 0x00008000U
1168 #define ADC_SMPR1_SMP15_1 0x00010000U
1169 #define ADC_SMPR1_SMP15_2 0x00020000U
1170 #define ADC_SMPR1_SMP16 0x001C0000U
1171 #define ADC_SMPR1_SMP16_0 0x00040000U
1172 #define ADC_SMPR1_SMP16_1 0x00080000U
1173 #define ADC_SMPR1_SMP16_2 0x00100000U
1174 #define ADC_SMPR1_SMP17 0x00E00000U
1175 #define ADC_SMPR1_SMP17_0 0x00200000U
1176 #define ADC_SMPR1_SMP17_1 0x00400000U
1177 #define ADC_SMPR1_SMP17_2 0x00800000U
1178 #define ADC_SMPR1_SMP18 0x07000000U
1179 #define ADC_SMPR1_SMP18_0 0x01000000U
1180 #define ADC_SMPR1_SMP18_1 0x02000000U
1181 #define ADC_SMPR1_SMP18_2 0x04000000U
1183 /****************** Bit definition for ADC_SMPR2 register *******************/
1184 #define ADC_SMPR2_SMP0 0x00000007U
1185 #define ADC_SMPR2_SMP0_0 0x00000001U
1186 #define ADC_SMPR2_SMP0_1 0x00000002U
1187 #define ADC_SMPR2_SMP0_2 0x00000004U
1188 #define ADC_SMPR2_SMP1 0x00000038U
1189 #define ADC_SMPR2_SMP1_0 0x00000008U
1190 #define ADC_SMPR2_SMP1_1 0x00000010U
1191 #define ADC_SMPR2_SMP1_2 0x00000020U
1192 #define ADC_SMPR2_SMP2 0x000001C0U
1193 #define ADC_SMPR2_SMP2_0 0x00000040U
1194 #define ADC_SMPR2_SMP2_1 0x00000080U
1195 #define ADC_SMPR2_SMP2_2 0x00000100U
1196 #define ADC_SMPR2_SMP3 0x00000E00U
1197 #define ADC_SMPR2_SMP3_0 0x00000200U
1198 #define ADC_SMPR2_SMP3_1 0x00000400U
1199 #define ADC_SMPR2_SMP3_2 0x00000800U
1200 #define ADC_SMPR2_SMP4 0x00007000U
1201 #define ADC_SMPR2_SMP4_0 0x00001000U
1202 #define ADC_SMPR2_SMP4_1 0x00002000U
1203 #define ADC_SMPR2_SMP4_2 0x00004000U
1204 #define ADC_SMPR2_SMP5 0x00038000U
1205 #define ADC_SMPR2_SMP5_0 0x00008000U
1206 #define ADC_SMPR2_SMP5_1 0x00010000U
1207 #define ADC_SMPR2_SMP5_2 0x00020000U
1208 #define ADC_SMPR2_SMP6 0x001C0000U
1209 #define ADC_SMPR2_SMP6_0 0x00040000U
1210 #define ADC_SMPR2_SMP6_1 0x00080000U
1211 #define ADC_SMPR2_SMP6_2 0x00100000U
1212 #define ADC_SMPR2_SMP7 0x00E00000U
1213 #define ADC_SMPR2_SMP7_0 0x00200000U
1214 #define ADC_SMPR2_SMP7_1 0x00400000U
1215 #define ADC_SMPR2_SMP7_2 0x00800000U
1216 #define ADC_SMPR2_SMP8 0x07000000U
1217 #define ADC_SMPR2_SMP8_0 0x01000000U
1218 #define ADC_SMPR2_SMP8_1 0x02000000U
1219 #define ADC_SMPR2_SMP8_2 0x04000000U
1220 #define ADC_SMPR2_SMP9 0x38000000U
1221 #define ADC_SMPR2_SMP9_0 0x08000000U
1222 #define ADC_SMPR2_SMP9_1 0x10000000U
1223 #define ADC_SMPR2_SMP9_2 0x20000000U
1225 /****************** Bit definition for ADC_JOFR1 register *******************/
1226 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1228 /****************** Bit definition for ADC_JOFR2 register *******************/
1229 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1231 /****************** Bit definition for ADC_JOFR3 register *******************/
1232 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1234 /****************** Bit definition for ADC_JOFR4 register *******************/
1235 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1237 /******************* Bit definition for ADC_HTR register ********************/
1238 #define ADC_HTR_HT 0x0FFFU
1240 /******************* Bit definition for ADC_LTR register ********************/
1241 #define ADC_LTR_LT 0x0FFFU
1243 /******************* Bit definition for ADC_SQR1 register *******************/
1244 #define ADC_SQR1_SQ13 0x0000001FU
1245 #define ADC_SQR1_SQ13_0 0x00000001U
1246 #define ADC_SQR1_SQ13_1 0x00000002U
1247 #define ADC_SQR1_SQ13_2 0x00000004U
1248 #define ADC_SQR1_SQ13_3 0x00000008U
1249 #define ADC_SQR1_SQ13_4 0x00000010U
1250 #define ADC_SQR1_SQ14 0x000003E0U
1251 #define ADC_SQR1_SQ14_0 0x00000020U
1252 #define ADC_SQR1_SQ14_1 0x00000040U
1253 #define ADC_SQR1_SQ14_2 0x00000080U
1254 #define ADC_SQR1_SQ14_3 0x00000100U
1255 #define ADC_SQR1_SQ14_4 0x00000200U
1256 #define ADC_SQR1_SQ15 0x00007C00U
1257 #define ADC_SQR1_SQ15_0 0x00000400U
1258 #define ADC_SQR1_SQ15_1 0x00000800U
1259 #define ADC_SQR1_SQ15_2 0x00001000U
1260 #define ADC_SQR1_SQ15_3 0x00002000U
1261 #define ADC_SQR1_SQ15_4 0x00004000U
1262 #define ADC_SQR1_SQ16 0x000F8000U
1263 #define ADC_SQR1_SQ16_0 0x00008000U
1264 #define ADC_SQR1_SQ16_1 0x00010000U
1265 #define ADC_SQR1_SQ16_2 0x00020000U
1266 #define ADC_SQR1_SQ16_3 0x00040000U
1267 #define ADC_SQR1_SQ16_4 0x00080000U
1268 #define ADC_SQR1_L 0x00F00000U
1269 #define ADC_SQR1_L_0 0x00100000U
1270 #define ADC_SQR1_L_1 0x00200000U
1271 #define ADC_SQR1_L_2 0x00400000U
1272 #define ADC_SQR1_L_3 0x00800000U
1274 /******************* Bit definition for ADC_SQR2 register *******************/
1275 #define ADC_SQR2_SQ7 0x0000001FU
1276 #define ADC_SQR2_SQ7_0 0x00000001U
1277 #define ADC_SQR2_SQ7_1 0x00000002U
1278 #define ADC_SQR2_SQ7_2 0x00000004U
1279 #define ADC_SQR2_SQ7_3 0x00000008U
1280 #define ADC_SQR2_SQ7_4 0x00000010U
1281 #define ADC_SQR2_SQ8 0x000003E0U
1282 #define ADC_SQR2_SQ8_0 0x00000020U
1283 #define ADC_SQR2_SQ8_1 0x00000040U
1284 #define ADC_SQR2_SQ8_2 0x00000080U
1285 #define ADC_SQR2_SQ8_3 0x00000100U
1286 #define ADC_SQR2_SQ8_4 0x00000200U
1287 #define ADC_SQR2_SQ9 0x00007C00U
1288 #define ADC_SQR2_SQ9_0 0x00000400U
1289 #define ADC_SQR2_SQ9_1 0x00000800U
1290 #define ADC_SQR2_SQ9_2 0x00001000U
1291 #define ADC_SQR2_SQ9_3 0x00002000U
1292 #define ADC_SQR2_SQ9_4 0x00004000U
1293 #define ADC_SQR2_SQ10 0x000F8000U
1294 #define ADC_SQR2_SQ10_0 0x00008000U
1295 #define ADC_SQR2_SQ10_1 0x00010000U
1296 #define ADC_SQR2_SQ10_2 0x00020000U
1297 #define ADC_SQR2_SQ10_3 0x00040000U
1298 #define ADC_SQR2_SQ10_4 0x00080000U
1299 #define ADC_SQR2_SQ11 0x01F00000U
1300 #define ADC_SQR2_SQ11_0 0x00100000U
1301 #define ADC_SQR2_SQ11_1 0x00200000U
1302 #define ADC_SQR2_SQ11_2 0x00400000U
1303 #define ADC_SQR2_SQ11_3 0x00800000U
1304 #define ADC_SQR2_SQ11_4 0x01000000U
1305 #define ADC_SQR2_SQ12 0x3E000000U
1306 #define ADC_SQR2_SQ12_0 0x02000000U
1307 #define ADC_SQR2_SQ12_1 0x04000000U
1308 #define ADC_SQR2_SQ12_2 0x08000000U
1309 #define ADC_SQR2_SQ12_3 0x10000000U
1310 #define ADC_SQR2_SQ12_4 0x20000000U
1312 /******************* Bit definition for ADC_SQR3 register *******************/
1313 #define ADC_SQR3_SQ1 0x0000001FU
1314 #define ADC_SQR3_SQ1_0 0x00000001U
1315 #define ADC_SQR3_SQ1_1 0x00000002U
1316 #define ADC_SQR3_SQ1_2 0x00000004U
1317 #define ADC_SQR3_SQ1_3 0x00000008U
1318 #define ADC_SQR3_SQ1_4 0x00000010U
1319 #define ADC_SQR3_SQ2 0x000003E0U
1320 #define ADC_SQR3_SQ2_0 0x00000020U
1321 #define ADC_SQR3_SQ2_1 0x00000040U
1322 #define ADC_SQR3_SQ2_2 0x00000080U
1323 #define ADC_SQR3_SQ2_3 0x00000100U
1324 #define ADC_SQR3_SQ2_4 0x00000200U
1325 #define ADC_SQR3_SQ3 0x00007C00U
1326 #define ADC_SQR3_SQ3_0 0x00000400U
1327 #define ADC_SQR3_SQ3_1 0x00000800U
1328 #define ADC_SQR3_SQ3_2 0x00001000U
1329 #define ADC_SQR3_SQ3_3 0x00002000U
1330 #define ADC_SQR3_SQ3_4 0x00004000U
1331 #define ADC_SQR3_SQ4 0x000F8000U
1332 #define ADC_SQR3_SQ4_0 0x00008000U
1333 #define ADC_SQR3_SQ4_1 0x00010000U
1334 #define ADC_SQR3_SQ4_2 0x00020000U
1335 #define ADC_SQR3_SQ4_3 0x00040000U
1336 #define ADC_SQR3_SQ4_4 0x00080000U
1337 #define ADC_SQR3_SQ5 0x01F00000U
1338 #define ADC_SQR3_SQ5_0 0x00100000U
1339 #define ADC_SQR3_SQ5_1 0x00200000U
1340 #define ADC_SQR3_SQ5_2 0x00400000U
1341 #define ADC_SQR3_SQ5_3 0x00800000U
1342 #define ADC_SQR3_SQ5_4 0x01000000U
1343 #define ADC_SQR3_SQ6 0x3E000000U
1344 #define ADC_SQR3_SQ6_0 0x02000000U
1345 #define ADC_SQR3_SQ6_1 0x04000000U
1346 #define ADC_SQR3_SQ6_2 0x08000000U
1347 #define ADC_SQR3_SQ6_3 0x10000000U
1348 #define ADC_SQR3_SQ6_4 0x20000000U
1350 /******************* Bit definition for ADC_JSQR register *******************/
1351 #define ADC_JSQR_JSQ1 0x0000001FU
1352 #define ADC_JSQR_JSQ1_0 0x00000001U
1353 #define ADC_JSQR_JSQ1_1 0x00000002U
1354 #define ADC_JSQR_JSQ1_2 0x00000004U
1355 #define ADC_JSQR_JSQ1_3 0x00000008U
1356 #define ADC_JSQR_JSQ1_4 0x00000010U
1357 #define ADC_JSQR_JSQ2 0x000003E0U
1358 #define ADC_JSQR_JSQ2_0 0x00000020U
1359 #define ADC_JSQR_JSQ2_1 0x00000040U
1360 #define ADC_JSQR_JSQ2_2 0x00000080U
1361 #define ADC_JSQR_JSQ2_3 0x00000100U
1362 #define ADC_JSQR_JSQ2_4 0x00000200U
1363 #define ADC_JSQR_JSQ3 0x00007C00U
1364 #define ADC_JSQR_JSQ3_0 0x00000400U
1365 #define ADC_JSQR_JSQ3_1 0x00000800U
1366 #define ADC_JSQR_JSQ3_2 0x00001000U
1367 #define ADC_JSQR_JSQ3_3 0x00002000U
1368 #define ADC_JSQR_JSQ3_4 0x00004000U
1369 #define ADC_JSQR_JSQ4 0x000F8000U
1370 #define ADC_JSQR_JSQ4_0 0x00008000U
1371 #define ADC_JSQR_JSQ4_1 0x00010000U
1372 #define ADC_JSQR_JSQ4_2 0x00020000U
1373 #define ADC_JSQR_JSQ4_3 0x00040000U
1374 #define ADC_JSQR_JSQ4_4 0x00080000U
1375 #define ADC_JSQR_JL 0x00300000U
1376 #define ADC_JSQR_JL_0 0x00100000U
1377 #define ADC_JSQR_JL_1 0x00200000U
1379 /******************* Bit definition for ADC_JDR1 register *******************/
1380 #define ADC_JDR1_JDATA 0xFFFFU
1382 /******************* Bit definition for ADC_JDR2 register *******************/
1383 #define ADC_JDR2_JDATA 0xFFFFU
1385 /******************* Bit definition for ADC_JDR3 register *******************/
1386 #define ADC_JDR3_JDATA 0xFFFFU
1388 /******************* Bit definition for ADC_JDR4 register *******************/
1389 #define ADC_JDR4_JDATA 0xFFFFU
1391 /******************** Bit definition for ADC_DR register ********************/
1392 #define ADC_DR_DATA 0x0000FFFFU
1393 #define ADC_DR_ADC2DATA 0xFFFF0000U
1395 /******************* Bit definition for ADC_CSR register ********************/
1396 #define ADC_CSR_AWD1 0x00000001U
1397 #define ADC_CSR_EOC1 0x00000002U
1398 #define ADC_CSR_JEOC1 0x00000004U
1399 #define ADC_CSR_JSTRT1 0x00000008U
1400 #define ADC_CSR_STRT1 0x00000010U
1401 #define ADC_CSR_OVR1 0x00000020U
1402 #define ADC_CSR_AWD2 0x00000100U
1403 #define ADC_CSR_EOC2 0x00000200U
1404 #define ADC_CSR_JEOC2 0x00000400U
1405 #define ADC_CSR_JSTRT2 0x00000800U
1406 #define ADC_CSR_STRT2 0x00001000U
1407 #define ADC_CSR_OVR2 0x00002000U
1408 #define ADC_CSR_AWD3 0x00010000U
1409 #define ADC_CSR_EOC3 0x00020000U
1410 #define ADC_CSR_JEOC3 0x00040000U
1411 #define ADC_CSR_JSTRT3 0x00080000U
1412 #define ADC_CSR_STRT3 0x00100000U
1413 #define ADC_CSR_OVR3 0x00200000U
1415 /* Legacy defines */
1416 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1417 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1418 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1419 
1420 /******************* Bit definition for ADC_CCR register ********************/
1421 #define ADC_CCR_MULTI 0x0000001FU
1422 #define ADC_CCR_MULTI_0 0x00000001U
1423 #define ADC_CCR_MULTI_1 0x00000002U
1424 #define ADC_CCR_MULTI_2 0x00000004U
1425 #define ADC_CCR_MULTI_3 0x00000008U
1426 #define ADC_CCR_MULTI_4 0x00000010U
1427 #define ADC_CCR_DELAY 0x00000F00U
1428 #define ADC_CCR_DELAY_0 0x00000100U
1429 #define ADC_CCR_DELAY_1 0x00000200U
1430 #define ADC_CCR_DELAY_2 0x00000400U
1431 #define ADC_CCR_DELAY_3 0x00000800U
1432 #define ADC_CCR_DDS 0x00002000U
1433 #define ADC_CCR_DMA 0x0000C000U
1434 #define ADC_CCR_DMA_0 0x00004000U
1435 #define ADC_CCR_DMA_1 0x00008000U
1436 #define ADC_CCR_ADCPRE 0x00030000U
1437 #define ADC_CCR_ADCPRE_0 0x00010000U
1438 #define ADC_CCR_ADCPRE_1 0x00020000U
1439 #define ADC_CCR_VBATE 0x00400000U
1440 #define ADC_CCR_TSVREFE 0x00800000U
1442 /******************* Bit definition for ADC_CDR register ********************/
1443 #define ADC_CDR_DATA1 0x0000FFFFU
1444 #define ADC_CDR_DATA2 0xFFFF0000U
1446 /******************************************************************************/
1447 /* */
1448 /* Controller Area Network */
1449 /* */
1450 /******************************************************************************/
1452 /******************* Bit definition for CAN_MCR register ********************/
1453 #define CAN_MCR_INRQ 0x00000001U
1454 #define CAN_MCR_SLEEP 0x00000002U
1455 #define CAN_MCR_TXFP 0x00000004U
1456 #define CAN_MCR_RFLM 0x00000008U
1457 #define CAN_MCR_NART 0x00000010U
1458 #define CAN_MCR_AWUM 0x00000020U
1459 #define CAN_MCR_ABOM 0x00000040U
1460 #define CAN_MCR_TTCM 0x00000080U
1461 #define CAN_MCR_RESET 0x00008000U
1462 #define CAN_MCR_DBF 0x00010000U
1463 /******************* Bit definition for CAN_MSR register ********************/
1464 #define CAN_MSR_INAK 0x0001U
1465 #define CAN_MSR_SLAK 0x0002U
1466 #define CAN_MSR_ERRI 0x0004U
1467 #define CAN_MSR_WKUI 0x0008U
1468 #define CAN_MSR_SLAKI 0x0010U
1469 #define CAN_MSR_TXM 0x0100U
1470 #define CAN_MSR_RXM 0x0200U
1471 #define CAN_MSR_SAMP 0x0400U
1472 #define CAN_MSR_RX 0x0800U
1474 /******************* Bit definition for CAN_TSR register ********************/
1475 #define CAN_TSR_RQCP0 0x00000001U
1476 #define CAN_TSR_TXOK0 0x00000002U
1477 #define CAN_TSR_ALST0 0x00000004U
1478 #define CAN_TSR_TERR0 0x00000008U
1479 #define CAN_TSR_ABRQ0 0x00000080U
1480 #define CAN_TSR_RQCP1 0x00000100U
1481 #define CAN_TSR_TXOK1 0x00000200U
1482 #define CAN_TSR_ALST1 0x00000400U
1483 #define CAN_TSR_TERR1 0x00000800U
1484 #define CAN_TSR_ABRQ1 0x00008000U
1485 #define CAN_TSR_RQCP2 0x00010000U
1486 #define CAN_TSR_TXOK2 0x00020000U
1487 #define CAN_TSR_ALST2 0x00040000U
1488 #define CAN_TSR_TERR2 0x00080000U
1489 #define CAN_TSR_ABRQ2 0x00800000U
1490 #define CAN_TSR_CODE 0x03000000U
1492 #define CAN_TSR_TME 0x1C000000U
1493 #define CAN_TSR_TME0 0x04000000U
1494 #define CAN_TSR_TME1 0x08000000U
1495 #define CAN_TSR_TME2 0x10000000U
1497 #define CAN_TSR_LOW 0xE0000000U
1498 #define CAN_TSR_LOW0 0x20000000U
1499 #define CAN_TSR_LOW1 0x40000000U
1500 #define CAN_TSR_LOW2 0x80000000U
1502 /******************* Bit definition for CAN_RF0R register *******************/
1503 #define CAN_RF0R_FMP0 0x03U
1504 #define CAN_RF0R_FULL0 0x08U
1505 #define CAN_RF0R_FOVR0 0x10U
1506 #define CAN_RF0R_RFOM0 0x20U
1508 /******************* Bit definition for CAN_RF1R register *******************/
1509 #define CAN_RF1R_FMP1 0x03U
1510 #define CAN_RF1R_FULL1 0x08U
1511 #define CAN_RF1R_FOVR1 0x10U
1512 #define CAN_RF1R_RFOM1 0x20U
1514 /******************** Bit definition for CAN_IER register *******************/
1515 #define CAN_IER_TMEIE 0x00000001U
1516 #define CAN_IER_FMPIE0 0x00000002U
1517 #define CAN_IER_FFIE0 0x00000004U
1518 #define CAN_IER_FOVIE0 0x00000008U
1519 #define CAN_IER_FMPIE1 0x00000010U
1520 #define CAN_IER_FFIE1 0x00000020U
1521 #define CAN_IER_FOVIE1 0x00000040U
1522 #define CAN_IER_EWGIE 0x00000100U
1523 #define CAN_IER_EPVIE 0x00000200U
1524 #define CAN_IER_BOFIE 0x00000400U
1525 #define CAN_IER_LECIE 0x00000800U
1526 #define CAN_IER_ERRIE 0x00008000U
1527 #define CAN_IER_WKUIE 0x00010000U
1528 #define CAN_IER_SLKIE 0x00020000U
1529 #define CAN_IER_EWGIE 0x00000100U
1530 #define CAN_IER_EPVIE 0x00000200U
1531 #define CAN_IER_BOFIE 0x00000400U
1532 #define CAN_IER_LECIE 0x00000800U
1533 #define CAN_IER_ERRIE 0x00008000U
1536 /******************** Bit definition for CAN_ESR register *******************/
1537 #define CAN_ESR_EWGF 0x00000001U
1538 #define CAN_ESR_EPVF 0x00000002U
1539 #define CAN_ESR_BOFF 0x00000004U
1541 #define CAN_ESR_LEC 0x00000070U
1542 #define CAN_ESR_LEC_0 0x00000010U
1543 #define CAN_ESR_LEC_1 0x00000020U
1544 #define CAN_ESR_LEC_2 0x00000040U
1546 #define CAN_ESR_TEC 0x00FF0000U
1547 #define CAN_ESR_REC 0xFF000000U
1549 /******************* Bit definition for CAN_BTR register ********************/
1550 #define CAN_BTR_BRP 0x000003FFU
1551 #define CAN_BTR_TS1 0x000F0000U
1552 #define CAN_BTR_TS1_0 0x00010000U
1553 #define CAN_BTR_TS1_1 0x00020000U
1554 #define CAN_BTR_TS1_2 0x00040000U
1555 #define CAN_BTR_TS1_3 0x00080000U
1556 #define CAN_BTR_TS2 0x00700000U
1557 #define CAN_BTR_TS2_0 0x00100000U
1558 #define CAN_BTR_TS2_1 0x00200000U
1559 #define CAN_BTR_TS2_2 0x00400000U
1560 #define CAN_BTR_SJW 0x03000000U
1561 #define CAN_BTR_SJW_0 0x01000000U
1562 #define CAN_BTR_SJW_1 0x02000000U
1563 #define CAN_BTR_LBKM 0x40000000U
1564 #define CAN_BTR_SILM 0x80000000U
1568 /****************** Bit definition for CAN_TI0R register ********************/
1569 #define CAN_TI0R_TXRQ 0x00000001U
1570 #define CAN_TI0R_RTR 0x00000002U
1571 #define CAN_TI0R_IDE 0x00000004U
1572 #define CAN_TI0R_EXID 0x001FFFF8U
1573 #define CAN_TI0R_STID 0xFFE00000U
1575 /****************** Bit definition for CAN_TDT0R register *******************/
1576 #define CAN_TDT0R_DLC 0x0000000FU
1577 #define CAN_TDT0R_TGT 0x00000100U
1578 #define CAN_TDT0R_TIME 0xFFFF0000U
1580 /****************** Bit definition for CAN_TDL0R register *******************/
1581 #define CAN_TDL0R_DATA0 0x000000FFU
1582 #define CAN_TDL0R_DATA1 0x0000FF00U
1583 #define CAN_TDL0R_DATA2 0x00FF0000U
1584 #define CAN_TDL0R_DATA3 0xFF000000U
1586 /****************** Bit definition for CAN_TDH0R register *******************/
1587 #define CAN_TDH0R_DATA4 0x000000FFU
1588 #define CAN_TDH0R_DATA5 0x0000FF00U
1589 #define CAN_TDH0R_DATA6 0x00FF0000U
1590 #define CAN_TDH0R_DATA7 0xFF000000U
1592 /******************* Bit definition for CAN_TI1R register *******************/
1593 #define CAN_TI1R_TXRQ 0x00000001U
1594 #define CAN_TI1R_RTR 0x00000002U
1595 #define CAN_TI1R_IDE 0x00000004U
1596 #define CAN_TI1R_EXID 0x001FFFF8U
1597 #define CAN_TI1R_STID 0xFFE00000U
1599 /******************* Bit definition for CAN_TDT1R register ******************/
1600 #define CAN_TDT1R_DLC 0x0000000FU
1601 #define CAN_TDT1R_TGT 0x00000100U
1602 #define CAN_TDT1R_TIME 0xFFFF0000U
1604 /******************* Bit definition for CAN_TDL1R register ******************/
1605 #define CAN_TDL1R_DATA0 0x000000FFU
1606 #define CAN_TDL1R_DATA1 0x0000FF00U
1607 #define CAN_TDL1R_DATA2 0x00FF0000U
1608 #define CAN_TDL1R_DATA3 0xFF000000U
1610 /******************* Bit definition for CAN_TDH1R register ******************/
1611 #define CAN_TDH1R_DATA4 0x000000FFU
1612 #define CAN_TDH1R_DATA5 0x0000FF00U
1613 #define CAN_TDH1R_DATA6 0x00FF0000U
1614 #define CAN_TDH1R_DATA7 0xFF000000U
1616 /******************* Bit definition for CAN_TI2R register *******************/
1617 #define CAN_TI2R_TXRQ 0x00000001U
1618 #define CAN_TI2R_RTR 0x00000002U
1619 #define CAN_TI2R_IDE 0x00000004U
1620 #define CAN_TI2R_EXID 0x001FFFF8U
1621 #define CAN_TI2R_STID 0xFFE00000U
1623 /******************* Bit definition for CAN_TDT2R register ******************/
1624 #define CAN_TDT2R_DLC 0x0000000FU
1625 #define CAN_TDT2R_TGT 0x00000100U
1626 #define CAN_TDT2R_TIME 0xFFFF0000U
1628 /******************* Bit definition for CAN_TDL2R register ******************/
1629 #define CAN_TDL2R_DATA0 0x000000FFU
1630 #define CAN_TDL2R_DATA1 0x0000FF00U
1631 #define CAN_TDL2R_DATA2 0x00FF0000U
1632 #define CAN_TDL2R_DATA3 0xFF000000U
1634 /******************* Bit definition for CAN_TDH2R register ******************/
1635 #define CAN_TDH2R_DATA4 0x000000FFU
1636 #define CAN_TDH2R_DATA5 0x0000FF00U
1637 #define CAN_TDH2R_DATA6 0x00FF0000U
1638 #define CAN_TDH2R_DATA7 0xFF000000U
1640 /******************* Bit definition for CAN_RI0R register *******************/
1641 #define CAN_RI0R_RTR 0x00000002U
1642 #define CAN_RI0R_IDE 0x00000004U
1643 #define CAN_RI0R_EXID 0x001FFFF8U
1644 #define CAN_RI0R_STID 0xFFE00000U
1646 /******************* Bit definition for CAN_RDT0R register ******************/
1647 #define CAN_RDT0R_DLC 0x0000000FU
1648 #define CAN_RDT0R_FMI 0x0000FF00U
1649 #define CAN_RDT0R_TIME 0xFFFF0000U
1651 /******************* Bit definition for CAN_RDL0R register ******************/
1652 #define CAN_RDL0R_DATA0 0x000000FFU
1653 #define CAN_RDL0R_DATA1 0x0000FF00U
1654 #define CAN_RDL0R_DATA2 0x00FF0000U
1655 #define CAN_RDL0R_DATA3 0xFF000000U
1657 /******************* Bit definition for CAN_RDH0R register ******************/
1658 #define CAN_RDH0R_DATA4 0x000000FFU
1659 #define CAN_RDH0R_DATA5 0x0000FF00U
1660 #define CAN_RDH0R_DATA6 0x00FF0000U
1661 #define CAN_RDH0R_DATA7 0xFF000000U
1663 /******************* Bit definition for CAN_RI1R register *******************/
1664 #define CAN_RI1R_RTR 0x00000002U
1665 #define CAN_RI1R_IDE 0x00000004U
1666 #define CAN_RI1R_EXID 0x001FFFF8U
1667 #define CAN_RI1R_STID 0xFFE00000U
1669 /******************* Bit definition for CAN_RDT1R register ******************/
1670 #define CAN_RDT1R_DLC 0x0000000FU
1671 #define CAN_RDT1R_FMI 0x0000FF00U
1672 #define CAN_RDT1R_TIME 0xFFFF0000U
1674 /******************* Bit definition for CAN_RDL1R register ******************/
1675 #define CAN_RDL1R_DATA0 0x000000FFU
1676 #define CAN_RDL1R_DATA1 0x0000FF00U
1677 #define CAN_RDL1R_DATA2 0x00FF0000U
1678 #define CAN_RDL1R_DATA3 0xFF000000U
1680 /******************* Bit definition for CAN_RDH1R register ******************/
1681 #define CAN_RDH1R_DATA4 0x000000FFU
1682 #define CAN_RDH1R_DATA5 0x0000FF00U
1683 #define CAN_RDH1R_DATA6 0x00FF0000U
1684 #define CAN_RDH1R_DATA7 0xFF000000U
1687 /******************* Bit definition for CAN_FMR register ********************/
1688 #define CAN_FMR_FINIT 0x01U
1689 #define CAN_FMR_CAN2SB 0x00003F00U
1691 /******************* Bit definition for CAN_FM1R register *******************/
1692 #define CAN_FM1R_FBM 0x0FFFFFFFU
1693 #define CAN_FM1R_FBM0 0x00000001U
1694 #define CAN_FM1R_FBM1 0x00000002U
1695 #define CAN_FM1R_FBM2 0x00000004U
1696 #define CAN_FM1R_FBM3 0x00000008U
1697 #define CAN_FM1R_FBM4 0x00000010U
1698 #define CAN_FM1R_FBM5 0x00000020U
1699 #define CAN_FM1R_FBM6 0x00000040U
1700 #define CAN_FM1R_FBM7 0x00000080U
1701 #define CAN_FM1R_FBM8 0x00000100U
1702 #define CAN_FM1R_FBM9 0x00000200U
1703 #define CAN_FM1R_FBM10 0x00000400U
1704 #define CAN_FM1R_FBM11 0x00000800U
1705 #define CAN_FM1R_FBM12 0x00001000U
1706 #define CAN_FM1R_FBM13 0x00002000U
1707 #define CAN_FM1R_FBM14 0x00004000U
1708 #define CAN_FM1R_FBM15 0x00008000U
1709 #define CAN_FM1R_FBM16 0x00010000U
1710 #define CAN_FM1R_FBM17 0x00020000U
1711 #define CAN_FM1R_FBM18 0x00040000U
1712 #define CAN_FM1R_FBM19 0x00080000U
1713 #define CAN_FM1R_FBM20 0x00100000U
1714 #define CAN_FM1R_FBM21 0x00200000U
1715 #define CAN_FM1R_FBM22 0x00400000U
1716 #define CAN_FM1R_FBM23 0x00800000U
1717 #define CAN_FM1R_FBM24 0x01000000U
1718 #define CAN_FM1R_FBM25 0x02000000U
1719 #define CAN_FM1R_FBM26 0x04000000U
1720 #define CAN_FM1R_FBM27 0x08000000U
1722 /******************* Bit definition for CAN_FS1R register *******************/
1723 #define CAN_FS1R_FSC 0x0FFFFFFFU
1724 #define CAN_FS1R_FSC0 0x00000001U
1725 #define CAN_FS1R_FSC1 0x00000002U
1726 #define CAN_FS1R_FSC2 0x00000004U
1727 #define CAN_FS1R_FSC3 0x00000008U
1728 #define CAN_FS1R_FSC4 0x00000010U
1729 #define CAN_FS1R_FSC5 0x00000020U
1730 #define CAN_FS1R_FSC6 0x00000040U
1731 #define CAN_FS1R_FSC7 0x00000080U
1732 #define CAN_FS1R_FSC8 0x00000100U
1733 #define CAN_FS1R_FSC9 0x00000200U
1734 #define CAN_FS1R_FSC10 0x00000400U
1735 #define CAN_FS1R_FSC11 0x00000800U
1736 #define CAN_FS1R_FSC12 0x00001000U
1737 #define CAN_FS1R_FSC13 0x00002000U
1738 #define CAN_FS1R_FSC14 0x00004000U
1739 #define CAN_FS1R_FSC15 0x00008000U
1740 #define CAN_FS1R_FSC16 0x00010000U
1741 #define CAN_FS1R_FSC17 0x00020000U
1742 #define CAN_FS1R_FSC18 0x00040000U
1743 #define CAN_FS1R_FSC19 0x00080000U
1744 #define CAN_FS1R_FSC20 0x00100000U
1745 #define CAN_FS1R_FSC21 0x00200000U
1746 #define CAN_FS1R_FSC22 0x00400000U
1747 #define CAN_FS1R_FSC23 0x00800000U
1748 #define CAN_FS1R_FSC24 0x01000000U
1749 #define CAN_FS1R_FSC25 0x02000000U
1750 #define CAN_FS1R_FSC26 0x04000000U
1751 #define CAN_FS1R_FSC27 0x08000000U
1753 /****************** Bit definition for CAN_FFA1R register *******************/
1754 #define CAN_FFA1R_FFA 0x0FFFFFFFU
1755 #define CAN_FFA1R_FFA0 0x00000001U
1756 #define CAN_FFA1R_FFA1 0x00000002U
1757 #define CAN_FFA1R_FFA2 0x00000004U
1758 #define CAN_FFA1R_FFA3 0x00000008U
1759 #define CAN_FFA1R_FFA4 0x00000010U
1760 #define CAN_FFA1R_FFA5 0x00000020U
1761 #define CAN_FFA1R_FFA6 0x00000040U
1762 #define CAN_FFA1R_FFA7 0x00000080U
1763 #define CAN_FFA1R_FFA8 0x00000100U
1764 #define CAN_FFA1R_FFA9 0x00000200U
1765 #define CAN_FFA1R_FFA10 0x00000400U
1766 #define CAN_FFA1R_FFA11 0x00000800U
1767 #define CAN_FFA1R_FFA12 0x00001000U
1768 #define CAN_FFA1R_FFA13 0x00002000U
1769 #define CAN_FFA1R_FFA14 0x00004000U
1770 #define CAN_FFA1R_FFA15 0x00008000U
1771 #define CAN_FFA1R_FFA16 0x00010000U
1772 #define CAN_FFA1R_FFA17 0x00020000U
1773 #define CAN_FFA1R_FFA18 0x00040000U
1774 #define CAN_FFA1R_FFA19 0x00080000U
1775 #define CAN_FFA1R_FFA20 0x00100000U
1776 #define CAN_FFA1R_FFA21 0x00200000U
1777 #define CAN_FFA1R_FFA22 0x00400000U
1778 #define CAN_FFA1R_FFA23 0x00800000U
1779 #define CAN_FFA1R_FFA24 0x01000000U
1780 #define CAN_FFA1R_FFA25 0x02000000U
1781 #define CAN_FFA1R_FFA26 0x04000000U
1782 #define CAN_FFA1R_FFA27 0x08000000U
1784 /******************* Bit definition for CAN_FA1R register *******************/
1785 #define CAN_FA1R_FACT 0x0FFFFFFFU
1786 #define CAN_FA1R_FACT0 0x00000001U
1787 #define CAN_FA1R_FACT1 0x00000002U
1788 #define CAN_FA1R_FACT2 0x00000004U
1789 #define CAN_FA1R_FACT3 0x00000008U
1790 #define CAN_FA1R_FACT4 0x00000010U
1791 #define CAN_FA1R_FACT5 0x00000020U
1792 #define CAN_FA1R_FACT6 0x00000040U
1793 #define CAN_FA1R_FACT7 0x00000080U
1794 #define CAN_FA1R_FACT8 0x00000100U
1795 #define CAN_FA1R_FACT9 0x00000200U
1796 #define CAN_FA1R_FACT10 0x00000400U
1797 #define CAN_FA1R_FACT11 0x00000800U
1798 #define CAN_FA1R_FACT12 0x00001000U
1799 #define CAN_FA1R_FACT13 0x00002000U
1800 #define CAN_FA1R_FACT14 0x00004000U
1801 #define CAN_FA1R_FACT15 0x00008000U
1802 #define CAN_FA1R_FACT16 0x00010000U
1803 #define CAN_FA1R_FACT17 0x00020000U
1804 #define CAN_FA1R_FACT18 0x00040000U
1805 #define CAN_FA1R_FACT19 0x00080000U
1806 #define CAN_FA1R_FACT20 0x00100000U
1807 #define CAN_FA1R_FACT21 0x00200000U
1808 #define CAN_FA1R_FACT22 0x00400000U
1809 #define CAN_FA1R_FACT23 0x00800000U
1810 #define CAN_FA1R_FACT24 0x01000000U
1811 #define CAN_FA1R_FACT25 0x02000000U
1812 #define CAN_FA1R_FACT26 0x04000000U
1813 #define CAN_FA1R_FACT27 0x08000000U
1815 /******************* Bit definition for CAN_F0R1 register *******************/
1816 #define CAN_F0R1_FB0 0x00000001U
1817 #define CAN_F0R1_FB1 0x00000002U
1818 #define CAN_F0R1_FB2 0x00000004U
1819 #define CAN_F0R1_FB3 0x00000008U
1820 #define CAN_F0R1_FB4 0x00000010U
1821 #define CAN_F0R1_FB5 0x00000020U
1822 #define CAN_F0R1_FB6 0x00000040U
1823 #define CAN_F0R1_FB7 0x00000080U
1824 #define CAN_F0R1_FB8 0x00000100U
1825 #define CAN_F0R1_FB9 0x00000200U
1826 #define CAN_F0R1_FB10 0x00000400U
1827 #define CAN_F0R1_FB11 0x00000800U
1828 #define CAN_F0R1_FB12 0x00001000U
1829 #define CAN_F0R1_FB13 0x00002000U
1830 #define CAN_F0R1_FB14 0x00004000U
1831 #define CAN_F0R1_FB15 0x00008000U
1832 #define CAN_F0R1_FB16 0x00010000U
1833 #define CAN_F0R1_FB17 0x00020000U
1834 #define CAN_F0R1_FB18 0x00040000U
1835 #define CAN_F0R1_FB19 0x00080000U
1836 #define CAN_F0R1_FB20 0x00100000U
1837 #define CAN_F0R1_FB21 0x00200000U
1838 #define CAN_F0R1_FB22 0x00400000U
1839 #define CAN_F0R1_FB23 0x00800000U
1840 #define CAN_F0R1_FB24 0x01000000U
1841 #define CAN_F0R1_FB25 0x02000000U
1842 #define CAN_F0R1_FB26 0x04000000U
1843 #define CAN_F0R1_FB27 0x08000000U
1844 #define CAN_F0R1_FB28 0x10000000U
1845 #define CAN_F0R1_FB29 0x20000000U
1846 #define CAN_F0R1_FB30 0x40000000U
1847 #define CAN_F0R1_FB31 0x80000000U
1849 /******************* Bit definition for CAN_F1R1 register *******************/
1850 #define CAN_F1R1_FB0 0x00000001U
1851 #define CAN_F1R1_FB1 0x00000002U
1852 #define CAN_F1R1_FB2 0x00000004U
1853 #define CAN_F1R1_FB3 0x00000008U
1854 #define CAN_F1R1_FB4 0x00000010U
1855 #define CAN_F1R1_FB5 0x00000020U
1856 #define CAN_F1R1_FB6 0x00000040U
1857 #define CAN_F1R1_FB7 0x00000080U
1858 #define CAN_F1R1_FB8 0x00000100U
1859 #define CAN_F1R1_FB9 0x00000200U
1860 #define CAN_F1R1_FB10 0x00000400U
1861 #define CAN_F1R1_FB11 0x00000800U
1862 #define CAN_F1R1_FB12 0x00001000U
1863 #define CAN_F1R1_FB13 0x00002000U
1864 #define CAN_F1R1_FB14 0x00004000U
1865 #define CAN_F1R1_FB15 0x00008000U
1866 #define CAN_F1R1_FB16 0x00010000U
1867 #define CAN_F1R1_FB17 0x00020000U
1868 #define CAN_F1R1_FB18 0x00040000U
1869 #define CAN_F1R1_FB19 0x00080000U
1870 #define CAN_F1R1_FB20 0x00100000U
1871 #define CAN_F1R1_FB21 0x00200000U
1872 #define CAN_F1R1_FB22 0x00400000U
1873 #define CAN_F1R1_FB23 0x00800000U
1874 #define CAN_F1R1_FB24 0x01000000U
1875 #define CAN_F1R1_FB25 0x02000000U
1876 #define CAN_F1R1_FB26 0x04000000U
1877 #define CAN_F1R1_FB27 0x08000000U
1878 #define CAN_F1R1_FB28 0x10000000U
1879 #define CAN_F1R1_FB29 0x20000000U
1880 #define CAN_F1R1_FB30 0x40000000U
1881 #define CAN_F1R1_FB31 0x80000000U
1883 /******************* Bit definition for CAN_F2R1 register *******************/
1884 #define CAN_F2R1_FB0 0x00000001U
1885 #define CAN_F2R1_FB1 0x00000002U
1886 #define CAN_F2R1_FB2 0x00000004U
1887 #define CAN_F2R1_FB3 0x00000008U
1888 #define CAN_F2R1_FB4 0x00000010U
1889 #define CAN_F2R1_FB5 0x00000020U
1890 #define CAN_F2R1_FB6 0x00000040U
1891 #define CAN_F2R1_FB7 0x00000080U
1892 #define CAN_F2R1_FB8 0x00000100U
1893 #define CAN_F2R1_FB9 0x00000200U
1894 #define CAN_F2R1_FB10 0x00000400U
1895 #define CAN_F2R1_FB11 0x00000800U
1896 #define CAN_F2R1_FB12 0x00001000U
1897 #define CAN_F2R1_FB13 0x00002000U
1898 #define CAN_F2R1_FB14 0x00004000U
1899 #define CAN_F2R1_FB15 0x00008000U
1900 #define CAN_F2R1_FB16 0x00010000U
1901 #define CAN_F2R1_FB17 0x00020000U
1902 #define CAN_F2R1_FB18 0x00040000U
1903 #define CAN_F2R1_FB19 0x00080000U
1904 #define CAN_F2R1_FB20 0x00100000U
1905 #define CAN_F2R1_FB21 0x00200000U
1906 #define CAN_F2R1_FB22 0x00400000U
1907 #define CAN_F2R1_FB23 0x00800000U
1908 #define CAN_F2R1_FB24 0x01000000U
1909 #define CAN_F2R1_FB25 0x02000000U
1910 #define CAN_F2R1_FB26 0x04000000U
1911 #define CAN_F2R1_FB27 0x08000000U
1912 #define CAN_F2R1_FB28 0x10000000U
1913 #define CAN_F2R1_FB29 0x20000000U
1914 #define CAN_F2R1_FB30 0x40000000U
1915 #define CAN_F2R1_FB31 0x80000000U
1917 /******************* Bit definition for CAN_F3R1 register *******************/
1918 #define CAN_F3R1_FB0 0x00000001U
1919 #define CAN_F3R1_FB1 0x00000002U
1920 #define CAN_F3R1_FB2 0x00000004U
1921 #define CAN_F3R1_FB3 0x00000008U
1922 #define CAN_F3R1_FB4 0x00000010U
1923 #define CAN_F3R1_FB5 0x00000020U
1924 #define CAN_F3R1_FB6 0x00000040U
1925 #define CAN_F3R1_FB7 0x00000080U
1926 #define CAN_F3R1_FB8 0x00000100U
1927 #define CAN_F3R1_FB9 0x00000200U
1928 #define CAN_F3R1_FB10 0x00000400U
1929 #define CAN_F3R1_FB11 0x00000800U
1930 #define CAN_F3R1_FB12 0x00001000U
1931 #define CAN_F3R1_FB13 0x00002000U
1932 #define CAN_F3R1_FB14 0x00004000U
1933 #define CAN_F3R1_FB15 0x00008000U
1934 #define CAN_F3R1_FB16 0x00010000U
1935 #define CAN_F3R1_FB17 0x00020000U
1936 #define CAN_F3R1_FB18 0x00040000U
1937 #define CAN_F3R1_FB19 0x00080000U
1938 #define CAN_F3R1_FB20 0x00100000U
1939 #define CAN_F3R1_FB21 0x00200000U
1940 #define CAN_F3R1_FB22 0x00400000U
1941 #define CAN_F3R1_FB23 0x00800000U
1942 #define CAN_F3R1_FB24 0x01000000U
1943 #define CAN_F3R1_FB25 0x02000000U
1944 #define CAN_F3R1_FB26 0x04000000U
1945 #define CAN_F3R1_FB27 0x08000000U
1946 #define CAN_F3R1_FB28 0x10000000U
1947 #define CAN_F3R1_FB29 0x20000000U
1948 #define CAN_F3R1_FB30 0x40000000U
1949 #define CAN_F3R1_FB31 0x80000000U
1951 /******************* Bit definition for CAN_F4R1 register *******************/
1952 #define CAN_F4R1_FB0 0x00000001U
1953 #define CAN_F4R1_FB1 0x00000002U
1954 #define CAN_F4R1_FB2 0x00000004U
1955 #define CAN_F4R1_FB3 0x00000008U
1956 #define CAN_F4R1_FB4 0x00000010U
1957 #define CAN_F4R1_FB5 0x00000020U
1958 #define CAN_F4R1_FB6 0x00000040U
1959 #define CAN_F4R1_FB7 0x00000080U
1960 #define CAN_F4R1_FB8 0x00000100U
1961 #define CAN_F4R1_FB9 0x00000200U
1962 #define CAN_F4R1_FB10 0x00000400U
1963 #define CAN_F4R1_FB11 0x00000800U
1964 #define CAN_F4R1_FB12 0x00001000U
1965 #define CAN_F4R1_FB13 0x00002000U
1966 #define CAN_F4R1_FB14 0x00004000U
1967 #define CAN_F4R1_FB15 0x00008000U
1968 #define CAN_F4R1_FB16 0x00010000U
1969 #define CAN_F4R1_FB17 0x00020000U
1970 #define CAN_F4R1_FB18 0x00040000U
1971 #define CAN_F4R1_FB19 0x00080000U
1972 #define CAN_F4R1_FB20 0x00100000U
1973 #define CAN_F4R1_FB21 0x00200000U
1974 #define CAN_F4R1_FB22 0x00400000U
1975 #define CAN_F4R1_FB23 0x00800000U
1976 #define CAN_F4R1_FB24 0x01000000U
1977 #define CAN_F4R1_FB25 0x02000000U
1978 #define CAN_F4R1_FB26 0x04000000U
1979 #define CAN_F4R1_FB27 0x08000000U
1980 #define CAN_F4R1_FB28 0x10000000U
1981 #define CAN_F4R1_FB29 0x20000000U
1982 #define CAN_F4R1_FB30 0x40000000U
1983 #define CAN_F4R1_FB31 0x80000000U
1985 /******************* Bit definition for CAN_F5R1 register *******************/
1986 #define CAN_F5R1_FB0 0x00000001U
1987 #define CAN_F5R1_FB1 0x00000002U
1988 #define CAN_F5R1_FB2 0x00000004U
1989 #define CAN_F5R1_FB3 0x00000008U
1990 #define CAN_F5R1_FB4 0x00000010U
1991 #define CAN_F5R1_FB5 0x00000020U
1992 #define CAN_F5R1_FB6 0x00000040U
1993 #define CAN_F5R1_FB7 0x00000080U
1994 #define CAN_F5R1_FB8 0x00000100U
1995 #define CAN_F5R1_FB9 0x00000200U
1996 #define CAN_F5R1_FB10 0x00000400U
1997 #define CAN_F5R1_FB11 0x00000800U
1998 #define CAN_F5R1_FB12 0x00001000U
1999 #define CAN_F5R1_FB13 0x00002000U
2000 #define CAN_F5R1_FB14 0x00004000U
2001 #define CAN_F5R1_FB15 0x00008000U
2002 #define CAN_F5R1_FB16 0x00010000U
2003 #define CAN_F5R1_FB17 0x00020000U
2004 #define CAN_F5R1_FB18 0x00040000U
2005 #define CAN_F5R1_FB19 0x00080000U
2006 #define CAN_F5R1_FB20 0x00100000U
2007 #define CAN_F5R1_FB21 0x00200000U
2008 #define CAN_F5R1_FB22 0x00400000U
2009 #define CAN_F5R1_FB23 0x00800000U
2010 #define CAN_F5R1_FB24 0x01000000U
2011 #define CAN_F5R1_FB25 0x02000000U
2012 #define CAN_F5R1_FB26 0x04000000U
2013 #define CAN_F5R1_FB27 0x08000000U
2014 #define CAN_F5R1_FB28 0x10000000U
2015 #define CAN_F5R1_FB29 0x20000000U
2016 #define CAN_F5R1_FB30 0x40000000U
2017 #define CAN_F5R1_FB31 0x80000000U
2019 /******************* Bit definition for CAN_F6R1 register *******************/
2020 #define CAN_F6R1_FB0 0x00000001U
2021 #define CAN_F6R1_FB1 0x00000002U
2022 #define CAN_F6R1_FB2 0x00000004U
2023 #define CAN_F6R1_FB3 0x00000008U
2024 #define CAN_F6R1_FB4 0x00000010U
2025 #define CAN_F6R1_FB5 0x00000020U
2026 #define CAN_F6R1_FB6 0x00000040U
2027 #define CAN_F6R1_FB7 0x00000080U
2028 #define CAN_F6R1_FB8 0x00000100U
2029 #define CAN_F6R1_FB9 0x00000200U
2030 #define CAN_F6R1_FB10 0x00000400U
2031 #define CAN_F6R1_FB11 0x00000800U
2032 #define CAN_F6R1_FB12 0x00001000U
2033 #define CAN_F6R1_FB13 0x00002000U
2034 #define CAN_F6R1_FB14 0x00004000U
2035 #define CAN_F6R1_FB15 0x00008000U
2036 #define CAN_F6R1_FB16 0x00010000U
2037 #define CAN_F6R1_FB17 0x00020000U
2038 #define CAN_F6R1_FB18 0x00040000U
2039 #define CAN_F6R1_FB19 0x00080000U
2040 #define CAN_F6R1_FB20 0x00100000U
2041 #define CAN_F6R1_FB21 0x00200000U
2042 #define CAN_F6R1_FB22 0x00400000U
2043 #define CAN_F6R1_FB23 0x00800000U
2044 #define CAN_F6R1_FB24 0x01000000U
2045 #define CAN_F6R1_FB25 0x02000000U
2046 #define CAN_F6R1_FB26 0x04000000U
2047 #define CAN_F6R1_FB27 0x08000000U
2048 #define CAN_F6R1_FB28 0x10000000U
2049 #define CAN_F6R1_FB29 0x20000000U
2050 #define CAN_F6R1_FB30 0x40000000U
2051 #define CAN_F6R1_FB31 0x80000000U
2053 /******************* Bit definition for CAN_F7R1 register *******************/
2054 #define CAN_F7R1_FB0 0x00000001U
2055 #define CAN_F7R1_FB1 0x00000002U
2056 #define CAN_F7R1_FB2 0x00000004U
2057 #define CAN_F7R1_FB3 0x00000008U
2058 #define CAN_F7R1_FB4 0x00000010U
2059 #define CAN_F7R1_FB5 0x00000020U
2060 #define CAN_F7R1_FB6 0x00000040U
2061 #define CAN_F7R1_FB7 0x00000080U
2062 #define CAN_F7R1_FB8 0x00000100U
2063 #define CAN_F7R1_FB9 0x00000200U
2064 #define CAN_F7R1_FB10 0x00000400U
2065 #define CAN_F7R1_FB11 0x00000800U
2066 #define CAN_F7R1_FB12 0x00001000U
2067 #define CAN_F7R1_FB13 0x00002000U
2068 #define CAN_F7R1_FB14 0x00004000U
2069 #define CAN_F7R1_FB15 0x00008000U
2070 #define CAN_F7R1_FB16 0x00010000U
2071 #define CAN_F7R1_FB17 0x00020000U
2072 #define CAN_F7R1_FB18 0x00040000U
2073 #define CAN_F7R1_FB19 0x00080000U
2074 #define CAN_F7R1_FB20 0x00100000U
2075 #define CAN_F7R1_FB21 0x00200000U
2076 #define CAN_F7R1_FB22 0x00400000U
2077 #define CAN_F7R1_FB23 0x00800000U
2078 #define CAN_F7R1_FB24 0x01000000U
2079 #define CAN_F7R1_FB25 0x02000000U
2080 #define CAN_F7R1_FB26 0x04000000U
2081 #define CAN_F7R1_FB27 0x08000000U
2082 #define CAN_F7R1_FB28 0x10000000U
2083 #define CAN_F7R1_FB29 0x20000000U
2084 #define CAN_F7R1_FB30 0x40000000U
2085 #define CAN_F7R1_FB31 0x80000000U
2087 /******************* Bit definition for CAN_F8R1 register *******************/
2088 #define CAN_F8R1_FB0 0x00000001U
2089 #define CAN_F8R1_FB1 0x00000002U
2090 #define CAN_F8R1_FB2 0x00000004U
2091 #define CAN_F8R1_FB3 0x00000008U
2092 #define CAN_F8R1_FB4 0x00000010U
2093 #define CAN_F8R1_FB5 0x00000020U
2094 #define CAN_F8R1_FB6 0x00000040U
2095 #define CAN_F8R1_FB7 0x00000080U
2096 #define CAN_F8R1_FB8 0x00000100U
2097 #define CAN_F8R1_FB9 0x00000200U
2098 #define CAN_F8R1_FB10 0x00000400U
2099 #define CAN_F8R1_FB11 0x00000800U
2100 #define CAN_F8R1_FB12 0x00001000U
2101 #define CAN_F8R1_FB13 0x00002000U
2102 #define CAN_F8R1_FB14 0x00004000U
2103 #define CAN_F8R1_FB15 0x00008000U
2104 #define CAN_F8R1_FB16 0x00010000U
2105 #define CAN_F8R1_FB17 0x00020000U
2106 #define CAN_F8R1_FB18 0x00040000U
2107 #define CAN_F8R1_FB19 0x00080000U
2108 #define CAN_F8R1_FB20 0x00100000U
2109 #define CAN_F8R1_FB21 0x00200000U
2110 #define CAN_F8R1_FB22 0x00400000U
2111 #define CAN_F8R1_FB23 0x00800000U
2112 #define CAN_F8R1_FB24 0x01000000U
2113 #define CAN_F8R1_FB25 0x02000000U
2114 #define CAN_F8R1_FB26 0x04000000U
2115 #define CAN_F8R1_FB27 0x08000000U
2116 #define CAN_F8R1_FB28 0x10000000U
2117 #define CAN_F8R1_FB29 0x20000000U
2118 #define CAN_F8R1_FB30 0x40000000U
2119 #define CAN_F8R1_FB31 0x80000000U
2121 /******************* Bit definition for CAN_F9R1 register *******************/
2122 #define CAN_F9R1_FB0 0x00000001U
2123 #define CAN_F9R1_FB1 0x00000002U
2124 #define CAN_F9R1_FB2 0x00000004U
2125 #define CAN_F9R1_FB3 0x00000008U
2126 #define CAN_F9R1_FB4 0x00000010U
2127 #define CAN_F9R1_FB5 0x00000020U
2128 #define CAN_F9R1_FB6 0x00000040U
2129 #define CAN_F9R1_FB7 0x00000080U
2130 #define CAN_F9R1_FB8 0x00000100U
2131 #define CAN_F9R1_FB9 0x00000200U
2132 #define CAN_F9R1_FB10 0x00000400U
2133 #define CAN_F9R1_FB11 0x00000800U
2134 #define CAN_F9R1_FB12 0x00001000U
2135 #define CAN_F9R1_FB13 0x00002000U
2136 #define CAN_F9R1_FB14 0x00004000U
2137 #define CAN_F9R1_FB15 0x00008000U
2138 #define CAN_F9R1_FB16 0x00010000U
2139 #define CAN_F9R1_FB17 0x00020000U
2140 #define CAN_F9R1_FB18 0x00040000U
2141 #define CAN_F9R1_FB19 0x00080000U
2142 #define CAN_F9R1_FB20 0x00100000U
2143 #define CAN_F9R1_FB21 0x00200000U
2144 #define CAN_F9R1_FB22 0x00400000U
2145 #define CAN_F9R1_FB23 0x00800000U
2146 #define CAN_F9R1_FB24 0x01000000U
2147 #define CAN_F9R1_FB25 0x02000000U
2148 #define CAN_F9R1_FB26 0x04000000U
2149 #define CAN_F9R1_FB27 0x08000000U
2150 #define CAN_F9R1_FB28 0x10000000U
2151 #define CAN_F9R1_FB29 0x20000000U
2152 #define CAN_F9R1_FB30 0x40000000U
2153 #define CAN_F9R1_FB31 0x80000000U
2155 /******************* Bit definition for CAN_F10R1 register ******************/
2156 #define CAN_F10R1_FB0 0x00000001U
2157 #define CAN_F10R1_FB1 0x00000002U
2158 #define CAN_F10R1_FB2 0x00000004U
2159 #define CAN_F10R1_FB3 0x00000008U
2160 #define CAN_F10R1_FB4 0x00000010U
2161 #define CAN_F10R1_FB5 0x00000020U
2162 #define CAN_F10R1_FB6 0x00000040U
2163 #define CAN_F10R1_FB7 0x00000080U
2164 #define CAN_F10R1_FB8 0x00000100U
2165 #define CAN_F10R1_FB9 0x00000200U
2166 #define CAN_F10R1_FB10 0x00000400U
2167 #define CAN_F10R1_FB11 0x00000800U
2168 #define CAN_F10R1_FB12 0x00001000U
2169 #define CAN_F10R1_FB13 0x00002000U
2170 #define CAN_F10R1_FB14 0x00004000U
2171 #define CAN_F10R1_FB15 0x00008000U
2172 #define CAN_F10R1_FB16 0x00010000U
2173 #define CAN_F10R1_FB17 0x00020000U
2174 #define CAN_F10R1_FB18 0x00040000U
2175 #define CAN_F10R1_FB19 0x00080000U
2176 #define CAN_F10R1_FB20 0x00100000U
2177 #define CAN_F10R1_FB21 0x00200000U
2178 #define CAN_F10R1_FB22 0x00400000U
2179 #define CAN_F10R1_FB23 0x00800000U
2180 #define CAN_F10R1_FB24 0x01000000U
2181 #define CAN_F10R1_FB25 0x02000000U
2182 #define CAN_F10R1_FB26 0x04000000U
2183 #define CAN_F10R1_FB27 0x08000000U
2184 #define CAN_F10R1_FB28 0x10000000U
2185 #define CAN_F10R1_FB29 0x20000000U
2186 #define CAN_F10R1_FB30 0x40000000U
2187 #define CAN_F10R1_FB31 0x80000000U
2189 /******************* Bit definition for CAN_F11R1 register ******************/
2190 #define CAN_F11R1_FB0 0x00000001U
2191 #define CAN_F11R1_FB1 0x00000002U
2192 #define CAN_F11R1_FB2 0x00000004U
2193 #define CAN_F11R1_FB3 0x00000008U
2194 #define CAN_F11R1_FB4 0x00000010U
2195 #define CAN_F11R1_FB5 0x00000020U
2196 #define CAN_F11R1_FB6 0x00000040U
2197 #define CAN_F11R1_FB7 0x00000080U
2198 #define CAN_F11R1_FB8 0x00000100U
2199 #define CAN_F11R1_FB9 0x00000200U
2200 #define CAN_F11R1_FB10 0x00000400U
2201 #define CAN_F11R1_FB11 0x00000800U
2202 #define CAN_F11R1_FB12 0x00001000U
2203 #define CAN_F11R1_FB13 0x00002000U
2204 #define CAN_F11R1_FB14 0x00004000U
2205 #define CAN_F11R1_FB15 0x00008000U
2206 #define CAN_F11R1_FB16 0x00010000U
2207 #define CAN_F11R1_FB17 0x00020000U
2208 #define CAN_F11R1_FB18 0x00040000U
2209 #define CAN_F11R1_FB19 0x00080000U
2210 #define CAN_F11R1_FB20 0x00100000U
2211 #define CAN_F11R1_FB21 0x00200000U
2212 #define CAN_F11R1_FB22 0x00400000U
2213 #define CAN_F11R1_FB23 0x00800000U
2214 #define CAN_F11R1_FB24 0x01000000U
2215 #define CAN_F11R1_FB25 0x02000000U
2216 #define CAN_F11R1_FB26 0x04000000U
2217 #define CAN_F11R1_FB27 0x08000000U
2218 #define CAN_F11R1_FB28 0x10000000U
2219 #define CAN_F11R1_FB29 0x20000000U
2220 #define CAN_F11R1_FB30 0x40000000U
2221 #define CAN_F11R1_FB31 0x80000000U
2223 /******************* Bit definition for CAN_F12R1 register ******************/
2224 #define CAN_F12R1_FB0 0x00000001U
2225 #define CAN_F12R1_FB1 0x00000002U
2226 #define CAN_F12R1_FB2 0x00000004U
2227 #define CAN_F12R1_FB3 0x00000008U
2228 #define CAN_F12R1_FB4 0x00000010U
2229 #define CAN_F12R1_FB5 0x00000020U
2230 #define CAN_F12R1_FB6 0x00000040U
2231 #define CAN_F12R1_FB7 0x00000080U
2232 #define CAN_F12R1_FB8 0x00000100U
2233 #define CAN_F12R1_FB9 0x00000200U
2234 #define CAN_F12R1_FB10 0x00000400U
2235 #define CAN_F12R1_FB11 0x00000800U
2236 #define CAN_F12R1_FB12 0x00001000U
2237 #define CAN_F12R1_FB13 0x00002000U
2238 #define CAN_F12R1_FB14 0x00004000U
2239 #define CAN_F12R1_FB15 0x00008000U
2240 #define CAN_F12R1_FB16 0x00010000U
2241 #define CAN_F12R1_FB17 0x00020000U
2242 #define CAN_F12R1_FB18 0x00040000U
2243 #define CAN_F12R1_FB19 0x00080000U
2244 #define CAN_F12R1_FB20 0x00100000U
2245 #define CAN_F12R1_FB21 0x00200000U
2246 #define CAN_F12R1_FB22 0x00400000U
2247 #define CAN_F12R1_FB23 0x00800000U
2248 #define CAN_F12R1_FB24 0x01000000U
2249 #define CAN_F12R1_FB25 0x02000000U
2250 #define CAN_F12R1_FB26 0x04000000U
2251 #define CAN_F12R1_FB27 0x08000000U
2252 #define CAN_F12R1_FB28 0x10000000U
2253 #define CAN_F12R1_FB29 0x20000000U
2254 #define CAN_F12R1_FB30 0x40000000U
2255 #define CAN_F12R1_FB31 0x80000000U
2257 /******************* Bit definition for CAN_F13R1 register ******************/
2258 #define CAN_F13R1_FB0 0x00000001U
2259 #define CAN_F13R1_FB1 0x00000002U
2260 #define CAN_F13R1_FB2 0x00000004U
2261 #define CAN_F13R1_FB3 0x00000008U
2262 #define CAN_F13R1_FB4 0x00000010U
2263 #define CAN_F13R1_FB5 0x00000020U
2264 #define CAN_F13R1_FB6 0x00000040U
2265 #define CAN_F13R1_FB7 0x00000080U
2266 #define CAN_F13R1_FB8 0x00000100U
2267 #define CAN_F13R1_FB9 0x00000200U
2268 #define CAN_F13R1_FB10 0x00000400U
2269 #define CAN_F13R1_FB11 0x00000800U
2270 #define CAN_F13R1_FB12 0x00001000U
2271 #define CAN_F13R1_FB13 0x00002000U
2272 #define CAN_F13R1_FB14 0x00004000U
2273 #define CAN_F13R1_FB15 0x00008000U
2274 #define CAN_F13R1_FB16 0x00010000U
2275 #define CAN_F13R1_FB17 0x00020000U
2276 #define CAN_F13R1_FB18 0x00040000U
2277 #define CAN_F13R1_FB19 0x00080000U
2278 #define CAN_F13R1_FB20 0x00100000U
2279 #define CAN_F13R1_FB21 0x00200000U
2280 #define CAN_F13R1_FB22 0x00400000U
2281 #define CAN_F13R1_FB23 0x00800000U
2282 #define CAN_F13R1_FB24 0x01000000U
2283 #define CAN_F13R1_FB25 0x02000000U
2284 #define CAN_F13R1_FB26 0x04000000U
2285 #define CAN_F13R1_FB27 0x08000000U
2286 #define CAN_F13R1_FB28 0x10000000U
2287 #define CAN_F13R1_FB29 0x20000000U
2288 #define CAN_F13R1_FB30 0x40000000U
2289 #define CAN_F13R1_FB31 0x80000000U
2291 /******************* Bit definition for CAN_F0R2 register *******************/
2292 #define CAN_F0R2_FB0 0x00000001U
2293 #define CAN_F0R2_FB1 0x00000002U
2294 #define CAN_F0R2_FB2 0x00000004U
2295 #define CAN_F0R2_FB3 0x00000008U
2296 #define CAN_F0R2_FB4 0x00000010U
2297 #define CAN_F0R2_FB5 0x00000020U
2298 #define CAN_F0R2_FB6 0x00000040U
2299 #define CAN_F0R2_FB7 0x00000080U
2300 #define CAN_F0R2_FB8 0x00000100U
2301 #define CAN_F0R2_FB9 0x00000200U
2302 #define CAN_F0R2_FB10 0x00000400U
2303 #define CAN_F0R2_FB11 0x00000800U
2304 #define CAN_F0R2_FB12 0x00001000U
2305 #define CAN_F0R2_FB13 0x00002000U
2306 #define CAN_F0R2_FB14 0x00004000U
2307 #define CAN_F0R2_FB15 0x00008000U
2308 #define CAN_F0R2_FB16 0x00010000U
2309 #define CAN_F0R2_FB17 0x00020000U
2310 #define CAN_F0R2_FB18 0x00040000U
2311 #define CAN_F0R2_FB19 0x00080000U
2312 #define CAN_F0R2_FB20 0x00100000U
2313 #define CAN_F0R2_FB21 0x00200000U
2314 #define CAN_F0R2_FB22 0x00400000U
2315 #define CAN_F0R2_FB23 0x00800000U
2316 #define CAN_F0R2_FB24 0x01000000U
2317 #define CAN_F0R2_FB25 0x02000000U
2318 #define CAN_F0R2_FB26 0x04000000U
2319 #define CAN_F0R2_FB27 0x08000000U
2320 #define CAN_F0R2_FB28 0x10000000U
2321 #define CAN_F0R2_FB29 0x20000000U
2322 #define CAN_F0R2_FB30 0x40000000U
2323 #define CAN_F0R2_FB31 0x80000000U
2325 /******************* Bit definition for CAN_F1R2 register *******************/
2326 #define CAN_F1R2_FB0 0x00000001U
2327 #define CAN_F1R2_FB1 0x00000002U
2328 #define CAN_F1R2_FB2 0x00000004U
2329 #define CAN_F1R2_FB3 0x00000008U
2330 #define CAN_F1R2_FB4 0x00000010U
2331 #define CAN_F1R2_FB5 0x00000020U
2332 #define CAN_F1R2_FB6 0x00000040U
2333 #define CAN_F1R2_FB7 0x00000080U
2334 #define CAN_F1R2_FB8 0x00000100U
2335 #define CAN_F1R2_FB9 0x00000200U
2336 #define CAN_F1R2_FB10 0x00000400U
2337 #define CAN_F1R2_FB11 0x00000800U
2338 #define CAN_F1R2_FB12 0x00001000U
2339 #define CAN_F1R2_FB13 0x00002000U
2340 #define CAN_F1R2_FB14 0x00004000U
2341 #define CAN_F1R2_FB15 0x00008000U
2342 #define CAN_F1R2_FB16 0x00010000U
2343 #define CAN_F1R2_FB17 0x00020000U
2344 #define CAN_F1R2_FB18 0x00040000U
2345 #define CAN_F1R2_FB19 0x00080000U
2346 #define CAN_F1R2_FB20 0x00100000U
2347 #define CAN_F1R2_FB21 0x00200000U
2348 #define CAN_F1R2_FB22 0x00400000U
2349 #define CAN_F1R2_FB23 0x00800000U
2350 #define CAN_F1R2_FB24 0x01000000U
2351 #define CAN_F1R2_FB25 0x02000000U
2352 #define CAN_F1R2_FB26 0x04000000U
2353 #define CAN_F1R2_FB27 0x08000000U
2354 #define CAN_F1R2_FB28 0x10000000U
2355 #define CAN_F1R2_FB29 0x20000000U
2356 #define CAN_F1R2_FB30 0x40000000U
2357 #define CAN_F1R2_FB31 0x80000000U
2359 /******************* Bit definition for CAN_F2R2 register *******************/
2360 #define CAN_F2R2_FB0 0x00000001U
2361 #define CAN_F2R2_FB1 0x00000002U
2362 #define CAN_F2R2_FB2 0x00000004U
2363 #define CAN_F2R2_FB3 0x00000008U
2364 #define CAN_F2R2_FB4 0x00000010U
2365 #define CAN_F2R2_FB5 0x00000020U
2366 #define CAN_F2R2_FB6 0x00000040U
2367 #define CAN_F2R2_FB7 0x00000080U
2368 #define CAN_F2R2_FB8 0x00000100U
2369 #define CAN_F2R2_FB9 0x00000200U
2370 #define CAN_F2R2_FB10 0x00000400U
2371 #define CAN_F2R2_FB11 0x00000800U
2372 #define CAN_F2R2_FB12 0x00001000U
2373 #define CAN_F2R2_FB13 0x00002000U
2374 #define CAN_F2R2_FB14 0x00004000U
2375 #define CAN_F2R2_FB15 0x00008000U
2376 #define CAN_F2R2_FB16 0x00010000U
2377 #define CAN_F2R2_FB17 0x00020000U
2378 #define CAN_F2R2_FB18 0x00040000U
2379 #define CAN_F2R2_FB19 0x00080000U
2380 #define CAN_F2R2_FB20 0x00100000U
2381 #define CAN_F2R2_FB21 0x00200000U
2382 #define CAN_F2R2_FB22 0x00400000U
2383 #define CAN_F2R2_FB23 0x00800000U
2384 #define CAN_F2R2_FB24 0x01000000U
2385 #define CAN_F2R2_FB25 0x02000000U
2386 #define CAN_F2R2_FB26 0x04000000U
2387 #define CAN_F2R2_FB27 0x08000000U
2388 #define CAN_F2R2_FB28 0x10000000U
2389 #define CAN_F2R2_FB29 0x20000000U
2390 #define CAN_F2R2_FB30 0x40000000U
2391 #define CAN_F2R2_FB31 0x80000000U
2393 /******************* Bit definition for CAN_F3R2 register *******************/
2394 #define CAN_F3R2_FB0 0x00000001U
2395 #define CAN_F3R2_FB1 0x00000002U
2396 #define CAN_F3R2_FB2 0x00000004U
2397 #define CAN_F3R2_FB3 0x00000008U
2398 #define CAN_F3R2_FB4 0x00000010U
2399 #define CAN_F3R2_FB5 0x00000020U
2400 #define CAN_F3R2_FB6 0x00000040U
2401 #define CAN_F3R2_FB7 0x00000080U
2402 #define CAN_F3R2_FB8 0x00000100U
2403 #define CAN_F3R2_FB9 0x00000200U
2404 #define CAN_F3R2_FB10 0x00000400U
2405 #define CAN_F3R2_FB11 0x00000800U
2406 #define CAN_F3R2_FB12 0x00001000U
2407 #define CAN_F3R2_FB13 0x00002000U
2408 #define CAN_F3R2_FB14 0x00004000U
2409 #define CAN_F3R2_FB15 0x00008000U
2410 #define CAN_F3R2_FB16 0x00010000U
2411 #define CAN_F3R2_FB17 0x00020000U
2412 #define CAN_F3R2_FB18 0x00040000U
2413 #define CAN_F3R2_FB19 0x00080000U
2414 #define CAN_F3R2_FB20 0x00100000U
2415 #define CAN_F3R2_FB21 0x00200000U
2416 #define CAN_F3R2_FB22 0x00400000U
2417 #define CAN_F3R2_FB23 0x00800000U
2418 #define CAN_F3R2_FB24 0x01000000U
2419 #define CAN_F3R2_FB25 0x02000000U
2420 #define CAN_F3R2_FB26 0x04000000U
2421 #define CAN_F3R2_FB27 0x08000000U
2422 #define CAN_F3R2_FB28 0x10000000U
2423 #define CAN_F3R2_FB29 0x20000000U
2424 #define CAN_F3R2_FB30 0x40000000U
2425 #define CAN_F3R2_FB31 0x80000000U
2427 /******************* Bit definition for CAN_F4R2 register *******************/
2428 #define CAN_F4R2_FB0 0x00000001U
2429 #define CAN_F4R2_FB1 0x00000002U
2430 #define CAN_F4R2_FB2 0x00000004U
2431 #define CAN_F4R2_FB3 0x00000008U
2432 #define CAN_F4R2_FB4 0x00000010U
2433 #define CAN_F4R2_FB5 0x00000020U
2434 #define CAN_F4R2_FB6 0x00000040U
2435 #define CAN_F4R2_FB7 0x00000080U
2436 #define CAN_F4R2_FB8 0x00000100U
2437 #define CAN_F4R2_FB9 0x00000200U
2438 #define CAN_F4R2_FB10 0x00000400U
2439 #define CAN_F4R2_FB11 0x00000800U
2440 #define CAN_F4R2_FB12 0x00001000U
2441 #define CAN_F4R2_FB13 0x00002000U
2442 #define CAN_F4R2_FB14 0x00004000U
2443 #define CAN_F4R2_FB15 0x00008000U
2444 #define CAN_F4R2_FB16 0x00010000U
2445 #define CAN_F4R2_FB17 0x00020000U
2446 #define CAN_F4R2_FB18 0x00040000U
2447 #define CAN_F4R2_FB19 0x00080000U
2448 #define CAN_F4R2_FB20 0x00100000U
2449 #define CAN_F4R2_FB21 0x00200000U
2450 #define CAN_F4R2_FB22 0x00400000U
2451 #define CAN_F4R2_FB23 0x00800000U
2452 #define CAN_F4R2_FB24 0x01000000U
2453 #define CAN_F4R2_FB25 0x02000000U
2454 #define CAN_F4R2_FB26 0x04000000U
2455 #define CAN_F4R2_FB27 0x08000000U
2456 #define CAN_F4R2_FB28 0x10000000U
2457 #define CAN_F4R2_FB29 0x20000000U
2458 #define CAN_F4R2_FB30 0x40000000U
2459 #define CAN_F4R2_FB31 0x80000000U
2461 /******************* Bit definition for CAN_F5R2 register *******************/
2462 #define CAN_F5R2_FB0 0x00000001U
2463 #define CAN_F5R2_FB1 0x00000002U
2464 #define CAN_F5R2_FB2 0x00000004U
2465 #define CAN_F5R2_FB3 0x00000008U
2466 #define CAN_F5R2_FB4 0x00000010U
2467 #define CAN_F5R2_FB5 0x00000020U
2468 #define CAN_F5R2_FB6 0x00000040U
2469 #define CAN_F5R2_FB7 0x00000080U
2470 #define CAN_F5R2_FB8 0x00000100U
2471 #define CAN_F5R2_FB9 0x00000200U
2472 #define CAN_F5R2_FB10 0x00000400U
2473 #define CAN_F5R2_FB11 0x00000800U
2474 #define CAN_F5R2_FB12 0x00001000U
2475 #define CAN_F5R2_FB13 0x00002000U
2476 #define CAN_F5R2_FB14 0x00004000U
2477 #define CAN_F5R2_FB15 0x00008000U
2478 #define CAN_F5R2_FB16 0x00010000U
2479 #define CAN_F5R2_FB17 0x00020000U
2480 #define CAN_F5R2_FB18 0x00040000U
2481 #define CAN_F5R2_FB19 0x00080000U
2482 #define CAN_F5R2_FB20 0x00100000U
2483 #define CAN_F5R2_FB21 0x00200000U
2484 #define CAN_F5R2_FB22 0x00400000U
2485 #define CAN_F5R2_FB23 0x00800000U
2486 #define CAN_F5R2_FB24 0x01000000U
2487 #define CAN_F5R2_FB25 0x02000000U
2488 #define CAN_F5R2_FB26 0x04000000U
2489 #define CAN_F5R2_FB27 0x08000000U
2490 #define CAN_F5R2_FB28 0x10000000U
2491 #define CAN_F5R2_FB29 0x20000000U
2492 #define CAN_F5R2_FB30 0x40000000U
2493 #define CAN_F5R2_FB31 0x80000000U
2495 /******************* Bit definition for CAN_F6R2 register *******************/
2496 #define CAN_F6R2_FB0 0x00000001U
2497 #define CAN_F6R2_FB1 0x00000002U
2498 #define CAN_F6R2_FB2 0x00000004U
2499 #define CAN_F6R2_FB3 0x00000008U
2500 #define CAN_F6R2_FB4 0x00000010U
2501 #define CAN_F6R2_FB5 0x00000020U
2502 #define CAN_F6R2_FB6 0x00000040U
2503 #define CAN_F6R2_FB7 0x00000080U
2504 #define CAN_F6R2_FB8 0x00000100U
2505 #define CAN_F6R2_FB9 0x00000200U
2506 #define CAN_F6R2_FB10 0x00000400U
2507 #define CAN_F6R2_FB11 0x00000800U
2508 #define CAN_F6R2_FB12 0x00001000U
2509 #define CAN_F6R2_FB13 0x00002000U
2510 #define CAN_F6R2_FB14 0x00004000U
2511 #define CAN_F6R2_FB15 0x00008000U
2512 #define CAN_F6R2_FB16 0x00010000U
2513 #define CAN_F6R2_FB17 0x00020000U
2514 #define CAN_F6R2_FB18 0x00040000U
2515 #define CAN_F6R2_FB19 0x00080000U
2516 #define CAN_F6R2_FB20 0x00100000U
2517 #define CAN_F6R2_FB21 0x00200000U
2518 #define CAN_F6R2_FB22 0x00400000U
2519 #define CAN_F6R2_FB23 0x00800000U
2520 #define CAN_F6R2_FB24 0x01000000U
2521 #define CAN_F6R2_FB25 0x02000000U
2522 #define CAN_F6R2_FB26 0x04000000U
2523 #define CAN_F6R2_FB27 0x08000000U
2524 #define CAN_F6R2_FB28 0x10000000U
2525 #define CAN_F6R2_FB29 0x20000000U
2526 #define CAN_F6R2_FB30 0x40000000U
2527 #define CAN_F6R2_FB31 0x80000000U
2529 /******************* Bit definition for CAN_F7R2 register *******************/
2530 #define CAN_F7R2_FB0 0x00000001U
2531 #define CAN_F7R2_FB1 0x00000002U
2532 #define CAN_F7R2_FB2 0x00000004U
2533 #define CAN_F7R2_FB3 0x00000008U
2534 #define CAN_F7R2_FB4 0x00000010U
2535 #define CAN_F7R2_FB5 0x00000020U
2536 #define CAN_F7R2_FB6 0x00000040U
2537 #define CAN_F7R2_FB7 0x00000080U
2538 #define CAN_F7R2_FB8 0x00000100U
2539 #define CAN_F7R2_FB9 0x00000200U
2540 #define CAN_F7R2_FB10 0x00000400U
2541 #define CAN_F7R2_FB11 0x00000800U
2542 #define CAN_F7R2_FB12 0x00001000U
2543 #define CAN_F7R2_FB13 0x00002000U
2544 #define CAN_F7R2_FB14 0x00004000U
2545 #define CAN_F7R2_FB15 0x00008000U
2546 #define CAN_F7R2_FB16 0x00010000U
2547 #define CAN_F7R2_FB17 0x00020000U
2548 #define CAN_F7R2_FB18 0x00040000U
2549 #define CAN_F7R2_FB19 0x00080000U
2550 #define CAN_F7R2_FB20 0x00100000U
2551 #define CAN_F7R2_FB21 0x00200000U
2552 #define CAN_F7R2_FB22 0x00400000U
2553 #define CAN_F7R2_FB23 0x00800000U
2554 #define CAN_F7R2_FB24 0x01000000U
2555 #define CAN_F7R2_FB25 0x02000000U
2556 #define CAN_F7R2_FB26 0x04000000U
2557 #define CAN_F7R2_FB27 0x08000000U
2558 #define CAN_F7R2_FB28 0x10000000U
2559 #define CAN_F7R2_FB29 0x20000000U
2560 #define CAN_F7R2_FB30 0x40000000U
2561 #define CAN_F7R2_FB31 0x80000000U
2563 /******************* Bit definition for CAN_F8R2 register *******************/
2564 #define CAN_F8R2_FB0 0x00000001U
2565 #define CAN_F8R2_FB1 0x00000002U
2566 #define CAN_F8R2_FB2 0x00000004U
2567 #define CAN_F8R2_FB3 0x00000008U
2568 #define CAN_F8R2_FB4 0x00000010U
2569 #define CAN_F8R2_FB5 0x00000020U
2570 #define CAN_F8R2_FB6 0x00000040U
2571 #define CAN_F8R2_FB7 0x00000080U
2572 #define CAN_F8R2_FB8 0x00000100U
2573 #define CAN_F8R2_FB9 0x00000200U
2574 #define CAN_F8R2_FB10 0x00000400U
2575 #define CAN_F8R2_FB11 0x00000800U
2576 #define CAN_F8R2_FB12 0x00001000U
2577 #define CAN_F8R2_FB13 0x00002000U
2578 #define CAN_F8R2_FB14 0x00004000U
2579 #define CAN_F8R2_FB15 0x00008000U
2580 #define CAN_F8R2_FB16 0x00010000U
2581 #define CAN_F8R2_FB17 0x00020000U
2582 #define CAN_F8R2_FB18 0x00040000U
2583 #define CAN_F8R2_FB19 0x00080000U
2584 #define CAN_F8R2_FB20 0x00100000U
2585 #define CAN_F8R2_FB21 0x00200000U
2586 #define CAN_F8R2_FB22 0x00400000U
2587 #define CAN_F8R2_FB23 0x00800000U
2588 #define CAN_F8R2_FB24 0x01000000U
2589 #define CAN_F8R2_FB25 0x02000000U
2590 #define CAN_F8R2_FB26 0x04000000U
2591 #define CAN_F8R2_FB27 0x08000000U
2592 #define CAN_F8R2_FB28 0x10000000U
2593 #define CAN_F8R2_FB29 0x20000000U
2594 #define CAN_F8R2_FB30 0x40000000U
2595 #define CAN_F8R2_FB31 0x80000000U
2597 /******************* Bit definition for CAN_F9R2 register *******************/
2598 #define CAN_F9R2_FB0 0x00000001U
2599 #define CAN_F9R2_FB1 0x00000002U
2600 #define CAN_F9R2_FB2 0x00000004U
2601 #define CAN_F9R2_FB3 0x00000008U
2602 #define CAN_F9R2_FB4 0x00000010U
2603 #define CAN_F9R2_FB5 0x00000020U
2604 #define CAN_F9R2_FB6 0x00000040U
2605 #define CAN_F9R2_FB7 0x00000080U
2606 #define CAN_F9R2_FB8 0x00000100U
2607 #define CAN_F9R2_FB9 0x00000200U
2608 #define CAN_F9R2_FB10 0x00000400U
2609 #define CAN_F9R2_FB11 0x00000800U
2610 #define CAN_F9R2_FB12 0x00001000U
2611 #define CAN_F9R2_FB13 0x00002000U
2612 #define CAN_F9R2_FB14 0x00004000U
2613 #define CAN_F9R2_FB15 0x00008000U
2614 #define CAN_F9R2_FB16 0x00010000U
2615 #define CAN_F9R2_FB17 0x00020000U
2616 #define CAN_F9R2_FB18 0x00040000U
2617 #define CAN_F9R2_FB19 0x00080000U
2618 #define CAN_F9R2_FB20 0x00100000U
2619 #define CAN_F9R2_FB21 0x00200000U
2620 #define CAN_F9R2_FB22 0x00400000U
2621 #define CAN_F9R2_FB23 0x00800000U
2622 #define CAN_F9R2_FB24 0x01000000U
2623 #define CAN_F9R2_FB25 0x02000000U
2624 #define CAN_F9R2_FB26 0x04000000U
2625 #define CAN_F9R2_FB27 0x08000000U
2626 #define CAN_F9R2_FB28 0x10000000U
2627 #define CAN_F9R2_FB29 0x20000000U
2628 #define CAN_F9R2_FB30 0x40000000U
2629 #define CAN_F9R2_FB31 0x80000000U
2631 /******************* Bit definition for CAN_F10R2 register ******************/
2632 #define CAN_F10R2_FB0 0x00000001U
2633 #define CAN_F10R2_FB1 0x00000002U
2634 #define CAN_F10R2_FB2 0x00000004U
2635 #define CAN_F10R2_FB3 0x00000008U
2636 #define CAN_F10R2_FB4 0x00000010U
2637 #define CAN_F10R2_FB5 0x00000020U
2638 #define CAN_F10R2_FB6 0x00000040U
2639 #define CAN_F10R2_FB7 0x00000080U
2640 #define CAN_F10R2_FB8 0x00000100U
2641 #define CAN_F10R2_FB9 0x00000200U
2642 #define CAN_F10R2_FB10 0x00000400U
2643 #define CAN_F10R2_FB11 0x00000800U
2644 #define CAN_F10R2_FB12 0x00001000U
2645 #define CAN_F10R2_FB13 0x00002000U
2646 #define CAN_F10R2_FB14 0x00004000U
2647 #define CAN_F10R2_FB15 0x00008000U
2648 #define CAN_F10R2_FB16 0x00010000U
2649 #define CAN_F10R2_FB17 0x00020000U
2650 #define CAN_F10R2_FB18 0x00040000U
2651 #define CAN_F10R2_FB19 0x00080000U
2652 #define CAN_F10R2_FB20 0x00100000U
2653 #define CAN_F10R2_FB21 0x00200000U
2654 #define CAN_F10R2_FB22 0x00400000U
2655 #define CAN_F10R2_FB23 0x00800000U
2656 #define CAN_F10R2_FB24 0x01000000U
2657 #define CAN_F10R2_FB25 0x02000000U
2658 #define CAN_F10R2_FB26 0x04000000U
2659 #define CAN_F10R2_FB27 0x08000000U
2660 #define CAN_F10R2_FB28 0x10000000U
2661 #define CAN_F10R2_FB29 0x20000000U
2662 #define CAN_F10R2_FB30 0x40000000U
2663 #define CAN_F10R2_FB31 0x80000000U
2665 /******************* Bit definition for CAN_F11R2 register ******************/
2666 #define CAN_F11R2_FB0 0x00000001U
2667 #define CAN_F11R2_FB1 0x00000002U
2668 #define CAN_F11R2_FB2 0x00000004U
2669 #define CAN_F11R2_FB3 0x00000008U
2670 #define CAN_F11R2_FB4 0x00000010U
2671 #define CAN_F11R2_FB5 0x00000020U
2672 #define CAN_F11R2_FB6 0x00000040U
2673 #define CAN_F11R2_FB7 0x00000080U
2674 #define CAN_F11R2_FB8 0x00000100U
2675 #define CAN_F11R2_FB9 0x00000200U
2676 #define CAN_F11R2_FB10 0x00000400U
2677 #define CAN_F11R2_FB11 0x00000800U
2678 #define CAN_F11R2_FB12 0x00001000U
2679 #define CAN_F11R2_FB13 0x00002000U
2680 #define CAN_F11R2_FB14 0x00004000U
2681 #define CAN_F11R2_FB15 0x00008000U
2682 #define CAN_F11R2_FB16 0x00010000U
2683 #define CAN_F11R2_FB17 0x00020000U
2684 #define CAN_F11R2_FB18 0x00040000U
2685 #define CAN_F11R2_FB19 0x00080000U
2686 #define CAN_F11R2_FB20 0x00100000U
2687 #define CAN_F11R2_FB21 0x00200000U
2688 #define CAN_F11R2_FB22 0x00400000U
2689 #define CAN_F11R2_FB23 0x00800000U
2690 #define CAN_F11R2_FB24 0x01000000U
2691 #define CAN_F11R2_FB25 0x02000000U
2692 #define CAN_F11R2_FB26 0x04000000U
2693 #define CAN_F11R2_FB27 0x08000000U
2694 #define CAN_F11R2_FB28 0x10000000U
2695 #define CAN_F11R2_FB29 0x20000000U
2696 #define CAN_F11R2_FB30 0x40000000U
2697 #define CAN_F11R2_FB31 0x80000000U
2699 /******************* Bit definition for CAN_F12R2 register ******************/
2700 #define CAN_F12R2_FB0 0x00000001U
2701 #define CAN_F12R2_FB1 0x00000002U
2702 #define CAN_F12R2_FB2 0x00000004U
2703 #define CAN_F12R2_FB3 0x00000008U
2704 #define CAN_F12R2_FB4 0x00000010U
2705 #define CAN_F12R2_FB5 0x00000020U
2706 #define CAN_F12R2_FB6 0x00000040U
2707 #define CAN_F12R2_FB7 0x00000080U
2708 #define CAN_F12R2_FB8 0x00000100U
2709 #define CAN_F12R2_FB9 0x00000200U
2710 #define CAN_F12R2_FB10 0x00000400U
2711 #define CAN_F12R2_FB11 0x00000800U
2712 #define CAN_F12R2_FB12 0x00001000U
2713 #define CAN_F12R2_FB13 0x00002000U
2714 #define CAN_F12R2_FB14 0x00004000U
2715 #define CAN_F12R2_FB15 0x00008000U
2716 #define CAN_F12R2_FB16 0x00010000U
2717 #define CAN_F12R2_FB17 0x00020000U
2718 #define CAN_F12R2_FB18 0x00040000U
2719 #define CAN_F12R2_FB19 0x00080000U
2720 #define CAN_F12R2_FB20 0x00100000U
2721 #define CAN_F12R2_FB21 0x00200000U
2722 #define CAN_F12R2_FB22 0x00400000U
2723 #define CAN_F12R2_FB23 0x00800000U
2724 #define CAN_F12R2_FB24 0x01000000U
2725 #define CAN_F12R2_FB25 0x02000000U
2726 #define CAN_F12R2_FB26 0x04000000U
2727 #define CAN_F12R2_FB27 0x08000000U
2728 #define CAN_F12R2_FB28 0x10000000U
2729 #define CAN_F12R2_FB29 0x20000000U
2730 #define CAN_F12R2_FB30 0x40000000U
2731 #define CAN_F12R2_FB31 0x80000000U
2733 /******************* Bit definition for CAN_F13R2 register ******************/
2734 #define CAN_F13R2_FB0 0x00000001U
2735 #define CAN_F13R2_FB1 0x00000002U
2736 #define CAN_F13R2_FB2 0x00000004U
2737 #define CAN_F13R2_FB3 0x00000008U
2738 #define CAN_F13R2_FB4 0x00000010U
2739 #define CAN_F13R2_FB5 0x00000020U
2740 #define CAN_F13R2_FB6 0x00000040U
2741 #define CAN_F13R2_FB7 0x00000080U
2742 #define CAN_F13R2_FB8 0x00000100U
2743 #define CAN_F13R2_FB9 0x00000200U
2744 #define CAN_F13R2_FB10 0x00000400U
2745 #define CAN_F13R2_FB11 0x00000800U
2746 #define CAN_F13R2_FB12 0x00001000U
2747 #define CAN_F13R2_FB13 0x00002000U
2748 #define CAN_F13R2_FB14 0x00004000U
2749 #define CAN_F13R2_FB15 0x00008000U
2750 #define CAN_F13R2_FB16 0x00010000U
2751 #define CAN_F13R2_FB17 0x00020000U
2752 #define CAN_F13R2_FB18 0x00040000U
2753 #define CAN_F13R2_FB19 0x00080000U
2754 #define CAN_F13R2_FB20 0x00100000U
2755 #define CAN_F13R2_FB21 0x00200000U
2756 #define CAN_F13R2_FB22 0x00400000U
2757 #define CAN_F13R2_FB23 0x00800000U
2758 #define CAN_F13R2_FB24 0x01000000U
2759 #define CAN_F13R2_FB25 0x02000000U
2760 #define CAN_F13R2_FB26 0x04000000U
2761 #define CAN_F13R2_FB27 0x08000000U
2762 #define CAN_F13R2_FB28 0x10000000U
2763 #define CAN_F13R2_FB29 0x20000000U
2764 #define CAN_F13R2_FB30 0x40000000U
2765 #define CAN_F13R2_FB31 0x80000000U
2767 /******************************************************************************/
2768 /* */
2769 /* CRC calculation unit */
2770 /* */
2771 /******************************************************************************/
2772 /******************* Bit definition for CRC_DR register *********************/
2773 #define CRC_DR_DR 0xFFFFFFFFU
2776 /******************* Bit definition for CRC_IDR register ********************/
2777 #define CRC_IDR_IDR 0xFFU
2780 /******************** Bit definition for CRC_CR register ********************/
2781 #define CRC_CR_RESET 0x01U
2784 /******************************************************************************/
2785 /* */
2786 /* Digital to Analog Converter */
2787 /* */
2788 /******************************************************************************/
2789 /******************** Bit definition for DAC_CR register ********************/
2790 #define DAC_CR_EN1 0x00000001U
2791 #define DAC_CR_BOFF1 0x00000002U
2792 #define DAC_CR_TEN1 0x00000004U
2794 #define DAC_CR_TSEL1 0x00000038U
2795 #define DAC_CR_TSEL1_0 0x00000008U
2796 #define DAC_CR_TSEL1_1 0x00000010U
2797 #define DAC_CR_TSEL1_2 0x00000020U
2799 #define DAC_CR_WAVE1 0x000000C0U
2800 #define DAC_CR_WAVE1_0 0x00000040U
2801 #define DAC_CR_WAVE1_1 0x00000080U
2803 #define DAC_CR_MAMP1 0x00000F00U
2804 #define DAC_CR_MAMP1_0 0x00000100U
2805 #define DAC_CR_MAMP1_1 0x00000200U
2806 #define DAC_CR_MAMP1_2 0x00000400U
2807 #define DAC_CR_MAMP1_3 0x00000800U
2809 #define DAC_CR_DMAEN1 0x00001000U
2810 #define DAC_CR_DMAUDRIE1 0x00002000U
2811 #define DAC_CR_EN2 0x00010000U
2812 #define DAC_CR_BOFF2 0x00020000U
2813 #define DAC_CR_TEN2 0x00040000U
2815 #define DAC_CR_TSEL2 0x00380000U
2816 #define DAC_CR_TSEL2_0 0x00080000U
2817 #define DAC_CR_TSEL2_1 0x00100000U
2818 #define DAC_CR_TSEL2_2 0x00200000U
2820 #define DAC_CR_WAVE2 0x00C00000U
2821 #define DAC_CR_WAVE2_0 0x00400000U
2822 #define DAC_CR_WAVE2_1 0x00800000U
2824 #define DAC_CR_MAMP2 0x0F000000U
2825 #define DAC_CR_MAMP2_0 0x01000000U
2826 #define DAC_CR_MAMP2_1 0x02000000U
2827 #define DAC_CR_MAMP2_2 0x04000000U
2828 #define DAC_CR_MAMP2_3 0x08000000U
2830 #define DAC_CR_DMAEN2 0x10000000U
2831 #define DAC_CR_DMAUDRIE2 0x20000000U
2833 /***************** Bit definition for DAC_SWTRIGR register ******************/
2834 #define DAC_SWTRIGR_SWTRIG1 0x01U
2835 #define DAC_SWTRIGR_SWTRIG2 0x02U
2837 /***************** Bit definition for DAC_DHR12R1 register ******************/
2838 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
2840 /***************** Bit definition for DAC_DHR12L1 register ******************/
2841 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
2843 /****************** Bit definition for DAC_DHR8R1 register ******************/
2844 #define DAC_DHR8R1_DACC1DHR 0xFFU
2846 /***************** Bit definition for DAC_DHR12R2 register ******************/
2847 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
2849 /***************** Bit definition for DAC_DHR12L2 register ******************/
2850 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
2852 /****************** Bit definition for DAC_DHR8R2 register ******************/
2853 #define DAC_DHR8R2_DACC2DHR 0xFFU
2855 /***************** Bit definition for DAC_DHR12RD register ******************/
2856 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
2857 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
2859 /***************** Bit definition for DAC_DHR12LD register ******************/
2860 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
2861 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
2863 /****************** Bit definition for DAC_DHR8RD register ******************/
2864 #define DAC_DHR8RD_DACC1DHR 0x00FFU
2865 #define DAC_DHR8RD_DACC2DHR 0xFF00U
2867 /******************* Bit definition for DAC_DOR1 register *******************/
2868 #define DAC_DOR1_DACC1DOR 0x0FFFU
2870 /******************* Bit definition for DAC_DOR2 register *******************/
2871 #define DAC_DOR2_DACC2DOR 0x0FFFU
2873 /******************** Bit definition for DAC_SR register ********************/
2874 #define DAC_SR_DMAUDR1 0x00002000U
2875 #define DAC_SR_DMAUDR2 0x20000000U
2877 /******************************************************************************/
2878 /* */
2879 /* Debug MCU */
2880 /* */
2881 /******************************************************************************/
2882 
2883 /******************************************************************************/
2884 /* */
2885 /* DMA Controller */
2886 /* */
2887 /******************************************************************************/
2888 /******************** Bits definition for DMA_SxCR register *****************/
2889 #define DMA_SxCR_CHSEL 0x0E000000U
2890 #define DMA_SxCR_CHSEL_0 0x02000000U
2891 #define DMA_SxCR_CHSEL_1 0x04000000U
2892 #define DMA_SxCR_CHSEL_2 0x08000000U
2893 #define DMA_SxCR_MBURST 0x01800000U
2894 #define DMA_SxCR_MBURST_0 0x00800000U
2895 #define DMA_SxCR_MBURST_1 0x01000000U
2896 #define DMA_SxCR_PBURST 0x00600000U
2897 #define DMA_SxCR_PBURST_0 0x00200000U
2898 #define DMA_SxCR_PBURST_1 0x00400000U
2899 #define DMA_SxCR_CT 0x00080000U
2900 #define DMA_SxCR_DBM 0x00040000U
2901 #define DMA_SxCR_PL 0x00030000U
2902 #define DMA_SxCR_PL_0 0x00010000U
2903 #define DMA_SxCR_PL_1 0x00020000U
2904 #define DMA_SxCR_PINCOS 0x00008000U
2905 #define DMA_SxCR_MSIZE 0x00006000U
2906 #define DMA_SxCR_MSIZE_0 0x00002000U
2907 #define DMA_SxCR_MSIZE_1 0x00004000U
2908 #define DMA_SxCR_PSIZE 0x00001800U
2909 #define DMA_SxCR_PSIZE_0 0x00000800U
2910 #define DMA_SxCR_PSIZE_1 0x00001000U
2911 #define DMA_SxCR_MINC 0x00000400U
2912 #define DMA_SxCR_PINC 0x00000200U
2913 #define DMA_SxCR_CIRC 0x00000100U
2914 #define DMA_SxCR_DIR 0x000000C0U
2915 #define DMA_SxCR_DIR_0 0x00000040U
2916 #define DMA_SxCR_DIR_1 0x00000080U
2917 #define DMA_SxCR_PFCTRL 0x00000020U
2918 #define DMA_SxCR_TCIE 0x00000010U
2919 #define DMA_SxCR_HTIE 0x00000008U
2920 #define DMA_SxCR_TEIE 0x00000004U
2921 #define DMA_SxCR_DMEIE 0x00000002U
2922 #define DMA_SxCR_EN 0x00000001U
2923 
2924 /* Legacy defines */
2925 #define DMA_SxCR_ACK 0x00100000U
2926 
2927 /******************** Bits definition for DMA_SxCNDTR register **************/
2928 #define DMA_SxNDT 0x0000FFFFU
2929 #define DMA_SxNDT_0 0x00000001U
2930 #define DMA_SxNDT_1 0x00000002U
2931 #define DMA_SxNDT_2 0x00000004U
2932 #define DMA_SxNDT_3 0x00000008U
2933 #define DMA_SxNDT_4 0x00000010U
2934 #define DMA_SxNDT_5 0x00000020U
2935 #define DMA_SxNDT_6 0x00000040U
2936 #define DMA_SxNDT_7 0x00000080U
2937 #define DMA_SxNDT_8 0x00000100U
2938 #define DMA_SxNDT_9 0x00000200U
2939 #define DMA_SxNDT_10 0x00000400U
2940 #define DMA_SxNDT_11 0x00000800U
2941 #define DMA_SxNDT_12 0x00001000U
2942 #define DMA_SxNDT_13 0x00002000U
2943 #define DMA_SxNDT_14 0x00004000U
2944 #define DMA_SxNDT_15 0x00008000U
2945 
2946 /******************** Bits definition for DMA_SxFCR register ****************/
2947 #define DMA_SxFCR_FEIE 0x00000080U
2948 #define DMA_SxFCR_FS 0x00000038U
2949 #define DMA_SxFCR_FS_0 0x00000008U
2950 #define DMA_SxFCR_FS_1 0x00000010U
2951 #define DMA_SxFCR_FS_2 0x00000020U
2952 #define DMA_SxFCR_DMDIS 0x00000004U
2953 #define DMA_SxFCR_FTH 0x00000003U
2954 #define DMA_SxFCR_FTH_0 0x00000001U
2955 #define DMA_SxFCR_FTH_1 0x00000002U
2956 
2957 /******************** Bits definition for DMA_LISR register *****************/
2958 #define DMA_LISR_TCIF3 0x08000000U
2959 #define DMA_LISR_HTIF3 0x04000000U
2960 #define DMA_LISR_TEIF3 0x02000000U
2961 #define DMA_LISR_DMEIF3 0x01000000U
2962 #define DMA_LISR_FEIF3 0x00400000U
2963 #define DMA_LISR_TCIF2 0x00200000U
2964 #define DMA_LISR_HTIF2 0x00100000U
2965 #define DMA_LISR_TEIF2 0x00080000U
2966 #define DMA_LISR_DMEIF2 0x00040000U
2967 #define DMA_LISR_FEIF2 0x00010000U
2968 #define DMA_LISR_TCIF1 0x00000800U
2969 #define DMA_LISR_HTIF1 0x00000400U
2970 #define DMA_LISR_TEIF1 0x00000200U
2971 #define DMA_LISR_DMEIF1 0x00000100U
2972 #define DMA_LISR_FEIF1 0x00000040U
2973 #define DMA_LISR_TCIF0 0x00000020U
2974 #define DMA_LISR_HTIF0 0x00000010U
2975 #define DMA_LISR_TEIF0 0x00000008U
2976 #define DMA_LISR_DMEIF0 0x00000004U
2977 #define DMA_LISR_FEIF0 0x00000001U
2978 
2979 /******************** Bits definition for DMA_HISR register *****************/
2980 #define DMA_HISR_TCIF7 0x08000000U
2981 #define DMA_HISR_HTIF7 0x04000000U
2982 #define DMA_HISR_TEIF7 0x02000000U
2983 #define DMA_HISR_DMEIF7 0x01000000U
2984 #define DMA_HISR_FEIF7 0x00400000U
2985 #define DMA_HISR_TCIF6 0x00200000U
2986 #define DMA_HISR_HTIF6 0x00100000U
2987 #define DMA_HISR_TEIF6 0x00080000U
2988 #define DMA_HISR_DMEIF6 0x00040000U
2989 #define DMA_HISR_FEIF6 0x00010000U
2990 #define DMA_HISR_TCIF5 0x00000800U
2991 #define DMA_HISR_HTIF5 0x00000400U
2992 #define DMA_HISR_TEIF5 0x00000200U
2993 #define DMA_HISR_DMEIF5 0x00000100U
2994 #define DMA_HISR_FEIF5 0x00000040U
2995 #define DMA_HISR_TCIF4 0x00000020U
2996 #define DMA_HISR_HTIF4 0x00000010U
2997 #define DMA_HISR_TEIF4 0x00000008U
2998 #define DMA_HISR_DMEIF4 0x00000004U
2999 #define DMA_HISR_FEIF4 0x00000001U
3000 
3001 /******************** Bits definition for DMA_LIFCR register ****************/
3002 #define DMA_LIFCR_CTCIF3 0x08000000U
3003 #define DMA_LIFCR_CHTIF3 0x04000000U
3004 #define DMA_LIFCR_CTEIF3 0x02000000U
3005 #define DMA_LIFCR_CDMEIF3 0x01000000U
3006 #define DMA_LIFCR_CFEIF3 0x00400000U
3007 #define DMA_LIFCR_CTCIF2 0x00200000U
3008 #define DMA_LIFCR_CHTIF2 0x00100000U
3009 #define DMA_LIFCR_CTEIF2 0x00080000U
3010 #define DMA_LIFCR_CDMEIF2 0x00040000U
3011 #define DMA_LIFCR_CFEIF2 0x00010000U
3012 #define DMA_LIFCR_CTCIF1 0x00000800U
3013 #define DMA_LIFCR_CHTIF1 0x00000400U
3014 #define DMA_LIFCR_CTEIF1 0x00000200U
3015 #define DMA_LIFCR_CDMEIF1 0x00000100U
3016 #define DMA_LIFCR_CFEIF1 0x00000040U
3017 #define DMA_LIFCR_CTCIF0 0x00000020U
3018 #define DMA_LIFCR_CHTIF0 0x00000010U
3019 #define DMA_LIFCR_CTEIF0 0x00000008U
3020 #define DMA_LIFCR_CDMEIF0 0x00000004U
3021 #define DMA_LIFCR_CFEIF0 0x00000001U
3022 
3023 /******************** Bits definition for DMA_HIFCR register ****************/
3024 #define DMA_HIFCR_CTCIF7 0x08000000U
3025 #define DMA_HIFCR_CHTIF7 0x04000000U
3026 #define DMA_HIFCR_CTEIF7 0x02000000U
3027 #define DMA_HIFCR_CDMEIF7 0x01000000U
3028 #define DMA_HIFCR_CFEIF7 0x00400000U
3029 #define DMA_HIFCR_CTCIF6 0x00200000U
3030 #define DMA_HIFCR_CHTIF6 0x00100000U
3031 #define DMA_HIFCR_CTEIF6 0x00080000U
3032 #define DMA_HIFCR_CDMEIF6 0x00040000U
3033 #define DMA_HIFCR_CFEIF6 0x00010000U
3034 #define DMA_HIFCR_CTCIF5 0x00000800U
3035 #define DMA_HIFCR_CHTIF5 0x00000400U
3036 #define DMA_HIFCR_CTEIF5 0x00000200U
3037 #define DMA_HIFCR_CDMEIF5 0x00000100U
3038 #define DMA_HIFCR_CFEIF5 0x00000040U
3039 #define DMA_HIFCR_CTCIF4 0x00000020U
3040 #define DMA_HIFCR_CHTIF4 0x00000010U
3041 #define DMA_HIFCR_CTEIF4 0x00000008U
3042 #define DMA_HIFCR_CDMEIF4 0x00000004U
3043 #define DMA_HIFCR_CFEIF4 0x00000001U
3044 
3045 
3046 /******************************************************************************/
3047 /* */
3048 /* External Interrupt/Event Controller */
3049 /* */
3050 /******************************************************************************/
3051 /******************* Bit definition for EXTI_IMR register *******************/
3052 #define EXTI_IMR_MR0 0x00000001U
3053 #define EXTI_IMR_MR1 0x00000002U
3054 #define EXTI_IMR_MR2 0x00000004U
3055 #define EXTI_IMR_MR3 0x00000008U
3056 #define EXTI_IMR_MR4 0x00000010U
3057 #define EXTI_IMR_MR5 0x00000020U
3058 #define EXTI_IMR_MR6 0x00000040U
3059 #define EXTI_IMR_MR7 0x00000080U
3060 #define EXTI_IMR_MR8 0x00000100U
3061 #define EXTI_IMR_MR9 0x00000200U
3062 #define EXTI_IMR_MR10 0x00000400U
3063 #define EXTI_IMR_MR11 0x00000800U
3064 #define EXTI_IMR_MR12 0x00001000U
3065 #define EXTI_IMR_MR13 0x00002000U
3066 #define EXTI_IMR_MR14 0x00004000U
3067 #define EXTI_IMR_MR15 0x00008000U
3068 #define EXTI_IMR_MR16 0x00010000U
3069 #define EXTI_IMR_MR17 0x00020000U
3070 #define EXTI_IMR_MR18 0x00040000U
3071 #define EXTI_IMR_MR19 0x00080000U
3072 #define EXTI_IMR_MR20 0x00100000U
3073 #define EXTI_IMR_MR21 0x00200000U
3074 #define EXTI_IMR_MR22 0x00400000U
3076 /******************* Bit definition for EXTI_EMR register *******************/
3077 #define EXTI_EMR_MR0 0x00000001U
3078 #define EXTI_EMR_MR1 0x00000002U
3079 #define EXTI_EMR_MR2 0x00000004U
3080 #define EXTI_EMR_MR3 0x00000008U
3081 #define EXTI_EMR_MR4 0x00000010U
3082 #define EXTI_EMR_MR5 0x00000020U
3083 #define EXTI_EMR_MR6 0x00000040U
3084 #define EXTI_EMR_MR7 0x00000080U
3085 #define EXTI_EMR_MR8 0x00000100U
3086 #define EXTI_EMR_MR9 0x00000200U
3087 #define EXTI_EMR_MR10 0x00000400U
3088 #define EXTI_EMR_MR11 0x00000800U
3089 #define EXTI_EMR_MR12 0x00001000U
3090 #define EXTI_EMR_MR13 0x00002000U
3091 #define EXTI_EMR_MR14 0x00004000U
3092 #define EXTI_EMR_MR15 0x00008000U
3093 #define EXTI_EMR_MR16 0x00010000U
3094 #define EXTI_EMR_MR17 0x00020000U
3095 #define EXTI_EMR_MR18 0x00040000U
3096 #define EXTI_EMR_MR19 0x00080000U
3097 #define EXTI_EMR_MR20 0x00100000U
3098 #define EXTI_EMR_MR21 0x00200000U
3099 #define EXTI_EMR_MR22 0x00400000U
3101 /****************** Bit definition for EXTI_RTSR register *******************/
3102 #define EXTI_RTSR_TR0 0x00000001U
3103 #define EXTI_RTSR_TR1 0x00000002U
3104 #define EXTI_RTSR_TR2 0x00000004U
3105 #define EXTI_RTSR_TR3 0x00000008U
3106 #define EXTI_RTSR_TR4 0x00000010U
3107 #define EXTI_RTSR_TR5 0x00000020U
3108 #define EXTI_RTSR_TR6 0x00000040U
3109 #define EXTI_RTSR_TR7 0x00000080U
3110 #define EXTI_RTSR_TR8 0x00000100U
3111 #define EXTI_RTSR_TR9 0x00000200U
3112 #define EXTI_RTSR_TR10 0x00000400U
3113 #define EXTI_RTSR_TR11 0x00000800U
3114 #define EXTI_RTSR_TR12 0x00001000U
3115 #define EXTI_RTSR_TR13 0x00002000U
3116 #define EXTI_RTSR_TR14 0x00004000U
3117 #define EXTI_RTSR_TR15 0x00008000U
3118 #define EXTI_RTSR_TR16 0x00010000U
3119 #define EXTI_RTSR_TR17 0x00020000U
3120 #define EXTI_RTSR_TR18 0x00040000U
3121 #define EXTI_RTSR_TR19 0x00080000U
3122 #define EXTI_RTSR_TR20 0x00100000U
3123 #define EXTI_RTSR_TR21 0x00200000U
3124 #define EXTI_RTSR_TR22 0x00400000U
3126 /****************** Bit definition for EXTI_FTSR register *******************/
3127 #define EXTI_FTSR_TR0 0x00000001U
3128 #define EXTI_FTSR_TR1 0x00000002U
3129 #define EXTI_FTSR_TR2 0x00000004U
3130 #define EXTI_FTSR_TR3 0x00000008U
3131 #define EXTI_FTSR_TR4 0x00000010U
3132 #define EXTI_FTSR_TR5 0x00000020U
3133 #define EXTI_FTSR_TR6 0x00000040U
3134 #define EXTI_FTSR_TR7 0x00000080U
3135 #define EXTI_FTSR_TR8 0x00000100U
3136 #define EXTI_FTSR_TR9 0x00000200U
3137 #define EXTI_FTSR_TR10 0x00000400U
3138 #define EXTI_FTSR_TR11 0x00000800U
3139 #define EXTI_FTSR_TR12 0x00001000U
3140 #define EXTI_FTSR_TR13 0x00002000U
3141 #define EXTI_FTSR_TR14 0x00004000U
3142 #define EXTI_FTSR_TR15 0x00008000U
3143 #define EXTI_FTSR_TR16 0x00010000U
3144 #define EXTI_FTSR_TR17 0x00020000U
3145 #define EXTI_FTSR_TR18 0x00040000U
3146 #define EXTI_FTSR_TR19 0x00080000U
3147 #define EXTI_FTSR_TR20 0x00100000U
3148 #define EXTI_FTSR_TR21 0x00200000U
3149 #define EXTI_FTSR_TR22 0x00400000U
3151 /****************** Bit definition for EXTI_SWIER register ******************/
3152 #define EXTI_SWIER_SWIER0 0x00000001U
3153 #define EXTI_SWIER_SWIER1 0x00000002U
3154 #define EXTI_SWIER_SWIER2 0x00000004U
3155 #define EXTI_SWIER_SWIER3 0x00000008U
3156 #define EXTI_SWIER_SWIER4 0x00000010U
3157 #define EXTI_SWIER_SWIER5 0x00000020U
3158 #define EXTI_SWIER_SWIER6 0x00000040U
3159 #define EXTI_SWIER_SWIER7 0x00000080U
3160 #define EXTI_SWIER_SWIER8 0x00000100U
3161 #define EXTI_SWIER_SWIER9 0x00000200U
3162 #define EXTI_SWIER_SWIER10 0x00000400U
3163 #define EXTI_SWIER_SWIER11 0x00000800U
3164 #define EXTI_SWIER_SWIER12 0x00001000U
3165 #define EXTI_SWIER_SWIER13 0x00002000U
3166 #define EXTI_SWIER_SWIER14 0x00004000U
3167 #define EXTI_SWIER_SWIER15 0x00008000U
3168 #define EXTI_SWIER_SWIER16 0x00010000U
3169 #define EXTI_SWIER_SWIER17 0x00020000U
3170 #define EXTI_SWIER_SWIER18 0x00040000U
3171 #define EXTI_SWIER_SWIER19 0x00080000U
3172 #define EXTI_SWIER_SWIER20 0x00100000U
3173 #define EXTI_SWIER_SWIER21 0x00200000U
3174 #define EXTI_SWIER_SWIER22 0x00400000U
3176 /******************* Bit definition for EXTI_PR register ********************/
3177 #define EXTI_PR_PR0 0x00000001U
3178 #define EXTI_PR_PR1 0x00000002U
3179 #define EXTI_PR_PR2 0x00000004U
3180 #define EXTI_PR_PR3 0x00000008U
3181 #define EXTI_PR_PR4 0x00000010U
3182 #define EXTI_PR_PR5 0x00000020U
3183 #define EXTI_PR_PR6 0x00000040U
3184 #define EXTI_PR_PR7 0x00000080U
3185 #define EXTI_PR_PR8 0x00000100U
3186 #define EXTI_PR_PR9 0x00000200U
3187 #define EXTI_PR_PR10 0x00000400U
3188 #define EXTI_PR_PR11 0x00000800U
3189 #define EXTI_PR_PR12 0x00001000U
3190 #define EXTI_PR_PR13 0x00002000U
3191 #define EXTI_PR_PR14 0x00004000U
3192 #define EXTI_PR_PR15 0x00008000U
3193 #define EXTI_PR_PR16 0x00010000U
3194 #define EXTI_PR_PR17 0x00020000U
3195 #define EXTI_PR_PR18 0x00040000U
3196 #define EXTI_PR_PR19 0x00080000U
3197 #define EXTI_PR_PR20 0x00100000U
3198 #define EXTI_PR_PR21 0x00200000U
3199 #define EXTI_PR_PR22 0x00400000U
3201 /******************************************************************************/
3202 /* */
3203 /* FLASH */
3204 /* */
3205 /******************************************************************************/
3206 /******************* Bits definition for FLASH_ACR register *****************/
3207 #define FLASH_ACR_LATENCY 0x0000000FU
3208 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3209 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3210 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3211 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3212 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3213 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3214 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3215 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3216 
3217 #define FLASH_ACR_PRFTEN 0x00000100U
3218 #define FLASH_ACR_ICEN 0x00000200U
3219 #define FLASH_ACR_DCEN 0x00000400U
3220 #define FLASH_ACR_ICRST 0x00000800U
3221 #define FLASH_ACR_DCRST 0x00001000U
3222 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3223 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3224 
3225 /******************* Bits definition for FLASH_SR register ******************/
3226 #define FLASH_SR_EOP 0x00000001U
3227 #define FLASH_SR_SOP 0x00000002U
3228 #define FLASH_SR_WRPERR 0x00000010U
3229 #define FLASH_SR_PGAERR 0x00000020U
3230 #define FLASH_SR_PGPERR 0x00000040U
3231 #define FLASH_SR_PGSERR 0x00000080U
3232 #define FLASH_SR_BSY 0x00010000U
3233 
3234 /******************* Bits definition for FLASH_CR register ******************/
3235 #define FLASH_CR_PG 0x00000001U
3236 #define FLASH_CR_SER 0x00000002U
3237 #define FLASH_CR_MER 0x00000004U
3238 #define FLASH_CR_SNB 0x000000F8U
3239 #define FLASH_CR_SNB_0 0x00000008U
3240 #define FLASH_CR_SNB_1 0x00000010U
3241 #define FLASH_CR_SNB_2 0x00000020U
3242 #define FLASH_CR_SNB_3 0x00000040U
3243 #define FLASH_CR_SNB_4 0x00000080U
3244 #define FLASH_CR_PSIZE 0x00000300U
3245 #define FLASH_CR_PSIZE_0 0x00000100U
3246 #define FLASH_CR_PSIZE_1 0x00000200U
3247 #define FLASH_CR_STRT 0x00010000U
3248 #define FLASH_CR_EOPIE 0x01000000U
3249 #define FLASH_CR_LOCK 0x80000000U
3250 
3251 /******************* Bits definition for FLASH_OPTCR register ***************/
3252 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3253 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3254 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3255 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3256 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3257 
3258 #define FLASH_OPTCR_WDG_SW 0x00000020U
3259 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3260 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3261 #define FLASH_OPTCR_RDP 0x0000FF00U
3262 #define FLASH_OPTCR_RDP_0 0x00000100U
3263 #define FLASH_OPTCR_RDP_1 0x00000200U
3264 #define FLASH_OPTCR_RDP_2 0x00000400U
3265 #define FLASH_OPTCR_RDP_3 0x00000800U
3266 #define FLASH_OPTCR_RDP_4 0x00001000U
3267 #define FLASH_OPTCR_RDP_5 0x00002000U
3268 #define FLASH_OPTCR_RDP_6 0x00004000U
3269 #define FLASH_OPTCR_RDP_7 0x00008000U
3270 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3271 #define FLASH_OPTCR_nWRP_0 0x00010000U
3272 #define FLASH_OPTCR_nWRP_1 0x00020000U
3273 #define FLASH_OPTCR_nWRP_2 0x00040000U
3274 #define FLASH_OPTCR_nWRP_3 0x00080000U
3275 #define FLASH_OPTCR_nWRP_4 0x00100000U
3276 #define FLASH_OPTCR_nWRP_5 0x00200000U
3277 #define FLASH_OPTCR_nWRP_6 0x00400000U
3278 #define FLASH_OPTCR_nWRP_7 0x00800000U
3279 #define FLASH_OPTCR_nWRP_8 0x01000000U
3280 #define FLASH_OPTCR_nWRP_9 0x02000000U
3281 #define FLASH_OPTCR_nWRP_10 0x04000000U
3282 #define FLASH_OPTCR_nWRP_11 0x08000000U
3283 
3284 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3285 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3286 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3287 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3288 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3289 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3290 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3291 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3292 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3293 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3294 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3295 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3296 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3297 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3298 
3299 /******************************************************************************/
3300 /* */
3301 /* Flexible Static Memory Controller */
3302 /* */
3303 /******************************************************************************/
3304 /****************** Bit definition for FSMC_BCR1 register *******************/
3305 #define FSMC_BCR1_MBKEN 0x00000001U
3306 #define FSMC_BCR1_MUXEN 0x00000002U
3308 #define FSMC_BCR1_MTYP 0x0000000CU
3309 #define FSMC_BCR1_MTYP_0 0x00000004U
3310 #define FSMC_BCR1_MTYP_1 0x00000008U
3312 #define FSMC_BCR1_MWID 0x00000030U
3313 #define FSMC_BCR1_MWID_0 0x00000010U
3314 #define FSMC_BCR1_MWID_1 0x00000020U
3316 #define FSMC_BCR1_FACCEN 0x00000040U
3317 #define FSMC_BCR1_BURSTEN 0x00000100U
3318 #define FSMC_BCR1_WAITPOL 0x00000200U
3319 #define FSMC_BCR1_WRAPMOD 0x00000400U
3320 #define FSMC_BCR1_WAITCFG 0x00000800U
3321 #define FSMC_BCR1_WREN 0x00001000U
3322 #define FSMC_BCR1_WAITEN 0x00002000U
3323 #define FSMC_BCR1_EXTMOD 0x00004000U
3324 #define FSMC_BCR1_ASYNCWAIT 0x00008000U
3325 #define FSMC_BCR1_CPSIZE 0x00070000U
3326 #define FSMC_BCR1_CPSIZE_0 0x00010000U
3327 #define FSMC_BCR1_CPSIZE_1 0x00020000U
3328 #define FSMC_BCR1_CPSIZE_2 0x00040000U
3329 #define FSMC_BCR1_CBURSTRW 0x00080000U
3331 /****************** Bit definition for FSMC_BCR2 register *******************/
3332 #define FSMC_BCR2_MBKEN 0x00000001U
3333 #define FSMC_BCR2_MUXEN 0x00000002U
3335 #define FSMC_BCR2_MTYP 0x0000000CU
3336 #define FSMC_BCR2_MTYP_0 0x00000004U
3337 #define FSMC_BCR2_MTYP_1 0x00000008U
3339 #define FSMC_BCR2_MWID 0x00000030U
3340 #define FSMC_BCR2_MWID_0 0x00000010U
3341 #define FSMC_BCR2_MWID_1 0x00000020U
3343 #define FSMC_BCR2_FACCEN 0x00000040U
3344 #define FSMC_BCR2_BURSTEN 0x00000100U
3345 #define FSMC_BCR2_WAITPOL 0x00000200U
3346 #define FSMC_BCR2_WRAPMOD 0x00000400U
3347 #define FSMC_BCR2_WAITCFG 0x00000800U
3348 #define FSMC_BCR2_WREN 0x00001000U
3349 #define FSMC_BCR2_WAITEN 0x00002000U
3350 #define FSMC_BCR2_EXTMOD 0x00004000U
3351 #define FSMC_BCR2_ASYNCWAIT 0x00008000U
3352 #define FSMC_BCR2_CPSIZE 0x00070000U
3353 #define FSMC_BCR2_CPSIZE_0 0x00010000U
3354 #define FSMC_BCR2_CPSIZE_1 0x00020000U
3355 #define FSMC_BCR2_CPSIZE_2 0x00040000U
3356 #define FSMC_BCR2_CBURSTRW 0x00080000U
3358 /****************** Bit definition for FSMC_BCR3 register *******************/
3359 #define FSMC_BCR3_MBKEN 0x00000001U
3360 #define FSMC_BCR3_MUXEN 0x00000002U
3362 #define FSMC_BCR3_MTYP 0x0000000CU
3363 #define FSMC_BCR3_MTYP_0 0x00000004U
3364 #define FSMC_BCR3_MTYP_1 0x00000008U
3366 #define FSMC_BCR3_MWID 0x00000030U
3367 #define FSMC_BCR3_MWID_0 0x00000010U
3368 #define FSMC_BCR3_MWID_1 0x00000020U
3370 #define FSMC_BCR3_FACCEN 0x00000040U
3371 #define FSMC_BCR3_BURSTEN 0x00000100U
3372 #define FSMC_BCR3_WAITPOL 0x00000200U
3373 #define FSMC_BCR3_WRAPMOD 0x00000400U
3374 #define FSMC_BCR3_WAITCFG 0x00000800U
3375 #define FSMC_BCR3_WREN 0x00001000U
3376 #define FSMC_BCR3_WAITEN 0x00002000U
3377 #define FSMC_BCR3_EXTMOD 0x00004000U
3378 #define FSMC_BCR3_ASYNCWAIT 0x00008000U
3379 #define FSMC_BCR3_CPSIZE 0x00070000U
3380 #define FSMC_BCR3_CPSIZE_0 0x00010000U
3381 #define FSMC_BCR3_CPSIZE_1 0x00020000U
3382 #define FSMC_BCR3_CPSIZE_2 0x00040000U
3383 #define FSMC_BCR3_CBURSTRW 0x00080000U
3385 /****************** Bit definition for FSMC_BCR4 register *******************/
3386 #define FSMC_BCR4_MBKEN 0x00000001U
3387 #define FSMC_BCR4_MUXEN 0x00000002U
3389 #define FSMC_BCR4_MTYP 0x0000000CU
3390 #define FSMC_BCR4_MTYP_0 0x00000004U
3391 #define FSMC_BCR4_MTYP_1 0x00000008U
3393 #define FSMC_BCR4_MWID 0x00000030U
3394 #define FSMC_BCR4_MWID_0 0x00000010U
3395 #define FSMC_BCR4_MWID_1 0x00000020U
3397 #define FSMC_BCR4_FACCEN 0x00000040U
3398 #define FSMC_BCR4_BURSTEN 0x00000100U
3399 #define FSMC_BCR4_WAITPOL 0x00000200U
3400 #define FSMC_BCR4_WRAPMOD 0x00000400U
3401 #define FSMC_BCR4_WAITCFG 0x00000800U
3402 #define FSMC_BCR4_WREN 0x00001000U
3403 #define FSMC_BCR4_WAITEN 0x00002000U
3404 #define FSMC_BCR4_EXTMOD 0x00004000U
3405 #define FSMC_BCR4_ASYNCWAIT 0x00008000U
3406 #define FSMC_BCR4_CPSIZE 0x00070000U
3407 #define FSMC_BCR4_CPSIZE_0 0x00010000U
3408 #define FSMC_BCR4_CPSIZE_1 0x00020000U
3409 #define FSMC_BCR4_CPSIZE_2 0x00040000U
3410 #define FSMC_BCR4_CBURSTRW 0x00080000U
3412 /****************** Bit definition for FSMC_BTR1 register ******************/
3413 #define FSMC_BTR1_ADDSET 0x0000000FU
3414 #define FSMC_BTR1_ADDSET_0 0x00000001U
3415 #define FSMC_BTR1_ADDSET_1 0x00000002U
3416 #define FSMC_BTR1_ADDSET_2 0x00000004U
3417 #define FSMC_BTR1_ADDSET_3 0x00000008U
3419 #define FSMC_BTR1_ADDHLD 0x000000F0U
3420 #define FSMC_BTR1_ADDHLD_0 0x00000010U
3421 #define FSMC_BTR1_ADDHLD_1 0x00000020U
3422 #define FSMC_BTR1_ADDHLD_2 0x00000040U
3423 #define FSMC_BTR1_ADDHLD_3 0x00000080U
3425 #define FSMC_BTR1_DATAST 0x0000FF00U
3426 #define FSMC_BTR1_DATAST_0 0x00000100U
3427 #define FSMC_BTR1_DATAST_1 0x00000200U
3428 #define FSMC_BTR1_DATAST_2 0x00000400U
3429 #define FSMC_BTR1_DATAST_3 0x00000800U
3430 #define FSMC_BTR1_DATAST_4 0x00001000U
3431 #define FSMC_BTR1_DATAST_5 0x00002000U
3432 #define FSMC_BTR1_DATAST_6 0x00004000U
3433 #define FSMC_BTR1_DATAST_7 0x00008000U
3435 #define FSMC_BTR1_BUSTURN 0x000F0000U
3436 #define FSMC_BTR1_BUSTURN_0 0x00010000U
3437 #define FSMC_BTR1_BUSTURN_1 0x00020000U
3438 #define FSMC_BTR1_BUSTURN_2 0x00040000U
3439 #define FSMC_BTR1_BUSTURN_3 0x00080000U
3441 #define FSMC_BTR1_CLKDIV 0x00F00000U
3442 #define FSMC_BTR1_CLKDIV_0 0x00100000U
3443 #define FSMC_BTR1_CLKDIV_1 0x00200000U
3444 #define FSMC_BTR1_CLKDIV_2 0x00400000U
3445 #define FSMC_BTR1_CLKDIV_3 0x00800000U
3447 #define FSMC_BTR1_DATLAT 0x0F000000U
3448 #define FSMC_BTR1_DATLAT_0 0x01000000U
3449 #define FSMC_BTR1_DATLAT_1 0x02000000U
3450 #define FSMC_BTR1_DATLAT_2 0x04000000U
3451 #define FSMC_BTR1_DATLAT_3 0x08000000U
3453 #define FSMC_BTR1_ACCMOD 0x30000000U
3454 #define FSMC_BTR1_ACCMOD_0 0x10000000U
3455 #define FSMC_BTR1_ACCMOD_1 0x20000000U
3457 /****************** Bit definition for FSMC_BTR2 register *******************/
3458 #define FSMC_BTR2_ADDSET 0x0000000FU
3459 #define FSMC_BTR2_ADDSET_0 0x00000001U
3460 #define FSMC_BTR2_ADDSET_1 0x00000002U
3461 #define FSMC_BTR2_ADDSET_2 0x00000004U
3462 #define FSMC_BTR2_ADDSET_3 0x00000008U
3464 #define FSMC_BTR2_ADDHLD 0x000000F0U
3465 #define FSMC_BTR2_ADDHLD_0 0x00000010U
3466 #define FSMC_BTR2_ADDHLD_1 0x00000020U
3467 #define FSMC_BTR2_ADDHLD_2 0x00000040U
3468 #define FSMC_BTR2_ADDHLD_3 0x00000080U
3470 #define FSMC_BTR2_DATAST 0x0000FF00U
3471 #define FSMC_BTR2_DATAST_0 0x00000100U
3472 #define FSMC_BTR2_DATAST_1 0x00000200U
3473 #define FSMC_BTR2_DATAST_2 0x00000400U
3474 #define FSMC_BTR2_DATAST_3 0x00000800U
3475 #define FSMC_BTR2_DATAST_4 0x00001000U
3476 #define FSMC_BTR2_DATAST_5 0x00002000U
3477 #define FSMC_BTR2_DATAST_6 0x00004000U
3478 #define FSMC_BTR2_DATAST_7 0x00008000U
3480 #define FSMC_BTR2_BUSTURN 0x000F0000U
3481 #define FSMC_BTR2_BUSTURN_0 0x00010000U
3482 #define FSMC_BTR2_BUSTURN_1 0x00020000U
3483 #define FSMC_BTR2_BUSTURN_2 0x00040000U
3484 #define FSMC_BTR2_BUSTURN_3 0x00080000U
3486 #define FSMC_BTR2_CLKDIV 0x00F00000U
3487 #define FSMC_BTR2_CLKDIV_0 0x00100000U
3488 #define FSMC_BTR2_CLKDIV_1 0x00200000U
3489 #define FSMC_BTR2_CLKDIV_2 0x00400000U
3490 #define FSMC_BTR2_CLKDIV_3 0x00800000U
3492 #define FSMC_BTR2_DATLAT 0x0F000000U
3493 #define FSMC_BTR2_DATLAT_0 0x01000000U
3494 #define FSMC_BTR2_DATLAT_1 0x02000000U
3495 #define FSMC_BTR2_DATLAT_2 0x04000000U
3496 #define FSMC_BTR2_DATLAT_3 0x08000000U
3498 #define FSMC_BTR2_ACCMOD 0x30000000U
3499 #define FSMC_BTR2_ACCMOD_0 0x10000000U
3500 #define FSMC_BTR2_ACCMOD_1 0x20000000U
3502 /******************* Bit definition for FSMC_BTR3 register *******************/
3503 #define FSMC_BTR3_ADDSET 0x0000000FU
3504 #define FSMC_BTR3_ADDSET_0 0x00000001U
3505 #define FSMC_BTR3_ADDSET_1 0x00000002U
3506 #define FSMC_BTR3_ADDSET_2 0x00000004U
3507 #define FSMC_BTR3_ADDSET_3 0x00000008U
3509 #define FSMC_BTR3_ADDHLD 0x000000F0U
3510 #define FSMC_BTR3_ADDHLD_0 0x00000010U
3511 #define FSMC_BTR3_ADDHLD_1 0x00000020U
3512 #define FSMC_BTR3_ADDHLD_2 0x00000040U
3513 #define FSMC_BTR3_ADDHLD_3 0x00000080U
3515 #define FSMC_BTR3_DATAST 0x0000FF00U
3516 #define FSMC_BTR3_DATAST_0 0x00000100U
3517 #define FSMC_BTR3_DATAST_1 0x00000200U
3518 #define FSMC_BTR3_DATAST_2 0x00000400U
3519 #define FSMC_BTR3_DATAST_3 0x00000800U
3520 #define FSMC_BTR3_DATAST_4 0x00001000U
3521 #define FSMC_BTR3_DATAST_5 0x00002000U
3522 #define FSMC_BTR3_DATAST_6 0x00004000U
3523 #define FSMC_BTR3_DATAST_7 0x00008000U
3525 #define FSMC_BTR3_BUSTURN 0x000F0000U
3526 #define FSMC_BTR3_BUSTURN_0 0x00010000U
3527 #define FSMC_BTR3_BUSTURN_1 0x00020000U
3528 #define FSMC_BTR3_BUSTURN_2 0x00040000U
3529 #define FSMC_BTR3_BUSTURN_3 0x00080000U
3531 #define FSMC_BTR3_CLKDIV 0x00F00000U
3532 #define FSMC_BTR3_CLKDIV_0 0x00100000U
3533 #define FSMC_BTR3_CLKDIV_1 0x00200000U
3534 #define FSMC_BTR3_CLKDIV_2 0x00400000U
3535 #define FSMC_BTR3_CLKDIV_3 0x00800000U
3537 #define FSMC_BTR3_DATLAT 0x0F000000U
3538 #define FSMC_BTR3_DATLAT_0 0x01000000U
3539 #define FSMC_BTR3_DATLAT_1 0x02000000U
3540 #define FSMC_BTR3_DATLAT_2 0x04000000U
3541 #define FSMC_BTR3_DATLAT_3 0x08000000U
3543 #define FSMC_BTR3_ACCMOD 0x30000000U
3544 #define FSMC_BTR3_ACCMOD_0 0x10000000U
3545 #define FSMC_BTR3_ACCMOD_1 0x20000000U
3547 /****************** Bit definition for FSMC_BTR4 register *******************/
3548 #define FSMC_BTR4_ADDSET 0x0000000FU
3549 #define FSMC_BTR4_ADDSET_0 0x00000001U
3550 #define FSMC_BTR4_ADDSET_1 0x00000002U
3551 #define FSMC_BTR4_ADDSET_2 0x00000004U
3552 #define FSMC_BTR4_ADDSET_3 0x00000008U
3554 #define FSMC_BTR4_ADDHLD 0x000000F0U
3555 #define FSMC_BTR4_ADDHLD_0 0x00000010U
3556 #define FSMC_BTR4_ADDHLD_1 0x00000020U
3557 #define FSMC_BTR4_ADDHLD_2 0x00000040U
3558 #define FSMC_BTR4_ADDHLD_3 0x00000080U
3560 #define FSMC_BTR4_DATAST 0x0000FF00U
3561 #define FSMC_BTR4_DATAST_0 0x00000100U
3562 #define FSMC_BTR4_DATAST_1 0x00000200U
3563 #define FSMC_BTR4_DATAST_2 0x00000400U
3564 #define FSMC_BTR4_DATAST_3 0x00000800U
3565 #define FSMC_BTR4_DATAST_4 0x00001000U
3566 #define FSMC_BTR4_DATAST_5 0x00002000U
3567 #define FSMC_BTR4_DATAST_6 0x00004000U
3568 #define FSMC_BTR4_DATAST_7 0x00008000U
3570 #define FSMC_BTR4_BUSTURN 0x000F0000U
3571 #define FSMC_BTR4_BUSTURN_0 0x00010000U
3572 #define FSMC_BTR4_BUSTURN_1 0x00020000U
3573 #define FSMC_BTR4_BUSTURN_2 0x00040000U
3574 #define FSMC_BTR4_BUSTURN_3 0x00080000U
3576 #define FSMC_BTR4_CLKDIV 0x00F00000U
3577 #define FSMC_BTR4_CLKDIV_0 0x00100000U
3578 #define FSMC_BTR4_CLKDIV_1 0x00200000U
3579 #define FSMC_BTR4_CLKDIV_2 0x00400000U
3580 #define FSMC_BTR4_CLKDIV_3 0x00800000U
3582 #define FSMC_BTR4_DATLAT 0x0F000000U
3583 #define FSMC_BTR4_DATLAT_0 0x01000000U
3584 #define FSMC_BTR4_DATLAT_1 0x02000000U
3585 #define FSMC_BTR4_DATLAT_2 0x04000000U
3586 #define FSMC_BTR4_DATLAT_3 0x08000000U
3588 #define FSMC_BTR4_ACCMOD 0x30000000U
3589 #define FSMC_BTR4_ACCMOD_0 0x10000000U
3590 #define FSMC_BTR4_ACCMOD_1 0x20000000U
3592 /****************** Bit definition for FSMC_BWTR1 register ******************/
3593 #define FSMC_BWTR1_ADDSET 0x0000000FU
3594 #define FSMC_BWTR1_ADDSET_0 0x00000001U
3595 #define FSMC_BWTR1_ADDSET_1 0x00000002U
3596 #define FSMC_BWTR1_ADDSET_2 0x00000004U
3597 #define FSMC_BWTR1_ADDSET_3 0x00000008U
3599 #define FSMC_BWTR1_ADDHLD 0x000000F0U
3600 #define FSMC_BWTR1_ADDHLD_0 0x00000010U
3601 #define FSMC_BWTR1_ADDHLD_1 0x00000020U
3602 #define FSMC_BWTR1_ADDHLD_2 0x00000040U
3603 #define FSMC_BWTR1_ADDHLD_3 0x00000080U
3605 #define FSMC_BWTR1_DATAST 0x0000FF00U
3606 #define FSMC_BWTR1_DATAST_0 0x00000100U
3607 #define FSMC_BWTR1_DATAST_1 0x00000200U
3608 #define FSMC_BWTR1_DATAST_2 0x00000400U
3609 #define FSMC_BWTR1_DATAST_3 0x00000800U
3610 #define FSMC_BWTR1_DATAST_4 0x00001000U
3611 #define FSMC_BWTR1_DATAST_5 0x00002000U
3612 #define FSMC_BWTR1_DATAST_6 0x00004000U
3613 #define FSMC_BWTR1_DATAST_7 0x00008000U
3615 #define FSMC_BWTR1_BUSTURN 0x000F0000U
3616 #define FSMC_BWTR1_BUSTURN_0 0x00010000U
3617 #define FSMC_BWTR1_BUSTURN_1 0x00020000U
3618 #define FSMC_BWTR1_BUSTURN_2 0x00040000U
3619 #define FSMC_BWTR1_BUSTURN_3 0x00080000U
3621 #define FSMC_BWTR1_ACCMOD 0x30000000U
3622 #define FSMC_BWTR1_ACCMOD_0 0x10000000U
3623 #define FSMC_BWTR1_ACCMOD_1 0x20000000U
3625 /****************** Bit definition for FSMC_BWTR2 register ******************/
3626 #define FSMC_BWTR2_ADDSET 0x0000000FU
3627 #define FSMC_BWTR2_ADDSET_0 0x00000001U
3628 #define FSMC_BWTR2_ADDSET_1 0x00000002U
3629 #define FSMC_BWTR2_ADDSET_2 0x00000004U
3630 #define FSMC_BWTR2_ADDSET_3 0x00000008U
3632 #define FSMC_BWTR2_ADDHLD 0x000000F0U
3633 #define FSMC_BWTR2_ADDHLD_0 0x00000010U
3634 #define FSMC_BWTR2_ADDHLD_1 0x00000020U
3635 #define FSMC_BWTR2_ADDHLD_2 0x00000040U
3636 #define FSMC_BWTR2_ADDHLD_3 0x00000080U
3638 #define FSMC_BWTR2_DATAST 0x0000FF00U
3639 #define FSMC_BWTR2_DATAST_0 0x00000100U
3640 #define FSMC_BWTR2_DATAST_1 0x00000200U
3641 #define FSMC_BWTR2_DATAST_2 0x00000400U
3642 #define FSMC_BWTR2_DATAST_3 0x00000800U
3643 #define FSMC_BWTR2_DATAST_4 0x00001000U
3644 #define FSMC_BWTR2_DATAST_5 0x00002000U
3645 #define FSMC_BWTR2_DATAST_6 0x00004000U
3646 #define FSMC_BWTR2_DATAST_7 0x00008000U
3648 #define FSMC_BWTR2_BUSTURN 0x000F0000U
3649 #define FSMC_BWTR2_BUSTURN_0 0x00010000U
3650 #define FSMC_BWTR2_BUSTURN_1 0x00020000U
3651 #define FSMC_BWTR2_BUSTURN_2 0x00040000U
3652 #define FSMC_BWTR2_BUSTURN_3 0x00080000U
3654 #define FSMC_BWTR2_ACCMOD 0x30000000U
3655 #define FSMC_BWTR2_ACCMOD_0 0x10000000U
3656 #define FSMC_BWTR2_ACCMOD_1 0x20000000U
3658 /****************** Bit definition for FSMC_BWTR3 register ******************/
3659 #define FSMC_BWTR3_ADDSET 0x0000000FU
3660 #define FSMC_BWTR3_ADDSET_0 0x00000001U
3661 #define FSMC_BWTR3_ADDSET_1 0x00000002U
3662 #define FSMC_BWTR3_ADDSET_2 0x00000004U
3663 #define FSMC_BWTR3_ADDSET_3 0x00000008U
3665 #define FSMC_BWTR3_ADDHLD 0x000000F0U
3666 #define FSMC_BWTR3_ADDHLD_0 0x00000010U
3667 #define FSMC_BWTR3_ADDHLD_1 0x00000020U
3668 #define FSMC_BWTR3_ADDHLD_2 0x00000040U
3669 #define FSMC_BWTR3_ADDHLD_3 0x00000080U
3671 #define FSMC_BWTR3_DATAST 0x0000FF00U
3672 #define FSMC_BWTR3_DATAST_0 0x00000100U
3673 #define FSMC_BWTR3_DATAST_1 0x00000200U
3674 #define FSMC_BWTR3_DATAST_2 0x00000400U
3675 #define FSMC_BWTR3_DATAST_3 0x00000800U
3676 #define FSMC_BWTR3_DATAST_4 0x00001000U
3677 #define FSMC_BWTR3_DATAST_5 0x00002000U
3678 #define FSMC_BWTR3_DATAST_6 0x00004000U
3679 #define FSMC_BWTR3_DATAST_7 0x00008000U
3681 #define FSMC_BWTR3_BUSTURN 0x000F0000U
3682 #define FSMC_BWTR3_BUSTURN_0 0x00010000U
3683 #define FSMC_BWTR3_BUSTURN_1 0x00020000U
3684 #define FSMC_BWTR3_BUSTURN_2 0x00040000U
3685 #define FSMC_BWTR3_BUSTURN_3 0x00080000U
3687 #define FSMC_BWTR3_ACCMOD 0x30000000U
3688 #define FSMC_BWTR3_ACCMOD_0 0x10000000U
3689 #define FSMC_BWTR3_ACCMOD_1 0x20000000U
3691 /****************** Bit definition for FSMC_BWTR4 register ******************/
3692 #define FSMC_BWTR4_ADDSET 0x0000000FU
3693 #define FSMC_BWTR4_ADDSET_0 0x00000001U
3694 #define FSMC_BWTR4_ADDSET_1 0x00000002U
3695 #define FSMC_BWTR4_ADDSET_2 0x00000004U
3696 #define FSMC_BWTR4_ADDSET_3 0x00000008U
3698 #define FSMC_BWTR4_ADDHLD 0x000000F0U
3699 #define FSMC_BWTR4_ADDHLD_0 0x00000010U
3700 #define FSMC_BWTR4_ADDHLD_1 0x00000020U
3701 #define FSMC_BWTR4_ADDHLD_2 0x00000040U
3702 #define FSMC_BWTR4_ADDHLD_3 0x00000080U
3704 #define FSMC_BWTR4_DATAST 0x0000FF00U
3705 #define FSMC_BWTR4_DATAST_0 0x00000100U
3706 #define FSMC_BWTR4_DATAST_1 0x00000200U
3707 #define FSMC_BWTR4_DATAST_2 0x00000400U
3708 #define FSMC_BWTR4_DATAST_3 0x00000800U
3709 #define FSMC_BWTR4_DATAST_4 0x00001000U
3710 #define FSMC_BWTR4_DATAST_5 0x00002000U
3711 #define FSMC_BWTR4_DATAST_6 0x00004000U
3712 #define FSMC_BWTR4_DATAST_7 0x00008000U
3714 #define FSMC_BWTR4_BUSTURN 0x000F0000U
3715 #define FSMC_BWTR4_BUSTURN_0 0x00010000U
3716 #define FSMC_BWTR4_BUSTURN_1 0x00020000U
3717 #define FSMC_BWTR4_BUSTURN_2 0x00040000U
3718 #define FSMC_BWTR4_BUSTURN_3 0x00080000U
3720 #define FSMC_BWTR4_ACCMOD 0x30000000U
3721 #define FSMC_BWTR4_ACCMOD_0 0x10000000U
3722 #define FSMC_BWTR4_ACCMOD_1 0x20000000U
3724 /****************** Bit definition for FSMC_PCR2 register *******************/
3725 #define FSMC_PCR2_PWAITEN 0x00000002U
3726 #define FSMC_PCR2_PBKEN 0x00000004U
3727 #define FSMC_PCR2_PTYP 0x00000008U
3729 #define FSMC_PCR2_PWID 0x00000030U
3730 #define FSMC_PCR2_PWID_0 0x00000010U
3731 #define FSMC_PCR2_PWID_1 0x00000020U
3733 #define FSMC_PCR2_ECCEN 0x00000040U
3735 #define FSMC_PCR2_TCLR 0x00001E00U
3736 #define FSMC_PCR2_TCLR_0 0x00000200U
3737 #define FSMC_PCR2_TCLR_1 0x00000400U
3738 #define FSMC_PCR2_TCLR_2 0x00000800U
3739 #define FSMC_PCR2_TCLR_3 0x00001000U
3741 #define FSMC_PCR2_TAR 0x0001E000U
3742 #define FSMC_PCR2_TAR_0 0x00002000U
3743 #define FSMC_PCR2_TAR_1 0x00004000U
3744 #define FSMC_PCR2_TAR_2 0x00008000U
3745 #define FSMC_PCR2_TAR_3 0x00010000U
3747 #define FSMC_PCR2_ECCPS 0x000E0000U
3748 #define FSMC_PCR2_ECCPS_0 0x00020000U
3749 #define FSMC_PCR2_ECCPS_1 0x00040000U
3750 #define FSMC_PCR2_ECCPS_2 0x00080000U
3752 /****************** Bit definition for FSMC_PCR3 register *******************/
3753 #define FSMC_PCR3_PWAITEN 0x00000002U
3754 #define FSMC_PCR3_PBKEN 0x00000004U
3755 #define FSMC_PCR3_PTYP 0x00000008U
3757 #define FSMC_PCR3_PWID 0x00000030U
3758 #define FSMC_PCR3_PWID_0 0x00000010U
3759 #define FSMC_PCR3_PWID_1 0x00000020U
3761 #define FSMC_PCR3_ECCEN 0x00000040U
3763 #define FSMC_PCR3_TCLR 0x00001E00U
3764 #define FSMC_PCR3_TCLR_0 0x00000200U
3765 #define FSMC_PCR3_TCLR_1 0x00000400U
3766 #define FSMC_PCR3_TCLR_2 0x00000800U
3767 #define FSMC_PCR3_TCLR_3 0x00001000U
3769 #define FSMC_PCR3_TAR 0x0001E000U
3770 #define FSMC_PCR3_TAR_0 0x00002000U
3771 #define FSMC_PCR3_TAR_1 0x00004000U
3772 #define FSMC_PCR3_TAR_2 0x00008000U
3773 #define FSMC_PCR3_TAR_3 0x00010000U
3775 #define FSMC_PCR3_ECCPS 0x000E0000U
3776 #define FSMC_PCR3_ECCPS_0 0x00020000U
3777 #define FSMC_PCR3_ECCPS_1 0x00040000U
3778 #define FSMC_PCR3_ECCPS_2 0x00080000U
3780 /****************** Bit definition for FSMC_PCR4 register *******************/
3781 #define FSMC_PCR4_PWAITEN 0x00000002U
3782 #define FSMC_PCR4_PBKEN 0x00000004U
3783 #define FSMC_PCR4_PTYP 0x00000008U
3785 #define FSMC_PCR4_PWID 0x00000030U
3786 #define FSMC_PCR4_PWID_0 0x00000010U
3787 #define FSMC_PCR4_PWID_1 0x00000020U
3789 #define FSMC_PCR4_ECCEN 0x00000040U
3791 #define FSMC_PCR4_TCLR 0x00001E00U
3792 #define FSMC_PCR4_TCLR_0 0x00000200U
3793 #define FSMC_PCR4_TCLR_1 0x00000400U
3794 #define FSMC_PCR4_TCLR_2 0x00000800U
3795 #define FSMC_PCR4_TCLR_3 0x00001000U
3797 #define FSMC_PCR4_TAR 0x0001E000U
3798 #define FSMC_PCR4_TAR_0 0x00002000U
3799 #define FSMC_PCR4_TAR_1 0x00004000U
3800 #define FSMC_PCR4_TAR_2 0x00008000U
3801 #define FSMC_PCR4_TAR_3 0x00010000U
3803 #define FSMC_PCR4_ECCPS 0x000E0000U
3804 #define FSMC_PCR4_ECCPS_0 0x00020000U
3805 #define FSMC_PCR4_ECCPS_1 0x00040000U
3806 #define FSMC_PCR4_ECCPS_2 0x00080000U
3808 /******************* Bit definition for FSMC_SR2 register *******************/
3809 #define FSMC_SR2_IRS 0x01U
3810 #define FSMC_SR2_ILS 0x02U
3811 #define FSMC_SR2_IFS 0x04U
3812 #define FSMC_SR2_IREN 0x08U
3813 #define FSMC_SR2_ILEN 0x10U
3814 #define FSMC_SR2_IFEN 0x20U
3815 #define FSMC_SR2_FEMPT 0x40U
3817 /******************* Bit definition for FSMC_SR3 register *******************/
3818 #define FSMC_SR3_IRS 0x01U
3819 #define FSMC_SR3_ILS 0x02U
3820 #define FSMC_SR3_IFS 0x04U
3821 #define FSMC_SR3_IREN 0x08U
3822 #define FSMC_SR3_ILEN 0x10U
3823 #define FSMC_SR3_IFEN 0x20U
3824 #define FSMC_SR3_FEMPT 0x40U
3826 /******************* Bit definition for FSMC_SR4 register *******************/
3827 #define FSMC_SR4_IRS 0x01U
3828 #define FSMC_SR4_ILS 0x02U
3829 #define FSMC_SR4_IFS 0x04U
3830 #define FSMC_SR4_IREN 0x08U
3831 #define FSMC_SR4_ILEN 0x10U
3832 #define FSMC_SR4_IFEN 0x20U
3833 #define FSMC_SR4_FEMPT 0x40U
3835 /****************** Bit definition for FSMC_PMEM2 register ******************/
3836 #define FSMC_PMEM2_MEMSET2 0x000000FFU
3837 #define FSMC_PMEM2_MEMSET2_0 0x00000001U
3838 #define FSMC_PMEM2_MEMSET2_1 0x00000002U
3839 #define FSMC_PMEM2_MEMSET2_2 0x00000004U
3840 #define FSMC_PMEM2_MEMSET2_3 0x00000008U
3841 #define FSMC_PMEM2_MEMSET2_4 0x00000010U
3842 #define FSMC_PMEM2_MEMSET2_5 0x00000020U
3843 #define FSMC_PMEM2_MEMSET2_6 0x00000040U
3844 #define FSMC_PMEM2_MEMSET2_7 0x00000080U
3846 #define FSMC_PMEM2_MEMWAIT2 0x0000FF00U
3847 #define FSMC_PMEM2_MEMWAIT2_0 0x00000100U
3848 #define FSMC_PMEM2_MEMWAIT2_1 0x00000200U
3849 #define FSMC_PMEM2_MEMWAIT2_2 0x00000400U
3850 #define FSMC_PMEM2_MEMWAIT2_3 0x00000800U
3851 #define FSMC_PMEM2_MEMWAIT2_4 0x00001000U
3852 #define FSMC_PMEM2_MEMWAIT2_5 0x00002000U
3853 #define FSMC_PMEM2_MEMWAIT2_6 0x00004000U
3854 #define FSMC_PMEM2_MEMWAIT2_7 0x00008000U
3856 #define FSMC_PMEM2_MEMHOLD2 0x00FF0000U
3857 #define FSMC_PMEM2_MEMHOLD2_0 0x00010000U
3858 #define FSMC_PMEM2_MEMHOLD2_1 0x00020000U
3859 #define FSMC_PMEM2_MEMHOLD2_2 0x00040000U
3860 #define FSMC_PMEM2_MEMHOLD2_3 0x00080000U
3861 #define FSMC_PMEM2_MEMHOLD2_4 0x00100000U
3862 #define FSMC_PMEM2_MEMHOLD2_5 0x00200000U
3863 #define FSMC_PMEM2_MEMHOLD2_6 0x00400000U
3864 #define FSMC_PMEM2_MEMHOLD2_7 0x00800000U
3866 #define FSMC_PMEM2_MEMHIZ2 0xFF000000U
3867 #define FSMC_PMEM2_MEMHIZ2_0 0x01000000U
3868 #define FSMC_PMEM2_MEMHIZ2_1 0x02000000U
3869 #define FSMC_PMEM2_MEMHIZ2_2 0x04000000U
3870 #define FSMC_PMEM2_MEMHIZ2_3 0x08000000U
3871 #define FSMC_PMEM2_MEMHIZ2_4 0x10000000U
3872 #define FSMC_PMEM2_MEMHIZ2_5 0x20000000U
3873 #define FSMC_PMEM2_MEMHIZ2_6 0x40000000U
3874 #define FSMC_PMEM2_MEMHIZ2_7 0x80000000U
3876 /****************** Bit definition for FSMC_PMEM3 register ******************/
3877 #define FSMC_PMEM3_MEMSET3 0x000000FFU
3878 #define FSMC_PMEM3_MEMSET3_0 0x00000001U
3879 #define FSMC_PMEM3_MEMSET3_1 0x00000002U
3880 #define FSMC_PMEM3_MEMSET3_2 0x00000004U
3881 #define FSMC_PMEM3_MEMSET3_3 0x00000008U
3882 #define FSMC_PMEM3_MEMSET3_4 0x00000010U
3883 #define FSMC_PMEM3_MEMSET3_5 0x00000020U
3884 #define FSMC_PMEM3_MEMSET3_6 0x00000040U
3885 #define FSMC_PMEM3_MEMSET3_7 0x00000080U
3887 #define FSMC_PMEM3_MEMWAIT3 0x0000FF00U
3888 #define FSMC_PMEM3_MEMWAIT3_0 0x00000100U
3889 #define FSMC_PMEM3_MEMWAIT3_1 0x00000200U
3890 #define FSMC_PMEM3_MEMWAIT3_2 0x00000400U
3891 #define FSMC_PMEM3_MEMWAIT3_3 0x00000800U
3892 #define FSMC_PMEM3_MEMWAIT3_4 0x00001000U
3893 #define FSMC_PMEM3_MEMWAIT3_5 0x00002000U
3894 #define FSMC_PMEM3_MEMWAIT3_6 0x00004000U
3895 #define FSMC_PMEM3_MEMWAIT3_7 0x00008000U
3897 #define FSMC_PMEM3_MEMHOLD3 0x00FF0000U
3898 #define FSMC_PMEM3_MEMHOLD3_0 0x00010000U
3899 #define FSMC_PMEM3_MEMHOLD3_1 0x00020000U
3900 #define FSMC_PMEM3_MEMHOLD3_2 0x00040000U
3901 #define FSMC_PMEM3_MEMHOLD3_3 0x00080000U
3902 #define FSMC_PMEM3_MEMHOLD3_4 0x00100000U
3903 #define FSMC_PMEM3_MEMHOLD3_5 0x00200000U
3904 #define FSMC_PMEM3_MEMHOLD3_6 0x00400000U
3905 #define FSMC_PMEM3_MEMHOLD3_7 0x00800000U
3907 #define FSMC_PMEM3_MEMHIZ3 0xFF000000U
3908 #define FSMC_PMEM3_MEMHIZ3_0 0x01000000U
3909 #define FSMC_PMEM3_MEMHIZ3_1 0x02000000U
3910 #define FSMC_PMEM3_MEMHIZ3_2 0x04000000U
3911 #define FSMC_PMEM3_MEMHIZ3_3 0x08000000U
3912 #define FSMC_PMEM3_MEMHIZ3_4 0x10000000U
3913 #define FSMC_PMEM3_MEMHIZ3_5 0x20000000U
3914 #define FSMC_PMEM3_MEMHIZ3_6 0x40000000U
3915 #define FSMC_PMEM3_MEMHIZ3_7 0x80000000U
3917 /****************** Bit definition for FSMC_PMEM4 register ******************/
3918 #define FSMC_PMEM4_MEMSET4 0x000000FFU
3919 #define FSMC_PMEM4_MEMSET4_0 0x00000001U
3920 #define FSMC_PMEM4_MEMSET4_1 0x00000002U
3921 #define FSMC_PMEM4_MEMSET4_2 0x00000004U
3922 #define FSMC_PMEM4_MEMSET4_3 0x00000008U
3923 #define FSMC_PMEM4_MEMSET4_4 0x00000010U
3924 #define FSMC_PMEM4_MEMSET4_5 0x00000020U
3925 #define FSMC_PMEM4_MEMSET4_6 0x00000040U
3926 #define FSMC_PMEM4_MEMSET4_7 0x00000080U
3928 #define FSMC_PMEM4_MEMWAIT4 0x0000FF00U
3929 #define FSMC_PMEM4_MEMWAIT4_0 0x00000100U
3930 #define FSMC_PMEM4_MEMWAIT4_1 0x00000200U
3931 #define FSMC_PMEM4_MEMWAIT4_2 0x00000400U
3932 #define FSMC_PMEM4_MEMWAIT4_3 0x00000800U
3933 #define FSMC_PMEM4_MEMWAIT4_4 0x00001000U
3934 #define FSMC_PMEM4_MEMWAIT4_5 0x00002000U
3935 #define FSMC_PMEM4_MEMWAIT4_6 0x00004000U
3936 #define FSMC_PMEM4_MEMWAIT4_7 0x00008000U
3938 #define FSMC_PMEM4_MEMHOLD4 0x00FF0000U
3939 #define FSMC_PMEM4_MEMHOLD4_0 0x00010000U
3940 #define FSMC_PMEM4_MEMHOLD4_1 0x00020000U
3941 #define FSMC_PMEM4_MEMHOLD4_2 0x00040000U
3942 #define FSMC_PMEM4_MEMHOLD4_3 0x00080000U
3943 #define FSMC_PMEM4_MEMHOLD4_4 0x00100000U
3944 #define FSMC_PMEM4_MEMHOLD4_5 0x00200000U
3945 #define FSMC_PMEM4_MEMHOLD4_6 0x00400000U
3946 #define FSMC_PMEM4_MEMHOLD4_7 0x00800000U
3948 #define FSMC_PMEM4_MEMHIZ4 0xFF000000U
3949 #define FSMC_PMEM4_MEMHIZ4_0 0x01000000U
3950 #define FSMC_PMEM4_MEMHIZ4_1 0x02000000U
3951 #define FSMC_PMEM4_MEMHIZ4_2 0x04000000U
3952 #define FSMC_PMEM4_MEMHIZ4_3 0x08000000U
3953 #define FSMC_PMEM4_MEMHIZ4_4 0x10000000U
3954 #define FSMC_PMEM4_MEMHIZ4_5 0x20000000U
3955 #define FSMC_PMEM4_MEMHIZ4_6 0x40000000U
3956 #define FSMC_PMEM4_MEMHIZ4_7 0x80000000U
3958 /****************** Bit definition for FSMC_PATT2 register ******************/
3959 #define FSMC_PATT2_ATTSET2 0x000000FFU
3960 #define FSMC_PATT2_ATTSET2_0 0x00000001U
3961 #define FSMC_PATT2_ATTSET2_1 0x00000002U
3962 #define FSMC_PATT2_ATTSET2_2 0x00000004U
3963 #define FSMC_PATT2_ATTSET2_3 0x00000008U
3964 #define FSMC_PATT2_ATTSET2_4 0x00000010U
3965 #define FSMC_PATT2_ATTSET2_5 0x00000020U
3966 #define FSMC_PATT2_ATTSET2_6 0x00000040U
3967 #define FSMC_PATT2_ATTSET2_7 0x00000080U
3969 #define FSMC_PATT2_ATTWAIT2 0x0000FF00U
3970 #define FSMC_PATT2_ATTWAIT2_0 0x00000100U
3971 #define FSMC_PATT2_ATTWAIT2_1 0x00000200U
3972 #define FSMC_PATT2_ATTWAIT2_2 0x00000400U
3973 #define FSMC_PATT2_ATTWAIT2_3 0x00000800U
3974 #define FSMC_PATT2_ATTWAIT2_4 0x00001000U
3975 #define FSMC_PATT2_ATTWAIT2_5 0x00002000U
3976 #define FSMC_PATT2_ATTWAIT2_6 0x00004000U
3977 #define FSMC_PATT2_ATTWAIT2_7 0x00008000U
3979 #define FSMC_PATT2_ATTHOLD2 0x00FF0000U
3980 #define FSMC_PATT2_ATTHOLD2_0 0x00010000U
3981 #define FSMC_PATT2_ATTHOLD2_1 0x00020000U
3982 #define FSMC_PATT2_ATTHOLD2_2 0x00040000U
3983 #define FSMC_PATT2_ATTHOLD2_3 0x00080000U
3984 #define FSMC_PATT2_ATTHOLD2_4 0x00100000U
3985 #define FSMC_PATT2_ATTHOLD2_5 0x00200000U
3986 #define FSMC_PATT2_ATTHOLD2_6 0x00400000U
3987 #define FSMC_PATT2_ATTHOLD2_7 0x00800000U
3989 #define FSMC_PATT2_ATTHIZ2 0xFF000000U
3990 #define FSMC_PATT2_ATTHIZ2_0 0x01000000U
3991 #define FSMC_PATT2_ATTHIZ2_1 0x02000000U
3992 #define FSMC_PATT2_ATTHIZ2_2 0x04000000U
3993 #define FSMC_PATT2_ATTHIZ2_3 0x08000000U
3994 #define FSMC_PATT2_ATTHIZ2_4 0x10000000U
3995 #define FSMC_PATT2_ATTHIZ2_5 0x20000000U
3996 #define FSMC_PATT2_ATTHIZ2_6 0x40000000U
3997 #define FSMC_PATT2_ATTHIZ2_7 0x80000000U
3999 /****************** Bit definition for FSMC_PATT3 register ******************/
4000 #define FSMC_PATT3_ATTSET3 0x000000FFU
4001 #define FSMC_PATT3_ATTSET3_0 0x00000001U
4002 #define FSMC_PATT3_ATTSET3_1 0x00000002U
4003 #define FSMC_PATT3_ATTSET3_2 0x00000004U
4004 #define FSMC_PATT3_ATTSET3_3 0x00000008U
4005 #define FSMC_PATT3_ATTSET3_4 0x00000010U
4006 #define FSMC_PATT3_ATTSET3_5 0x00000020U
4007 #define FSMC_PATT3_ATTSET3_6 0x00000040U
4008 #define FSMC_PATT3_ATTSET3_7 0x00000080U
4010 #define FSMC_PATT3_ATTWAIT3 0x0000FF00U
4011 #define FSMC_PATT3_ATTWAIT3_0 0x00000100U
4012 #define FSMC_PATT3_ATTWAIT3_1 0x00000200U
4013 #define FSMC_PATT3_ATTWAIT3_2 0x00000400U
4014 #define FSMC_PATT3_ATTWAIT3_3 0x00000800U
4015 #define FSMC_PATT3_ATTWAIT3_4 0x00001000U
4016 #define FSMC_PATT3_ATTWAIT3_5 0x00002000U
4017 #define FSMC_PATT3_ATTWAIT3_6 0x00004000U
4018 #define FSMC_PATT3_ATTWAIT3_7 0x00008000U
4020 #define FSMC_PATT3_ATTHOLD3 0x00FF0000U
4021 #define FSMC_PATT3_ATTHOLD3_0 0x00010000U
4022 #define FSMC_PATT3_ATTHOLD3_1 0x00020000U
4023 #define FSMC_PATT3_ATTHOLD3_2 0x00040000U
4024 #define FSMC_PATT3_ATTHOLD3_3 0x00080000U
4025 #define FSMC_PATT3_ATTHOLD3_4 0x00100000U
4026 #define FSMC_PATT3_ATTHOLD3_5 0x00200000U
4027 #define FSMC_PATT3_ATTHOLD3_6 0x00400000U
4028 #define FSMC_PATT3_ATTHOLD3_7 0x00800000U
4030 #define FSMC_PATT3_ATTHIZ3 0xFF000000U
4031 #define FSMC_PATT3_ATTHIZ3_0 0x01000000U
4032 #define FSMC_PATT3_ATTHIZ3_1 0x02000000U
4033 #define FSMC_PATT3_ATTHIZ3_2 0x04000000U
4034 #define FSMC_PATT3_ATTHIZ3_3 0x08000000U
4035 #define FSMC_PATT3_ATTHIZ3_4 0x10000000U
4036 #define FSMC_PATT3_ATTHIZ3_5 0x20000000U
4037 #define FSMC_PATT3_ATTHIZ3_6 0x40000000U
4038 #define FSMC_PATT3_ATTHIZ3_7 0x80000000U
4040 /****************** Bit definition for FSMC_PATT4 register ******************/
4041 #define FSMC_PATT4_ATTSET4 0x000000FFU
4042 #define FSMC_PATT4_ATTSET4_0 0x00000001U
4043 #define FSMC_PATT4_ATTSET4_1 0x00000002U
4044 #define FSMC_PATT4_ATTSET4_2 0x00000004U
4045 #define FSMC_PATT4_ATTSET4_3 0x00000008U
4046 #define FSMC_PATT4_ATTSET4_4 0x00000010U
4047 #define FSMC_PATT4_ATTSET4_5 0x00000020U
4048 #define FSMC_PATT4_ATTSET4_6 0x00000040U
4049 #define FSMC_PATT4_ATTSET4_7 0x00000080U
4051 #define FSMC_PATT4_ATTWAIT4 0x0000FF00U
4052 #define FSMC_PATT4_ATTWAIT4_0 0x00000100U
4053 #define FSMC_PATT4_ATTWAIT4_1 0x00000200U
4054 #define FSMC_PATT4_ATTWAIT4_2 0x00000400U
4055 #define FSMC_PATT4_ATTWAIT4_3 0x00000800U
4056 #define FSMC_PATT4_ATTWAIT4_4 0x00001000U
4057 #define FSMC_PATT4_ATTWAIT4_5 0x00002000U
4058 #define FSMC_PATT4_ATTWAIT4_6 0x00004000U
4059 #define FSMC_PATT4_ATTWAIT4_7 0x00008000U
4061 #define FSMC_PATT4_ATTHOLD4 0x00FF0000U
4062 #define FSMC_PATT4_ATTHOLD4_0 0x00010000U
4063 #define FSMC_PATT4_ATTHOLD4_1 0x00020000U
4064 #define FSMC_PATT4_ATTHOLD4_2 0x00040000U
4065 #define FSMC_PATT4_ATTHOLD4_3 0x00080000U
4066 #define FSMC_PATT4_ATTHOLD4_4 0x00100000U
4067 #define FSMC_PATT4_ATTHOLD4_5 0x00200000U
4068 #define FSMC_PATT4_ATTHOLD4_6 0x00400000U
4069 #define FSMC_PATT4_ATTHOLD4_7 0x00800000U
4071 #define FSMC_PATT4_ATTHIZ4 0xFF000000U
4072 #define FSMC_PATT4_ATTHIZ4_0 0x01000000U
4073 #define FSMC_PATT4_ATTHIZ4_1 0x02000000U
4074 #define FSMC_PATT4_ATTHIZ4_2 0x04000000U
4075 #define FSMC_PATT4_ATTHIZ4_3 0x08000000U
4076 #define FSMC_PATT4_ATTHIZ4_4 0x10000000U
4077 #define FSMC_PATT4_ATTHIZ4_5 0x20000000U
4078 #define FSMC_PATT4_ATTHIZ4_6 0x40000000U
4079 #define FSMC_PATT4_ATTHIZ4_7 0x80000000U
4081 /****************** Bit definition for FSMC_PIO4 register *******************/
4082 #define FSMC_PIO4_IOSET4 0x000000FFU
4083 #define FSMC_PIO4_IOSET4_0 0x00000001U
4084 #define FSMC_PIO4_IOSET4_1 0x00000002U
4085 #define FSMC_PIO4_IOSET4_2 0x00000004U
4086 #define FSMC_PIO4_IOSET4_3 0x00000008U
4087 #define FSMC_PIO4_IOSET4_4 0x00000010U
4088 #define FSMC_PIO4_IOSET4_5 0x00000020U
4089 #define FSMC_PIO4_IOSET4_6 0x00000040U
4090 #define FSMC_PIO4_IOSET4_7 0x00000080U
4092 #define FSMC_PIO4_IOWAIT4 0x0000FF00U
4093 #define FSMC_PIO4_IOWAIT4_0 0x00000100U
4094 #define FSMC_PIO4_IOWAIT4_1 0x00000200U
4095 #define FSMC_PIO4_IOWAIT4_2 0x00000400U
4096 #define FSMC_PIO4_IOWAIT4_3 0x00000800U
4097 #define FSMC_PIO4_IOWAIT4_4 0x00001000U
4098 #define FSMC_PIO4_IOWAIT4_5 0x00002000U
4099 #define FSMC_PIO4_IOWAIT4_6 0x00004000U
4100 #define FSMC_PIO4_IOWAIT4_7 0x00008000U
4102 #define FSMC_PIO4_IOHOLD4 0x00FF0000U
4103 #define FSMC_PIO4_IOHOLD4_0 0x00010000U
4104 #define FSMC_PIO4_IOHOLD4_1 0x00020000U
4105 #define FSMC_PIO4_IOHOLD4_2 0x00040000U
4106 #define FSMC_PIO4_IOHOLD4_3 0x00080000U
4107 #define FSMC_PIO4_IOHOLD4_4 0x00100000U
4108 #define FSMC_PIO4_IOHOLD4_5 0x00200000U
4109 #define FSMC_PIO4_IOHOLD4_6 0x00400000U
4110 #define FSMC_PIO4_IOHOLD4_7 0x00800000U
4112 #define FSMC_PIO4_IOHIZ4 0xFF000000U
4113 #define FSMC_PIO4_IOHIZ4_0 0x01000000U
4114 #define FSMC_PIO4_IOHIZ4_1 0x02000000U
4115 #define FSMC_PIO4_IOHIZ4_2 0x04000000U
4116 #define FSMC_PIO4_IOHIZ4_3 0x08000000U
4117 #define FSMC_PIO4_IOHIZ4_4 0x10000000U
4118 #define FSMC_PIO4_IOHIZ4_5 0x20000000U
4119 #define FSMC_PIO4_IOHIZ4_6 0x40000000U
4120 #define FSMC_PIO4_IOHIZ4_7 0x80000000U
4122 /****************** Bit definition for FSMC_ECCR2 register ******************/
4123 #define FSMC_ECCR2_ECC2 0xFFFFFFFFU
4125 /****************** Bit definition for FSMC_ECCR3 register ******************/
4126 #define FSMC_ECCR3_ECC3 0xFFFFFFFFU
4128 /******************************************************************************/
4129 /* */
4130 /* General Purpose I/O */
4131 /* */
4132 /******************************************************************************/
4133 /****************** Bits definition for GPIO_MODER register *****************/
4134 #define GPIO_MODER_MODER0 0x00000003U
4135 #define GPIO_MODER_MODER0_0 0x00000001U
4136 #define GPIO_MODER_MODER0_1 0x00000002U
4137 
4138 #define GPIO_MODER_MODER1 0x0000000CU
4139 #define GPIO_MODER_MODER1_0 0x00000004U
4140 #define GPIO_MODER_MODER1_1 0x00000008U
4141 
4142 #define GPIO_MODER_MODER2 0x00000030U
4143 #define GPIO_MODER_MODER2_0 0x00000010U
4144 #define GPIO_MODER_MODER2_1 0x00000020U
4145 
4146 #define GPIO_MODER_MODER3 0x000000C0U
4147 #define GPIO_MODER_MODER3_0 0x00000040U
4148 #define GPIO_MODER_MODER3_1 0x00000080U
4149 
4150 #define GPIO_MODER_MODER4 0x00000300U
4151 #define GPIO_MODER_MODER4_0 0x00000100U
4152 #define GPIO_MODER_MODER4_1 0x00000200U
4153 
4154 #define GPIO_MODER_MODER5 0x00000C00U
4155 #define GPIO_MODER_MODER5_0 0x00000400U
4156 #define GPIO_MODER_MODER5_1 0x00000800U
4157 
4158 #define GPIO_MODER_MODER6 0x00003000U
4159 #define GPIO_MODER_MODER6_0 0x00001000U
4160 #define GPIO_MODER_MODER6_1 0x00002000U
4161 
4162 #define GPIO_MODER_MODER7 0x0000C000U
4163 #define GPIO_MODER_MODER7_0 0x00004000U
4164 #define GPIO_MODER_MODER7_1 0x00008000U
4165 
4166 #define GPIO_MODER_MODER8 0x00030000U
4167 #define GPIO_MODER_MODER8_0 0x00010000U
4168 #define GPIO_MODER_MODER8_1 0x00020000U
4169 
4170 #define GPIO_MODER_MODER9 0x000C0000U
4171 #define GPIO_MODER_MODER9_0 0x00040000U
4172 #define GPIO_MODER_MODER9_1 0x00080000U
4173 
4174 #define GPIO_MODER_MODER10 0x00300000U
4175 #define GPIO_MODER_MODER10_0 0x00100000U
4176 #define GPIO_MODER_MODER10_1 0x00200000U
4177 
4178 #define GPIO_MODER_MODER11 0x00C00000U
4179 #define GPIO_MODER_MODER11_0 0x00400000U
4180 #define GPIO_MODER_MODER11_1 0x00800000U
4181 
4182 #define GPIO_MODER_MODER12 0x03000000U
4183 #define GPIO_MODER_MODER12_0 0x01000000U
4184 #define GPIO_MODER_MODER12_1 0x02000000U
4185 
4186 #define GPIO_MODER_MODER13 0x0C000000U
4187 #define GPIO_MODER_MODER13_0 0x04000000U
4188 #define GPIO_MODER_MODER13_1 0x08000000U
4189 
4190 #define GPIO_MODER_MODER14 0x30000000U
4191 #define GPIO_MODER_MODER14_0 0x10000000U
4192 #define GPIO_MODER_MODER14_1 0x20000000U
4193 
4194 #define GPIO_MODER_MODER15 0xC0000000U
4195 #define GPIO_MODER_MODER15_0 0x40000000U
4196 #define GPIO_MODER_MODER15_1 0x80000000U
4197 
4198 /****************** Bits definition for GPIO_OTYPER register ****************/
4199 #define GPIO_OTYPER_OT_0 0x00000001U
4200 #define GPIO_OTYPER_OT_1 0x00000002U
4201 #define GPIO_OTYPER_OT_2 0x00000004U
4202 #define GPIO_OTYPER_OT_3 0x00000008U
4203 #define GPIO_OTYPER_OT_4 0x00000010U
4204 #define GPIO_OTYPER_OT_5 0x00000020U
4205 #define GPIO_OTYPER_OT_6 0x00000040U
4206 #define GPIO_OTYPER_OT_7 0x00000080U
4207 #define GPIO_OTYPER_OT_8 0x00000100U
4208 #define GPIO_OTYPER_OT_9 0x00000200U
4209 #define GPIO_OTYPER_OT_10 0x00000400U
4210 #define GPIO_OTYPER_OT_11 0x00000800U
4211 #define GPIO_OTYPER_OT_12 0x00001000U
4212 #define GPIO_OTYPER_OT_13 0x00002000U
4213 #define GPIO_OTYPER_OT_14 0x00004000U
4214 #define GPIO_OTYPER_OT_15 0x00008000U
4215 
4216 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4217 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4218 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4219 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4220 
4221 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4222 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4223 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4224 
4225 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4226 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4227 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4228 
4229 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4230 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4231 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4232 
4233 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4234 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4235 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4236 
4237 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4238 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4239 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4240 
4241 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4242 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4243 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4244 
4245 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4246 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4247 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4248 
4249 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4250 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4251 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4252 
4253 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4254 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4255 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4256 
4257 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4258 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4259 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4260 
4261 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4262 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4263 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4264 
4265 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4266 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4267 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4268 
4269 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4270 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4271 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4272 
4273 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4274 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4275 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4276 
4277 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4278 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4279 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4280 
4281 /****************** Bits definition for GPIO_PUPDR register *****************/
4282 #define GPIO_PUPDR_PUPDR0 0x00000003U
4283 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4284 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4285 
4286 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4287 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4288 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4289 
4290 #define GPIO_PUPDR_PUPDR2 0x00000030U
4291 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4292 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4293 
4294 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4295 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4296 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4297 
4298 #define GPIO_PUPDR_PUPDR4 0x00000300U
4299 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4300 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4301 
4302 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4303 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4304 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4305 
4306 #define GPIO_PUPDR_PUPDR6 0x00003000U
4307 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4308 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4309 
4310 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4311 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4312 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4313 
4314 #define GPIO_PUPDR_PUPDR8 0x00030000U
4315 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4316 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4317 
4318 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4319 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4320 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4321 
4322 #define GPIO_PUPDR_PUPDR10 0x00300000U
4323 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4324 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4325 
4326 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4327 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4328 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4329 
4330 #define GPIO_PUPDR_PUPDR12 0x03000000U
4331 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4332 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4333 
4334 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4335 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4336 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4337 
4338 #define GPIO_PUPDR_PUPDR14 0x30000000U
4339 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4340 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
4341 
4342 #define GPIO_PUPDR_PUPDR15 0xC0000000U
4343 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
4344 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
4345 
4346 /****************** Bits definition for GPIO_IDR register *******************/
4347 #define GPIO_IDR_IDR_0 0x00000001U
4348 #define GPIO_IDR_IDR_1 0x00000002U
4349 #define GPIO_IDR_IDR_2 0x00000004U
4350 #define GPIO_IDR_IDR_3 0x00000008U
4351 #define GPIO_IDR_IDR_4 0x00000010U
4352 #define GPIO_IDR_IDR_5 0x00000020U
4353 #define GPIO_IDR_IDR_6 0x00000040U
4354 #define GPIO_IDR_IDR_7 0x00000080U
4355 #define GPIO_IDR_IDR_8 0x00000100U
4356 #define GPIO_IDR_IDR_9 0x00000200U
4357 #define GPIO_IDR_IDR_10 0x00000400U
4358 #define GPIO_IDR_IDR_11 0x00000800U
4359 #define GPIO_IDR_IDR_12 0x00001000U
4360 #define GPIO_IDR_IDR_13 0x00002000U
4361 #define GPIO_IDR_IDR_14 0x00004000U
4362 #define GPIO_IDR_IDR_15 0x00008000U
4363 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4364 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4365 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4366 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4367 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4368 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4369 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4370 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4371 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4372 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4373 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4374 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4375 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4376 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4377 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4378 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4379 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4380 
4381 /****************** Bits definition for GPIO_ODR register *******************/
4382 #define GPIO_ODR_ODR_0 0x00000001U
4383 #define GPIO_ODR_ODR_1 0x00000002U
4384 #define GPIO_ODR_ODR_2 0x00000004U
4385 #define GPIO_ODR_ODR_3 0x00000008U
4386 #define GPIO_ODR_ODR_4 0x00000010U
4387 #define GPIO_ODR_ODR_5 0x00000020U
4388 #define GPIO_ODR_ODR_6 0x00000040U
4389 #define GPIO_ODR_ODR_7 0x00000080U
4390 #define GPIO_ODR_ODR_8 0x00000100U
4391 #define GPIO_ODR_ODR_9 0x00000200U
4392 #define GPIO_ODR_ODR_10 0x00000400U
4393 #define GPIO_ODR_ODR_11 0x00000800U
4394 #define GPIO_ODR_ODR_12 0x00001000U
4395 #define GPIO_ODR_ODR_13 0x00002000U
4396 #define GPIO_ODR_ODR_14 0x00004000U
4397 #define GPIO_ODR_ODR_15 0x00008000U
4398 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4399 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4400 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4401 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4402 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4403 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4404 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4405 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4406 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4407 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4408 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4409 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4410 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4411 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4412 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4413 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4414 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4415 
4416 /****************** Bits definition for GPIO_BSRR register ******************/
4417 #define GPIO_BSRR_BS_0 0x00000001U
4418 #define GPIO_BSRR_BS_1 0x00000002U
4419 #define GPIO_BSRR_BS_2 0x00000004U
4420 #define GPIO_BSRR_BS_3 0x00000008U
4421 #define GPIO_BSRR_BS_4 0x00000010U
4422 #define GPIO_BSRR_BS_5 0x00000020U
4423 #define GPIO_BSRR_BS_6 0x00000040U
4424 #define GPIO_BSRR_BS_7 0x00000080U
4425 #define GPIO_BSRR_BS_8 0x00000100U
4426 #define GPIO_BSRR_BS_9 0x00000200U
4427 #define GPIO_BSRR_BS_10 0x00000400U
4428 #define GPIO_BSRR_BS_11 0x00000800U
4429 #define GPIO_BSRR_BS_12 0x00001000U
4430 #define GPIO_BSRR_BS_13 0x00002000U
4431 #define GPIO_BSRR_BS_14 0x00004000U
4432 #define GPIO_BSRR_BS_15 0x00008000U
4433 #define GPIO_BSRR_BR_0 0x00010000U
4434 #define GPIO_BSRR_BR_1 0x00020000U
4435 #define GPIO_BSRR_BR_2 0x00040000U
4436 #define GPIO_BSRR_BR_3 0x00080000U
4437 #define GPIO_BSRR_BR_4 0x00100000U
4438 #define GPIO_BSRR_BR_5 0x00200000U
4439 #define GPIO_BSRR_BR_6 0x00400000U
4440 #define GPIO_BSRR_BR_7 0x00800000U
4441 #define GPIO_BSRR_BR_8 0x01000000U
4442 #define GPIO_BSRR_BR_9 0x02000000U
4443 #define GPIO_BSRR_BR_10 0x04000000U
4444 #define GPIO_BSRR_BR_11 0x08000000U
4445 #define GPIO_BSRR_BR_12 0x10000000U
4446 #define GPIO_BSRR_BR_13 0x20000000U
4447 #define GPIO_BSRR_BR_14 0x40000000U
4448 #define GPIO_BSRR_BR_15 0x80000000U
4449 
4450 /****************** Bit definition for GPIO_LCKR register *********************/
4451 #define GPIO_LCKR_LCK0 0x00000001U
4452 #define GPIO_LCKR_LCK1 0x00000002U
4453 #define GPIO_LCKR_LCK2 0x00000004U
4454 #define GPIO_LCKR_LCK3 0x00000008U
4455 #define GPIO_LCKR_LCK4 0x00000010U
4456 #define GPIO_LCKR_LCK5 0x00000020U
4457 #define GPIO_LCKR_LCK6 0x00000040U
4458 #define GPIO_LCKR_LCK7 0x00000080U
4459 #define GPIO_LCKR_LCK8 0x00000100U
4460 #define GPIO_LCKR_LCK9 0x00000200U
4461 #define GPIO_LCKR_LCK10 0x00000400U
4462 #define GPIO_LCKR_LCK11 0x00000800U
4463 #define GPIO_LCKR_LCK12 0x00001000U
4464 #define GPIO_LCKR_LCK13 0x00002000U
4465 #define GPIO_LCKR_LCK14 0x00004000U
4466 #define GPIO_LCKR_LCK15 0x00008000U
4467 #define GPIO_LCKR_LCKK 0x00010000U
4468 
4469 /******************************************************************************/
4470 /* */
4471 /* Inter-integrated Circuit Interface */
4472 /* */
4473 /******************************************************************************/
4474 /******************* Bit definition for I2C_CR1 register ********************/
4475 #define I2C_CR1_PE 0x00000001U
4476 #define I2C_CR1_SMBUS 0x00000002U
4477 #define I2C_CR1_SMBTYPE 0x00000008U
4478 #define I2C_CR1_ENARP 0x00000010U
4479 #define I2C_CR1_ENPEC 0x00000020U
4480 #define I2C_CR1_ENGC 0x00000040U
4481 #define I2C_CR1_NOSTRETCH 0x00000080U
4482 #define I2C_CR1_START 0x00000100U
4483 #define I2C_CR1_STOP 0x00000200U
4484 #define I2C_CR1_ACK 0x00000400U
4485 #define I2C_CR1_POS 0x00000800U
4486 #define I2C_CR1_PEC 0x00001000U
4487 #define I2C_CR1_ALERT 0x00002000U
4488 #define I2C_CR1_SWRST 0x00008000U
4490 /******************* Bit definition for I2C_CR2 register ********************/
4491 #define I2C_CR2_FREQ 0x0000003FU
4492 #define I2C_CR2_FREQ_0 0x00000001U
4493 #define I2C_CR2_FREQ_1 0x00000002U
4494 #define I2C_CR2_FREQ_2 0x00000004U
4495 #define I2C_CR2_FREQ_3 0x00000008U
4496 #define I2C_CR2_FREQ_4 0x00000010U
4497 #define I2C_CR2_FREQ_5 0x00000020U
4499 #define I2C_CR2_ITERREN 0x00000100U
4500 #define I2C_CR2_ITEVTEN 0x00000200U
4501 #define I2C_CR2_ITBUFEN 0x00000400U
4502 #define I2C_CR2_DMAEN 0x00000800U
4503 #define I2C_CR2_LAST 0x00001000U
4505 /******************* Bit definition for I2C_OAR1 register *******************/
4506 #define I2C_OAR1_ADD1_7 0x000000FEU
4507 #define I2C_OAR1_ADD8_9 0x00000300U
4509 #define I2C_OAR1_ADD0 0x00000001U
4510 #define I2C_OAR1_ADD1 0x00000002U
4511 #define I2C_OAR1_ADD2 0x00000004U
4512 #define I2C_OAR1_ADD3 0x00000008U
4513 #define I2C_OAR1_ADD4 0x00000010U
4514 #define I2C_OAR1_ADD5 0x00000020U
4515 #define I2C_OAR1_ADD6 0x00000040U
4516 #define I2C_OAR1_ADD7 0x00000080U
4517 #define I2C_OAR1_ADD8 0x00000100U
4518 #define I2C_OAR1_ADD9 0x00000200U
4520 #define I2C_OAR1_ADDMODE 0x00008000U
4522 /******************* Bit definition for I2C_OAR2 register *******************/
4523 #define I2C_OAR2_ENDUAL 0x00000001U
4524 #define I2C_OAR2_ADD2 0x000000FEU
4526 /******************** Bit definition for I2C_DR register ********************/
4527 #define I2C_DR_DR 0x000000FFU
4529 /******************* Bit definition for I2C_SR1 register ********************/
4530 #define I2C_SR1_SB 0x00000001U
4531 #define I2C_SR1_ADDR 0x00000002U
4532 #define I2C_SR1_BTF 0x00000004U
4533 #define I2C_SR1_ADD10 0x00000008U
4534 #define I2C_SR1_STOPF 0x00000010U
4535 #define I2C_SR1_RXNE 0x00000040U
4536 #define I2C_SR1_TXE 0x00000080U
4537 #define I2C_SR1_BERR 0x00000100U
4538 #define I2C_SR1_ARLO 0x00000200U
4539 #define I2C_SR1_AF 0x00000400U
4540 #define I2C_SR1_OVR 0x00000800U
4541 #define I2C_SR1_PECERR 0x00001000U
4542 #define I2C_SR1_TIMEOUT 0x00004000U
4543 #define I2C_SR1_SMBALERT 0x00008000U
4545 /******************* Bit definition for I2C_SR2 register ********************/
4546 #define I2C_SR2_MSL 0x00000001U
4547 #define I2C_SR2_BUSY 0x00000002U
4548 #define I2C_SR2_TRA 0x00000004U
4549 #define I2C_SR2_GENCALL 0x00000010U
4550 #define I2C_SR2_SMBDEFAULT 0x00000020U
4551 #define I2C_SR2_SMBHOST 0x00000040U
4552 #define I2C_SR2_DUALF 0x00000080U
4553 #define I2C_SR2_PEC 0x0000FF00U
4555 /******************* Bit definition for I2C_CCR register ********************/
4556 #define I2C_CCR_CCR 0x00000FFFU
4557 #define I2C_CCR_DUTY 0x00004000U
4558 #define I2C_CCR_FS 0x00008000U
4560 /****************** Bit definition for I2C_TRISE register *******************/
4561 #define I2C_TRISE_TRISE 0x0000003FU
4563 /****************** Bit definition for I2C_FLTR register *******************/
4564 #define I2C_FLTR_DNF 0x0000000FU
4565 #define I2C_FLTR_ANOFF 0x00000010U
4567 /******************************************************************************/
4568 /* */
4569 /* Independent WATCHDOG */
4570 /* */
4571 /******************************************************************************/
4572 /******************* Bit definition for IWDG_KR register ********************/
4573 #define IWDG_KR_KEY 0xFFFFU
4575 /******************* Bit definition for IWDG_PR register ********************/
4576 #define IWDG_PR_PR 0x07U
4577 #define IWDG_PR_PR_0 0x01U
4578 #define IWDG_PR_PR_1 0x02U
4579 #define IWDG_PR_PR_2 0x04U
4581 /******************* Bit definition for IWDG_RLR register *******************/
4582 #define IWDG_RLR_RL 0x0FFFU
4584 /******************* Bit definition for IWDG_SR register ********************/
4585 #define IWDG_SR_PVU 0x01U
4586 #define IWDG_SR_RVU 0x02U
4589 /******************************************************************************/
4590 /* */
4591 /* Power Control */
4592 /* */
4593 /******************************************************************************/
4594 /******************** Bit definition for PWR_CR register ********************/
4595 #define PWR_CR_LPDS 0x00000001U
4596 #define PWR_CR_PDDS 0x00000002U
4597 #define PWR_CR_CWUF 0x00000004U
4598 #define PWR_CR_CSBF 0x00000008U
4599 #define PWR_CR_PVDE 0x00000010U
4601 #define PWR_CR_PLS 0x000000E0U
4602 #define PWR_CR_PLS_0 0x00000020U
4603 #define PWR_CR_PLS_1 0x00000040U
4604 #define PWR_CR_PLS_2 0x00000080U
4607 #define PWR_CR_PLS_LEV0 0x00000000U
4608 #define PWR_CR_PLS_LEV1 0x00000020U
4609 #define PWR_CR_PLS_LEV2 0x00000040U
4610 #define PWR_CR_PLS_LEV3 0x00000060U
4611 #define PWR_CR_PLS_LEV4 0x00000080U
4612 #define PWR_CR_PLS_LEV5 0x000000A0U
4613 #define PWR_CR_PLS_LEV6 0x000000C0U
4614 #define PWR_CR_PLS_LEV7 0x000000E0U
4616 #define PWR_CR_DBP 0x00000100U
4617 #define PWR_CR_FPDS 0x00000200U
4618 #define PWR_CR_VOS 0x00004000U
4620 /* Legacy define */
4621 #define PWR_CR_PMODE PWR_CR_VOS
4622 
4623 /******************* Bit definition for PWR_CSR register ********************/
4624 #define PWR_CSR_WUF 0x00000001U
4625 #define PWR_CSR_SBF 0x00000002U
4626 #define PWR_CSR_PVDO 0x00000004U
4627 #define PWR_CSR_BRR 0x00000008U
4628 #define PWR_CSR_EWUP 0x00000100U
4629 #define PWR_CSR_BRE 0x00000200U
4630 #define PWR_CSR_VOSRDY 0x00004000U
4632 /* Legacy define */
4633 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
4634 
4635 /******************************************************************************/
4636 /* */
4637 /* Reset and Clock Control */
4638 /* */
4639 /******************************************************************************/
4640 /******************** Bit definition for RCC_CR register ********************/
4641 #define RCC_CR_HSION 0x00000001U
4642 #define RCC_CR_HSIRDY 0x00000002U
4643 
4644 #define RCC_CR_HSITRIM 0x000000F8U
4645 #define RCC_CR_HSITRIM_0 0x00000008U
4646 #define RCC_CR_HSITRIM_1 0x00000010U
4647 #define RCC_CR_HSITRIM_2 0x00000020U
4648 #define RCC_CR_HSITRIM_3 0x00000040U
4649 #define RCC_CR_HSITRIM_4 0x00000080U
4651 #define RCC_CR_HSICAL 0x0000FF00U
4652 #define RCC_CR_HSICAL_0 0x00000100U
4653 #define RCC_CR_HSICAL_1 0x00000200U
4654 #define RCC_CR_HSICAL_2 0x00000400U
4655 #define RCC_CR_HSICAL_3 0x00000800U
4656 #define RCC_CR_HSICAL_4 0x00001000U
4657 #define RCC_CR_HSICAL_5 0x00002000U
4658 #define RCC_CR_HSICAL_6 0x00004000U
4659 #define RCC_CR_HSICAL_7 0x00008000U
4661 #define RCC_CR_HSEON 0x00010000U
4662 #define RCC_CR_HSERDY 0x00020000U
4663 #define RCC_CR_HSEBYP 0x00040000U
4664 #define RCC_CR_CSSON 0x00080000U
4665 #define RCC_CR_PLLON 0x01000000U
4666 #define RCC_CR_PLLRDY 0x02000000U
4667 #define RCC_CR_PLLI2SON 0x04000000U
4668 #define RCC_CR_PLLI2SRDY 0x08000000U
4669 
4670 /******************** Bit definition for RCC_PLLCFGR register ***************/
4671 #define RCC_PLLCFGR_PLLM 0x0000003FU
4672 #define RCC_PLLCFGR_PLLM_0 0x00000001U
4673 #define RCC_PLLCFGR_PLLM_1 0x00000002U
4674 #define RCC_PLLCFGR_PLLM_2 0x00000004U
4675 #define RCC_PLLCFGR_PLLM_3 0x00000008U
4676 #define RCC_PLLCFGR_PLLM_4 0x00000010U
4677 #define RCC_PLLCFGR_PLLM_5 0x00000020U
4678 
4679 #define RCC_PLLCFGR_PLLN 0x00007FC0U
4680 #define RCC_PLLCFGR_PLLN_0 0x00000040U
4681 #define RCC_PLLCFGR_PLLN_1 0x00000080U
4682 #define RCC_PLLCFGR_PLLN_2 0x00000100U
4683 #define RCC_PLLCFGR_PLLN_3 0x00000200U
4684 #define RCC_PLLCFGR_PLLN_4 0x00000400U
4685 #define RCC_PLLCFGR_PLLN_5 0x00000800U
4686 #define RCC_PLLCFGR_PLLN_6 0x00001000U
4687 #define RCC_PLLCFGR_PLLN_7 0x00002000U
4688 #define RCC_PLLCFGR_PLLN_8 0x00004000U
4689 
4690 #define RCC_PLLCFGR_PLLP 0x00030000U
4691 #define RCC_PLLCFGR_PLLP_0 0x00010000U
4692 #define RCC_PLLCFGR_PLLP_1 0x00020000U
4693 
4694 #define RCC_PLLCFGR_PLLSRC 0x00400000U
4695 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
4696 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
4697 
4698 #define RCC_PLLCFGR_PLLQ 0x0F000000U
4699 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
4700 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
4701 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
4702 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
4703 
4704 /******************** Bit definition for RCC_CFGR register ******************/
4706 #define RCC_CFGR_SW 0x00000003U
4707 #define RCC_CFGR_SW_0 0x00000001U
4708 #define RCC_CFGR_SW_1 0x00000002U
4710 #define RCC_CFGR_SW_HSI 0x00000000U
4711 #define RCC_CFGR_SW_HSE 0x00000001U
4712 #define RCC_CFGR_SW_PLL 0x00000002U
4715 #define RCC_CFGR_SWS 0x0000000CU
4716 #define RCC_CFGR_SWS_0 0x00000004U
4717 #define RCC_CFGR_SWS_1 0x00000008U
4719 #define RCC_CFGR_SWS_HSI 0x00000000U
4720 #define RCC_CFGR_SWS_HSE 0x00000004U
4721 #define RCC_CFGR_SWS_PLL 0x00000008U
4724 #define RCC_CFGR_HPRE 0x000000F0U
4725 #define RCC_CFGR_HPRE_0 0x00000010U
4726 #define RCC_CFGR_HPRE_1 0x00000020U
4727 #define RCC_CFGR_HPRE_2 0x00000040U
4728 #define RCC_CFGR_HPRE_3 0x00000080U
4730 #define RCC_CFGR_HPRE_DIV1 0x00000000U
4731 #define RCC_CFGR_HPRE_DIV2 0x00000080U
4732 #define RCC_CFGR_HPRE_DIV4 0x00000090U
4733 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
4734 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
4735 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
4736 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
4737 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
4738 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
4741 #define RCC_CFGR_PPRE1 0x00001C00U
4742 #define RCC_CFGR_PPRE1_0 0x00000400U
4743 #define RCC_CFGR_PPRE1_1 0x00000800U
4744 #define RCC_CFGR_PPRE1_2 0x00001000U
4746 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
4747 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
4748 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
4749 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
4750 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
4753 #define RCC_CFGR_PPRE2 0x0000E000U
4754 #define RCC_CFGR_PPRE2_0 0x00002000U
4755 #define RCC_CFGR_PPRE2_1 0x00004000U
4756 #define RCC_CFGR_PPRE2_2 0x00008000U
4758 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
4759 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
4760 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
4761 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
4762 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
4765 #define RCC_CFGR_RTCPRE 0x001F0000U
4766 #define RCC_CFGR_RTCPRE_0 0x00010000U
4767 #define RCC_CFGR_RTCPRE_1 0x00020000U
4768 #define RCC_CFGR_RTCPRE_2 0x00040000U
4769 #define RCC_CFGR_RTCPRE_3 0x00080000U
4770 #define RCC_CFGR_RTCPRE_4 0x00100000U
4771 
4773 #define RCC_CFGR_MCO1 0x00600000U
4774 #define RCC_CFGR_MCO1_0 0x00200000U
4775 #define RCC_CFGR_MCO1_1 0x00400000U
4776 
4777 #define RCC_CFGR_I2SSRC 0x00800000U
4778 
4779 #define RCC_CFGR_MCO1PRE 0x07000000U
4780 #define RCC_CFGR_MCO1PRE_0 0x01000000U
4781 #define RCC_CFGR_MCO1PRE_1 0x02000000U
4782 #define RCC_CFGR_MCO1PRE_2 0x04000000U
4783 
4784 #define RCC_CFGR_MCO2PRE 0x38000000U
4785 #define RCC_CFGR_MCO2PRE_0 0x08000000U
4786 #define RCC_CFGR_MCO2PRE_1 0x10000000U
4787 #define RCC_CFGR_MCO2PRE_2 0x20000000U
4788 
4789 #define RCC_CFGR_MCO2 0xC0000000U
4790 #define RCC_CFGR_MCO2_0 0x40000000U
4791 #define RCC_CFGR_MCO2_1 0x80000000U
4792 
4793 /******************** Bit definition for RCC_CIR register *******************/
4794 #define RCC_CIR_LSIRDYF 0x00000001U
4795 #define RCC_CIR_LSERDYF 0x00000002U
4796 #define RCC_CIR_HSIRDYF 0x00000004U
4797 #define RCC_CIR_HSERDYF 0x00000008U
4798 #define RCC_CIR_PLLRDYF 0x00000010U
4799 #define RCC_CIR_PLLI2SRDYF 0x00000020U
4800 
4801 #define RCC_CIR_CSSF 0x00000080U
4802 #define RCC_CIR_LSIRDYIE 0x00000100U
4803 #define RCC_CIR_LSERDYIE 0x00000200U
4804 #define RCC_CIR_HSIRDYIE 0x00000400U
4805 #define RCC_CIR_HSERDYIE 0x00000800U
4806 #define RCC_CIR_PLLRDYIE 0x00001000U
4807 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
4808 
4809 #define RCC_CIR_LSIRDYC 0x00010000U
4810 #define RCC_CIR_LSERDYC 0x00020000U
4811 #define RCC_CIR_HSIRDYC 0x00040000U
4812 #define RCC_CIR_HSERDYC 0x00080000U
4813 #define RCC_CIR_PLLRDYC 0x00100000U
4814 #define RCC_CIR_PLLI2SRDYC 0x00200000U
4815 
4816 #define RCC_CIR_CSSC 0x00800000U
4817 
4818 /******************** Bit definition for RCC_AHB1RSTR register **************/
4819 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
4820 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
4821 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
4822 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
4823 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
4824 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
4825 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
4826 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
4827 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
4828 #define RCC_AHB1RSTR_CRCRST 0x00001000U
4829 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
4830 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
4831 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
4832 
4833 /******************** Bit definition for RCC_AHB2RSTR register **************/
4834 #define RCC_AHB2RSTR_RNGRST 0x00000040U
4835 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
4836 
4837 /******************** Bit definition for RCC_AHB3RSTR register **************/
4838 
4839 #define RCC_AHB3RSTR_FSMCRST 0x00000001U
4840 
4841 /******************** Bit definition for RCC_APB1RSTR register **************/
4842 #define RCC_APB1RSTR_TIM2RST 0x00000001U
4843 #define RCC_APB1RSTR_TIM3RST 0x00000002U
4844 #define RCC_APB1RSTR_TIM4RST 0x00000004U
4845 #define RCC_APB1RSTR_TIM5RST 0x00000008U
4846 #define RCC_APB1RSTR_TIM6RST 0x00000010U
4847 #define RCC_APB1RSTR_TIM7RST 0x00000020U
4848 #define RCC_APB1RSTR_TIM12RST 0x00000040U
4849 #define RCC_APB1RSTR_TIM13RST 0x00000080U
4850 #define RCC_APB1RSTR_TIM14RST 0x00000100U
4851 #define RCC_APB1RSTR_WWDGRST 0x00000800U
4852 #define RCC_APB1RSTR_SPI2RST 0x00004000U
4853 #define RCC_APB1RSTR_SPI3RST 0x00008000U
4854 #define RCC_APB1RSTR_USART2RST 0x00020000U
4855 #define RCC_APB1RSTR_USART3RST 0x00040000U
4856 #define RCC_APB1RSTR_UART4RST 0x00080000U
4857 #define RCC_APB1RSTR_UART5RST 0x00100000U
4858 #define RCC_APB1RSTR_I2C1RST 0x00200000U
4859 #define RCC_APB1RSTR_I2C2RST 0x00400000U
4860 #define RCC_APB1RSTR_I2C3RST 0x00800000U
4861 #define RCC_APB1RSTR_CAN1RST 0x02000000U
4862 #define RCC_APB1RSTR_CAN2RST 0x04000000U
4863 #define RCC_APB1RSTR_PWRRST 0x10000000U
4864 #define RCC_APB1RSTR_DACRST 0x20000000U
4865 
4866 /******************** Bit definition for RCC_APB2RSTR register **************/
4867 #define RCC_APB2RSTR_TIM1RST 0x00000001U
4868 #define RCC_APB2RSTR_TIM8RST 0x00000002U
4869 #define RCC_APB2RSTR_USART1RST 0x00000010U
4870 #define RCC_APB2RSTR_USART6RST 0x00000020U
4871 #define RCC_APB2RSTR_ADCRST 0x00000100U
4872 #define RCC_APB2RSTR_SDIORST 0x00000800U
4873 #define RCC_APB2RSTR_SPI1RST 0x00001000U
4874 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
4875 #define RCC_APB2RSTR_TIM9RST 0x00010000U
4876 #define RCC_APB2RSTR_TIM10RST 0x00020000U
4877 #define RCC_APB2RSTR_TIM11RST 0x00040000U
4878 
4879 /* Old SPI1RST bit definition, maintained for legacy purpose */
4880 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
4881 
4882 /******************** Bit definition for RCC_AHB1ENR register ***************/
4883 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
4884 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
4885 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
4886 #define RCC_AHB1ENR_GPIODEN 0x00000008U
4887 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
4888 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
4889 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
4890 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
4891 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
4892 #define RCC_AHB1ENR_CRCEN 0x00001000U
4893 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
4894 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
4895 #define RCC_AHB1ENR_DMA1EN 0x00200000U
4896 #define RCC_AHB1ENR_DMA2EN 0x00400000U
4897 
4898 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
4899 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
4900 
4901 /******************** Bit definition for RCC_AHB2ENR register ***************/
4902 #define RCC_AHB2ENR_RNGEN 0x00000040U
4903 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
4904 
4905 /******************** Bit definition for RCC_AHB3ENR register ***************/
4906 
4907 #define RCC_AHB3ENR_FSMCEN 0x00000001U
4908 
4909 /******************** Bit definition for RCC_APB1ENR register ***************/
4910 #define RCC_APB1ENR_TIM2EN 0x00000001U
4911 #define RCC_APB1ENR_TIM3EN 0x00000002U
4912 #define RCC_APB1ENR_TIM4EN 0x00000004U
4913 #define RCC_APB1ENR_TIM5EN 0x00000008U
4914 #define RCC_APB1ENR_TIM6EN 0x00000010U
4915 #define RCC_APB1ENR_TIM7EN 0x00000020U
4916 #define RCC_APB1ENR_TIM12EN 0x00000040U
4917 #define RCC_APB1ENR_TIM13EN 0x00000080U
4918 #define RCC_APB1ENR_TIM14EN 0x00000100U
4919 #define RCC_APB1ENR_WWDGEN 0x00000800U
4920 #define RCC_APB1ENR_SPI2EN 0x00004000U
4921 #define RCC_APB1ENR_SPI3EN 0x00008000U
4922 #define RCC_APB1ENR_USART2EN 0x00020000U
4923 #define RCC_APB1ENR_USART3EN 0x00040000U
4924 #define RCC_APB1ENR_UART4EN 0x00080000U
4925 #define RCC_APB1ENR_UART5EN 0x00100000U
4926 #define RCC_APB1ENR_I2C1EN 0x00200000U
4927 #define RCC_APB1ENR_I2C2EN 0x00400000U
4928 #define RCC_APB1ENR_I2C3EN 0x00800000U
4929 #define RCC_APB1ENR_CAN1EN 0x02000000U
4930 #define RCC_APB1ENR_CAN2EN 0x04000000U
4931 #define RCC_APB1ENR_PWREN 0x10000000U
4932 #define RCC_APB1ENR_DACEN 0x20000000U
4933 
4934 /******************** Bit definition for RCC_APB2ENR register ***************/
4935 #define RCC_APB2ENR_TIM1EN 0x00000001U
4936 #define RCC_APB2ENR_TIM8EN 0x00000002U
4937 #define RCC_APB2ENR_USART1EN 0x00000010U
4938 #define RCC_APB2ENR_USART6EN 0x00000020U
4939 #define RCC_APB2ENR_ADC1EN 0x00000100U
4940 #define RCC_APB2ENR_ADC2EN 0x00000200U
4941 #define RCC_APB2ENR_ADC3EN 0x00000400U
4942 #define RCC_APB2ENR_SDIOEN 0x00000800U
4943 #define RCC_APB2ENR_SPI1EN 0x00001000U
4944 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
4945 #define RCC_APB2ENR_TIM9EN 0x00010000U
4946 #define RCC_APB2ENR_TIM10EN 0x00020000U
4947 #define RCC_APB2ENR_TIM11EN 0x00040000U
4948 #define RCC_APB2ENR_SPI5EN 0x00100000U
4949 #define RCC_APB2ENR_SPI6EN 0x00200000U
4950 
4951 /******************** Bit definition for RCC_AHB1LPENR register *************/
4952 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
4953 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
4954 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
4955 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
4956 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
4957 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
4958 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
4959 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
4960 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
4961 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
4962 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
4963 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
4964 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
4965 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
4966 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
4967 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
4968 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
4969 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
4970 
4971 /******************** Bit definition for RCC_AHB2LPENR register *************/
4972 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
4973 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
4974 
4975 /******************** Bit definition for RCC_AHB3LPENR register *************/
4976 
4977 #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
4978 
4979 /******************** Bit definition for RCC_APB1LPENR register *************/
4980 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
4981 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
4982 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
4983 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
4984 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
4985 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
4986 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
4987 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
4988 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
4989 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
4990 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
4991 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
4992 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
4993 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
4994 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
4995 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
4996 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
4997 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
4998 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
4999 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5000 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5001 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5002 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5003 
5004 /******************** Bit definition for RCC_APB2LPENR register *************/
5005 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5006 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5007 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5008 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5009 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5010 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5011 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5012 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
5013 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5014 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5015 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5016 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5017 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5018 
5019 /******************** Bit definition for RCC_BDCR register ******************/
5020 #define RCC_BDCR_LSEON 0x00000001U
5021 #define RCC_BDCR_LSERDY 0x00000002U
5022 #define RCC_BDCR_LSEBYP 0x00000004U
5023 
5024 #define RCC_BDCR_RTCSEL 0x00000300U
5025 #define RCC_BDCR_RTCSEL_0 0x00000100U
5026 #define RCC_BDCR_RTCSEL_1 0x00000200U
5027 
5028 #define RCC_BDCR_RTCEN 0x00008000U
5029 #define RCC_BDCR_BDRST 0x00010000U
5030 
5031 /******************** Bit definition for RCC_CSR register *******************/
5032 #define RCC_CSR_LSION 0x00000001U
5033 #define RCC_CSR_LSIRDY 0x00000002U
5034 #define RCC_CSR_RMVF 0x01000000U
5035 #define RCC_CSR_BORRSTF 0x02000000U
5036 #define RCC_CSR_PADRSTF 0x04000000U
5037 #define RCC_CSR_PORRSTF 0x08000000U
5038 #define RCC_CSR_SFTRSTF 0x10000000U
5039 #define RCC_CSR_WDGRSTF 0x20000000U
5040 #define RCC_CSR_WWDGRSTF 0x40000000U
5041 #define RCC_CSR_LPWRRSTF 0x80000000U
5042 
5043 /******************** Bit definition for RCC_SSCGR register *****************/
5044 #define RCC_SSCGR_MODPER 0x00001FFFU
5045 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5046 #define RCC_SSCGR_SPREADSEL 0x40000000U
5047 #define RCC_SSCGR_SSCGEN 0x80000000U
5048 
5049 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5050 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5051 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5052 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5053 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5054 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5055 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5056 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5057 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5058 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5059 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5060 
5061 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5062 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5063 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5064 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5065 
5066 /******************************************************************************/
5067 /* */
5068 /* RNG */
5069 /* */
5070 /******************************************************************************/
5071 /******************** Bits definition for RNG_CR register *******************/
5072 #define RNG_CR_RNGEN 0x00000004U
5073 #define RNG_CR_IE 0x00000008U
5074 
5075 /******************** Bits definition for RNG_SR register *******************/
5076 #define RNG_SR_DRDY 0x00000001U
5077 #define RNG_SR_CECS 0x00000002U
5078 #define RNG_SR_SECS 0x00000004U
5079 #define RNG_SR_CEIS 0x00000020U
5080 #define RNG_SR_SEIS 0x00000040U
5081 
5082 /******************************************************************************/
5083 /* */
5084 /* Real-Time Clock (RTC) */
5085 /* */
5086 /******************************************************************************/
5087 /******************** Bits definition for RTC_TR register *******************/
5088 #define RTC_TR_PM 0x00400000U
5089 #define RTC_TR_HT 0x00300000U
5090 #define RTC_TR_HT_0 0x00100000U
5091 #define RTC_TR_HT_1 0x00200000U
5092 #define RTC_TR_HU 0x000F0000U
5093 #define RTC_TR_HU_0 0x00010000U
5094 #define RTC_TR_HU_1 0x00020000U
5095 #define RTC_TR_HU_2 0x00040000U
5096 #define RTC_TR_HU_3 0x00080000U
5097 #define RTC_TR_MNT 0x00007000U
5098 #define RTC_TR_MNT_0 0x00001000U
5099 #define RTC_TR_MNT_1 0x00002000U
5100 #define RTC_TR_MNT_2 0x00004000U
5101 #define RTC_TR_MNU 0x00000F00U
5102 #define RTC_TR_MNU_0 0x00000100U
5103 #define RTC_TR_MNU_1 0x00000200U
5104 #define RTC_TR_MNU_2 0x00000400U
5105 #define RTC_TR_MNU_3 0x00000800U
5106 #define RTC_TR_ST 0x00000070U
5107 #define RTC_TR_ST_0 0x00000010U
5108 #define RTC_TR_ST_1 0x00000020U
5109 #define RTC_TR_ST_2 0x00000040U
5110 #define RTC_TR_SU 0x0000000FU
5111 #define RTC_TR_SU_0 0x00000001U
5112 #define RTC_TR_SU_1 0x00000002U
5113 #define RTC_TR_SU_2 0x00000004U
5114 #define RTC_TR_SU_3 0x00000008U
5115 
5116 /******************** Bits definition for RTC_DR register *******************/
5117 #define RTC_DR_YT 0x00F00000U
5118 #define RTC_DR_YT_0 0x00100000U
5119 #define RTC_DR_YT_1 0x00200000U
5120 #define RTC_DR_YT_2 0x00400000U
5121 #define RTC_DR_YT_3 0x00800000U
5122 #define RTC_DR_YU 0x000F0000U
5123 #define RTC_DR_YU_0 0x00010000U
5124 #define RTC_DR_YU_1 0x00020000U
5125 #define RTC_DR_YU_2 0x00040000U
5126 #define RTC_DR_YU_3 0x00080000U
5127 #define RTC_DR_WDU 0x0000E000U
5128 #define RTC_DR_WDU_0 0x00002000U
5129 #define RTC_DR_WDU_1 0x00004000U
5130 #define RTC_DR_WDU_2 0x00008000U
5131 #define RTC_DR_MT 0x00001000U
5132 #define RTC_DR_MU 0x00000F00U
5133 #define RTC_DR_MU_0 0x00000100U
5134 #define RTC_DR_MU_1 0x00000200U
5135 #define RTC_DR_MU_2 0x00000400U
5136 #define RTC_DR_MU_3 0x00000800U
5137 #define RTC_DR_DT 0x00000030U
5138 #define RTC_DR_DT_0 0x00000010U
5139 #define RTC_DR_DT_1 0x00000020U
5140 #define RTC_DR_DU 0x0000000FU
5141 #define RTC_DR_DU_0 0x00000001U
5142 #define RTC_DR_DU_1 0x00000002U
5143 #define RTC_DR_DU_2 0x00000004U
5144 #define RTC_DR_DU_3 0x00000008U
5145 
5146 /******************** Bits definition for RTC_CR register *******************/
5147 #define RTC_CR_COE 0x00800000U
5148 #define RTC_CR_OSEL 0x00600000U
5149 #define RTC_CR_OSEL_0 0x00200000U
5150 #define RTC_CR_OSEL_1 0x00400000U
5151 #define RTC_CR_POL 0x00100000U
5152 #define RTC_CR_COSEL 0x00080000U
5153 #define RTC_CR_BCK 0x00040000U
5154 #define RTC_CR_SUB1H 0x00020000U
5155 #define RTC_CR_ADD1H 0x00010000U
5156 #define RTC_CR_TSIE 0x00008000U
5157 #define RTC_CR_WUTIE 0x00004000U
5158 #define RTC_CR_ALRBIE 0x00002000U
5159 #define RTC_CR_ALRAIE 0x00001000U
5160 #define RTC_CR_TSE 0x00000800U
5161 #define RTC_CR_WUTE 0x00000400U
5162 #define RTC_CR_ALRBE 0x00000200U
5163 #define RTC_CR_ALRAE 0x00000100U
5164 #define RTC_CR_DCE 0x00000080U
5165 #define RTC_CR_FMT 0x00000040U
5166 #define RTC_CR_BYPSHAD 0x00000020U
5167 #define RTC_CR_REFCKON 0x00000010U
5168 #define RTC_CR_TSEDGE 0x00000008U
5169 #define RTC_CR_WUCKSEL 0x00000007U
5170 #define RTC_CR_WUCKSEL_0 0x00000001U
5171 #define RTC_CR_WUCKSEL_1 0x00000002U
5172 #define RTC_CR_WUCKSEL_2 0x00000004U
5173 
5174 /******************** Bits definition for RTC_ISR register ******************/
5175 #define RTC_ISR_RECALPF 0x00010000U
5176 #define RTC_ISR_TAMP1F 0x00002000U
5177 #define RTC_ISR_TAMP2F 0x00004000U
5178 #define RTC_ISR_TSOVF 0x00001000U
5179 #define RTC_ISR_TSF 0x00000800U
5180 #define RTC_ISR_WUTF 0x00000400U
5181 #define RTC_ISR_ALRBF 0x00000200U
5182 #define RTC_ISR_ALRAF 0x00000100U
5183 #define RTC_ISR_INIT 0x00000080U
5184 #define RTC_ISR_INITF 0x00000040U
5185 #define RTC_ISR_RSF 0x00000020U
5186 #define RTC_ISR_INITS 0x00000010U
5187 #define RTC_ISR_SHPF 0x00000008U
5188 #define RTC_ISR_WUTWF 0x00000004U
5189 #define RTC_ISR_ALRBWF 0x00000002U
5190 #define RTC_ISR_ALRAWF 0x00000001U
5191 
5192 /******************** Bits definition for RTC_PRER register *****************/
5193 #define RTC_PRER_PREDIV_A 0x007F0000U
5194 #define RTC_PRER_PREDIV_S 0x00007FFFU
5195 
5196 /******************** Bits definition for RTC_WUTR register *****************/
5197 #define RTC_WUTR_WUT 0x0000FFFFU
5198 
5199 /******************** Bits definition for RTC_CALIBR register ***************/
5200 #define RTC_CALIBR_DCS 0x00000080U
5201 #define RTC_CALIBR_DC 0x0000001FU
5202 
5203 /******************** Bits definition for RTC_ALRMAR register ***************/
5204 #define RTC_ALRMAR_MSK4 0x80000000U
5205 #define RTC_ALRMAR_WDSEL 0x40000000U
5206 #define RTC_ALRMAR_DT 0x30000000U
5207 #define RTC_ALRMAR_DT_0 0x10000000U
5208 #define RTC_ALRMAR_DT_1 0x20000000U
5209 #define RTC_ALRMAR_DU 0x0F000000U
5210 #define RTC_ALRMAR_DU_0 0x01000000U
5211 #define RTC_ALRMAR_DU_1 0x02000000U
5212 #define RTC_ALRMAR_DU_2 0x04000000U
5213 #define RTC_ALRMAR_DU_3 0x08000000U
5214 #define RTC_ALRMAR_MSK3 0x00800000U
5215 #define RTC_ALRMAR_PM 0x00400000U
5216 #define RTC_ALRMAR_HT 0x00300000U
5217 #define RTC_ALRMAR_HT_0 0x00100000U
5218 #define RTC_ALRMAR_HT_1 0x00200000U
5219 #define RTC_ALRMAR_HU 0x000F0000U
5220 #define RTC_ALRMAR_HU_0 0x00010000U
5221 #define RTC_ALRMAR_HU_1 0x00020000U
5222 #define RTC_ALRMAR_HU_2 0x00040000U
5223 #define RTC_ALRMAR_HU_3 0x00080000U
5224 #define RTC_ALRMAR_MSK2 0x00008000U
5225 #define RTC_ALRMAR_MNT 0x00007000U
5226 #define RTC_ALRMAR_MNT_0 0x00001000U
5227 #define RTC_ALRMAR_MNT_1 0x00002000U
5228 #define RTC_ALRMAR_MNT_2 0x00004000U
5229 #define RTC_ALRMAR_MNU 0x00000F00U
5230 #define RTC_ALRMAR_MNU_0 0x00000100U
5231 #define RTC_ALRMAR_MNU_1 0x00000200U
5232 #define RTC_ALRMAR_MNU_2 0x00000400U
5233 #define RTC_ALRMAR_MNU_3 0x00000800U
5234 #define RTC_ALRMAR_MSK1 0x00000080U
5235 #define RTC_ALRMAR_ST 0x00000070U
5236 #define RTC_ALRMAR_ST_0 0x00000010U
5237 #define RTC_ALRMAR_ST_1 0x00000020U
5238 #define RTC_ALRMAR_ST_2 0x00000040U
5239 #define RTC_ALRMAR_SU 0x0000000FU
5240 #define RTC_ALRMAR_SU_0 0x00000001U
5241 #define RTC_ALRMAR_SU_1 0x00000002U
5242 #define RTC_ALRMAR_SU_2 0x00000004U
5243 #define RTC_ALRMAR_SU_3 0x00000008U
5244 
5245 /******************** Bits definition for RTC_ALRMBR register ***************/
5246 #define RTC_ALRMBR_MSK4 0x80000000U
5247 #define RTC_ALRMBR_WDSEL 0x40000000U
5248 #define RTC_ALRMBR_DT 0x30000000U
5249 #define RTC_ALRMBR_DT_0 0x10000000U
5250 #define RTC_ALRMBR_DT_1 0x20000000U
5251 #define RTC_ALRMBR_DU 0x0F000000U
5252 #define RTC_ALRMBR_DU_0 0x01000000U
5253 #define RTC_ALRMBR_DU_1 0x02000000U
5254 #define RTC_ALRMBR_DU_2 0x04000000U
5255 #define RTC_ALRMBR_DU_3 0x08000000U
5256 #define RTC_ALRMBR_MSK3 0x00800000U
5257 #define RTC_ALRMBR_PM 0x00400000U
5258 #define RTC_ALRMBR_HT 0x00300000U
5259 #define RTC_ALRMBR_HT_0 0x00100000U
5260 #define RTC_ALRMBR_HT_1 0x00200000U
5261 #define RTC_ALRMBR_HU 0x000F0000U
5262 #define RTC_ALRMBR_HU_0 0x00010000U
5263 #define RTC_ALRMBR_HU_1 0x00020000U
5264 #define RTC_ALRMBR_HU_2 0x00040000U
5265 #define RTC_ALRMBR_HU_3 0x00080000U
5266 #define RTC_ALRMBR_MSK2 0x00008000U
5267 #define RTC_ALRMBR_MNT 0x00007000U
5268 #define RTC_ALRMBR_MNT_0 0x00001000U
5269 #define RTC_ALRMBR_MNT_1 0x00002000U
5270 #define RTC_ALRMBR_MNT_2 0x00004000U
5271 #define RTC_ALRMBR_MNU 0x00000F00U
5272 #define RTC_ALRMBR_MNU_0 0x00000100U
5273 #define RTC_ALRMBR_MNU_1 0x00000200U
5274 #define RTC_ALRMBR_MNU_2 0x00000400U
5275 #define RTC_ALRMBR_MNU_3 0x00000800U
5276 #define RTC_ALRMBR_MSK1 0x00000080U
5277 #define RTC_ALRMBR_ST 0x00000070U
5278 #define RTC_ALRMBR_ST_0 0x00000010U
5279 #define RTC_ALRMBR_ST_1 0x00000020U
5280 #define RTC_ALRMBR_ST_2 0x00000040U
5281 #define RTC_ALRMBR_SU 0x0000000FU
5282 #define RTC_ALRMBR_SU_0 0x00000001U
5283 #define RTC_ALRMBR_SU_1 0x00000002U
5284 #define RTC_ALRMBR_SU_2 0x00000004U
5285 #define RTC_ALRMBR_SU_3 0x00000008U
5286 
5287 /******************** Bits definition for RTC_WPR register ******************/
5288 #define RTC_WPR_KEY 0x000000FFU
5289 
5290 /******************** Bits definition for RTC_SSR register ******************/
5291 #define RTC_SSR_SS 0x0000FFFFU
5292 
5293 /******************** Bits definition for RTC_SHIFTR register ***************/
5294 #define RTC_SHIFTR_SUBFS 0x00007FFFU
5295 #define RTC_SHIFTR_ADD1S 0x80000000U
5296 
5297 /******************** Bits definition for RTC_TSTR register *****************/
5298 #define RTC_TSTR_PM 0x00400000U
5299 #define RTC_TSTR_HT 0x00300000U
5300 #define RTC_TSTR_HT_0 0x00100000U
5301 #define RTC_TSTR_HT_1 0x00200000U
5302 #define RTC_TSTR_HU 0x000F0000U
5303 #define RTC_TSTR_HU_0 0x00010000U
5304 #define RTC_TSTR_HU_1 0x00020000U
5305 #define RTC_TSTR_HU_2 0x00040000U
5306 #define RTC_TSTR_HU_3 0x00080000U
5307 #define RTC_TSTR_MNT 0x00007000U
5308 #define RTC_TSTR_MNT_0 0x00001000U
5309 #define RTC_TSTR_MNT_1 0x00002000U
5310 #define RTC_TSTR_MNT_2 0x00004000U
5311 #define RTC_TSTR_MNU 0x00000F00U
5312 #define RTC_TSTR_MNU_0 0x00000100U
5313 #define RTC_TSTR_MNU_1 0x00000200U
5314 #define RTC_TSTR_MNU_2 0x00000400U
5315 #define RTC_TSTR_MNU_3 0x00000800U
5316 #define RTC_TSTR_ST 0x00000070U
5317 #define RTC_TSTR_ST_0 0x00000010U
5318 #define RTC_TSTR_ST_1 0x00000020U
5319 #define RTC_TSTR_ST_2 0x00000040U
5320 #define RTC_TSTR_SU 0x0000000FU
5321 #define RTC_TSTR_SU_0 0x00000001U
5322 #define RTC_TSTR_SU_1 0x00000002U
5323 #define RTC_TSTR_SU_2 0x00000004U
5324 #define RTC_TSTR_SU_3 0x00000008U
5325 
5326 /******************** Bits definition for RTC_TSDR register *****************/
5327 #define RTC_TSDR_WDU 0x0000E000U
5328 #define RTC_TSDR_WDU_0 0x00002000U
5329 #define RTC_TSDR_WDU_1 0x00004000U
5330 #define RTC_TSDR_WDU_2 0x00008000U
5331 #define RTC_TSDR_MT 0x00001000U
5332 #define RTC_TSDR_MU 0x00000F00U
5333 #define RTC_TSDR_MU_0 0x00000100U
5334 #define RTC_TSDR_MU_1 0x00000200U
5335 #define RTC_TSDR_MU_2 0x00000400U
5336 #define RTC_TSDR_MU_3 0x00000800U
5337 #define RTC_TSDR_DT 0x00000030U
5338 #define RTC_TSDR_DT_0 0x00000010U
5339 #define RTC_TSDR_DT_1 0x00000020U
5340 #define RTC_TSDR_DU 0x0000000FU
5341 #define RTC_TSDR_DU_0 0x00000001U
5342 #define RTC_TSDR_DU_1 0x00000002U
5343 #define RTC_TSDR_DU_2 0x00000004U
5344 #define RTC_TSDR_DU_3 0x00000008U
5345 
5346 /******************** Bits definition for RTC_TSSSR register ****************/
5347 #define RTC_TSSSR_SS 0x0000FFFFU
5348 
5349 /******************** Bits definition for RTC_CAL register *****************/
5350 #define RTC_CALR_CALP 0x00008000U
5351 #define RTC_CALR_CALW8 0x00004000U
5352 #define RTC_CALR_CALW16 0x00002000U
5353 #define RTC_CALR_CALM 0x000001FFU
5354 #define RTC_CALR_CALM_0 0x00000001U
5355 #define RTC_CALR_CALM_1 0x00000002U
5356 #define RTC_CALR_CALM_2 0x00000004U
5357 #define RTC_CALR_CALM_3 0x00000008U
5358 #define RTC_CALR_CALM_4 0x00000010U
5359 #define RTC_CALR_CALM_5 0x00000020U
5360 #define RTC_CALR_CALM_6 0x00000040U
5361 #define RTC_CALR_CALM_7 0x00000080U
5362 #define RTC_CALR_CALM_8 0x00000100U
5363 
5364 /******************** Bits definition for RTC_TAFCR register ****************/
5365 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
5366 #define RTC_TAFCR_TSINSEL 0x00020000U
5367 #define RTC_TAFCR_TAMPINSEL 0x00010000U
5368 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
5369 #define RTC_TAFCR_TAMPPRCH 0x00006000U
5370 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
5371 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
5372 #define RTC_TAFCR_TAMPFLT 0x00001800U
5373 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
5374 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
5375 #define RTC_TAFCR_TAMPFREQ 0x00000700U
5376 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
5377 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
5378 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
5379 #define RTC_TAFCR_TAMPTS 0x00000080U
5380 #define RTC_TAFCR_TAMP2TRG 0x00000010U
5381 #define RTC_TAFCR_TAMP2E 0x00000008U
5382 #define RTC_TAFCR_TAMPIE 0x00000004U
5383 #define RTC_TAFCR_TAMP1TRG 0x00000002U
5384 #define RTC_TAFCR_TAMP1E 0x00000001U
5385 
5386 /******************** Bits definition for RTC_ALRMASSR register *************/
5387 #define RTC_ALRMASSR_MASKSS 0x0F000000U
5388 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
5389 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
5390 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
5391 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
5392 #define RTC_ALRMASSR_SS 0x00007FFFU
5393 
5394 /******************** Bits definition for RTC_ALRMBSSR register *************/
5395 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
5396 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
5397 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
5398 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
5399 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
5400 #define RTC_ALRMBSSR_SS 0x00007FFFU
5401 
5402 /******************** Bits definition for RTC_BKP0R register ****************/
5403 #define RTC_BKP0R 0xFFFFFFFFU
5404 
5405 /******************** Bits definition for RTC_BKP1R register ****************/
5406 #define RTC_BKP1R 0xFFFFFFFFU
5407 
5408 /******************** Bits definition for RTC_BKP2R register ****************/
5409 #define RTC_BKP2R 0xFFFFFFFFU
5410 
5411 /******************** Bits definition for RTC_BKP3R register ****************/
5412 #define RTC_BKP3R 0xFFFFFFFFU
5413 
5414 /******************** Bits definition for RTC_BKP4R register ****************/
5415 #define RTC_BKP4R 0xFFFFFFFFU
5416 
5417 /******************** Bits definition for RTC_BKP5R register ****************/
5418 #define RTC_BKP5R 0xFFFFFFFFU
5419 
5420 /******************** Bits definition for RTC_BKP6R register ****************/
5421 #define RTC_BKP6R 0xFFFFFFFFU
5422 
5423 /******************** Bits definition for RTC_BKP7R register ****************/
5424 #define RTC_BKP7R 0xFFFFFFFFU
5425 
5426 /******************** Bits definition for RTC_BKP8R register ****************/
5427 #define RTC_BKP8R 0xFFFFFFFFU
5428 
5429 /******************** Bits definition for RTC_BKP9R register ****************/
5430 #define RTC_BKP9R 0xFFFFFFFFU
5431 
5432 /******************** Bits definition for RTC_BKP10R register ***************/
5433 #define RTC_BKP10R 0xFFFFFFFFU
5434 
5435 /******************** Bits definition for RTC_BKP11R register ***************/
5436 #define RTC_BKP11R 0xFFFFFFFFU
5437 
5438 /******************** Bits definition for RTC_BKP12R register ***************/
5439 #define RTC_BKP12R 0xFFFFFFFFU
5440 
5441 /******************** Bits definition for RTC_BKP13R register ***************/
5442 #define RTC_BKP13R 0xFFFFFFFFU
5443 
5444 /******************** Bits definition for RTC_BKP14R register ***************/
5445 #define RTC_BKP14R 0xFFFFFFFFU
5446 
5447 /******************** Bits definition for RTC_BKP15R register ***************/
5448 #define RTC_BKP15R 0xFFFFFFFFU
5449 
5450 /******************** Bits definition for RTC_BKP16R register ***************/
5451 #define RTC_BKP16R 0xFFFFFFFFU
5452 
5453 /******************** Bits definition for RTC_BKP17R register ***************/
5454 #define RTC_BKP17R 0xFFFFFFFFU
5455 
5456 /******************** Bits definition for RTC_BKP18R register ***************/
5457 #define RTC_BKP18R 0xFFFFFFFFU
5458 
5459 /******************** Bits definition for RTC_BKP19R register ***************/
5460 #define RTC_BKP19R 0xFFFFFFFFU
5461 
5462 
5463 
5464 /******************************************************************************/
5465 /* */
5466 /* SD host Interface */
5467 /* */
5468 /******************************************************************************/
5469 /****************** Bit definition for SDIO_POWER register ******************/
5470 #define SDIO_POWER_PWRCTRL 0x03U
5471 #define SDIO_POWER_PWRCTRL_0 0x01U
5472 #define SDIO_POWER_PWRCTRL_1 0x02U
5474 /****************** Bit definition for SDIO_CLKCR register ******************/
5475 #define SDIO_CLKCR_CLKDIV 0x00FFU
5476 #define SDIO_CLKCR_CLKEN 0x0100U
5477 #define SDIO_CLKCR_PWRSAV 0x0200U
5478 #define SDIO_CLKCR_BYPASS 0x0400U
5480 #define SDIO_CLKCR_WIDBUS 0x1800U
5481 #define SDIO_CLKCR_WIDBUS_0 0x0800U
5482 #define SDIO_CLKCR_WIDBUS_1 0x1000U
5484 #define SDIO_CLKCR_NEGEDGE 0x2000U
5485 #define SDIO_CLKCR_HWFC_EN 0x4000U
5487 /******************* Bit definition for SDIO_ARG register *******************/
5488 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
5490 /******************* Bit definition for SDIO_CMD register *******************/
5491 #define SDIO_CMD_CMDINDEX 0x003FU
5493 #define SDIO_CMD_WAITRESP 0x00C0U
5494 #define SDIO_CMD_WAITRESP_0 0x0040U
5495 #define SDIO_CMD_WAITRESP_1 0x0080U
5497 #define SDIO_CMD_WAITINT 0x0100U
5498 #define SDIO_CMD_WAITPEND 0x0200U
5499 #define SDIO_CMD_CPSMEN 0x0400U
5500 #define SDIO_CMD_SDIOSUSPEND 0x0800U
5501 #define SDIO_CMD_ENCMDCOMPL 0x1000U
5502 #define SDIO_CMD_NIEN 0x2000U
5503 #define SDIO_CMD_CEATACMD 0x4000U
5505 /***************** Bit definition for SDIO_RESPCMD register *****************/
5506 #define SDIO_RESPCMD_RESPCMD 0x3FU
5508 /****************** Bit definition for SDIO_RESP0 register ******************/
5509 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
5511 /****************** Bit definition for SDIO_RESP1 register ******************/
5512 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
5514 /****************** Bit definition for SDIO_RESP2 register ******************/
5515 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
5517 /****************** Bit definition for SDIO_RESP3 register ******************/
5518 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
5520 /****************** Bit definition for SDIO_RESP4 register ******************/
5521 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
5523 /****************** Bit definition for SDIO_DTIMER register *****************/
5524 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
5526 /****************** Bit definition for SDIO_DLEN register *******************/
5527 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
5529 /****************** Bit definition for SDIO_DCTRL register ******************/
5530 #define SDIO_DCTRL_DTEN 0x0001U
5531 #define SDIO_DCTRL_DTDIR 0x0002U
5532 #define SDIO_DCTRL_DTMODE 0x0004U
5533 #define SDIO_DCTRL_DMAEN 0x0008U
5535 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
5536 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
5537 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
5538 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
5539 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
5541 #define SDIO_DCTRL_RWSTART 0x0100U
5542 #define SDIO_DCTRL_RWSTOP 0x0200U
5543 #define SDIO_DCTRL_RWMOD 0x0400U
5544 #define SDIO_DCTRL_SDIOEN 0x0800U
5546 /****************** Bit definition for SDIO_DCOUNT register *****************/
5547 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
5549 /****************** Bit definition for SDIO_STA register ********************/
5550 #define SDIO_STA_CCRCFAIL 0x00000001U
5551 #define SDIO_STA_DCRCFAIL 0x00000002U
5552 #define SDIO_STA_CTIMEOUT 0x00000004U
5553 #define SDIO_STA_DTIMEOUT 0x00000008U
5554 #define SDIO_STA_TXUNDERR 0x00000010U
5555 #define SDIO_STA_RXOVERR 0x00000020U
5556 #define SDIO_STA_CMDREND 0x00000040U
5557 #define SDIO_STA_CMDSENT 0x00000080U
5558 #define SDIO_STA_DATAEND 0x00000100U
5559 #define SDIO_STA_STBITERR 0x00000200U
5560 #define SDIO_STA_DBCKEND 0x00000400U
5561 #define SDIO_STA_CMDACT 0x00000800U
5562 #define SDIO_STA_TXACT 0x00001000U
5563 #define SDIO_STA_RXACT 0x00002000U
5564 #define SDIO_STA_TXFIFOHE 0x00004000U
5565 #define SDIO_STA_RXFIFOHF 0x00008000U
5566 #define SDIO_STA_TXFIFOF 0x00010000U
5567 #define SDIO_STA_RXFIFOF 0x00020000U
5568 #define SDIO_STA_TXFIFOE 0x00040000U
5569 #define SDIO_STA_RXFIFOE 0x00080000U
5570 #define SDIO_STA_TXDAVL 0x00100000U
5571 #define SDIO_STA_RXDAVL 0x00200000U
5572 #define SDIO_STA_SDIOIT 0x00400000U
5573 #define SDIO_STA_CEATAEND 0x00800000U
5575 /******************* Bit definition for SDIO_ICR register *******************/
5576 #define SDIO_ICR_CCRCFAILC 0x00000001U
5577 #define SDIO_ICR_DCRCFAILC 0x00000002U
5578 #define SDIO_ICR_CTIMEOUTC 0x00000004U
5579 #define SDIO_ICR_DTIMEOUTC 0x00000008U
5580 #define SDIO_ICR_TXUNDERRC 0x00000010U
5581 #define SDIO_ICR_RXOVERRC 0x00000020U
5582 #define SDIO_ICR_CMDRENDC 0x00000040U
5583 #define SDIO_ICR_CMDSENTC 0x00000080U
5584 #define SDIO_ICR_DATAENDC 0x00000100U
5585 #define SDIO_ICR_STBITERRC 0x00000200U
5586 #define SDIO_ICR_DBCKENDC 0x00000400U
5587 #define SDIO_ICR_SDIOITC 0x00400000U
5588 #define SDIO_ICR_CEATAENDC 0x00800000U
5590 /****************** Bit definition for SDIO_MASK register *******************/
5591 #define SDIO_MASK_CCRCFAILIE 0x00000001U
5592 #define SDIO_MASK_DCRCFAILIE 0x00000002U
5593 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
5594 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
5595 #define SDIO_MASK_TXUNDERRIE 0x00000010U
5596 #define SDIO_MASK_RXOVERRIE 0x00000020U
5597 #define SDIO_MASK_CMDRENDIE 0x00000040U
5598 #define SDIO_MASK_CMDSENTIE 0x00000080U
5599 #define SDIO_MASK_DATAENDIE 0x00000100U
5600 #define SDIO_MASK_STBITERRIE 0x00000200U
5601 #define SDIO_MASK_DBCKENDIE 0x00000400U
5602 #define SDIO_MASK_CMDACTIE 0x00000800U
5603 #define SDIO_MASK_TXACTIE 0x00001000U
5604 #define SDIO_MASK_RXACTIE 0x00002000U
5605 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
5606 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
5607 #define SDIO_MASK_TXFIFOFIE 0x00010000U
5608 #define SDIO_MASK_RXFIFOFIE 0x00020000U
5609 #define SDIO_MASK_TXFIFOEIE 0x00040000U
5610 #define SDIO_MASK_RXFIFOEIE 0x00080000U
5611 #define SDIO_MASK_TXDAVLIE 0x00100000U
5612 #define SDIO_MASK_RXDAVLIE 0x00200000U
5613 #define SDIO_MASK_SDIOITIE 0x00400000U
5614 #define SDIO_MASK_CEATAENDIE 0x00800000U
5616 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5617 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
5619 /****************** Bit definition for SDIO_FIFO register *******************/
5620 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
5622 /******************************************************************************/
5623 /* */
5624 /* Serial Peripheral Interface */
5625 /* */
5626 /******************************************************************************/
5627 /******************* Bit definition for SPI_CR1 register ********************/
5628 #define SPI_CR1_CPHA 0x00000001U
5629 #define SPI_CR1_CPOL 0x00000002U
5630 #define SPI_CR1_MSTR 0x00000004U
5632 #define SPI_CR1_BR 0x00000038U
5633 #define SPI_CR1_BR_0 0x00000008U
5634 #define SPI_CR1_BR_1 0x00000010U
5635 #define SPI_CR1_BR_2 0x00000020U
5637 #define SPI_CR1_SPE 0x00000040U
5638 #define SPI_CR1_LSBFIRST 0x00000080U
5639 #define SPI_CR1_SSI 0x00000100U
5640 #define SPI_CR1_SSM 0x00000200U
5641 #define SPI_CR1_RXONLY 0x00000400U
5642 #define SPI_CR1_DFF 0x00000800U
5643 #define SPI_CR1_CRCNEXT 0x00001000U
5644 #define SPI_CR1_CRCEN 0x00002000U
5645 #define SPI_CR1_BIDIOE 0x00004000U
5646 #define SPI_CR1_BIDIMODE 0x00008000U
5648 /******************* Bit definition for SPI_CR2 register ********************/
5649 #define SPI_CR2_RXDMAEN 0x00000001U
5650 #define SPI_CR2_TXDMAEN 0x00000002U
5651 #define SPI_CR2_SSOE 0x00000004U
5652 #define SPI_CR2_FRF 0x00000010U
5653 #define SPI_CR2_ERRIE 0x00000020U
5654 #define SPI_CR2_RXNEIE 0x00000040U
5655 #define SPI_CR2_TXEIE 0x00000080U
5657 /******************** Bit definition for SPI_SR register ********************/
5658 #define SPI_SR_RXNE 0x00000001U
5659 #define SPI_SR_TXE 0x00000002U
5660 #define SPI_SR_CHSIDE 0x00000004U
5661 #define SPI_SR_UDR 0x00000008U
5662 #define SPI_SR_CRCERR 0x00000010U
5663 #define SPI_SR_MODF 0x00000020U
5664 #define SPI_SR_OVR 0x00000040U
5665 #define SPI_SR_BSY 0x00000080U
5666 #define SPI_SR_FRE 0x00000100U
5668 /******************** Bit definition for SPI_DR register ********************/
5669 #define SPI_DR_DR 0x0000FFFFU
5671 /******************* Bit definition for SPI_CRCPR register ******************/
5672 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
5674 /****************** Bit definition for SPI_RXCRCR register ******************/
5675 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
5677 /****************** Bit definition for SPI_TXCRCR register ******************/
5678 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
5680 /****************** Bit definition for SPI_I2SCFGR register *****************/
5681 #define SPI_I2SCFGR_CHLEN 0x00000001U
5683 #define SPI_I2SCFGR_DATLEN 0x00000006U
5684 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
5685 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
5687 #define SPI_I2SCFGR_CKPOL 0x00000008U
5689 #define SPI_I2SCFGR_I2SSTD 0x00000030U
5690 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
5691 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
5693 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
5695 #define SPI_I2SCFGR_I2SCFG 0x00000300U
5696 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
5697 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
5699 #define SPI_I2SCFGR_I2SE 0x00000400U
5700 #define SPI_I2SCFGR_I2SMOD 0x00000800U
5702 /****************** Bit definition for SPI_I2SPR register *******************/
5703 #define SPI_I2SPR_I2SDIV 0x000000FFU
5704 #define SPI_I2SPR_ODD 0x00000100U
5705 #define SPI_I2SPR_MCKOE 0x00000200U
5707 /******************************************************************************/
5708 /* */
5709 /* SYSCFG */
5710 /* */
5711 /******************************************************************************/
5712 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
5713 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
5714 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
5715 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
5716 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
5717 
5718 /****************** Bit definition for SYSCFG_PMC register ******************/
5719 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
5720 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
5721 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
5722 
5723 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5724 #define SYSCFG_EXTICR1_EXTI0 0x000FU
5725 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
5726 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
5727 #define SYSCFG_EXTICR1_EXTI3 0xF000U
5731 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
5732 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
5733 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
5734 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
5735 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
5736 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
5737 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
5738 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
5739 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
5744 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
5745 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
5746 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
5747 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
5748 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
5749 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
5750 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
5751 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
5752 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
5757 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
5758 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
5759 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
5760 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
5761 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
5762 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
5763 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
5764 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
5765 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
5770 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
5771 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
5772 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
5773 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
5774 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
5775 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
5776 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
5777 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
5778 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
5780 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5781 #define SYSCFG_EXTICR2_EXTI4 0x000FU
5782 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
5783 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
5784 #define SYSCFG_EXTICR2_EXTI7 0xF000U
5788 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
5789 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
5790 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
5791 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
5792 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
5793 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
5794 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
5795 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
5796 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
5801 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
5802 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
5803 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
5804 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
5805 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
5806 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
5807 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
5808 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
5809 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
5814 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
5815 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
5816 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
5817 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
5818 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
5819 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
5820 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
5821 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
5822 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
5827 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
5828 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
5829 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
5830 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
5831 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
5832 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
5833 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
5834 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
5835 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
5838 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5839 #define SYSCFG_EXTICR3_EXTI8 0x000FU
5840 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
5841 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
5842 #define SYSCFG_EXTICR3_EXTI11 0xF000U
5847 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
5848 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
5849 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
5850 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
5851 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
5852 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
5853 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
5854 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
5855 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
5860 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
5861 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
5862 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
5863 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
5864 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
5865 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
5866 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
5867 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
5868 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
5873 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
5874 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
5875 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
5876 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
5877 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
5878 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
5879 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
5880 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
5881 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
5886 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
5887 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
5888 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
5889 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
5890 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
5891 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
5892 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
5893 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
5894 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
5896 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5897 #define SYSCFG_EXTICR4_EXTI12 0x000FU
5898 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
5899 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
5900 #define SYSCFG_EXTICR4_EXTI15 0xF000U
5904 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
5905 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
5906 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
5907 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
5908 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
5909 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
5910 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
5911 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
5916 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
5917 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
5918 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
5919 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
5920 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
5921 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
5922 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
5923 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
5928 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
5929 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
5930 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
5931 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
5932 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
5933 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
5934 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
5935 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
5940 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
5941 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
5942 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
5943 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
5944 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
5945 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
5946 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
5947 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
5949 /****************** Bit definition for SYSCFG_CMPCR register ****************/
5950 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
5951 #define SYSCFG_CMPCR_READY 0x00000100U
5953 /******************************************************************************/
5954 /* */
5955 /* TIM */
5956 /* */
5957 /******************************************************************************/
5958 /******************* Bit definition for TIM_CR1 register ********************/
5959 #define TIM_CR1_CEN 0x0001U
5960 #define TIM_CR1_UDIS 0x0002U
5961 #define TIM_CR1_URS 0x0004U
5962 #define TIM_CR1_OPM 0x0008U
5963 #define TIM_CR1_DIR 0x0010U
5965 #define TIM_CR1_CMS 0x0060U
5966 #define TIM_CR1_CMS_0 0x0020U
5967 #define TIM_CR1_CMS_1 0x0040U
5969 #define TIM_CR1_ARPE 0x0080U
5971 #define TIM_CR1_CKD 0x0300U
5972 #define TIM_CR1_CKD_0 0x0100U
5973 #define TIM_CR1_CKD_1 0x0200U
5975 /******************* Bit definition for TIM_CR2 register ********************/
5976 #define TIM_CR2_CCPC 0x0001U
5977 #define TIM_CR2_CCUS 0x0004U
5978 #define TIM_CR2_CCDS 0x0008U
5980 #define TIM_CR2_MMS 0x0070U
5981 #define TIM_CR2_MMS_0 0x0010U
5982 #define TIM_CR2_MMS_1 0x0020U
5983 #define TIM_CR2_MMS_2 0x0040U
5985 #define TIM_CR2_TI1S 0x0080U
5986 #define TIM_CR2_OIS1 0x0100U
5987 #define TIM_CR2_OIS1N 0x0200U
5988 #define TIM_CR2_OIS2 0x0400U
5989 #define TIM_CR2_OIS2N 0x0800U
5990 #define TIM_CR2_OIS3 0x1000U
5991 #define TIM_CR2_OIS3N 0x2000U
5992 #define TIM_CR2_OIS4 0x4000U
5994 /******************* Bit definition for TIM_SMCR register *******************/
5995 #define TIM_SMCR_SMS 0x0007U
5996 #define TIM_SMCR_SMS_0 0x0001U
5997 #define TIM_SMCR_SMS_1 0x0002U
5998 #define TIM_SMCR_SMS_2 0x0004U
6000 #define TIM_SMCR_TS 0x0070U
6001 #define TIM_SMCR_TS_0 0x0010U
6002 #define TIM_SMCR_TS_1 0x0020U
6003 #define TIM_SMCR_TS_2 0x0040U
6005 #define TIM_SMCR_MSM 0x0080U
6007 #define TIM_SMCR_ETF 0x0F00U
6008 #define TIM_SMCR_ETF_0 0x0100U
6009 #define TIM_SMCR_ETF_1 0x0200U
6010 #define TIM_SMCR_ETF_2 0x0400U
6011 #define TIM_SMCR_ETF_3 0x0800U
6013 #define TIM_SMCR_ETPS 0x3000U
6014 #define TIM_SMCR_ETPS_0 0x1000U
6015 #define TIM_SMCR_ETPS_1 0x2000U
6017 #define TIM_SMCR_ECE 0x4000U
6018 #define TIM_SMCR_ETP 0x8000U
6020 /******************* Bit definition for TIM_DIER register *******************/
6021 #define TIM_DIER_UIE 0x0001U
6022 #define TIM_DIER_CC1IE 0x0002U
6023 #define TIM_DIER_CC2IE 0x0004U
6024 #define TIM_DIER_CC3IE 0x0008U
6025 #define TIM_DIER_CC4IE 0x0010U
6026 #define TIM_DIER_COMIE 0x0020U
6027 #define TIM_DIER_TIE 0x0040U
6028 #define TIM_DIER_BIE 0x0080U
6029 #define TIM_DIER_UDE 0x0100U
6030 #define TIM_DIER_CC1DE 0x0200U
6031 #define TIM_DIER_CC2DE 0x0400U
6032 #define TIM_DIER_CC3DE 0x0800U
6033 #define TIM_DIER_CC4DE 0x1000U
6034 #define TIM_DIER_COMDE 0x2000U
6035 #define TIM_DIER_TDE 0x4000U
6037 /******************** Bit definition for TIM_SR register ********************/
6038 #define TIM_SR_UIF 0x0001U
6039 #define TIM_SR_CC1IF 0x0002U
6040 #define TIM_SR_CC2IF 0x0004U
6041 #define TIM_SR_CC3IF 0x0008U
6042 #define TIM_SR_CC4IF 0x0010U
6043 #define TIM_SR_COMIF 0x0020U
6044 #define TIM_SR_TIF 0x0040U
6045 #define TIM_SR_BIF 0x0080U
6046 #define TIM_SR_CC1OF 0x0200U
6047 #define TIM_SR_CC2OF 0x0400U
6048 #define TIM_SR_CC3OF 0x0800U
6049 #define TIM_SR_CC4OF 0x1000U
6051 /******************* Bit definition for TIM_EGR register ********************/
6052 #define TIM_EGR_UG 0x01U
6053 #define TIM_EGR_CC1G 0x02U
6054 #define TIM_EGR_CC2G 0x04U
6055 #define TIM_EGR_CC3G 0x08U
6056 #define TIM_EGR_CC4G 0x10U
6057 #define TIM_EGR_COMG 0x20U
6058 #define TIM_EGR_TG 0x40U
6059 #define TIM_EGR_BG 0x80U
6061 /****************** Bit definition for TIM_CCMR1 register *******************/
6062 #define TIM_CCMR1_CC1S 0x0003U
6063 #define TIM_CCMR1_CC1S_0 0x0001U
6064 #define TIM_CCMR1_CC1S_1 0x0002U
6066 #define TIM_CCMR1_OC1FE 0x0004U
6067 #define TIM_CCMR1_OC1PE 0x0008U
6069 #define TIM_CCMR1_OC1M 0x0070U
6070 #define TIM_CCMR1_OC1M_0 0x0010U
6071 #define TIM_CCMR1_OC1M_1 0x0020U
6072 #define TIM_CCMR1_OC1M_2 0x0040U
6074 #define TIM_CCMR1_OC1CE 0x0080U
6076 #define TIM_CCMR1_CC2S 0x0300U
6077 #define TIM_CCMR1_CC2S_0 0x0100U
6078 #define TIM_CCMR1_CC2S_1 0x0200U
6080 #define TIM_CCMR1_OC2FE 0x0400U
6081 #define TIM_CCMR1_OC2PE 0x0800U
6083 #define TIM_CCMR1_OC2M 0x7000U
6084 #define TIM_CCMR1_OC2M_0 0x1000U
6085 #define TIM_CCMR1_OC2M_1 0x2000U
6086 #define TIM_CCMR1_OC2M_2 0x4000U
6088 #define TIM_CCMR1_OC2CE 0x8000U
6090 /*----------------------------------------------------------------------------*/
6091 
6092 #define TIM_CCMR1_IC1PSC 0x000CU
6093 #define TIM_CCMR1_IC1PSC_0 0x0004U
6094 #define TIM_CCMR1_IC1PSC_1 0x0008U
6096 #define TIM_CCMR1_IC1F 0x00F0U
6097 #define TIM_CCMR1_IC1F_0 0x0010U
6098 #define TIM_CCMR1_IC1F_1 0x0020U
6099 #define TIM_CCMR1_IC1F_2 0x0040U
6100 #define TIM_CCMR1_IC1F_3 0x0080U
6102 #define TIM_CCMR1_IC2PSC 0x0C00U
6103 #define TIM_CCMR1_IC2PSC_0 0x0400U
6104 #define TIM_CCMR1_IC2PSC_1 0x0800U
6106 #define TIM_CCMR1_IC2F 0xF000U
6107 #define TIM_CCMR1_IC2F_0 0x1000U
6108 #define TIM_CCMR1_IC2F_1 0x2000U
6109 #define TIM_CCMR1_IC2F_2 0x4000U
6110 #define TIM_CCMR1_IC2F_3 0x8000U
6112 /****************** Bit definition for TIM_CCMR2 register *******************/
6113 #define TIM_CCMR2_CC3S 0x0003U
6114 #define TIM_CCMR2_CC3S_0 0x0001U
6115 #define TIM_CCMR2_CC3S_1 0x0002U
6117 #define TIM_CCMR2_OC3FE 0x0004U
6118 #define TIM_CCMR2_OC3PE 0x0008U
6120 #define TIM_CCMR2_OC3M 0x0070U
6121 #define TIM_CCMR2_OC3M_0 0x0010U
6122 #define TIM_CCMR2_OC3M_1 0x0020U
6123 #define TIM_CCMR2_OC3M_2 0x0040U
6125 #define TIM_CCMR2_OC3CE 0x0080U
6127 #define TIM_CCMR2_CC4S 0x0300U
6128 #define TIM_CCMR2_CC4S_0 0x0100U
6129 #define TIM_CCMR2_CC4S_1 0x0200U
6131 #define TIM_CCMR2_OC4FE 0x0400U
6132 #define TIM_CCMR2_OC4PE 0x0800U
6134 #define TIM_CCMR2_OC4M 0x7000U
6135 #define TIM_CCMR2_OC4M_0 0x1000U
6136 #define TIM_CCMR2_OC4M_1 0x2000U
6137 #define TIM_CCMR2_OC4M_2 0x4000U
6139 #define TIM_CCMR2_OC4CE 0x8000U
6141 /*----------------------------------------------------------------------------*/
6142 
6143 #define TIM_CCMR2_IC3PSC 0x000CU
6144 #define TIM_CCMR2_IC3PSC_0 0x0004U
6145 #define TIM_CCMR2_IC3PSC_1 0x0008U
6147 #define TIM_CCMR2_IC3F 0x00F0U
6148 #define TIM_CCMR2_IC3F_0 0x0010U
6149 #define TIM_CCMR2_IC3F_1 0x0020U
6150 #define TIM_CCMR2_IC3F_2 0x0040U
6151 #define TIM_CCMR2_IC3F_3 0x0080U
6153 #define TIM_CCMR2_IC4PSC 0x0C00U
6154 #define TIM_CCMR2_IC4PSC_0 0x0400U
6155 #define TIM_CCMR2_IC4PSC_1 0x0800U
6157 #define TIM_CCMR2_IC4F 0xF000U
6158 #define TIM_CCMR2_IC4F_0 0x1000U
6159 #define TIM_CCMR2_IC4F_1 0x2000U
6160 #define TIM_CCMR2_IC4F_2 0x4000U
6161 #define TIM_CCMR2_IC4F_3 0x8000U
6163 /******************* Bit definition for TIM_CCER register *******************/
6164 #define TIM_CCER_CC1E 0x0001U
6165 #define TIM_CCER_CC1P 0x0002U
6166 #define TIM_CCER_CC1NE 0x0004U
6167 #define TIM_CCER_CC1NP 0x0008U
6168 #define TIM_CCER_CC2E 0x0010U
6169 #define TIM_CCER_CC2P 0x0020U
6170 #define TIM_CCER_CC2NE 0x0040U
6171 #define TIM_CCER_CC2NP 0x0080U
6172 #define TIM_CCER_CC3E 0x0100U
6173 #define TIM_CCER_CC3P 0x0200U
6174 #define TIM_CCER_CC3NE 0x0400U
6175 #define TIM_CCER_CC3NP 0x0800U
6176 #define TIM_CCER_CC4E 0x1000U
6177 #define TIM_CCER_CC4P 0x2000U
6178 #define TIM_CCER_CC4NP 0x8000U
6180 /******************* Bit definition for TIM_CNT register ********************/
6181 #define TIM_CNT_CNT 0xFFFFU
6183 /******************* Bit definition for TIM_PSC register ********************/
6184 #define TIM_PSC_PSC 0xFFFFU
6186 /******************* Bit definition for TIM_ARR register ********************/
6187 #define TIM_ARR_ARR 0xFFFFU
6189 /******************* Bit definition for TIM_RCR register ********************/
6190 #define TIM_RCR_REP 0xFFU
6192 /******************* Bit definition for TIM_CCR1 register *******************/
6193 #define TIM_CCR1_CCR1 0xFFFFU
6195 /******************* Bit definition for TIM_CCR2 register *******************/
6196 #define TIM_CCR2_CCR2 0xFFFFU
6198 /******************* Bit definition for TIM_CCR3 register *******************/
6199 #define TIM_CCR3_CCR3 0xFFFFU
6201 /******************* Bit definition for TIM_CCR4 register *******************/
6202 #define TIM_CCR4_CCR4 0xFFFFU
6204 /******************* Bit definition for TIM_BDTR register *******************/
6205 #define TIM_BDTR_DTG 0x00FFU
6206 #define TIM_BDTR_DTG_0 0x0001U
6207 #define TIM_BDTR_DTG_1 0x0002U
6208 #define TIM_BDTR_DTG_2 0x0004U
6209 #define TIM_BDTR_DTG_3 0x0008U
6210 #define TIM_BDTR_DTG_4 0x0010U
6211 #define TIM_BDTR_DTG_5 0x0020U
6212 #define TIM_BDTR_DTG_6 0x0040U
6213 #define TIM_BDTR_DTG_7 0x0080U
6215 #define TIM_BDTR_LOCK 0x0300U
6216 #define TIM_BDTR_LOCK_0 0x0100U
6217 #define TIM_BDTR_LOCK_1 0x0200U
6219 #define TIM_BDTR_OSSI 0x0400U
6220 #define TIM_BDTR_OSSR 0x0800U
6221 #define TIM_BDTR_BKE 0x1000U
6222 #define TIM_BDTR_BKP 0x2000U
6223 #define TIM_BDTR_AOE 0x4000U
6224 #define TIM_BDTR_MOE 0x8000U
6226 /******************* Bit definition for TIM_DCR register ********************/
6227 #define TIM_DCR_DBA 0x001FU
6228 #define TIM_DCR_DBA_0 0x0001U
6229 #define TIM_DCR_DBA_1 0x0002U
6230 #define TIM_DCR_DBA_2 0x0004U
6231 #define TIM_DCR_DBA_3 0x0008U
6232 #define TIM_DCR_DBA_4 0x0010U
6234 #define TIM_DCR_DBL 0x1F00U
6235 #define TIM_DCR_DBL_0 0x0100U
6236 #define TIM_DCR_DBL_1 0x0200U
6237 #define TIM_DCR_DBL_2 0x0400U
6238 #define TIM_DCR_DBL_3 0x0800U
6239 #define TIM_DCR_DBL_4 0x1000U
6241 /******************* Bit definition for TIM_DMAR register *******************/
6242 #define TIM_DMAR_DMAB 0xFFFFU
6244 /******************* Bit definition for TIM_OR register *********************/
6245 #define TIM_OR_TI4_RMP 0x00C0U
6246 #define TIM_OR_TI4_RMP_0 0x0040U
6247 #define TIM_OR_TI4_RMP_1 0x0080U
6248 #define TIM_OR_ITR1_RMP 0x0C00U
6249 #define TIM_OR_ITR1_RMP_0 0x0400U
6250 #define TIM_OR_ITR1_RMP_1 0x0800U
6253 /******************************************************************************/
6254 /* */
6255 /* Universal Synchronous Asynchronous Receiver Transmitter */
6256 /* */
6257 /******************************************************************************/
6258 /******************* Bit definition for USART_SR register *******************/
6259 #define USART_SR_PE 0x0001U
6260 #define USART_SR_FE 0x0002U
6261 #define USART_SR_NE 0x0004U
6262 #define USART_SR_ORE 0x0008U
6263 #define USART_SR_IDLE 0x0010U
6264 #define USART_SR_RXNE 0x0020U
6265 #define USART_SR_TC 0x0040U
6266 #define USART_SR_TXE 0x0080U
6267 #define USART_SR_LBD 0x0100U
6268 #define USART_SR_CTS 0x0200U
6270 /******************* Bit definition for USART_DR register *******************/
6271 #define USART_DR_DR 0x01FFU
6273 /****************** Bit definition for USART_BRR register *******************/
6274 #define USART_BRR_DIV_Fraction 0x000FU
6275 #define USART_BRR_DIV_Mantissa 0xFFF0U
6277 /****************** Bit definition for USART_CR1 register *******************/
6278 #define USART_CR1_SBK 0x0001U
6279 #define USART_CR1_RWU 0x0002U
6280 #define USART_CR1_RE 0x0004U
6281 #define USART_CR1_TE 0x0008U
6282 #define USART_CR1_IDLEIE 0x0010U
6283 #define USART_CR1_RXNEIE 0x0020U
6284 #define USART_CR1_TCIE 0x0040U
6285 #define USART_CR1_TXEIE 0x0080U
6286 #define USART_CR1_PEIE 0x0100U
6287 #define USART_CR1_PS 0x0200U
6288 #define USART_CR1_PCE 0x0400U
6289 #define USART_CR1_WAKE 0x0800U
6290 #define USART_CR1_M 0x1000U
6291 #define USART_CR1_UE 0x2000U
6292 #define USART_CR1_OVER8 0x8000U
6294 /****************** Bit definition for USART_CR2 register *******************/
6295 #define USART_CR2_ADD 0x000FU
6296 #define USART_CR2_LBDL 0x0020U
6297 #define USART_CR2_LBDIE 0x0040U
6298 #define USART_CR2_LBCL 0x0100U
6299 #define USART_CR2_CPHA 0x0200U
6300 #define USART_CR2_CPOL 0x0400U
6301 #define USART_CR2_CLKEN 0x0800U
6303 #define USART_CR2_STOP 0x3000U
6304 #define USART_CR2_STOP_0 0x1000U
6305 #define USART_CR2_STOP_1 0x2000U
6307 #define USART_CR2_LINEN 0x4000U
6309 /****************** Bit definition for USART_CR3 register *******************/
6310 #define USART_CR3_EIE 0x0001U
6311 #define USART_CR3_IREN 0x0002U
6312 #define USART_CR3_IRLP 0x0004U
6313 #define USART_CR3_HDSEL 0x0008U
6314 #define USART_CR3_NACK 0x0010U
6315 #define USART_CR3_SCEN 0x0020U
6316 #define USART_CR3_DMAR 0x0040U
6317 #define USART_CR3_DMAT 0x0080U
6318 #define USART_CR3_RTSE 0x0100U
6319 #define USART_CR3_CTSE 0x0200U
6320 #define USART_CR3_CTSIE 0x0400U
6321 #define USART_CR3_ONEBIT 0x0800U
6323 /****************** Bit definition for USART_GTPR register ******************/
6324 #define USART_GTPR_PSC 0x00FFU
6325 #define USART_GTPR_PSC_0 0x0001U
6326 #define USART_GTPR_PSC_1 0x0002U
6327 #define USART_GTPR_PSC_2 0x0004U
6328 #define USART_GTPR_PSC_3 0x0008U
6329 #define USART_GTPR_PSC_4 0x0010U
6330 #define USART_GTPR_PSC_5 0x0020U
6331 #define USART_GTPR_PSC_6 0x0040U
6332 #define USART_GTPR_PSC_7 0x0080U
6334 #define USART_GTPR_GT 0xFF00U
6336 /******************************************************************************/
6337 /* */
6338 /* Window WATCHDOG */
6339 /* */
6340 /******************************************************************************/
6341 /******************* Bit definition for WWDG_CR register ********************/
6342 #define WWDG_CR_T 0x7FU
6343 #define WWDG_CR_T_0 0x01U
6344 #define WWDG_CR_T_1 0x02U
6345 #define WWDG_CR_T_2 0x04U
6346 #define WWDG_CR_T_3 0x08U
6347 #define WWDG_CR_T_4 0x10U
6348 #define WWDG_CR_T_5 0x20U
6349 #define WWDG_CR_T_6 0x40U
6350 /* Legacy defines */
6351 #define WWDG_CR_T0 WWDG_CR_T_0
6352 #define WWDG_CR_T1 WWDG_CR_T_1
6353 #define WWDG_CR_T2 WWDG_CR_T_2
6354 #define WWDG_CR_T3 WWDG_CR_T_3
6355 #define WWDG_CR_T4 WWDG_CR_T_4
6356 #define WWDG_CR_T5 WWDG_CR_T_5
6357 #define WWDG_CR_T6 WWDG_CR_T_6
6358 
6359 #define WWDG_CR_WDGA 0x80U
6361 /******************* Bit definition for WWDG_CFR register *******************/
6362 #define WWDG_CFR_W 0x007FU
6363 #define WWDG_CFR_W_0 0x0001U
6364 #define WWDG_CFR_W_1 0x0002U
6365 #define WWDG_CFR_W_2 0x0004U
6366 #define WWDG_CFR_W_3 0x0008U
6367 #define WWDG_CFR_W_4 0x0010U
6368 #define WWDG_CFR_W_5 0x0020U
6369 #define WWDG_CFR_W_6 0x0040U
6370 /* Legacy defines */
6371 #define WWDG_CFR_W0 WWDG_CFR_W_0
6372 #define WWDG_CFR_W1 WWDG_CFR_W_1
6373 #define WWDG_CFR_W2 WWDG_CFR_W_2
6374 #define WWDG_CFR_W3 WWDG_CFR_W_3
6375 #define WWDG_CFR_W4 WWDG_CFR_W_4
6376 #define WWDG_CFR_W5 WWDG_CFR_W_5
6377 #define WWDG_CFR_W6 WWDG_CFR_W_6
6378 
6379 #define WWDG_CFR_WDGTB 0x0180U
6380 #define WWDG_CFR_WDGTB_0 0x0080U
6381 #define WWDG_CFR_WDGTB_1 0x0100U
6382 /* Legacy defines */
6383 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6384 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6385 
6386 #define WWDG_CFR_EWI 0x0200U
6388 /******************* Bit definition for WWDG_SR register ********************/
6389 #define WWDG_SR_EWIF 0x01U
6392 /******************************************************************************/
6393 /* */
6394 /* DBG */
6395 /* */
6396 /******************************************************************************/
6397 /******************** Bit definition for DBGMCU_IDCODE register *************/
6398 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
6399 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
6400 
6401 /******************** Bit definition for DBGMCU_CR register *****************/
6402 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
6403 #define DBGMCU_CR_DBG_STOP 0x00000002U
6404 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
6405 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
6406 
6407 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
6408 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
6409 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
6411 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6412 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
6413 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
6414 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
6415 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
6416 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
6417 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
6418 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
6419 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
6420 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
6421 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
6422 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
6423 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
6424 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
6425 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
6426 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
6427 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
6428 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
6429 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
6430 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6431 
6432 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6433 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
6434 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
6435 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
6436 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
6437 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
6438 
6439 /******************************************************************************/
6440 /* */
6441 /* USB_OTG */
6442 /* */
6443 /******************************************************************************/
6444 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
6445 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
6446 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
6447 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
6448 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
6449 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
6450 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
6451 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
6452 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
6453 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
6454 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
6456 /******************** Bit definition forUSB_OTG_HCFG register ********************/
6457 
6458 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
6459 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
6460 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
6461 #define USB_OTG_HCFG_FSLSS 0x00000004U
6463 /******************** Bit definition forUSB_OTG_DCFG register ********************/
6464 
6465 #define USB_OTG_DCFG_DSPD 0x00000003U
6466 #define USB_OTG_DCFG_DSPD_0 0x00000001U
6467 #define USB_OTG_DCFG_DSPD_1 0x00000002U
6468 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
6470 #define USB_OTG_DCFG_DAD 0x000007F0U
6471 #define USB_OTG_DCFG_DAD_0 0x00000010U
6472 #define USB_OTG_DCFG_DAD_1 0x00000020U
6473 #define USB_OTG_DCFG_DAD_2 0x00000040U
6474 #define USB_OTG_DCFG_DAD_3 0x00000080U
6475 #define USB_OTG_DCFG_DAD_4 0x00000100U
6476 #define USB_OTG_DCFG_DAD_5 0x00000200U
6477 #define USB_OTG_DCFG_DAD_6 0x00000400U
6479 #define USB_OTG_DCFG_PFIVL 0x00001800U
6480 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
6481 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
6483 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
6484 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
6485 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
6487 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
6488 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
6489 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
6490 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
6492 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
6493 #define USB_OTG_GOTGINT_SEDET 0x00000004U
6494 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
6495 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
6496 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
6497 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
6498 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
6500 /******************** Bit definition forUSB_OTG_DCTL register ********************/
6501 #define USB_OTG_DCTL_RWUSIG 0x00000001U
6502 #define USB_OTG_DCTL_SDIS 0x00000002U
6503 #define USB_OTG_DCTL_GINSTS 0x00000004U
6504 #define USB_OTG_DCTL_GONSTS 0x00000008U
6506 #define USB_OTG_DCTL_TCTL 0x00000070U
6507 #define USB_OTG_DCTL_TCTL_0 0x00000010U
6508 #define USB_OTG_DCTL_TCTL_1 0x00000020U
6509 #define USB_OTG_DCTL_TCTL_2 0x00000040U
6510 #define USB_OTG_DCTL_SGINAK 0x00000080U
6511 #define USB_OTG_DCTL_CGINAK 0x00000100U
6512 #define USB_OTG_DCTL_SGONAK 0x00000200U
6513 #define USB_OTG_DCTL_CGONAK 0x00000400U
6514 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
6516 /******************** Bit definition forUSB_OTG_HFIR register ********************/
6517 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
6519 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
6520 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
6521 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
6523 /******************** Bit definition forUSB_OTG_DSTS register ********************/
6524 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
6526 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
6527 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
6528 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
6529 #define USB_OTG_DSTS_EERR 0x00000008U
6530 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
6532 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
6533 #define USB_OTG_GAHBCFG_GINT 0x00000001U
6535 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
6536 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
6537 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
6538 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
6539 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
6540 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
6541 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
6542 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
6544 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
6545 
6546 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
6547 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
6548 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
6549 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
6550 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
6551 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
6552 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
6554 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
6555 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
6556 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
6557 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
6558 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
6559 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
6560 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
6561 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
6562 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
6563 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
6564 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
6565 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
6566 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
6567 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
6568 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
6569 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
6570 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
6571 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
6573 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
6574 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
6575 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
6576 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
6577 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
6578 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
6580 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
6581 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
6582 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
6583 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
6584 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
6585 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
6586 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
6587 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
6589 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
6590 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
6591 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
6592 #define USB_OTG_DIEPMSK_TOM 0x00000008U
6593 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
6594 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
6595 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
6596 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
6597 #define USB_OTG_DIEPMSK_BIM 0x00000200U
6599 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
6600 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
6602 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
6603 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
6604 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
6605 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
6606 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
6607 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
6608 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
6609 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
6610 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
6612 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
6613 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
6614 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
6615 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
6616 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
6617 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
6618 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
6619 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
6620 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
6622 /******************** Bit definition forUSB_OTG_HAINT register ********************/
6623 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
6625 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
6626 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
6627 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
6628 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
6629 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
6630 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
6631 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
6632 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
6634 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
6635 #define USB_OTG_GINTSTS_CMOD 0x00000001U
6636 #define USB_OTG_GINTSTS_MMIS 0x00000002U
6637 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
6638 #define USB_OTG_GINTSTS_SOF 0x00000008U
6639 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
6640 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
6641 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
6642 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
6643 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
6644 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
6645 #define USB_OTG_GINTSTS_USBRST 0x00001000U
6646 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
6647 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
6648 #define USB_OTG_GINTSTS_EOPF 0x00008000U
6649 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
6650 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
6651 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
6652 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
6653 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
6654 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
6655 #define USB_OTG_GINTSTS_HCINT 0x02000000U
6656 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
6657 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
6658 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
6659 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
6660 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
6662 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
6663 #define USB_OTG_GINTMSK_MMISM 0x00000002U
6664 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
6665 #define USB_OTG_GINTMSK_SOFM 0x00000008U
6666 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
6667 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
6668 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
6669 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
6670 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
6671 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
6672 #define USB_OTG_GINTMSK_USBRST 0x00001000U
6673 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
6674 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
6675 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
6676 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
6677 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
6678 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
6679 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
6680 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
6681 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
6682 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
6683 #define USB_OTG_GINTMSK_HCIM 0x02000000U
6684 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
6685 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
6686 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
6687 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
6688 #define USB_OTG_GINTMSK_WUIM 0x80000000U
6690 /******************** Bit definition forUSB_OTG_DAINT register ********************/
6691 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
6692 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
6694 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
6695 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
6697 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
6698 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
6699 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
6700 #define USB_OTG_GRXSTSP_DPID 0x00018000U
6701 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
6703 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
6704 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
6705 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
6707 /******************** Bit definition for OTG register ********************/
6708 
6709 #define USB_OTG_CHNUM 0x0000000FU
6710 #define USB_OTG_CHNUM_0 0x00000001U
6711 #define USB_OTG_CHNUM_1 0x00000002U
6712 #define USB_OTG_CHNUM_2 0x00000004U
6713 #define USB_OTG_CHNUM_3 0x00000008U
6714 #define USB_OTG_BCNT 0x00007FF0U
6716 #define USB_OTG_DPID 0x00018000U
6717 #define USB_OTG_DPID_0 0x00008000U
6718 #define USB_OTG_DPID_1 0x00010000U
6720 #define USB_OTG_PKTSTS 0x001E0000U
6721 #define USB_OTG_PKTSTS_0 0x00020000U
6722 #define USB_OTG_PKTSTS_1 0x00040000U
6723 #define USB_OTG_PKTSTS_2 0x00080000U
6724 #define USB_OTG_PKTSTS_3 0x00100000U
6726 #define USB_OTG_EPNUM 0x0000000FU
6727 #define USB_OTG_EPNUM_0 0x00000001U
6728 #define USB_OTG_EPNUM_1 0x00000002U
6729 #define USB_OTG_EPNUM_2 0x00000004U
6730 #define USB_OTG_EPNUM_3 0x00000008U
6732 #define USB_OTG_FRMNUM 0x01E00000U
6733 #define USB_OTG_FRMNUM_0 0x00200000U
6734 #define USB_OTG_FRMNUM_1 0x00400000U
6735 #define USB_OTG_FRMNUM_2 0x00800000U
6736 #define USB_OTG_FRMNUM_3 0x01000000U
6738 /******************** Bit definition for OTG register ********************/
6739 
6740 #define USB_OTG_CHNUM 0x0000000FU
6741 #define USB_OTG_CHNUM_0 0x00000001U
6742 #define USB_OTG_CHNUM_1 0x00000002U
6743 #define USB_OTG_CHNUM_2 0x00000004U
6744 #define USB_OTG_CHNUM_3 0x00000008U
6745 #define USB_OTG_BCNT 0x00007FF0U
6747 #define USB_OTG_DPID 0x00018000U
6748 #define USB_OTG_DPID_0 0x00008000U
6749 #define USB_OTG_DPID_1 0x00010000U
6751 #define USB_OTG_PKTSTS 0x001E0000U
6752 #define USB_OTG_PKTSTS_0 0x00020000U
6753 #define USB_OTG_PKTSTS_1 0x00040000U
6754 #define USB_OTG_PKTSTS_2 0x00080000U
6755 #define USB_OTG_PKTSTS_3 0x00100000U
6757 #define USB_OTG_EPNUM 0x0000000FU
6758 #define USB_OTG_EPNUM_0 0x00000001U
6759 #define USB_OTG_EPNUM_1 0x00000002U
6760 #define USB_OTG_EPNUM_2 0x00000004U
6761 #define USB_OTG_EPNUM_3 0x00000008U
6763 #define USB_OTG_FRMNUM 0x01E00000U
6764 #define USB_OTG_FRMNUM_0 0x00200000U
6765 #define USB_OTG_FRMNUM_1 0x00400000U
6766 #define USB_OTG_FRMNUM_2 0x00800000U
6767 #define USB_OTG_FRMNUM_3 0x01000000U
6769 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
6770 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
6772 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
6773 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
6775 /******************** Bit definition for OTG register ********************/
6776 #define USB_OTG_NPTXFSA 0x0000FFFFU
6777 #define USB_OTG_NPTXFD 0xFFFF0000U
6778 #define USB_OTG_TX0FSA 0x0000FFFFU
6779 #define USB_OTG_TX0FD 0xFFFF0000U
6781 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
6782 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
6784 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
6785 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
6787 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
6788 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
6789 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
6790 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
6791 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
6792 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
6793 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
6794 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
6795 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
6797 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
6798 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
6799 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
6800 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
6801 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
6802 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
6803 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
6804 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
6806 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
6807 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
6808 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
6810 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
6811 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
6812 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
6813 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
6814 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
6815 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
6816 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
6817 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
6818 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
6819 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
6820 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
6822 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
6823 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
6824 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
6825 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
6826 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
6827 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
6828 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
6829 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
6830 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
6831 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
6832 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
6834 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
6835 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
6837 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
6838 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
6839 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
6841 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
6842 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
6843 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
6844 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
6845 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
6846 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
6847 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
6849 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
6850 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
6851 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
6853 /******************** Bit definition forUSB_OTG_CID register ********************/
6854 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
6856 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
6857 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
6858 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
6859 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
6860 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
6861 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
6862 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
6863 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
6864 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
6865 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
6867 /******************** Bit definition forUSB_OTG_HPRT register ********************/
6868 #define USB_OTG_HPRT_PCSTS 0x00000001U
6869 #define USB_OTG_HPRT_PCDET 0x00000002U
6870 #define USB_OTG_HPRT_PENA 0x00000004U
6871 #define USB_OTG_HPRT_PENCHNG 0x00000008U
6872 #define USB_OTG_HPRT_POCA 0x00000010U
6873 #define USB_OTG_HPRT_POCCHNG 0x00000020U
6874 #define USB_OTG_HPRT_PRES 0x00000040U
6875 #define USB_OTG_HPRT_PSUSP 0x00000080U
6876 #define USB_OTG_HPRT_PRST 0x00000100U
6878 #define USB_OTG_HPRT_PLSTS 0x00000C00U
6879 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
6880 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
6881 #define USB_OTG_HPRT_PPWR 0x00001000U
6883 #define USB_OTG_HPRT_PTCTL 0x0001E000U
6884 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
6885 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
6886 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
6887 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
6889 #define USB_OTG_HPRT_PSPD 0x00060000U
6890 #define USB_OTG_HPRT_PSPD_0 0x00020000U
6891 #define USB_OTG_HPRT_PSPD_1 0x00040000U
6893 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
6894 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
6895 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
6896 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
6897 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
6898 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
6899 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
6900 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
6901 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
6902 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
6903 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
6904 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
6906 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
6907 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
6908 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
6910 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
6911 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
6912 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
6913 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
6914 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
6916 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
6917 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
6918 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
6919 #define USB_OTG_DIEPCTL_STALL 0x00200000U
6921 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
6922 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
6923 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
6924 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
6925 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
6926 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
6927 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
6928 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
6929 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
6930 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
6931 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
6933 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
6934 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
6936 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
6937 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
6938 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
6939 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
6940 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
6941 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
6942 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
6944 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
6945 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
6946 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
6948 #define USB_OTG_HCCHAR_MC 0x00300000U
6949 #define USB_OTG_HCCHAR_MC_0 0x00100000U
6950 #define USB_OTG_HCCHAR_MC_1 0x00200000U
6952 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
6953 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
6954 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
6955 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
6956 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
6957 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
6958 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
6959 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
6960 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
6961 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
6962 #define USB_OTG_HCCHAR_CHENA 0x80000000U
6964 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
6965 
6966 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
6967 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
6968 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
6969 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
6970 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
6971 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
6972 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
6973 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
6975 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
6976 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
6977 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
6978 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
6979 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
6980 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
6981 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
6982 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
6984 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
6985 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
6986 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
6987 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
6988 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
6990 /******************** Bit definition forUSB_OTG_HCINT register ********************/
6991 #define USB_OTG_HCINT_XFRC 0x00000001U
6992 #define USB_OTG_HCINT_CHH 0x00000002U
6993 #define USB_OTG_HCINT_AHBERR 0x00000004U
6994 #define USB_OTG_HCINT_STALL 0x00000008U
6995 #define USB_OTG_HCINT_NAK 0x00000010U
6996 #define USB_OTG_HCINT_ACK 0x00000020U
6997 #define USB_OTG_HCINT_NYET 0x00000040U
6998 #define USB_OTG_HCINT_TXERR 0x00000080U
6999 #define USB_OTG_HCINT_BBERR 0x00000100U
7000 #define USB_OTG_HCINT_FRMOR 0x00000200U
7001 #define USB_OTG_HCINT_DTERR 0x00000400U
7003 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
7004 #define USB_OTG_DIEPINT_XFRC 0x00000001U
7005 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
7006 #define USB_OTG_DIEPINT_TOC 0x00000008U
7007 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
7008 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
7009 #define USB_OTG_DIEPINT_TXFE 0x00000080U
7010 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
7011 #define USB_OTG_DIEPINT_BNA 0x00000200U
7012 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
7013 #define USB_OTG_DIEPINT_BERR 0x00001000U
7014 #define USB_OTG_DIEPINT_NAK 0x00002000U
7016 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
7017 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
7018 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
7019 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
7020 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
7021 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
7022 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
7023 #define USB_OTG_HCINTMSK_NYET 0x00000040U
7024 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
7025 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
7026 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
7027 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
7029 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
7030 
7031 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
7032 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
7033 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
7034 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
7035 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
7036 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
7037 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
7038 #define USB_OTG_HCTSIZ_DPID 0x60000000U
7039 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
7040 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
7042 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
7043 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
7045 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
7046 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
7048 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
7049 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
7051 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
7052 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
7053 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
7055 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
7056 
7057 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
7058 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
7059 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
7060 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
7061 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
7062 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
7063 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
7064 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
7065 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
7066 #define USB_OTG_DOEPCTL_STALL 0x00200000U
7067 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
7068 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
7069 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
7070 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
7072 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
7073 #define USB_OTG_DOEPINT_XFRC 0x00000001U
7074 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
7075 #define USB_OTG_DOEPINT_STUP 0x00000008U
7076 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
7077 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
7078 #define USB_OTG_DOEPINT_NYET 0x00004000U
7080 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
7081 
7082 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
7083 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
7085 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
7086 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
7087 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
7089 /******************** Bit definition for PCGCCTL register ********************/
7090 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
7091 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
7092 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
7106 /******************************* ADC Instances ********************************/
7107 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
7108  ((INSTANCE) == ADC2) || \
7109  ((INSTANCE) == ADC3))
7110 
7111 /******************************* CAN Instances ********************************/
7112 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
7113  ((INSTANCE) == CAN2))
7114 
7115 /******************************* CRC Instances ********************************/
7116 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7117 
7118 /******************************* DAC Instances ********************************/
7119 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
7120 
7121 /******************************** DMA Instances *******************************/
7122 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7123  ((INSTANCE) == DMA1_Stream1) || \
7124  ((INSTANCE) == DMA1_Stream2) || \
7125  ((INSTANCE) == DMA1_Stream3) || \
7126  ((INSTANCE) == DMA1_Stream4) || \
7127  ((INSTANCE) == DMA1_Stream5) || \
7128  ((INSTANCE) == DMA1_Stream6) || \
7129  ((INSTANCE) == DMA1_Stream7) || \
7130  ((INSTANCE) == DMA2_Stream0) || \
7131  ((INSTANCE) == DMA2_Stream1) || \
7132  ((INSTANCE) == DMA2_Stream2) || \
7133  ((INSTANCE) == DMA2_Stream3) || \
7134  ((INSTANCE) == DMA2_Stream4) || \
7135  ((INSTANCE) == DMA2_Stream5) || \
7136  ((INSTANCE) == DMA2_Stream6) || \
7137  ((INSTANCE) == DMA2_Stream7))
7138 
7139 /******************************* GPIO Instances *******************************/
7140 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7141  ((INSTANCE) == GPIOB) || \
7142  ((INSTANCE) == GPIOC) || \
7143  ((INSTANCE) == GPIOD) || \
7144  ((INSTANCE) == GPIOE) || \
7145  ((INSTANCE) == GPIOF) || \
7146  ((INSTANCE) == GPIOG) || \
7147  ((INSTANCE) == GPIOH) || \
7148  ((INSTANCE) == GPIOI))
7149 
7150 /******************************** I2C Instances *******************************/
7151 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7152  ((INSTANCE) == I2C2) || \
7153  ((INSTANCE) == I2C3))
7154 
7155 /******************************** I2S Instances *******************************/
7156 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
7157  ((INSTANCE) == SPI3))
7158 
7159 /*************************** I2S Extended Instances ***************************/
7160 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
7161  ((INSTANCE) == SPI3) || \
7162  ((INSTANCE) == I2S2ext) || \
7163  ((INSTANCE) == I2S3ext))
7164 
7165 /******************************* RNG Instances ********************************/
7166 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
7167 
7168 /****************************** RTC Instances *********************************/
7169 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7170 
7171 /******************************** SPI Instances *******************************/
7172 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7173  ((INSTANCE) == SPI2) || \
7174  ((INSTANCE) == SPI3))
7175 
7176 /*************************** SPI Extended Instances ***************************/
7177 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
7178  ((INSTANCE) == SPI2) || \
7179  ((INSTANCE) == SPI3) || \
7180  ((INSTANCE) == I2S2ext) || \
7181  ((INSTANCE) == I2S3ext))
7182 
7183 /****************** TIM Instances : All supported instances *******************/
7184 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7185  ((INSTANCE) == TIM2) || \
7186  ((INSTANCE) == TIM3) || \
7187  ((INSTANCE) == TIM4) || \
7188  ((INSTANCE) == TIM5) || \
7189  ((INSTANCE) == TIM6) || \
7190  ((INSTANCE) == TIM7) || \
7191  ((INSTANCE) == TIM8) || \
7192  ((INSTANCE) == TIM9) || \
7193  ((INSTANCE) == TIM10) || \
7194  ((INSTANCE) == TIM11) || \
7195  ((INSTANCE) == TIM12) || \
7196  ((INSTANCE) == TIM13) || \
7197  ((INSTANCE) == TIM14))
7198 
7199 /************* TIM Instances : at least 1 capture/compare channel *************/
7200 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7201  ((INSTANCE) == TIM2) || \
7202  ((INSTANCE) == TIM3) || \
7203  ((INSTANCE) == TIM4) || \
7204  ((INSTANCE) == TIM5) || \
7205  ((INSTANCE) == TIM8) || \
7206  ((INSTANCE) == TIM9) || \
7207  ((INSTANCE) == TIM10) || \
7208  ((INSTANCE) == TIM11) || \
7209  ((INSTANCE) == TIM12) || \
7210  ((INSTANCE) == TIM13) || \
7211  ((INSTANCE) == TIM14))
7212 
7213 /************ TIM Instances : at least 2 capture/compare channels *************/
7214 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7215  ((INSTANCE) == TIM2) || \
7216  ((INSTANCE) == TIM3) || \
7217  ((INSTANCE) == TIM4) || \
7218  ((INSTANCE) == TIM5) || \
7219  ((INSTANCE) == TIM8) || \
7220  ((INSTANCE) == TIM9) || \
7221  ((INSTANCE) == TIM12))
7222 
7223 /************ TIM Instances : at least 3 capture/compare channels *************/
7224 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7225  ((INSTANCE) == TIM2) || \
7226  ((INSTANCE) == TIM3) || \
7227  ((INSTANCE) == TIM4) || \
7228  ((INSTANCE) == TIM5) || \
7229  ((INSTANCE) == TIM8))
7230 
7231 /************ TIM Instances : at least 4 capture/compare channels *************/
7232 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7233  ((INSTANCE) == TIM2) || \
7234  ((INSTANCE) == TIM3) || \
7235  ((INSTANCE) == TIM4) || \
7236  ((INSTANCE) == TIM5) || \
7237  ((INSTANCE) == TIM8))
7238 
7239 /******************** TIM Instances : Advanced-control timers *****************/
7240 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7241  ((INSTANCE) == TIM8))
7242 
7243 /******************* TIM Instances : Timer input XOR function *****************/
7244 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7245  ((INSTANCE) == TIM2) || \
7246  ((INSTANCE) == TIM3) || \
7247  ((INSTANCE) == TIM4) || \
7248  ((INSTANCE) == TIM5) || \
7249  ((INSTANCE) == TIM8))
7250 
7251 /****************** TIM Instances : DMA requests generation (UDE) *************/
7252 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7253  ((INSTANCE) == TIM2) || \
7254  ((INSTANCE) == TIM3) || \
7255  ((INSTANCE) == TIM4) || \
7256  ((INSTANCE) == TIM5) || \
7257  ((INSTANCE) == TIM6) || \
7258  ((INSTANCE) == TIM7) || \
7259  ((INSTANCE) == TIM8))
7260 
7261 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
7262 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7263  ((INSTANCE) == TIM2) || \
7264  ((INSTANCE) == TIM3) || \
7265  ((INSTANCE) == TIM4) || \
7266  ((INSTANCE) == TIM5) || \
7267  ((INSTANCE) == TIM8))
7268 
7269 /************ TIM Instances : DMA requests generation (COMDE) *****************/
7270 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7271  ((INSTANCE) == TIM2) || \
7272  ((INSTANCE) == TIM3) || \
7273  ((INSTANCE) == TIM4) || \
7274  ((INSTANCE) == TIM5) || \
7275  ((INSTANCE) == TIM8))
7276 
7277 /******************** TIM Instances : DMA burst feature ***********************/
7278 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7279  ((INSTANCE) == TIM2) || \
7280  ((INSTANCE) == TIM3) || \
7281  ((INSTANCE) == TIM4) || \
7282  ((INSTANCE) == TIM5) || \
7283  ((INSTANCE) == TIM8))
7284 
7285 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
7286 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7287  ((INSTANCE) == TIM2) || \
7288  ((INSTANCE) == TIM3) || \
7289  ((INSTANCE) == TIM4) || \
7290  ((INSTANCE) == TIM5) || \
7291  ((INSTANCE) == TIM6) || \
7292  ((INSTANCE) == TIM7) || \
7293  ((INSTANCE) == TIM8) || \
7294  ((INSTANCE) == TIM9) || \
7295  ((INSTANCE) == TIM12))
7296 
7297 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7298 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7299  ((INSTANCE) == TIM2) || \
7300  ((INSTANCE) == TIM3) || \
7301  ((INSTANCE) == TIM4) || \
7302  ((INSTANCE) == TIM5) || \
7303  ((INSTANCE) == TIM8) || \
7304  ((INSTANCE) == TIM9) || \
7305  ((INSTANCE) == TIM12))
7306 
7307 /********************** TIM Instances : 32 bit Counter ************************/
7308 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
7309  ((INSTANCE) == TIM5))
7310 
7311 /***************** TIM Instances : external trigger input availabe ************/
7312 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7313  ((INSTANCE) == TIM2) || \
7314  ((INSTANCE) == TIM3) || \
7315  ((INSTANCE) == TIM4) || \
7316  ((INSTANCE) == TIM5) || \
7317  ((INSTANCE) == TIM8))
7318 
7319 /****************** TIM Instances : remapping capability **********************/
7320 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7321  ((INSTANCE) == TIM5) || \
7322  ((INSTANCE) == TIM11))
7323 
7324 /******************* TIM Instances : output(s) available **********************/
7325 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7326  ((((INSTANCE) == TIM1) && \
7327  (((CHANNEL) == TIM_CHANNEL_1) || \
7328  ((CHANNEL) == TIM_CHANNEL_2) || \
7329  ((CHANNEL) == TIM_CHANNEL_3) || \
7330  ((CHANNEL) == TIM_CHANNEL_4))) \
7331  || \
7332  (((INSTANCE) == TIM2) && \
7333  (((CHANNEL) == TIM_CHANNEL_1) || \
7334  ((CHANNEL) == TIM_CHANNEL_2) || \
7335  ((CHANNEL) == TIM_CHANNEL_3) || \
7336  ((CHANNEL) == TIM_CHANNEL_4))) \
7337  || \
7338  (((INSTANCE) == TIM3) && \
7339  (((CHANNEL) == TIM_CHANNEL_1) || \
7340  ((CHANNEL) == TIM_CHANNEL_2) || \
7341  ((CHANNEL) == TIM_CHANNEL_3) || \
7342  ((CHANNEL) == TIM_CHANNEL_4))) \
7343  || \
7344  (((INSTANCE) == TIM4) && \
7345  (((CHANNEL) == TIM_CHANNEL_1) || \
7346  ((CHANNEL) == TIM_CHANNEL_2) || \
7347  ((CHANNEL) == TIM_CHANNEL_3) || \
7348  ((CHANNEL) == TIM_CHANNEL_4))) \
7349  || \
7350  (((INSTANCE) == TIM5) && \
7351  (((CHANNEL) == TIM_CHANNEL_1) || \
7352  ((CHANNEL) == TIM_CHANNEL_2) || \
7353  ((CHANNEL) == TIM_CHANNEL_3) || \
7354  ((CHANNEL) == TIM_CHANNEL_4))) \
7355  || \
7356  (((INSTANCE) == TIM8) && \
7357  (((CHANNEL) == TIM_CHANNEL_1) || \
7358  ((CHANNEL) == TIM_CHANNEL_2) || \
7359  ((CHANNEL) == TIM_CHANNEL_3) || \
7360  ((CHANNEL) == TIM_CHANNEL_4))) \
7361  || \
7362  (((INSTANCE) == TIM9) && \
7363  (((CHANNEL) == TIM_CHANNEL_1) || \
7364  ((CHANNEL) == TIM_CHANNEL_2))) \
7365  || \
7366  (((INSTANCE) == TIM10) && \
7367  (((CHANNEL) == TIM_CHANNEL_1))) \
7368  || \
7369  (((INSTANCE) == TIM11) && \
7370  (((CHANNEL) == TIM_CHANNEL_1))) \
7371  || \
7372  (((INSTANCE) == TIM12) && \
7373  (((CHANNEL) == TIM_CHANNEL_1) || \
7374  ((CHANNEL) == TIM_CHANNEL_2))) \
7375  || \
7376  (((INSTANCE) == TIM13) && \
7377  (((CHANNEL) == TIM_CHANNEL_1))) \
7378  || \
7379  (((INSTANCE) == TIM14) && \
7380  (((CHANNEL) == TIM_CHANNEL_1))))
7381 
7382 /************ TIM Instances : complementary output(s) available ***************/
7383 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
7384  ((((INSTANCE) == TIM1) && \
7385  (((CHANNEL) == TIM_CHANNEL_1) || \
7386  ((CHANNEL) == TIM_CHANNEL_2) || \
7387  ((CHANNEL) == TIM_CHANNEL_3))) \
7388  || \
7389  (((INSTANCE) == TIM8) && \
7390  (((CHANNEL) == TIM_CHANNEL_1) || \
7391  ((CHANNEL) == TIM_CHANNEL_2) || \
7392  ((CHANNEL) == TIM_CHANNEL_3))))
7393 
7394 /******************** USART Instances : Synchronous mode **********************/
7395 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7396  ((INSTANCE) == USART2) || \
7397  ((INSTANCE) == USART3) || \
7398  ((INSTANCE) == USART6))
7399 
7400 /******************** UART Instances : Asynchronous mode **********************/
7401 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7402  ((INSTANCE) == USART2) || \
7403  ((INSTANCE) == USART3) || \
7404  ((INSTANCE) == UART4) || \
7405  ((INSTANCE) == UART5) || \
7406  ((INSTANCE) == USART6))
7407 
7408 /****************** UART Instances : Hardware Flow control ********************/
7409 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7410  ((INSTANCE) == USART2) || \
7411  ((INSTANCE) == USART3) || \
7412  ((INSTANCE) == USART6))
7413 
7414 /********************* UART Instances : Smard card mode ***********************/
7415 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7416  ((INSTANCE) == USART2) || \
7417  ((INSTANCE) == USART3) || \
7418  ((INSTANCE) == USART6))
7419 
7420 /*********************** UART Instances : IRDA mode ***************************/
7421 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7422  ((INSTANCE) == USART2) || \
7423  ((INSTANCE) == USART3) || \
7424  ((INSTANCE) == UART4) || \
7425  ((INSTANCE) == UART5) || \
7426  ((INSTANCE) == USART6))
7427 
7428 /*********************** PCD Instances ****************************************/
7429 /*********************** PCD Instances ****************************************/
7430 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
7431  ((INSTANCE) == USB_OTG_HS))
7432 
7433 /*********************** HCD Instances ****************************************/
7434 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
7435  ((INSTANCE) == USB_OTG_HS))
7436 
7437 /****************************** IWDG Instances ********************************/
7438 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
7439 
7440 /****************************** WWDG Instances ********************************/
7441 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
7442 
7443 /****************************** SDIO Instances ********************************/
7444 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
7445 
7446 /****************************** USB Exported Constants ************************/
7447 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
7448 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
7449 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
7450 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
7451 
7452 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
7453 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
7454 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
7455 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
7456 
7457 /******************************************************************************/
7458 /* For a painless codes migration between the STM32F4xx device product */
7459 /* lines, the aliases defined below are put in place to overcome the */
7460 /* differences in the interrupt handlers and IRQn definitions. */
7461 /* No need to update developed interrupt code when moving across */
7462 /* product lines within the same STM32F4 Family */
7463 /******************************************************************************/
7464 
7465 /* Aliases for __IRQn */
7466 #define FMC_IRQn FSMC_IRQn
7467 
7468 /* Aliases for __IRQHandler */
7469 #define FMC_IRQHandler FSMC_IRQHandler
7470 
7483 #ifdef __cplusplus
7484 }
7485 #endif /* __cplusplus */
7486 
7487 #endif /* __STM32F405xx_H */
7488 
7489 
7490 
7491 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32f405xx.h:316
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32f405xx.h:712
TAMP_STAMP_IRQn
Definition: stm32f405xx.h:99
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f405xx.h:395
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32f405xx.h:319
FSMC_Bank2_3_TypeDef::PCR3
__IO uint32_t PCR3
Definition: stm32f405xx.h:423
TIM2_IRQn
Definition: stm32f405xx.h:125
UART4_IRQn
Definition: stm32f405xx.h:149
UART5_IRQn
Definition: stm32f405xx.h:150
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f405xx.h:123
EXTI2_IRQn
Definition: stm32f405xx.h:105
EXTI4_IRQn
Definition: stm32f405xx.h:107
USART1_IRQn
Definition: stm32f405xx.h:134
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f405xx.h:142
TIM4_IRQn
Definition: stm32f405xx.h:127
RTC_Alarm_IRQn
Definition: stm32f405xx.h:138
CAN2_SCE_IRQn
Definition: stm32f405xx.h:161
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f405xx.h:284
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f405xx.h:257
PendSV_IRQn
Definition: stm32f405xx.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f405xx.h:100
CAN1_RX1_IRQn
Definition: stm32f405xx.h:118
TIM6_DAC_IRQn
Definition: stm32f405xx.h:151
CAN1_TX_IRQn
Definition: stm32f405xx.h:116
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f405xx.h:132
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
OTG_FS_WKUP_IRQn
Definition: stm32f405xx.h:139
DMA_TypeDef
Definition: stm32f401xc.h:243
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:309
DMA1_Stream2_IRQn
Definition: stm32f405xx.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f405xx.h:133
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:711
FSMC_Bank2_3_TypeDef::PMEM2
__IO uint32_t PMEM2
Definition: stm32f405xx.h:417
FSMC_Bank2_3_TypeDef::ECCR3
__IO uint32_t ECCR3
Definition: stm32f405xx.h:428
__I
#define __I
Definition: core_cm0.h:210
FSMC_Bank2_3_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f405xx.h:421
DMA2_Stream5_IRQn
Definition: stm32f405xx.h:163
FSMC_Bank2_3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f405xx.h:419
ADC_IRQn
Definition: stm32f405xx.h:115
CAN1_RX0_IRQn
Definition: stm32f405xx.h:117
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32f405xx.h:310
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f405xx.h:283
RCC_IRQn
Definition: stm32f405xx.h:102
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32f405xx.h:318
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f405xx.h:256
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32f405xx.h:317
DebugMonitor_IRQn
Definition: stm32f405xx.h:93
DMA2_Stream3_IRQn
Definition: stm32f405xx.h:156
NonMaskableInt_IRQn
Definition: stm32f405xx.h:88
FSMC_Bank2_3_TypeDef::PATT2
__IO uint32_t PATT2
Definition: stm32f405xx.h:418
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f405xx.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f405xx.h:141
DMA1_Stream1_IRQn
Definition: stm32f405xx.h:109
DMA2_Stream7_IRQn
Definition: stm32f405xx.h:165
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f405xx.h:280
DMA2_Stream6_IRQn
Definition: stm32f405xx.h:164
BusFault_IRQn
Definition: stm32f405xx.h:90
FSMC_Bank2_3_TypeDef::ECCR2
__IO uint32_t ECCR2
Definition: stm32f405xx.h:420
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f405xx.h:273
I2C3_ER_IRQn
Definition: stm32f405xx.h:168
CAN2_RX0_IRQn
Definition: stm32f405xx.h:159
USART6_IRQn
Definition: stm32f405xx.h:166
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f405xx.h:278
PVD_IRQn
Definition: stm32f405xx.h:98
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32f405xx.h:311
__IO
#define __IO
Definition: core_cm0.h:213
FSMC_Bank2_3_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f405xx.h:422
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f405xx.h:112
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f405xx.h:710
FSMC_Bank2_3_TypeDef::PCR2
__IO uint32_t PCR2
Definition: stm32f405xx.h:415
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f405xx.h:246
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f405xx.h:281
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f405xx.h:285
DMA1_Stream0_IRQn
Definition: stm32f405xx.h:108
OTG_HS_IRQn
Definition: stm32f405xx.h:172
FSMC_Bank2_3_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f405xx.h:416
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
TIM8_CC_IRQn
Definition: stm32f405xx.h:143
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f405xx.h:266
DMA1_Stream3_IRQn
Definition: stm32f405xx.h:111
FPU_IRQn
Definition: stm32f405xx.h:174
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
OTG_FS_IRQn
Definition: stm32f405xx.h:162
DMA2_Stream2_IRQn
Definition: stm32f405xx.h:155
FSMC_Bank4_TypeDef::PCR4
__IO uint32_t PCR4
Definition: stm32f405xx.h:437
OTG_HS_EP1_OUT_IRQn
Definition: stm32f405xx.h:169
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f405xx.h:268
OTG_HS_EP1_IN_IRQn
Definition: stm32f405xx.h:170
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f405xx.h:146
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32f405xx.h:313
I2C3_EV_IRQn
Definition: stm32f405xx.h:167
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f405xx.h:135
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f405xx.h:152
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f405xx.h:232
I2C2_EV_IRQn
Definition: stm32f405xx.h:130
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f405xx.h:126
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f405xx.h:104
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32f405xx.h:321
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f405xx.h:235
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32f405xx.h:314
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f405xx.h:92
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32f405xx.h:312
TIM1_CC_IRQn
Definition: stm32f405xx.h:124
TIM8_BRK_TIM12_IRQn
Definition: stm32f405xx.h:140
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f405xx.h:279
FSMC_Bank4_TypeDef::PATT4
__IO uint32_t PATT4
Definition: stm32f405xx.h:440
HASH_RNG_IRQn
Definition: stm32f405xx.h:173
FLASH_IRQn
Definition: stm32f405xx.h:101
DMA1_Stream5_IRQn
Definition: stm32f405xx.h:113
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f405xx.h:95
TIM1_UP_TIM10_IRQn
Definition: stm32f405xx.h:122
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f405xx.h:131
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f405xx.h:247
FSMC_Bank4_TypeDef::PMEM4
__IO uint32_t PMEM4
Definition: stm32f405xx.h:439
UsageFault_IRQn
Definition: stm32f405xx.h:91
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f405xx.h:272
FSMC_Bank2_3_TypeDef::PMEM3
__IO uint32_t PMEM3
Definition: stm32f405xx.h:425
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f405xx.h:404
SPI3_IRQn
Definition: stm32f405xx.h:148
DMA2_Stream1_IRQn
Definition: stm32f405xx.h:154
EXTI9_5_IRQn
Definition: stm32f405xx.h:120
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f405xx.h:271
I2C1_EV_IRQn
Definition: stm32f405xx.h:128
DMA1_Stream6_IRQn
Definition: stm32f405xx.h:114
FSMC_Bank2_3_TypeDef::SR3
__IO uint32_t SR3
Definition: stm32f405xx.h:424
OTG_HS_WKUP_IRQn
Definition: stm32f405xx.h:171
I2C1_ER_IRQn
Definition: stm32f405xx.h:129
FSMC_Bank4_TypeDef::SR4
__IO uint32_t SR4
Definition: stm32f405xx.h:438
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f405xx.h:282
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
FSMC_IRQn
Definition: stm32f405xx.h:145
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f405xx.h:244
FSMC_Bank2_3_TypeDef::PATT3
__IO uint32_t PATT3
Definition: stm32f405xx.h:426
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f405xx.h:234
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f405xx.h:270
FSMC_Bank2_3_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f405xx.h:413
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f405xx.h:245
CAN2_RX1_IRQn
Definition: stm32f405xx.h:160
DMA2_Stream4_IRQn
Definition: stm32f405xx.h:157
WWDG_IRQn
Definition: stm32f405xx.h:97
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32f405xx.h:320
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f405xx.h:267
DMA1_Stream7_IRQn
Definition: stm32f405xx.h:144
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f405xx.h:233
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f405xx.h:269
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
FSMC_Bank2_3_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f405xx.h:427
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f405xx.h:322
EXTI15_10_IRQn
Definition: stm32f405xx.h:137
CAN1_SCE_IRQn
Definition: stm32f405xx.h:119
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f405xx.h:103
DMA2_Stream0_IRQn
Definition: stm32f405xx.h:153
TIM1_BRK_TIM9_IRQn
Definition: stm32f405xx.h:121
FSMC_Bank4_TypeDef::PIO4
__IO uint32_t PIO4
Definition: stm32f405xx.h:441
CAN2_TX_IRQn
Definition: stm32f405xx.h:158
TIM5_IRQn
Definition: stm32f405xx.h:147
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f405xx.h:106
USART3_IRQn
Definition: stm32f405xx.h:136
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32f405xx.h:315
MemoryManagement_IRQn
Definition: stm32f405xx.h:89
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f405xx.h:435