STM CMSIS
stm32f407xx.h
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1 
52 #ifndef __STM32F407xx_H
53 #define __STM32F407xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  CAN1_TX_IRQn = 19,
117  CAN1_RX0_IRQn = 20,
118  CAN1_RX1_IRQn = 21,
119  CAN1_SCE_IRQn = 22,
120  EXTI9_5_IRQn = 23,
121  TIM1_BRK_TIM9_IRQn = 24,
122  TIM1_UP_TIM10_IRQn = 25,
123  TIM1_TRG_COM_TIM11_IRQn = 26,
124  TIM1_CC_IRQn = 27,
125  TIM2_IRQn = 28,
126  TIM3_IRQn = 29,
127  TIM4_IRQn = 30,
128  I2C1_EV_IRQn = 31,
129  I2C1_ER_IRQn = 32,
130  I2C2_EV_IRQn = 33,
131  I2C2_ER_IRQn = 34,
132  SPI1_IRQn = 35,
133  SPI2_IRQn = 36,
134  USART1_IRQn = 37,
135  USART2_IRQn = 38,
136  USART3_IRQn = 39,
137  EXTI15_10_IRQn = 40,
138  RTC_Alarm_IRQn = 41,
139  OTG_FS_WKUP_IRQn = 42,
140  TIM8_BRK_TIM12_IRQn = 43,
141  TIM8_UP_TIM13_IRQn = 44,
142  TIM8_TRG_COM_TIM14_IRQn = 45,
143  TIM8_CC_IRQn = 46,
144  DMA1_Stream7_IRQn = 47,
145  FSMC_IRQn = 48,
146  SDIO_IRQn = 49,
147  TIM5_IRQn = 50,
148  SPI3_IRQn = 51,
149  UART4_IRQn = 52,
150  UART5_IRQn = 53,
151  TIM6_DAC_IRQn = 54,
152  TIM7_IRQn = 55,
153  DMA2_Stream0_IRQn = 56,
154  DMA2_Stream1_IRQn = 57,
155  DMA2_Stream2_IRQn = 58,
156  DMA2_Stream3_IRQn = 59,
157  DMA2_Stream4_IRQn = 60,
158  ETH_IRQn = 61,
159  ETH_WKUP_IRQn = 62,
160  CAN2_TX_IRQn = 63,
161  CAN2_RX0_IRQn = 64,
162  CAN2_RX1_IRQn = 65,
163  CAN2_SCE_IRQn = 66,
164  OTG_FS_IRQn = 67,
165  DMA2_Stream5_IRQn = 68,
166  DMA2_Stream6_IRQn = 69,
167  DMA2_Stream7_IRQn = 70,
168  USART6_IRQn = 71,
169  I2C3_EV_IRQn = 72,
170  I2C3_ER_IRQn = 73,
171  OTG_HS_EP1_OUT_IRQn = 74,
172  OTG_HS_EP1_IN_IRQn = 75,
173  OTG_HS_WKUP_IRQn = 76,
174  OTG_HS_IRQn = 77,
175  DCMI_IRQn = 78,
176  HASH_RNG_IRQn = 80,
177  FPU_IRQn = 81
178 } IRQn_Type;
179 
184 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
185 #include "system_stm32f4xx.h"
186 #include <stdint.h>
187 
196 typedef struct
197 {
198  __IO uint32_t SR;
199  __IO uint32_t CR1;
200  __IO uint32_t CR2;
201  __IO uint32_t SMPR1;
202  __IO uint32_t SMPR2;
203  __IO uint32_t JOFR1;
204  __IO uint32_t JOFR2;
205  __IO uint32_t JOFR3;
206  __IO uint32_t JOFR4;
207  __IO uint32_t HTR;
208  __IO uint32_t LTR;
209  __IO uint32_t SQR1;
210  __IO uint32_t SQR2;
211  __IO uint32_t SQR3;
212  __IO uint32_t JSQR;
213  __IO uint32_t JDR1;
214  __IO uint32_t JDR2;
215  __IO uint32_t JDR3;
216  __IO uint32_t JDR4;
217  __IO uint32_t DR;
218 } ADC_TypeDef;
219 
220 typedef struct
221 {
222  __IO uint32_t CSR;
223  __IO uint32_t CCR;
224  __IO uint32_t CDR;
226 } ADC_Common_TypeDef;
227 
228 
233 typedef struct
234 {
235  __IO uint32_t TIR;
236  __IO uint32_t TDTR;
237  __IO uint32_t TDLR;
238  __IO uint32_t TDHR;
239 } CAN_TxMailBox_TypeDef;
240 
245 typedef struct
246 {
247  __IO uint32_t RIR;
248  __IO uint32_t RDTR;
249  __IO uint32_t RDLR;
250  __IO uint32_t RDHR;
251 } CAN_FIFOMailBox_TypeDef;
252 
257 typedef struct
258 {
259  __IO uint32_t FR1;
260  __IO uint32_t FR2;
261 } CAN_FilterRegister_TypeDef;
262 
267 typedef struct
268 {
269  __IO uint32_t MCR;
270  __IO uint32_t MSR;
271  __IO uint32_t TSR;
272  __IO uint32_t RF0R;
273  __IO uint32_t RF1R;
274  __IO uint32_t IER;
275  __IO uint32_t ESR;
276  __IO uint32_t BTR;
277  uint32_t RESERVED0[88];
278  CAN_TxMailBox_TypeDef sTxMailBox[3];
279  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
280  uint32_t RESERVED1[12];
281  __IO uint32_t FMR;
282  __IO uint32_t FM1R;
283  uint32_t RESERVED2;
284  __IO uint32_t FS1R;
285  uint32_t RESERVED3;
286  __IO uint32_t FFA1R;
287  uint32_t RESERVED4;
288  __IO uint32_t FA1R;
289  uint32_t RESERVED5[8];
290  CAN_FilterRegister_TypeDef sFilterRegister[28];
291 } CAN_TypeDef;
292 
297 typedef struct
298 {
299  __IO uint32_t DR;
300  __IO uint8_t IDR;
301  uint8_t RESERVED0;
302  uint16_t RESERVED1;
303  __IO uint32_t CR;
304 } CRC_TypeDef;
305 
310 typedef struct
311 {
312  __IO uint32_t CR;
313  __IO uint32_t SWTRIGR;
314  __IO uint32_t DHR12R1;
315  __IO uint32_t DHR12L1;
316  __IO uint32_t DHR8R1;
317  __IO uint32_t DHR12R2;
318  __IO uint32_t DHR12L2;
319  __IO uint32_t DHR8R2;
320  __IO uint32_t DHR12RD;
321  __IO uint32_t DHR12LD;
322  __IO uint32_t DHR8RD;
323  __IO uint32_t DOR1;
324  __IO uint32_t DOR2;
325  __IO uint32_t SR;
326 } DAC_TypeDef;
327 
332 typedef struct
333 {
334  __IO uint32_t IDCODE;
335  __IO uint32_t CR;
336  __IO uint32_t APB1FZ;
337  __IO uint32_t APB2FZ;
338 }DBGMCU_TypeDef;
339 
344 typedef struct
345 {
346  __IO uint32_t CR;
347  __IO uint32_t SR;
348  __IO uint32_t RISR;
349  __IO uint32_t IER;
350  __IO uint32_t MISR;
351  __IO uint32_t ICR;
352  __IO uint32_t ESCR;
353  __IO uint32_t ESUR;
354  __IO uint32_t CWSTRTR;
355  __IO uint32_t CWSIZER;
356  __IO uint32_t DR;
357 } DCMI_TypeDef;
358 
363 typedef struct
364 {
365  __IO uint32_t CR;
366  __IO uint32_t NDTR;
367  __IO uint32_t PAR;
368  __IO uint32_t M0AR;
369  __IO uint32_t M1AR;
370  __IO uint32_t FCR;
371 } DMA_Stream_TypeDef;
372 
373 typedef struct
374 {
375  __IO uint32_t LISR;
376  __IO uint32_t HISR;
377  __IO uint32_t LIFCR;
378  __IO uint32_t HIFCR;
379 } DMA_TypeDef;
380 
381 
386 typedef struct
387 {
388  __IO uint32_t MACCR;
389  __IO uint32_t MACFFR;
390  __IO uint32_t MACHTHR;
391  __IO uint32_t MACHTLR;
392  __IO uint32_t MACMIIAR;
393  __IO uint32_t MACMIIDR;
394  __IO uint32_t MACFCR;
395  __IO uint32_t MACVLANTR; /* 8 */
396  uint32_t RESERVED0[2];
397  __IO uint32_t MACRWUFFR; /* 11 */
398  __IO uint32_t MACPMTCSR;
399  uint32_t RESERVED1[2];
400  __IO uint32_t MACSR; /* 15 */
401  __IO uint32_t MACIMR;
402  __IO uint32_t MACA0HR;
403  __IO uint32_t MACA0LR;
404  __IO uint32_t MACA1HR;
405  __IO uint32_t MACA1LR;
406  __IO uint32_t MACA2HR;
407  __IO uint32_t MACA2LR;
408  __IO uint32_t MACA3HR;
409  __IO uint32_t MACA3LR; /* 24 */
410  uint32_t RESERVED2[40];
411  __IO uint32_t MMCCR; /* 65 */
412  __IO uint32_t MMCRIR;
413  __IO uint32_t MMCTIR;
414  __IO uint32_t MMCRIMR;
415  __IO uint32_t MMCTIMR; /* 69 */
416  uint32_t RESERVED3[14];
417  __IO uint32_t MMCTGFSCCR; /* 84 */
418  __IO uint32_t MMCTGFMSCCR;
419  uint32_t RESERVED4[5];
420  __IO uint32_t MMCTGFCR;
421  uint32_t RESERVED5[10];
422  __IO uint32_t MMCRFCECR;
423  __IO uint32_t MMCRFAECR;
424  uint32_t RESERVED6[10];
425  __IO uint32_t MMCRGUFCR;
426  uint32_t RESERVED7[334];
427  __IO uint32_t PTPTSCR;
428  __IO uint32_t PTPSSIR;
429  __IO uint32_t PTPTSHR;
430  __IO uint32_t PTPTSLR;
431  __IO uint32_t PTPTSHUR;
432  __IO uint32_t PTPTSLUR;
433  __IO uint32_t PTPTSAR;
434  __IO uint32_t PTPTTHR;
435  __IO uint32_t PTPTTLR;
436  __IO uint32_t RESERVED8;
437  __IO uint32_t PTPTSSR;
438  uint32_t RESERVED9[565];
439  __IO uint32_t DMABMR;
440  __IO uint32_t DMATPDR;
441  __IO uint32_t DMARPDR;
442  __IO uint32_t DMARDLAR;
443  __IO uint32_t DMATDLAR;
444  __IO uint32_t DMASR;
445  __IO uint32_t DMAOMR;
446  __IO uint32_t DMAIER;
447  __IO uint32_t DMAMFBOCR;
448  __IO uint32_t DMARSWTR;
449  uint32_t RESERVED10[8];
450  __IO uint32_t DMACHTDR;
451  __IO uint32_t DMACHRDR;
452  __IO uint32_t DMACHTBAR;
453  __IO uint32_t DMACHRBAR;
454 } ETH_TypeDef;
455 
460 typedef struct
461 {
462  __IO uint32_t IMR;
463  __IO uint32_t EMR;
464  __IO uint32_t RTSR;
465  __IO uint32_t FTSR;
466  __IO uint32_t SWIER;
467  __IO uint32_t PR;
468 } EXTI_TypeDef;
469 
474 typedef struct
475 {
476  __IO uint32_t ACR;
477  __IO uint32_t KEYR;
478  __IO uint32_t OPTKEYR;
479  __IO uint32_t SR;
480  __IO uint32_t CR;
481  __IO uint32_t OPTCR;
482  __IO uint32_t OPTCR1;
483 } FLASH_TypeDef;
484 
485 
490 typedef struct
491 {
492  __IO uint32_t BTCR[8];
493 } FSMC_Bank1_TypeDef;
494 
499 typedef struct
500 {
501  __IO uint32_t BWTR[7];
502 } FSMC_Bank1E_TypeDef;
503 
508 typedef struct
509 {
510  __IO uint32_t PCR2;
511  __IO uint32_t SR2;
512  __IO uint32_t PMEM2;
513  __IO uint32_t PATT2;
514  uint32_t RESERVED0;
515  __IO uint32_t ECCR2;
516  uint32_t RESERVED1;
517  uint32_t RESERVED2;
518  __IO uint32_t PCR3;
519  __IO uint32_t SR3;
520  __IO uint32_t PMEM3;
521  __IO uint32_t PATT3;
522  uint32_t RESERVED3;
523  __IO uint32_t ECCR3;
524 } FSMC_Bank2_3_TypeDef;
525 
530 typedef struct
531 {
532  __IO uint32_t PCR4;
533  __IO uint32_t SR4;
534  __IO uint32_t PMEM4;
535  __IO uint32_t PATT4;
536  __IO uint32_t PIO4;
537 } FSMC_Bank4_TypeDef;
538 
539 
544 typedef struct
545 {
546  __IO uint32_t MODER;
547  __IO uint32_t OTYPER;
548  __IO uint32_t OSPEEDR;
549  __IO uint32_t PUPDR;
550  __IO uint32_t IDR;
551  __IO uint32_t ODR;
552  __IO uint32_t BSRR;
553  __IO uint32_t LCKR;
554  __IO uint32_t AFR[2];
555 } GPIO_TypeDef;
556 
561 typedef struct
562 {
563  __IO uint32_t MEMRMP;
564  __IO uint32_t PMC;
565  __IO uint32_t EXTICR[4];
566  uint32_t RESERVED[2];
567  __IO uint32_t CMPCR;
568 } SYSCFG_TypeDef;
569 
574 typedef struct
575 {
576  __IO uint32_t CR1;
577  __IO uint32_t CR2;
578  __IO uint32_t OAR1;
579  __IO uint32_t OAR2;
580  __IO uint32_t DR;
581  __IO uint32_t SR1;
582  __IO uint32_t SR2;
583  __IO uint32_t CCR;
584  __IO uint32_t TRISE;
585  __IO uint32_t FLTR;
586 } I2C_TypeDef;
587 
592 typedef struct
593 {
594  __IO uint32_t KR;
595  __IO uint32_t PR;
596  __IO uint32_t RLR;
597  __IO uint32_t SR;
598 } IWDG_TypeDef;
599 
604 typedef struct
605 {
606  __IO uint32_t CR;
607  __IO uint32_t CSR;
608 } PWR_TypeDef;
609 
614 typedef struct
615 {
616  __IO uint32_t CR;
617  __IO uint32_t PLLCFGR;
618  __IO uint32_t CFGR;
619  __IO uint32_t CIR;
620  __IO uint32_t AHB1RSTR;
621  __IO uint32_t AHB2RSTR;
622  __IO uint32_t AHB3RSTR;
623  uint32_t RESERVED0;
624  __IO uint32_t APB1RSTR;
625  __IO uint32_t APB2RSTR;
626  uint32_t RESERVED1[2];
627  __IO uint32_t AHB1ENR;
628  __IO uint32_t AHB2ENR;
629  __IO uint32_t AHB3ENR;
630  uint32_t RESERVED2;
631  __IO uint32_t APB1ENR;
632  __IO uint32_t APB2ENR;
633  uint32_t RESERVED3[2];
634  __IO uint32_t AHB1LPENR;
635  __IO uint32_t AHB2LPENR;
636  __IO uint32_t AHB3LPENR;
637  uint32_t RESERVED4;
638  __IO uint32_t APB1LPENR;
639  __IO uint32_t APB2LPENR;
640  uint32_t RESERVED5[2];
641  __IO uint32_t BDCR;
642  __IO uint32_t CSR;
643  uint32_t RESERVED6[2];
644  __IO uint32_t SSCGR;
645  __IO uint32_t PLLI2SCFGR;
647 } RCC_TypeDef;
648 
653 typedef struct
654 {
655  __IO uint32_t TR;
656  __IO uint32_t DR;
657  __IO uint32_t CR;
658  __IO uint32_t ISR;
659  __IO uint32_t PRER;
660  __IO uint32_t WUTR;
661  __IO uint32_t CALIBR;
662  __IO uint32_t ALRMAR;
663  __IO uint32_t ALRMBR;
664  __IO uint32_t WPR;
665  __IO uint32_t SSR;
666  __IO uint32_t SHIFTR;
667  __IO uint32_t TSTR;
668  __IO uint32_t TSDR;
669  __IO uint32_t TSSSR;
670  __IO uint32_t CALR;
671  __IO uint32_t TAFCR;
672  __IO uint32_t ALRMASSR;
673  __IO uint32_t ALRMBSSR;
674  uint32_t RESERVED7;
675  __IO uint32_t BKP0R;
676  __IO uint32_t BKP1R;
677  __IO uint32_t BKP2R;
678  __IO uint32_t BKP3R;
679  __IO uint32_t BKP4R;
680  __IO uint32_t BKP5R;
681  __IO uint32_t BKP6R;
682  __IO uint32_t BKP7R;
683  __IO uint32_t BKP8R;
684  __IO uint32_t BKP9R;
685  __IO uint32_t BKP10R;
686  __IO uint32_t BKP11R;
687  __IO uint32_t BKP12R;
688  __IO uint32_t BKP13R;
689  __IO uint32_t BKP14R;
690  __IO uint32_t BKP15R;
691  __IO uint32_t BKP16R;
692  __IO uint32_t BKP17R;
693  __IO uint32_t BKP18R;
694  __IO uint32_t BKP19R;
695 } RTC_TypeDef;
696 
697 
702 typedef struct
703 {
704  __IO uint32_t POWER;
705  __IO uint32_t CLKCR;
706  __IO uint32_t ARG;
707  __IO uint32_t CMD;
708  __I uint32_t RESPCMD;
709  __I uint32_t RESP1;
710  __I uint32_t RESP2;
711  __I uint32_t RESP3;
712  __I uint32_t RESP4;
713  __IO uint32_t DTIMER;
714  __IO uint32_t DLEN;
715  __IO uint32_t DCTRL;
716  __I uint32_t DCOUNT;
717  __I uint32_t STA;
718  __IO uint32_t ICR;
719  __IO uint32_t MASK;
720  uint32_t RESERVED0[2];
721  __I uint32_t FIFOCNT;
722  uint32_t RESERVED1[13];
723  __IO uint32_t FIFO;
724 } SDIO_TypeDef;
725 
730 typedef struct
731 {
732  __IO uint32_t CR1;
733  __IO uint32_t CR2;
734  __IO uint32_t SR;
735  __IO uint32_t DR;
736  __IO uint32_t CRCPR;
737  __IO uint32_t RXCRCR;
738  __IO uint32_t TXCRCR;
739  __IO uint32_t I2SCFGR;
740  __IO uint32_t I2SPR;
741 } SPI_TypeDef;
742 
747 typedef struct
748 {
749  __IO uint32_t CR1;
750  __IO uint32_t CR2;
751  __IO uint32_t SMCR;
752  __IO uint32_t DIER;
753  __IO uint32_t SR;
754  __IO uint32_t EGR;
755  __IO uint32_t CCMR1;
756  __IO uint32_t CCMR2;
757  __IO uint32_t CCER;
758  __IO uint32_t CNT;
759  __IO uint32_t PSC;
760  __IO uint32_t ARR;
761  __IO uint32_t RCR;
762  __IO uint32_t CCR1;
763  __IO uint32_t CCR2;
764  __IO uint32_t CCR3;
765  __IO uint32_t CCR4;
766  __IO uint32_t BDTR;
767  __IO uint32_t DCR;
768  __IO uint32_t DMAR;
769  __IO uint32_t OR;
770 } TIM_TypeDef;
771 
776 typedef struct
777 {
778  __IO uint32_t SR;
779  __IO uint32_t DR;
780  __IO uint32_t BRR;
781  __IO uint32_t CR1;
782  __IO uint32_t CR2;
783  __IO uint32_t CR3;
784  __IO uint32_t GTPR;
785 } USART_TypeDef;
786 
791 typedef struct
792 {
793  __IO uint32_t CR;
794  __IO uint32_t CFR;
795  __IO uint32_t SR;
796 } WWDG_TypeDef;
797 
802 typedef struct
803 {
804  __IO uint32_t CR;
805  __IO uint32_t SR;
806  __IO uint32_t DR;
807 } RNG_TypeDef;
808 
809 
810 
814 typedef struct
815 {
816  __IO uint32_t GOTGCTL;
817  __IO uint32_t GOTGINT;
818  __IO uint32_t GAHBCFG;
819  __IO uint32_t GUSBCFG;
820  __IO uint32_t GRSTCTL;
821  __IO uint32_t GINTSTS;
822  __IO uint32_t GINTMSK;
823  __IO uint32_t GRXSTSR;
824  __IO uint32_t GRXSTSP;
825  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
826  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
827  __IO uint32_t HNPTXSTS;
828  uint32_t Reserved30[2]; /* Reserved 030h*/
829  __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
830  __IO uint32_t CID; /* User ID Register 03Ch*/
831  uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
832  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
833  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
834 }
835 USB_OTG_GlobalTypeDef;
836 
837 
838 
842 typedef struct
843 {
844  __IO uint32_t DCFG; /* dev Configuration Register 800h*/
845  __IO uint32_t DCTL; /* dev Control Register 804h*/
846  __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
847  uint32_t Reserved0C; /* Reserved 80Ch*/
848  __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
849  __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
850  __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
851  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
852  uint32_t Reserved20; /* Reserved 820h*/
853  uint32_t Reserved9; /* Reserved 824h*/
854  __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
855  __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
856  __IO uint32_t DTHRCTL; /* dev thr 830h*/
857  __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
858  __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
859  __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
860  uint32_t Reserved40; /* dedicated EP mask 840h*/
861  __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
862  uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
863  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
864 }
865 USB_OTG_DeviceTypeDef;
866 
867 
871 typedef struct
872 {
873  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
874  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
875  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
876  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
877  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
878  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
879  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
880  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
881 }
882 USB_OTG_INEndpointTypeDef;
883 
884 
888 typedef struct
889 {
890  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
891  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
892  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
893  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
894  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
895  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
896  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
897 }
898 USB_OTG_OUTEndpointTypeDef;
899 
900 
904 typedef struct
905 {
906  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
907  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
908  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
909  uint32_t Reserved40C; /* Reserved 40Ch*/
910  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
911  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
912  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
913 }
914 USB_OTG_HostTypeDef;
915 
916 
920 typedef struct
921 {
922  __IO uint32_t HCCHAR;
923  __IO uint32_t HCSPLT;
924  __IO uint32_t HCINT;
925  __IO uint32_t HCINTMSK;
926  __IO uint32_t HCTSIZ;
927  __IO uint32_t HCDMA;
928  uint32_t Reserved[2];
929 }
930 USB_OTG_HostChannelTypeDef;
931 
932 
936 #define FLASH_BASE 0x08000000U
937 #define CCMDATARAM_BASE 0x10000000U
938 #define SRAM1_BASE 0x20000000U
939 #define SRAM2_BASE 0x2001C000U
940 #define PERIPH_BASE 0x40000000U
941 #define BKPSRAM_BASE 0x40024000U
942 #define FSMC_R_BASE 0xA0000000U
943 #define SRAM1_BB_BASE 0x22000000U
944 #define SRAM2_BB_BASE 0x22380000U
945 #define PERIPH_BB_BASE 0x42000000U
946 #define BKPSRAM_BB_BASE 0x42480000U
947 #define FLASH_END 0x080FFFFFU
948 #define CCMDATARAM_END 0x1000FFFFU
950 /* Legacy defines */
951 #define SRAM_BASE SRAM1_BASE
952 #define SRAM_BB_BASE SRAM1_BB_BASE
953 
954 
956 #define APB1PERIPH_BASE PERIPH_BASE
957 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
958 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
959 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
960 
962 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
963 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
964 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
965 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
966 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
967 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
968 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
969 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
970 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
971 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
972 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
973 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
974 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
975 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
976 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
977 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
978 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
979 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
980 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
981 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
982 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
983 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
984 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
985 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
986 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
987 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
988 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
989 
991 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
992 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
993 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
994 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
995 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
996 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
997 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
998 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
999 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1000 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1001 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1002 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1003 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1004 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1005 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1006 
1008 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1009 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1010 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1011 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1012 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1013 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1014 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1015 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1016 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1017 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1018 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1019 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1020 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1021 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1022 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1023 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1024 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1025 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1026 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1027 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1028 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1029 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1030 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1031 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1032 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1033 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1034 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1035 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1036 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1037 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1038 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1039 #define ETH_MAC_BASE (ETH_BASE)
1040 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1041 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1042 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1043 
1045 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1046 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1047 
1049 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
1050 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
1051 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
1052 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
1053 
1054 /* Debug MCU registers base address */
1055 #define DBGMCU_BASE 0xE0042000U
1056 
1058 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1059 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1060 
1061 #define USB_OTG_GLOBAL_BASE 0x000U
1062 #define USB_OTG_DEVICE_BASE 0x800U
1063 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1064 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1065 #define USB_OTG_EP_REG_SIZE 0x20U
1066 #define USB_OTG_HOST_BASE 0x400U
1067 #define USB_OTG_HOST_PORT_BASE 0x440U
1068 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1069 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1070 #define USB_OTG_PCGCCTL_BASE 0xE00U
1071 #define USB_OTG_FIFO_BASE 0x1000U
1072 #define USB_OTG_FIFO_SIZE 0x1000U
1073 
1081 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1082 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1083 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1084 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1085 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1086 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1087 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1088 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1089 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1090 #define RTC ((RTC_TypeDef *) RTC_BASE)
1091 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1092 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1093 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1094 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1095 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1096 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1097 #define USART2 ((USART_TypeDef *) USART2_BASE)
1098 #define USART3 ((USART_TypeDef *) USART3_BASE)
1099 #define UART4 ((USART_TypeDef *) UART4_BASE)
1100 #define UART5 ((USART_TypeDef *) UART5_BASE)
1101 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1102 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1103 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1104 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1105 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1106 #define PWR ((PWR_TypeDef *) PWR_BASE)
1107 #define DAC ((DAC_TypeDef *) DAC_BASE)
1108 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1109 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1110 #define USART1 ((USART_TypeDef *) USART1_BASE)
1111 #define USART6 ((USART_TypeDef *) USART6_BASE)
1112 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1113 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1114 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1115 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1116 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1117 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1118 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1119 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1120 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1121 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1122 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1123 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1124 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1125 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1126 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1127 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1128 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1129 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1130 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1131 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1132 #define CRC ((CRC_TypeDef *) CRC_BASE)
1133 #define RCC ((RCC_TypeDef *) RCC_BASE)
1134 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1135 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1136 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1137 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1138 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1139 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1140 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1141 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1142 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1143 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1144 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1145 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1146 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1147 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1148 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1149 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1150 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1151 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1152 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1153 #define ETH ((ETH_TypeDef *) ETH_BASE)
1154 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1155 #define RNG ((RNG_TypeDef *) RNG_BASE)
1156 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1157 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1158 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1159 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1160 
1161 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1162 
1163 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1164 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1165 
1178 /******************************************************************************/
1179 /* Peripheral Registers_Bits_Definition */
1180 /******************************************************************************/
1181 
1182 /******************************************************************************/
1183 /* */
1184 /* Analog to Digital Converter */
1185 /* */
1186 /******************************************************************************/
1187 /******************** Bit definition for ADC_SR register ********************/
1188 #define ADC_SR_AWD 0x00000001U
1189 #define ADC_SR_EOC 0x00000002U
1190 #define ADC_SR_JEOC 0x00000004U
1191 #define ADC_SR_JSTRT 0x00000008U
1192 #define ADC_SR_STRT 0x00000010U
1193 #define ADC_SR_OVR 0x00000020U
1195 /******************* Bit definition for ADC_CR1 register ********************/
1196 #define ADC_CR1_AWDCH 0x0000001FU
1197 #define ADC_CR1_AWDCH_0 0x00000001U
1198 #define ADC_CR1_AWDCH_1 0x00000002U
1199 #define ADC_CR1_AWDCH_2 0x00000004U
1200 #define ADC_CR1_AWDCH_3 0x00000008U
1201 #define ADC_CR1_AWDCH_4 0x00000010U
1202 #define ADC_CR1_EOCIE 0x00000020U
1203 #define ADC_CR1_AWDIE 0x00000040U
1204 #define ADC_CR1_JEOCIE 0x00000080U
1205 #define ADC_CR1_SCAN 0x00000100U
1206 #define ADC_CR1_AWDSGL 0x00000200U
1207 #define ADC_CR1_JAUTO 0x00000400U
1208 #define ADC_CR1_DISCEN 0x00000800U
1209 #define ADC_CR1_JDISCEN 0x00001000U
1210 #define ADC_CR1_DISCNUM 0x0000E000U
1211 #define ADC_CR1_DISCNUM_0 0x00002000U
1212 #define ADC_CR1_DISCNUM_1 0x00004000U
1213 #define ADC_CR1_DISCNUM_2 0x00008000U
1214 #define ADC_CR1_JAWDEN 0x00400000U
1215 #define ADC_CR1_AWDEN 0x00800000U
1216 #define ADC_CR1_RES 0x03000000U
1217 #define ADC_CR1_RES_0 0x01000000U
1218 #define ADC_CR1_RES_1 0x02000000U
1219 #define ADC_CR1_OVRIE 0x04000000U
1221 /******************* Bit definition for ADC_CR2 register ********************/
1222 #define ADC_CR2_ADON 0x00000001U
1223 #define ADC_CR2_CONT 0x00000002U
1224 #define ADC_CR2_DMA 0x00000100U
1225 #define ADC_CR2_DDS 0x00000200U
1226 #define ADC_CR2_EOCS 0x00000400U
1227 #define ADC_CR2_ALIGN 0x00000800U
1228 #define ADC_CR2_JEXTSEL 0x000F0000U
1229 #define ADC_CR2_JEXTSEL_0 0x00010000U
1230 #define ADC_CR2_JEXTSEL_1 0x00020000U
1231 #define ADC_CR2_JEXTSEL_2 0x00040000U
1232 #define ADC_CR2_JEXTSEL_3 0x00080000U
1233 #define ADC_CR2_JEXTEN 0x00300000U
1234 #define ADC_CR2_JEXTEN_0 0x00100000U
1235 #define ADC_CR2_JEXTEN_1 0x00200000U
1236 #define ADC_CR2_JSWSTART 0x00400000U
1237 #define ADC_CR2_EXTSEL 0x0F000000U
1238 #define ADC_CR2_EXTSEL_0 0x01000000U
1239 #define ADC_CR2_EXTSEL_1 0x02000000U
1240 #define ADC_CR2_EXTSEL_2 0x04000000U
1241 #define ADC_CR2_EXTSEL_3 0x08000000U
1242 #define ADC_CR2_EXTEN 0x30000000U
1243 #define ADC_CR2_EXTEN_0 0x10000000U
1244 #define ADC_CR2_EXTEN_1 0x20000000U
1245 #define ADC_CR2_SWSTART 0x40000000U
1247 /****************** Bit definition for ADC_SMPR1 register *******************/
1248 #define ADC_SMPR1_SMP10 0x00000007U
1249 #define ADC_SMPR1_SMP10_0 0x00000001U
1250 #define ADC_SMPR1_SMP10_1 0x00000002U
1251 #define ADC_SMPR1_SMP10_2 0x00000004U
1252 #define ADC_SMPR1_SMP11 0x00000038U
1253 #define ADC_SMPR1_SMP11_0 0x00000008U
1254 #define ADC_SMPR1_SMP11_1 0x00000010U
1255 #define ADC_SMPR1_SMP11_2 0x00000020U
1256 #define ADC_SMPR1_SMP12 0x000001C0U
1257 #define ADC_SMPR1_SMP12_0 0x00000040U
1258 #define ADC_SMPR1_SMP12_1 0x00000080U
1259 #define ADC_SMPR1_SMP12_2 0x00000100U
1260 #define ADC_SMPR1_SMP13 0x00000E00U
1261 #define ADC_SMPR1_SMP13_0 0x00000200U
1262 #define ADC_SMPR1_SMP13_1 0x00000400U
1263 #define ADC_SMPR1_SMP13_2 0x00000800U
1264 #define ADC_SMPR1_SMP14 0x00007000U
1265 #define ADC_SMPR1_SMP14_0 0x00001000U
1266 #define ADC_SMPR1_SMP14_1 0x00002000U
1267 #define ADC_SMPR1_SMP14_2 0x00004000U
1268 #define ADC_SMPR1_SMP15 0x00038000U
1269 #define ADC_SMPR1_SMP15_0 0x00008000U
1270 #define ADC_SMPR1_SMP15_1 0x00010000U
1271 #define ADC_SMPR1_SMP15_2 0x00020000U
1272 #define ADC_SMPR1_SMP16 0x001C0000U
1273 #define ADC_SMPR1_SMP16_0 0x00040000U
1274 #define ADC_SMPR1_SMP16_1 0x00080000U
1275 #define ADC_SMPR1_SMP16_2 0x00100000U
1276 #define ADC_SMPR1_SMP17 0x00E00000U
1277 #define ADC_SMPR1_SMP17_0 0x00200000U
1278 #define ADC_SMPR1_SMP17_1 0x00400000U
1279 #define ADC_SMPR1_SMP17_2 0x00800000U
1280 #define ADC_SMPR1_SMP18 0x07000000U
1281 #define ADC_SMPR1_SMP18_0 0x01000000U
1282 #define ADC_SMPR1_SMP18_1 0x02000000U
1283 #define ADC_SMPR1_SMP18_2 0x04000000U
1285 /****************** Bit definition for ADC_SMPR2 register *******************/
1286 #define ADC_SMPR2_SMP0 0x00000007U
1287 #define ADC_SMPR2_SMP0_0 0x00000001U
1288 #define ADC_SMPR2_SMP0_1 0x00000002U
1289 #define ADC_SMPR2_SMP0_2 0x00000004U
1290 #define ADC_SMPR2_SMP1 0x00000038U
1291 #define ADC_SMPR2_SMP1_0 0x00000008U
1292 #define ADC_SMPR2_SMP1_1 0x00000010U
1293 #define ADC_SMPR2_SMP1_2 0x00000020U
1294 #define ADC_SMPR2_SMP2 0x000001C0U
1295 #define ADC_SMPR2_SMP2_0 0x00000040U
1296 #define ADC_SMPR2_SMP2_1 0x00000080U
1297 #define ADC_SMPR2_SMP2_2 0x00000100U
1298 #define ADC_SMPR2_SMP3 0x00000E00U
1299 #define ADC_SMPR2_SMP3_0 0x00000200U
1300 #define ADC_SMPR2_SMP3_1 0x00000400U
1301 #define ADC_SMPR2_SMP3_2 0x00000800U
1302 #define ADC_SMPR2_SMP4 0x00007000U
1303 #define ADC_SMPR2_SMP4_0 0x00001000U
1304 #define ADC_SMPR2_SMP4_1 0x00002000U
1305 #define ADC_SMPR2_SMP4_2 0x00004000U
1306 #define ADC_SMPR2_SMP5 0x00038000U
1307 #define ADC_SMPR2_SMP5_0 0x00008000U
1308 #define ADC_SMPR2_SMP5_1 0x00010000U
1309 #define ADC_SMPR2_SMP5_2 0x00020000U
1310 #define ADC_SMPR2_SMP6 0x001C0000U
1311 #define ADC_SMPR2_SMP6_0 0x00040000U
1312 #define ADC_SMPR2_SMP6_1 0x00080000U
1313 #define ADC_SMPR2_SMP6_2 0x00100000U
1314 #define ADC_SMPR2_SMP7 0x00E00000U
1315 #define ADC_SMPR2_SMP7_0 0x00200000U
1316 #define ADC_SMPR2_SMP7_1 0x00400000U
1317 #define ADC_SMPR2_SMP7_2 0x00800000U
1318 #define ADC_SMPR2_SMP8 0x07000000U
1319 #define ADC_SMPR2_SMP8_0 0x01000000U
1320 #define ADC_SMPR2_SMP8_1 0x02000000U
1321 #define ADC_SMPR2_SMP8_2 0x04000000U
1322 #define ADC_SMPR2_SMP9 0x38000000U
1323 #define ADC_SMPR2_SMP9_0 0x08000000U
1324 #define ADC_SMPR2_SMP9_1 0x10000000U
1325 #define ADC_SMPR2_SMP9_2 0x20000000U
1327 /****************** Bit definition for ADC_JOFR1 register *******************/
1328 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1330 /****************** Bit definition for ADC_JOFR2 register *******************/
1331 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1333 /****************** Bit definition for ADC_JOFR3 register *******************/
1334 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1336 /****************** Bit definition for ADC_JOFR4 register *******************/
1337 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1339 /******************* Bit definition for ADC_HTR register ********************/
1340 #define ADC_HTR_HT 0x0FFFU
1342 /******************* Bit definition for ADC_LTR register ********************/
1343 #define ADC_LTR_LT 0x0FFFU
1345 /******************* Bit definition for ADC_SQR1 register *******************/
1346 #define ADC_SQR1_SQ13 0x0000001FU
1347 #define ADC_SQR1_SQ13_0 0x00000001U
1348 #define ADC_SQR1_SQ13_1 0x00000002U
1349 #define ADC_SQR1_SQ13_2 0x00000004U
1350 #define ADC_SQR1_SQ13_3 0x00000008U
1351 #define ADC_SQR1_SQ13_4 0x00000010U
1352 #define ADC_SQR1_SQ14 0x000003E0U
1353 #define ADC_SQR1_SQ14_0 0x00000020U
1354 #define ADC_SQR1_SQ14_1 0x00000040U
1355 #define ADC_SQR1_SQ14_2 0x00000080U
1356 #define ADC_SQR1_SQ14_3 0x00000100U
1357 #define ADC_SQR1_SQ14_4 0x00000200U
1358 #define ADC_SQR1_SQ15 0x00007C00U
1359 #define ADC_SQR1_SQ15_0 0x00000400U
1360 #define ADC_SQR1_SQ15_1 0x00000800U
1361 #define ADC_SQR1_SQ15_2 0x00001000U
1362 #define ADC_SQR1_SQ15_3 0x00002000U
1363 #define ADC_SQR1_SQ15_4 0x00004000U
1364 #define ADC_SQR1_SQ16 0x000F8000U
1365 #define ADC_SQR1_SQ16_0 0x00008000U
1366 #define ADC_SQR1_SQ16_1 0x00010000U
1367 #define ADC_SQR1_SQ16_2 0x00020000U
1368 #define ADC_SQR1_SQ16_3 0x00040000U
1369 #define ADC_SQR1_SQ16_4 0x00080000U
1370 #define ADC_SQR1_L 0x00F00000U
1371 #define ADC_SQR1_L_0 0x00100000U
1372 #define ADC_SQR1_L_1 0x00200000U
1373 #define ADC_SQR1_L_2 0x00400000U
1374 #define ADC_SQR1_L_3 0x00800000U
1376 /******************* Bit definition for ADC_SQR2 register *******************/
1377 #define ADC_SQR2_SQ7 0x0000001FU
1378 #define ADC_SQR2_SQ7_0 0x00000001U
1379 #define ADC_SQR2_SQ7_1 0x00000002U
1380 #define ADC_SQR2_SQ7_2 0x00000004U
1381 #define ADC_SQR2_SQ7_3 0x00000008U
1382 #define ADC_SQR2_SQ7_4 0x00000010U
1383 #define ADC_SQR2_SQ8 0x000003E0U
1384 #define ADC_SQR2_SQ8_0 0x00000020U
1385 #define ADC_SQR2_SQ8_1 0x00000040U
1386 #define ADC_SQR2_SQ8_2 0x00000080U
1387 #define ADC_SQR2_SQ8_3 0x00000100U
1388 #define ADC_SQR2_SQ8_4 0x00000200U
1389 #define ADC_SQR2_SQ9 0x00007C00U
1390 #define ADC_SQR2_SQ9_0 0x00000400U
1391 #define ADC_SQR2_SQ9_1 0x00000800U
1392 #define ADC_SQR2_SQ9_2 0x00001000U
1393 #define ADC_SQR2_SQ9_3 0x00002000U
1394 #define ADC_SQR2_SQ9_4 0x00004000U
1395 #define ADC_SQR2_SQ10 0x000F8000U
1396 #define ADC_SQR2_SQ10_0 0x00008000U
1397 #define ADC_SQR2_SQ10_1 0x00010000U
1398 #define ADC_SQR2_SQ10_2 0x00020000U
1399 #define ADC_SQR2_SQ10_3 0x00040000U
1400 #define ADC_SQR2_SQ10_4 0x00080000U
1401 #define ADC_SQR2_SQ11 0x01F00000U
1402 #define ADC_SQR2_SQ11_0 0x00100000U
1403 #define ADC_SQR2_SQ11_1 0x00200000U
1404 #define ADC_SQR2_SQ11_2 0x00400000U
1405 #define ADC_SQR2_SQ11_3 0x00800000U
1406 #define ADC_SQR2_SQ11_4 0x01000000U
1407 #define ADC_SQR2_SQ12 0x3E000000U
1408 #define ADC_SQR2_SQ12_0 0x02000000U
1409 #define ADC_SQR2_SQ12_1 0x04000000U
1410 #define ADC_SQR2_SQ12_2 0x08000000U
1411 #define ADC_SQR2_SQ12_3 0x10000000U
1412 #define ADC_SQR2_SQ12_4 0x20000000U
1414 /******************* Bit definition for ADC_SQR3 register *******************/
1415 #define ADC_SQR3_SQ1 0x0000001FU
1416 #define ADC_SQR3_SQ1_0 0x00000001U
1417 #define ADC_SQR3_SQ1_1 0x00000002U
1418 #define ADC_SQR3_SQ1_2 0x00000004U
1419 #define ADC_SQR3_SQ1_3 0x00000008U
1420 #define ADC_SQR3_SQ1_4 0x00000010U
1421 #define ADC_SQR3_SQ2 0x000003E0U
1422 #define ADC_SQR3_SQ2_0 0x00000020U
1423 #define ADC_SQR3_SQ2_1 0x00000040U
1424 #define ADC_SQR3_SQ2_2 0x00000080U
1425 #define ADC_SQR3_SQ2_3 0x00000100U
1426 #define ADC_SQR3_SQ2_4 0x00000200U
1427 #define ADC_SQR3_SQ3 0x00007C00U
1428 #define ADC_SQR3_SQ3_0 0x00000400U
1429 #define ADC_SQR3_SQ3_1 0x00000800U
1430 #define ADC_SQR3_SQ3_2 0x00001000U
1431 #define ADC_SQR3_SQ3_3 0x00002000U
1432 #define ADC_SQR3_SQ3_4 0x00004000U
1433 #define ADC_SQR3_SQ4 0x000F8000U
1434 #define ADC_SQR3_SQ4_0 0x00008000U
1435 #define ADC_SQR3_SQ4_1 0x00010000U
1436 #define ADC_SQR3_SQ4_2 0x00020000U
1437 #define ADC_SQR3_SQ4_3 0x00040000U
1438 #define ADC_SQR3_SQ4_4 0x00080000U
1439 #define ADC_SQR3_SQ5 0x01F00000U
1440 #define ADC_SQR3_SQ5_0 0x00100000U
1441 #define ADC_SQR3_SQ5_1 0x00200000U
1442 #define ADC_SQR3_SQ5_2 0x00400000U
1443 #define ADC_SQR3_SQ5_3 0x00800000U
1444 #define ADC_SQR3_SQ5_4 0x01000000U
1445 #define ADC_SQR3_SQ6 0x3E000000U
1446 #define ADC_SQR3_SQ6_0 0x02000000U
1447 #define ADC_SQR3_SQ6_1 0x04000000U
1448 #define ADC_SQR3_SQ6_2 0x08000000U
1449 #define ADC_SQR3_SQ6_3 0x10000000U
1450 #define ADC_SQR3_SQ6_4 0x20000000U
1452 /******************* Bit definition for ADC_JSQR register *******************/
1453 #define ADC_JSQR_JSQ1 0x0000001FU
1454 #define ADC_JSQR_JSQ1_0 0x00000001U
1455 #define ADC_JSQR_JSQ1_1 0x00000002U
1456 #define ADC_JSQR_JSQ1_2 0x00000004U
1457 #define ADC_JSQR_JSQ1_3 0x00000008U
1458 #define ADC_JSQR_JSQ1_4 0x00000010U
1459 #define ADC_JSQR_JSQ2 0x000003E0U
1460 #define ADC_JSQR_JSQ2_0 0x00000020U
1461 #define ADC_JSQR_JSQ2_1 0x00000040U
1462 #define ADC_JSQR_JSQ2_2 0x00000080U
1463 #define ADC_JSQR_JSQ2_3 0x00000100U
1464 #define ADC_JSQR_JSQ2_4 0x00000200U
1465 #define ADC_JSQR_JSQ3 0x00007C00U
1466 #define ADC_JSQR_JSQ3_0 0x00000400U
1467 #define ADC_JSQR_JSQ3_1 0x00000800U
1468 #define ADC_JSQR_JSQ3_2 0x00001000U
1469 #define ADC_JSQR_JSQ3_3 0x00002000U
1470 #define ADC_JSQR_JSQ3_4 0x00004000U
1471 #define ADC_JSQR_JSQ4 0x000F8000U
1472 #define ADC_JSQR_JSQ4_0 0x00008000U
1473 #define ADC_JSQR_JSQ4_1 0x00010000U
1474 #define ADC_JSQR_JSQ4_2 0x00020000U
1475 #define ADC_JSQR_JSQ4_3 0x00040000U
1476 #define ADC_JSQR_JSQ4_4 0x00080000U
1477 #define ADC_JSQR_JL 0x00300000U
1478 #define ADC_JSQR_JL_0 0x00100000U
1479 #define ADC_JSQR_JL_1 0x00200000U
1481 /******************* Bit definition for ADC_JDR1 register *******************/
1482 #define ADC_JDR1_JDATA 0xFFFFU
1484 /******************* Bit definition for ADC_JDR2 register *******************/
1485 #define ADC_JDR2_JDATA 0xFFFFU
1487 /******************* Bit definition for ADC_JDR3 register *******************/
1488 #define ADC_JDR3_JDATA 0xFFFFU
1490 /******************* Bit definition for ADC_JDR4 register *******************/
1491 #define ADC_JDR4_JDATA 0xFFFFU
1493 /******************** Bit definition for ADC_DR register ********************/
1494 #define ADC_DR_DATA 0x0000FFFFU
1495 #define ADC_DR_ADC2DATA 0xFFFF0000U
1497 /******************* Bit definition for ADC_CSR register ********************/
1498 #define ADC_CSR_AWD1 0x00000001U
1499 #define ADC_CSR_EOC1 0x00000002U
1500 #define ADC_CSR_JEOC1 0x00000004U
1501 #define ADC_CSR_JSTRT1 0x00000008U
1502 #define ADC_CSR_STRT1 0x00000010U
1503 #define ADC_CSR_OVR1 0x00000020U
1504 #define ADC_CSR_AWD2 0x00000100U
1505 #define ADC_CSR_EOC2 0x00000200U
1506 #define ADC_CSR_JEOC2 0x00000400U
1507 #define ADC_CSR_JSTRT2 0x00000800U
1508 #define ADC_CSR_STRT2 0x00001000U
1509 #define ADC_CSR_OVR2 0x00002000U
1510 #define ADC_CSR_AWD3 0x00010000U
1511 #define ADC_CSR_EOC3 0x00020000U
1512 #define ADC_CSR_JEOC3 0x00040000U
1513 #define ADC_CSR_JSTRT3 0x00080000U
1514 #define ADC_CSR_STRT3 0x00100000U
1515 #define ADC_CSR_OVR3 0x00200000U
1517 /* Legacy defines */
1518 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1519 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1520 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1521 
1522 /******************* Bit definition for ADC_CCR register ********************/
1523 #define ADC_CCR_MULTI 0x0000001FU
1524 #define ADC_CCR_MULTI_0 0x00000001U
1525 #define ADC_CCR_MULTI_1 0x00000002U
1526 #define ADC_CCR_MULTI_2 0x00000004U
1527 #define ADC_CCR_MULTI_3 0x00000008U
1528 #define ADC_CCR_MULTI_4 0x00000010U
1529 #define ADC_CCR_DELAY 0x00000F00U
1530 #define ADC_CCR_DELAY_0 0x00000100U
1531 #define ADC_CCR_DELAY_1 0x00000200U
1532 #define ADC_CCR_DELAY_2 0x00000400U
1533 #define ADC_CCR_DELAY_3 0x00000800U
1534 #define ADC_CCR_DDS 0x00002000U
1535 #define ADC_CCR_DMA 0x0000C000U
1536 #define ADC_CCR_DMA_0 0x00004000U
1537 #define ADC_CCR_DMA_1 0x00008000U
1538 #define ADC_CCR_ADCPRE 0x00030000U
1539 #define ADC_CCR_ADCPRE_0 0x00010000U
1540 #define ADC_CCR_ADCPRE_1 0x00020000U
1541 #define ADC_CCR_VBATE 0x00400000U
1542 #define ADC_CCR_TSVREFE 0x00800000U
1544 /******************* Bit definition for ADC_CDR register ********************/
1545 #define ADC_CDR_DATA1 0x0000FFFFU
1546 #define ADC_CDR_DATA2 0xFFFF0000U
1548 /******************************************************************************/
1549 /* */
1550 /* Controller Area Network */
1551 /* */
1552 /******************************************************************************/
1554 /******************* Bit definition for CAN_MCR register ********************/
1555 #define CAN_MCR_INRQ 0x00000001U
1556 #define CAN_MCR_SLEEP 0x00000002U
1557 #define CAN_MCR_TXFP 0x00000004U
1558 #define CAN_MCR_RFLM 0x00000008U
1559 #define CAN_MCR_NART 0x00000010U
1560 #define CAN_MCR_AWUM 0x00000020U
1561 #define CAN_MCR_ABOM 0x00000040U
1562 #define CAN_MCR_TTCM 0x00000080U
1563 #define CAN_MCR_RESET 0x00008000U
1564 #define CAN_MCR_DBF 0x00010000U
1565 /******************* Bit definition for CAN_MSR register ********************/
1566 #define CAN_MSR_INAK 0x0001U
1567 #define CAN_MSR_SLAK 0x0002U
1568 #define CAN_MSR_ERRI 0x0004U
1569 #define CAN_MSR_WKUI 0x0008U
1570 #define CAN_MSR_SLAKI 0x0010U
1571 #define CAN_MSR_TXM 0x0100U
1572 #define CAN_MSR_RXM 0x0200U
1573 #define CAN_MSR_SAMP 0x0400U
1574 #define CAN_MSR_RX 0x0800U
1576 /******************* Bit definition for CAN_TSR register ********************/
1577 #define CAN_TSR_RQCP0 0x00000001U
1578 #define CAN_TSR_TXOK0 0x00000002U
1579 #define CAN_TSR_ALST0 0x00000004U
1580 #define CAN_TSR_TERR0 0x00000008U
1581 #define CAN_TSR_ABRQ0 0x00000080U
1582 #define CAN_TSR_RQCP1 0x00000100U
1583 #define CAN_TSR_TXOK1 0x00000200U
1584 #define CAN_TSR_ALST1 0x00000400U
1585 #define CAN_TSR_TERR1 0x00000800U
1586 #define CAN_TSR_ABRQ1 0x00008000U
1587 #define CAN_TSR_RQCP2 0x00010000U
1588 #define CAN_TSR_TXOK2 0x00020000U
1589 #define CAN_TSR_ALST2 0x00040000U
1590 #define CAN_TSR_TERR2 0x00080000U
1591 #define CAN_TSR_ABRQ2 0x00800000U
1592 #define CAN_TSR_CODE 0x03000000U
1594 #define CAN_TSR_TME 0x1C000000U
1595 #define CAN_TSR_TME0 0x04000000U
1596 #define CAN_TSR_TME1 0x08000000U
1597 #define CAN_TSR_TME2 0x10000000U
1599 #define CAN_TSR_LOW 0xE0000000U
1600 #define CAN_TSR_LOW0 0x20000000U
1601 #define CAN_TSR_LOW1 0x40000000U
1602 #define CAN_TSR_LOW2 0x80000000U
1604 /******************* Bit definition for CAN_RF0R register *******************/
1605 #define CAN_RF0R_FMP0 0x03U
1606 #define CAN_RF0R_FULL0 0x08U
1607 #define CAN_RF0R_FOVR0 0x10U
1608 #define CAN_RF0R_RFOM0 0x20U
1610 /******************* Bit definition for CAN_RF1R register *******************/
1611 #define CAN_RF1R_FMP1 0x03U
1612 #define CAN_RF1R_FULL1 0x08U
1613 #define CAN_RF1R_FOVR1 0x10U
1614 #define CAN_RF1R_RFOM1 0x20U
1616 /******************** Bit definition for CAN_IER register *******************/
1617 #define CAN_IER_TMEIE 0x00000001U
1618 #define CAN_IER_FMPIE0 0x00000002U
1619 #define CAN_IER_FFIE0 0x00000004U
1620 #define CAN_IER_FOVIE0 0x00000008U
1621 #define CAN_IER_FMPIE1 0x00000010U
1622 #define CAN_IER_FFIE1 0x00000020U
1623 #define CAN_IER_FOVIE1 0x00000040U
1624 #define CAN_IER_EWGIE 0x00000100U
1625 #define CAN_IER_EPVIE 0x00000200U
1626 #define CAN_IER_BOFIE 0x00000400U
1627 #define CAN_IER_LECIE 0x00000800U
1628 #define CAN_IER_ERRIE 0x00008000U
1629 #define CAN_IER_WKUIE 0x00010000U
1630 #define CAN_IER_SLKIE 0x00020000U
1631 #define CAN_IER_EWGIE 0x00000100U
1632 #define CAN_IER_EPVIE 0x00000200U
1633 #define CAN_IER_BOFIE 0x00000400U
1634 #define CAN_IER_LECIE 0x00000800U
1635 #define CAN_IER_ERRIE 0x00008000U
1638 /******************** Bit definition for CAN_ESR register *******************/
1639 #define CAN_ESR_EWGF 0x00000001U
1640 #define CAN_ESR_EPVF 0x00000002U
1641 #define CAN_ESR_BOFF 0x00000004U
1643 #define CAN_ESR_LEC 0x00000070U
1644 #define CAN_ESR_LEC_0 0x00000010U
1645 #define CAN_ESR_LEC_1 0x00000020U
1646 #define CAN_ESR_LEC_2 0x00000040U
1648 #define CAN_ESR_TEC 0x00FF0000U
1649 #define CAN_ESR_REC 0xFF000000U
1651 /******************* Bit definition for CAN_BTR register ********************/
1652 #define CAN_BTR_BRP 0x000003FFU
1653 #define CAN_BTR_TS1 0x000F0000U
1654 #define CAN_BTR_TS1_0 0x00010000U
1655 #define CAN_BTR_TS1_1 0x00020000U
1656 #define CAN_BTR_TS1_2 0x00040000U
1657 #define CAN_BTR_TS1_3 0x00080000U
1658 #define CAN_BTR_TS2 0x00700000U
1659 #define CAN_BTR_TS2_0 0x00100000U
1660 #define CAN_BTR_TS2_1 0x00200000U
1661 #define CAN_BTR_TS2_2 0x00400000U
1662 #define CAN_BTR_SJW 0x03000000U
1663 #define CAN_BTR_SJW_0 0x01000000U
1664 #define CAN_BTR_SJW_1 0x02000000U
1665 #define CAN_BTR_LBKM 0x40000000U
1666 #define CAN_BTR_SILM 0x80000000U
1670 /****************** Bit definition for CAN_TI0R register ********************/
1671 #define CAN_TI0R_TXRQ 0x00000001U
1672 #define CAN_TI0R_RTR 0x00000002U
1673 #define CAN_TI0R_IDE 0x00000004U
1674 #define CAN_TI0R_EXID 0x001FFFF8U
1675 #define CAN_TI0R_STID 0xFFE00000U
1677 /****************** Bit definition for CAN_TDT0R register *******************/
1678 #define CAN_TDT0R_DLC 0x0000000FU
1679 #define CAN_TDT0R_TGT 0x00000100U
1680 #define CAN_TDT0R_TIME 0xFFFF0000U
1682 /****************** Bit definition for CAN_TDL0R register *******************/
1683 #define CAN_TDL0R_DATA0 0x000000FFU
1684 #define CAN_TDL0R_DATA1 0x0000FF00U
1685 #define CAN_TDL0R_DATA2 0x00FF0000U
1686 #define CAN_TDL0R_DATA3 0xFF000000U
1688 /****************** Bit definition for CAN_TDH0R register *******************/
1689 #define CAN_TDH0R_DATA4 0x000000FFU
1690 #define CAN_TDH0R_DATA5 0x0000FF00U
1691 #define CAN_TDH0R_DATA6 0x00FF0000U
1692 #define CAN_TDH0R_DATA7 0xFF000000U
1694 /******************* Bit definition for CAN_TI1R register *******************/
1695 #define CAN_TI1R_TXRQ 0x00000001U
1696 #define CAN_TI1R_RTR 0x00000002U
1697 #define CAN_TI1R_IDE 0x00000004U
1698 #define CAN_TI1R_EXID 0x001FFFF8U
1699 #define CAN_TI1R_STID 0xFFE00000U
1701 /******************* Bit definition for CAN_TDT1R register ******************/
1702 #define CAN_TDT1R_DLC 0x0000000FU
1703 #define CAN_TDT1R_TGT 0x00000100U
1704 #define CAN_TDT1R_TIME 0xFFFF0000U
1706 /******************* Bit definition for CAN_TDL1R register ******************/
1707 #define CAN_TDL1R_DATA0 0x000000FFU
1708 #define CAN_TDL1R_DATA1 0x0000FF00U
1709 #define CAN_TDL1R_DATA2 0x00FF0000U
1710 #define CAN_TDL1R_DATA3 0xFF000000U
1712 /******************* Bit definition for CAN_TDH1R register ******************/
1713 #define CAN_TDH1R_DATA4 0x000000FFU
1714 #define CAN_TDH1R_DATA5 0x0000FF00U
1715 #define CAN_TDH1R_DATA6 0x00FF0000U
1716 #define CAN_TDH1R_DATA7 0xFF000000U
1718 /******************* Bit definition for CAN_TI2R register *******************/
1719 #define CAN_TI2R_TXRQ 0x00000001U
1720 #define CAN_TI2R_RTR 0x00000002U
1721 #define CAN_TI2R_IDE 0x00000004U
1722 #define CAN_TI2R_EXID 0x001FFFF8U
1723 #define CAN_TI2R_STID 0xFFE00000U
1725 /******************* Bit definition for CAN_TDT2R register ******************/
1726 #define CAN_TDT2R_DLC 0x0000000FU
1727 #define CAN_TDT2R_TGT 0x00000100U
1728 #define CAN_TDT2R_TIME 0xFFFF0000U
1730 /******************* Bit definition for CAN_TDL2R register ******************/
1731 #define CAN_TDL2R_DATA0 0x000000FFU
1732 #define CAN_TDL2R_DATA1 0x0000FF00U
1733 #define CAN_TDL2R_DATA2 0x00FF0000U
1734 #define CAN_TDL2R_DATA3 0xFF000000U
1736 /******************* Bit definition for CAN_TDH2R register ******************/
1737 #define CAN_TDH2R_DATA4 0x000000FFU
1738 #define CAN_TDH2R_DATA5 0x0000FF00U
1739 #define CAN_TDH2R_DATA6 0x00FF0000U
1740 #define CAN_TDH2R_DATA7 0xFF000000U
1742 /******************* Bit definition for CAN_RI0R register *******************/
1743 #define CAN_RI0R_RTR 0x00000002U
1744 #define CAN_RI0R_IDE 0x00000004U
1745 #define CAN_RI0R_EXID 0x001FFFF8U
1746 #define CAN_RI0R_STID 0xFFE00000U
1748 /******************* Bit definition for CAN_RDT0R register ******************/
1749 #define CAN_RDT0R_DLC 0x0000000FU
1750 #define CAN_RDT0R_FMI 0x0000FF00U
1751 #define CAN_RDT0R_TIME 0xFFFF0000U
1753 /******************* Bit definition for CAN_RDL0R register ******************/
1754 #define CAN_RDL0R_DATA0 0x000000FFU
1755 #define CAN_RDL0R_DATA1 0x0000FF00U
1756 #define CAN_RDL0R_DATA2 0x00FF0000U
1757 #define CAN_RDL0R_DATA3 0xFF000000U
1759 /******************* Bit definition for CAN_RDH0R register ******************/
1760 #define CAN_RDH0R_DATA4 0x000000FFU
1761 #define CAN_RDH0R_DATA5 0x0000FF00U
1762 #define CAN_RDH0R_DATA6 0x00FF0000U
1763 #define CAN_RDH0R_DATA7 0xFF000000U
1765 /******************* Bit definition for CAN_RI1R register *******************/
1766 #define CAN_RI1R_RTR 0x00000002U
1767 #define CAN_RI1R_IDE 0x00000004U
1768 #define CAN_RI1R_EXID 0x001FFFF8U
1769 #define CAN_RI1R_STID 0xFFE00000U
1771 /******************* Bit definition for CAN_RDT1R register ******************/
1772 #define CAN_RDT1R_DLC 0x0000000FU
1773 #define CAN_RDT1R_FMI 0x0000FF00U
1774 #define CAN_RDT1R_TIME 0xFFFF0000U
1776 /******************* Bit definition for CAN_RDL1R register ******************/
1777 #define CAN_RDL1R_DATA0 0x000000FFU
1778 #define CAN_RDL1R_DATA1 0x0000FF00U
1779 #define CAN_RDL1R_DATA2 0x00FF0000U
1780 #define CAN_RDL1R_DATA3 0xFF000000U
1782 /******************* Bit definition for CAN_RDH1R register ******************/
1783 #define CAN_RDH1R_DATA4 0x000000FFU
1784 #define CAN_RDH1R_DATA5 0x0000FF00U
1785 #define CAN_RDH1R_DATA6 0x00FF0000U
1786 #define CAN_RDH1R_DATA7 0xFF000000U
1789 /******************* Bit definition for CAN_FMR register ********************/
1790 #define CAN_FMR_FINIT 0x01U
1791 #define CAN_FMR_CAN2SB 0x00003F00U
1793 /******************* Bit definition for CAN_FM1R register *******************/
1794 #define CAN_FM1R_FBM 0x0FFFFFFFU
1795 #define CAN_FM1R_FBM0 0x00000001U
1796 #define CAN_FM1R_FBM1 0x00000002U
1797 #define CAN_FM1R_FBM2 0x00000004U
1798 #define CAN_FM1R_FBM3 0x00000008U
1799 #define CAN_FM1R_FBM4 0x00000010U
1800 #define CAN_FM1R_FBM5 0x00000020U
1801 #define CAN_FM1R_FBM6 0x00000040U
1802 #define CAN_FM1R_FBM7 0x00000080U
1803 #define CAN_FM1R_FBM8 0x00000100U
1804 #define CAN_FM1R_FBM9 0x00000200U
1805 #define CAN_FM1R_FBM10 0x00000400U
1806 #define CAN_FM1R_FBM11 0x00000800U
1807 #define CAN_FM1R_FBM12 0x00001000U
1808 #define CAN_FM1R_FBM13 0x00002000U
1809 #define CAN_FM1R_FBM14 0x00004000U
1810 #define CAN_FM1R_FBM15 0x00008000U
1811 #define CAN_FM1R_FBM16 0x00010000U
1812 #define CAN_FM1R_FBM17 0x00020000U
1813 #define CAN_FM1R_FBM18 0x00040000U
1814 #define CAN_FM1R_FBM19 0x00080000U
1815 #define CAN_FM1R_FBM20 0x00100000U
1816 #define CAN_FM1R_FBM21 0x00200000U
1817 #define CAN_FM1R_FBM22 0x00400000U
1818 #define CAN_FM1R_FBM23 0x00800000U
1819 #define CAN_FM1R_FBM24 0x01000000U
1820 #define CAN_FM1R_FBM25 0x02000000U
1821 #define CAN_FM1R_FBM26 0x04000000U
1822 #define CAN_FM1R_FBM27 0x08000000U
1824 /******************* Bit definition for CAN_FS1R register *******************/
1825 #define CAN_FS1R_FSC 0x0FFFFFFFU
1826 #define CAN_FS1R_FSC0 0x00000001U
1827 #define CAN_FS1R_FSC1 0x00000002U
1828 #define CAN_FS1R_FSC2 0x00000004U
1829 #define CAN_FS1R_FSC3 0x00000008U
1830 #define CAN_FS1R_FSC4 0x00000010U
1831 #define CAN_FS1R_FSC5 0x00000020U
1832 #define CAN_FS1R_FSC6 0x00000040U
1833 #define CAN_FS1R_FSC7 0x00000080U
1834 #define CAN_FS1R_FSC8 0x00000100U
1835 #define CAN_FS1R_FSC9 0x00000200U
1836 #define CAN_FS1R_FSC10 0x00000400U
1837 #define CAN_FS1R_FSC11 0x00000800U
1838 #define CAN_FS1R_FSC12 0x00001000U
1839 #define CAN_FS1R_FSC13 0x00002000U
1840 #define CAN_FS1R_FSC14 0x00004000U
1841 #define CAN_FS1R_FSC15 0x00008000U
1842 #define CAN_FS1R_FSC16 0x00010000U
1843 #define CAN_FS1R_FSC17 0x00020000U
1844 #define CAN_FS1R_FSC18 0x00040000U
1845 #define CAN_FS1R_FSC19 0x00080000U
1846 #define CAN_FS1R_FSC20 0x00100000U
1847 #define CAN_FS1R_FSC21 0x00200000U
1848 #define CAN_FS1R_FSC22 0x00400000U
1849 #define CAN_FS1R_FSC23 0x00800000U
1850 #define CAN_FS1R_FSC24 0x01000000U
1851 #define CAN_FS1R_FSC25 0x02000000U
1852 #define CAN_FS1R_FSC26 0x04000000U
1853 #define CAN_FS1R_FSC27 0x08000000U
1855 /****************** Bit definition for CAN_FFA1R register *******************/
1856 #define CAN_FFA1R_FFA 0x0FFFFFFFU
1857 #define CAN_FFA1R_FFA0 0x00000001U
1858 #define CAN_FFA1R_FFA1 0x00000002U
1859 #define CAN_FFA1R_FFA2 0x00000004U
1860 #define CAN_FFA1R_FFA3 0x00000008U
1861 #define CAN_FFA1R_FFA4 0x00000010U
1862 #define CAN_FFA1R_FFA5 0x00000020U
1863 #define CAN_FFA1R_FFA6 0x00000040U
1864 #define CAN_FFA1R_FFA7 0x00000080U
1865 #define CAN_FFA1R_FFA8 0x00000100U
1866 #define CAN_FFA1R_FFA9 0x00000200U
1867 #define CAN_FFA1R_FFA10 0x00000400U
1868 #define CAN_FFA1R_FFA11 0x00000800U
1869 #define CAN_FFA1R_FFA12 0x00001000U
1870 #define CAN_FFA1R_FFA13 0x00002000U
1871 #define CAN_FFA1R_FFA14 0x00004000U
1872 #define CAN_FFA1R_FFA15 0x00008000U
1873 #define CAN_FFA1R_FFA16 0x00010000U
1874 #define CAN_FFA1R_FFA17 0x00020000U
1875 #define CAN_FFA1R_FFA18 0x00040000U
1876 #define CAN_FFA1R_FFA19 0x00080000U
1877 #define CAN_FFA1R_FFA20 0x00100000U
1878 #define CAN_FFA1R_FFA21 0x00200000U
1879 #define CAN_FFA1R_FFA22 0x00400000U
1880 #define CAN_FFA1R_FFA23 0x00800000U
1881 #define CAN_FFA1R_FFA24 0x01000000U
1882 #define CAN_FFA1R_FFA25 0x02000000U
1883 #define CAN_FFA1R_FFA26 0x04000000U
1884 #define CAN_FFA1R_FFA27 0x08000000U
1886 /******************* Bit definition for CAN_FA1R register *******************/
1887 #define CAN_FA1R_FACT 0x0FFFFFFFU
1888 #define CAN_FA1R_FACT0 0x00000001U
1889 #define CAN_FA1R_FACT1 0x00000002U
1890 #define CAN_FA1R_FACT2 0x00000004U
1891 #define CAN_FA1R_FACT3 0x00000008U
1892 #define CAN_FA1R_FACT4 0x00000010U
1893 #define CAN_FA1R_FACT5 0x00000020U
1894 #define CAN_FA1R_FACT6 0x00000040U
1895 #define CAN_FA1R_FACT7 0x00000080U
1896 #define CAN_FA1R_FACT8 0x00000100U
1897 #define CAN_FA1R_FACT9 0x00000200U
1898 #define CAN_FA1R_FACT10 0x00000400U
1899 #define CAN_FA1R_FACT11 0x00000800U
1900 #define CAN_FA1R_FACT12 0x00001000U
1901 #define CAN_FA1R_FACT13 0x00002000U
1902 #define CAN_FA1R_FACT14 0x00004000U
1903 #define CAN_FA1R_FACT15 0x00008000U
1904 #define CAN_FA1R_FACT16 0x00010000U
1905 #define CAN_FA1R_FACT17 0x00020000U
1906 #define CAN_FA1R_FACT18 0x00040000U
1907 #define CAN_FA1R_FACT19 0x00080000U
1908 #define CAN_FA1R_FACT20 0x00100000U
1909 #define CAN_FA1R_FACT21 0x00200000U
1910 #define CAN_FA1R_FACT22 0x00400000U
1911 #define CAN_FA1R_FACT23 0x00800000U
1912 #define CAN_FA1R_FACT24 0x01000000U
1913 #define CAN_FA1R_FACT25 0x02000000U
1914 #define CAN_FA1R_FACT26 0x04000000U
1915 #define CAN_FA1R_FACT27 0x08000000U
1917 /******************* Bit definition for CAN_F0R1 register *******************/
1918 #define CAN_F0R1_FB0 0x00000001U
1919 #define CAN_F0R1_FB1 0x00000002U
1920 #define CAN_F0R1_FB2 0x00000004U
1921 #define CAN_F0R1_FB3 0x00000008U
1922 #define CAN_F0R1_FB4 0x00000010U
1923 #define CAN_F0R1_FB5 0x00000020U
1924 #define CAN_F0R1_FB6 0x00000040U
1925 #define CAN_F0R1_FB7 0x00000080U
1926 #define CAN_F0R1_FB8 0x00000100U
1927 #define CAN_F0R1_FB9 0x00000200U
1928 #define CAN_F0R1_FB10 0x00000400U
1929 #define CAN_F0R1_FB11 0x00000800U
1930 #define CAN_F0R1_FB12 0x00001000U
1931 #define CAN_F0R1_FB13 0x00002000U
1932 #define CAN_F0R1_FB14 0x00004000U
1933 #define CAN_F0R1_FB15 0x00008000U
1934 #define CAN_F0R1_FB16 0x00010000U
1935 #define CAN_F0R1_FB17 0x00020000U
1936 #define CAN_F0R1_FB18 0x00040000U
1937 #define CAN_F0R1_FB19 0x00080000U
1938 #define CAN_F0R1_FB20 0x00100000U
1939 #define CAN_F0R1_FB21 0x00200000U
1940 #define CAN_F0R1_FB22 0x00400000U
1941 #define CAN_F0R1_FB23 0x00800000U
1942 #define CAN_F0R1_FB24 0x01000000U
1943 #define CAN_F0R1_FB25 0x02000000U
1944 #define CAN_F0R1_FB26 0x04000000U
1945 #define CAN_F0R1_FB27 0x08000000U
1946 #define CAN_F0R1_FB28 0x10000000U
1947 #define CAN_F0R1_FB29 0x20000000U
1948 #define CAN_F0R1_FB30 0x40000000U
1949 #define CAN_F0R1_FB31 0x80000000U
1951 /******************* Bit definition for CAN_F1R1 register *******************/
1952 #define CAN_F1R1_FB0 0x00000001U
1953 #define CAN_F1R1_FB1 0x00000002U
1954 #define CAN_F1R1_FB2 0x00000004U
1955 #define CAN_F1R1_FB3 0x00000008U
1956 #define CAN_F1R1_FB4 0x00000010U
1957 #define CAN_F1R1_FB5 0x00000020U
1958 #define CAN_F1R1_FB6 0x00000040U
1959 #define CAN_F1R1_FB7 0x00000080U
1960 #define CAN_F1R1_FB8 0x00000100U
1961 #define CAN_F1R1_FB9 0x00000200U
1962 #define CAN_F1R1_FB10 0x00000400U
1963 #define CAN_F1R1_FB11 0x00000800U
1964 #define CAN_F1R1_FB12 0x00001000U
1965 #define CAN_F1R1_FB13 0x00002000U
1966 #define CAN_F1R1_FB14 0x00004000U
1967 #define CAN_F1R1_FB15 0x00008000U
1968 #define CAN_F1R1_FB16 0x00010000U
1969 #define CAN_F1R1_FB17 0x00020000U
1970 #define CAN_F1R1_FB18 0x00040000U
1971 #define CAN_F1R1_FB19 0x00080000U
1972 #define CAN_F1R1_FB20 0x00100000U
1973 #define CAN_F1R1_FB21 0x00200000U
1974 #define CAN_F1R1_FB22 0x00400000U
1975 #define CAN_F1R1_FB23 0x00800000U
1976 #define CAN_F1R1_FB24 0x01000000U
1977 #define CAN_F1R1_FB25 0x02000000U
1978 #define CAN_F1R1_FB26 0x04000000U
1979 #define CAN_F1R1_FB27 0x08000000U
1980 #define CAN_F1R1_FB28 0x10000000U
1981 #define CAN_F1R1_FB29 0x20000000U
1982 #define CAN_F1R1_FB30 0x40000000U
1983 #define CAN_F1R1_FB31 0x80000000U
1985 /******************* Bit definition for CAN_F2R1 register *******************/
1986 #define CAN_F2R1_FB0 0x00000001U
1987 #define CAN_F2R1_FB1 0x00000002U
1988 #define CAN_F2R1_FB2 0x00000004U
1989 #define CAN_F2R1_FB3 0x00000008U
1990 #define CAN_F2R1_FB4 0x00000010U
1991 #define CAN_F2R1_FB5 0x00000020U
1992 #define CAN_F2R1_FB6 0x00000040U
1993 #define CAN_F2R1_FB7 0x00000080U
1994 #define CAN_F2R1_FB8 0x00000100U
1995 #define CAN_F2R1_FB9 0x00000200U
1996 #define CAN_F2R1_FB10 0x00000400U
1997 #define CAN_F2R1_FB11 0x00000800U
1998 #define CAN_F2R1_FB12 0x00001000U
1999 #define CAN_F2R1_FB13 0x00002000U
2000 #define CAN_F2R1_FB14 0x00004000U
2001 #define CAN_F2R1_FB15 0x00008000U
2002 #define CAN_F2R1_FB16 0x00010000U
2003 #define CAN_F2R1_FB17 0x00020000U
2004 #define CAN_F2R1_FB18 0x00040000U
2005 #define CAN_F2R1_FB19 0x00080000U
2006 #define CAN_F2R1_FB20 0x00100000U
2007 #define CAN_F2R1_FB21 0x00200000U
2008 #define CAN_F2R1_FB22 0x00400000U
2009 #define CAN_F2R1_FB23 0x00800000U
2010 #define CAN_F2R1_FB24 0x01000000U
2011 #define CAN_F2R1_FB25 0x02000000U
2012 #define CAN_F2R1_FB26 0x04000000U
2013 #define CAN_F2R1_FB27 0x08000000U
2014 #define CAN_F2R1_FB28 0x10000000U
2015 #define CAN_F2R1_FB29 0x20000000U
2016 #define CAN_F2R1_FB30 0x40000000U
2017 #define CAN_F2R1_FB31 0x80000000U
2019 /******************* Bit definition for CAN_F3R1 register *******************/
2020 #define CAN_F3R1_FB0 0x00000001U
2021 #define CAN_F3R1_FB1 0x00000002U
2022 #define CAN_F3R1_FB2 0x00000004U
2023 #define CAN_F3R1_FB3 0x00000008U
2024 #define CAN_F3R1_FB4 0x00000010U
2025 #define CAN_F3R1_FB5 0x00000020U
2026 #define CAN_F3R1_FB6 0x00000040U
2027 #define CAN_F3R1_FB7 0x00000080U
2028 #define CAN_F3R1_FB8 0x00000100U
2029 #define CAN_F3R1_FB9 0x00000200U
2030 #define CAN_F3R1_FB10 0x00000400U
2031 #define CAN_F3R1_FB11 0x00000800U
2032 #define CAN_F3R1_FB12 0x00001000U
2033 #define CAN_F3R1_FB13 0x00002000U
2034 #define CAN_F3R1_FB14 0x00004000U
2035 #define CAN_F3R1_FB15 0x00008000U
2036 #define CAN_F3R1_FB16 0x00010000U
2037 #define CAN_F3R1_FB17 0x00020000U
2038 #define CAN_F3R1_FB18 0x00040000U
2039 #define CAN_F3R1_FB19 0x00080000U
2040 #define CAN_F3R1_FB20 0x00100000U
2041 #define CAN_F3R1_FB21 0x00200000U
2042 #define CAN_F3R1_FB22 0x00400000U
2043 #define CAN_F3R1_FB23 0x00800000U
2044 #define CAN_F3R1_FB24 0x01000000U
2045 #define CAN_F3R1_FB25 0x02000000U
2046 #define CAN_F3R1_FB26 0x04000000U
2047 #define CAN_F3R1_FB27 0x08000000U
2048 #define CAN_F3R1_FB28 0x10000000U
2049 #define CAN_F3R1_FB29 0x20000000U
2050 #define CAN_F3R1_FB30 0x40000000U
2051 #define CAN_F3R1_FB31 0x80000000U
2053 /******************* Bit definition for CAN_F4R1 register *******************/
2054 #define CAN_F4R1_FB0 0x00000001U
2055 #define CAN_F4R1_FB1 0x00000002U
2056 #define CAN_F4R1_FB2 0x00000004U
2057 #define CAN_F4R1_FB3 0x00000008U
2058 #define CAN_F4R1_FB4 0x00000010U
2059 #define CAN_F4R1_FB5 0x00000020U
2060 #define CAN_F4R1_FB6 0x00000040U
2061 #define CAN_F4R1_FB7 0x00000080U
2062 #define CAN_F4R1_FB8 0x00000100U
2063 #define CAN_F4R1_FB9 0x00000200U
2064 #define CAN_F4R1_FB10 0x00000400U
2065 #define CAN_F4R1_FB11 0x00000800U
2066 #define CAN_F4R1_FB12 0x00001000U
2067 #define CAN_F4R1_FB13 0x00002000U
2068 #define CAN_F4R1_FB14 0x00004000U
2069 #define CAN_F4R1_FB15 0x00008000U
2070 #define CAN_F4R1_FB16 0x00010000U
2071 #define CAN_F4R1_FB17 0x00020000U
2072 #define CAN_F4R1_FB18 0x00040000U
2073 #define CAN_F4R1_FB19 0x00080000U
2074 #define CAN_F4R1_FB20 0x00100000U
2075 #define CAN_F4R1_FB21 0x00200000U
2076 #define CAN_F4R1_FB22 0x00400000U
2077 #define CAN_F4R1_FB23 0x00800000U
2078 #define CAN_F4R1_FB24 0x01000000U
2079 #define CAN_F4R1_FB25 0x02000000U
2080 #define CAN_F4R1_FB26 0x04000000U
2081 #define CAN_F4R1_FB27 0x08000000U
2082 #define CAN_F4R1_FB28 0x10000000U
2083 #define CAN_F4R1_FB29 0x20000000U
2084 #define CAN_F4R1_FB30 0x40000000U
2085 #define CAN_F4R1_FB31 0x80000000U
2087 /******************* Bit definition for CAN_F5R1 register *******************/
2088 #define CAN_F5R1_FB0 0x00000001U
2089 #define CAN_F5R1_FB1 0x00000002U
2090 #define CAN_F5R1_FB2 0x00000004U
2091 #define CAN_F5R1_FB3 0x00000008U
2092 #define CAN_F5R1_FB4 0x00000010U
2093 #define CAN_F5R1_FB5 0x00000020U
2094 #define CAN_F5R1_FB6 0x00000040U
2095 #define CAN_F5R1_FB7 0x00000080U
2096 #define CAN_F5R1_FB8 0x00000100U
2097 #define CAN_F5R1_FB9 0x00000200U
2098 #define CAN_F5R1_FB10 0x00000400U
2099 #define CAN_F5R1_FB11 0x00000800U
2100 #define CAN_F5R1_FB12 0x00001000U
2101 #define CAN_F5R1_FB13 0x00002000U
2102 #define CAN_F5R1_FB14 0x00004000U
2103 #define CAN_F5R1_FB15 0x00008000U
2104 #define CAN_F5R1_FB16 0x00010000U
2105 #define CAN_F5R1_FB17 0x00020000U
2106 #define CAN_F5R1_FB18 0x00040000U
2107 #define CAN_F5R1_FB19 0x00080000U
2108 #define CAN_F5R1_FB20 0x00100000U
2109 #define CAN_F5R1_FB21 0x00200000U
2110 #define CAN_F5R1_FB22 0x00400000U
2111 #define CAN_F5R1_FB23 0x00800000U
2112 #define CAN_F5R1_FB24 0x01000000U
2113 #define CAN_F5R1_FB25 0x02000000U
2114 #define CAN_F5R1_FB26 0x04000000U
2115 #define CAN_F5R1_FB27 0x08000000U
2116 #define CAN_F5R1_FB28 0x10000000U
2117 #define CAN_F5R1_FB29 0x20000000U
2118 #define CAN_F5R1_FB30 0x40000000U
2119 #define CAN_F5R1_FB31 0x80000000U
2121 /******************* Bit definition for CAN_F6R1 register *******************/
2122 #define CAN_F6R1_FB0 0x00000001U
2123 #define CAN_F6R1_FB1 0x00000002U
2124 #define CAN_F6R1_FB2 0x00000004U
2125 #define CAN_F6R1_FB3 0x00000008U
2126 #define CAN_F6R1_FB4 0x00000010U
2127 #define CAN_F6R1_FB5 0x00000020U
2128 #define CAN_F6R1_FB6 0x00000040U
2129 #define CAN_F6R1_FB7 0x00000080U
2130 #define CAN_F6R1_FB8 0x00000100U
2131 #define CAN_F6R1_FB9 0x00000200U
2132 #define CAN_F6R1_FB10 0x00000400U
2133 #define CAN_F6R1_FB11 0x00000800U
2134 #define CAN_F6R1_FB12 0x00001000U
2135 #define CAN_F6R1_FB13 0x00002000U
2136 #define CAN_F6R1_FB14 0x00004000U
2137 #define CAN_F6R1_FB15 0x00008000U
2138 #define CAN_F6R1_FB16 0x00010000U
2139 #define CAN_F6R1_FB17 0x00020000U
2140 #define CAN_F6R1_FB18 0x00040000U
2141 #define CAN_F6R1_FB19 0x00080000U
2142 #define CAN_F6R1_FB20 0x00100000U
2143 #define CAN_F6R1_FB21 0x00200000U
2144 #define CAN_F6R1_FB22 0x00400000U
2145 #define CAN_F6R1_FB23 0x00800000U
2146 #define CAN_F6R1_FB24 0x01000000U
2147 #define CAN_F6R1_FB25 0x02000000U
2148 #define CAN_F6R1_FB26 0x04000000U
2149 #define CAN_F6R1_FB27 0x08000000U
2150 #define CAN_F6R1_FB28 0x10000000U
2151 #define CAN_F6R1_FB29 0x20000000U
2152 #define CAN_F6R1_FB30 0x40000000U
2153 #define CAN_F6R1_FB31 0x80000000U
2155 /******************* Bit definition for CAN_F7R1 register *******************/
2156 #define CAN_F7R1_FB0 0x00000001U
2157 #define CAN_F7R1_FB1 0x00000002U
2158 #define CAN_F7R1_FB2 0x00000004U
2159 #define CAN_F7R1_FB3 0x00000008U
2160 #define CAN_F7R1_FB4 0x00000010U
2161 #define CAN_F7R1_FB5 0x00000020U
2162 #define CAN_F7R1_FB6 0x00000040U
2163 #define CAN_F7R1_FB7 0x00000080U
2164 #define CAN_F7R1_FB8 0x00000100U
2165 #define CAN_F7R1_FB9 0x00000200U
2166 #define CAN_F7R1_FB10 0x00000400U
2167 #define CAN_F7R1_FB11 0x00000800U
2168 #define CAN_F7R1_FB12 0x00001000U
2169 #define CAN_F7R1_FB13 0x00002000U
2170 #define CAN_F7R1_FB14 0x00004000U
2171 #define CAN_F7R1_FB15 0x00008000U
2172 #define CAN_F7R1_FB16 0x00010000U
2173 #define CAN_F7R1_FB17 0x00020000U
2174 #define CAN_F7R1_FB18 0x00040000U
2175 #define CAN_F7R1_FB19 0x00080000U
2176 #define CAN_F7R1_FB20 0x00100000U
2177 #define CAN_F7R1_FB21 0x00200000U
2178 #define CAN_F7R1_FB22 0x00400000U
2179 #define CAN_F7R1_FB23 0x00800000U
2180 #define CAN_F7R1_FB24 0x01000000U
2181 #define CAN_F7R1_FB25 0x02000000U
2182 #define CAN_F7R1_FB26 0x04000000U
2183 #define CAN_F7R1_FB27 0x08000000U
2184 #define CAN_F7R1_FB28 0x10000000U
2185 #define CAN_F7R1_FB29 0x20000000U
2186 #define CAN_F7R1_FB30 0x40000000U
2187 #define CAN_F7R1_FB31 0x80000000U
2189 /******************* Bit definition for CAN_F8R1 register *******************/
2190 #define CAN_F8R1_FB0 0x00000001U
2191 #define CAN_F8R1_FB1 0x00000002U
2192 #define CAN_F8R1_FB2 0x00000004U
2193 #define CAN_F8R1_FB3 0x00000008U
2194 #define CAN_F8R1_FB4 0x00000010U
2195 #define CAN_F8R1_FB5 0x00000020U
2196 #define CAN_F8R1_FB6 0x00000040U
2197 #define CAN_F8R1_FB7 0x00000080U
2198 #define CAN_F8R1_FB8 0x00000100U
2199 #define CAN_F8R1_FB9 0x00000200U
2200 #define CAN_F8R1_FB10 0x00000400U
2201 #define CAN_F8R1_FB11 0x00000800U
2202 #define CAN_F8R1_FB12 0x00001000U
2203 #define CAN_F8R1_FB13 0x00002000U
2204 #define CAN_F8R1_FB14 0x00004000U
2205 #define CAN_F8R1_FB15 0x00008000U
2206 #define CAN_F8R1_FB16 0x00010000U
2207 #define CAN_F8R1_FB17 0x00020000U
2208 #define CAN_F8R1_FB18 0x00040000U
2209 #define CAN_F8R1_FB19 0x00080000U
2210 #define CAN_F8R1_FB20 0x00100000U
2211 #define CAN_F8R1_FB21 0x00200000U
2212 #define CAN_F8R1_FB22 0x00400000U
2213 #define CAN_F8R1_FB23 0x00800000U
2214 #define CAN_F8R1_FB24 0x01000000U
2215 #define CAN_F8R1_FB25 0x02000000U
2216 #define CAN_F8R1_FB26 0x04000000U
2217 #define CAN_F8R1_FB27 0x08000000U
2218 #define CAN_F8R1_FB28 0x10000000U
2219 #define CAN_F8R1_FB29 0x20000000U
2220 #define CAN_F8R1_FB30 0x40000000U
2221 #define CAN_F8R1_FB31 0x80000000U
2223 /******************* Bit definition for CAN_F9R1 register *******************/
2224 #define CAN_F9R1_FB0 0x00000001U
2225 #define CAN_F9R1_FB1 0x00000002U
2226 #define CAN_F9R1_FB2 0x00000004U
2227 #define CAN_F9R1_FB3 0x00000008U
2228 #define CAN_F9R1_FB4 0x00000010U
2229 #define CAN_F9R1_FB5 0x00000020U
2230 #define CAN_F9R1_FB6 0x00000040U
2231 #define CAN_F9R1_FB7 0x00000080U
2232 #define CAN_F9R1_FB8 0x00000100U
2233 #define CAN_F9R1_FB9 0x00000200U
2234 #define CAN_F9R1_FB10 0x00000400U
2235 #define CAN_F9R1_FB11 0x00000800U
2236 #define CAN_F9R1_FB12 0x00001000U
2237 #define CAN_F9R1_FB13 0x00002000U
2238 #define CAN_F9R1_FB14 0x00004000U
2239 #define CAN_F9R1_FB15 0x00008000U
2240 #define CAN_F9R1_FB16 0x00010000U
2241 #define CAN_F9R1_FB17 0x00020000U
2242 #define CAN_F9R1_FB18 0x00040000U
2243 #define CAN_F9R1_FB19 0x00080000U
2244 #define CAN_F9R1_FB20 0x00100000U
2245 #define CAN_F9R1_FB21 0x00200000U
2246 #define CAN_F9R1_FB22 0x00400000U
2247 #define CAN_F9R1_FB23 0x00800000U
2248 #define CAN_F9R1_FB24 0x01000000U
2249 #define CAN_F9R1_FB25 0x02000000U
2250 #define CAN_F9R1_FB26 0x04000000U
2251 #define CAN_F9R1_FB27 0x08000000U
2252 #define CAN_F9R1_FB28 0x10000000U
2253 #define CAN_F9R1_FB29 0x20000000U
2254 #define CAN_F9R1_FB30 0x40000000U
2255 #define CAN_F9R1_FB31 0x80000000U
2257 /******************* Bit definition for CAN_F10R1 register ******************/
2258 #define CAN_F10R1_FB0 0x00000001U
2259 #define CAN_F10R1_FB1 0x00000002U
2260 #define CAN_F10R1_FB2 0x00000004U
2261 #define CAN_F10R1_FB3 0x00000008U
2262 #define CAN_F10R1_FB4 0x00000010U
2263 #define CAN_F10R1_FB5 0x00000020U
2264 #define CAN_F10R1_FB6 0x00000040U
2265 #define CAN_F10R1_FB7 0x00000080U
2266 #define CAN_F10R1_FB8 0x00000100U
2267 #define CAN_F10R1_FB9 0x00000200U
2268 #define CAN_F10R1_FB10 0x00000400U
2269 #define CAN_F10R1_FB11 0x00000800U
2270 #define CAN_F10R1_FB12 0x00001000U
2271 #define CAN_F10R1_FB13 0x00002000U
2272 #define CAN_F10R1_FB14 0x00004000U
2273 #define CAN_F10R1_FB15 0x00008000U
2274 #define CAN_F10R1_FB16 0x00010000U
2275 #define CAN_F10R1_FB17 0x00020000U
2276 #define CAN_F10R1_FB18 0x00040000U
2277 #define CAN_F10R1_FB19 0x00080000U
2278 #define CAN_F10R1_FB20 0x00100000U
2279 #define CAN_F10R1_FB21 0x00200000U
2280 #define CAN_F10R1_FB22 0x00400000U
2281 #define CAN_F10R1_FB23 0x00800000U
2282 #define CAN_F10R1_FB24 0x01000000U
2283 #define CAN_F10R1_FB25 0x02000000U
2284 #define CAN_F10R1_FB26 0x04000000U
2285 #define CAN_F10R1_FB27 0x08000000U
2286 #define CAN_F10R1_FB28 0x10000000U
2287 #define CAN_F10R1_FB29 0x20000000U
2288 #define CAN_F10R1_FB30 0x40000000U
2289 #define CAN_F10R1_FB31 0x80000000U
2291 /******************* Bit definition for CAN_F11R1 register ******************/
2292 #define CAN_F11R1_FB0 0x00000001U
2293 #define CAN_F11R1_FB1 0x00000002U
2294 #define CAN_F11R1_FB2 0x00000004U
2295 #define CAN_F11R1_FB3 0x00000008U
2296 #define CAN_F11R1_FB4 0x00000010U
2297 #define CAN_F11R1_FB5 0x00000020U
2298 #define CAN_F11R1_FB6 0x00000040U
2299 #define CAN_F11R1_FB7 0x00000080U
2300 #define CAN_F11R1_FB8 0x00000100U
2301 #define CAN_F11R1_FB9 0x00000200U
2302 #define CAN_F11R1_FB10 0x00000400U
2303 #define CAN_F11R1_FB11 0x00000800U
2304 #define CAN_F11R1_FB12 0x00001000U
2305 #define CAN_F11R1_FB13 0x00002000U
2306 #define CAN_F11R1_FB14 0x00004000U
2307 #define CAN_F11R1_FB15 0x00008000U
2308 #define CAN_F11R1_FB16 0x00010000U
2309 #define CAN_F11R1_FB17 0x00020000U
2310 #define CAN_F11R1_FB18 0x00040000U
2311 #define CAN_F11R1_FB19 0x00080000U
2312 #define CAN_F11R1_FB20 0x00100000U
2313 #define CAN_F11R1_FB21 0x00200000U
2314 #define CAN_F11R1_FB22 0x00400000U
2315 #define CAN_F11R1_FB23 0x00800000U
2316 #define CAN_F11R1_FB24 0x01000000U
2317 #define CAN_F11R1_FB25 0x02000000U
2318 #define CAN_F11R1_FB26 0x04000000U
2319 #define CAN_F11R1_FB27 0x08000000U
2320 #define CAN_F11R1_FB28 0x10000000U
2321 #define CAN_F11R1_FB29 0x20000000U
2322 #define CAN_F11R1_FB30 0x40000000U
2323 #define CAN_F11R1_FB31 0x80000000U
2325 /******************* Bit definition for CAN_F12R1 register ******************/
2326 #define CAN_F12R1_FB0 0x00000001U
2327 #define CAN_F12R1_FB1 0x00000002U
2328 #define CAN_F12R1_FB2 0x00000004U
2329 #define CAN_F12R1_FB3 0x00000008U
2330 #define CAN_F12R1_FB4 0x00000010U
2331 #define CAN_F12R1_FB5 0x00000020U
2332 #define CAN_F12R1_FB6 0x00000040U
2333 #define CAN_F12R1_FB7 0x00000080U
2334 #define CAN_F12R1_FB8 0x00000100U
2335 #define CAN_F12R1_FB9 0x00000200U
2336 #define CAN_F12R1_FB10 0x00000400U
2337 #define CAN_F12R1_FB11 0x00000800U
2338 #define CAN_F12R1_FB12 0x00001000U
2339 #define CAN_F12R1_FB13 0x00002000U
2340 #define CAN_F12R1_FB14 0x00004000U
2341 #define CAN_F12R1_FB15 0x00008000U
2342 #define CAN_F12R1_FB16 0x00010000U
2343 #define CAN_F12R1_FB17 0x00020000U
2344 #define CAN_F12R1_FB18 0x00040000U
2345 #define CAN_F12R1_FB19 0x00080000U
2346 #define CAN_F12R1_FB20 0x00100000U
2347 #define CAN_F12R1_FB21 0x00200000U
2348 #define CAN_F12R1_FB22 0x00400000U
2349 #define CAN_F12R1_FB23 0x00800000U
2350 #define CAN_F12R1_FB24 0x01000000U
2351 #define CAN_F12R1_FB25 0x02000000U
2352 #define CAN_F12R1_FB26 0x04000000U
2353 #define CAN_F12R1_FB27 0x08000000U
2354 #define CAN_F12R1_FB28 0x10000000U
2355 #define CAN_F12R1_FB29 0x20000000U
2356 #define CAN_F12R1_FB30 0x40000000U
2357 #define CAN_F12R1_FB31 0x80000000U
2359 /******************* Bit definition for CAN_F13R1 register ******************/
2360 #define CAN_F13R1_FB0 0x00000001U
2361 #define CAN_F13R1_FB1 0x00000002U
2362 #define CAN_F13R1_FB2 0x00000004U
2363 #define CAN_F13R1_FB3 0x00000008U
2364 #define CAN_F13R1_FB4 0x00000010U
2365 #define CAN_F13R1_FB5 0x00000020U
2366 #define CAN_F13R1_FB6 0x00000040U
2367 #define CAN_F13R1_FB7 0x00000080U
2368 #define CAN_F13R1_FB8 0x00000100U
2369 #define CAN_F13R1_FB9 0x00000200U
2370 #define CAN_F13R1_FB10 0x00000400U
2371 #define CAN_F13R1_FB11 0x00000800U
2372 #define CAN_F13R1_FB12 0x00001000U
2373 #define CAN_F13R1_FB13 0x00002000U
2374 #define CAN_F13R1_FB14 0x00004000U
2375 #define CAN_F13R1_FB15 0x00008000U
2376 #define CAN_F13R1_FB16 0x00010000U
2377 #define CAN_F13R1_FB17 0x00020000U
2378 #define CAN_F13R1_FB18 0x00040000U
2379 #define CAN_F13R1_FB19 0x00080000U
2380 #define CAN_F13R1_FB20 0x00100000U
2381 #define CAN_F13R1_FB21 0x00200000U
2382 #define CAN_F13R1_FB22 0x00400000U
2383 #define CAN_F13R1_FB23 0x00800000U
2384 #define CAN_F13R1_FB24 0x01000000U
2385 #define CAN_F13R1_FB25 0x02000000U
2386 #define CAN_F13R1_FB26 0x04000000U
2387 #define CAN_F13R1_FB27 0x08000000U
2388 #define CAN_F13R1_FB28 0x10000000U
2389 #define CAN_F13R1_FB29 0x20000000U
2390 #define CAN_F13R1_FB30 0x40000000U
2391 #define CAN_F13R1_FB31 0x80000000U
2393 /******************* Bit definition for CAN_F0R2 register *******************/
2394 #define CAN_F0R2_FB0 0x00000001U
2395 #define CAN_F0R2_FB1 0x00000002U
2396 #define CAN_F0R2_FB2 0x00000004U
2397 #define CAN_F0R2_FB3 0x00000008U
2398 #define CAN_F0R2_FB4 0x00000010U
2399 #define CAN_F0R2_FB5 0x00000020U
2400 #define CAN_F0R2_FB6 0x00000040U
2401 #define CAN_F0R2_FB7 0x00000080U
2402 #define CAN_F0R2_FB8 0x00000100U
2403 #define CAN_F0R2_FB9 0x00000200U
2404 #define CAN_F0R2_FB10 0x00000400U
2405 #define CAN_F0R2_FB11 0x00000800U
2406 #define CAN_F0R2_FB12 0x00001000U
2407 #define CAN_F0R2_FB13 0x00002000U
2408 #define CAN_F0R2_FB14 0x00004000U
2409 #define CAN_F0R2_FB15 0x00008000U
2410 #define CAN_F0R2_FB16 0x00010000U
2411 #define CAN_F0R2_FB17 0x00020000U
2412 #define CAN_F0R2_FB18 0x00040000U
2413 #define CAN_F0R2_FB19 0x00080000U
2414 #define CAN_F0R2_FB20 0x00100000U
2415 #define CAN_F0R2_FB21 0x00200000U
2416 #define CAN_F0R2_FB22 0x00400000U
2417 #define CAN_F0R2_FB23 0x00800000U
2418 #define CAN_F0R2_FB24 0x01000000U
2419 #define CAN_F0R2_FB25 0x02000000U
2420 #define CAN_F0R2_FB26 0x04000000U
2421 #define CAN_F0R2_FB27 0x08000000U
2422 #define CAN_F0R2_FB28 0x10000000U
2423 #define CAN_F0R2_FB29 0x20000000U
2424 #define CAN_F0R2_FB30 0x40000000U
2425 #define CAN_F0R2_FB31 0x80000000U
2427 /******************* Bit definition for CAN_F1R2 register *******************/
2428 #define CAN_F1R2_FB0 0x00000001U
2429 #define CAN_F1R2_FB1 0x00000002U
2430 #define CAN_F1R2_FB2 0x00000004U
2431 #define CAN_F1R2_FB3 0x00000008U
2432 #define CAN_F1R2_FB4 0x00000010U
2433 #define CAN_F1R2_FB5 0x00000020U
2434 #define CAN_F1R2_FB6 0x00000040U
2435 #define CAN_F1R2_FB7 0x00000080U
2436 #define CAN_F1R2_FB8 0x00000100U
2437 #define CAN_F1R2_FB9 0x00000200U
2438 #define CAN_F1R2_FB10 0x00000400U
2439 #define CAN_F1R2_FB11 0x00000800U
2440 #define CAN_F1R2_FB12 0x00001000U
2441 #define CAN_F1R2_FB13 0x00002000U
2442 #define CAN_F1R2_FB14 0x00004000U
2443 #define CAN_F1R2_FB15 0x00008000U
2444 #define CAN_F1R2_FB16 0x00010000U
2445 #define CAN_F1R2_FB17 0x00020000U
2446 #define CAN_F1R2_FB18 0x00040000U
2447 #define CAN_F1R2_FB19 0x00080000U
2448 #define CAN_F1R2_FB20 0x00100000U
2449 #define CAN_F1R2_FB21 0x00200000U
2450 #define CAN_F1R2_FB22 0x00400000U
2451 #define CAN_F1R2_FB23 0x00800000U
2452 #define CAN_F1R2_FB24 0x01000000U
2453 #define CAN_F1R2_FB25 0x02000000U
2454 #define CAN_F1R2_FB26 0x04000000U
2455 #define CAN_F1R2_FB27 0x08000000U
2456 #define CAN_F1R2_FB28 0x10000000U
2457 #define CAN_F1R2_FB29 0x20000000U
2458 #define CAN_F1R2_FB30 0x40000000U
2459 #define CAN_F1R2_FB31 0x80000000U
2461 /******************* Bit definition for CAN_F2R2 register *******************/
2462 #define CAN_F2R2_FB0 0x00000001U
2463 #define CAN_F2R2_FB1 0x00000002U
2464 #define CAN_F2R2_FB2 0x00000004U
2465 #define CAN_F2R2_FB3 0x00000008U
2466 #define CAN_F2R2_FB4 0x00000010U
2467 #define CAN_F2R2_FB5 0x00000020U
2468 #define CAN_F2R2_FB6 0x00000040U
2469 #define CAN_F2R2_FB7 0x00000080U
2470 #define CAN_F2R2_FB8 0x00000100U
2471 #define CAN_F2R2_FB9 0x00000200U
2472 #define CAN_F2R2_FB10 0x00000400U
2473 #define CAN_F2R2_FB11 0x00000800U
2474 #define CAN_F2R2_FB12 0x00001000U
2475 #define CAN_F2R2_FB13 0x00002000U
2476 #define CAN_F2R2_FB14 0x00004000U
2477 #define CAN_F2R2_FB15 0x00008000U
2478 #define CAN_F2R2_FB16 0x00010000U
2479 #define CAN_F2R2_FB17 0x00020000U
2480 #define CAN_F2R2_FB18 0x00040000U
2481 #define CAN_F2R2_FB19 0x00080000U
2482 #define CAN_F2R2_FB20 0x00100000U
2483 #define CAN_F2R2_FB21 0x00200000U
2484 #define CAN_F2R2_FB22 0x00400000U
2485 #define CAN_F2R2_FB23 0x00800000U
2486 #define CAN_F2R2_FB24 0x01000000U
2487 #define CAN_F2R2_FB25 0x02000000U
2488 #define CAN_F2R2_FB26 0x04000000U
2489 #define CAN_F2R2_FB27 0x08000000U
2490 #define CAN_F2R2_FB28 0x10000000U
2491 #define CAN_F2R2_FB29 0x20000000U
2492 #define CAN_F2R2_FB30 0x40000000U
2493 #define CAN_F2R2_FB31 0x80000000U
2495 /******************* Bit definition for CAN_F3R2 register *******************/
2496 #define CAN_F3R2_FB0 0x00000001U
2497 #define CAN_F3R2_FB1 0x00000002U
2498 #define CAN_F3R2_FB2 0x00000004U
2499 #define CAN_F3R2_FB3 0x00000008U
2500 #define CAN_F3R2_FB4 0x00000010U
2501 #define CAN_F3R2_FB5 0x00000020U
2502 #define CAN_F3R2_FB6 0x00000040U
2503 #define CAN_F3R2_FB7 0x00000080U
2504 #define CAN_F3R2_FB8 0x00000100U
2505 #define CAN_F3R2_FB9 0x00000200U
2506 #define CAN_F3R2_FB10 0x00000400U
2507 #define CAN_F3R2_FB11 0x00000800U
2508 #define CAN_F3R2_FB12 0x00001000U
2509 #define CAN_F3R2_FB13 0x00002000U
2510 #define CAN_F3R2_FB14 0x00004000U
2511 #define CAN_F3R2_FB15 0x00008000U
2512 #define CAN_F3R2_FB16 0x00010000U
2513 #define CAN_F3R2_FB17 0x00020000U
2514 #define CAN_F3R2_FB18 0x00040000U
2515 #define CAN_F3R2_FB19 0x00080000U
2516 #define CAN_F3R2_FB20 0x00100000U
2517 #define CAN_F3R2_FB21 0x00200000U
2518 #define CAN_F3R2_FB22 0x00400000U
2519 #define CAN_F3R2_FB23 0x00800000U
2520 #define CAN_F3R2_FB24 0x01000000U
2521 #define CAN_F3R2_FB25 0x02000000U
2522 #define CAN_F3R2_FB26 0x04000000U
2523 #define CAN_F3R2_FB27 0x08000000U
2524 #define CAN_F3R2_FB28 0x10000000U
2525 #define CAN_F3R2_FB29 0x20000000U
2526 #define CAN_F3R2_FB30 0x40000000U
2527 #define CAN_F3R2_FB31 0x80000000U
2529 /******************* Bit definition for CAN_F4R2 register *******************/
2530 #define CAN_F4R2_FB0 0x00000001U
2531 #define CAN_F4R2_FB1 0x00000002U
2532 #define CAN_F4R2_FB2 0x00000004U
2533 #define CAN_F4R2_FB3 0x00000008U
2534 #define CAN_F4R2_FB4 0x00000010U
2535 #define CAN_F4R2_FB5 0x00000020U
2536 #define CAN_F4R2_FB6 0x00000040U
2537 #define CAN_F4R2_FB7 0x00000080U
2538 #define CAN_F4R2_FB8 0x00000100U
2539 #define CAN_F4R2_FB9 0x00000200U
2540 #define CAN_F4R2_FB10 0x00000400U
2541 #define CAN_F4R2_FB11 0x00000800U
2542 #define CAN_F4R2_FB12 0x00001000U
2543 #define CAN_F4R2_FB13 0x00002000U
2544 #define CAN_F4R2_FB14 0x00004000U
2545 #define CAN_F4R2_FB15 0x00008000U
2546 #define CAN_F4R2_FB16 0x00010000U
2547 #define CAN_F4R2_FB17 0x00020000U
2548 #define CAN_F4R2_FB18 0x00040000U
2549 #define CAN_F4R2_FB19 0x00080000U
2550 #define CAN_F4R2_FB20 0x00100000U
2551 #define CAN_F4R2_FB21 0x00200000U
2552 #define CAN_F4R2_FB22 0x00400000U
2553 #define CAN_F4R2_FB23 0x00800000U
2554 #define CAN_F4R2_FB24 0x01000000U
2555 #define CAN_F4R2_FB25 0x02000000U
2556 #define CAN_F4R2_FB26 0x04000000U
2557 #define CAN_F4R2_FB27 0x08000000U
2558 #define CAN_F4R2_FB28 0x10000000U
2559 #define CAN_F4R2_FB29 0x20000000U
2560 #define CAN_F4R2_FB30 0x40000000U
2561 #define CAN_F4R2_FB31 0x80000000U
2563 /******************* Bit definition for CAN_F5R2 register *******************/
2564 #define CAN_F5R2_FB0 0x00000001U
2565 #define CAN_F5R2_FB1 0x00000002U
2566 #define CAN_F5R2_FB2 0x00000004U
2567 #define CAN_F5R2_FB3 0x00000008U
2568 #define CAN_F5R2_FB4 0x00000010U
2569 #define CAN_F5R2_FB5 0x00000020U
2570 #define CAN_F5R2_FB6 0x00000040U
2571 #define CAN_F5R2_FB7 0x00000080U
2572 #define CAN_F5R2_FB8 0x00000100U
2573 #define CAN_F5R2_FB9 0x00000200U
2574 #define CAN_F5R2_FB10 0x00000400U
2575 #define CAN_F5R2_FB11 0x00000800U
2576 #define CAN_F5R2_FB12 0x00001000U
2577 #define CAN_F5R2_FB13 0x00002000U
2578 #define CAN_F5R2_FB14 0x00004000U
2579 #define CAN_F5R2_FB15 0x00008000U
2580 #define CAN_F5R2_FB16 0x00010000U
2581 #define CAN_F5R2_FB17 0x00020000U
2582 #define CAN_F5R2_FB18 0x00040000U
2583 #define CAN_F5R2_FB19 0x00080000U
2584 #define CAN_F5R2_FB20 0x00100000U
2585 #define CAN_F5R2_FB21 0x00200000U
2586 #define CAN_F5R2_FB22 0x00400000U
2587 #define CAN_F5R2_FB23 0x00800000U
2588 #define CAN_F5R2_FB24 0x01000000U
2589 #define CAN_F5R2_FB25 0x02000000U
2590 #define CAN_F5R2_FB26 0x04000000U
2591 #define CAN_F5R2_FB27 0x08000000U
2592 #define CAN_F5R2_FB28 0x10000000U
2593 #define CAN_F5R2_FB29 0x20000000U
2594 #define CAN_F5R2_FB30 0x40000000U
2595 #define CAN_F5R2_FB31 0x80000000U
2597 /******************* Bit definition for CAN_F6R2 register *******************/
2598 #define CAN_F6R2_FB0 0x00000001U
2599 #define CAN_F6R2_FB1 0x00000002U
2600 #define CAN_F6R2_FB2 0x00000004U
2601 #define CAN_F6R2_FB3 0x00000008U
2602 #define CAN_F6R2_FB4 0x00000010U
2603 #define CAN_F6R2_FB5 0x00000020U
2604 #define CAN_F6R2_FB6 0x00000040U
2605 #define CAN_F6R2_FB7 0x00000080U
2606 #define CAN_F6R2_FB8 0x00000100U
2607 #define CAN_F6R2_FB9 0x00000200U
2608 #define CAN_F6R2_FB10 0x00000400U
2609 #define CAN_F6R2_FB11 0x00000800U
2610 #define CAN_F6R2_FB12 0x00001000U
2611 #define CAN_F6R2_FB13 0x00002000U
2612 #define CAN_F6R2_FB14 0x00004000U
2613 #define CAN_F6R2_FB15 0x00008000U
2614 #define CAN_F6R2_FB16 0x00010000U
2615 #define CAN_F6R2_FB17 0x00020000U
2616 #define CAN_F6R2_FB18 0x00040000U
2617 #define CAN_F6R2_FB19 0x00080000U
2618 #define CAN_F6R2_FB20 0x00100000U
2619 #define CAN_F6R2_FB21 0x00200000U
2620 #define CAN_F6R2_FB22 0x00400000U
2621 #define CAN_F6R2_FB23 0x00800000U
2622 #define CAN_F6R2_FB24 0x01000000U
2623 #define CAN_F6R2_FB25 0x02000000U
2624 #define CAN_F6R2_FB26 0x04000000U
2625 #define CAN_F6R2_FB27 0x08000000U
2626 #define CAN_F6R2_FB28 0x10000000U
2627 #define CAN_F6R2_FB29 0x20000000U
2628 #define CAN_F6R2_FB30 0x40000000U
2629 #define CAN_F6R2_FB31 0x80000000U
2631 /******************* Bit definition for CAN_F7R2 register *******************/
2632 #define CAN_F7R2_FB0 0x00000001U
2633 #define CAN_F7R2_FB1 0x00000002U
2634 #define CAN_F7R2_FB2 0x00000004U
2635 #define CAN_F7R2_FB3 0x00000008U
2636 #define CAN_F7R2_FB4 0x00000010U
2637 #define CAN_F7R2_FB5 0x00000020U
2638 #define CAN_F7R2_FB6 0x00000040U
2639 #define CAN_F7R2_FB7 0x00000080U
2640 #define CAN_F7R2_FB8 0x00000100U
2641 #define CAN_F7R2_FB9 0x00000200U
2642 #define CAN_F7R2_FB10 0x00000400U
2643 #define CAN_F7R2_FB11 0x00000800U
2644 #define CAN_F7R2_FB12 0x00001000U
2645 #define CAN_F7R2_FB13 0x00002000U
2646 #define CAN_F7R2_FB14 0x00004000U
2647 #define CAN_F7R2_FB15 0x00008000U
2648 #define CAN_F7R2_FB16 0x00010000U
2649 #define CAN_F7R2_FB17 0x00020000U
2650 #define CAN_F7R2_FB18 0x00040000U
2651 #define CAN_F7R2_FB19 0x00080000U
2652 #define CAN_F7R2_FB20 0x00100000U
2653 #define CAN_F7R2_FB21 0x00200000U
2654 #define CAN_F7R2_FB22 0x00400000U
2655 #define CAN_F7R2_FB23 0x00800000U
2656 #define CAN_F7R2_FB24 0x01000000U
2657 #define CAN_F7R2_FB25 0x02000000U
2658 #define CAN_F7R2_FB26 0x04000000U
2659 #define CAN_F7R2_FB27 0x08000000U
2660 #define CAN_F7R2_FB28 0x10000000U
2661 #define CAN_F7R2_FB29 0x20000000U
2662 #define CAN_F7R2_FB30 0x40000000U
2663 #define CAN_F7R2_FB31 0x80000000U
2665 /******************* Bit definition for CAN_F8R2 register *******************/
2666 #define CAN_F8R2_FB0 0x00000001U
2667 #define CAN_F8R2_FB1 0x00000002U
2668 #define CAN_F8R2_FB2 0x00000004U
2669 #define CAN_F8R2_FB3 0x00000008U
2670 #define CAN_F8R2_FB4 0x00000010U
2671 #define CAN_F8R2_FB5 0x00000020U
2672 #define CAN_F8R2_FB6 0x00000040U
2673 #define CAN_F8R2_FB7 0x00000080U
2674 #define CAN_F8R2_FB8 0x00000100U
2675 #define CAN_F8R2_FB9 0x00000200U
2676 #define CAN_F8R2_FB10 0x00000400U
2677 #define CAN_F8R2_FB11 0x00000800U
2678 #define CAN_F8R2_FB12 0x00001000U
2679 #define CAN_F8R2_FB13 0x00002000U
2680 #define CAN_F8R2_FB14 0x00004000U
2681 #define CAN_F8R2_FB15 0x00008000U
2682 #define CAN_F8R2_FB16 0x00010000U
2683 #define CAN_F8R2_FB17 0x00020000U
2684 #define CAN_F8R2_FB18 0x00040000U
2685 #define CAN_F8R2_FB19 0x00080000U
2686 #define CAN_F8R2_FB20 0x00100000U
2687 #define CAN_F8R2_FB21 0x00200000U
2688 #define CAN_F8R2_FB22 0x00400000U
2689 #define CAN_F8R2_FB23 0x00800000U
2690 #define CAN_F8R2_FB24 0x01000000U
2691 #define CAN_F8R2_FB25 0x02000000U
2692 #define CAN_F8R2_FB26 0x04000000U
2693 #define CAN_F8R2_FB27 0x08000000U
2694 #define CAN_F8R2_FB28 0x10000000U
2695 #define CAN_F8R2_FB29 0x20000000U
2696 #define CAN_F8R2_FB30 0x40000000U
2697 #define CAN_F8R2_FB31 0x80000000U
2699 /******************* Bit definition for CAN_F9R2 register *******************/
2700 #define CAN_F9R2_FB0 0x00000001U
2701 #define CAN_F9R2_FB1 0x00000002U
2702 #define CAN_F9R2_FB2 0x00000004U
2703 #define CAN_F9R2_FB3 0x00000008U
2704 #define CAN_F9R2_FB4 0x00000010U
2705 #define CAN_F9R2_FB5 0x00000020U
2706 #define CAN_F9R2_FB6 0x00000040U
2707 #define CAN_F9R2_FB7 0x00000080U
2708 #define CAN_F9R2_FB8 0x00000100U
2709 #define CAN_F9R2_FB9 0x00000200U
2710 #define CAN_F9R2_FB10 0x00000400U
2711 #define CAN_F9R2_FB11 0x00000800U
2712 #define CAN_F9R2_FB12 0x00001000U
2713 #define CAN_F9R2_FB13 0x00002000U
2714 #define CAN_F9R2_FB14 0x00004000U
2715 #define CAN_F9R2_FB15 0x00008000U
2716 #define CAN_F9R2_FB16 0x00010000U
2717 #define CAN_F9R2_FB17 0x00020000U
2718 #define CAN_F9R2_FB18 0x00040000U
2719 #define CAN_F9R2_FB19 0x00080000U
2720 #define CAN_F9R2_FB20 0x00100000U
2721 #define CAN_F9R2_FB21 0x00200000U
2722 #define CAN_F9R2_FB22 0x00400000U
2723 #define CAN_F9R2_FB23 0x00800000U
2724 #define CAN_F9R2_FB24 0x01000000U
2725 #define CAN_F9R2_FB25 0x02000000U
2726 #define CAN_F9R2_FB26 0x04000000U
2727 #define CAN_F9R2_FB27 0x08000000U
2728 #define CAN_F9R2_FB28 0x10000000U
2729 #define CAN_F9R2_FB29 0x20000000U
2730 #define CAN_F9R2_FB30 0x40000000U
2731 #define CAN_F9R2_FB31 0x80000000U
2733 /******************* Bit definition for CAN_F10R2 register ******************/
2734 #define CAN_F10R2_FB0 0x00000001U
2735 #define CAN_F10R2_FB1 0x00000002U
2736 #define CAN_F10R2_FB2 0x00000004U
2737 #define CAN_F10R2_FB3 0x00000008U
2738 #define CAN_F10R2_FB4 0x00000010U
2739 #define CAN_F10R2_FB5 0x00000020U
2740 #define CAN_F10R2_FB6 0x00000040U
2741 #define CAN_F10R2_FB7 0x00000080U
2742 #define CAN_F10R2_FB8 0x00000100U
2743 #define CAN_F10R2_FB9 0x00000200U
2744 #define CAN_F10R2_FB10 0x00000400U
2745 #define CAN_F10R2_FB11 0x00000800U
2746 #define CAN_F10R2_FB12 0x00001000U
2747 #define CAN_F10R2_FB13 0x00002000U
2748 #define CAN_F10R2_FB14 0x00004000U
2749 #define CAN_F10R2_FB15 0x00008000U
2750 #define CAN_F10R2_FB16 0x00010000U
2751 #define CAN_F10R2_FB17 0x00020000U
2752 #define CAN_F10R2_FB18 0x00040000U
2753 #define CAN_F10R2_FB19 0x00080000U
2754 #define CAN_F10R2_FB20 0x00100000U
2755 #define CAN_F10R2_FB21 0x00200000U
2756 #define CAN_F10R2_FB22 0x00400000U
2757 #define CAN_F10R2_FB23 0x00800000U
2758 #define CAN_F10R2_FB24 0x01000000U
2759 #define CAN_F10R2_FB25 0x02000000U
2760 #define CAN_F10R2_FB26 0x04000000U
2761 #define CAN_F10R2_FB27 0x08000000U
2762 #define CAN_F10R2_FB28 0x10000000U
2763 #define CAN_F10R2_FB29 0x20000000U
2764 #define CAN_F10R2_FB30 0x40000000U
2765 #define CAN_F10R2_FB31 0x80000000U
2767 /******************* Bit definition for CAN_F11R2 register ******************/
2768 #define CAN_F11R2_FB0 0x00000001U
2769 #define CAN_F11R2_FB1 0x00000002U
2770 #define CAN_F11R2_FB2 0x00000004U
2771 #define CAN_F11R2_FB3 0x00000008U
2772 #define CAN_F11R2_FB4 0x00000010U
2773 #define CAN_F11R2_FB5 0x00000020U
2774 #define CAN_F11R2_FB6 0x00000040U
2775 #define CAN_F11R2_FB7 0x00000080U
2776 #define CAN_F11R2_FB8 0x00000100U
2777 #define CAN_F11R2_FB9 0x00000200U
2778 #define CAN_F11R2_FB10 0x00000400U
2779 #define CAN_F11R2_FB11 0x00000800U
2780 #define CAN_F11R2_FB12 0x00001000U
2781 #define CAN_F11R2_FB13 0x00002000U
2782 #define CAN_F11R2_FB14 0x00004000U
2783 #define CAN_F11R2_FB15 0x00008000U
2784 #define CAN_F11R2_FB16 0x00010000U
2785 #define CAN_F11R2_FB17 0x00020000U
2786 #define CAN_F11R2_FB18 0x00040000U
2787 #define CAN_F11R2_FB19 0x00080000U
2788 #define CAN_F11R2_FB20 0x00100000U
2789 #define CAN_F11R2_FB21 0x00200000U
2790 #define CAN_F11R2_FB22 0x00400000U
2791 #define CAN_F11R2_FB23 0x00800000U
2792 #define CAN_F11R2_FB24 0x01000000U
2793 #define CAN_F11R2_FB25 0x02000000U
2794 #define CAN_F11R2_FB26 0x04000000U
2795 #define CAN_F11R2_FB27 0x08000000U
2796 #define CAN_F11R2_FB28 0x10000000U
2797 #define CAN_F11R2_FB29 0x20000000U
2798 #define CAN_F11R2_FB30 0x40000000U
2799 #define CAN_F11R2_FB31 0x80000000U
2801 /******************* Bit definition for CAN_F12R2 register ******************/
2802 #define CAN_F12R2_FB0 0x00000001U
2803 #define CAN_F12R2_FB1 0x00000002U
2804 #define CAN_F12R2_FB2 0x00000004U
2805 #define CAN_F12R2_FB3 0x00000008U
2806 #define CAN_F12R2_FB4 0x00000010U
2807 #define CAN_F12R2_FB5 0x00000020U
2808 #define CAN_F12R2_FB6 0x00000040U
2809 #define CAN_F12R2_FB7 0x00000080U
2810 #define CAN_F12R2_FB8 0x00000100U
2811 #define CAN_F12R2_FB9 0x00000200U
2812 #define CAN_F12R2_FB10 0x00000400U
2813 #define CAN_F12R2_FB11 0x00000800U
2814 #define CAN_F12R2_FB12 0x00001000U
2815 #define CAN_F12R2_FB13 0x00002000U
2816 #define CAN_F12R2_FB14 0x00004000U
2817 #define CAN_F12R2_FB15 0x00008000U
2818 #define CAN_F12R2_FB16 0x00010000U
2819 #define CAN_F12R2_FB17 0x00020000U
2820 #define CAN_F12R2_FB18 0x00040000U
2821 #define CAN_F12R2_FB19 0x00080000U
2822 #define CAN_F12R2_FB20 0x00100000U
2823 #define CAN_F12R2_FB21 0x00200000U
2824 #define CAN_F12R2_FB22 0x00400000U
2825 #define CAN_F12R2_FB23 0x00800000U
2826 #define CAN_F12R2_FB24 0x01000000U
2827 #define CAN_F12R2_FB25 0x02000000U
2828 #define CAN_F12R2_FB26 0x04000000U
2829 #define CAN_F12R2_FB27 0x08000000U
2830 #define CAN_F12R2_FB28 0x10000000U
2831 #define CAN_F12R2_FB29 0x20000000U
2832 #define CAN_F12R2_FB30 0x40000000U
2833 #define CAN_F12R2_FB31 0x80000000U
2835 /******************* Bit definition for CAN_F13R2 register ******************/
2836 #define CAN_F13R2_FB0 0x00000001U
2837 #define CAN_F13R2_FB1 0x00000002U
2838 #define CAN_F13R2_FB2 0x00000004U
2839 #define CAN_F13R2_FB3 0x00000008U
2840 #define CAN_F13R2_FB4 0x00000010U
2841 #define CAN_F13R2_FB5 0x00000020U
2842 #define CAN_F13R2_FB6 0x00000040U
2843 #define CAN_F13R2_FB7 0x00000080U
2844 #define CAN_F13R2_FB8 0x00000100U
2845 #define CAN_F13R2_FB9 0x00000200U
2846 #define CAN_F13R2_FB10 0x00000400U
2847 #define CAN_F13R2_FB11 0x00000800U
2848 #define CAN_F13R2_FB12 0x00001000U
2849 #define CAN_F13R2_FB13 0x00002000U
2850 #define CAN_F13R2_FB14 0x00004000U
2851 #define CAN_F13R2_FB15 0x00008000U
2852 #define CAN_F13R2_FB16 0x00010000U
2853 #define CAN_F13R2_FB17 0x00020000U
2854 #define CAN_F13R2_FB18 0x00040000U
2855 #define CAN_F13R2_FB19 0x00080000U
2856 #define CAN_F13R2_FB20 0x00100000U
2857 #define CAN_F13R2_FB21 0x00200000U
2858 #define CAN_F13R2_FB22 0x00400000U
2859 #define CAN_F13R2_FB23 0x00800000U
2860 #define CAN_F13R2_FB24 0x01000000U
2861 #define CAN_F13R2_FB25 0x02000000U
2862 #define CAN_F13R2_FB26 0x04000000U
2863 #define CAN_F13R2_FB27 0x08000000U
2864 #define CAN_F13R2_FB28 0x10000000U
2865 #define CAN_F13R2_FB29 0x20000000U
2866 #define CAN_F13R2_FB30 0x40000000U
2867 #define CAN_F13R2_FB31 0x80000000U
2869 /******************************************************************************/
2870 /* */
2871 /* CRC calculation unit */
2872 /* */
2873 /******************************************************************************/
2874 /******************* Bit definition for CRC_DR register *********************/
2875 #define CRC_DR_DR 0xFFFFFFFFU
2878 /******************* Bit definition for CRC_IDR register ********************/
2879 #define CRC_IDR_IDR 0xFFU
2882 /******************** Bit definition for CRC_CR register ********************/
2883 #define CRC_CR_RESET 0x01U
2886 /******************************************************************************/
2887 /* */
2888 /* Digital to Analog Converter */
2889 /* */
2890 /******************************************************************************/
2891 /******************** Bit definition for DAC_CR register ********************/
2892 #define DAC_CR_EN1 0x00000001U
2893 #define DAC_CR_BOFF1 0x00000002U
2894 #define DAC_CR_TEN1 0x00000004U
2896 #define DAC_CR_TSEL1 0x00000038U
2897 #define DAC_CR_TSEL1_0 0x00000008U
2898 #define DAC_CR_TSEL1_1 0x00000010U
2899 #define DAC_CR_TSEL1_2 0x00000020U
2901 #define DAC_CR_WAVE1 0x000000C0U
2902 #define DAC_CR_WAVE1_0 0x00000040U
2903 #define DAC_CR_WAVE1_1 0x00000080U
2905 #define DAC_CR_MAMP1 0x00000F00U
2906 #define DAC_CR_MAMP1_0 0x00000100U
2907 #define DAC_CR_MAMP1_1 0x00000200U
2908 #define DAC_CR_MAMP1_2 0x00000400U
2909 #define DAC_CR_MAMP1_3 0x00000800U
2911 #define DAC_CR_DMAEN1 0x00001000U
2912 #define DAC_CR_DMAUDRIE1 0x00002000U
2913 #define DAC_CR_EN2 0x00010000U
2914 #define DAC_CR_BOFF2 0x00020000U
2915 #define DAC_CR_TEN2 0x00040000U
2917 #define DAC_CR_TSEL2 0x00380000U
2918 #define DAC_CR_TSEL2_0 0x00080000U
2919 #define DAC_CR_TSEL2_1 0x00100000U
2920 #define DAC_CR_TSEL2_2 0x00200000U
2922 #define DAC_CR_WAVE2 0x00C00000U
2923 #define DAC_CR_WAVE2_0 0x00400000U
2924 #define DAC_CR_WAVE2_1 0x00800000U
2926 #define DAC_CR_MAMP2 0x0F000000U
2927 #define DAC_CR_MAMP2_0 0x01000000U
2928 #define DAC_CR_MAMP2_1 0x02000000U
2929 #define DAC_CR_MAMP2_2 0x04000000U
2930 #define DAC_CR_MAMP2_3 0x08000000U
2932 #define DAC_CR_DMAEN2 0x10000000U
2933 #define DAC_CR_DMAUDRIE2 0x20000000U
2935 /***************** Bit definition for DAC_SWTRIGR register ******************/
2936 #define DAC_SWTRIGR_SWTRIG1 0x01U
2937 #define DAC_SWTRIGR_SWTRIG2 0x02U
2939 /***************** Bit definition for DAC_DHR12R1 register ******************/
2940 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
2942 /***************** Bit definition for DAC_DHR12L1 register ******************/
2943 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
2945 /****************** Bit definition for DAC_DHR8R1 register ******************/
2946 #define DAC_DHR8R1_DACC1DHR 0xFFU
2948 /***************** Bit definition for DAC_DHR12R2 register ******************/
2949 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
2951 /***************** Bit definition for DAC_DHR12L2 register ******************/
2952 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
2954 /****************** Bit definition for DAC_DHR8R2 register ******************/
2955 #define DAC_DHR8R2_DACC2DHR 0xFFU
2957 /***************** Bit definition for DAC_DHR12RD register ******************/
2958 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
2959 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
2961 /***************** Bit definition for DAC_DHR12LD register ******************/
2962 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
2963 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
2965 /****************** Bit definition for DAC_DHR8RD register ******************/
2966 #define DAC_DHR8RD_DACC1DHR 0x00FFU
2967 #define DAC_DHR8RD_DACC2DHR 0xFF00U
2969 /******************* Bit definition for DAC_DOR1 register *******************/
2970 #define DAC_DOR1_DACC1DOR 0x0FFFU
2972 /******************* Bit definition for DAC_DOR2 register *******************/
2973 #define DAC_DOR2_DACC2DOR 0x0FFFU
2975 /******************** Bit definition for DAC_SR register ********************/
2976 #define DAC_SR_DMAUDR1 0x00002000U
2977 #define DAC_SR_DMAUDR2 0x20000000U
2979 /******************************************************************************/
2980 /* */
2981 /* Debug MCU */
2982 /* */
2983 /******************************************************************************/
2984 
2985 /******************************************************************************/
2986 /* */
2987 /* DCMI */
2988 /* */
2989 /******************************************************************************/
2990 /******************** Bits definition for DCMI_CR register ******************/
2991 #define DCMI_CR_CAPTURE 0x00000001U
2992 #define DCMI_CR_CM 0x00000002U
2993 #define DCMI_CR_CROP 0x00000004U
2994 #define DCMI_CR_JPEG 0x00000008U
2995 #define DCMI_CR_ESS 0x00000010U
2996 #define DCMI_CR_PCKPOL 0x00000020U
2997 #define DCMI_CR_HSPOL 0x00000040U
2998 #define DCMI_CR_VSPOL 0x00000080U
2999 #define DCMI_CR_FCRC_0 0x00000100U
3000 #define DCMI_CR_FCRC_1 0x00000200U
3001 #define DCMI_CR_EDM_0 0x00000400U
3002 #define DCMI_CR_EDM_1 0x00000800U
3003 #define DCMI_CR_CRE 0x00001000U
3004 #define DCMI_CR_ENABLE 0x00004000U
3005 
3006 /******************** Bits definition for DCMI_SR register ******************/
3007 #define DCMI_SR_HSYNC 0x00000001U
3008 #define DCMI_SR_VSYNC 0x00000002U
3009 #define DCMI_SR_FNE 0x00000004U
3010 
3011 /******************** Bits definition for DCMI_RIS register *****************/
3012 #define DCMI_RIS_FRAME_RIS 0x00000001U
3013 #define DCMI_RIS_OVR_RIS 0x00000002U
3014 #define DCMI_RIS_ERR_RIS 0x00000004U
3015 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3016 #define DCMI_RIS_LINE_RIS 0x00000010U
3017 /* Legacy defines */
3018 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3019 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
3020 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3021 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3022 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3023 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3024 
3025 /******************** Bits definition for DCMI_IER register *****************/
3026 #define DCMI_IER_FRAME_IE 0x00000001U
3027 #define DCMI_IER_OVR_IE 0x00000002U
3028 #define DCMI_IER_ERR_IE 0x00000004U
3029 #define DCMI_IER_VSYNC_IE 0x00000008U
3030 #define DCMI_IER_LINE_IE 0x00000010U
3031 /* Legacy defines */
3032 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3033 
3034 /******************** Bits definition for DCMI_MIS register *****************/
3035 #define DCMI_MIS_FRAME_MIS 0x00000001U
3036 #define DCMI_MIS_OVR_MIS 0x00000002U
3037 #define DCMI_MIS_ERR_MIS 0x00000004U
3038 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3039 #define DCMI_MIS_LINE_MIS 0x00000010U
3040 
3041 /* Legacy defines */
3042 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3043 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3044 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3045 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3046 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3047 
3048 /******************** Bits definition for DCMI_ICR register *****************/
3049 #define DCMI_ICR_FRAME_ISC 0x00000001U
3050 #define DCMI_ICR_OVR_ISC 0x00000002U
3051 #define DCMI_ICR_ERR_ISC 0x00000004U
3052 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3053 #define DCMI_ICR_LINE_ISC 0x00000010U
3054 
3055 /* Legacy defines */
3056 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3057 
3058 /******************** Bits definition for DCMI_ESCR register ******************/
3059 #define DCMI_ESCR_FSC 0x000000FFU
3060 #define DCMI_ESCR_LSC 0x0000FF00U
3061 #define DCMI_ESCR_LEC 0x00FF0000U
3062 #define DCMI_ESCR_FEC 0xFF000000U
3063 
3064 /******************** Bits definition for DCMI_ESUR register ******************/
3065 #define DCMI_ESUR_FSU 0x000000FFU
3066 #define DCMI_ESUR_LSU 0x0000FF00U
3067 #define DCMI_ESUR_LEU 0x00FF0000U
3068 #define DCMI_ESUR_FEU 0xFF000000U
3069 
3070 /******************** Bits definition for DCMI_CWSTRT register ******************/
3071 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3072 #define DCMI_CWSTRT_VST 0x1FFF0000U
3073 
3074 /******************** Bits definition for DCMI_CWSIZE register ******************/
3075 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3076 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3077 
3078 /******************** Bits definition for DCMI_DR register ******************/
3079 #define DCMI_DR_BYTE0 0x000000FFU
3080 #define DCMI_DR_BYTE1 0x0000FF00U
3081 #define DCMI_DR_BYTE2 0x00FF0000U
3082 #define DCMI_DR_BYTE3 0xFF000000U
3083 
3084 /******************************************************************************/
3085 /* */
3086 /* DMA Controller */
3087 /* */
3088 /******************************************************************************/
3089 /******************** Bits definition for DMA_SxCR register *****************/
3090 #define DMA_SxCR_CHSEL 0x0E000000U
3091 #define DMA_SxCR_CHSEL_0 0x02000000U
3092 #define DMA_SxCR_CHSEL_1 0x04000000U
3093 #define DMA_SxCR_CHSEL_2 0x08000000U
3094 #define DMA_SxCR_MBURST 0x01800000U
3095 #define DMA_SxCR_MBURST_0 0x00800000U
3096 #define DMA_SxCR_MBURST_1 0x01000000U
3097 #define DMA_SxCR_PBURST 0x00600000U
3098 #define DMA_SxCR_PBURST_0 0x00200000U
3099 #define DMA_SxCR_PBURST_1 0x00400000U
3100 #define DMA_SxCR_CT 0x00080000U
3101 #define DMA_SxCR_DBM 0x00040000U
3102 #define DMA_SxCR_PL 0x00030000U
3103 #define DMA_SxCR_PL_0 0x00010000U
3104 #define DMA_SxCR_PL_1 0x00020000U
3105 #define DMA_SxCR_PINCOS 0x00008000U
3106 #define DMA_SxCR_MSIZE 0x00006000U
3107 #define DMA_SxCR_MSIZE_0 0x00002000U
3108 #define DMA_SxCR_MSIZE_1 0x00004000U
3109 #define DMA_SxCR_PSIZE 0x00001800U
3110 #define DMA_SxCR_PSIZE_0 0x00000800U
3111 #define DMA_SxCR_PSIZE_1 0x00001000U
3112 #define DMA_SxCR_MINC 0x00000400U
3113 #define DMA_SxCR_PINC 0x00000200U
3114 #define DMA_SxCR_CIRC 0x00000100U
3115 #define DMA_SxCR_DIR 0x000000C0U
3116 #define DMA_SxCR_DIR_0 0x00000040U
3117 #define DMA_SxCR_DIR_1 0x00000080U
3118 #define DMA_SxCR_PFCTRL 0x00000020U
3119 #define DMA_SxCR_TCIE 0x00000010U
3120 #define DMA_SxCR_HTIE 0x00000008U
3121 #define DMA_SxCR_TEIE 0x00000004U
3122 #define DMA_SxCR_DMEIE 0x00000002U
3123 #define DMA_SxCR_EN 0x00000001U
3124 
3125 /* Legacy defines */
3126 #define DMA_SxCR_ACK 0x00100000U
3127 
3128 /******************** Bits definition for DMA_SxCNDTR register **************/
3129 #define DMA_SxNDT 0x0000FFFFU
3130 #define DMA_SxNDT_0 0x00000001U
3131 #define DMA_SxNDT_1 0x00000002U
3132 #define DMA_SxNDT_2 0x00000004U
3133 #define DMA_SxNDT_3 0x00000008U
3134 #define DMA_SxNDT_4 0x00000010U
3135 #define DMA_SxNDT_5 0x00000020U
3136 #define DMA_SxNDT_6 0x00000040U
3137 #define DMA_SxNDT_7 0x00000080U
3138 #define DMA_SxNDT_8 0x00000100U
3139 #define DMA_SxNDT_9 0x00000200U
3140 #define DMA_SxNDT_10 0x00000400U
3141 #define DMA_SxNDT_11 0x00000800U
3142 #define DMA_SxNDT_12 0x00001000U
3143 #define DMA_SxNDT_13 0x00002000U
3144 #define DMA_SxNDT_14 0x00004000U
3145 #define DMA_SxNDT_15 0x00008000U
3146 
3147 /******************** Bits definition for DMA_SxFCR register ****************/
3148 #define DMA_SxFCR_FEIE 0x00000080U
3149 #define DMA_SxFCR_FS 0x00000038U
3150 #define DMA_SxFCR_FS_0 0x00000008U
3151 #define DMA_SxFCR_FS_1 0x00000010U
3152 #define DMA_SxFCR_FS_2 0x00000020U
3153 #define DMA_SxFCR_DMDIS 0x00000004U
3154 #define DMA_SxFCR_FTH 0x00000003U
3155 #define DMA_SxFCR_FTH_0 0x00000001U
3156 #define DMA_SxFCR_FTH_1 0x00000002U
3157 
3158 /******************** Bits definition for DMA_LISR register *****************/
3159 #define DMA_LISR_TCIF3 0x08000000U
3160 #define DMA_LISR_HTIF3 0x04000000U
3161 #define DMA_LISR_TEIF3 0x02000000U
3162 #define DMA_LISR_DMEIF3 0x01000000U
3163 #define DMA_LISR_FEIF3 0x00400000U
3164 #define DMA_LISR_TCIF2 0x00200000U
3165 #define DMA_LISR_HTIF2 0x00100000U
3166 #define DMA_LISR_TEIF2 0x00080000U
3167 #define DMA_LISR_DMEIF2 0x00040000U
3168 #define DMA_LISR_FEIF2 0x00010000U
3169 #define DMA_LISR_TCIF1 0x00000800U
3170 #define DMA_LISR_HTIF1 0x00000400U
3171 #define DMA_LISR_TEIF1 0x00000200U
3172 #define DMA_LISR_DMEIF1 0x00000100U
3173 #define DMA_LISR_FEIF1 0x00000040U
3174 #define DMA_LISR_TCIF0 0x00000020U
3175 #define DMA_LISR_HTIF0 0x00000010U
3176 #define DMA_LISR_TEIF0 0x00000008U
3177 #define DMA_LISR_DMEIF0 0x00000004U
3178 #define DMA_LISR_FEIF0 0x00000001U
3179 
3180 /******************** Bits definition for DMA_HISR register *****************/
3181 #define DMA_HISR_TCIF7 0x08000000U
3182 #define DMA_HISR_HTIF7 0x04000000U
3183 #define DMA_HISR_TEIF7 0x02000000U
3184 #define DMA_HISR_DMEIF7 0x01000000U
3185 #define DMA_HISR_FEIF7 0x00400000U
3186 #define DMA_HISR_TCIF6 0x00200000U
3187 #define DMA_HISR_HTIF6 0x00100000U
3188 #define DMA_HISR_TEIF6 0x00080000U
3189 #define DMA_HISR_DMEIF6 0x00040000U
3190 #define DMA_HISR_FEIF6 0x00010000U
3191 #define DMA_HISR_TCIF5 0x00000800U
3192 #define DMA_HISR_HTIF5 0x00000400U
3193 #define DMA_HISR_TEIF5 0x00000200U
3194 #define DMA_HISR_DMEIF5 0x00000100U
3195 #define DMA_HISR_FEIF5 0x00000040U
3196 #define DMA_HISR_TCIF4 0x00000020U
3197 #define DMA_HISR_HTIF4 0x00000010U
3198 #define DMA_HISR_TEIF4 0x00000008U
3199 #define DMA_HISR_DMEIF4 0x00000004U
3200 #define DMA_HISR_FEIF4 0x00000001U
3201 
3202 /******************** Bits definition for DMA_LIFCR register ****************/
3203 #define DMA_LIFCR_CTCIF3 0x08000000U
3204 #define DMA_LIFCR_CHTIF3 0x04000000U
3205 #define DMA_LIFCR_CTEIF3 0x02000000U
3206 #define DMA_LIFCR_CDMEIF3 0x01000000U
3207 #define DMA_LIFCR_CFEIF3 0x00400000U
3208 #define DMA_LIFCR_CTCIF2 0x00200000U
3209 #define DMA_LIFCR_CHTIF2 0x00100000U
3210 #define DMA_LIFCR_CTEIF2 0x00080000U
3211 #define DMA_LIFCR_CDMEIF2 0x00040000U
3212 #define DMA_LIFCR_CFEIF2 0x00010000U
3213 #define DMA_LIFCR_CTCIF1 0x00000800U
3214 #define DMA_LIFCR_CHTIF1 0x00000400U
3215 #define DMA_LIFCR_CTEIF1 0x00000200U
3216 #define DMA_LIFCR_CDMEIF1 0x00000100U
3217 #define DMA_LIFCR_CFEIF1 0x00000040U
3218 #define DMA_LIFCR_CTCIF0 0x00000020U
3219 #define DMA_LIFCR_CHTIF0 0x00000010U
3220 #define DMA_LIFCR_CTEIF0 0x00000008U
3221 #define DMA_LIFCR_CDMEIF0 0x00000004U
3222 #define DMA_LIFCR_CFEIF0 0x00000001U
3223 
3224 /******************** Bits definition for DMA_HIFCR register ****************/
3225 #define DMA_HIFCR_CTCIF7 0x08000000U
3226 #define DMA_HIFCR_CHTIF7 0x04000000U
3227 #define DMA_HIFCR_CTEIF7 0x02000000U
3228 #define DMA_HIFCR_CDMEIF7 0x01000000U
3229 #define DMA_HIFCR_CFEIF7 0x00400000U
3230 #define DMA_HIFCR_CTCIF6 0x00200000U
3231 #define DMA_HIFCR_CHTIF6 0x00100000U
3232 #define DMA_HIFCR_CTEIF6 0x00080000U
3233 #define DMA_HIFCR_CDMEIF6 0x00040000U
3234 #define DMA_HIFCR_CFEIF6 0x00010000U
3235 #define DMA_HIFCR_CTCIF5 0x00000800U
3236 #define DMA_HIFCR_CHTIF5 0x00000400U
3237 #define DMA_HIFCR_CTEIF5 0x00000200U
3238 #define DMA_HIFCR_CDMEIF5 0x00000100U
3239 #define DMA_HIFCR_CFEIF5 0x00000040U
3240 #define DMA_HIFCR_CTCIF4 0x00000020U
3241 #define DMA_HIFCR_CHTIF4 0x00000010U
3242 #define DMA_HIFCR_CTEIF4 0x00000008U
3243 #define DMA_HIFCR_CDMEIF4 0x00000004U
3244 #define DMA_HIFCR_CFEIF4 0x00000001U
3245 
3246 
3247 /******************************************************************************/
3248 /* */
3249 /* External Interrupt/Event Controller */
3250 /* */
3251 /******************************************************************************/
3252 /******************* Bit definition for EXTI_IMR register *******************/
3253 #define EXTI_IMR_MR0 0x00000001U
3254 #define EXTI_IMR_MR1 0x00000002U
3255 #define EXTI_IMR_MR2 0x00000004U
3256 #define EXTI_IMR_MR3 0x00000008U
3257 #define EXTI_IMR_MR4 0x00000010U
3258 #define EXTI_IMR_MR5 0x00000020U
3259 #define EXTI_IMR_MR6 0x00000040U
3260 #define EXTI_IMR_MR7 0x00000080U
3261 #define EXTI_IMR_MR8 0x00000100U
3262 #define EXTI_IMR_MR9 0x00000200U
3263 #define EXTI_IMR_MR10 0x00000400U
3264 #define EXTI_IMR_MR11 0x00000800U
3265 #define EXTI_IMR_MR12 0x00001000U
3266 #define EXTI_IMR_MR13 0x00002000U
3267 #define EXTI_IMR_MR14 0x00004000U
3268 #define EXTI_IMR_MR15 0x00008000U
3269 #define EXTI_IMR_MR16 0x00010000U
3270 #define EXTI_IMR_MR17 0x00020000U
3271 #define EXTI_IMR_MR18 0x00040000U
3272 #define EXTI_IMR_MR19 0x00080000U
3273 #define EXTI_IMR_MR20 0x00100000U
3274 #define EXTI_IMR_MR21 0x00200000U
3275 #define EXTI_IMR_MR22 0x00400000U
3277 /******************* Bit definition for EXTI_EMR register *******************/
3278 #define EXTI_EMR_MR0 0x00000001U
3279 #define EXTI_EMR_MR1 0x00000002U
3280 #define EXTI_EMR_MR2 0x00000004U
3281 #define EXTI_EMR_MR3 0x00000008U
3282 #define EXTI_EMR_MR4 0x00000010U
3283 #define EXTI_EMR_MR5 0x00000020U
3284 #define EXTI_EMR_MR6 0x00000040U
3285 #define EXTI_EMR_MR7 0x00000080U
3286 #define EXTI_EMR_MR8 0x00000100U
3287 #define EXTI_EMR_MR9 0x00000200U
3288 #define EXTI_EMR_MR10 0x00000400U
3289 #define EXTI_EMR_MR11 0x00000800U
3290 #define EXTI_EMR_MR12 0x00001000U
3291 #define EXTI_EMR_MR13 0x00002000U
3292 #define EXTI_EMR_MR14 0x00004000U
3293 #define EXTI_EMR_MR15 0x00008000U
3294 #define EXTI_EMR_MR16 0x00010000U
3295 #define EXTI_EMR_MR17 0x00020000U
3296 #define EXTI_EMR_MR18 0x00040000U
3297 #define EXTI_EMR_MR19 0x00080000U
3298 #define EXTI_EMR_MR20 0x00100000U
3299 #define EXTI_EMR_MR21 0x00200000U
3300 #define EXTI_EMR_MR22 0x00400000U
3302 /****************** Bit definition for EXTI_RTSR register *******************/
3303 #define EXTI_RTSR_TR0 0x00000001U
3304 #define EXTI_RTSR_TR1 0x00000002U
3305 #define EXTI_RTSR_TR2 0x00000004U
3306 #define EXTI_RTSR_TR3 0x00000008U
3307 #define EXTI_RTSR_TR4 0x00000010U
3308 #define EXTI_RTSR_TR5 0x00000020U
3309 #define EXTI_RTSR_TR6 0x00000040U
3310 #define EXTI_RTSR_TR7 0x00000080U
3311 #define EXTI_RTSR_TR8 0x00000100U
3312 #define EXTI_RTSR_TR9 0x00000200U
3313 #define EXTI_RTSR_TR10 0x00000400U
3314 #define EXTI_RTSR_TR11 0x00000800U
3315 #define EXTI_RTSR_TR12 0x00001000U
3316 #define EXTI_RTSR_TR13 0x00002000U
3317 #define EXTI_RTSR_TR14 0x00004000U
3318 #define EXTI_RTSR_TR15 0x00008000U
3319 #define EXTI_RTSR_TR16 0x00010000U
3320 #define EXTI_RTSR_TR17 0x00020000U
3321 #define EXTI_RTSR_TR18 0x00040000U
3322 #define EXTI_RTSR_TR19 0x00080000U
3323 #define EXTI_RTSR_TR20 0x00100000U
3324 #define EXTI_RTSR_TR21 0x00200000U
3325 #define EXTI_RTSR_TR22 0x00400000U
3327 /****************** Bit definition for EXTI_FTSR register *******************/
3328 #define EXTI_FTSR_TR0 0x00000001U
3329 #define EXTI_FTSR_TR1 0x00000002U
3330 #define EXTI_FTSR_TR2 0x00000004U
3331 #define EXTI_FTSR_TR3 0x00000008U
3332 #define EXTI_FTSR_TR4 0x00000010U
3333 #define EXTI_FTSR_TR5 0x00000020U
3334 #define EXTI_FTSR_TR6 0x00000040U
3335 #define EXTI_FTSR_TR7 0x00000080U
3336 #define EXTI_FTSR_TR8 0x00000100U
3337 #define EXTI_FTSR_TR9 0x00000200U
3338 #define EXTI_FTSR_TR10 0x00000400U
3339 #define EXTI_FTSR_TR11 0x00000800U
3340 #define EXTI_FTSR_TR12 0x00001000U
3341 #define EXTI_FTSR_TR13 0x00002000U
3342 #define EXTI_FTSR_TR14 0x00004000U
3343 #define EXTI_FTSR_TR15 0x00008000U
3344 #define EXTI_FTSR_TR16 0x00010000U
3345 #define EXTI_FTSR_TR17 0x00020000U
3346 #define EXTI_FTSR_TR18 0x00040000U
3347 #define EXTI_FTSR_TR19 0x00080000U
3348 #define EXTI_FTSR_TR20 0x00100000U
3349 #define EXTI_FTSR_TR21 0x00200000U
3350 #define EXTI_FTSR_TR22 0x00400000U
3352 /****************** Bit definition for EXTI_SWIER register ******************/
3353 #define EXTI_SWIER_SWIER0 0x00000001U
3354 #define EXTI_SWIER_SWIER1 0x00000002U
3355 #define EXTI_SWIER_SWIER2 0x00000004U
3356 #define EXTI_SWIER_SWIER3 0x00000008U
3357 #define EXTI_SWIER_SWIER4 0x00000010U
3358 #define EXTI_SWIER_SWIER5 0x00000020U
3359 #define EXTI_SWIER_SWIER6 0x00000040U
3360 #define EXTI_SWIER_SWIER7 0x00000080U
3361 #define EXTI_SWIER_SWIER8 0x00000100U
3362 #define EXTI_SWIER_SWIER9 0x00000200U
3363 #define EXTI_SWIER_SWIER10 0x00000400U
3364 #define EXTI_SWIER_SWIER11 0x00000800U
3365 #define EXTI_SWIER_SWIER12 0x00001000U
3366 #define EXTI_SWIER_SWIER13 0x00002000U
3367 #define EXTI_SWIER_SWIER14 0x00004000U
3368 #define EXTI_SWIER_SWIER15 0x00008000U
3369 #define EXTI_SWIER_SWIER16 0x00010000U
3370 #define EXTI_SWIER_SWIER17 0x00020000U
3371 #define EXTI_SWIER_SWIER18 0x00040000U
3372 #define EXTI_SWIER_SWIER19 0x00080000U
3373 #define EXTI_SWIER_SWIER20 0x00100000U
3374 #define EXTI_SWIER_SWIER21 0x00200000U
3375 #define EXTI_SWIER_SWIER22 0x00400000U
3377 /******************* Bit definition for EXTI_PR register ********************/
3378 #define EXTI_PR_PR0 0x00000001U
3379 #define EXTI_PR_PR1 0x00000002U
3380 #define EXTI_PR_PR2 0x00000004U
3381 #define EXTI_PR_PR3 0x00000008U
3382 #define EXTI_PR_PR4 0x00000010U
3383 #define EXTI_PR_PR5 0x00000020U
3384 #define EXTI_PR_PR6 0x00000040U
3385 #define EXTI_PR_PR7 0x00000080U
3386 #define EXTI_PR_PR8 0x00000100U
3387 #define EXTI_PR_PR9 0x00000200U
3388 #define EXTI_PR_PR10 0x00000400U
3389 #define EXTI_PR_PR11 0x00000800U
3390 #define EXTI_PR_PR12 0x00001000U
3391 #define EXTI_PR_PR13 0x00002000U
3392 #define EXTI_PR_PR14 0x00004000U
3393 #define EXTI_PR_PR15 0x00008000U
3394 #define EXTI_PR_PR16 0x00010000U
3395 #define EXTI_PR_PR17 0x00020000U
3396 #define EXTI_PR_PR18 0x00040000U
3397 #define EXTI_PR_PR19 0x00080000U
3398 #define EXTI_PR_PR20 0x00100000U
3399 #define EXTI_PR_PR21 0x00200000U
3400 #define EXTI_PR_PR22 0x00400000U
3402 /******************************************************************************/
3403 /* */
3404 /* FLASH */
3405 /* */
3406 /******************************************************************************/
3407 /******************* Bits definition for FLASH_ACR register *****************/
3408 #define FLASH_ACR_LATENCY 0x0000000FU
3409 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3410 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3411 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3412 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3413 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3414 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3415 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3416 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3417 
3418 #define FLASH_ACR_PRFTEN 0x00000100U
3419 #define FLASH_ACR_ICEN 0x00000200U
3420 #define FLASH_ACR_DCEN 0x00000400U
3421 #define FLASH_ACR_ICRST 0x00000800U
3422 #define FLASH_ACR_DCRST 0x00001000U
3423 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3424 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3425 
3426 /******************* Bits definition for FLASH_SR register ******************/
3427 #define FLASH_SR_EOP 0x00000001U
3428 #define FLASH_SR_SOP 0x00000002U
3429 #define FLASH_SR_WRPERR 0x00000010U
3430 #define FLASH_SR_PGAERR 0x00000020U
3431 #define FLASH_SR_PGPERR 0x00000040U
3432 #define FLASH_SR_PGSERR 0x00000080U
3433 #define FLASH_SR_BSY 0x00010000U
3434 
3435 /******************* Bits definition for FLASH_CR register ******************/
3436 #define FLASH_CR_PG 0x00000001U
3437 #define FLASH_CR_SER 0x00000002U
3438 #define FLASH_CR_MER 0x00000004U
3439 #define FLASH_CR_SNB 0x000000F8U
3440 #define FLASH_CR_SNB_0 0x00000008U
3441 #define FLASH_CR_SNB_1 0x00000010U
3442 #define FLASH_CR_SNB_2 0x00000020U
3443 #define FLASH_CR_SNB_3 0x00000040U
3444 #define FLASH_CR_SNB_4 0x00000080U
3445 #define FLASH_CR_PSIZE 0x00000300U
3446 #define FLASH_CR_PSIZE_0 0x00000100U
3447 #define FLASH_CR_PSIZE_1 0x00000200U
3448 #define FLASH_CR_STRT 0x00010000U
3449 #define FLASH_CR_EOPIE 0x01000000U
3450 #define FLASH_CR_LOCK 0x80000000U
3451 
3452 /******************* Bits definition for FLASH_OPTCR register ***************/
3453 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3454 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3455 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3456 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3457 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3458 
3459 #define FLASH_OPTCR_WDG_SW 0x00000020U
3460 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3461 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3462 #define FLASH_OPTCR_RDP 0x0000FF00U
3463 #define FLASH_OPTCR_RDP_0 0x00000100U
3464 #define FLASH_OPTCR_RDP_1 0x00000200U
3465 #define FLASH_OPTCR_RDP_2 0x00000400U
3466 #define FLASH_OPTCR_RDP_3 0x00000800U
3467 #define FLASH_OPTCR_RDP_4 0x00001000U
3468 #define FLASH_OPTCR_RDP_5 0x00002000U
3469 #define FLASH_OPTCR_RDP_6 0x00004000U
3470 #define FLASH_OPTCR_RDP_7 0x00008000U
3471 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3472 #define FLASH_OPTCR_nWRP_0 0x00010000U
3473 #define FLASH_OPTCR_nWRP_1 0x00020000U
3474 #define FLASH_OPTCR_nWRP_2 0x00040000U
3475 #define FLASH_OPTCR_nWRP_3 0x00080000U
3476 #define FLASH_OPTCR_nWRP_4 0x00100000U
3477 #define FLASH_OPTCR_nWRP_5 0x00200000U
3478 #define FLASH_OPTCR_nWRP_6 0x00400000U
3479 #define FLASH_OPTCR_nWRP_7 0x00800000U
3480 #define FLASH_OPTCR_nWRP_8 0x01000000U
3481 #define FLASH_OPTCR_nWRP_9 0x02000000U
3482 #define FLASH_OPTCR_nWRP_10 0x04000000U
3483 #define FLASH_OPTCR_nWRP_11 0x08000000U
3484 
3485 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3486 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3487 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3488 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3489 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3490 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3491 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3492 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3493 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3494 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3495 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3496 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3497 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3498 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3499 
3500 /******************************************************************************/
3501 /* */
3502 /* Flexible Static Memory Controller */
3503 /* */
3504 /******************************************************************************/
3505 /****************** Bit definition for FSMC_BCR1 register *******************/
3506 #define FSMC_BCR1_MBKEN 0x00000001U
3507 #define FSMC_BCR1_MUXEN 0x00000002U
3509 #define FSMC_BCR1_MTYP 0x0000000CU
3510 #define FSMC_BCR1_MTYP_0 0x00000004U
3511 #define FSMC_BCR1_MTYP_1 0x00000008U
3513 #define FSMC_BCR1_MWID 0x00000030U
3514 #define FSMC_BCR1_MWID_0 0x00000010U
3515 #define FSMC_BCR1_MWID_1 0x00000020U
3517 #define FSMC_BCR1_FACCEN 0x00000040U
3518 #define FSMC_BCR1_BURSTEN 0x00000100U
3519 #define FSMC_BCR1_WAITPOL 0x00000200U
3520 #define FSMC_BCR1_WRAPMOD 0x00000400U
3521 #define FSMC_BCR1_WAITCFG 0x00000800U
3522 #define FSMC_BCR1_WREN 0x00001000U
3523 #define FSMC_BCR1_WAITEN 0x00002000U
3524 #define FSMC_BCR1_EXTMOD 0x00004000U
3525 #define FSMC_BCR1_ASYNCWAIT 0x00008000U
3526 #define FSMC_BCR1_CPSIZE 0x00070000U
3527 #define FSMC_BCR1_CPSIZE_0 0x00010000U
3528 #define FSMC_BCR1_CPSIZE_1 0x00020000U
3529 #define FSMC_BCR1_CPSIZE_2 0x00040000U
3530 #define FSMC_BCR1_CBURSTRW 0x00080000U
3532 /****************** Bit definition for FSMC_BCR2 register *******************/
3533 #define FSMC_BCR2_MBKEN 0x00000001U
3534 #define FSMC_BCR2_MUXEN 0x00000002U
3536 #define FSMC_BCR2_MTYP 0x0000000CU
3537 #define FSMC_BCR2_MTYP_0 0x00000004U
3538 #define FSMC_BCR2_MTYP_1 0x00000008U
3540 #define FSMC_BCR2_MWID 0x00000030U
3541 #define FSMC_BCR2_MWID_0 0x00000010U
3542 #define FSMC_BCR2_MWID_1 0x00000020U
3544 #define FSMC_BCR2_FACCEN 0x00000040U
3545 #define FSMC_BCR2_BURSTEN 0x00000100U
3546 #define FSMC_BCR2_WAITPOL 0x00000200U
3547 #define FSMC_BCR2_WRAPMOD 0x00000400U
3548 #define FSMC_BCR2_WAITCFG 0x00000800U
3549 #define FSMC_BCR2_WREN 0x00001000U
3550 #define FSMC_BCR2_WAITEN 0x00002000U
3551 #define FSMC_BCR2_EXTMOD 0x00004000U
3552 #define FSMC_BCR2_ASYNCWAIT 0x00008000U
3553 #define FSMC_BCR2_CPSIZE 0x00070000U
3554 #define FSMC_BCR2_CPSIZE_0 0x00010000U
3555 #define FSMC_BCR2_CPSIZE_1 0x00020000U
3556 #define FSMC_BCR2_CPSIZE_2 0x00040000U
3557 #define FSMC_BCR2_CBURSTRW 0x00080000U
3559 /****************** Bit definition for FSMC_BCR3 register *******************/
3560 #define FSMC_BCR3_MBKEN 0x00000001U
3561 #define FSMC_BCR3_MUXEN 0x00000002U
3563 #define FSMC_BCR3_MTYP 0x0000000CU
3564 #define FSMC_BCR3_MTYP_0 0x00000004U
3565 #define FSMC_BCR3_MTYP_1 0x00000008U
3567 #define FSMC_BCR3_MWID 0x00000030U
3568 #define FSMC_BCR3_MWID_0 0x00000010U
3569 #define FSMC_BCR3_MWID_1 0x00000020U
3571 #define FSMC_BCR3_FACCEN 0x00000040U
3572 #define FSMC_BCR3_BURSTEN 0x00000100U
3573 #define FSMC_BCR3_WAITPOL 0x00000200U
3574 #define FSMC_BCR3_WRAPMOD 0x00000400U
3575 #define FSMC_BCR3_WAITCFG 0x00000800U
3576 #define FSMC_BCR3_WREN 0x00001000U
3577 #define FSMC_BCR3_WAITEN 0x00002000U
3578 #define FSMC_BCR3_EXTMOD 0x00004000U
3579 #define FSMC_BCR3_ASYNCWAIT 0x00008000U
3580 #define FSMC_BCR3_CPSIZE 0x00070000U
3581 #define FSMC_BCR3_CPSIZE_0 0x00010000U
3582 #define FSMC_BCR3_CPSIZE_1 0x00020000U
3583 #define FSMC_BCR3_CPSIZE_2 0x00040000U
3584 #define FSMC_BCR3_CBURSTRW 0x00080000U
3586 /****************** Bit definition for FSMC_BCR4 register *******************/
3587 #define FSMC_BCR4_MBKEN 0x00000001U
3588 #define FSMC_BCR4_MUXEN 0x00000002U
3590 #define FSMC_BCR4_MTYP 0x0000000CU
3591 #define FSMC_BCR4_MTYP_0 0x00000004U
3592 #define FSMC_BCR4_MTYP_1 0x00000008U
3594 #define FSMC_BCR4_MWID 0x00000030U
3595 #define FSMC_BCR4_MWID_0 0x00000010U
3596 #define FSMC_BCR4_MWID_1 0x00000020U
3598 #define FSMC_BCR4_FACCEN 0x00000040U
3599 #define FSMC_BCR4_BURSTEN 0x00000100U
3600 #define FSMC_BCR4_WAITPOL 0x00000200U
3601 #define FSMC_BCR4_WRAPMOD 0x00000400U
3602 #define FSMC_BCR4_WAITCFG 0x00000800U
3603 #define FSMC_BCR4_WREN 0x00001000U
3604 #define FSMC_BCR4_WAITEN 0x00002000U
3605 #define FSMC_BCR4_EXTMOD 0x00004000U
3606 #define FSMC_BCR4_ASYNCWAIT 0x00008000U
3607 #define FSMC_BCR4_CPSIZE 0x00070000U
3608 #define FSMC_BCR4_CPSIZE_0 0x00010000U
3609 #define FSMC_BCR4_CPSIZE_1 0x00020000U
3610 #define FSMC_BCR4_CPSIZE_2 0x00040000U
3611 #define FSMC_BCR4_CBURSTRW 0x00080000U
3613 /****************** Bit definition for FSMC_BTR1 register ******************/
3614 #define FSMC_BTR1_ADDSET 0x0000000FU
3615 #define FSMC_BTR1_ADDSET_0 0x00000001U
3616 #define FSMC_BTR1_ADDSET_1 0x00000002U
3617 #define FSMC_BTR1_ADDSET_2 0x00000004U
3618 #define FSMC_BTR1_ADDSET_3 0x00000008U
3620 #define FSMC_BTR1_ADDHLD 0x000000F0U
3621 #define FSMC_BTR1_ADDHLD_0 0x00000010U
3622 #define FSMC_BTR1_ADDHLD_1 0x00000020U
3623 #define FSMC_BTR1_ADDHLD_2 0x00000040U
3624 #define FSMC_BTR1_ADDHLD_3 0x00000080U
3626 #define FSMC_BTR1_DATAST 0x0000FF00U
3627 #define FSMC_BTR1_DATAST_0 0x00000100U
3628 #define FSMC_BTR1_DATAST_1 0x00000200U
3629 #define FSMC_BTR1_DATAST_2 0x00000400U
3630 #define FSMC_BTR1_DATAST_3 0x00000800U
3631 #define FSMC_BTR1_DATAST_4 0x00001000U
3632 #define FSMC_BTR1_DATAST_5 0x00002000U
3633 #define FSMC_BTR1_DATAST_6 0x00004000U
3634 #define FSMC_BTR1_DATAST_7 0x00008000U
3636 #define FSMC_BTR1_BUSTURN 0x000F0000U
3637 #define FSMC_BTR1_BUSTURN_0 0x00010000U
3638 #define FSMC_BTR1_BUSTURN_1 0x00020000U
3639 #define FSMC_BTR1_BUSTURN_2 0x00040000U
3640 #define FSMC_BTR1_BUSTURN_3 0x00080000U
3642 #define FSMC_BTR1_CLKDIV 0x00F00000U
3643 #define FSMC_BTR1_CLKDIV_0 0x00100000U
3644 #define FSMC_BTR1_CLKDIV_1 0x00200000U
3645 #define FSMC_BTR1_CLKDIV_2 0x00400000U
3646 #define FSMC_BTR1_CLKDIV_3 0x00800000U
3648 #define FSMC_BTR1_DATLAT 0x0F000000U
3649 #define FSMC_BTR1_DATLAT_0 0x01000000U
3650 #define FSMC_BTR1_DATLAT_1 0x02000000U
3651 #define FSMC_BTR1_DATLAT_2 0x04000000U
3652 #define FSMC_BTR1_DATLAT_3 0x08000000U
3654 #define FSMC_BTR1_ACCMOD 0x30000000U
3655 #define FSMC_BTR1_ACCMOD_0 0x10000000U
3656 #define FSMC_BTR1_ACCMOD_1 0x20000000U
3658 /****************** Bit definition for FSMC_BTR2 register *******************/
3659 #define FSMC_BTR2_ADDSET 0x0000000FU
3660 #define FSMC_BTR2_ADDSET_0 0x00000001U
3661 #define FSMC_BTR2_ADDSET_1 0x00000002U
3662 #define FSMC_BTR2_ADDSET_2 0x00000004U
3663 #define FSMC_BTR2_ADDSET_3 0x00000008U
3665 #define FSMC_BTR2_ADDHLD 0x000000F0U
3666 #define FSMC_BTR2_ADDHLD_0 0x00000010U
3667 #define FSMC_BTR2_ADDHLD_1 0x00000020U
3668 #define FSMC_BTR2_ADDHLD_2 0x00000040U
3669 #define FSMC_BTR2_ADDHLD_3 0x00000080U
3671 #define FSMC_BTR2_DATAST 0x0000FF00U
3672 #define FSMC_BTR2_DATAST_0 0x00000100U
3673 #define FSMC_BTR2_DATAST_1 0x00000200U
3674 #define FSMC_BTR2_DATAST_2 0x00000400U
3675 #define FSMC_BTR2_DATAST_3 0x00000800U
3676 #define FSMC_BTR2_DATAST_4 0x00001000U
3677 #define FSMC_BTR2_DATAST_5 0x00002000U
3678 #define FSMC_BTR2_DATAST_6 0x00004000U
3679 #define FSMC_BTR2_DATAST_7 0x00008000U
3681 #define FSMC_BTR2_BUSTURN 0x000F0000U
3682 #define FSMC_BTR2_BUSTURN_0 0x00010000U
3683 #define FSMC_BTR2_BUSTURN_1 0x00020000U
3684 #define FSMC_BTR2_BUSTURN_2 0x00040000U
3685 #define FSMC_BTR2_BUSTURN_3 0x00080000U
3687 #define FSMC_BTR2_CLKDIV 0x00F00000U
3688 #define FSMC_BTR2_CLKDIV_0 0x00100000U
3689 #define FSMC_BTR2_CLKDIV_1 0x00200000U
3690 #define FSMC_BTR2_CLKDIV_2 0x00400000U
3691 #define FSMC_BTR2_CLKDIV_3 0x00800000U
3693 #define FSMC_BTR2_DATLAT 0x0F000000U
3694 #define FSMC_BTR2_DATLAT_0 0x01000000U
3695 #define FSMC_BTR2_DATLAT_1 0x02000000U
3696 #define FSMC_BTR2_DATLAT_2 0x04000000U
3697 #define FSMC_BTR2_DATLAT_3 0x08000000U
3699 #define FSMC_BTR2_ACCMOD 0x30000000U
3700 #define FSMC_BTR2_ACCMOD_0 0x10000000U
3701 #define FSMC_BTR2_ACCMOD_1 0x20000000U
3703 /******************* Bit definition for FSMC_BTR3 register *******************/
3704 #define FSMC_BTR3_ADDSET 0x0000000FU
3705 #define FSMC_BTR3_ADDSET_0 0x00000001U
3706 #define FSMC_BTR3_ADDSET_1 0x00000002U
3707 #define FSMC_BTR3_ADDSET_2 0x00000004U
3708 #define FSMC_BTR3_ADDSET_3 0x00000008U
3710 #define FSMC_BTR3_ADDHLD 0x000000F0U
3711 #define FSMC_BTR3_ADDHLD_0 0x00000010U
3712 #define FSMC_BTR3_ADDHLD_1 0x00000020U
3713 #define FSMC_BTR3_ADDHLD_2 0x00000040U
3714 #define FSMC_BTR3_ADDHLD_3 0x00000080U
3716 #define FSMC_BTR3_DATAST 0x0000FF00U
3717 #define FSMC_BTR3_DATAST_0 0x00000100U
3718 #define FSMC_BTR3_DATAST_1 0x00000200U
3719 #define FSMC_BTR3_DATAST_2 0x00000400U
3720 #define FSMC_BTR3_DATAST_3 0x00000800U
3721 #define FSMC_BTR3_DATAST_4 0x00001000U
3722 #define FSMC_BTR3_DATAST_5 0x00002000U
3723 #define FSMC_BTR3_DATAST_6 0x00004000U
3724 #define FSMC_BTR3_DATAST_7 0x00008000U
3726 #define FSMC_BTR3_BUSTURN 0x000F0000U
3727 #define FSMC_BTR3_BUSTURN_0 0x00010000U
3728 #define FSMC_BTR3_BUSTURN_1 0x00020000U
3729 #define FSMC_BTR3_BUSTURN_2 0x00040000U
3730 #define FSMC_BTR3_BUSTURN_3 0x00080000U
3732 #define FSMC_BTR3_CLKDIV 0x00F00000U
3733 #define FSMC_BTR3_CLKDIV_0 0x00100000U
3734 #define FSMC_BTR3_CLKDIV_1 0x00200000U
3735 #define FSMC_BTR3_CLKDIV_2 0x00400000U
3736 #define FSMC_BTR3_CLKDIV_3 0x00800000U
3738 #define FSMC_BTR3_DATLAT 0x0F000000U
3739 #define FSMC_BTR3_DATLAT_0 0x01000000U
3740 #define FSMC_BTR3_DATLAT_1 0x02000000U
3741 #define FSMC_BTR3_DATLAT_2 0x04000000U
3742 #define FSMC_BTR3_DATLAT_3 0x08000000U
3744 #define FSMC_BTR3_ACCMOD 0x30000000U
3745 #define FSMC_BTR3_ACCMOD_0 0x10000000U
3746 #define FSMC_BTR3_ACCMOD_1 0x20000000U
3748 /****************** Bit definition for FSMC_BTR4 register *******************/
3749 #define FSMC_BTR4_ADDSET 0x0000000FU
3750 #define FSMC_BTR4_ADDSET_0 0x00000001U
3751 #define FSMC_BTR4_ADDSET_1 0x00000002U
3752 #define FSMC_BTR4_ADDSET_2 0x00000004U
3753 #define FSMC_BTR4_ADDSET_3 0x00000008U
3755 #define FSMC_BTR4_ADDHLD 0x000000F0U
3756 #define FSMC_BTR4_ADDHLD_0 0x00000010U
3757 #define FSMC_BTR4_ADDHLD_1 0x00000020U
3758 #define FSMC_BTR4_ADDHLD_2 0x00000040U
3759 #define FSMC_BTR4_ADDHLD_3 0x00000080U
3761 #define FSMC_BTR4_DATAST 0x0000FF00U
3762 #define FSMC_BTR4_DATAST_0 0x00000100U
3763 #define FSMC_BTR4_DATAST_1 0x00000200U
3764 #define FSMC_BTR4_DATAST_2 0x00000400U
3765 #define FSMC_BTR4_DATAST_3 0x00000800U
3766 #define FSMC_BTR4_DATAST_4 0x00001000U
3767 #define FSMC_BTR4_DATAST_5 0x00002000U
3768 #define FSMC_BTR4_DATAST_6 0x00004000U
3769 #define FSMC_BTR4_DATAST_7 0x00008000U
3771 #define FSMC_BTR4_BUSTURN 0x000F0000U
3772 #define FSMC_BTR4_BUSTURN_0 0x00010000U
3773 #define FSMC_BTR4_BUSTURN_1 0x00020000U
3774 #define FSMC_BTR4_BUSTURN_2 0x00040000U
3775 #define FSMC_BTR4_BUSTURN_3 0x00080000U
3777 #define FSMC_BTR4_CLKDIV 0x00F00000U
3778 #define FSMC_BTR4_CLKDIV_0 0x00100000U
3779 #define FSMC_BTR4_CLKDIV_1 0x00200000U
3780 #define FSMC_BTR4_CLKDIV_2 0x00400000U
3781 #define FSMC_BTR4_CLKDIV_3 0x00800000U
3783 #define FSMC_BTR4_DATLAT 0x0F000000U
3784 #define FSMC_BTR4_DATLAT_0 0x01000000U
3785 #define FSMC_BTR4_DATLAT_1 0x02000000U
3786 #define FSMC_BTR4_DATLAT_2 0x04000000U
3787 #define FSMC_BTR4_DATLAT_3 0x08000000U
3789 #define FSMC_BTR4_ACCMOD 0x30000000U
3790 #define FSMC_BTR4_ACCMOD_0 0x10000000U
3791 #define FSMC_BTR4_ACCMOD_1 0x20000000U
3793 /****************** Bit definition for FSMC_BWTR1 register ******************/
3794 #define FSMC_BWTR1_ADDSET 0x0000000FU
3795 #define FSMC_BWTR1_ADDSET_0 0x00000001U
3796 #define FSMC_BWTR1_ADDSET_1 0x00000002U
3797 #define FSMC_BWTR1_ADDSET_2 0x00000004U
3798 #define FSMC_BWTR1_ADDSET_3 0x00000008U
3800 #define FSMC_BWTR1_ADDHLD 0x000000F0U
3801 #define FSMC_BWTR1_ADDHLD_0 0x00000010U
3802 #define FSMC_BWTR1_ADDHLD_1 0x00000020U
3803 #define FSMC_BWTR1_ADDHLD_2 0x00000040U
3804 #define FSMC_BWTR1_ADDHLD_3 0x00000080U
3806 #define FSMC_BWTR1_DATAST 0x0000FF00U
3807 #define FSMC_BWTR1_DATAST_0 0x00000100U
3808 #define FSMC_BWTR1_DATAST_1 0x00000200U
3809 #define FSMC_BWTR1_DATAST_2 0x00000400U
3810 #define FSMC_BWTR1_DATAST_3 0x00000800U
3811 #define FSMC_BWTR1_DATAST_4 0x00001000U
3812 #define FSMC_BWTR1_DATAST_5 0x00002000U
3813 #define FSMC_BWTR1_DATAST_6 0x00004000U
3814 #define FSMC_BWTR1_DATAST_7 0x00008000U
3816 #define FSMC_BWTR1_BUSTURN 0x000F0000U
3817 #define FSMC_BWTR1_BUSTURN_0 0x00010000U
3818 #define FSMC_BWTR1_BUSTURN_1 0x00020000U
3819 #define FSMC_BWTR1_BUSTURN_2 0x00040000U
3820 #define FSMC_BWTR1_BUSTURN_3 0x00080000U
3822 #define FSMC_BWTR1_ACCMOD 0x30000000U
3823 #define FSMC_BWTR1_ACCMOD_0 0x10000000U
3824 #define FSMC_BWTR1_ACCMOD_1 0x20000000U
3826 /****************** Bit definition for FSMC_BWTR2 register ******************/
3827 #define FSMC_BWTR2_ADDSET 0x0000000FU
3828 #define FSMC_BWTR2_ADDSET_0 0x00000001U
3829 #define FSMC_BWTR2_ADDSET_1 0x00000002U
3830 #define FSMC_BWTR2_ADDSET_2 0x00000004U
3831 #define FSMC_BWTR2_ADDSET_3 0x00000008U
3833 #define FSMC_BWTR2_ADDHLD 0x000000F0U
3834 #define FSMC_BWTR2_ADDHLD_0 0x00000010U
3835 #define FSMC_BWTR2_ADDHLD_1 0x00000020U
3836 #define FSMC_BWTR2_ADDHLD_2 0x00000040U
3837 #define FSMC_BWTR2_ADDHLD_3 0x00000080U
3839 #define FSMC_BWTR2_DATAST 0x0000FF00U
3840 #define FSMC_BWTR2_DATAST_0 0x00000100U
3841 #define FSMC_BWTR2_DATAST_1 0x00000200U
3842 #define FSMC_BWTR2_DATAST_2 0x00000400U
3843 #define FSMC_BWTR2_DATAST_3 0x00000800U
3844 #define FSMC_BWTR2_DATAST_4 0x00001000U
3845 #define FSMC_BWTR2_DATAST_5 0x00002000U
3846 #define FSMC_BWTR2_DATAST_6 0x00004000U
3847 #define FSMC_BWTR2_DATAST_7 0x00008000U
3849 #define FSMC_BWTR2_BUSTURN 0x000F0000U
3850 #define FSMC_BWTR2_BUSTURN_0 0x00010000U
3851 #define FSMC_BWTR2_BUSTURN_1 0x00020000U
3852 #define FSMC_BWTR2_BUSTURN_2 0x00040000U
3853 #define FSMC_BWTR2_BUSTURN_3 0x00080000U
3855 #define FSMC_BWTR2_ACCMOD 0x30000000U
3856 #define FSMC_BWTR2_ACCMOD_0 0x10000000U
3857 #define FSMC_BWTR2_ACCMOD_1 0x20000000U
3859 /****************** Bit definition for FSMC_BWTR3 register ******************/
3860 #define FSMC_BWTR3_ADDSET 0x0000000FU
3861 #define FSMC_BWTR3_ADDSET_0 0x00000001U
3862 #define FSMC_BWTR3_ADDSET_1 0x00000002U
3863 #define FSMC_BWTR3_ADDSET_2 0x00000004U
3864 #define FSMC_BWTR3_ADDSET_3 0x00000008U
3866 #define FSMC_BWTR3_ADDHLD 0x000000F0U
3867 #define FSMC_BWTR3_ADDHLD_0 0x00000010U
3868 #define FSMC_BWTR3_ADDHLD_1 0x00000020U
3869 #define FSMC_BWTR3_ADDHLD_2 0x00000040U
3870 #define FSMC_BWTR3_ADDHLD_3 0x00000080U
3872 #define FSMC_BWTR3_DATAST 0x0000FF00U
3873 #define FSMC_BWTR3_DATAST_0 0x00000100U
3874 #define FSMC_BWTR3_DATAST_1 0x00000200U
3875 #define FSMC_BWTR3_DATAST_2 0x00000400U
3876 #define FSMC_BWTR3_DATAST_3 0x00000800U
3877 #define FSMC_BWTR3_DATAST_4 0x00001000U
3878 #define FSMC_BWTR3_DATAST_5 0x00002000U
3879 #define FSMC_BWTR3_DATAST_6 0x00004000U
3880 #define FSMC_BWTR3_DATAST_7 0x00008000U
3882 #define FSMC_BWTR3_BUSTURN 0x000F0000U
3883 #define FSMC_BWTR3_BUSTURN_0 0x00010000U
3884 #define FSMC_BWTR3_BUSTURN_1 0x00020000U
3885 #define FSMC_BWTR3_BUSTURN_2 0x00040000U
3886 #define FSMC_BWTR3_BUSTURN_3 0x00080000U
3888 #define FSMC_BWTR3_ACCMOD 0x30000000U
3889 #define FSMC_BWTR3_ACCMOD_0 0x10000000U
3890 #define FSMC_BWTR3_ACCMOD_1 0x20000000U
3892 /****************** Bit definition for FSMC_BWTR4 register ******************/
3893 #define FSMC_BWTR4_ADDSET 0x0000000FU
3894 #define FSMC_BWTR4_ADDSET_0 0x00000001U
3895 #define FSMC_BWTR4_ADDSET_1 0x00000002U
3896 #define FSMC_BWTR4_ADDSET_2 0x00000004U
3897 #define FSMC_BWTR4_ADDSET_3 0x00000008U
3899 #define FSMC_BWTR4_ADDHLD 0x000000F0U
3900 #define FSMC_BWTR4_ADDHLD_0 0x00000010U
3901 #define FSMC_BWTR4_ADDHLD_1 0x00000020U
3902 #define FSMC_BWTR4_ADDHLD_2 0x00000040U
3903 #define FSMC_BWTR4_ADDHLD_3 0x00000080U
3905 #define FSMC_BWTR4_DATAST 0x0000FF00U
3906 #define FSMC_BWTR4_DATAST_0 0x00000100U
3907 #define FSMC_BWTR4_DATAST_1 0x00000200U
3908 #define FSMC_BWTR4_DATAST_2 0x00000400U
3909 #define FSMC_BWTR4_DATAST_3 0x00000800U
3910 #define FSMC_BWTR4_DATAST_4 0x00001000U
3911 #define FSMC_BWTR4_DATAST_5 0x00002000U
3912 #define FSMC_BWTR4_DATAST_6 0x00004000U
3913 #define FSMC_BWTR4_DATAST_7 0x00008000U
3915 #define FSMC_BWTR4_BUSTURN 0x000F0000U
3916 #define FSMC_BWTR4_BUSTURN_0 0x00010000U
3917 #define FSMC_BWTR4_BUSTURN_1 0x00020000U
3918 #define FSMC_BWTR4_BUSTURN_2 0x00040000U
3919 #define FSMC_BWTR4_BUSTURN_3 0x00080000U
3921 #define FSMC_BWTR4_ACCMOD 0x30000000U
3922 #define FSMC_BWTR4_ACCMOD_0 0x10000000U
3923 #define FSMC_BWTR4_ACCMOD_1 0x20000000U
3925 /****************** Bit definition for FSMC_PCR2 register *******************/
3926 #define FSMC_PCR2_PWAITEN 0x00000002U
3927 #define FSMC_PCR2_PBKEN 0x00000004U
3928 #define FSMC_PCR2_PTYP 0x00000008U
3930 #define FSMC_PCR2_PWID 0x00000030U
3931 #define FSMC_PCR2_PWID_0 0x00000010U
3932 #define FSMC_PCR2_PWID_1 0x00000020U
3934 #define FSMC_PCR2_ECCEN 0x00000040U
3936 #define FSMC_PCR2_TCLR 0x00001E00U
3937 #define FSMC_PCR2_TCLR_0 0x00000200U
3938 #define FSMC_PCR2_TCLR_1 0x00000400U
3939 #define FSMC_PCR2_TCLR_2 0x00000800U
3940 #define FSMC_PCR2_TCLR_3 0x00001000U
3942 #define FSMC_PCR2_TAR 0x0001E000U
3943 #define FSMC_PCR2_TAR_0 0x00002000U
3944 #define FSMC_PCR2_TAR_1 0x00004000U
3945 #define FSMC_PCR2_TAR_2 0x00008000U
3946 #define FSMC_PCR2_TAR_3 0x00010000U
3948 #define FSMC_PCR2_ECCPS 0x000E0000U
3949 #define FSMC_PCR2_ECCPS_0 0x00020000U
3950 #define FSMC_PCR2_ECCPS_1 0x00040000U
3951 #define FSMC_PCR2_ECCPS_2 0x00080000U
3953 /****************** Bit definition for FSMC_PCR3 register *******************/
3954 #define FSMC_PCR3_PWAITEN 0x00000002U
3955 #define FSMC_PCR3_PBKEN 0x00000004U
3956 #define FSMC_PCR3_PTYP 0x00000008U
3958 #define FSMC_PCR3_PWID 0x00000030U
3959 #define FSMC_PCR3_PWID_0 0x00000010U
3960 #define FSMC_PCR3_PWID_1 0x00000020U
3962 #define FSMC_PCR3_ECCEN 0x00000040U
3964 #define FSMC_PCR3_TCLR 0x00001E00U
3965 #define FSMC_PCR3_TCLR_0 0x00000200U
3966 #define FSMC_PCR3_TCLR_1 0x00000400U
3967 #define FSMC_PCR3_TCLR_2 0x00000800U
3968 #define FSMC_PCR3_TCLR_3 0x00001000U
3970 #define FSMC_PCR3_TAR 0x0001E000U
3971 #define FSMC_PCR3_TAR_0 0x00002000U
3972 #define FSMC_PCR3_TAR_1 0x00004000U
3973 #define FSMC_PCR3_TAR_2 0x00008000U
3974 #define FSMC_PCR3_TAR_3 0x00010000U
3976 #define FSMC_PCR3_ECCPS 0x000E0000U
3977 #define FSMC_PCR3_ECCPS_0 0x00020000U
3978 #define FSMC_PCR3_ECCPS_1 0x00040000U
3979 #define FSMC_PCR3_ECCPS_2 0x00080000U
3981 /****************** Bit definition for FSMC_PCR4 register *******************/
3982 #define FSMC_PCR4_PWAITEN 0x00000002U
3983 #define FSMC_PCR4_PBKEN 0x00000004U
3984 #define FSMC_PCR4_PTYP 0x00000008U
3986 #define FSMC_PCR4_PWID 0x00000030U
3987 #define FSMC_PCR4_PWID_0 0x00000010U
3988 #define FSMC_PCR4_PWID_1 0x00000020U
3990 #define FSMC_PCR4_ECCEN 0x00000040U
3992 #define FSMC_PCR4_TCLR 0x00001E00U
3993 #define FSMC_PCR4_TCLR_0 0x00000200U
3994 #define FSMC_PCR4_TCLR_1 0x00000400U
3995 #define FSMC_PCR4_TCLR_2 0x00000800U
3996 #define FSMC_PCR4_TCLR_3 0x00001000U
3998 #define FSMC_PCR4_TAR 0x0001E000U
3999 #define FSMC_PCR4_TAR_0 0x00002000U
4000 #define FSMC_PCR4_TAR_1 0x00004000U
4001 #define FSMC_PCR4_TAR_2 0x00008000U
4002 #define FSMC_PCR4_TAR_3 0x00010000U
4004 #define FSMC_PCR4_ECCPS 0x000E0000U
4005 #define FSMC_PCR4_ECCPS_0 0x00020000U
4006 #define FSMC_PCR4_ECCPS_1 0x00040000U
4007 #define FSMC_PCR4_ECCPS_2 0x00080000U
4009 /******************* Bit definition for FSMC_SR2 register *******************/
4010 #define FSMC_SR2_IRS 0x01U
4011 #define FSMC_SR2_ILS 0x02U
4012 #define FSMC_SR2_IFS 0x04U
4013 #define FSMC_SR2_IREN 0x08U
4014 #define FSMC_SR2_ILEN 0x10U
4015 #define FSMC_SR2_IFEN 0x20U
4016 #define FSMC_SR2_FEMPT 0x40U
4018 /******************* Bit definition for FSMC_SR3 register *******************/
4019 #define FSMC_SR3_IRS 0x01U
4020 #define FSMC_SR3_ILS 0x02U
4021 #define FSMC_SR3_IFS 0x04U
4022 #define FSMC_SR3_IREN 0x08U
4023 #define FSMC_SR3_ILEN 0x10U
4024 #define FSMC_SR3_IFEN 0x20U
4025 #define FSMC_SR3_FEMPT 0x40U
4027 /******************* Bit definition for FSMC_SR4 register *******************/
4028 #define FSMC_SR4_IRS 0x01U
4029 #define FSMC_SR4_ILS 0x02U
4030 #define FSMC_SR4_IFS 0x04U
4031 #define FSMC_SR4_IREN 0x08U
4032 #define FSMC_SR4_ILEN 0x10U
4033 #define FSMC_SR4_IFEN 0x20U
4034 #define FSMC_SR4_FEMPT 0x40U
4036 /****************** Bit definition for FSMC_PMEM2 register ******************/
4037 #define FSMC_PMEM2_MEMSET2 0x000000FFU
4038 #define FSMC_PMEM2_MEMSET2_0 0x00000001U
4039 #define FSMC_PMEM2_MEMSET2_1 0x00000002U
4040 #define FSMC_PMEM2_MEMSET2_2 0x00000004U
4041 #define FSMC_PMEM2_MEMSET2_3 0x00000008U
4042 #define FSMC_PMEM2_MEMSET2_4 0x00000010U
4043 #define FSMC_PMEM2_MEMSET2_5 0x00000020U
4044 #define FSMC_PMEM2_MEMSET2_6 0x00000040U
4045 #define FSMC_PMEM2_MEMSET2_7 0x00000080U
4047 #define FSMC_PMEM2_MEMWAIT2 0x0000FF00U
4048 #define FSMC_PMEM2_MEMWAIT2_0 0x00000100U
4049 #define FSMC_PMEM2_MEMWAIT2_1 0x00000200U
4050 #define FSMC_PMEM2_MEMWAIT2_2 0x00000400U
4051 #define FSMC_PMEM2_MEMWAIT2_3 0x00000800U
4052 #define FSMC_PMEM2_MEMWAIT2_4 0x00001000U
4053 #define FSMC_PMEM2_MEMWAIT2_5 0x00002000U
4054 #define FSMC_PMEM2_MEMWAIT2_6 0x00004000U
4055 #define FSMC_PMEM2_MEMWAIT2_7 0x00008000U
4057 #define FSMC_PMEM2_MEMHOLD2 0x00FF0000U
4058 #define FSMC_PMEM2_MEMHOLD2_0 0x00010000U
4059 #define FSMC_PMEM2_MEMHOLD2_1 0x00020000U
4060 #define FSMC_PMEM2_MEMHOLD2_2 0x00040000U
4061 #define FSMC_PMEM2_MEMHOLD2_3 0x00080000U
4062 #define FSMC_PMEM2_MEMHOLD2_4 0x00100000U
4063 #define FSMC_PMEM2_MEMHOLD2_5 0x00200000U
4064 #define FSMC_PMEM2_MEMHOLD2_6 0x00400000U
4065 #define FSMC_PMEM2_MEMHOLD2_7 0x00800000U
4067 #define FSMC_PMEM2_MEMHIZ2 0xFF000000U
4068 #define FSMC_PMEM2_MEMHIZ2_0 0x01000000U
4069 #define FSMC_PMEM2_MEMHIZ2_1 0x02000000U
4070 #define FSMC_PMEM2_MEMHIZ2_2 0x04000000U
4071 #define FSMC_PMEM2_MEMHIZ2_3 0x08000000U
4072 #define FSMC_PMEM2_MEMHIZ2_4 0x10000000U
4073 #define FSMC_PMEM2_MEMHIZ2_5 0x20000000U
4074 #define FSMC_PMEM2_MEMHIZ2_6 0x40000000U
4075 #define FSMC_PMEM2_MEMHIZ2_7 0x80000000U
4077 /****************** Bit definition for FSMC_PMEM3 register ******************/
4078 #define FSMC_PMEM3_MEMSET3 0x000000FFU
4079 #define FSMC_PMEM3_MEMSET3_0 0x00000001U
4080 #define FSMC_PMEM3_MEMSET3_1 0x00000002U
4081 #define FSMC_PMEM3_MEMSET3_2 0x00000004U
4082 #define FSMC_PMEM3_MEMSET3_3 0x00000008U
4083 #define FSMC_PMEM3_MEMSET3_4 0x00000010U
4084 #define FSMC_PMEM3_MEMSET3_5 0x00000020U
4085 #define FSMC_PMEM3_MEMSET3_6 0x00000040U
4086 #define FSMC_PMEM3_MEMSET3_7 0x00000080U
4088 #define FSMC_PMEM3_MEMWAIT3 0x0000FF00U
4089 #define FSMC_PMEM3_MEMWAIT3_0 0x00000100U
4090 #define FSMC_PMEM3_MEMWAIT3_1 0x00000200U
4091 #define FSMC_PMEM3_MEMWAIT3_2 0x00000400U
4092 #define FSMC_PMEM3_MEMWAIT3_3 0x00000800U
4093 #define FSMC_PMEM3_MEMWAIT3_4 0x00001000U
4094 #define FSMC_PMEM3_MEMWAIT3_5 0x00002000U
4095 #define FSMC_PMEM3_MEMWAIT3_6 0x00004000U
4096 #define FSMC_PMEM3_MEMWAIT3_7 0x00008000U
4098 #define FSMC_PMEM3_MEMHOLD3 0x00FF0000U
4099 #define FSMC_PMEM3_MEMHOLD3_0 0x00010000U
4100 #define FSMC_PMEM3_MEMHOLD3_1 0x00020000U
4101 #define FSMC_PMEM3_MEMHOLD3_2 0x00040000U
4102 #define FSMC_PMEM3_MEMHOLD3_3 0x00080000U
4103 #define FSMC_PMEM3_MEMHOLD3_4 0x00100000U
4104 #define FSMC_PMEM3_MEMHOLD3_5 0x00200000U
4105 #define FSMC_PMEM3_MEMHOLD3_6 0x00400000U
4106 #define FSMC_PMEM3_MEMHOLD3_7 0x00800000U
4108 #define FSMC_PMEM3_MEMHIZ3 0xFF000000U
4109 #define FSMC_PMEM3_MEMHIZ3_0 0x01000000U
4110 #define FSMC_PMEM3_MEMHIZ3_1 0x02000000U
4111 #define FSMC_PMEM3_MEMHIZ3_2 0x04000000U
4112 #define FSMC_PMEM3_MEMHIZ3_3 0x08000000U
4113 #define FSMC_PMEM3_MEMHIZ3_4 0x10000000U
4114 #define FSMC_PMEM3_MEMHIZ3_5 0x20000000U
4115 #define FSMC_PMEM3_MEMHIZ3_6 0x40000000U
4116 #define FSMC_PMEM3_MEMHIZ3_7 0x80000000U
4118 /****************** Bit definition for FSMC_PMEM4 register ******************/
4119 #define FSMC_PMEM4_MEMSET4 0x000000FFU
4120 #define FSMC_PMEM4_MEMSET4_0 0x00000001U
4121 #define FSMC_PMEM4_MEMSET4_1 0x00000002U
4122 #define FSMC_PMEM4_MEMSET4_2 0x00000004U
4123 #define FSMC_PMEM4_MEMSET4_3 0x00000008U
4124 #define FSMC_PMEM4_MEMSET4_4 0x00000010U
4125 #define FSMC_PMEM4_MEMSET4_5 0x00000020U
4126 #define FSMC_PMEM4_MEMSET4_6 0x00000040U
4127 #define FSMC_PMEM4_MEMSET4_7 0x00000080U
4129 #define FSMC_PMEM4_MEMWAIT4 0x0000FF00U
4130 #define FSMC_PMEM4_MEMWAIT4_0 0x00000100U
4131 #define FSMC_PMEM4_MEMWAIT4_1 0x00000200U
4132 #define FSMC_PMEM4_MEMWAIT4_2 0x00000400U
4133 #define FSMC_PMEM4_MEMWAIT4_3 0x00000800U
4134 #define FSMC_PMEM4_MEMWAIT4_4 0x00001000U
4135 #define FSMC_PMEM4_MEMWAIT4_5 0x00002000U
4136 #define FSMC_PMEM4_MEMWAIT4_6 0x00004000U
4137 #define FSMC_PMEM4_MEMWAIT4_7 0x00008000U
4139 #define FSMC_PMEM4_MEMHOLD4 0x00FF0000U
4140 #define FSMC_PMEM4_MEMHOLD4_0 0x00010000U
4141 #define FSMC_PMEM4_MEMHOLD4_1 0x00020000U
4142 #define FSMC_PMEM4_MEMHOLD4_2 0x00040000U
4143 #define FSMC_PMEM4_MEMHOLD4_3 0x00080000U
4144 #define FSMC_PMEM4_MEMHOLD4_4 0x00100000U
4145 #define FSMC_PMEM4_MEMHOLD4_5 0x00200000U
4146 #define FSMC_PMEM4_MEMHOLD4_6 0x00400000U
4147 #define FSMC_PMEM4_MEMHOLD4_7 0x00800000U
4149 #define FSMC_PMEM4_MEMHIZ4 0xFF000000U
4150 #define FSMC_PMEM4_MEMHIZ4_0 0x01000000U
4151 #define FSMC_PMEM4_MEMHIZ4_1 0x02000000U
4152 #define FSMC_PMEM4_MEMHIZ4_2 0x04000000U
4153 #define FSMC_PMEM4_MEMHIZ4_3 0x08000000U
4154 #define FSMC_PMEM4_MEMHIZ4_4 0x10000000U
4155 #define FSMC_PMEM4_MEMHIZ4_5 0x20000000U
4156 #define FSMC_PMEM4_MEMHIZ4_6 0x40000000U
4157 #define FSMC_PMEM4_MEMHIZ4_7 0x80000000U
4159 /****************** Bit definition for FSMC_PATT2 register ******************/
4160 #define FSMC_PATT2_ATTSET2 0x000000FFU
4161 #define FSMC_PATT2_ATTSET2_0 0x00000001U
4162 #define FSMC_PATT2_ATTSET2_1 0x00000002U
4163 #define FSMC_PATT2_ATTSET2_2 0x00000004U
4164 #define FSMC_PATT2_ATTSET2_3 0x00000008U
4165 #define FSMC_PATT2_ATTSET2_4 0x00000010U
4166 #define FSMC_PATT2_ATTSET2_5 0x00000020U
4167 #define FSMC_PATT2_ATTSET2_6 0x00000040U
4168 #define FSMC_PATT2_ATTSET2_7 0x00000080U
4170 #define FSMC_PATT2_ATTWAIT2 0x0000FF00U
4171 #define FSMC_PATT2_ATTWAIT2_0 0x00000100U
4172 #define FSMC_PATT2_ATTWAIT2_1 0x00000200U
4173 #define FSMC_PATT2_ATTWAIT2_2 0x00000400U
4174 #define FSMC_PATT2_ATTWAIT2_3 0x00000800U
4175 #define FSMC_PATT2_ATTWAIT2_4 0x00001000U
4176 #define FSMC_PATT2_ATTWAIT2_5 0x00002000U
4177 #define FSMC_PATT2_ATTWAIT2_6 0x00004000U
4178 #define FSMC_PATT2_ATTWAIT2_7 0x00008000U
4180 #define FSMC_PATT2_ATTHOLD2 0x00FF0000U
4181 #define FSMC_PATT2_ATTHOLD2_0 0x00010000U
4182 #define FSMC_PATT2_ATTHOLD2_1 0x00020000U
4183 #define FSMC_PATT2_ATTHOLD2_2 0x00040000U
4184 #define FSMC_PATT2_ATTHOLD2_3 0x00080000U
4185 #define FSMC_PATT2_ATTHOLD2_4 0x00100000U
4186 #define FSMC_PATT2_ATTHOLD2_5 0x00200000U
4187 #define FSMC_PATT2_ATTHOLD2_6 0x00400000U
4188 #define FSMC_PATT2_ATTHOLD2_7 0x00800000U
4190 #define FSMC_PATT2_ATTHIZ2 0xFF000000U
4191 #define FSMC_PATT2_ATTHIZ2_0 0x01000000U
4192 #define FSMC_PATT2_ATTHIZ2_1 0x02000000U
4193 #define FSMC_PATT2_ATTHIZ2_2 0x04000000U
4194 #define FSMC_PATT2_ATTHIZ2_3 0x08000000U
4195 #define FSMC_PATT2_ATTHIZ2_4 0x10000000U
4196 #define FSMC_PATT2_ATTHIZ2_5 0x20000000U
4197 #define FSMC_PATT2_ATTHIZ2_6 0x40000000U
4198 #define FSMC_PATT2_ATTHIZ2_7 0x80000000U
4200 /****************** Bit definition for FSMC_PATT3 register ******************/
4201 #define FSMC_PATT3_ATTSET3 0x000000FFU
4202 #define FSMC_PATT3_ATTSET3_0 0x00000001U
4203 #define FSMC_PATT3_ATTSET3_1 0x00000002U
4204 #define FSMC_PATT3_ATTSET3_2 0x00000004U
4205 #define FSMC_PATT3_ATTSET3_3 0x00000008U
4206 #define FSMC_PATT3_ATTSET3_4 0x00000010U
4207 #define FSMC_PATT3_ATTSET3_5 0x00000020U
4208 #define FSMC_PATT3_ATTSET3_6 0x00000040U
4209 #define FSMC_PATT3_ATTSET3_7 0x00000080U
4211 #define FSMC_PATT3_ATTWAIT3 0x0000FF00U
4212 #define FSMC_PATT3_ATTWAIT3_0 0x00000100U
4213 #define FSMC_PATT3_ATTWAIT3_1 0x00000200U
4214 #define FSMC_PATT3_ATTWAIT3_2 0x00000400U
4215 #define FSMC_PATT3_ATTWAIT3_3 0x00000800U
4216 #define FSMC_PATT3_ATTWAIT3_4 0x00001000U
4217 #define FSMC_PATT3_ATTWAIT3_5 0x00002000U
4218 #define FSMC_PATT3_ATTWAIT3_6 0x00004000U
4219 #define FSMC_PATT3_ATTWAIT3_7 0x00008000U
4221 #define FSMC_PATT3_ATTHOLD3 0x00FF0000U
4222 #define FSMC_PATT3_ATTHOLD3_0 0x00010000U
4223 #define FSMC_PATT3_ATTHOLD3_1 0x00020000U
4224 #define FSMC_PATT3_ATTHOLD3_2 0x00040000U
4225 #define FSMC_PATT3_ATTHOLD3_3 0x00080000U
4226 #define FSMC_PATT3_ATTHOLD3_4 0x00100000U
4227 #define FSMC_PATT3_ATTHOLD3_5 0x00200000U
4228 #define FSMC_PATT3_ATTHOLD3_6 0x00400000U
4229 #define FSMC_PATT3_ATTHOLD3_7 0x00800000U
4231 #define FSMC_PATT3_ATTHIZ3 0xFF000000U
4232 #define FSMC_PATT3_ATTHIZ3_0 0x01000000U
4233 #define FSMC_PATT3_ATTHIZ3_1 0x02000000U
4234 #define FSMC_PATT3_ATTHIZ3_2 0x04000000U
4235 #define FSMC_PATT3_ATTHIZ3_3 0x08000000U
4236 #define FSMC_PATT3_ATTHIZ3_4 0x10000000U
4237 #define FSMC_PATT3_ATTHIZ3_5 0x20000000U
4238 #define FSMC_PATT3_ATTHIZ3_6 0x40000000U
4239 #define FSMC_PATT3_ATTHIZ3_7 0x80000000U
4241 /****************** Bit definition for FSMC_PATT4 register ******************/
4242 #define FSMC_PATT4_ATTSET4 0x000000FFU
4243 #define FSMC_PATT4_ATTSET4_0 0x00000001U
4244 #define FSMC_PATT4_ATTSET4_1 0x00000002U
4245 #define FSMC_PATT4_ATTSET4_2 0x00000004U
4246 #define FSMC_PATT4_ATTSET4_3 0x00000008U
4247 #define FSMC_PATT4_ATTSET4_4 0x00000010U
4248 #define FSMC_PATT4_ATTSET4_5 0x00000020U
4249 #define FSMC_PATT4_ATTSET4_6 0x00000040U
4250 #define FSMC_PATT4_ATTSET4_7 0x00000080U
4252 #define FSMC_PATT4_ATTWAIT4 0x0000FF00U
4253 #define FSMC_PATT4_ATTWAIT4_0 0x00000100U
4254 #define FSMC_PATT4_ATTWAIT4_1 0x00000200U
4255 #define FSMC_PATT4_ATTWAIT4_2 0x00000400U
4256 #define FSMC_PATT4_ATTWAIT4_3 0x00000800U
4257 #define FSMC_PATT4_ATTWAIT4_4 0x00001000U
4258 #define FSMC_PATT4_ATTWAIT4_5 0x00002000U
4259 #define FSMC_PATT4_ATTWAIT4_6 0x00004000U
4260 #define FSMC_PATT4_ATTWAIT4_7 0x00008000U
4262 #define FSMC_PATT4_ATTHOLD4 0x00FF0000U
4263 #define FSMC_PATT4_ATTHOLD4_0 0x00010000U
4264 #define FSMC_PATT4_ATTHOLD4_1 0x00020000U
4265 #define FSMC_PATT4_ATTHOLD4_2 0x00040000U
4266 #define FSMC_PATT4_ATTHOLD4_3 0x00080000U
4267 #define FSMC_PATT4_ATTHOLD4_4 0x00100000U
4268 #define FSMC_PATT4_ATTHOLD4_5 0x00200000U
4269 #define FSMC_PATT4_ATTHOLD4_6 0x00400000U
4270 #define FSMC_PATT4_ATTHOLD4_7 0x00800000U
4272 #define FSMC_PATT4_ATTHIZ4 0xFF000000U
4273 #define FSMC_PATT4_ATTHIZ4_0 0x01000000U
4274 #define FSMC_PATT4_ATTHIZ4_1 0x02000000U
4275 #define FSMC_PATT4_ATTHIZ4_2 0x04000000U
4276 #define FSMC_PATT4_ATTHIZ4_3 0x08000000U
4277 #define FSMC_PATT4_ATTHIZ4_4 0x10000000U
4278 #define FSMC_PATT4_ATTHIZ4_5 0x20000000U
4279 #define FSMC_PATT4_ATTHIZ4_6 0x40000000U
4280 #define FSMC_PATT4_ATTHIZ4_7 0x80000000U
4282 /****************** Bit definition for FSMC_PIO4 register *******************/
4283 #define FSMC_PIO4_IOSET4 0x000000FFU
4284 #define FSMC_PIO4_IOSET4_0 0x00000001U
4285 #define FSMC_PIO4_IOSET4_1 0x00000002U
4286 #define FSMC_PIO4_IOSET4_2 0x00000004U
4287 #define FSMC_PIO4_IOSET4_3 0x00000008U
4288 #define FSMC_PIO4_IOSET4_4 0x00000010U
4289 #define FSMC_PIO4_IOSET4_5 0x00000020U
4290 #define FSMC_PIO4_IOSET4_6 0x00000040U
4291 #define FSMC_PIO4_IOSET4_7 0x00000080U
4293 #define FSMC_PIO4_IOWAIT4 0x0000FF00U
4294 #define FSMC_PIO4_IOWAIT4_0 0x00000100U
4295 #define FSMC_PIO4_IOWAIT4_1 0x00000200U
4296 #define FSMC_PIO4_IOWAIT4_2 0x00000400U
4297 #define FSMC_PIO4_IOWAIT4_3 0x00000800U
4298 #define FSMC_PIO4_IOWAIT4_4 0x00001000U
4299 #define FSMC_PIO4_IOWAIT4_5 0x00002000U
4300 #define FSMC_PIO4_IOWAIT4_6 0x00004000U
4301 #define FSMC_PIO4_IOWAIT4_7 0x00008000U
4303 #define FSMC_PIO4_IOHOLD4 0x00FF0000U
4304 #define FSMC_PIO4_IOHOLD4_0 0x00010000U
4305 #define FSMC_PIO4_IOHOLD4_1 0x00020000U
4306 #define FSMC_PIO4_IOHOLD4_2 0x00040000U
4307 #define FSMC_PIO4_IOHOLD4_3 0x00080000U
4308 #define FSMC_PIO4_IOHOLD4_4 0x00100000U
4309 #define FSMC_PIO4_IOHOLD4_5 0x00200000U
4310 #define FSMC_PIO4_IOHOLD4_6 0x00400000U
4311 #define FSMC_PIO4_IOHOLD4_7 0x00800000U
4313 #define FSMC_PIO4_IOHIZ4 0xFF000000U
4314 #define FSMC_PIO4_IOHIZ4_0 0x01000000U
4315 #define FSMC_PIO4_IOHIZ4_1 0x02000000U
4316 #define FSMC_PIO4_IOHIZ4_2 0x04000000U
4317 #define FSMC_PIO4_IOHIZ4_3 0x08000000U
4318 #define FSMC_PIO4_IOHIZ4_4 0x10000000U
4319 #define FSMC_PIO4_IOHIZ4_5 0x20000000U
4320 #define FSMC_PIO4_IOHIZ4_6 0x40000000U
4321 #define FSMC_PIO4_IOHIZ4_7 0x80000000U
4323 /****************** Bit definition for FSMC_ECCR2 register ******************/
4324 #define FSMC_ECCR2_ECC2 0xFFFFFFFFU
4326 /****************** Bit definition for FSMC_ECCR3 register ******************/
4327 #define FSMC_ECCR3_ECC3 0xFFFFFFFFU
4329 /******************************************************************************/
4330 /* */
4331 /* General Purpose I/O */
4332 /* */
4333 /******************************************************************************/
4334 /****************** Bits definition for GPIO_MODER register *****************/
4335 #define GPIO_MODER_MODER0 0x00000003U
4336 #define GPIO_MODER_MODER0_0 0x00000001U
4337 #define GPIO_MODER_MODER0_1 0x00000002U
4338 
4339 #define GPIO_MODER_MODER1 0x0000000CU
4340 #define GPIO_MODER_MODER1_0 0x00000004U
4341 #define GPIO_MODER_MODER1_1 0x00000008U
4342 
4343 #define GPIO_MODER_MODER2 0x00000030U
4344 #define GPIO_MODER_MODER2_0 0x00000010U
4345 #define GPIO_MODER_MODER2_1 0x00000020U
4346 
4347 #define GPIO_MODER_MODER3 0x000000C0U
4348 #define GPIO_MODER_MODER3_0 0x00000040U
4349 #define GPIO_MODER_MODER3_1 0x00000080U
4350 
4351 #define GPIO_MODER_MODER4 0x00000300U
4352 #define GPIO_MODER_MODER4_0 0x00000100U
4353 #define GPIO_MODER_MODER4_1 0x00000200U
4354 
4355 #define GPIO_MODER_MODER5 0x00000C00U
4356 #define GPIO_MODER_MODER5_0 0x00000400U
4357 #define GPIO_MODER_MODER5_1 0x00000800U
4358 
4359 #define GPIO_MODER_MODER6 0x00003000U
4360 #define GPIO_MODER_MODER6_0 0x00001000U
4361 #define GPIO_MODER_MODER6_1 0x00002000U
4362 
4363 #define GPIO_MODER_MODER7 0x0000C000U
4364 #define GPIO_MODER_MODER7_0 0x00004000U
4365 #define GPIO_MODER_MODER7_1 0x00008000U
4366 
4367 #define GPIO_MODER_MODER8 0x00030000U
4368 #define GPIO_MODER_MODER8_0 0x00010000U
4369 #define GPIO_MODER_MODER8_1 0x00020000U
4370 
4371 #define GPIO_MODER_MODER9 0x000C0000U
4372 #define GPIO_MODER_MODER9_0 0x00040000U
4373 #define GPIO_MODER_MODER9_1 0x00080000U
4374 
4375 #define GPIO_MODER_MODER10 0x00300000U
4376 #define GPIO_MODER_MODER10_0 0x00100000U
4377 #define GPIO_MODER_MODER10_1 0x00200000U
4378 
4379 #define GPIO_MODER_MODER11 0x00C00000U
4380 #define GPIO_MODER_MODER11_0 0x00400000U
4381 #define GPIO_MODER_MODER11_1 0x00800000U
4382 
4383 #define GPIO_MODER_MODER12 0x03000000U
4384 #define GPIO_MODER_MODER12_0 0x01000000U
4385 #define GPIO_MODER_MODER12_1 0x02000000U
4386 
4387 #define GPIO_MODER_MODER13 0x0C000000U
4388 #define GPIO_MODER_MODER13_0 0x04000000U
4389 #define GPIO_MODER_MODER13_1 0x08000000U
4390 
4391 #define GPIO_MODER_MODER14 0x30000000U
4392 #define GPIO_MODER_MODER14_0 0x10000000U
4393 #define GPIO_MODER_MODER14_1 0x20000000U
4394 
4395 #define GPIO_MODER_MODER15 0xC0000000U
4396 #define GPIO_MODER_MODER15_0 0x40000000U
4397 #define GPIO_MODER_MODER15_1 0x80000000U
4398 
4399 /****************** Bits definition for GPIO_OTYPER register ****************/
4400 #define GPIO_OTYPER_OT_0 0x00000001U
4401 #define GPIO_OTYPER_OT_1 0x00000002U
4402 #define GPIO_OTYPER_OT_2 0x00000004U
4403 #define GPIO_OTYPER_OT_3 0x00000008U
4404 #define GPIO_OTYPER_OT_4 0x00000010U
4405 #define GPIO_OTYPER_OT_5 0x00000020U
4406 #define GPIO_OTYPER_OT_6 0x00000040U
4407 #define GPIO_OTYPER_OT_7 0x00000080U
4408 #define GPIO_OTYPER_OT_8 0x00000100U
4409 #define GPIO_OTYPER_OT_9 0x00000200U
4410 #define GPIO_OTYPER_OT_10 0x00000400U
4411 #define GPIO_OTYPER_OT_11 0x00000800U
4412 #define GPIO_OTYPER_OT_12 0x00001000U
4413 #define GPIO_OTYPER_OT_13 0x00002000U
4414 #define GPIO_OTYPER_OT_14 0x00004000U
4415 #define GPIO_OTYPER_OT_15 0x00008000U
4416 
4417 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4418 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4419 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4420 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4421 
4422 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4423 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4424 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4425 
4426 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4427 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4428 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4429 
4430 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4431 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4432 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4433 
4434 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4435 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4436 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4437 
4438 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4439 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4440 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4441 
4442 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4443 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4444 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4445 
4446 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4447 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4448 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4449 
4450 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4451 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4452 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4453 
4454 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4455 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4456 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4457 
4458 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4459 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4460 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4461 
4462 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4463 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4464 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4465 
4466 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4467 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4468 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4469 
4470 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4471 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4472 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4473 
4474 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4475 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4476 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4477 
4478 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4479 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4480 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4481 
4482 /****************** Bits definition for GPIO_PUPDR register *****************/
4483 #define GPIO_PUPDR_PUPDR0 0x00000003U
4484 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4485 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4486 
4487 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4488 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4489 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4490 
4491 #define GPIO_PUPDR_PUPDR2 0x00000030U
4492 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4493 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4494 
4495 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4496 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4497 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4498 
4499 #define GPIO_PUPDR_PUPDR4 0x00000300U
4500 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4501 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4502 
4503 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4504 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4505 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4506 
4507 #define GPIO_PUPDR_PUPDR6 0x00003000U
4508 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4509 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4510 
4511 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4512 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4513 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4514 
4515 #define GPIO_PUPDR_PUPDR8 0x00030000U
4516 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4517 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4518 
4519 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4520 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4521 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4522 
4523 #define GPIO_PUPDR_PUPDR10 0x00300000U
4524 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4525 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4526 
4527 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4528 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4529 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4530 
4531 #define GPIO_PUPDR_PUPDR12 0x03000000U
4532 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4533 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4534 
4535 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4536 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4537 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4538 
4539 #define GPIO_PUPDR_PUPDR14 0x30000000U
4540 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4541 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
4542 
4543 #define GPIO_PUPDR_PUPDR15 0xC0000000U
4544 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
4545 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
4546 
4547 /****************** Bits definition for GPIO_IDR register *******************/
4548 #define GPIO_IDR_IDR_0 0x00000001U
4549 #define GPIO_IDR_IDR_1 0x00000002U
4550 #define GPIO_IDR_IDR_2 0x00000004U
4551 #define GPIO_IDR_IDR_3 0x00000008U
4552 #define GPIO_IDR_IDR_4 0x00000010U
4553 #define GPIO_IDR_IDR_5 0x00000020U
4554 #define GPIO_IDR_IDR_6 0x00000040U
4555 #define GPIO_IDR_IDR_7 0x00000080U
4556 #define GPIO_IDR_IDR_8 0x00000100U
4557 #define GPIO_IDR_IDR_9 0x00000200U
4558 #define GPIO_IDR_IDR_10 0x00000400U
4559 #define GPIO_IDR_IDR_11 0x00000800U
4560 #define GPIO_IDR_IDR_12 0x00001000U
4561 #define GPIO_IDR_IDR_13 0x00002000U
4562 #define GPIO_IDR_IDR_14 0x00004000U
4563 #define GPIO_IDR_IDR_15 0x00008000U
4564 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4565 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4566 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4567 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4568 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4569 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4570 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4571 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4572 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4573 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4574 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4575 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4576 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4577 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4578 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4579 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4580 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4581 
4582 /****************** Bits definition for GPIO_ODR register *******************/
4583 #define GPIO_ODR_ODR_0 0x00000001U
4584 #define GPIO_ODR_ODR_1 0x00000002U
4585 #define GPIO_ODR_ODR_2 0x00000004U
4586 #define GPIO_ODR_ODR_3 0x00000008U
4587 #define GPIO_ODR_ODR_4 0x00000010U
4588 #define GPIO_ODR_ODR_5 0x00000020U
4589 #define GPIO_ODR_ODR_6 0x00000040U
4590 #define GPIO_ODR_ODR_7 0x00000080U
4591 #define GPIO_ODR_ODR_8 0x00000100U
4592 #define GPIO_ODR_ODR_9 0x00000200U
4593 #define GPIO_ODR_ODR_10 0x00000400U
4594 #define GPIO_ODR_ODR_11 0x00000800U
4595 #define GPIO_ODR_ODR_12 0x00001000U
4596 #define GPIO_ODR_ODR_13 0x00002000U
4597 #define GPIO_ODR_ODR_14 0x00004000U
4598 #define GPIO_ODR_ODR_15 0x00008000U
4599 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4600 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4601 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4602 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4603 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4604 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4605 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4606 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4607 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4608 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4609 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4610 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4611 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4612 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4613 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4614 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4615 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4616 
4617 /****************** Bits definition for GPIO_BSRR register ******************/
4618 #define GPIO_BSRR_BS_0 0x00000001U
4619 #define GPIO_BSRR_BS_1 0x00000002U
4620 #define GPIO_BSRR_BS_2 0x00000004U
4621 #define GPIO_BSRR_BS_3 0x00000008U
4622 #define GPIO_BSRR_BS_4 0x00000010U
4623 #define GPIO_BSRR_BS_5 0x00000020U
4624 #define GPIO_BSRR_BS_6 0x00000040U
4625 #define GPIO_BSRR_BS_7 0x00000080U
4626 #define GPIO_BSRR_BS_8 0x00000100U
4627 #define GPIO_BSRR_BS_9 0x00000200U
4628 #define GPIO_BSRR_BS_10 0x00000400U
4629 #define GPIO_BSRR_BS_11 0x00000800U
4630 #define GPIO_BSRR_BS_12 0x00001000U
4631 #define GPIO_BSRR_BS_13 0x00002000U
4632 #define GPIO_BSRR_BS_14 0x00004000U
4633 #define GPIO_BSRR_BS_15 0x00008000U
4634 #define GPIO_BSRR_BR_0 0x00010000U
4635 #define GPIO_BSRR_BR_1 0x00020000U
4636 #define GPIO_BSRR_BR_2 0x00040000U
4637 #define GPIO_BSRR_BR_3 0x00080000U
4638 #define GPIO_BSRR_BR_4 0x00100000U
4639 #define GPIO_BSRR_BR_5 0x00200000U
4640 #define GPIO_BSRR_BR_6 0x00400000U
4641 #define GPIO_BSRR_BR_7 0x00800000U
4642 #define GPIO_BSRR_BR_8 0x01000000U
4643 #define GPIO_BSRR_BR_9 0x02000000U
4644 #define GPIO_BSRR_BR_10 0x04000000U
4645 #define GPIO_BSRR_BR_11 0x08000000U
4646 #define GPIO_BSRR_BR_12 0x10000000U
4647 #define GPIO_BSRR_BR_13 0x20000000U
4648 #define GPIO_BSRR_BR_14 0x40000000U
4649 #define GPIO_BSRR_BR_15 0x80000000U
4650 
4651 /****************** Bit definition for GPIO_LCKR register *********************/
4652 #define GPIO_LCKR_LCK0 0x00000001U
4653 #define GPIO_LCKR_LCK1 0x00000002U
4654 #define GPIO_LCKR_LCK2 0x00000004U
4655 #define GPIO_LCKR_LCK3 0x00000008U
4656 #define GPIO_LCKR_LCK4 0x00000010U
4657 #define GPIO_LCKR_LCK5 0x00000020U
4658 #define GPIO_LCKR_LCK6 0x00000040U
4659 #define GPIO_LCKR_LCK7 0x00000080U
4660 #define GPIO_LCKR_LCK8 0x00000100U
4661 #define GPIO_LCKR_LCK9 0x00000200U
4662 #define GPIO_LCKR_LCK10 0x00000400U
4663 #define GPIO_LCKR_LCK11 0x00000800U
4664 #define GPIO_LCKR_LCK12 0x00001000U
4665 #define GPIO_LCKR_LCK13 0x00002000U
4666 #define GPIO_LCKR_LCK14 0x00004000U
4667 #define GPIO_LCKR_LCK15 0x00008000U
4668 #define GPIO_LCKR_LCKK 0x00010000U
4669 
4670 /******************************************************************************/
4671 /* */
4672 /* Inter-integrated Circuit Interface */
4673 /* */
4674 /******************************************************************************/
4675 /******************* Bit definition for I2C_CR1 register ********************/
4676 #define I2C_CR1_PE 0x00000001U
4677 #define I2C_CR1_SMBUS 0x00000002U
4678 #define I2C_CR1_SMBTYPE 0x00000008U
4679 #define I2C_CR1_ENARP 0x00000010U
4680 #define I2C_CR1_ENPEC 0x00000020U
4681 #define I2C_CR1_ENGC 0x00000040U
4682 #define I2C_CR1_NOSTRETCH 0x00000080U
4683 #define I2C_CR1_START 0x00000100U
4684 #define I2C_CR1_STOP 0x00000200U
4685 #define I2C_CR1_ACK 0x00000400U
4686 #define I2C_CR1_POS 0x00000800U
4687 #define I2C_CR1_PEC 0x00001000U
4688 #define I2C_CR1_ALERT 0x00002000U
4689 #define I2C_CR1_SWRST 0x00008000U
4691 /******************* Bit definition for I2C_CR2 register ********************/
4692 #define I2C_CR2_FREQ 0x0000003FU
4693 #define I2C_CR2_FREQ_0 0x00000001U
4694 #define I2C_CR2_FREQ_1 0x00000002U
4695 #define I2C_CR2_FREQ_2 0x00000004U
4696 #define I2C_CR2_FREQ_3 0x00000008U
4697 #define I2C_CR2_FREQ_4 0x00000010U
4698 #define I2C_CR2_FREQ_5 0x00000020U
4700 #define I2C_CR2_ITERREN 0x00000100U
4701 #define I2C_CR2_ITEVTEN 0x00000200U
4702 #define I2C_CR2_ITBUFEN 0x00000400U
4703 #define I2C_CR2_DMAEN 0x00000800U
4704 #define I2C_CR2_LAST 0x00001000U
4706 /******************* Bit definition for I2C_OAR1 register *******************/
4707 #define I2C_OAR1_ADD1_7 0x000000FEU
4708 #define I2C_OAR1_ADD8_9 0x00000300U
4710 #define I2C_OAR1_ADD0 0x00000001U
4711 #define I2C_OAR1_ADD1 0x00000002U
4712 #define I2C_OAR1_ADD2 0x00000004U
4713 #define I2C_OAR1_ADD3 0x00000008U
4714 #define I2C_OAR1_ADD4 0x00000010U
4715 #define I2C_OAR1_ADD5 0x00000020U
4716 #define I2C_OAR1_ADD6 0x00000040U
4717 #define I2C_OAR1_ADD7 0x00000080U
4718 #define I2C_OAR1_ADD8 0x00000100U
4719 #define I2C_OAR1_ADD9 0x00000200U
4721 #define I2C_OAR1_ADDMODE 0x00008000U
4723 /******************* Bit definition for I2C_OAR2 register *******************/
4724 #define I2C_OAR2_ENDUAL 0x00000001U
4725 #define I2C_OAR2_ADD2 0x000000FEU
4727 /******************** Bit definition for I2C_DR register ********************/
4728 #define I2C_DR_DR 0x000000FFU
4730 /******************* Bit definition for I2C_SR1 register ********************/
4731 #define I2C_SR1_SB 0x00000001U
4732 #define I2C_SR1_ADDR 0x00000002U
4733 #define I2C_SR1_BTF 0x00000004U
4734 #define I2C_SR1_ADD10 0x00000008U
4735 #define I2C_SR1_STOPF 0x00000010U
4736 #define I2C_SR1_RXNE 0x00000040U
4737 #define I2C_SR1_TXE 0x00000080U
4738 #define I2C_SR1_BERR 0x00000100U
4739 #define I2C_SR1_ARLO 0x00000200U
4740 #define I2C_SR1_AF 0x00000400U
4741 #define I2C_SR1_OVR 0x00000800U
4742 #define I2C_SR1_PECERR 0x00001000U
4743 #define I2C_SR1_TIMEOUT 0x00004000U
4744 #define I2C_SR1_SMBALERT 0x00008000U
4746 /******************* Bit definition for I2C_SR2 register ********************/
4747 #define I2C_SR2_MSL 0x00000001U
4748 #define I2C_SR2_BUSY 0x00000002U
4749 #define I2C_SR2_TRA 0x00000004U
4750 #define I2C_SR2_GENCALL 0x00000010U
4751 #define I2C_SR2_SMBDEFAULT 0x00000020U
4752 #define I2C_SR2_SMBHOST 0x00000040U
4753 #define I2C_SR2_DUALF 0x00000080U
4754 #define I2C_SR2_PEC 0x0000FF00U
4756 /******************* Bit definition for I2C_CCR register ********************/
4757 #define I2C_CCR_CCR 0x00000FFFU
4758 #define I2C_CCR_DUTY 0x00004000U
4759 #define I2C_CCR_FS 0x00008000U
4761 /****************** Bit definition for I2C_TRISE register *******************/
4762 #define I2C_TRISE_TRISE 0x0000003FU
4764 /****************** Bit definition for I2C_FLTR register *******************/
4765 #define I2C_FLTR_DNF 0x0000000FU
4766 #define I2C_FLTR_ANOFF 0x00000010U
4768 /******************************************************************************/
4769 /* */
4770 /* Independent WATCHDOG */
4771 /* */
4772 /******************************************************************************/
4773 /******************* Bit definition for IWDG_KR register ********************/
4774 #define IWDG_KR_KEY 0xFFFFU
4776 /******************* Bit definition for IWDG_PR register ********************/
4777 #define IWDG_PR_PR 0x07U
4778 #define IWDG_PR_PR_0 0x01U
4779 #define IWDG_PR_PR_1 0x02U
4780 #define IWDG_PR_PR_2 0x04U
4782 /******************* Bit definition for IWDG_RLR register *******************/
4783 #define IWDG_RLR_RL 0x0FFFU
4785 /******************* Bit definition for IWDG_SR register ********************/
4786 #define IWDG_SR_PVU 0x01U
4787 #define IWDG_SR_RVU 0x02U
4790 /******************************************************************************/
4791 /* */
4792 /* Power Control */
4793 /* */
4794 /******************************************************************************/
4795 /******************** Bit definition for PWR_CR register ********************/
4796 #define PWR_CR_LPDS 0x00000001U
4797 #define PWR_CR_PDDS 0x00000002U
4798 #define PWR_CR_CWUF 0x00000004U
4799 #define PWR_CR_CSBF 0x00000008U
4800 #define PWR_CR_PVDE 0x00000010U
4802 #define PWR_CR_PLS 0x000000E0U
4803 #define PWR_CR_PLS_0 0x00000020U
4804 #define PWR_CR_PLS_1 0x00000040U
4805 #define PWR_CR_PLS_2 0x00000080U
4808 #define PWR_CR_PLS_LEV0 0x00000000U
4809 #define PWR_CR_PLS_LEV1 0x00000020U
4810 #define PWR_CR_PLS_LEV2 0x00000040U
4811 #define PWR_CR_PLS_LEV3 0x00000060U
4812 #define PWR_CR_PLS_LEV4 0x00000080U
4813 #define PWR_CR_PLS_LEV5 0x000000A0U
4814 #define PWR_CR_PLS_LEV6 0x000000C0U
4815 #define PWR_CR_PLS_LEV7 0x000000E0U
4817 #define PWR_CR_DBP 0x00000100U
4818 #define PWR_CR_FPDS 0x00000200U
4819 #define PWR_CR_VOS 0x00004000U
4821 /* Legacy define */
4822 #define PWR_CR_PMODE PWR_CR_VOS
4823 
4824 /******************* Bit definition for PWR_CSR register ********************/
4825 #define PWR_CSR_WUF 0x00000001U
4826 #define PWR_CSR_SBF 0x00000002U
4827 #define PWR_CSR_PVDO 0x00000004U
4828 #define PWR_CSR_BRR 0x00000008U
4829 #define PWR_CSR_EWUP 0x00000100U
4830 #define PWR_CSR_BRE 0x00000200U
4831 #define PWR_CSR_VOSRDY 0x00004000U
4833 /* Legacy define */
4834 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
4835 
4836 /******************************************************************************/
4837 /* */
4838 /* Reset and Clock Control */
4839 /* */
4840 /******************************************************************************/
4841 /******************** Bit definition for RCC_CR register ********************/
4842 #define RCC_CR_HSION 0x00000001U
4843 #define RCC_CR_HSIRDY 0x00000002U
4844 
4845 #define RCC_CR_HSITRIM 0x000000F8U
4846 #define RCC_CR_HSITRIM_0 0x00000008U
4847 #define RCC_CR_HSITRIM_1 0x00000010U
4848 #define RCC_CR_HSITRIM_2 0x00000020U
4849 #define RCC_CR_HSITRIM_3 0x00000040U
4850 #define RCC_CR_HSITRIM_4 0x00000080U
4852 #define RCC_CR_HSICAL 0x0000FF00U
4853 #define RCC_CR_HSICAL_0 0x00000100U
4854 #define RCC_CR_HSICAL_1 0x00000200U
4855 #define RCC_CR_HSICAL_2 0x00000400U
4856 #define RCC_CR_HSICAL_3 0x00000800U
4857 #define RCC_CR_HSICAL_4 0x00001000U
4858 #define RCC_CR_HSICAL_5 0x00002000U
4859 #define RCC_CR_HSICAL_6 0x00004000U
4860 #define RCC_CR_HSICAL_7 0x00008000U
4862 #define RCC_CR_HSEON 0x00010000U
4863 #define RCC_CR_HSERDY 0x00020000U
4864 #define RCC_CR_HSEBYP 0x00040000U
4865 #define RCC_CR_CSSON 0x00080000U
4866 #define RCC_CR_PLLON 0x01000000U
4867 #define RCC_CR_PLLRDY 0x02000000U
4868 #define RCC_CR_PLLI2SON 0x04000000U
4869 #define RCC_CR_PLLI2SRDY 0x08000000U
4870 
4871 /******************** Bit definition for RCC_PLLCFGR register ***************/
4872 #define RCC_PLLCFGR_PLLM 0x0000003FU
4873 #define RCC_PLLCFGR_PLLM_0 0x00000001U
4874 #define RCC_PLLCFGR_PLLM_1 0x00000002U
4875 #define RCC_PLLCFGR_PLLM_2 0x00000004U
4876 #define RCC_PLLCFGR_PLLM_3 0x00000008U
4877 #define RCC_PLLCFGR_PLLM_4 0x00000010U
4878 #define RCC_PLLCFGR_PLLM_5 0x00000020U
4879 
4880 #define RCC_PLLCFGR_PLLN 0x00007FC0U
4881 #define RCC_PLLCFGR_PLLN_0 0x00000040U
4882 #define RCC_PLLCFGR_PLLN_1 0x00000080U
4883 #define RCC_PLLCFGR_PLLN_2 0x00000100U
4884 #define RCC_PLLCFGR_PLLN_3 0x00000200U
4885 #define RCC_PLLCFGR_PLLN_4 0x00000400U
4886 #define RCC_PLLCFGR_PLLN_5 0x00000800U
4887 #define RCC_PLLCFGR_PLLN_6 0x00001000U
4888 #define RCC_PLLCFGR_PLLN_7 0x00002000U
4889 #define RCC_PLLCFGR_PLLN_8 0x00004000U
4890 
4891 #define RCC_PLLCFGR_PLLP 0x00030000U
4892 #define RCC_PLLCFGR_PLLP_0 0x00010000U
4893 #define RCC_PLLCFGR_PLLP_1 0x00020000U
4894 
4895 #define RCC_PLLCFGR_PLLSRC 0x00400000U
4896 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
4897 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
4898 
4899 #define RCC_PLLCFGR_PLLQ 0x0F000000U
4900 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
4901 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
4902 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
4903 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
4904 
4905 /******************** Bit definition for RCC_CFGR register ******************/
4907 #define RCC_CFGR_SW 0x00000003U
4908 #define RCC_CFGR_SW_0 0x00000001U
4909 #define RCC_CFGR_SW_1 0x00000002U
4911 #define RCC_CFGR_SW_HSI 0x00000000U
4912 #define RCC_CFGR_SW_HSE 0x00000001U
4913 #define RCC_CFGR_SW_PLL 0x00000002U
4916 #define RCC_CFGR_SWS 0x0000000CU
4917 #define RCC_CFGR_SWS_0 0x00000004U
4918 #define RCC_CFGR_SWS_1 0x00000008U
4920 #define RCC_CFGR_SWS_HSI 0x00000000U
4921 #define RCC_CFGR_SWS_HSE 0x00000004U
4922 #define RCC_CFGR_SWS_PLL 0x00000008U
4925 #define RCC_CFGR_HPRE 0x000000F0U
4926 #define RCC_CFGR_HPRE_0 0x00000010U
4927 #define RCC_CFGR_HPRE_1 0x00000020U
4928 #define RCC_CFGR_HPRE_2 0x00000040U
4929 #define RCC_CFGR_HPRE_3 0x00000080U
4931 #define RCC_CFGR_HPRE_DIV1 0x00000000U
4932 #define RCC_CFGR_HPRE_DIV2 0x00000080U
4933 #define RCC_CFGR_HPRE_DIV4 0x00000090U
4934 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
4935 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
4936 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
4937 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
4938 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
4939 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
4942 #define RCC_CFGR_PPRE1 0x00001C00U
4943 #define RCC_CFGR_PPRE1_0 0x00000400U
4944 #define RCC_CFGR_PPRE1_1 0x00000800U
4945 #define RCC_CFGR_PPRE1_2 0x00001000U
4947 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
4948 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
4949 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
4950 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
4951 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
4954 #define RCC_CFGR_PPRE2 0x0000E000U
4955 #define RCC_CFGR_PPRE2_0 0x00002000U
4956 #define RCC_CFGR_PPRE2_1 0x00004000U
4957 #define RCC_CFGR_PPRE2_2 0x00008000U
4959 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
4960 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
4961 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
4962 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
4963 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
4966 #define RCC_CFGR_RTCPRE 0x001F0000U
4967 #define RCC_CFGR_RTCPRE_0 0x00010000U
4968 #define RCC_CFGR_RTCPRE_1 0x00020000U
4969 #define RCC_CFGR_RTCPRE_2 0x00040000U
4970 #define RCC_CFGR_RTCPRE_3 0x00080000U
4971 #define RCC_CFGR_RTCPRE_4 0x00100000U
4972 
4974 #define RCC_CFGR_MCO1 0x00600000U
4975 #define RCC_CFGR_MCO1_0 0x00200000U
4976 #define RCC_CFGR_MCO1_1 0x00400000U
4977 
4978 #define RCC_CFGR_I2SSRC 0x00800000U
4979 
4980 #define RCC_CFGR_MCO1PRE 0x07000000U
4981 #define RCC_CFGR_MCO1PRE_0 0x01000000U
4982 #define RCC_CFGR_MCO1PRE_1 0x02000000U
4983 #define RCC_CFGR_MCO1PRE_2 0x04000000U
4984 
4985 #define RCC_CFGR_MCO2PRE 0x38000000U
4986 #define RCC_CFGR_MCO2PRE_0 0x08000000U
4987 #define RCC_CFGR_MCO2PRE_1 0x10000000U
4988 #define RCC_CFGR_MCO2PRE_2 0x20000000U
4989 
4990 #define RCC_CFGR_MCO2 0xC0000000U
4991 #define RCC_CFGR_MCO2_0 0x40000000U
4992 #define RCC_CFGR_MCO2_1 0x80000000U
4993 
4994 /******************** Bit definition for RCC_CIR register *******************/
4995 #define RCC_CIR_LSIRDYF 0x00000001U
4996 #define RCC_CIR_LSERDYF 0x00000002U
4997 #define RCC_CIR_HSIRDYF 0x00000004U
4998 #define RCC_CIR_HSERDYF 0x00000008U
4999 #define RCC_CIR_PLLRDYF 0x00000010U
5000 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5001 
5002 #define RCC_CIR_CSSF 0x00000080U
5003 #define RCC_CIR_LSIRDYIE 0x00000100U
5004 #define RCC_CIR_LSERDYIE 0x00000200U
5005 #define RCC_CIR_HSIRDYIE 0x00000400U
5006 #define RCC_CIR_HSERDYIE 0x00000800U
5007 #define RCC_CIR_PLLRDYIE 0x00001000U
5008 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5009 
5010 #define RCC_CIR_LSIRDYC 0x00010000U
5011 #define RCC_CIR_LSERDYC 0x00020000U
5012 #define RCC_CIR_HSIRDYC 0x00040000U
5013 #define RCC_CIR_HSERDYC 0x00080000U
5014 #define RCC_CIR_PLLRDYC 0x00100000U
5015 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5016 
5017 #define RCC_CIR_CSSC 0x00800000U
5018 
5019 /******************** Bit definition for RCC_AHB1RSTR register **************/
5020 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5021 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5022 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5023 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5024 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5025 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5026 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5027 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5028 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5029 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5030 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5031 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5032 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5033 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5034 
5035 /******************** Bit definition for RCC_AHB2RSTR register **************/
5036 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5037 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5038 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5039 
5040 /******************** Bit definition for RCC_AHB3RSTR register **************/
5041 
5042 #define RCC_AHB3RSTR_FSMCRST 0x00000001U
5043 
5044 /******************** Bit definition for RCC_APB1RSTR register **************/
5045 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5046 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5047 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5048 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5049 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5050 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5051 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5052 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5053 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5054 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5055 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5056 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5057 #define RCC_APB1RSTR_USART2RST 0x00020000U
5058 #define RCC_APB1RSTR_USART3RST 0x00040000U
5059 #define RCC_APB1RSTR_UART4RST 0x00080000U
5060 #define RCC_APB1RSTR_UART5RST 0x00100000U
5061 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5062 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5063 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5064 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5065 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5066 #define RCC_APB1RSTR_PWRRST 0x10000000U
5067 #define RCC_APB1RSTR_DACRST 0x20000000U
5068 
5069 /******************** Bit definition for RCC_APB2RSTR register **************/
5070 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5071 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5072 #define RCC_APB2RSTR_USART1RST 0x00000010U
5073 #define RCC_APB2RSTR_USART6RST 0x00000020U
5074 #define RCC_APB2RSTR_ADCRST 0x00000100U
5075 #define RCC_APB2RSTR_SDIORST 0x00000800U
5076 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5077 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5078 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5079 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5080 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5081 
5082 /* Old SPI1RST bit definition, maintained for legacy purpose */
5083 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5084 
5085 /******************** Bit definition for RCC_AHB1ENR register ***************/
5086 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5087 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5088 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5089 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5090 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5091 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5092 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5093 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5094 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5095 #define RCC_AHB1ENR_CRCEN 0x00001000U
5096 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5097 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
5098 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5099 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5100 
5101 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5102 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5103 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5104 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5105 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5106 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5107 
5108 /******************** Bit definition for RCC_AHB2ENR register ***************/
5109 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5110 #define RCC_AHB2ENR_RNGEN 0x00000040U
5111 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5112 
5113 /******************** Bit definition for RCC_AHB3ENR register ***************/
5114 
5115 #define RCC_AHB3ENR_FSMCEN 0x00000001U
5116 
5117 /******************** Bit definition for RCC_APB1ENR register ***************/
5118 #define RCC_APB1ENR_TIM2EN 0x00000001U
5119 #define RCC_APB1ENR_TIM3EN 0x00000002U
5120 #define RCC_APB1ENR_TIM4EN 0x00000004U
5121 #define RCC_APB1ENR_TIM5EN 0x00000008U
5122 #define RCC_APB1ENR_TIM6EN 0x00000010U
5123 #define RCC_APB1ENR_TIM7EN 0x00000020U
5124 #define RCC_APB1ENR_TIM12EN 0x00000040U
5125 #define RCC_APB1ENR_TIM13EN 0x00000080U
5126 #define RCC_APB1ENR_TIM14EN 0x00000100U
5127 #define RCC_APB1ENR_WWDGEN 0x00000800U
5128 #define RCC_APB1ENR_SPI2EN 0x00004000U
5129 #define RCC_APB1ENR_SPI3EN 0x00008000U
5130 #define RCC_APB1ENR_USART2EN 0x00020000U
5131 #define RCC_APB1ENR_USART3EN 0x00040000U
5132 #define RCC_APB1ENR_UART4EN 0x00080000U
5133 #define RCC_APB1ENR_UART5EN 0x00100000U
5134 #define RCC_APB1ENR_I2C1EN 0x00200000U
5135 #define RCC_APB1ENR_I2C2EN 0x00400000U
5136 #define RCC_APB1ENR_I2C3EN 0x00800000U
5137 #define RCC_APB1ENR_CAN1EN 0x02000000U
5138 #define RCC_APB1ENR_CAN2EN 0x04000000U
5139 #define RCC_APB1ENR_PWREN 0x10000000U
5140 #define RCC_APB1ENR_DACEN 0x20000000U
5141 
5142 /******************** Bit definition for RCC_APB2ENR register ***************/
5143 #define RCC_APB2ENR_TIM1EN 0x00000001U
5144 #define RCC_APB2ENR_TIM8EN 0x00000002U
5145 #define RCC_APB2ENR_USART1EN 0x00000010U
5146 #define RCC_APB2ENR_USART6EN 0x00000020U
5147 #define RCC_APB2ENR_ADC1EN 0x00000100U
5148 #define RCC_APB2ENR_ADC2EN 0x00000200U
5149 #define RCC_APB2ENR_ADC3EN 0x00000400U
5150 #define RCC_APB2ENR_SDIOEN 0x00000800U
5151 #define RCC_APB2ENR_SPI1EN 0x00001000U
5152 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5153 #define RCC_APB2ENR_TIM9EN 0x00010000U
5154 #define RCC_APB2ENR_TIM10EN 0x00020000U
5155 #define RCC_APB2ENR_TIM11EN 0x00040000U
5156 #define RCC_APB2ENR_SPI5EN 0x00100000U
5157 #define RCC_APB2ENR_SPI6EN 0x00200000U
5158 
5159 /******************** Bit definition for RCC_AHB1LPENR register *************/
5160 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5161 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5162 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5163 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5164 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5165 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5166 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5167 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5168 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5169 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5170 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5171 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5172 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5173 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5174 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5175 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5176 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5177 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5178 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5179 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5180 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5181 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5182 
5183 /******************** Bit definition for RCC_AHB2LPENR register *************/
5184 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5185 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5186 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5187 
5188 /******************** Bit definition for RCC_AHB3LPENR register *************/
5189 
5190 #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
5191 
5192 /******************** Bit definition for RCC_APB1LPENR register *************/
5193 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5194 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5195 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5196 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5197 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5198 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5199 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5200 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5201 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5202 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5203 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5204 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5205 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5206 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5207 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5208 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5209 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5210 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5211 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5212 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5213 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5214 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5215 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5216 
5217 /******************** Bit definition for RCC_APB2LPENR register *************/
5218 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5219 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5220 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5221 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5222 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5223 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5224 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5225 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
5226 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5227 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5228 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5229 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5230 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5231 
5232 /******************** Bit definition for RCC_BDCR register ******************/
5233 #define RCC_BDCR_LSEON 0x00000001U
5234 #define RCC_BDCR_LSERDY 0x00000002U
5235 #define RCC_BDCR_LSEBYP 0x00000004U
5236 
5237 #define RCC_BDCR_RTCSEL 0x00000300U
5238 #define RCC_BDCR_RTCSEL_0 0x00000100U
5239 #define RCC_BDCR_RTCSEL_1 0x00000200U
5240 
5241 #define RCC_BDCR_RTCEN 0x00008000U
5242 #define RCC_BDCR_BDRST 0x00010000U
5243 
5244 /******************** Bit definition for RCC_CSR register *******************/
5245 #define RCC_CSR_LSION 0x00000001U
5246 #define RCC_CSR_LSIRDY 0x00000002U
5247 #define RCC_CSR_RMVF 0x01000000U
5248 #define RCC_CSR_BORRSTF 0x02000000U
5249 #define RCC_CSR_PADRSTF 0x04000000U
5250 #define RCC_CSR_PORRSTF 0x08000000U
5251 #define RCC_CSR_SFTRSTF 0x10000000U
5252 #define RCC_CSR_WDGRSTF 0x20000000U
5253 #define RCC_CSR_WWDGRSTF 0x40000000U
5254 #define RCC_CSR_LPWRRSTF 0x80000000U
5255 
5256 /******************** Bit definition for RCC_SSCGR register *****************/
5257 #define RCC_SSCGR_MODPER 0x00001FFFU
5258 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5259 #define RCC_SSCGR_SPREADSEL 0x40000000U
5260 #define RCC_SSCGR_SSCGEN 0x80000000U
5261 
5262 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5263 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5264 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5265 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5266 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5267 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5268 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5269 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5270 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5271 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5272 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5273 
5274 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5275 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5276 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5277 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5278 
5279 /******************************************************************************/
5280 /* */
5281 /* RNG */
5282 /* */
5283 /******************************************************************************/
5284 /******************** Bits definition for RNG_CR register *******************/
5285 #define RNG_CR_RNGEN 0x00000004U
5286 #define RNG_CR_IE 0x00000008U
5287 
5288 /******************** Bits definition for RNG_SR register *******************/
5289 #define RNG_SR_DRDY 0x00000001U
5290 #define RNG_SR_CECS 0x00000002U
5291 #define RNG_SR_SECS 0x00000004U
5292 #define RNG_SR_CEIS 0x00000020U
5293 #define RNG_SR_SEIS 0x00000040U
5294 
5295 /******************************************************************************/
5296 /* */
5297 /* Real-Time Clock (RTC) */
5298 /* */
5299 /******************************************************************************/
5300 /******************** Bits definition for RTC_TR register *******************/
5301 #define RTC_TR_PM 0x00400000U
5302 #define RTC_TR_HT 0x00300000U
5303 #define RTC_TR_HT_0 0x00100000U
5304 #define RTC_TR_HT_1 0x00200000U
5305 #define RTC_TR_HU 0x000F0000U
5306 #define RTC_TR_HU_0 0x00010000U
5307 #define RTC_TR_HU_1 0x00020000U
5308 #define RTC_TR_HU_2 0x00040000U
5309 #define RTC_TR_HU_3 0x00080000U
5310 #define RTC_TR_MNT 0x00007000U
5311 #define RTC_TR_MNT_0 0x00001000U
5312 #define RTC_TR_MNT_1 0x00002000U
5313 #define RTC_TR_MNT_2 0x00004000U
5314 #define RTC_TR_MNU 0x00000F00U
5315 #define RTC_TR_MNU_0 0x00000100U
5316 #define RTC_TR_MNU_1 0x00000200U
5317 #define RTC_TR_MNU_2 0x00000400U
5318 #define RTC_TR_MNU_3 0x00000800U
5319 #define RTC_TR_ST 0x00000070U
5320 #define RTC_TR_ST_0 0x00000010U
5321 #define RTC_TR_ST_1 0x00000020U
5322 #define RTC_TR_ST_2 0x00000040U
5323 #define RTC_TR_SU 0x0000000FU
5324 #define RTC_TR_SU_0 0x00000001U
5325 #define RTC_TR_SU_1 0x00000002U
5326 #define RTC_TR_SU_2 0x00000004U
5327 #define RTC_TR_SU_3 0x00000008U
5328 
5329 /******************** Bits definition for RTC_DR register *******************/
5330 #define RTC_DR_YT 0x00F00000U
5331 #define RTC_DR_YT_0 0x00100000U
5332 #define RTC_DR_YT_1 0x00200000U
5333 #define RTC_DR_YT_2 0x00400000U
5334 #define RTC_DR_YT_3 0x00800000U
5335 #define RTC_DR_YU 0x000F0000U
5336 #define RTC_DR_YU_0 0x00010000U
5337 #define RTC_DR_YU_1 0x00020000U
5338 #define RTC_DR_YU_2 0x00040000U
5339 #define RTC_DR_YU_3 0x00080000U
5340 #define RTC_DR_WDU 0x0000E000U
5341 #define RTC_DR_WDU_0 0x00002000U
5342 #define RTC_DR_WDU_1 0x00004000U
5343 #define RTC_DR_WDU_2 0x00008000U
5344 #define RTC_DR_MT 0x00001000U
5345 #define RTC_DR_MU 0x00000F00U
5346 #define RTC_DR_MU_0 0x00000100U
5347 #define RTC_DR_MU_1 0x00000200U
5348 #define RTC_DR_MU_2 0x00000400U
5349 #define RTC_DR_MU_3 0x00000800U
5350 #define RTC_DR_DT 0x00000030U
5351 #define RTC_DR_DT_0 0x00000010U
5352 #define RTC_DR_DT_1 0x00000020U
5353 #define RTC_DR_DU 0x0000000FU
5354 #define RTC_DR_DU_0 0x00000001U
5355 #define RTC_DR_DU_1 0x00000002U
5356 #define RTC_DR_DU_2 0x00000004U
5357 #define RTC_DR_DU_3 0x00000008U
5358 
5359 /******************** Bits definition for RTC_CR register *******************/
5360 #define RTC_CR_COE 0x00800000U
5361 #define RTC_CR_OSEL 0x00600000U
5362 #define RTC_CR_OSEL_0 0x00200000U
5363 #define RTC_CR_OSEL_1 0x00400000U
5364 #define RTC_CR_POL 0x00100000U
5365 #define RTC_CR_COSEL 0x00080000U
5366 #define RTC_CR_BCK 0x00040000U
5367 #define RTC_CR_SUB1H 0x00020000U
5368 #define RTC_CR_ADD1H 0x00010000U
5369 #define RTC_CR_TSIE 0x00008000U
5370 #define RTC_CR_WUTIE 0x00004000U
5371 #define RTC_CR_ALRBIE 0x00002000U
5372 #define RTC_CR_ALRAIE 0x00001000U
5373 #define RTC_CR_TSE 0x00000800U
5374 #define RTC_CR_WUTE 0x00000400U
5375 #define RTC_CR_ALRBE 0x00000200U
5376 #define RTC_CR_ALRAE 0x00000100U
5377 #define RTC_CR_DCE 0x00000080U
5378 #define RTC_CR_FMT 0x00000040U
5379 #define RTC_CR_BYPSHAD 0x00000020U
5380 #define RTC_CR_REFCKON 0x00000010U
5381 #define RTC_CR_TSEDGE 0x00000008U
5382 #define RTC_CR_WUCKSEL 0x00000007U
5383 #define RTC_CR_WUCKSEL_0 0x00000001U
5384 #define RTC_CR_WUCKSEL_1 0x00000002U
5385 #define RTC_CR_WUCKSEL_2 0x00000004U
5386 
5387 /******************** Bits definition for RTC_ISR register ******************/
5388 #define RTC_ISR_RECALPF 0x00010000U
5389 #define RTC_ISR_TAMP1F 0x00002000U
5390 #define RTC_ISR_TAMP2F 0x00004000U
5391 #define RTC_ISR_TSOVF 0x00001000U
5392 #define RTC_ISR_TSF 0x00000800U
5393 #define RTC_ISR_WUTF 0x00000400U
5394 #define RTC_ISR_ALRBF 0x00000200U
5395 #define RTC_ISR_ALRAF 0x00000100U
5396 #define RTC_ISR_INIT 0x00000080U
5397 #define RTC_ISR_INITF 0x00000040U
5398 #define RTC_ISR_RSF 0x00000020U
5399 #define RTC_ISR_INITS 0x00000010U
5400 #define RTC_ISR_SHPF 0x00000008U
5401 #define RTC_ISR_WUTWF 0x00000004U
5402 #define RTC_ISR_ALRBWF 0x00000002U
5403 #define RTC_ISR_ALRAWF 0x00000001U
5404 
5405 /******************** Bits definition for RTC_PRER register *****************/
5406 #define RTC_PRER_PREDIV_A 0x007F0000U
5407 #define RTC_PRER_PREDIV_S 0x00007FFFU
5408 
5409 /******************** Bits definition for RTC_WUTR register *****************/
5410 #define RTC_WUTR_WUT 0x0000FFFFU
5411 
5412 /******************** Bits definition for RTC_CALIBR register ***************/
5413 #define RTC_CALIBR_DCS 0x00000080U
5414 #define RTC_CALIBR_DC 0x0000001FU
5415 
5416 /******************** Bits definition for RTC_ALRMAR register ***************/
5417 #define RTC_ALRMAR_MSK4 0x80000000U
5418 #define RTC_ALRMAR_WDSEL 0x40000000U
5419 #define RTC_ALRMAR_DT 0x30000000U
5420 #define RTC_ALRMAR_DT_0 0x10000000U
5421 #define RTC_ALRMAR_DT_1 0x20000000U
5422 #define RTC_ALRMAR_DU 0x0F000000U
5423 #define RTC_ALRMAR_DU_0 0x01000000U
5424 #define RTC_ALRMAR_DU_1 0x02000000U
5425 #define RTC_ALRMAR_DU_2 0x04000000U
5426 #define RTC_ALRMAR_DU_3 0x08000000U
5427 #define RTC_ALRMAR_MSK3 0x00800000U
5428 #define RTC_ALRMAR_PM 0x00400000U
5429 #define RTC_ALRMAR_HT 0x00300000U
5430 #define RTC_ALRMAR_HT_0 0x00100000U
5431 #define RTC_ALRMAR_HT_1 0x00200000U
5432 #define RTC_ALRMAR_HU 0x000F0000U
5433 #define RTC_ALRMAR_HU_0 0x00010000U
5434 #define RTC_ALRMAR_HU_1 0x00020000U
5435 #define RTC_ALRMAR_HU_2 0x00040000U
5436 #define RTC_ALRMAR_HU_3 0x00080000U
5437 #define RTC_ALRMAR_MSK2 0x00008000U
5438 #define RTC_ALRMAR_MNT 0x00007000U
5439 #define RTC_ALRMAR_MNT_0 0x00001000U
5440 #define RTC_ALRMAR_MNT_1 0x00002000U
5441 #define RTC_ALRMAR_MNT_2 0x00004000U
5442 #define RTC_ALRMAR_MNU 0x00000F00U
5443 #define RTC_ALRMAR_MNU_0 0x00000100U
5444 #define RTC_ALRMAR_MNU_1 0x00000200U
5445 #define RTC_ALRMAR_MNU_2 0x00000400U
5446 #define RTC_ALRMAR_MNU_3 0x00000800U
5447 #define RTC_ALRMAR_MSK1 0x00000080U
5448 #define RTC_ALRMAR_ST 0x00000070U
5449 #define RTC_ALRMAR_ST_0 0x00000010U
5450 #define RTC_ALRMAR_ST_1 0x00000020U
5451 #define RTC_ALRMAR_ST_2 0x00000040U
5452 #define RTC_ALRMAR_SU 0x0000000FU
5453 #define RTC_ALRMAR_SU_0 0x00000001U
5454 #define RTC_ALRMAR_SU_1 0x00000002U
5455 #define RTC_ALRMAR_SU_2 0x00000004U
5456 #define RTC_ALRMAR_SU_3 0x00000008U
5457 
5458 /******************** Bits definition for RTC_ALRMBR register ***************/
5459 #define RTC_ALRMBR_MSK4 0x80000000U
5460 #define RTC_ALRMBR_WDSEL 0x40000000U
5461 #define RTC_ALRMBR_DT 0x30000000U
5462 #define RTC_ALRMBR_DT_0 0x10000000U
5463 #define RTC_ALRMBR_DT_1 0x20000000U
5464 #define RTC_ALRMBR_DU 0x0F000000U
5465 #define RTC_ALRMBR_DU_0 0x01000000U
5466 #define RTC_ALRMBR_DU_1 0x02000000U
5467 #define RTC_ALRMBR_DU_2 0x04000000U
5468 #define RTC_ALRMBR_DU_3 0x08000000U
5469 #define RTC_ALRMBR_MSK3 0x00800000U
5470 #define RTC_ALRMBR_PM 0x00400000U
5471 #define RTC_ALRMBR_HT 0x00300000U
5472 #define RTC_ALRMBR_HT_0 0x00100000U
5473 #define RTC_ALRMBR_HT_1 0x00200000U
5474 #define RTC_ALRMBR_HU 0x000F0000U
5475 #define RTC_ALRMBR_HU_0 0x00010000U
5476 #define RTC_ALRMBR_HU_1 0x00020000U
5477 #define RTC_ALRMBR_HU_2 0x00040000U
5478 #define RTC_ALRMBR_HU_3 0x00080000U
5479 #define RTC_ALRMBR_MSK2 0x00008000U
5480 #define RTC_ALRMBR_MNT 0x00007000U
5481 #define RTC_ALRMBR_MNT_0 0x00001000U
5482 #define RTC_ALRMBR_MNT_1 0x00002000U
5483 #define RTC_ALRMBR_MNT_2 0x00004000U
5484 #define RTC_ALRMBR_MNU 0x00000F00U
5485 #define RTC_ALRMBR_MNU_0 0x00000100U
5486 #define RTC_ALRMBR_MNU_1 0x00000200U
5487 #define RTC_ALRMBR_MNU_2 0x00000400U
5488 #define RTC_ALRMBR_MNU_3 0x00000800U
5489 #define RTC_ALRMBR_MSK1 0x00000080U
5490 #define RTC_ALRMBR_ST 0x00000070U
5491 #define RTC_ALRMBR_ST_0 0x00000010U
5492 #define RTC_ALRMBR_ST_1 0x00000020U
5493 #define RTC_ALRMBR_ST_2 0x00000040U
5494 #define RTC_ALRMBR_SU 0x0000000FU
5495 #define RTC_ALRMBR_SU_0 0x00000001U
5496 #define RTC_ALRMBR_SU_1 0x00000002U
5497 #define RTC_ALRMBR_SU_2 0x00000004U
5498 #define RTC_ALRMBR_SU_3 0x00000008U
5499 
5500 /******************** Bits definition for RTC_WPR register ******************/
5501 #define RTC_WPR_KEY 0x000000FFU
5502 
5503 /******************** Bits definition for RTC_SSR register ******************/
5504 #define RTC_SSR_SS 0x0000FFFFU
5505 
5506 /******************** Bits definition for RTC_SHIFTR register ***************/
5507 #define RTC_SHIFTR_SUBFS 0x00007FFFU
5508 #define RTC_SHIFTR_ADD1S 0x80000000U
5509 
5510 /******************** Bits definition for RTC_TSTR register *****************/
5511 #define RTC_TSTR_PM 0x00400000U
5512 #define RTC_TSTR_HT 0x00300000U
5513 #define RTC_TSTR_HT_0 0x00100000U
5514 #define RTC_TSTR_HT_1 0x00200000U
5515 #define RTC_TSTR_HU 0x000F0000U
5516 #define RTC_TSTR_HU_0 0x00010000U
5517 #define RTC_TSTR_HU_1 0x00020000U
5518 #define RTC_TSTR_HU_2 0x00040000U
5519 #define RTC_TSTR_HU_3 0x00080000U
5520 #define RTC_TSTR_MNT 0x00007000U
5521 #define RTC_TSTR_MNT_0 0x00001000U
5522 #define RTC_TSTR_MNT_1 0x00002000U
5523 #define RTC_TSTR_MNT_2 0x00004000U
5524 #define RTC_TSTR_MNU 0x00000F00U
5525 #define RTC_TSTR_MNU_0 0x00000100U
5526 #define RTC_TSTR_MNU_1 0x00000200U
5527 #define RTC_TSTR_MNU_2 0x00000400U
5528 #define RTC_TSTR_MNU_3 0x00000800U
5529 #define RTC_TSTR_ST 0x00000070U
5530 #define RTC_TSTR_ST_0 0x00000010U
5531 #define RTC_TSTR_ST_1 0x00000020U
5532 #define RTC_TSTR_ST_2 0x00000040U
5533 #define RTC_TSTR_SU 0x0000000FU
5534 #define RTC_TSTR_SU_0 0x00000001U
5535 #define RTC_TSTR_SU_1 0x00000002U
5536 #define RTC_TSTR_SU_2 0x00000004U
5537 #define RTC_TSTR_SU_3 0x00000008U
5538 
5539 /******************** Bits definition for RTC_TSDR register *****************/
5540 #define RTC_TSDR_WDU 0x0000E000U
5541 #define RTC_TSDR_WDU_0 0x00002000U
5542 #define RTC_TSDR_WDU_1 0x00004000U
5543 #define RTC_TSDR_WDU_2 0x00008000U
5544 #define RTC_TSDR_MT 0x00001000U
5545 #define RTC_TSDR_MU 0x00000F00U
5546 #define RTC_TSDR_MU_0 0x00000100U
5547 #define RTC_TSDR_MU_1 0x00000200U
5548 #define RTC_TSDR_MU_2 0x00000400U
5549 #define RTC_TSDR_MU_3 0x00000800U
5550 #define RTC_TSDR_DT 0x00000030U
5551 #define RTC_TSDR_DT_0 0x00000010U
5552 #define RTC_TSDR_DT_1 0x00000020U
5553 #define RTC_TSDR_DU 0x0000000FU
5554 #define RTC_TSDR_DU_0 0x00000001U
5555 #define RTC_TSDR_DU_1 0x00000002U
5556 #define RTC_TSDR_DU_2 0x00000004U
5557 #define RTC_TSDR_DU_3 0x00000008U
5558 
5559 /******************** Bits definition for RTC_TSSSR register ****************/
5560 #define RTC_TSSSR_SS 0x0000FFFFU
5561 
5562 /******************** Bits definition for RTC_CAL register *****************/
5563 #define RTC_CALR_CALP 0x00008000U
5564 #define RTC_CALR_CALW8 0x00004000U
5565 #define RTC_CALR_CALW16 0x00002000U
5566 #define RTC_CALR_CALM 0x000001FFU
5567 #define RTC_CALR_CALM_0 0x00000001U
5568 #define RTC_CALR_CALM_1 0x00000002U
5569 #define RTC_CALR_CALM_2 0x00000004U
5570 #define RTC_CALR_CALM_3 0x00000008U
5571 #define RTC_CALR_CALM_4 0x00000010U
5572 #define RTC_CALR_CALM_5 0x00000020U
5573 #define RTC_CALR_CALM_6 0x00000040U
5574 #define RTC_CALR_CALM_7 0x00000080U
5575 #define RTC_CALR_CALM_8 0x00000100U
5576 
5577 /******************** Bits definition for RTC_TAFCR register ****************/
5578 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
5579 #define RTC_TAFCR_TSINSEL 0x00020000U
5580 #define RTC_TAFCR_TAMPINSEL 0x00010000U
5581 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
5582 #define RTC_TAFCR_TAMPPRCH 0x00006000U
5583 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
5584 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
5585 #define RTC_TAFCR_TAMPFLT 0x00001800U
5586 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
5587 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
5588 #define RTC_TAFCR_TAMPFREQ 0x00000700U
5589 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
5590 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
5591 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
5592 #define RTC_TAFCR_TAMPTS 0x00000080U
5593 #define RTC_TAFCR_TAMP2TRG 0x00000010U
5594 #define RTC_TAFCR_TAMP2E 0x00000008U
5595 #define RTC_TAFCR_TAMPIE 0x00000004U
5596 #define RTC_TAFCR_TAMP1TRG 0x00000002U
5597 #define RTC_TAFCR_TAMP1E 0x00000001U
5598 
5599 /******************** Bits definition for RTC_ALRMASSR register *************/
5600 #define RTC_ALRMASSR_MASKSS 0x0F000000U
5601 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
5602 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
5603 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
5604 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
5605 #define RTC_ALRMASSR_SS 0x00007FFFU
5606 
5607 /******************** Bits definition for RTC_ALRMBSSR register *************/
5608 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
5609 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
5610 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
5611 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
5612 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
5613 #define RTC_ALRMBSSR_SS 0x00007FFFU
5614 
5615 /******************** Bits definition for RTC_BKP0R register ****************/
5616 #define RTC_BKP0R 0xFFFFFFFFU
5617 
5618 /******************** Bits definition for RTC_BKP1R register ****************/
5619 #define RTC_BKP1R 0xFFFFFFFFU
5620 
5621 /******************** Bits definition for RTC_BKP2R register ****************/
5622 #define RTC_BKP2R 0xFFFFFFFFU
5623 
5624 /******************** Bits definition for RTC_BKP3R register ****************/
5625 #define RTC_BKP3R 0xFFFFFFFFU
5626 
5627 /******************** Bits definition for RTC_BKP4R register ****************/
5628 #define RTC_BKP4R 0xFFFFFFFFU
5629 
5630 /******************** Bits definition for RTC_BKP5R register ****************/
5631 #define RTC_BKP5R 0xFFFFFFFFU
5632 
5633 /******************** Bits definition for RTC_BKP6R register ****************/
5634 #define RTC_BKP6R 0xFFFFFFFFU
5635 
5636 /******************** Bits definition for RTC_BKP7R register ****************/
5637 #define RTC_BKP7R 0xFFFFFFFFU
5638 
5639 /******************** Bits definition for RTC_BKP8R register ****************/
5640 #define RTC_BKP8R 0xFFFFFFFFU
5641 
5642 /******************** Bits definition for RTC_BKP9R register ****************/
5643 #define RTC_BKP9R 0xFFFFFFFFU
5644 
5645 /******************** Bits definition for RTC_BKP10R register ***************/
5646 #define RTC_BKP10R 0xFFFFFFFFU
5647 
5648 /******************** Bits definition for RTC_BKP11R register ***************/
5649 #define RTC_BKP11R 0xFFFFFFFFU
5650 
5651 /******************** Bits definition for RTC_BKP12R register ***************/
5652 #define RTC_BKP12R 0xFFFFFFFFU
5653 
5654 /******************** Bits definition for RTC_BKP13R register ***************/
5655 #define RTC_BKP13R 0xFFFFFFFFU
5656 
5657 /******************** Bits definition for RTC_BKP14R register ***************/
5658 #define RTC_BKP14R 0xFFFFFFFFU
5659 
5660 /******************** Bits definition for RTC_BKP15R register ***************/
5661 #define RTC_BKP15R 0xFFFFFFFFU
5662 
5663 /******************** Bits definition for RTC_BKP16R register ***************/
5664 #define RTC_BKP16R 0xFFFFFFFFU
5665 
5666 /******************** Bits definition for RTC_BKP17R register ***************/
5667 #define RTC_BKP17R 0xFFFFFFFFU
5668 
5669 /******************** Bits definition for RTC_BKP18R register ***************/
5670 #define RTC_BKP18R 0xFFFFFFFFU
5671 
5672 /******************** Bits definition for RTC_BKP19R register ***************/
5673 #define RTC_BKP19R 0xFFFFFFFFU
5674 
5675 
5676 
5677 /******************************************************************************/
5678 /* */
5679 /* SD host Interface */
5680 /* */
5681 /******************************************************************************/
5682 /****************** Bit definition for SDIO_POWER register ******************/
5683 #define SDIO_POWER_PWRCTRL 0x03U
5684 #define SDIO_POWER_PWRCTRL_0 0x01U
5685 #define SDIO_POWER_PWRCTRL_1 0x02U
5687 /****************** Bit definition for SDIO_CLKCR register ******************/
5688 #define SDIO_CLKCR_CLKDIV 0x00FFU
5689 #define SDIO_CLKCR_CLKEN 0x0100U
5690 #define SDIO_CLKCR_PWRSAV 0x0200U
5691 #define SDIO_CLKCR_BYPASS 0x0400U
5693 #define SDIO_CLKCR_WIDBUS 0x1800U
5694 #define SDIO_CLKCR_WIDBUS_0 0x0800U
5695 #define SDIO_CLKCR_WIDBUS_1 0x1000U
5697 #define SDIO_CLKCR_NEGEDGE 0x2000U
5698 #define SDIO_CLKCR_HWFC_EN 0x4000U
5700 /******************* Bit definition for SDIO_ARG register *******************/
5701 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
5703 /******************* Bit definition for SDIO_CMD register *******************/
5704 #define SDIO_CMD_CMDINDEX 0x003FU
5706 #define SDIO_CMD_WAITRESP 0x00C0U
5707 #define SDIO_CMD_WAITRESP_0 0x0040U
5708 #define SDIO_CMD_WAITRESP_1 0x0080U
5710 #define SDIO_CMD_WAITINT 0x0100U
5711 #define SDIO_CMD_WAITPEND 0x0200U
5712 #define SDIO_CMD_CPSMEN 0x0400U
5713 #define SDIO_CMD_SDIOSUSPEND 0x0800U
5714 #define SDIO_CMD_ENCMDCOMPL 0x1000U
5715 #define SDIO_CMD_NIEN 0x2000U
5716 #define SDIO_CMD_CEATACMD 0x4000U
5718 /***************** Bit definition for SDIO_RESPCMD register *****************/
5719 #define SDIO_RESPCMD_RESPCMD 0x3FU
5721 /****************** Bit definition for SDIO_RESP0 register ******************/
5722 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
5724 /****************** Bit definition for SDIO_RESP1 register ******************/
5725 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
5727 /****************** Bit definition for SDIO_RESP2 register ******************/
5728 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
5730 /****************** Bit definition for SDIO_RESP3 register ******************/
5731 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
5733 /****************** Bit definition for SDIO_RESP4 register ******************/
5734 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
5736 /****************** Bit definition for SDIO_DTIMER register *****************/
5737 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
5739 /****************** Bit definition for SDIO_DLEN register *******************/
5740 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
5742 /****************** Bit definition for SDIO_DCTRL register ******************/
5743 #define SDIO_DCTRL_DTEN 0x0001U
5744 #define SDIO_DCTRL_DTDIR 0x0002U
5745 #define SDIO_DCTRL_DTMODE 0x0004U
5746 #define SDIO_DCTRL_DMAEN 0x0008U
5748 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
5749 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
5750 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
5751 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
5752 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
5754 #define SDIO_DCTRL_RWSTART 0x0100U
5755 #define SDIO_DCTRL_RWSTOP 0x0200U
5756 #define SDIO_DCTRL_RWMOD 0x0400U
5757 #define SDIO_DCTRL_SDIOEN 0x0800U
5759 /****************** Bit definition for SDIO_DCOUNT register *****************/
5760 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
5762 /****************** Bit definition for SDIO_STA register ********************/
5763 #define SDIO_STA_CCRCFAIL 0x00000001U
5764 #define SDIO_STA_DCRCFAIL 0x00000002U
5765 #define SDIO_STA_CTIMEOUT 0x00000004U
5766 #define SDIO_STA_DTIMEOUT 0x00000008U
5767 #define SDIO_STA_TXUNDERR 0x00000010U
5768 #define SDIO_STA_RXOVERR 0x00000020U
5769 #define SDIO_STA_CMDREND 0x00000040U
5770 #define SDIO_STA_CMDSENT 0x00000080U
5771 #define SDIO_STA_DATAEND 0x00000100U
5772 #define SDIO_STA_STBITERR 0x00000200U
5773 #define SDIO_STA_DBCKEND 0x00000400U
5774 #define SDIO_STA_CMDACT 0x00000800U
5775 #define SDIO_STA_TXACT 0x00001000U
5776 #define SDIO_STA_RXACT 0x00002000U
5777 #define SDIO_STA_TXFIFOHE 0x00004000U
5778 #define SDIO_STA_RXFIFOHF 0x00008000U
5779 #define SDIO_STA_TXFIFOF 0x00010000U
5780 #define SDIO_STA_RXFIFOF 0x00020000U
5781 #define SDIO_STA_TXFIFOE 0x00040000U
5782 #define SDIO_STA_RXFIFOE 0x00080000U
5783 #define SDIO_STA_TXDAVL 0x00100000U
5784 #define SDIO_STA_RXDAVL 0x00200000U
5785 #define SDIO_STA_SDIOIT 0x00400000U
5786 #define SDIO_STA_CEATAEND 0x00800000U
5788 /******************* Bit definition for SDIO_ICR register *******************/
5789 #define SDIO_ICR_CCRCFAILC 0x00000001U
5790 #define SDIO_ICR_DCRCFAILC 0x00000002U
5791 #define SDIO_ICR_CTIMEOUTC 0x00000004U
5792 #define SDIO_ICR_DTIMEOUTC 0x00000008U
5793 #define SDIO_ICR_TXUNDERRC 0x00000010U
5794 #define SDIO_ICR_RXOVERRC 0x00000020U
5795 #define SDIO_ICR_CMDRENDC 0x00000040U
5796 #define SDIO_ICR_CMDSENTC 0x00000080U
5797 #define SDIO_ICR_DATAENDC 0x00000100U
5798 #define SDIO_ICR_STBITERRC 0x00000200U
5799 #define SDIO_ICR_DBCKENDC 0x00000400U
5800 #define SDIO_ICR_SDIOITC 0x00400000U
5801 #define SDIO_ICR_CEATAENDC 0x00800000U
5803 /****************** Bit definition for SDIO_MASK register *******************/
5804 #define SDIO_MASK_CCRCFAILIE 0x00000001U
5805 #define SDIO_MASK_DCRCFAILIE 0x00000002U
5806 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
5807 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
5808 #define SDIO_MASK_TXUNDERRIE 0x00000010U
5809 #define SDIO_MASK_RXOVERRIE 0x00000020U
5810 #define SDIO_MASK_CMDRENDIE 0x00000040U
5811 #define SDIO_MASK_CMDSENTIE 0x00000080U
5812 #define SDIO_MASK_DATAENDIE 0x00000100U
5813 #define SDIO_MASK_STBITERRIE 0x00000200U
5814 #define SDIO_MASK_DBCKENDIE 0x00000400U
5815 #define SDIO_MASK_CMDACTIE 0x00000800U
5816 #define SDIO_MASK_TXACTIE 0x00001000U
5817 #define SDIO_MASK_RXACTIE 0x00002000U
5818 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
5819 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
5820 #define SDIO_MASK_TXFIFOFIE 0x00010000U
5821 #define SDIO_MASK_RXFIFOFIE 0x00020000U
5822 #define SDIO_MASK_TXFIFOEIE 0x00040000U
5823 #define SDIO_MASK_RXFIFOEIE 0x00080000U
5824 #define SDIO_MASK_TXDAVLIE 0x00100000U
5825 #define SDIO_MASK_RXDAVLIE 0x00200000U
5826 #define SDIO_MASK_SDIOITIE 0x00400000U
5827 #define SDIO_MASK_CEATAENDIE 0x00800000U
5829 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5830 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
5832 /****************** Bit definition for SDIO_FIFO register *******************/
5833 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
5835 /******************************************************************************/
5836 /* */
5837 /* Serial Peripheral Interface */
5838 /* */
5839 /******************************************************************************/
5840 /******************* Bit definition for SPI_CR1 register ********************/
5841 #define SPI_CR1_CPHA 0x00000001U
5842 #define SPI_CR1_CPOL 0x00000002U
5843 #define SPI_CR1_MSTR 0x00000004U
5845 #define SPI_CR1_BR 0x00000038U
5846 #define SPI_CR1_BR_0 0x00000008U
5847 #define SPI_CR1_BR_1 0x00000010U
5848 #define SPI_CR1_BR_2 0x00000020U
5850 #define SPI_CR1_SPE 0x00000040U
5851 #define SPI_CR1_LSBFIRST 0x00000080U
5852 #define SPI_CR1_SSI 0x00000100U
5853 #define SPI_CR1_SSM 0x00000200U
5854 #define SPI_CR1_RXONLY 0x00000400U
5855 #define SPI_CR1_DFF 0x00000800U
5856 #define SPI_CR1_CRCNEXT 0x00001000U
5857 #define SPI_CR1_CRCEN 0x00002000U
5858 #define SPI_CR1_BIDIOE 0x00004000U
5859 #define SPI_CR1_BIDIMODE 0x00008000U
5861 /******************* Bit definition for SPI_CR2 register ********************/
5862 #define SPI_CR2_RXDMAEN 0x00000001U
5863 #define SPI_CR2_TXDMAEN 0x00000002U
5864 #define SPI_CR2_SSOE 0x00000004U
5865 #define SPI_CR2_FRF 0x00000010U
5866 #define SPI_CR2_ERRIE 0x00000020U
5867 #define SPI_CR2_RXNEIE 0x00000040U
5868 #define SPI_CR2_TXEIE 0x00000080U
5870 /******************** Bit definition for SPI_SR register ********************/
5871 #define SPI_SR_RXNE 0x00000001U
5872 #define SPI_SR_TXE 0x00000002U
5873 #define SPI_SR_CHSIDE 0x00000004U
5874 #define SPI_SR_UDR 0x00000008U
5875 #define SPI_SR_CRCERR 0x00000010U
5876 #define SPI_SR_MODF 0x00000020U
5877 #define SPI_SR_OVR 0x00000040U
5878 #define SPI_SR_BSY 0x00000080U
5879 #define SPI_SR_FRE 0x00000100U
5881 /******************** Bit definition for SPI_DR register ********************/
5882 #define SPI_DR_DR 0x0000FFFFU
5884 /******************* Bit definition for SPI_CRCPR register ******************/
5885 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
5887 /****************** Bit definition for SPI_RXCRCR register ******************/
5888 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
5890 /****************** Bit definition for SPI_TXCRCR register ******************/
5891 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
5893 /****************** Bit definition for SPI_I2SCFGR register *****************/
5894 #define SPI_I2SCFGR_CHLEN 0x00000001U
5896 #define SPI_I2SCFGR_DATLEN 0x00000006U
5897 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
5898 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
5900 #define SPI_I2SCFGR_CKPOL 0x00000008U
5902 #define SPI_I2SCFGR_I2SSTD 0x00000030U
5903 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
5904 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
5906 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
5908 #define SPI_I2SCFGR_I2SCFG 0x00000300U
5909 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
5910 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
5912 #define SPI_I2SCFGR_I2SE 0x00000400U
5913 #define SPI_I2SCFGR_I2SMOD 0x00000800U
5915 /****************** Bit definition for SPI_I2SPR register *******************/
5916 #define SPI_I2SPR_I2SDIV 0x000000FFU
5917 #define SPI_I2SPR_ODD 0x00000100U
5918 #define SPI_I2SPR_MCKOE 0x00000200U
5920 /******************************************************************************/
5921 /* */
5922 /* SYSCFG */
5923 /* */
5924 /******************************************************************************/
5925 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
5926 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
5927 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
5928 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
5929 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
5930 
5931 /****************** Bit definition for SYSCFG_PMC register ******************/
5932 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
5933 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
5934 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
5935 
5936 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5937 #define SYSCFG_EXTICR1_EXTI0 0x000FU
5938 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
5939 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
5940 #define SYSCFG_EXTICR1_EXTI3 0xF000U
5944 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
5945 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
5946 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
5947 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
5948 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
5949 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
5950 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
5951 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
5952 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
5957 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
5958 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
5959 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
5960 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
5961 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
5962 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
5963 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
5964 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
5965 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
5970 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
5971 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
5972 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
5973 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
5974 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
5975 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
5976 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
5977 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
5978 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
5983 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
5984 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
5985 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
5986 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
5987 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
5988 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
5989 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
5990 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
5991 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
5993 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5994 #define SYSCFG_EXTICR2_EXTI4 0x000FU
5995 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
5996 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
5997 #define SYSCFG_EXTICR2_EXTI7 0xF000U
6001 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
6002 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
6003 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
6004 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
6005 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
6006 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
6007 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
6008 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
6009 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
6014 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
6015 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
6016 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
6017 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
6018 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
6019 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
6020 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
6021 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
6022 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
6027 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
6028 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
6029 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
6030 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
6031 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
6032 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
6033 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
6034 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
6035 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
6040 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
6041 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
6042 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
6043 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
6044 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
6045 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
6046 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
6047 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
6048 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
6051 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6052 #define SYSCFG_EXTICR3_EXTI8 0x000FU
6053 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
6054 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
6055 #define SYSCFG_EXTICR3_EXTI11 0xF000U
6060 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
6061 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
6062 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
6063 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
6064 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
6065 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
6066 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
6067 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
6068 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
6073 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
6074 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
6075 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
6076 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
6077 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
6078 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
6079 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
6080 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
6081 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
6086 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
6087 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
6088 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
6089 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
6090 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
6091 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
6092 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
6093 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
6094 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
6099 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
6100 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
6101 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
6102 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
6103 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
6104 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
6105 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
6106 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
6107 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
6109 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6110 #define SYSCFG_EXTICR4_EXTI12 0x000FU
6111 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
6112 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
6113 #define SYSCFG_EXTICR4_EXTI15 0xF000U
6117 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
6118 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
6119 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
6120 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
6121 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
6122 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
6123 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
6124 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
6129 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
6130 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
6131 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
6132 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
6133 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
6134 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
6135 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
6136 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
6141 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
6142 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
6143 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
6144 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
6145 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
6146 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
6147 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
6148 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
6153 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
6154 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
6155 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
6156 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
6157 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
6158 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
6159 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
6160 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
6162 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6163 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
6164 #define SYSCFG_CMPCR_READY 0x00000100U
6166 /******************************************************************************/
6167 /* */
6168 /* TIM */
6169 /* */
6170 /******************************************************************************/
6171 /******************* Bit definition for TIM_CR1 register ********************/
6172 #define TIM_CR1_CEN 0x0001U
6173 #define TIM_CR1_UDIS 0x0002U
6174 #define TIM_CR1_URS 0x0004U
6175 #define TIM_CR1_OPM 0x0008U
6176 #define TIM_CR1_DIR 0x0010U
6178 #define TIM_CR1_CMS 0x0060U
6179 #define TIM_CR1_CMS_0 0x0020U
6180 #define TIM_CR1_CMS_1 0x0040U
6182 #define TIM_CR1_ARPE 0x0080U
6184 #define TIM_CR1_CKD 0x0300U
6185 #define TIM_CR1_CKD_0 0x0100U
6186 #define TIM_CR1_CKD_1 0x0200U
6188 /******************* Bit definition for TIM_CR2 register ********************/
6189 #define TIM_CR2_CCPC 0x0001U
6190 #define TIM_CR2_CCUS 0x0004U
6191 #define TIM_CR2_CCDS 0x0008U
6193 #define TIM_CR2_MMS 0x0070U
6194 #define TIM_CR2_MMS_0 0x0010U
6195 #define TIM_CR2_MMS_1 0x0020U
6196 #define TIM_CR2_MMS_2 0x0040U
6198 #define TIM_CR2_TI1S 0x0080U
6199 #define TIM_CR2_OIS1 0x0100U
6200 #define TIM_CR2_OIS1N 0x0200U
6201 #define TIM_CR2_OIS2 0x0400U
6202 #define TIM_CR2_OIS2N 0x0800U
6203 #define TIM_CR2_OIS3 0x1000U
6204 #define TIM_CR2_OIS3N 0x2000U
6205 #define TIM_CR2_OIS4 0x4000U
6207 /******************* Bit definition for TIM_SMCR register *******************/
6208 #define TIM_SMCR_SMS 0x0007U
6209 #define TIM_SMCR_SMS_0 0x0001U
6210 #define TIM_SMCR_SMS_1 0x0002U
6211 #define TIM_SMCR_SMS_2 0x0004U
6213 #define TIM_SMCR_TS 0x0070U
6214 #define TIM_SMCR_TS_0 0x0010U
6215 #define TIM_SMCR_TS_1 0x0020U
6216 #define TIM_SMCR_TS_2 0x0040U
6218 #define TIM_SMCR_MSM 0x0080U
6220 #define TIM_SMCR_ETF 0x0F00U
6221 #define TIM_SMCR_ETF_0 0x0100U
6222 #define TIM_SMCR_ETF_1 0x0200U
6223 #define TIM_SMCR_ETF_2 0x0400U
6224 #define TIM_SMCR_ETF_3 0x0800U
6226 #define TIM_SMCR_ETPS 0x3000U
6227 #define TIM_SMCR_ETPS_0 0x1000U
6228 #define TIM_SMCR_ETPS_1 0x2000U
6230 #define TIM_SMCR_ECE 0x4000U
6231 #define TIM_SMCR_ETP 0x8000U
6233 /******************* Bit definition for TIM_DIER register *******************/
6234 #define TIM_DIER_UIE 0x0001U
6235 #define TIM_DIER_CC1IE 0x0002U
6236 #define TIM_DIER_CC2IE 0x0004U
6237 #define TIM_DIER_CC3IE 0x0008U
6238 #define TIM_DIER_CC4IE 0x0010U
6239 #define TIM_DIER_COMIE 0x0020U
6240 #define TIM_DIER_TIE 0x0040U
6241 #define TIM_DIER_BIE 0x0080U
6242 #define TIM_DIER_UDE 0x0100U
6243 #define TIM_DIER_CC1DE 0x0200U
6244 #define TIM_DIER_CC2DE 0x0400U
6245 #define TIM_DIER_CC3DE 0x0800U
6246 #define TIM_DIER_CC4DE 0x1000U
6247 #define TIM_DIER_COMDE 0x2000U
6248 #define TIM_DIER_TDE 0x4000U
6250 /******************** Bit definition for TIM_SR register ********************/
6251 #define TIM_SR_UIF 0x0001U
6252 #define TIM_SR_CC1IF 0x0002U
6253 #define TIM_SR_CC2IF 0x0004U
6254 #define TIM_SR_CC3IF 0x0008U
6255 #define TIM_SR_CC4IF 0x0010U
6256 #define TIM_SR_COMIF 0x0020U
6257 #define TIM_SR_TIF 0x0040U
6258 #define TIM_SR_BIF 0x0080U
6259 #define TIM_SR_CC1OF 0x0200U
6260 #define TIM_SR_CC2OF 0x0400U
6261 #define TIM_SR_CC3OF 0x0800U
6262 #define TIM_SR_CC4OF 0x1000U
6264 /******************* Bit definition for TIM_EGR register ********************/
6265 #define TIM_EGR_UG 0x01U
6266 #define TIM_EGR_CC1G 0x02U
6267 #define TIM_EGR_CC2G 0x04U
6268 #define TIM_EGR_CC3G 0x08U
6269 #define TIM_EGR_CC4G 0x10U
6270 #define TIM_EGR_COMG 0x20U
6271 #define TIM_EGR_TG 0x40U
6272 #define TIM_EGR_BG 0x80U
6274 /****************** Bit definition for TIM_CCMR1 register *******************/
6275 #define TIM_CCMR1_CC1S 0x0003U
6276 #define TIM_CCMR1_CC1S_0 0x0001U
6277 #define TIM_CCMR1_CC1S_1 0x0002U
6279 #define TIM_CCMR1_OC1FE 0x0004U
6280 #define TIM_CCMR1_OC1PE 0x0008U
6282 #define TIM_CCMR1_OC1M 0x0070U
6283 #define TIM_CCMR1_OC1M_0 0x0010U
6284 #define TIM_CCMR1_OC1M_1 0x0020U
6285 #define TIM_CCMR1_OC1M_2 0x0040U
6287 #define TIM_CCMR1_OC1CE 0x0080U
6289 #define TIM_CCMR1_CC2S 0x0300U
6290 #define TIM_CCMR1_CC2S_0 0x0100U
6291 #define TIM_CCMR1_CC2S_1 0x0200U
6293 #define TIM_CCMR1_OC2FE 0x0400U
6294 #define TIM_CCMR1_OC2PE 0x0800U
6296 #define TIM_CCMR1_OC2M 0x7000U
6297 #define TIM_CCMR1_OC2M_0 0x1000U
6298 #define TIM_CCMR1_OC2M_1 0x2000U
6299 #define TIM_CCMR1_OC2M_2 0x4000U
6301 #define TIM_CCMR1_OC2CE 0x8000U
6303 /*----------------------------------------------------------------------------*/
6304 
6305 #define TIM_CCMR1_IC1PSC 0x000CU
6306 #define TIM_CCMR1_IC1PSC_0 0x0004U
6307 #define TIM_CCMR1_IC1PSC_1 0x0008U
6309 #define TIM_CCMR1_IC1F 0x00F0U
6310 #define TIM_CCMR1_IC1F_0 0x0010U
6311 #define TIM_CCMR1_IC1F_1 0x0020U
6312 #define TIM_CCMR1_IC1F_2 0x0040U
6313 #define TIM_CCMR1_IC1F_3 0x0080U
6315 #define TIM_CCMR1_IC2PSC 0x0C00U
6316 #define TIM_CCMR1_IC2PSC_0 0x0400U
6317 #define TIM_CCMR1_IC2PSC_1 0x0800U
6319 #define TIM_CCMR1_IC2F 0xF000U
6320 #define TIM_CCMR1_IC2F_0 0x1000U
6321 #define TIM_CCMR1_IC2F_1 0x2000U
6322 #define TIM_CCMR1_IC2F_2 0x4000U
6323 #define TIM_CCMR1_IC2F_3 0x8000U
6325 /****************** Bit definition for TIM_CCMR2 register *******************/
6326 #define TIM_CCMR2_CC3S 0x0003U
6327 #define TIM_CCMR2_CC3S_0 0x0001U
6328 #define TIM_CCMR2_CC3S_1 0x0002U
6330 #define TIM_CCMR2_OC3FE 0x0004U
6331 #define TIM_CCMR2_OC3PE 0x0008U
6333 #define TIM_CCMR2_OC3M 0x0070U
6334 #define TIM_CCMR2_OC3M_0 0x0010U
6335 #define TIM_CCMR2_OC3M_1 0x0020U
6336 #define TIM_CCMR2_OC3M_2 0x0040U
6338 #define TIM_CCMR2_OC3CE 0x0080U
6340 #define TIM_CCMR2_CC4S 0x0300U
6341 #define TIM_CCMR2_CC4S_0 0x0100U
6342 #define TIM_CCMR2_CC4S_1 0x0200U
6344 #define TIM_CCMR2_OC4FE 0x0400U
6345 #define TIM_CCMR2_OC4PE 0x0800U
6347 #define TIM_CCMR2_OC4M 0x7000U
6348 #define TIM_CCMR2_OC4M_0 0x1000U
6349 #define TIM_CCMR2_OC4M_1 0x2000U
6350 #define TIM_CCMR2_OC4M_2 0x4000U
6352 #define TIM_CCMR2_OC4CE 0x8000U
6354 /*----------------------------------------------------------------------------*/
6355 
6356 #define TIM_CCMR2_IC3PSC 0x000CU
6357 #define TIM_CCMR2_IC3PSC_0 0x0004U
6358 #define TIM_CCMR2_IC3PSC_1 0x0008U
6360 #define TIM_CCMR2_IC3F 0x00F0U
6361 #define TIM_CCMR2_IC3F_0 0x0010U
6362 #define TIM_CCMR2_IC3F_1 0x0020U
6363 #define TIM_CCMR2_IC3F_2 0x0040U
6364 #define TIM_CCMR2_IC3F_3 0x0080U
6366 #define TIM_CCMR2_IC4PSC 0x0C00U
6367 #define TIM_CCMR2_IC4PSC_0 0x0400U
6368 #define TIM_CCMR2_IC4PSC_1 0x0800U
6370 #define TIM_CCMR2_IC4F 0xF000U
6371 #define TIM_CCMR2_IC4F_0 0x1000U
6372 #define TIM_CCMR2_IC4F_1 0x2000U
6373 #define TIM_CCMR2_IC4F_2 0x4000U
6374 #define TIM_CCMR2_IC4F_3 0x8000U
6376 /******************* Bit definition for TIM_CCER register *******************/
6377 #define TIM_CCER_CC1E 0x0001U
6378 #define TIM_CCER_CC1P 0x0002U
6379 #define TIM_CCER_CC1NE 0x0004U
6380 #define TIM_CCER_CC1NP 0x0008U
6381 #define TIM_CCER_CC2E 0x0010U
6382 #define TIM_CCER_CC2P 0x0020U
6383 #define TIM_CCER_CC2NE 0x0040U
6384 #define TIM_CCER_CC2NP 0x0080U
6385 #define TIM_CCER_CC3E 0x0100U
6386 #define TIM_CCER_CC3P 0x0200U
6387 #define TIM_CCER_CC3NE 0x0400U
6388 #define TIM_CCER_CC3NP 0x0800U
6389 #define TIM_CCER_CC4E 0x1000U
6390 #define TIM_CCER_CC4P 0x2000U
6391 #define TIM_CCER_CC4NP 0x8000U
6393 /******************* Bit definition for TIM_CNT register ********************/
6394 #define TIM_CNT_CNT 0xFFFFU
6396 /******************* Bit definition for TIM_PSC register ********************/
6397 #define TIM_PSC_PSC 0xFFFFU
6399 /******************* Bit definition for TIM_ARR register ********************/
6400 #define TIM_ARR_ARR 0xFFFFU
6402 /******************* Bit definition for TIM_RCR register ********************/
6403 #define TIM_RCR_REP 0xFFU
6405 /******************* Bit definition for TIM_CCR1 register *******************/
6406 #define TIM_CCR1_CCR1 0xFFFFU
6408 /******************* Bit definition for TIM_CCR2 register *******************/
6409 #define TIM_CCR2_CCR2 0xFFFFU
6411 /******************* Bit definition for TIM_CCR3 register *******************/
6412 #define TIM_CCR3_CCR3 0xFFFFU
6414 /******************* Bit definition for TIM_CCR4 register *******************/
6415 #define TIM_CCR4_CCR4 0xFFFFU
6417 /******************* Bit definition for TIM_BDTR register *******************/
6418 #define TIM_BDTR_DTG 0x00FFU
6419 #define TIM_BDTR_DTG_0 0x0001U
6420 #define TIM_BDTR_DTG_1 0x0002U
6421 #define TIM_BDTR_DTG_2 0x0004U
6422 #define TIM_BDTR_DTG_3 0x0008U
6423 #define TIM_BDTR_DTG_4 0x0010U
6424 #define TIM_BDTR_DTG_5 0x0020U
6425 #define TIM_BDTR_DTG_6 0x0040U
6426 #define TIM_BDTR_DTG_7 0x0080U
6428 #define TIM_BDTR_LOCK 0x0300U
6429 #define TIM_BDTR_LOCK_0 0x0100U
6430 #define TIM_BDTR_LOCK_1 0x0200U
6432 #define TIM_BDTR_OSSI 0x0400U
6433 #define TIM_BDTR_OSSR 0x0800U
6434 #define TIM_BDTR_BKE 0x1000U
6435 #define TIM_BDTR_BKP 0x2000U
6436 #define TIM_BDTR_AOE 0x4000U
6437 #define TIM_BDTR_MOE 0x8000U
6439 /******************* Bit definition for TIM_DCR register ********************/
6440 #define TIM_DCR_DBA 0x001FU
6441 #define TIM_DCR_DBA_0 0x0001U
6442 #define TIM_DCR_DBA_1 0x0002U
6443 #define TIM_DCR_DBA_2 0x0004U
6444 #define TIM_DCR_DBA_3 0x0008U
6445 #define TIM_DCR_DBA_4 0x0010U
6447 #define TIM_DCR_DBL 0x1F00U
6448 #define TIM_DCR_DBL_0 0x0100U
6449 #define TIM_DCR_DBL_1 0x0200U
6450 #define TIM_DCR_DBL_2 0x0400U
6451 #define TIM_DCR_DBL_3 0x0800U
6452 #define TIM_DCR_DBL_4 0x1000U
6454 /******************* Bit definition for TIM_DMAR register *******************/
6455 #define TIM_DMAR_DMAB 0xFFFFU
6457 /******************* Bit definition for TIM_OR register *********************/
6458 #define TIM_OR_TI4_RMP 0x00C0U
6459 #define TIM_OR_TI4_RMP_0 0x0040U
6460 #define TIM_OR_TI4_RMP_1 0x0080U
6461 #define TIM_OR_ITR1_RMP 0x0C00U
6462 #define TIM_OR_ITR1_RMP_0 0x0400U
6463 #define TIM_OR_ITR1_RMP_1 0x0800U
6466 /******************************************************************************/
6467 /* */
6468 /* Universal Synchronous Asynchronous Receiver Transmitter */
6469 /* */
6470 /******************************************************************************/
6471 /******************* Bit definition for USART_SR register *******************/
6472 #define USART_SR_PE 0x0001U
6473 #define USART_SR_FE 0x0002U
6474 #define USART_SR_NE 0x0004U
6475 #define USART_SR_ORE 0x0008U
6476 #define USART_SR_IDLE 0x0010U
6477 #define USART_SR_RXNE 0x0020U
6478 #define USART_SR_TC 0x0040U
6479 #define USART_SR_TXE 0x0080U
6480 #define USART_SR_LBD 0x0100U
6481 #define USART_SR_CTS 0x0200U
6483 /******************* Bit definition for USART_DR register *******************/
6484 #define USART_DR_DR 0x01FFU
6486 /****************** Bit definition for USART_BRR register *******************/
6487 #define USART_BRR_DIV_Fraction 0x000FU
6488 #define USART_BRR_DIV_Mantissa 0xFFF0U
6490 /****************** Bit definition for USART_CR1 register *******************/
6491 #define USART_CR1_SBK 0x0001U
6492 #define USART_CR1_RWU 0x0002U
6493 #define USART_CR1_RE 0x0004U
6494 #define USART_CR1_TE 0x0008U
6495 #define USART_CR1_IDLEIE 0x0010U
6496 #define USART_CR1_RXNEIE 0x0020U
6497 #define USART_CR1_TCIE 0x0040U
6498 #define USART_CR1_TXEIE 0x0080U
6499 #define USART_CR1_PEIE 0x0100U
6500 #define USART_CR1_PS 0x0200U
6501 #define USART_CR1_PCE 0x0400U
6502 #define USART_CR1_WAKE 0x0800U
6503 #define USART_CR1_M 0x1000U
6504 #define USART_CR1_UE 0x2000U
6505 #define USART_CR1_OVER8 0x8000U
6507 /****************** Bit definition for USART_CR2 register *******************/
6508 #define USART_CR2_ADD 0x000FU
6509 #define USART_CR2_LBDL 0x0020U
6510 #define USART_CR2_LBDIE 0x0040U
6511 #define USART_CR2_LBCL 0x0100U
6512 #define USART_CR2_CPHA 0x0200U
6513 #define USART_CR2_CPOL 0x0400U
6514 #define USART_CR2_CLKEN 0x0800U
6516 #define USART_CR2_STOP 0x3000U
6517 #define USART_CR2_STOP_0 0x1000U
6518 #define USART_CR2_STOP_1 0x2000U
6520 #define USART_CR2_LINEN 0x4000U
6522 /****************** Bit definition for USART_CR3 register *******************/
6523 #define USART_CR3_EIE 0x0001U
6524 #define USART_CR3_IREN 0x0002U
6525 #define USART_CR3_IRLP 0x0004U
6526 #define USART_CR3_HDSEL 0x0008U
6527 #define USART_CR3_NACK 0x0010U
6528 #define USART_CR3_SCEN 0x0020U
6529 #define USART_CR3_DMAR 0x0040U
6530 #define USART_CR3_DMAT 0x0080U
6531 #define USART_CR3_RTSE 0x0100U
6532 #define USART_CR3_CTSE 0x0200U
6533 #define USART_CR3_CTSIE 0x0400U
6534 #define USART_CR3_ONEBIT 0x0800U
6536 /****************** Bit definition for USART_GTPR register ******************/
6537 #define USART_GTPR_PSC 0x00FFU
6538 #define USART_GTPR_PSC_0 0x0001U
6539 #define USART_GTPR_PSC_1 0x0002U
6540 #define USART_GTPR_PSC_2 0x0004U
6541 #define USART_GTPR_PSC_3 0x0008U
6542 #define USART_GTPR_PSC_4 0x0010U
6543 #define USART_GTPR_PSC_5 0x0020U
6544 #define USART_GTPR_PSC_6 0x0040U
6545 #define USART_GTPR_PSC_7 0x0080U
6547 #define USART_GTPR_GT 0xFF00U
6549 /******************************************************************************/
6550 /* */
6551 /* Window WATCHDOG */
6552 /* */
6553 /******************************************************************************/
6554 /******************* Bit definition for WWDG_CR register ********************/
6555 #define WWDG_CR_T 0x7FU
6556 #define WWDG_CR_T_0 0x01U
6557 #define WWDG_CR_T_1 0x02U
6558 #define WWDG_CR_T_2 0x04U
6559 #define WWDG_CR_T_3 0x08U
6560 #define WWDG_CR_T_4 0x10U
6561 #define WWDG_CR_T_5 0x20U
6562 #define WWDG_CR_T_6 0x40U
6563 /* Legacy defines */
6564 #define WWDG_CR_T0 WWDG_CR_T_0
6565 #define WWDG_CR_T1 WWDG_CR_T_1
6566 #define WWDG_CR_T2 WWDG_CR_T_2
6567 #define WWDG_CR_T3 WWDG_CR_T_3
6568 #define WWDG_CR_T4 WWDG_CR_T_4
6569 #define WWDG_CR_T5 WWDG_CR_T_5
6570 #define WWDG_CR_T6 WWDG_CR_T_6
6571 
6572 #define WWDG_CR_WDGA 0x80U
6574 /******************* Bit definition for WWDG_CFR register *******************/
6575 #define WWDG_CFR_W 0x007FU
6576 #define WWDG_CFR_W_0 0x0001U
6577 #define WWDG_CFR_W_1 0x0002U
6578 #define WWDG_CFR_W_2 0x0004U
6579 #define WWDG_CFR_W_3 0x0008U
6580 #define WWDG_CFR_W_4 0x0010U
6581 #define WWDG_CFR_W_5 0x0020U
6582 #define WWDG_CFR_W_6 0x0040U
6583 /* Legacy defines */
6584 #define WWDG_CFR_W0 WWDG_CFR_W_0
6585 #define WWDG_CFR_W1 WWDG_CFR_W_1
6586 #define WWDG_CFR_W2 WWDG_CFR_W_2
6587 #define WWDG_CFR_W3 WWDG_CFR_W_3
6588 #define WWDG_CFR_W4 WWDG_CFR_W_4
6589 #define WWDG_CFR_W5 WWDG_CFR_W_5
6590 #define WWDG_CFR_W6 WWDG_CFR_W_6
6591 
6592 #define WWDG_CFR_WDGTB 0x0180U
6593 #define WWDG_CFR_WDGTB_0 0x0080U
6594 #define WWDG_CFR_WDGTB_1 0x0100U
6595 /* Legacy defines */
6596 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6597 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6598 
6599 #define WWDG_CFR_EWI 0x0200U
6601 /******************* Bit definition for WWDG_SR register ********************/
6602 #define WWDG_SR_EWIF 0x01U
6605 /******************************************************************************/
6606 /* */
6607 /* DBG */
6608 /* */
6609 /******************************************************************************/
6610 /******************** Bit definition for DBGMCU_IDCODE register *************/
6611 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
6612 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
6613 
6614 /******************** Bit definition for DBGMCU_CR register *****************/
6615 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
6616 #define DBGMCU_CR_DBG_STOP 0x00000002U
6617 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
6618 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
6619 
6620 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
6621 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
6622 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
6624 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6625 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
6626 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
6627 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
6628 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
6629 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
6630 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
6631 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
6632 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
6633 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
6634 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
6635 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
6636 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
6637 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
6638 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
6639 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
6640 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
6641 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
6642 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
6643 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6644 
6645 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6646 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
6647 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
6648 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
6649 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
6650 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
6651 
6652 /******************************************************************************/
6653 /* */
6654 /* Ethernet MAC Registers bits definitions */
6655 /* */
6656 /******************************************************************************/
6657 /* Bit definition for Ethernet MAC Control Register register */
6658 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
6659 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
6660 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
6661 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
6662  #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
6663  #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
6664  #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
6665  #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
6666  #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
6667  #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
6668  #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
6669 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
6670 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
6671 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
6672 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
6673 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
6674 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
6675 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
6676 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
6677 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
6678  a transmission attempt during retries after a collision: 0 =< r <2^k */
6679  #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
6680  #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
6681  #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
6682  #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
6683 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
6684 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
6685 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
6686 
6687 /* Bit definition for Ethernet MAC Frame Filter Register */
6688 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
6689 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
6690 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
6691 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
6692 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
6693  #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
6694  #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
6695  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
6696 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
6697 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
6698 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
6699 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
6700 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
6701 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
6702 
6703 /* Bit definition for Ethernet MAC Hash Table High Register */
6704 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
6705 
6706 /* Bit definition for Ethernet MAC Hash Table Low Register */
6707 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
6708 
6709 /* Bit definition for Ethernet MAC MII Address Register */
6710 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
6711 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
6712 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
6713  #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
6714  #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
6715  #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
6716  #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
6717  #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
6718 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
6719 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
6720 
6721 /* Bit definition for Ethernet MAC MII Data Register */
6722 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
6723 
6724 /* Bit definition for Ethernet MAC Flow Control Register */
6725 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
6726 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
6727 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
6728  #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
6729  #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
6730  #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
6731  #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
6732 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
6733 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
6734 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
6735 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
6736 
6737 /* Bit definition for Ethernet MAC VLAN Tag Register */
6738 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
6739 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
6740 
6741 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
6742 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
6743 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
6744  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
6745 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
6746  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
6747  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
6748  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
6749  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
6750  RSVD - Filter1 Command - RSVD - Filter0 Command
6751  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
6752  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
6753  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
6754 
6755 /* Bit definition for Ethernet MAC PMT Control and Status Register */
6756 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
6757 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
6758 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
6759 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
6760 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
6761 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
6762 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
6763 
6764 /* Bit definition for Ethernet MAC Status Register */
6765 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
6766 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
6767 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
6768 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
6769 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
6770 
6771 /* Bit definition for Ethernet MAC Interrupt Mask Register */
6772 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
6773 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
6774 
6775 /* Bit definition for Ethernet MAC Address0 High Register */
6776 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
6777 
6778 /* Bit definition for Ethernet MAC Address0 Low Register */
6779 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
6780 
6781 /* Bit definition for Ethernet MAC Address1 High Register */
6782 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
6783 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
6784 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
6785  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
6786  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
6787  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
6788  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
6789  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
6790  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
6791 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
6792 
6793 /* Bit definition for Ethernet MAC Address1 Low Register */
6794 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
6795 
6796 /* Bit definition for Ethernet MAC Address2 High Register */
6797 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
6798 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
6799 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
6800  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
6801  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
6802  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
6803  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
6804  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
6805  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
6806 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
6807 
6808 /* Bit definition for Ethernet MAC Address2 Low Register */
6809 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
6810 
6811 /* Bit definition for Ethernet MAC Address3 High Register */
6812 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
6813 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
6814 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
6815  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
6816  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
6817  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
6818  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
6819  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
6820  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
6821 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
6822 
6823 /* Bit definition for Ethernet MAC Address3 Low Register */
6824 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
6825 
6826 /******************************************************************************/
6827 /* Ethernet MMC Registers bits definition */
6828 /******************************************************************************/
6829 
6830 /* Bit definition for Ethernet MMC Contol Register */
6831 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
6832 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
6833 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
6834 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
6835 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
6836 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
6837 
6838 /* Bit definition for Ethernet MMC Receive Interrupt Register */
6839 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
6840 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
6841 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
6842 
6843 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
6844 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
6845 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
6846 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
6847 
6848 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
6849 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
6850 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
6851 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
6852 
6853 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
6854 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
6855 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
6856 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
6857 
6858 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
6859 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
6860 
6861 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
6862 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
6863 
6864 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
6865 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
6866 
6867 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
6868 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
6869 
6870 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
6871 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
6872 
6873 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
6874 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
6875 
6876 /******************************************************************************/
6877 /* Ethernet PTP Registers bits definition */
6878 /******************************************************************************/
6879 
6880 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
6881 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
6882 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
6883 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
6884 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
6885 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
6886 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
6887 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
6888 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
6889 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
6890 
6891 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
6892 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
6893 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
6894 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
6895 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
6896 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
6897 
6898 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
6899 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
6900 
6901 /* Bit definition for Ethernet PTP Time Stamp High Register */
6902 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
6903 
6904 /* Bit definition for Ethernet PTP Time Stamp Low Register */
6905 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
6906 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
6907 
6908 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
6909 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
6910 
6911 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
6912 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
6913 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
6914 
6915 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
6916 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
6917 
6918 /* Bit definition for Ethernet PTP Target Time High Register */
6919 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
6920 
6921 /* Bit definition for Ethernet PTP Target Time Low Register */
6922 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
6923 
6924 /* Bit definition for Ethernet PTP Time Stamp Status Register */
6925 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
6926 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
6927 
6928 /******************************************************************************/
6929 /* Ethernet DMA Registers bits definition */
6930 /******************************************************************************/
6931 
6932 /* Bit definition for Ethernet DMA Bus Mode Register */
6933 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
6934 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
6935 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
6936 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
6937  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
6938  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
6939  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
6940  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
6941  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
6942  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
6943  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
6944  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
6945  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
6946  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
6947  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
6948  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
6949 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
6950 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
6951  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
6952  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
6953  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
6954  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
6955 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
6956  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
6957  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
6958  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
6959  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
6960  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
6961  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
6962  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
6963  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
6964  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
6965  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
6966  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
6967  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
6968 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
6969 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
6970 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
6971 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
6972 
6973 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
6974 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
6975 
6976 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
6977 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
6978 
6979 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
6980 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
6981 
6982 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
6983 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
6984 
6985 /* Bit definition for Ethernet DMA Status Register */
6986 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
6987 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
6988 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
6989 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
6990  /* combination with EBS[2:0] for GetFlagStatus function */
6991  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
6992  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
6993  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
6994 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
6995  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
6996  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
6997  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
6998  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
6999  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
7000  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
7001 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
7002  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
7003  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
7004  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
7005  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
7006  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
7007  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
7008 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
7009 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
7010 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
7011 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
7012 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
7013 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
7014 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
7015 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
7016 #define ETH_DMASR_RS 0x00000040U /* Receive status */
7017 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
7018 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
7019 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
7020 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
7021 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
7022 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
7023 
7024 /* Bit definition for Ethernet DMA Operation Mode Register */
7025 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
7026 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
7027 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
7028 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
7029 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
7030 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
7031  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7032  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7033  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7034  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7035  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7036  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7037  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7038  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7039 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
7040 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
7041 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
7042 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
7043  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
7044  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
7045  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
7046  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
7047 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
7048 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
7049 
7050 /* Bit definition for Ethernet DMA Interrupt Enable Register */
7051 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
7052 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
7053 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
7054 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
7055 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
7056 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
7057 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
7058 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
7059 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
7060 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
7061 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
7062 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
7063 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
7064 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
7065 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
7066 
7067 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
7068 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
7069 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
7070 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
7071 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
7072 
7073 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
7074 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
7075 
7076 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
7077 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
7078 
7079 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
7080 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
7081 
7082 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
7083 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
7084 
7085 /******************************************************************************/
7086 /* */
7087 /* USB_OTG */
7088 /* */
7089 /******************************************************************************/
7090 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
7091 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
7092 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
7093 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
7094 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
7095 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
7096 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
7097 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
7098 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
7099 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
7100 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
7102 /******************** Bit definition forUSB_OTG_HCFG register ********************/
7103 
7104 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
7105 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
7106 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
7107 #define USB_OTG_HCFG_FSLSS 0x00000004U
7109 /******************** Bit definition forUSB_OTG_DCFG register ********************/
7110 
7111 #define USB_OTG_DCFG_DSPD 0x00000003U
7112 #define USB_OTG_DCFG_DSPD_0 0x00000001U
7113 #define USB_OTG_DCFG_DSPD_1 0x00000002U
7114 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
7116 #define USB_OTG_DCFG_DAD 0x000007F0U
7117 #define USB_OTG_DCFG_DAD_0 0x00000010U
7118 #define USB_OTG_DCFG_DAD_1 0x00000020U
7119 #define USB_OTG_DCFG_DAD_2 0x00000040U
7120 #define USB_OTG_DCFG_DAD_3 0x00000080U
7121 #define USB_OTG_DCFG_DAD_4 0x00000100U
7122 #define USB_OTG_DCFG_DAD_5 0x00000200U
7123 #define USB_OTG_DCFG_DAD_6 0x00000400U
7125 #define USB_OTG_DCFG_PFIVL 0x00001800U
7126 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
7127 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
7129 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
7130 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
7131 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
7133 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
7134 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
7135 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
7136 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
7138 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
7139 #define USB_OTG_GOTGINT_SEDET 0x00000004U
7140 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
7141 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
7142 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
7143 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
7144 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
7146 /******************** Bit definition forUSB_OTG_DCTL register ********************/
7147 #define USB_OTG_DCTL_RWUSIG 0x00000001U
7148 #define USB_OTG_DCTL_SDIS 0x00000002U
7149 #define USB_OTG_DCTL_GINSTS 0x00000004U
7150 #define USB_OTG_DCTL_GONSTS 0x00000008U
7152 #define USB_OTG_DCTL_TCTL 0x00000070U
7153 #define USB_OTG_DCTL_TCTL_0 0x00000010U
7154 #define USB_OTG_DCTL_TCTL_1 0x00000020U
7155 #define USB_OTG_DCTL_TCTL_2 0x00000040U
7156 #define USB_OTG_DCTL_SGINAK 0x00000080U
7157 #define USB_OTG_DCTL_CGINAK 0x00000100U
7158 #define USB_OTG_DCTL_SGONAK 0x00000200U
7159 #define USB_OTG_DCTL_CGONAK 0x00000400U
7160 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
7162 /******************** Bit definition forUSB_OTG_HFIR register ********************/
7163 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
7165 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
7166 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
7167 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
7169 /******************** Bit definition forUSB_OTG_DSTS register ********************/
7170 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
7172 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
7173 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
7174 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
7175 #define USB_OTG_DSTS_EERR 0x00000008U
7176 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
7178 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
7179 #define USB_OTG_GAHBCFG_GINT 0x00000001U
7181 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
7182 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
7183 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
7184 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
7185 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
7186 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
7187 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
7188 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
7190 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
7191 
7192 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
7193 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
7194 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
7195 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
7196 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
7197 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
7198 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
7200 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
7201 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
7202 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
7203 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
7204 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
7205 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
7206 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
7207 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
7208 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
7209 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
7210 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
7211 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
7212 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
7213 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
7214 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
7215 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
7216 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
7217 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
7219 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
7220 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
7221 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
7222 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
7223 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
7224 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
7226 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
7227 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
7228 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
7229 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
7230 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
7231 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
7232 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
7233 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
7235 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
7236 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
7237 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
7238 #define USB_OTG_DIEPMSK_TOM 0x00000008U
7239 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
7240 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
7241 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
7242 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
7243 #define USB_OTG_DIEPMSK_BIM 0x00000200U
7245 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
7246 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
7248 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
7249 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
7250 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
7251 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
7252 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
7253 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
7254 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
7255 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
7256 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
7258 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
7259 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
7260 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
7261 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
7262 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
7263 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
7264 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
7265 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
7266 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
7268 /******************** Bit definition forUSB_OTG_HAINT register ********************/
7269 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
7271 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
7272 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
7273 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
7274 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
7275 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
7276 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
7277 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
7278 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
7280 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
7281 #define USB_OTG_GINTSTS_CMOD 0x00000001U
7282 #define USB_OTG_GINTSTS_MMIS 0x00000002U
7283 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
7284 #define USB_OTG_GINTSTS_SOF 0x00000008U
7285 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
7286 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
7287 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
7288 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
7289 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
7290 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
7291 #define USB_OTG_GINTSTS_USBRST 0x00001000U
7292 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
7293 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
7294 #define USB_OTG_GINTSTS_EOPF 0x00008000U
7295 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
7296 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
7297 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
7298 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
7299 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
7300 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
7301 #define USB_OTG_GINTSTS_HCINT 0x02000000U
7302 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
7303 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
7304 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
7305 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
7306 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
7308 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
7309 #define USB_OTG_GINTMSK_MMISM 0x00000002U
7310 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
7311 #define USB_OTG_GINTMSK_SOFM 0x00000008U
7312 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
7313 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
7314 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
7315 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
7316 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
7317 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
7318 #define USB_OTG_GINTMSK_USBRST 0x00001000U
7319 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
7320 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
7321 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
7322 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
7323 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
7324 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
7325 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
7326 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
7327 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
7328 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
7329 #define USB_OTG_GINTMSK_HCIM 0x02000000U
7330 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
7331 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
7332 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
7333 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
7334 #define USB_OTG_GINTMSK_WUIM 0x80000000U
7336 /******************** Bit definition forUSB_OTG_DAINT register ********************/
7337 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
7338 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
7340 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
7341 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
7343 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
7344 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
7345 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
7346 #define USB_OTG_GRXSTSP_DPID 0x00018000U
7347 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
7349 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
7350 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
7351 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
7353 /******************** Bit definition for OTG register ********************/
7354 
7355 #define USB_OTG_CHNUM 0x0000000FU
7356 #define USB_OTG_CHNUM_0 0x00000001U
7357 #define USB_OTG_CHNUM_1 0x00000002U
7358 #define USB_OTG_CHNUM_2 0x00000004U
7359 #define USB_OTG_CHNUM_3 0x00000008U
7360 #define USB_OTG_BCNT 0x00007FF0U
7362 #define USB_OTG_DPID 0x00018000U
7363 #define USB_OTG_DPID_0 0x00008000U
7364 #define USB_OTG_DPID_1 0x00010000U
7366 #define USB_OTG_PKTSTS 0x001E0000U
7367 #define USB_OTG_PKTSTS_0 0x00020000U
7368 #define USB_OTG_PKTSTS_1 0x00040000U
7369 #define USB_OTG_PKTSTS_2 0x00080000U
7370 #define USB_OTG_PKTSTS_3 0x00100000U
7372 #define USB_OTG_EPNUM 0x0000000FU
7373 #define USB_OTG_EPNUM_0 0x00000001U
7374 #define USB_OTG_EPNUM_1 0x00000002U
7375 #define USB_OTG_EPNUM_2 0x00000004U
7376 #define USB_OTG_EPNUM_3 0x00000008U
7378 #define USB_OTG_FRMNUM 0x01E00000U
7379 #define USB_OTG_FRMNUM_0 0x00200000U
7380 #define USB_OTG_FRMNUM_1 0x00400000U
7381 #define USB_OTG_FRMNUM_2 0x00800000U
7382 #define USB_OTG_FRMNUM_3 0x01000000U
7384 /******************** Bit definition for OTG register ********************/
7385 
7386 #define USB_OTG_CHNUM 0x0000000FU
7387 #define USB_OTG_CHNUM_0 0x00000001U
7388 #define USB_OTG_CHNUM_1 0x00000002U
7389 #define USB_OTG_CHNUM_2 0x00000004U
7390 #define USB_OTG_CHNUM_3 0x00000008U
7391 #define USB_OTG_BCNT 0x00007FF0U
7393 #define USB_OTG_DPID 0x00018000U
7394 #define USB_OTG_DPID_0 0x00008000U
7395 #define USB_OTG_DPID_1 0x00010000U
7397 #define USB_OTG_PKTSTS 0x001E0000U
7398 #define USB_OTG_PKTSTS_0 0x00020000U
7399 #define USB_OTG_PKTSTS_1 0x00040000U
7400 #define USB_OTG_PKTSTS_2 0x00080000U
7401 #define USB_OTG_PKTSTS_3 0x00100000U
7403 #define USB_OTG_EPNUM 0x0000000FU
7404 #define USB_OTG_EPNUM_0 0x00000001U
7405 #define USB_OTG_EPNUM_1 0x00000002U
7406 #define USB_OTG_EPNUM_2 0x00000004U
7407 #define USB_OTG_EPNUM_3 0x00000008U
7409 #define USB_OTG_FRMNUM 0x01E00000U
7410 #define USB_OTG_FRMNUM_0 0x00200000U
7411 #define USB_OTG_FRMNUM_1 0x00400000U
7412 #define USB_OTG_FRMNUM_2 0x00800000U
7413 #define USB_OTG_FRMNUM_3 0x01000000U
7415 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
7416 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
7418 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
7419 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
7421 /******************** Bit definition for OTG register ********************/
7422 #define USB_OTG_NPTXFSA 0x0000FFFFU
7423 #define USB_OTG_NPTXFD 0xFFFF0000U
7424 #define USB_OTG_TX0FSA 0x0000FFFFU
7425 #define USB_OTG_TX0FD 0xFFFF0000U
7427 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
7428 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
7430 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
7431 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
7433 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
7434 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
7435 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
7436 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
7437 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
7438 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
7439 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
7440 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
7441 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
7443 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
7444 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
7445 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
7446 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
7447 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
7448 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
7449 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
7450 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
7452 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
7453 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
7454 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
7456 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
7457 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
7458 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
7459 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
7460 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
7461 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
7462 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
7463 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
7464 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
7465 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
7466 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
7468 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
7469 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
7470 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
7471 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
7472 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
7473 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
7474 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
7475 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
7476 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
7477 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
7478 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
7480 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
7481 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
7483 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
7484 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
7485 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
7487 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
7488 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
7489 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
7490 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
7491 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
7492 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
7493 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
7495 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
7496 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
7497 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
7499 /******************** Bit definition forUSB_OTG_CID register ********************/
7500 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
7502 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
7503 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
7504 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
7505 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
7506 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
7507 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
7508 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
7509 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
7510 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
7511 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
7513 /******************** Bit definition forUSB_OTG_HPRT register ********************/
7514 #define USB_OTG_HPRT_PCSTS 0x00000001U
7515 #define USB_OTG_HPRT_PCDET 0x00000002U
7516 #define USB_OTG_HPRT_PENA 0x00000004U
7517 #define USB_OTG_HPRT_PENCHNG 0x00000008U
7518 #define USB_OTG_HPRT_POCA 0x00000010U
7519 #define USB_OTG_HPRT_POCCHNG 0x00000020U
7520 #define USB_OTG_HPRT_PRES 0x00000040U
7521 #define USB_OTG_HPRT_PSUSP 0x00000080U
7522 #define USB_OTG_HPRT_PRST 0x00000100U
7524 #define USB_OTG_HPRT_PLSTS 0x00000C00U
7525 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
7526 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
7527 #define USB_OTG_HPRT_PPWR 0x00001000U
7529 #define USB_OTG_HPRT_PTCTL 0x0001E000U
7530 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
7531 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
7532 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
7533 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
7535 #define USB_OTG_HPRT_PSPD 0x00060000U
7536 #define USB_OTG_HPRT_PSPD_0 0x00020000U
7537 #define USB_OTG_HPRT_PSPD_1 0x00040000U
7539 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
7540 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
7541 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
7542 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
7543 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
7544 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
7545 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
7546 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
7547 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
7548 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
7549 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
7550 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
7552 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
7553 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
7554 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
7556 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
7557 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
7558 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
7559 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
7560 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
7562 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
7563 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
7564 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
7565 #define USB_OTG_DIEPCTL_STALL 0x00200000U
7567 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
7568 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
7569 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
7570 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
7571 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
7572 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
7573 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
7574 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
7575 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
7576 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
7577 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
7579 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
7580 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
7582 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
7583 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
7584 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
7585 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
7586 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
7587 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
7588 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
7590 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
7591 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
7592 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
7594 #define USB_OTG_HCCHAR_MC 0x00300000U
7595 #define USB_OTG_HCCHAR_MC_0 0x00100000U
7596 #define USB_OTG_HCCHAR_MC_1 0x00200000U
7598 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
7599 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
7600 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
7601 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
7602 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
7603 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
7604 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
7605 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
7606 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
7607 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
7608 #define USB_OTG_HCCHAR_CHENA 0x80000000U
7610 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
7611 
7612 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
7613 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
7614 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
7615 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
7616 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
7617 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
7618 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
7619 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
7621 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
7622 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
7623 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
7624 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
7625 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
7626 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
7627 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
7628 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
7630 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
7631 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
7632 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
7633 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
7634 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
7636 /******************** Bit definition forUSB_OTG_HCINT register ********************/
7637 #define USB_OTG_HCINT_XFRC 0x00000001U
7638 #define USB_OTG_HCINT_CHH 0x00000002U
7639 #define USB_OTG_HCINT_AHBERR 0x00000004U
7640 #define USB_OTG_HCINT_STALL 0x00000008U
7641 #define USB_OTG_HCINT_NAK 0x00000010U
7642 #define USB_OTG_HCINT_ACK 0x00000020U
7643 #define USB_OTG_HCINT_NYET 0x00000040U
7644 #define USB_OTG_HCINT_TXERR 0x00000080U
7645 #define USB_OTG_HCINT_BBERR 0x00000100U
7646 #define USB_OTG_HCINT_FRMOR 0x00000200U
7647 #define USB_OTG_HCINT_DTERR 0x00000400U
7649 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
7650 #define USB_OTG_DIEPINT_XFRC 0x00000001U
7651 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
7652 #define USB_OTG_DIEPINT_TOC 0x00000008U
7653 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
7654 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
7655 #define USB_OTG_DIEPINT_TXFE 0x00000080U
7656 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
7657 #define USB_OTG_DIEPINT_BNA 0x00000200U
7658 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
7659 #define USB_OTG_DIEPINT_BERR 0x00001000U
7660 #define USB_OTG_DIEPINT_NAK 0x00002000U
7662 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
7663 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
7664 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
7665 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
7666 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
7667 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
7668 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
7669 #define USB_OTG_HCINTMSK_NYET 0x00000040U
7670 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
7671 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
7672 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
7673 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
7675 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
7676 
7677 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
7678 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
7679 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
7680 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
7681 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
7682 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
7683 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
7684 #define USB_OTG_HCTSIZ_DPID 0x60000000U
7685 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
7686 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
7688 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
7689 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
7691 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
7692 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
7694 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
7695 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
7697 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
7698 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
7699 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
7701 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
7702 
7703 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
7704 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
7705 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
7706 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
7707 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
7708 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
7709 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
7710 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
7711 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
7712 #define USB_OTG_DOEPCTL_STALL 0x00200000U
7713 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
7714 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
7715 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
7716 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
7718 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
7719 #define USB_OTG_DOEPINT_XFRC 0x00000001U
7720 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
7721 #define USB_OTG_DOEPINT_STUP 0x00000008U
7722 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
7723 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
7724 #define USB_OTG_DOEPINT_NYET 0x00004000U
7726 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
7727 
7728 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
7729 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
7731 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
7732 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
7733 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
7735 /******************** Bit definition for PCGCCTL register ********************/
7736 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
7737 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
7738 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
7752 /******************************* ADC Instances ********************************/
7753 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
7754  ((INSTANCE) == ADC2) || \
7755  ((INSTANCE) == ADC3))
7756 
7757 /******************************* CAN Instances ********************************/
7758 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
7759  ((INSTANCE) == CAN2))
7760 
7761 /******************************* CRC Instances ********************************/
7762 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7763 
7764 /******************************* DAC Instances ********************************/
7765 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
7766 
7767 /******************************* DCMI Instances *******************************/
7768 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
7769 
7770 /******************************** DMA Instances *******************************/
7771 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7772  ((INSTANCE) == DMA1_Stream1) || \
7773  ((INSTANCE) == DMA1_Stream2) || \
7774  ((INSTANCE) == DMA1_Stream3) || \
7775  ((INSTANCE) == DMA1_Stream4) || \
7776  ((INSTANCE) == DMA1_Stream5) || \
7777  ((INSTANCE) == DMA1_Stream6) || \
7778  ((INSTANCE) == DMA1_Stream7) || \
7779  ((INSTANCE) == DMA2_Stream0) || \
7780  ((INSTANCE) == DMA2_Stream1) || \
7781  ((INSTANCE) == DMA2_Stream2) || \
7782  ((INSTANCE) == DMA2_Stream3) || \
7783  ((INSTANCE) == DMA2_Stream4) || \
7784  ((INSTANCE) == DMA2_Stream5) || \
7785  ((INSTANCE) == DMA2_Stream6) || \
7786  ((INSTANCE) == DMA2_Stream7))
7787 
7788 /******************************* GPIO Instances *******************************/
7789 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7790  ((INSTANCE) == GPIOB) || \
7791  ((INSTANCE) == GPIOC) || \
7792  ((INSTANCE) == GPIOD) || \
7793  ((INSTANCE) == GPIOE) || \
7794  ((INSTANCE) == GPIOF) || \
7795  ((INSTANCE) == GPIOG) || \
7796  ((INSTANCE) == GPIOH) || \
7797  ((INSTANCE) == GPIOI))
7798 
7799 /******************************** I2C Instances *******************************/
7800 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7801  ((INSTANCE) == I2C2) || \
7802  ((INSTANCE) == I2C3))
7803 
7804 /******************************** I2S Instances *******************************/
7805 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
7806  ((INSTANCE) == SPI3))
7807 
7808 /*************************** I2S Extended Instances ***************************/
7809 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
7810  ((INSTANCE) == SPI3) || \
7811  ((INSTANCE) == I2S2ext) || \
7812  ((INSTANCE) == I2S3ext))
7813 
7814 /******************************* RNG Instances ********************************/
7815 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
7816 
7817 /****************************** RTC Instances *********************************/
7818 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7819 
7820 /******************************** SPI Instances *******************************/
7821 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7822  ((INSTANCE) == SPI2) || \
7823  ((INSTANCE) == SPI3))
7824 
7825 /*************************** SPI Extended Instances ***************************/
7826 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
7827  ((INSTANCE) == SPI2) || \
7828  ((INSTANCE) == SPI3) || \
7829  ((INSTANCE) == I2S2ext) || \
7830  ((INSTANCE) == I2S3ext))
7831 
7832 /****************** TIM Instances : All supported instances *******************/
7833 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7834  ((INSTANCE) == TIM2) || \
7835  ((INSTANCE) == TIM3) || \
7836  ((INSTANCE) == TIM4) || \
7837  ((INSTANCE) == TIM5) || \
7838  ((INSTANCE) == TIM6) || \
7839  ((INSTANCE) == TIM7) || \
7840  ((INSTANCE) == TIM8) || \
7841  ((INSTANCE) == TIM9) || \
7842  ((INSTANCE) == TIM10) || \
7843  ((INSTANCE) == TIM11) || \
7844  ((INSTANCE) == TIM12) || \
7845  ((INSTANCE) == TIM13) || \
7846  ((INSTANCE) == TIM14))
7847 
7848 /************* TIM Instances : at least 1 capture/compare channel *************/
7849 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7850  ((INSTANCE) == TIM2) || \
7851  ((INSTANCE) == TIM3) || \
7852  ((INSTANCE) == TIM4) || \
7853  ((INSTANCE) == TIM5) || \
7854  ((INSTANCE) == TIM8) || \
7855  ((INSTANCE) == TIM9) || \
7856  ((INSTANCE) == TIM10) || \
7857  ((INSTANCE) == TIM11) || \
7858  ((INSTANCE) == TIM12) || \
7859  ((INSTANCE) == TIM13) || \
7860  ((INSTANCE) == TIM14))
7861 
7862 /************ TIM Instances : at least 2 capture/compare channels *************/
7863 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7864  ((INSTANCE) == TIM2) || \
7865  ((INSTANCE) == TIM3) || \
7866  ((INSTANCE) == TIM4) || \
7867  ((INSTANCE) == TIM5) || \
7868  ((INSTANCE) == TIM8) || \
7869  ((INSTANCE) == TIM9) || \
7870  ((INSTANCE) == TIM12))
7871 
7872 /************ TIM Instances : at least 3 capture/compare channels *************/
7873 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7874  ((INSTANCE) == TIM2) || \
7875  ((INSTANCE) == TIM3) || \
7876  ((INSTANCE) == TIM4) || \
7877  ((INSTANCE) == TIM5) || \
7878  ((INSTANCE) == TIM8))
7879 
7880 /************ TIM Instances : at least 4 capture/compare channels *************/
7881 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7882  ((INSTANCE) == TIM2) || \
7883  ((INSTANCE) == TIM3) || \
7884  ((INSTANCE) == TIM4) || \
7885  ((INSTANCE) == TIM5) || \
7886  ((INSTANCE) == TIM8))
7887 
7888 /******************** TIM Instances : Advanced-control timers *****************/
7889 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7890  ((INSTANCE) == TIM8))
7891 
7892 /******************* TIM Instances : Timer input XOR function *****************/
7893 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7894  ((INSTANCE) == TIM2) || \
7895  ((INSTANCE) == TIM3) || \
7896  ((INSTANCE) == TIM4) || \
7897  ((INSTANCE) == TIM5) || \
7898  ((INSTANCE) == TIM8))
7899 
7900 /****************** TIM Instances : DMA requests generation (UDE) *************/
7901 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7902  ((INSTANCE) == TIM2) || \
7903  ((INSTANCE) == TIM3) || \
7904  ((INSTANCE) == TIM4) || \
7905  ((INSTANCE) == TIM5) || \
7906  ((INSTANCE) == TIM6) || \
7907  ((INSTANCE) == TIM7) || \
7908  ((INSTANCE) == TIM8))
7909 
7910 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
7911 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7912  ((INSTANCE) == TIM2) || \
7913  ((INSTANCE) == TIM3) || \
7914  ((INSTANCE) == TIM4) || \
7915  ((INSTANCE) == TIM5) || \
7916  ((INSTANCE) == TIM8))
7917 
7918 /************ TIM Instances : DMA requests generation (COMDE) *****************/
7919 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7920  ((INSTANCE) == TIM2) || \
7921  ((INSTANCE) == TIM3) || \
7922  ((INSTANCE) == TIM4) || \
7923  ((INSTANCE) == TIM5) || \
7924  ((INSTANCE) == TIM8))
7925 
7926 /******************** TIM Instances : DMA burst feature ***********************/
7927 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7928  ((INSTANCE) == TIM2) || \
7929  ((INSTANCE) == TIM3) || \
7930  ((INSTANCE) == TIM4) || \
7931  ((INSTANCE) == TIM5) || \
7932  ((INSTANCE) == TIM8))
7933 
7934 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
7935 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7936  ((INSTANCE) == TIM2) || \
7937  ((INSTANCE) == TIM3) || \
7938  ((INSTANCE) == TIM4) || \
7939  ((INSTANCE) == TIM5) || \
7940  ((INSTANCE) == TIM6) || \
7941  ((INSTANCE) == TIM7) || \
7942  ((INSTANCE) == TIM8) || \
7943  ((INSTANCE) == TIM9) || \
7944  ((INSTANCE) == TIM12))
7945 
7946 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7947 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7948  ((INSTANCE) == TIM2) || \
7949  ((INSTANCE) == TIM3) || \
7950  ((INSTANCE) == TIM4) || \
7951  ((INSTANCE) == TIM5) || \
7952  ((INSTANCE) == TIM8) || \
7953  ((INSTANCE) == TIM9) || \
7954  ((INSTANCE) == TIM12))
7955 
7956 /********************** TIM Instances : 32 bit Counter ************************/
7957 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
7958  ((INSTANCE) == TIM5))
7959 
7960 /***************** TIM Instances : external trigger input availabe ************/
7961 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7962  ((INSTANCE) == TIM2) || \
7963  ((INSTANCE) == TIM3) || \
7964  ((INSTANCE) == TIM4) || \
7965  ((INSTANCE) == TIM5) || \
7966  ((INSTANCE) == TIM8))
7967 
7968 /****************** TIM Instances : remapping capability **********************/
7969 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7970  ((INSTANCE) == TIM5) || \
7971  ((INSTANCE) == TIM11))
7972 
7973 /******************* TIM Instances : output(s) available **********************/
7974 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7975  ((((INSTANCE) == TIM1) && \
7976  (((CHANNEL) == TIM_CHANNEL_1) || \
7977  ((CHANNEL) == TIM_CHANNEL_2) || \
7978  ((CHANNEL) == TIM_CHANNEL_3) || \
7979  ((CHANNEL) == TIM_CHANNEL_4))) \
7980  || \
7981  (((INSTANCE) == TIM2) && \
7982  (((CHANNEL) == TIM_CHANNEL_1) || \
7983  ((CHANNEL) == TIM_CHANNEL_2) || \
7984  ((CHANNEL) == TIM_CHANNEL_3) || \
7985  ((CHANNEL) == TIM_CHANNEL_4))) \
7986  || \
7987  (((INSTANCE) == TIM3) && \
7988  (((CHANNEL) == TIM_CHANNEL_1) || \
7989  ((CHANNEL) == TIM_CHANNEL_2) || \
7990  ((CHANNEL) == TIM_CHANNEL_3) || \
7991  ((CHANNEL) == TIM_CHANNEL_4))) \
7992  || \
7993  (((INSTANCE) == TIM4) && \
7994  (((CHANNEL) == TIM_CHANNEL_1) || \
7995  ((CHANNEL) == TIM_CHANNEL_2) || \
7996  ((CHANNEL) == TIM_CHANNEL_3) || \
7997  ((CHANNEL) == TIM_CHANNEL_4))) \
7998  || \
7999  (((INSTANCE) == TIM5) && \
8000  (((CHANNEL) == TIM_CHANNEL_1) || \
8001  ((CHANNEL) == TIM_CHANNEL_2) || \
8002  ((CHANNEL) == TIM_CHANNEL_3) || \
8003  ((CHANNEL) == TIM_CHANNEL_4))) \
8004  || \
8005  (((INSTANCE) == TIM8) && \
8006  (((CHANNEL) == TIM_CHANNEL_1) || \
8007  ((CHANNEL) == TIM_CHANNEL_2) || \
8008  ((CHANNEL) == TIM_CHANNEL_3) || \
8009  ((CHANNEL) == TIM_CHANNEL_4))) \
8010  || \
8011  (((INSTANCE) == TIM9) && \
8012  (((CHANNEL) == TIM_CHANNEL_1) || \
8013  ((CHANNEL) == TIM_CHANNEL_2))) \
8014  || \
8015  (((INSTANCE) == TIM10) && \
8016  (((CHANNEL) == TIM_CHANNEL_1))) \
8017  || \
8018  (((INSTANCE) == TIM11) && \
8019  (((CHANNEL) == TIM_CHANNEL_1))) \
8020  || \
8021  (((INSTANCE) == TIM12) && \
8022  (((CHANNEL) == TIM_CHANNEL_1) || \
8023  ((CHANNEL) == TIM_CHANNEL_2))) \
8024  || \
8025  (((INSTANCE) == TIM13) && \
8026  (((CHANNEL) == TIM_CHANNEL_1))) \
8027  || \
8028  (((INSTANCE) == TIM14) && \
8029  (((CHANNEL) == TIM_CHANNEL_1))))
8030 
8031 /************ TIM Instances : complementary output(s) available ***************/
8032 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8033  ((((INSTANCE) == TIM1) && \
8034  (((CHANNEL) == TIM_CHANNEL_1) || \
8035  ((CHANNEL) == TIM_CHANNEL_2) || \
8036  ((CHANNEL) == TIM_CHANNEL_3))) \
8037  || \
8038  (((INSTANCE) == TIM8) && \
8039  (((CHANNEL) == TIM_CHANNEL_1) || \
8040  ((CHANNEL) == TIM_CHANNEL_2) || \
8041  ((CHANNEL) == TIM_CHANNEL_3))))
8042 
8043 /******************** USART Instances : Synchronous mode **********************/
8044 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8045  ((INSTANCE) == USART2) || \
8046  ((INSTANCE) == USART3) || \
8047  ((INSTANCE) == USART6))
8048 
8049 /******************** UART Instances : Asynchronous mode **********************/
8050 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8051  ((INSTANCE) == USART2) || \
8052  ((INSTANCE) == USART3) || \
8053  ((INSTANCE) == UART4) || \
8054  ((INSTANCE) == UART5) || \
8055  ((INSTANCE) == USART6))
8056 
8057 /****************** UART Instances : Hardware Flow control ********************/
8058 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8059  ((INSTANCE) == USART2) || \
8060  ((INSTANCE) == USART3) || \
8061  ((INSTANCE) == USART6))
8062 
8063 /********************* UART Instances : Smard card mode ***********************/
8064 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8065  ((INSTANCE) == USART2) || \
8066  ((INSTANCE) == USART3) || \
8067  ((INSTANCE) == USART6))
8068 
8069 /*********************** UART Instances : IRDA mode ***************************/
8070 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8071  ((INSTANCE) == USART2) || \
8072  ((INSTANCE) == USART3) || \
8073  ((INSTANCE) == UART4) || \
8074  ((INSTANCE) == UART5) || \
8075  ((INSTANCE) == USART6))
8076 
8077 /*********************** PCD Instances ****************************************/
8078 /*********************** PCD Instances ****************************************/
8079 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
8080  ((INSTANCE) == USB_OTG_HS))
8081 
8082 /*********************** HCD Instances ****************************************/
8083 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
8084  ((INSTANCE) == USB_OTG_HS))
8085 
8086 /****************************** IWDG Instances ********************************/
8087 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
8088 
8089 /****************************** WWDG Instances ********************************/
8090 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8091 
8092 /****************************** SDIO Instances ********************************/
8093 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
8094 
8095 /****************************** USB Exported Constants ************************/
8096 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
8097 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
8098 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
8099 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
8100 
8101 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
8102 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
8103 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
8104 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
8105 
8106 /******************************************************************************/
8107 /* For a painless codes migration between the STM32F4xx device product */
8108 /* lines, the aliases defined below are put in place to overcome the */
8109 /* differences in the interrupt handlers and IRQn definitions. */
8110 /* No need to update developed interrupt code when moving across */
8111 /* product lines within the same STM32F4 Family */
8112 /******************************************************************************/
8113 
8114 /* Aliases for __IRQn */
8115 #define FMC_IRQn FSMC_IRQn
8116 
8117 /* Aliases for __IRQHandler */
8118 #define FMC_IRQHandler FSMC_IRQHandler
8119 
8132 #ifdef __cplusplus
8133 }
8134 #endif /* __cplusplus */
8135 
8136 #endif /* __STM32F407xx_H */
8137 
8138 
8139 
8140 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DCMI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f407xx.h:347
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
TAMP_STAMP_IRQn
Definition: stm32f407xx.h:99
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f405xx.h:395
TIM2_IRQn
Definition: stm32f407xx.h:125
UART4_IRQn
Definition: stm32f407xx.h:149
DCMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32f407xx.h:349
UART5_IRQn
Definition: stm32f407xx.h:150
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f407xx.h:123
EXTI2_IRQn
Definition: stm32f407xx.h:105
EXTI4_IRQn
Definition: stm32f407xx.h:107
USART1_IRQn
Definition: stm32f407xx.h:134
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
ETH_WKUP_IRQn
Definition: stm32f407xx.h:159
DCMI_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32f407xx.h:348
DCMI_TypeDef::ESUR
__IO uint32_t ESUR
Definition: stm32f407xx.h:353
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f407xx.h:142
TIM4_IRQn
Definition: stm32f407xx.h:127
RTC_Alarm_IRQn
Definition: stm32f407xx.h:138
CAN2_SCE_IRQn
Definition: stm32f407xx.h:163
PendSV_IRQn
Definition: stm32f407xx.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f407xx.h:100
CAN1_RX1_IRQn
Definition: stm32f407xx.h:118
TIM6_DAC_IRQn
Definition: stm32f407xx.h:151
CAN1_TX_IRQn
Definition: stm32f407xx.h:116
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f407xx.h:132
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
OTG_FS_WKUP_IRQn
Definition: stm32f407xx.h:139
DMA_TypeDef
Definition: stm32f401xc.h:243
ETH_IRQn
Definition: stm32f407xx.h:158
DMA1_Stream2_IRQn
Definition: stm32f407xx.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f407xx.h:133
__I
#define __I
Definition: core_cm0.h:210
DCMI_TypeDef::CWSIZER
__IO uint32_t CWSIZER
Definition: stm32f407xx.h:355
DCMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f407xx.h:351
DMA2_Stream5_IRQn
Definition: stm32f407xx.h:165
ADC_IRQn
Definition: stm32f407xx.h:115
CAN1_RX0_IRQn
Definition: stm32f407xx.h:117
RCC_IRQn
Definition: stm32f407xx.h:102
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DCMI_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32f407xx.h:350
DebugMonitor_IRQn
Definition: stm32f407xx.h:93
DMA2_Stream3_IRQn
Definition: stm32f407xx.h:156
NonMaskableInt_IRQn
Definition: stm32f407xx.h:88
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f407xx.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f407xx.h:141
DMA1_Stream1_IRQn
Definition: stm32f407xx.h:109
DMA2_Stream7_IRQn
Definition: stm32f407xx.h:167
DMA2_Stream6_IRQn
Definition: stm32f407xx.h:166
BusFault_IRQn
Definition: stm32f407xx.h:90
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
I2C3_ER_IRQn
Definition: stm32f407xx.h:170
CAN2_RX0_IRQn
Definition: stm32f407xx.h:161
USART6_IRQn
Definition: stm32f407xx.h:168
PVD_IRQn
Definition: stm32f407xx.h:98
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f407xx.h:112
DCMI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f407xx.h:356
DMA1_Stream0_IRQn
Definition: stm32f407xx.h:108
OTG_HS_IRQn
Definition: stm32f407xx.h:174
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
TIM8_CC_IRQn
Definition: stm32f407xx.h:143
DMA1_Stream3_IRQn
Definition: stm32f407xx.h:111
FPU_IRQn
Definition: stm32f407xx.h:177
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:386
OTG_FS_IRQn
Definition: stm32f407xx.h:164
DMA2_Stream2_IRQn
Definition: stm32f407xx.h:155
OTG_HS_EP1_OUT_IRQn
Definition: stm32f407xx.h:171
DCMI_TypeDef::CWSTRTR
__IO uint32_t CWSTRTR
Definition: stm32f407xx.h:354
OTG_HS_EP1_IN_IRQn
Definition: stm32f407xx.h:172
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f407xx.h:146
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f407xx.h:169
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f407xx.h:135
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f407xx.h:152
I2C2_EV_IRQn
Definition: stm32f407xx.h:130
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f407xx.h:126
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f407xx.h:104
DCMI_TypeDef::ESCR
__IO uint32_t ESCR
Definition: stm32f407xx.h:352
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f407xx.h:92
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f407xx.h:124
TIM8_BRK_TIM12_IRQn
Definition: stm32f407xx.h:140
HASH_RNG_IRQn
Definition: stm32f407xx.h:176
FLASH_IRQn
Definition: stm32f407xx.h:101
DMA1_Stream5_IRQn
Definition: stm32f407xx.h:113
DCMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f407xx.h:346
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f407xx.h:95
TIM1_UP_TIM10_IRQn
Definition: stm32f407xx.h:122
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f407xx.h:131
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:344
UsageFault_IRQn
Definition: stm32f407xx.h:91
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f405xx.h:404
SPI3_IRQn
Definition: stm32f407xx.h:148
DMA2_Stream1_IRQn
Definition: stm32f407xx.h:154
EXTI9_5_IRQn
Definition: stm32f407xx.h:120
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f407xx.h:128
DMA1_Stream6_IRQn
Definition: stm32f407xx.h:114
OTG_HS_WKUP_IRQn
Definition: stm32f407xx.h:173
I2C1_ER_IRQn
Definition: stm32f407xx.h:129
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
FSMC_IRQn
Definition: stm32f407xx.h:145
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
FSMC_Bank2_3_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f405xx.h:413
CAN2_RX1_IRQn
Definition: stm32f407xx.h:162
DMA2_Stream4_IRQn
Definition: stm32f407xx.h:157
WWDG_IRQn
Definition: stm32f407xx.h:97
DMA1_Stream7_IRQn
Definition: stm32f407xx.h:144
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
EXTI15_10_IRQn
Definition: stm32f407xx.h:137
CAN1_SCE_IRQn
Definition: stm32f407xx.h:119
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f407xx.h:103
DMA2_Stream0_IRQn
Definition: stm32f407xx.h:153
TIM1_BRK_TIM9_IRQn
Definition: stm32f407xx.h:121
CAN2_TX_IRQn
Definition: stm32f407xx.h:160
TIM5_IRQn
Definition: stm32f407xx.h:147
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f407xx.h:106
USART3_IRQn
Definition: stm32f407xx.h:136
DCMI_IRQn
Definition: stm32f407xx.h:175
MemoryManagement_IRQn
Definition: stm32f407xx.h:89
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f405xx.h:435