STM CMSIS
stm32f410cx.h
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1 
52 #ifndef __STM32F410Cx_H
53 #define __STM32F410Cx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  EXTI9_5_IRQn = 23,
117  TIM1_BRK_TIM9_IRQn = 24,
118  TIM1_UP_IRQn = 25,
119  TIM1_TRG_COM_TIM11_IRQn = 26,
120  TIM1_CC_IRQn = 27,
121  I2C1_EV_IRQn = 31,
122  I2C1_ER_IRQn = 32,
123  I2C2_EV_IRQn = 33,
124  I2C2_ER_IRQn = 34,
125  SPI1_IRQn = 35,
126  SPI2_IRQn = 36,
127  USART1_IRQn = 37,
128  USART2_IRQn = 38,
129  EXTI15_10_IRQn = 40,
130  RTC_Alarm_IRQn = 41,
131  DMA1_Stream7_IRQn = 47,
132  TIM5_IRQn = 50,
133  TIM6_DAC_IRQn = 54,
134  DMA2_Stream0_IRQn = 56,
135  DMA2_Stream1_IRQn = 57,
136  DMA2_Stream2_IRQn = 58,
137  DMA2_Stream3_IRQn = 59,
138  DMA2_Stream4_IRQn = 60,
139  DMA2_Stream5_IRQn = 68,
140  DMA2_Stream6_IRQn = 69,
141  DMA2_Stream7_IRQn = 70,
142  USART6_IRQn = 71,
143  RNG_IRQn = 80,
144  FPU_IRQn = 81,
145  SPI5_IRQn = 85,
146  FMPI2C1_EV_IRQn = 95,
147  FMPI2C1_ER_IRQn = 96,
148  LPTIM1_IRQn = 97
149 } IRQn_Type;
150 
155 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
156 #include "system_stm32f4xx.h"
157 #include <stdint.h>
158 
167 typedef struct
168 {
169  __IO uint32_t SR;
170  __IO uint32_t CR1;
171  __IO uint32_t CR2;
172  __IO uint32_t SMPR1;
173  __IO uint32_t SMPR2;
174  __IO uint32_t JOFR1;
175  __IO uint32_t JOFR2;
176  __IO uint32_t JOFR3;
177  __IO uint32_t JOFR4;
178  __IO uint32_t HTR;
179  __IO uint32_t LTR;
180  __IO uint32_t SQR1;
181  __IO uint32_t SQR2;
182  __IO uint32_t SQR3;
183  __IO uint32_t JSQR;
184  __IO uint32_t JDR1;
185  __IO uint32_t JDR2;
186  __IO uint32_t JDR3;
187  __IO uint32_t JDR4;
188  __IO uint32_t DR;
189 } ADC_TypeDef;
190 
191 typedef struct
192 {
193  __IO uint32_t CSR;
194  __IO uint32_t CCR;
195  __IO uint32_t CDR;
197 } ADC_Common_TypeDef;
198 
203 typedef struct
204 {
205  __IO uint32_t DR;
206  __IO uint8_t IDR;
207  uint8_t RESERVED0;
208  uint16_t RESERVED1;
209  __IO uint32_t CR;
210 } CRC_TypeDef;
211 
216 typedef struct
217 {
218  __IO uint32_t CR;
219  __IO uint32_t SWTRIGR;
220  __IO uint32_t DHR12R1;
221  __IO uint32_t DHR12L1;
222  __IO uint32_t DHR8R1;
223  __IO uint32_t DHR12R2;
224  __IO uint32_t DHR12L2;
225  __IO uint32_t DHR8R2;
226  __IO uint32_t DHR12RD;
227  __IO uint32_t DHR12LD;
228  __IO uint32_t DHR8RD;
229  __IO uint32_t DOR1;
230  __IO uint32_t DOR2;
231  __IO uint32_t SR;
232 } DAC_TypeDef;
233 
238 typedef struct
239 {
240  __IO uint32_t IDCODE;
241  __IO uint32_t CR;
242  __IO uint32_t APB1FZ;
243  __IO uint32_t APB2FZ;
244 }DBGMCU_TypeDef;
245 
246 
251 typedef struct
252 {
253  __IO uint32_t CR;
254  __IO uint32_t NDTR;
255  __IO uint32_t PAR;
256  __IO uint32_t M0AR;
257  __IO uint32_t M1AR;
258  __IO uint32_t FCR;
259 } DMA_Stream_TypeDef;
260 
261 typedef struct
262 {
263  __IO uint32_t LISR;
264  __IO uint32_t HISR;
265  __IO uint32_t LIFCR;
266  __IO uint32_t HIFCR;
267 } DMA_TypeDef;
268 
269 
274 typedef struct
275 {
276  __IO uint32_t IMR;
277  __IO uint32_t EMR;
278  __IO uint32_t RTSR;
279  __IO uint32_t FTSR;
280  __IO uint32_t SWIER;
281  __IO uint32_t PR;
282 } EXTI_TypeDef;
283 
288 typedef struct
289 {
290  __IO uint32_t ACR;
291  __IO uint32_t KEYR;
292  __IO uint32_t OPTKEYR;
293  __IO uint32_t SR;
294  __IO uint32_t CR;
295  __IO uint32_t OPTCR;
296  __IO uint32_t OPTCR1;
297 } FLASH_TypeDef;
298 
303 typedef struct
304 {
305  __IO uint32_t MODER;
306  __IO uint32_t OTYPER;
307  __IO uint32_t OSPEEDR;
308  __IO uint32_t PUPDR;
309  __IO uint32_t IDR;
310  __IO uint32_t ODR;
311  __IO uint32_t BSRR;
312  __IO uint32_t LCKR;
313  __IO uint32_t AFR[2];
314 } GPIO_TypeDef;
315 
320 typedef struct
321 {
322  __IO uint32_t MEMRMP;
323  __IO uint32_t PMC;
324  __IO uint32_t EXTICR[4];
325  uint32_t RESERVED;
326  uint32_t CFGR2;
327  __IO uint32_t CMPCR;
328  uint32_t RESERVED1[2];
329  __IO uint32_t CFGR;
330 } SYSCFG_TypeDef;
331 
336 typedef struct
337 {
338  __IO uint32_t CR1;
339  __IO uint32_t CR2;
340  __IO uint32_t OAR1;
341  __IO uint32_t OAR2;
342  __IO uint32_t DR;
343  __IO uint32_t SR1;
344  __IO uint32_t SR2;
345  __IO uint32_t CCR;
346  __IO uint32_t TRISE;
347  __IO uint32_t FLTR;
348 } I2C_TypeDef;
349 
354 typedef struct
355 {
356  __IO uint32_t CR1;
357  __IO uint32_t CR2;
358  __IO uint32_t OAR1;
359  __IO uint32_t OAR2;
360  __IO uint32_t TIMINGR;
361  __IO uint32_t TIMEOUTR;
362  __IO uint32_t ISR;
363  __IO uint32_t ICR;
364  __IO uint32_t PECR;
365  __IO uint32_t RXDR;
366  __IO uint32_t TXDR;
367 } FMPI2C_TypeDef;
368 
373 typedef struct
374 {
375  __IO uint32_t KR;
376  __IO uint32_t PR;
377  __IO uint32_t RLR;
378  __IO uint32_t SR;
379 } IWDG_TypeDef;
380 
385 typedef struct
386 {
387  __IO uint32_t CR;
388  __IO uint32_t CSR;
389 } PWR_TypeDef;
390 
395 typedef struct
396 {
397  __IO uint32_t CR;
398  __IO uint32_t PLLCFGR;
399  __IO uint32_t CFGR;
400  __IO uint32_t CIR;
401  __IO uint32_t AHB1RSTR;
402  uint32_t RESERVED0[3];
403  __IO uint32_t APB1RSTR;
404  __IO uint32_t APB2RSTR;
405  uint32_t RESERVED1[2];
406  __IO uint32_t AHB1ENR;
407  uint32_t RESERVED2[3];
408  __IO uint32_t APB1ENR;
409  __IO uint32_t APB2ENR;
410  uint32_t RESERVED3[2];
411  __IO uint32_t AHB1LPENR;
412  uint32_t RESERVED4[3];
413  __IO uint32_t APB1LPENR;
414  __IO uint32_t APB2LPENR;
415  uint32_t RESERVED5[2];
416  __IO uint32_t BDCR;
417  __IO uint32_t CSR;
418  uint32_t RESERVED6[2];
419  __IO uint32_t SSCGR;
420  uint32_t RESERVED7[2];
421  __IO uint32_t DCKCFGR;
422  __IO uint32_t CKGATENR;
423  __IO uint32_t DCKCFGR2;
425 } RCC_TypeDef;
426 
431 typedef struct
432 {
433  __IO uint32_t TR;
434  __IO uint32_t DR;
435  __IO uint32_t CR;
436  __IO uint32_t ISR;
437  __IO uint32_t PRER;
438  __IO uint32_t WUTR;
439  __IO uint32_t CALIBR;
440  __IO uint32_t ALRMAR;
441  __IO uint32_t ALRMBR;
442  __IO uint32_t WPR;
443  __IO uint32_t SSR;
444  __IO uint32_t SHIFTR;
445  __IO uint32_t TSTR;
446  __IO uint32_t TSDR;
447  __IO uint32_t TSSSR;
448  __IO uint32_t CALR;
449  __IO uint32_t TAFCR;
450  __IO uint32_t ALRMASSR;
451  __IO uint32_t ALRMBSSR;
452  uint32_t RESERVED7;
453  __IO uint32_t BKP0R;
454  __IO uint32_t BKP1R;
455  __IO uint32_t BKP2R;
456  __IO uint32_t BKP3R;
457  __IO uint32_t BKP4R;
458  __IO uint32_t BKP5R;
459  __IO uint32_t BKP6R;
460  __IO uint32_t BKP7R;
461  __IO uint32_t BKP8R;
462  __IO uint32_t BKP9R;
463  __IO uint32_t BKP10R;
464  __IO uint32_t BKP11R;
465  __IO uint32_t BKP12R;
466  __IO uint32_t BKP13R;
467  __IO uint32_t BKP14R;
468  __IO uint32_t BKP15R;
469  __IO uint32_t BKP16R;
470  __IO uint32_t BKP17R;
471  __IO uint32_t BKP18R;
472  __IO uint32_t BKP19R;
473 } RTC_TypeDef;
474 
479 typedef struct
480 {
481  __IO uint32_t CR1;
482  __IO uint32_t CR2;
483  __IO uint32_t SR;
484  __IO uint32_t DR;
485  __IO uint32_t CRCPR;
486  __IO uint32_t RXCRCR;
487  __IO uint32_t TXCRCR;
488  __IO uint32_t I2SCFGR;
489  __IO uint32_t I2SPR;
490 } SPI_TypeDef;
491 
496 typedef struct
497 {
498  __IO uint32_t CR1;
499  __IO uint32_t CR2;
500  __IO uint32_t SMCR;
501  __IO uint32_t DIER;
502  __IO uint32_t SR;
503  __IO uint32_t EGR;
504  __IO uint32_t CCMR1;
505  __IO uint32_t CCMR2;
506  __IO uint32_t CCER;
507  __IO uint32_t CNT;
508  __IO uint32_t PSC;
509  __IO uint32_t ARR;
510  __IO uint32_t RCR;
511  __IO uint32_t CCR1;
512  __IO uint32_t CCR2;
513  __IO uint32_t CCR3;
514  __IO uint32_t CCR4;
515  __IO uint32_t BDTR;
516  __IO uint32_t DCR;
517  __IO uint32_t DMAR;
518  __IO uint32_t OR;
519 } TIM_TypeDef;
520 
525 typedef struct
526 {
527  __IO uint32_t SR;
528  __IO uint32_t DR;
529  __IO uint32_t BRR;
530  __IO uint32_t CR1;
531  __IO uint32_t CR2;
532  __IO uint32_t CR3;
533  __IO uint32_t GTPR;
534 } USART_TypeDef;
535 
540 typedef struct
541 {
542  __IO uint32_t CR;
543  __IO uint32_t CFR;
544  __IO uint32_t SR;
545 } WWDG_TypeDef;
546 
547 
552 typedef struct
553 {
554  __IO uint32_t CR;
555  __IO uint32_t SR;
556  __IO uint32_t DR;
557 } RNG_TypeDef;
558 
559 
563 typedef struct
564 {
565  __IO uint32_t ISR;
566  __IO uint32_t ICR;
567  __IO uint32_t IER;
568  __IO uint32_t CFGR;
569  __IO uint32_t CR;
570  __IO uint32_t CMP;
571  __IO uint32_t ARR;
572  __IO uint32_t CNT;
573  __IO uint32_t OR;
574 } LPTIM_TypeDef;
575 
579 #define FLASH_BASE 0x08000000U
580 #define SRAM1_BASE 0x20000000U
581 #define PERIPH_BASE 0x40000000U
582 #define SRAM1_BB_BASE 0x22000000U
583 #define PERIPH_BB_BASE 0x42000000U
584 #define FLASH_END 0x0801FFFFU
586 /* Legacy defines */
587 #define SRAM_BASE SRAM1_BASE
588 #define SRAM_BB_BASE SRAM1_BB_BASE
589 
591 #define APB1PERIPH_BASE PERIPH_BASE
592 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
593 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
594 
596 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
597 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
598 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
599 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
600 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
601 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
602 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
603 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
604 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
605 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
606 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
607 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
608 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
609 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
610 
611 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
612 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
613 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
614 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
615 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
616 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
617 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
618 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
619 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
620 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
621 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
622 
624 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
625 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
626 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
627 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
628 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
629 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
630 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
631 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
632 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
633 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
634 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
635 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
636 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
637 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
638 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
639 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
640 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
641 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
642 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
643 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
644 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
645 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
646 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
647 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
648 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
649 #define RNG_BASE (PERIPH_BASE + 0x80000U)
650 
651 /* Debug MCU registers base address */
652 #define DBGMCU_BASE 0xE0042000U
653 
661 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
662 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
663 #define RTC ((RTC_TypeDef *) RTC_BASE)
664 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
665 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
666 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
667 #define USART2 ((USART_TypeDef *) USART2_BASE)
668 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
669 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
670 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
671 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
672 #define PWR ((PWR_TypeDef *) PWR_BASE)
673 #define DAC ((DAC_TypeDef *) DAC_BASE)
674 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
675 #define USART1 ((USART_TypeDef *) USART1_BASE)
676 #define USART6 ((USART_TypeDef *) USART6_BASE)
677 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
678 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
679 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
680 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
681 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
682 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
683 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
684 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
685 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
686 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
687 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
688 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
689 #define CRC ((CRC_TypeDef *) CRC_BASE)
690 #define RCC ((RCC_TypeDef *) RCC_BASE)
691 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
692 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
693 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
694 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
695 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
696 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
697 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
698 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
699 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
700 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
701 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
702 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
703 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
704 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
705 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
706 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
707 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
708 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
709 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
710 #define RNG ((RNG_TypeDef *) RNG_BASE)
711 
712 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
713 
726 /******************************************************************************/
727 /* Peripheral Registers_Bits_Definition */
728 /******************************************************************************/
729 
730 /******************************************************************************/
731 /* */
732 /* Analog to Digital Converter */
733 /* */
734 /******************************************************************************/
735 /******************** Bit definition for ADC_SR register ********************/
736 #define ADC_SR_AWD 0x00000001U
737 #define ADC_SR_EOC 0x00000002U
738 #define ADC_SR_JEOC 0x00000004U
739 #define ADC_SR_JSTRT 0x00000008U
740 #define ADC_SR_STRT 0x00000010U
741 #define ADC_SR_OVR 0x00000020U
743 /******************* Bit definition for ADC_CR1 register ********************/
744 #define ADC_CR1_AWDCH 0x0000001FU
745 #define ADC_CR1_AWDCH_0 0x00000001U
746 #define ADC_CR1_AWDCH_1 0x00000002U
747 #define ADC_CR1_AWDCH_2 0x00000004U
748 #define ADC_CR1_AWDCH_3 0x00000008U
749 #define ADC_CR1_AWDCH_4 0x00000010U
750 #define ADC_CR1_EOCIE 0x00000020U
751 #define ADC_CR1_AWDIE 0x00000040U
752 #define ADC_CR1_JEOCIE 0x00000080U
753 #define ADC_CR1_SCAN 0x00000100U
754 #define ADC_CR1_AWDSGL 0x00000200U
755 #define ADC_CR1_JAUTO 0x00000400U
756 #define ADC_CR1_DISCEN 0x00000800U
757 #define ADC_CR1_JDISCEN 0x00001000U
758 #define ADC_CR1_DISCNUM 0x0000E000U
759 #define ADC_CR1_DISCNUM_0 0x00002000U
760 #define ADC_CR1_DISCNUM_1 0x00004000U
761 #define ADC_CR1_DISCNUM_2 0x00008000U
762 #define ADC_CR1_JAWDEN 0x00400000U
763 #define ADC_CR1_AWDEN 0x00800000U
764 #define ADC_CR1_RES 0x03000000U
765 #define ADC_CR1_RES_0 0x01000000U
766 #define ADC_CR1_RES_1 0x02000000U
767 #define ADC_CR1_OVRIE 0x04000000U
769 /******************* Bit definition for ADC_CR2 register ********************/
770 #define ADC_CR2_ADON 0x00000001U
771 #define ADC_CR2_CONT 0x00000002U
772 #define ADC_CR2_DMA 0x00000100U
773 #define ADC_CR2_DDS 0x00000200U
774 #define ADC_CR2_EOCS 0x00000400U
775 #define ADC_CR2_ALIGN 0x00000800U
776 #define ADC_CR2_JEXTSEL 0x000F0000U
777 #define ADC_CR2_JEXTSEL_0 0x00010000U
778 #define ADC_CR2_JEXTSEL_1 0x00020000U
779 #define ADC_CR2_JEXTSEL_2 0x00040000U
780 #define ADC_CR2_JEXTSEL_3 0x00080000U
781 #define ADC_CR2_JEXTEN 0x00300000U
782 #define ADC_CR2_JEXTEN_0 0x00100000U
783 #define ADC_CR2_JEXTEN_1 0x00200000U
784 #define ADC_CR2_JSWSTART 0x00400000U
785 #define ADC_CR2_EXTSEL 0x0F000000U
786 #define ADC_CR2_EXTSEL_0 0x01000000U
787 #define ADC_CR2_EXTSEL_1 0x02000000U
788 #define ADC_CR2_EXTSEL_2 0x04000000U
789 #define ADC_CR2_EXTSEL_3 0x08000000U
790 #define ADC_CR2_EXTEN 0x30000000U
791 #define ADC_CR2_EXTEN_0 0x10000000U
792 #define ADC_CR2_EXTEN_1 0x20000000U
793 #define ADC_CR2_SWSTART 0x40000000U
795 /****************** Bit definition for ADC_SMPR1 register *******************/
796 #define ADC_SMPR1_SMP10 0x00000007U
797 #define ADC_SMPR1_SMP10_0 0x00000001U
798 #define ADC_SMPR1_SMP10_1 0x00000002U
799 #define ADC_SMPR1_SMP10_2 0x00000004U
800 #define ADC_SMPR1_SMP11 0x00000038U
801 #define ADC_SMPR1_SMP11_0 0x00000008U
802 #define ADC_SMPR1_SMP11_1 0x00000010U
803 #define ADC_SMPR1_SMP11_2 0x00000020U
804 #define ADC_SMPR1_SMP12 0x000001C0U
805 #define ADC_SMPR1_SMP12_0 0x00000040U
806 #define ADC_SMPR1_SMP12_1 0x00000080U
807 #define ADC_SMPR1_SMP12_2 0x00000100U
808 #define ADC_SMPR1_SMP13 0x00000E00U
809 #define ADC_SMPR1_SMP13_0 0x00000200U
810 #define ADC_SMPR1_SMP13_1 0x00000400U
811 #define ADC_SMPR1_SMP13_2 0x00000800U
812 #define ADC_SMPR1_SMP14 0x00007000U
813 #define ADC_SMPR1_SMP14_0 0x00001000U
814 #define ADC_SMPR1_SMP14_1 0x00002000U
815 #define ADC_SMPR1_SMP14_2 0x00004000U
816 #define ADC_SMPR1_SMP15 0x00038000U
817 #define ADC_SMPR1_SMP15_0 0x00008000U
818 #define ADC_SMPR1_SMP15_1 0x00010000U
819 #define ADC_SMPR1_SMP15_2 0x00020000U
820 #define ADC_SMPR1_SMP16 0x001C0000U
821 #define ADC_SMPR1_SMP16_0 0x00040000U
822 #define ADC_SMPR1_SMP16_1 0x00080000U
823 #define ADC_SMPR1_SMP16_2 0x00100000U
824 #define ADC_SMPR1_SMP17 0x00E00000U
825 #define ADC_SMPR1_SMP17_0 0x00200000U
826 #define ADC_SMPR1_SMP17_1 0x00400000U
827 #define ADC_SMPR1_SMP17_2 0x00800000U
828 #define ADC_SMPR1_SMP18 0x07000000U
829 #define ADC_SMPR1_SMP18_0 0x01000000U
830 #define ADC_SMPR1_SMP18_1 0x02000000U
831 #define ADC_SMPR1_SMP18_2 0x04000000U
833 /****************** Bit definition for ADC_SMPR2 register *******************/
834 #define ADC_SMPR2_SMP0 0x00000007U
835 #define ADC_SMPR2_SMP0_0 0x00000001U
836 #define ADC_SMPR2_SMP0_1 0x00000002U
837 #define ADC_SMPR2_SMP0_2 0x00000004U
838 #define ADC_SMPR2_SMP1 0x00000038U
839 #define ADC_SMPR2_SMP1_0 0x00000008U
840 #define ADC_SMPR2_SMP1_1 0x00000010U
841 #define ADC_SMPR2_SMP1_2 0x00000020U
842 #define ADC_SMPR2_SMP2 0x000001C0U
843 #define ADC_SMPR2_SMP2_0 0x00000040U
844 #define ADC_SMPR2_SMP2_1 0x00000080U
845 #define ADC_SMPR2_SMP2_2 0x00000100U
846 #define ADC_SMPR2_SMP3 0x00000E00U
847 #define ADC_SMPR2_SMP3_0 0x00000200U
848 #define ADC_SMPR2_SMP3_1 0x00000400U
849 #define ADC_SMPR2_SMP3_2 0x00000800U
850 #define ADC_SMPR2_SMP4 0x00007000U
851 #define ADC_SMPR2_SMP4_0 0x00001000U
852 #define ADC_SMPR2_SMP4_1 0x00002000U
853 #define ADC_SMPR2_SMP4_2 0x00004000U
854 #define ADC_SMPR2_SMP5 0x00038000U
855 #define ADC_SMPR2_SMP5_0 0x00008000U
856 #define ADC_SMPR2_SMP5_1 0x00010000U
857 #define ADC_SMPR2_SMP5_2 0x00020000U
858 #define ADC_SMPR2_SMP6 0x001C0000U
859 #define ADC_SMPR2_SMP6_0 0x00040000U
860 #define ADC_SMPR2_SMP6_1 0x00080000U
861 #define ADC_SMPR2_SMP6_2 0x00100000U
862 #define ADC_SMPR2_SMP7 0x00E00000U
863 #define ADC_SMPR2_SMP7_0 0x00200000U
864 #define ADC_SMPR2_SMP7_1 0x00400000U
865 #define ADC_SMPR2_SMP7_2 0x00800000U
866 #define ADC_SMPR2_SMP8 0x07000000U
867 #define ADC_SMPR2_SMP8_0 0x01000000U
868 #define ADC_SMPR2_SMP8_1 0x02000000U
869 #define ADC_SMPR2_SMP8_2 0x04000000U
870 #define ADC_SMPR2_SMP9 0x38000000U
871 #define ADC_SMPR2_SMP9_0 0x08000000U
872 #define ADC_SMPR2_SMP9_1 0x10000000U
873 #define ADC_SMPR2_SMP9_2 0x20000000U
875 /****************** Bit definition for ADC_JOFR1 register *******************/
876 #define ADC_JOFR1_JOFFSET1 0x0FFFU
878 /****************** Bit definition for ADC_JOFR2 register *******************/
879 #define ADC_JOFR2_JOFFSET2 0x0FFFU
881 /****************** Bit definition for ADC_JOFR3 register *******************/
882 #define ADC_JOFR3_JOFFSET3 0x0FFFU
884 /****************** Bit definition for ADC_JOFR4 register *******************/
885 #define ADC_JOFR4_JOFFSET4 0x0FFFU
887 /******************* Bit definition for ADC_HTR register ********************/
888 #define ADC_HTR_HT 0x0FFFU
890 /******************* Bit definition for ADC_LTR register ********************/
891 #define ADC_LTR_LT 0x0FFFU
893 /******************* Bit definition for ADC_SQR1 register *******************/
894 #define ADC_SQR1_SQ13 0x0000001FU
895 #define ADC_SQR1_SQ13_0 0x00000001U
896 #define ADC_SQR1_SQ13_1 0x00000002U
897 #define ADC_SQR1_SQ13_2 0x00000004U
898 #define ADC_SQR1_SQ13_3 0x00000008U
899 #define ADC_SQR1_SQ13_4 0x00000010U
900 #define ADC_SQR1_SQ14 0x000003E0U
901 #define ADC_SQR1_SQ14_0 0x00000020U
902 #define ADC_SQR1_SQ14_1 0x00000040U
903 #define ADC_SQR1_SQ14_2 0x00000080U
904 #define ADC_SQR1_SQ14_3 0x00000100U
905 #define ADC_SQR1_SQ14_4 0x00000200U
906 #define ADC_SQR1_SQ15 0x00007C00U
907 #define ADC_SQR1_SQ15_0 0x00000400U
908 #define ADC_SQR1_SQ15_1 0x00000800U
909 #define ADC_SQR1_SQ15_2 0x00001000U
910 #define ADC_SQR1_SQ15_3 0x00002000U
911 #define ADC_SQR1_SQ15_4 0x00004000U
912 #define ADC_SQR1_SQ16 0x000F8000U
913 #define ADC_SQR1_SQ16_0 0x00008000U
914 #define ADC_SQR1_SQ16_1 0x00010000U
915 #define ADC_SQR1_SQ16_2 0x00020000U
916 #define ADC_SQR1_SQ16_3 0x00040000U
917 #define ADC_SQR1_SQ16_4 0x00080000U
918 #define ADC_SQR1_L 0x00F00000U
919 #define ADC_SQR1_L_0 0x00100000U
920 #define ADC_SQR1_L_1 0x00200000U
921 #define ADC_SQR1_L_2 0x00400000U
922 #define ADC_SQR1_L_3 0x00800000U
924 /******************* Bit definition for ADC_SQR2 register *******************/
925 #define ADC_SQR2_SQ7 0x0000001FU
926 #define ADC_SQR2_SQ7_0 0x00000001U
927 #define ADC_SQR2_SQ7_1 0x00000002U
928 #define ADC_SQR2_SQ7_2 0x00000004U
929 #define ADC_SQR2_SQ7_3 0x00000008U
930 #define ADC_SQR2_SQ7_4 0x00000010U
931 #define ADC_SQR2_SQ8 0x000003E0U
932 #define ADC_SQR2_SQ8_0 0x00000020U
933 #define ADC_SQR2_SQ8_1 0x00000040U
934 #define ADC_SQR2_SQ8_2 0x00000080U
935 #define ADC_SQR2_SQ8_3 0x00000100U
936 #define ADC_SQR2_SQ8_4 0x00000200U
937 #define ADC_SQR2_SQ9 0x00007C00U
938 #define ADC_SQR2_SQ9_0 0x00000400U
939 #define ADC_SQR2_SQ9_1 0x00000800U
940 #define ADC_SQR2_SQ9_2 0x00001000U
941 #define ADC_SQR2_SQ9_3 0x00002000U
942 #define ADC_SQR2_SQ9_4 0x00004000U
943 #define ADC_SQR2_SQ10 0x000F8000U
944 #define ADC_SQR2_SQ10_0 0x00008000U
945 #define ADC_SQR2_SQ10_1 0x00010000U
946 #define ADC_SQR2_SQ10_2 0x00020000U
947 #define ADC_SQR2_SQ10_3 0x00040000U
948 #define ADC_SQR2_SQ10_4 0x00080000U
949 #define ADC_SQR2_SQ11 0x01F00000U
950 #define ADC_SQR2_SQ11_0 0x00100000U
951 #define ADC_SQR2_SQ11_1 0x00200000U
952 #define ADC_SQR2_SQ11_2 0x00400000U
953 #define ADC_SQR2_SQ11_3 0x00800000U
954 #define ADC_SQR2_SQ11_4 0x01000000U
955 #define ADC_SQR2_SQ12 0x3E000000U
956 #define ADC_SQR2_SQ12_0 0x02000000U
957 #define ADC_SQR2_SQ12_1 0x04000000U
958 #define ADC_SQR2_SQ12_2 0x08000000U
959 #define ADC_SQR2_SQ12_3 0x10000000U
960 #define ADC_SQR2_SQ12_4 0x20000000U
962 /******************* Bit definition for ADC_SQR3 register *******************/
963 #define ADC_SQR3_SQ1 0x0000001FU
964 #define ADC_SQR3_SQ1_0 0x00000001U
965 #define ADC_SQR3_SQ1_1 0x00000002U
966 #define ADC_SQR3_SQ1_2 0x00000004U
967 #define ADC_SQR3_SQ1_3 0x00000008U
968 #define ADC_SQR3_SQ1_4 0x00000010U
969 #define ADC_SQR3_SQ2 0x000003E0U
970 #define ADC_SQR3_SQ2_0 0x00000020U
971 #define ADC_SQR3_SQ2_1 0x00000040U
972 #define ADC_SQR3_SQ2_2 0x00000080U
973 #define ADC_SQR3_SQ2_3 0x00000100U
974 #define ADC_SQR3_SQ2_4 0x00000200U
975 #define ADC_SQR3_SQ3 0x00007C00U
976 #define ADC_SQR3_SQ3_0 0x00000400U
977 #define ADC_SQR3_SQ3_1 0x00000800U
978 #define ADC_SQR3_SQ3_2 0x00001000U
979 #define ADC_SQR3_SQ3_3 0x00002000U
980 #define ADC_SQR3_SQ3_4 0x00004000U
981 #define ADC_SQR3_SQ4 0x000F8000U
982 #define ADC_SQR3_SQ4_0 0x00008000U
983 #define ADC_SQR3_SQ4_1 0x00010000U
984 #define ADC_SQR3_SQ4_2 0x00020000U
985 #define ADC_SQR3_SQ4_3 0x00040000U
986 #define ADC_SQR3_SQ4_4 0x00080000U
987 #define ADC_SQR3_SQ5 0x01F00000U
988 #define ADC_SQR3_SQ5_0 0x00100000U
989 #define ADC_SQR3_SQ5_1 0x00200000U
990 #define ADC_SQR3_SQ5_2 0x00400000U
991 #define ADC_SQR3_SQ5_3 0x00800000U
992 #define ADC_SQR3_SQ5_4 0x01000000U
993 #define ADC_SQR3_SQ6 0x3E000000U
994 #define ADC_SQR3_SQ6_0 0x02000000U
995 #define ADC_SQR3_SQ6_1 0x04000000U
996 #define ADC_SQR3_SQ6_2 0x08000000U
997 #define ADC_SQR3_SQ6_3 0x10000000U
998 #define ADC_SQR3_SQ6_4 0x20000000U
1000 /******************* Bit definition for ADC_JSQR register *******************/
1001 #define ADC_JSQR_JSQ1 0x0000001FU
1002 #define ADC_JSQR_JSQ1_0 0x00000001U
1003 #define ADC_JSQR_JSQ1_1 0x00000002U
1004 #define ADC_JSQR_JSQ1_2 0x00000004U
1005 #define ADC_JSQR_JSQ1_3 0x00000008U
1006 #define ADC_JSQR_JSQ1_4 0x00000010U
1007 #define ADC_JSQR_JSQ2 0x000003E0U
1008 #define ADC_JSQR_JSQ2_0 0x00000020U
1009 #define ADC_JSQR_JSQ2_1 0x00000040U
1010 #define ADC_JSQR_JSQ2_2 0x00000080U
1011 #define ADC_JSQR_JSQ2_3 0x00000100U
1012 #define ADC_JSQR_JSQ2_4 0x00000200U
1013 #define ADC_JSQR_JSQ3 0x00007C00U
1014 #define ADC_JSQR_JSQ3_0 0x00000400U
1015 #define ADC_JSQR_JSQ3_1 0x00000800U
1016 #define ADC_JSQR_JSQ3_2 0x00001000U
1017 #define ADC_JSQR_JSQ3_3 0x00002000U
1018 #define ADC_JSQR_JSQ3_4 0x00004000U
1019 #define ADC_JSQR_JSQ4 0x000F8000U
1020 #define ADC_JSQR_JSQ4_0 0x00008000U
1021 #define ADC_JSQR_JSQ4_1 0x00010000U
1022 #define ADC_JSQR_JSQ4_2 0x00020000U
1023 #define ADC_JSQR_JSQ4_3 0x00040000U
1024 #define ADC_JSQR_JSQ4_4 0x00080000U
1025 #define ADC_JSQR_JL 0x00300000U
1026 #define ADC_JSQR_JL_0 0x00100000U
1027 #define ADC_JSQR_JL_1 0x00200000U
1029 /******************* Bit definition for ADC_JDR1 register *******************/
1030 #define ADC_JDR1_JDATA 0xFFFFU
1032 /******************* Bit definition for ADC_JDR2 register *******************/
1033 #define ADC_JDR2_JDATA 0xFFFFU
1035 /******************* Bit definition for ADC_JDR3 register *******************/
1036 #define ADC_JDR3_JDATA 0xFFFFU
1038 /******************* Bit definition for ADC_JDR4 register *******************/
1039 #define ADC_JDR4_JDATA 0xFFFFU
1041 /******************** Bit definition for ADC_DR register ********************/
1042 #define ADC_DR_DATA 0x0000FFFFU
1043 #define ADC_DR_ADC2DATA 0xFFFF0000U
1045 /******************* Bit definition for ADC_CSR register ********************/
1046 #define ADC_CSR_AWD1 0x00000001U
1047 #define ADC_CSR_EOC1 0x00000002U
1048 #define ADC_CSR_JEOC1 0x00000004U
1049 #define ADC_CSR_JSTRT1 0x00000008U
1050 #define ADC_CSR_STRT1 0x00000010U
1051 #define ADC_CSR_OVR1 0x00000020U
1052 #define ADC_CSR_AWD2 0x00000100U
1053 #define ADC_CSR_EOC2 0x00000200U
1054 #define ADC_CSR_JEOC2 0x00000400U
1055 #define ADC_CSR_JSTRT2 0x00000800U
1056 #define ADC_CSR_STRT2 0x00001000U
1057 #define ADC_CSR_OVR2 0x00002000U
1058 #define ADC_CSR_AWD3 0x00010000U
1059 #define ADC_CSR_EOC3 0x00020000U
1060 #define ADC_CSR_JEOC3 0x00040000U
1061 #define ADC_CSR_JSTRT3 0x00080000U
1062 #define ADC_CSR_STRT3 0x00100000U
1063 #define ADC_CSR_OVR3 0x00200000U
1065 /* Legacy defines */
1066 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1067 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1068 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1069 
1070 /******************* Bit definition for ADC_CCR register ********************/
1071 #define ADC_CCR_MULTI 0x0000001FU
1072 #define ADC_CCR_MULTI_0 0x00000001U
1073 #define ADC_CCR_MULTI_1 0x00000002U
1074 #define ADC_CCR_MULTI_2 0x00000004U
1075 #define ADC_CCR_MULTI_3 0x00000008U
1076 #define ADC_CCR_MULTI_4 0x00000010U
1077 #define ADC_CCR_DELAY 0x00000F00U
1078 #define ADC_CCR_DELAY_0 0x00000100U
1079 #define ADC_CCR_DELAY_1 0x00000200U
1080 #define ADC_CCR_DELAY_2 0x00000400U
1081 #define ADC_CCR_DELAY_3 0x00000800U
1082 #define ADC_CCR_DDS 0x00002000U
1083 #define ADC_CCR_DMA 0x0000C000U
1084 #define ADC_CCR_DMA_0 0x00004000U
1085 #define ADC_CCR_DMA_1 0x00008000U
1086 #define ADC_CCR_ADCPRE 0x00030000U
1087 #define ADC_CCR_ADCPRE_0 0x00010000U
1088 #define ADC_CCR_ADCPRE_1 0x00020000U
1089 #define ADC_CCR_VBATE 0x00400000U
1090 #define ADC_CCR_TSVREFE 0x00800000U
1092 /******************* Bit definition for ADC_CDR register ********************/
1093 #define ADC_CDR_DATA1 0x0000FFFFU
1094 #define ADC_CDR_DATA2 0xFFFF0000U
1096 /******************************************************************************/
1097 /* */
1098 /* CRC calculation unit */
1099 /* */
1100 /******************************************************************************/
1101 /******************* Bit definition for CRC_DR register *********************/
1102 #define CRC_DR_DR 0xFFFFFFFFU
1105 /******************* Bit definition for CRC_IDR register ********************/
1106 #define CRC_IDR_IDR 0xFFU
1109 /******************** Bit definition for CRC_CR register ********************/
1110 #define CRC_CR_RESET 0x01U
1112 /******************************************************************************/
1113 /* */
1114 /* Debug MCU */
1115 /* */
1116 /******************************************************************************/
1117 
1118 /******************************************************************************/
1119 /* */
1120 /* DMA Controller */
1121 /* */
1122 /******************************************************************************/
1123 /******************** Bits definition for DMA_SxCR register *****************/
1124 #define DMA_SxCR_CHSEL 0x0E000000U
1125 #define DMA_SxCR_CHSEL_0 0x02000000U
1126 #define DMA_SxCR_CHSEL_1 0x04000000U
1127 #define DMA_SxCR_CHSEL_2 0x08000000U
1128 #define DMA_SxCR_MBURST 0x01800000U
1129 #define DMA_SxCR_MBURST_0 0x00800000U
1130 #define DMA_SxCR_MBURST_1 0x01000000U
1131 #define DMA_SxCR_PBURST 0x00600000U
1132 #define DMA_SxCR_PBURST_0 0x00200000U
1133 #define DMA_SxCR_PBURST_1 0x00400000U
1134 #define DMA_SxCR_CT 0x00080000U
1135 #define DMA_SxCR_DBM 0x00040000U
1136 #define DMA_SxCR_PL 0x00030000U
1137 #define DMA_SxCR_PL_0 0x00010000U
1138 #define DMA_SxCR_PL_1 0x00020000U
1139 #define DMA_SxCR_PINCOS 0x00008000U
1140 #define DMA_SxCR_MSIZE 0x00006000U
1141 #define DMA_SxCR_MSIZE_0 0x00002000U
1142 #define DMA_SxCR_MSIZE_1 0x00004000U
1143 #define DMA_SxCR_PSIZE 0x00001800U
1144 #define DMA_SxCR_PSIZE_0 0x00000800U
1145 #define DMA_SxCR_PSIZE_1 0x00001000U
1146 #define DMA_SxCR_MINC 0x00000400U
1147 #define DMA_SxCR_PINC 0x00000200U
1148 #define DMA_SxCR_CIRC 0x00000100U
1149 #define DMA_SxCR_DIR 0x000000C0U
1150 #define DMA_SxCR_DIR_0 0x00000040U
1151 #define DMA_SxCR_DIR_1 0x00000080U
1152 #define DMA_SxCR_PFCTRL 0x00000020U
1153 #define DMA_SxCR_TCIE 0x00000010U
1154 #define DMA_SxCR_HTIE 0x00000008U
1155 #define DMA_SxCR_TEIE 0x00000004U
1156 #define DMA_SxCR_DMEIE 0x00000002U
1157 #define DMA_SxCR_EN 0x00000001U
1158 
1159 /* Legacy defines */
1160 #define DMA_SxCR_ACK 0x00100000U
1161 
1162 /******************** Bits definition for DMA_SxCNDTR register **************/
1163 #define DMA_SxNDT 0x0000FFFFU
1164 #define DMA_SxNDT_0 0x00000001U
1165 #define DMA_SxNDT_1 0x00000002U
1166 #define DMA_SxNDT_2 0x00000004U
1167 #define DMA_SxNDT_3 0x00000008U
1168 #define DMA_SxNDT_4 0x00000010U
1169 #define DMA_SxNDT_5 0x00000020U
1170 #define DMA_SxNDT_6 0x00000040U
1171 #define DMA_SxNDT_7 0x00000080U
1172 #define DMA_SxNDT_8 0x00000100U
1173 #define DMA_SxNDT_9 0x00000200U
1174 #define DMA_SxNDT_10 0x00000400U
1175 #define DMA_SxNDT_11 0x00000800U
1176 #define DMA_SxNDT_12 0x00001000U
1177 #define DMA_SxNDT_13 0x00002000U
1178 #define DMA_SxNDT_14 0x00004000U
1179 #define DMA_SxNDT_15 0x00008000U
1180 
1181 /******************** Bits definition for DMA_SxFCR register ****************/
1182 #define DMA_SxFCR_FEIE 0x00000080U
1183 #define DMA_SxFCR_FS 0x00000038U
1184 #define DMA_SxFCR_FS_0 0x00000008U
1185 #define DMA_SxFCR_FS_1 0x00000010U
1186 #define DMA_SxFCR_FS_2 0x00000020U
1187 #define DMA_SxFCR_DMDIS 0x00000004U
1188 #define DMA_SxFCR_FTH 0x00000003U
1189 #define DMA_SxFCR_FTH_0 0x00000001U
1190 #define DMA_SxFCR_FTH_1 0x00000002U
1191 
1192 /******************** Bits definition for DMA_LISR register *****************/
1193 #define DMA_LISR_TCIF3 0x08000000U
1194 #define DMA_LISR_HTIF3 0x04000000U
1195 #define DMA_LISR_TEIF3 0x02000000U
1196 #define DMA_LISR_DMEIF3 0x01000000U
1197 #define DMA_LISR_FEIF3 0x00400000U
1198 #define DMA_LISR_TCIF2 0x00200000U
1199 #define DMA_LISR_HTIF2 0x00100000U
1200 #define DMA_LISR_TEIF2 0x00080000U
1201 #define DMA_LISR_DMEIF2 0x00040000U
1202 #define DMA_LISR_FEIF2 0x00010000U
1203 #define DMA_LISR_TCIF1 0x00000800U
1204 #define DMA_LISR_HTIF1 0x00000400U
1205 #define DMA_LISR_TEIF1 0x00000200U
1206 #define DMA_LISR_DMEIF1 0x00000100U
1207 #define DMA_LISR_FEIF1 0x00000040U
1208 #define DMA_LISR_TCIF0 0x00000020U
1209 #define DMA_LISR_HTIF0 0x00000010U
1210 #define DMA_LISR_TEIF0 0x00000008U
1211 #define DMA_LISR_DMEIF0 0x00000004U
1212 #define DMA_LISR_FEIF0 0x00000001U
1213 
1214 /******************** Bits definition for DMA_HISR register *****************/
1215 #define DMA_HISR_TCIF7 0x08000000U
1216 #define DMA_HISR_HTIF7 0x04000000U
1217 #define DMA_HISR_TEIF7 0x02000000U
1218 #define DMA_HISR_DMEIF7 0x01000000U
1219 #define DMA_HISR_FEIF7 0x00400000U
1220 #define DMA_HISR_TCIF6 0x00200000U
1221 #define DMA_HISR_HTIF6 0x00100000U
1222 #define DMA_HISR_TEIF6 0x00080000U
1223 #define DMA_HISR_DMEIF6 0x00040000U
1224 #define DMA_HISR_FEIF6 0x00010000U
1225 #define DMA_HISR_TCIF5 0x00000800U
1226 #define DMA_HISR_HTIF5 0x00000400U
1227 #define DMA_HISR_TEIF5 0x00000200U
1228 #define DMA_HISR_DMEIF5 0x00000100U
1229 #define DMA_HISR_FEIF5 0x00000040U
1230 #define DMA_HISR_TCIF4 0x00000020U
1231 #define DMA_HISR_HTIF4 0x00000010U
1232 #define DMA_HISR_TEIF4 0x00000008U
1233 #define DMA_HISR_DMEIF4 0x00000004U
1234 #define DMA_HISR_FEIF4 0x00000001U
1235 
1236 /******************** Bits definition for DMA_LIFCR register ****************/
1237 #define DMA_LIFCR_CTCIF3 0x08000000U
1238 #define DMA_LIFCR_CHTIF3 0x04000000U
1239 #define DMA_LIFCR_CTEIF3 0x02000000U
1240 #define DMA_LIFCR_CDMEIF3 0x01000000U
1241 #define DMA_LIFCR_CFEIF3 0x00400000U
1242 #define DMA_LIFCR_CTCIF2 0x00200000U
1243 #define DMA_LIFCR_CHTIF2 0x00100000U
1244 #define DMA_LIFCR_CTEIF2 0x00080000U
1245 #define DMA_LIFCR_CDMEIF2 0x00040000U
1246 #define DMA_LIFCR_CFEIF2 0x00010000U
1247 #define DMA_LIFCR_CTCIF1 0x00000800U
1248 #define DMA_LIFCR_CHTIF1 0x00000400U
1249 #define DMA_LIFCR_CTEIF1 0x00000200U
1250 #define DMA_LIFCR_CDMEIF1 0x00000100U
1251 #define DMA_LIFCR_CFEIF1 0x00000040U
1252 #define DMA_LIFCR_CTCIF0 0x00000020U
1253 #define DMA_LIFCR_CHTIF0 0x00000010U
1254 #define DMA_LIFCR_CTEIF0 0x00000008U
1255 #define DMA_LIFCR_CDMEIF0 0x00000004U
1256 #define DMA_LIFCR_CFEIF0 0x00000001U
1257 
1258 /******************** Bits definition for DMA_HIFCR register ****************/
1259 #define DMA_HIFCR_CTCIF7 0x08000000U
1260 #define DMA_HIFCR_CHTIF7 0x04000000U
1261 #define DMA_HIFCR_CTEIF7 0x02000000U
1262 #define DMA_HIFCR_CDMEIF7 0x01000000U
1263 #define DMA_HIFCR_CFEIF7 0x00400000U
1264 #define DMA_HIFCR_CTCIF6 0x00200000U
1265 #define DMA_HIFCR_CHTIF6 0x00100000U
1266 #define DMA_HIFCR_CTEIF6 0x00080000U
1267 #define DMA_HIFCR_CDMEIF6 0x00040000U
1268 #define DMA_HIFCR_CFEIF6 0x00010000U
1269 #define DMA_HIFCR_CTCIF5 0x00000800U
1270 #define DMA_HIFCR_CHTIF5 0x00000400U
1271 #define DMA_HIFCR_CTEIF5 0x00000200U
1272 #define DMA_HIFCR_CDMEIF5 0x00000100U
1273 #define DMA_HIFCR_CFEIF5 0x00000040U
1274 #define DMA_HIFCR_CTCIF4 0x00000020U
1275 #define DMA_HIFCR_CHTIF4 0x00000010U
1276 #define DMA_HIFCR_CTEIF4 0x00000008U
1277 #define DMA_HIFCR_CDMEIF4 0x00000004U
1278 #define DMA_HIFCR_CFEIF4 0x00000001U
1279 
1280 
1281 /******************************************************************************/
1282 /* */
1283 /* External Interrupt/Event Controller */
1284 /* */
1285 /******************************************************************************/
1286 /******************* Bit definition for EXTI_IMR register *******************/
1287 #define EXTI_IMR_MR0 0x00000001U
1288 #define EXTI_IMR_MR1 0x00000002U
1289 #define EXTI_IMR_MR2 0x00000004U
1290 #define EXTI_IMR_MR3 0x00000008U
1291 #define EXTI_IMR_MR4 0x00000010U
1292 #define EXTI_IMR_MR5 0x00000020U
1293 #define EXTI_IMR_MR6 0x00000040U
1294 #define EXTI_IMR_MR7 0x00000080U
1295 #define EXTI_IMR_MR8 0x00000100U
1296 #define EXTI_IMR_MR9 0x00000200U
1297 #define EXTI_IMR_MR10 0x00000400U
1298 #define EXTI_IMR_MR11 0x00000800U
1299 #define EXTI_IMR_MR12 0x00001000U
1300 #define EXTI_IMR_MR13 0x00002000U
1301 #define EXTI_IMR_MR14 0x00004000U
1302 #define EXTI_IMR_MR15 0x00008000U
1303 #define EXTI_IMR_MR16 0x00010000U
1304 #define EXTI_IMR_MR17 0x00020000U
1305 #define EXTI_IMR_MR18 0x00040000U
1306 #define EXTI_IMR_MR19 0x00080000U
1307 #define EXTI_IMR_MR20 0x00100000U
1308 #define EXTI_IMR_MR21 0x00200000U
1309 #define EXTI_IMR_MR22 0x00400000U
1310 #define EXTI_IMR_MR23 0x00800000U
1312 /******************* Bit definition for EXTI_EMR register *******************/
1313 #define EXTI_EMR_MR0 0x00000001U
1314 #define EXTI_EMR_MR1 0x00000002U
1315 #define EXTI_EMR_MR2 0x00000004U
1316 #define EXTI_EMR_MR3 0x00000008U
1317 #define EXTI_EMR_MR4 0x00000010U
1318 #define EXTI_EMR_MR5 0x00000020U
1319 #define EXTI_EMR_MR6 0x00000040U
1320 #define EXTI_EMR_MR7 0x00000080U
1321 #define EXTI_EMR_MR8 0x00000100U
1322 #define EXTI_EMR_MR9 0x00000200U
1323 #define EXTI_EMR_MR10 0x00000400U
1324 #define EXTI_EMR_MR11 0x00000800U
1325 #define EXTI_EMR_MR12 0x00001000U
1326 #define EXTI_EMR_MR13 0x00002000U
1327 #define EXTI_EMR_MR14 0x00004000U
1328 #define EXTI_EMR_MR15 0x00008000U
1329 #define EXTI_EMR_MR16 0x00010000U
1330 #define EXTI_EMR_MR17 0x00020000U
1331 #define EXTI_EMR_MR18 0x00040000U
1332 #define EXTI_EMR_MR19 0x00080000U
1333 #define EXTI_EMR_MR20 0x00100000U
1334 #define EXTI_EMR_MR21 0x00200000U
1335 #define EXTI_EMR_MR22 0x00400000U
1336 #define EXTI_EMR_MR23 0x00800000U
1338 /****************** Bit definition for EXTI_RTSR register *******************/
1339 #define EXTI_RTSR_TR0 0x00000001U
1340 #define EXTI_RTSR_TR1 0x00000002U
1341 #define EXTI_RTSR_TR2 0x00000004U
1342 #define EXTI_RTSR_TR3 0x00000008U
1343 #define EXTI_RTSR_TR4 0x00000010U
1344 #define EXTI_RTSR_TR5 0x00000020U
1345 #define EXTI_RTSR_TR6 0x00000040U
1346 #define EXTI_RTSR_TR7 0x00000080U
1347 #define EXTI_RTSR_TR8 0x00000100U
1348 #define EXTI_RTSR_TR9 0x00000200U
1349 #define EXTI_RTSR_TR10 0x00000400U
1350 #define EXTI_RTSR_TR11 0x00000800U
1351 #define EXTI_RTSR_TR12 0x00001000U
1352 #define EXTI_RTSR_TR13 0x00002000U
1353 #define EXTI_RTSR_TR14 0x00004000U
1354 #define EXTI_RTSR_TR15 0x00008000U
1355 #define EXTI_RTSR_TR16 0x00010000U
1356 #define EXTI_RTSR_TR17 0x00020000U
1357 #define EXTI_RTSR_TR18 0x00040000U
1358 #define EXTI_RTSR_TR19 0x00080000U
1359 #define EXTI_RTSR_TR20 0x00100000U
1360 #define EXTI_RTSR_TR21 0x00200000U
1361 #define EXTI_RTSR_TR22 0x00400000U
1362 #define EXTI_RTSR_TR23 0x00800000U
1364 /****************** Bit definition for EXTI_FTSR register *******************/
1365 #define EXTI_FTSR_TR0 0x00000001U
1366 #define EXTI_FTSR_TR1 0x00000002U
1367 #define EXTI_FTSR_TR2 0x00000004U
1368 #define EXTI_FTSR_TR3 0x00000008U
1369 #define EXTI_FTSR_TR4 0x00000010U
1370 #define EXTI_FTSR_TR5 0x00000020U
1371 #define EXTI_FTSR_TR6 0x00000040U
1372 #define EXTI_FTSR_TR7 0x00000080U
1373 #define EXTI_FTSR_TR8 0x00000100U
1374 #define EXTI_FTSR_TR9 0x00000200U
1375 #define EXTI_FTSR_TR10 0x00000400U
1376 #define EXTI_FTSR_TR11 0x00000800U
1377 #define EXTI_FTSR_TR12 0x00001000U
1378 #define EXTI_FTSR_TR13 0x00002000U
1379 #define EXTI_FTSR_TR14 0x00004000U
1380 #define EXTI_FTSR_TR15 0x00008000U
1381 #define EXTI_FTSR_TR16 0x00010000U
1382 #define EXTI_FTSR_TR17 0x00020000U
1383 #define EXTI_FTSR_TR18 0x00040000U
1384 #define EXTI_FTSR_TR19 0x00080000U
1385 #define EXTI_FTSR_TR20 0x00100000U
1386 #define EXTI_FTSR_TR21 0x00200000U
1387 #define EXTI_FTSR_TR22 0x00400000U
1388 #define EXTI_FTSR_TR23 0x00800000U
1390 /****************** Bit definition for EXTI_SWIER register ******************/
1391 #define EXTI_SWIER_SWIER0 0x00000001U
1392 #define EXTI_SWIER_SWIER1 0x00000002U
1393 #define EXTI_SWIER_SWIER2 0x00000004U
1394 #define EXTI_SWIER_SWIER3 0x00000008U
1395 #define EXTI_SWIER_SWIER4 0x00000010U
1396 #define EXTI_SWIER_SWIER5 0x00000020U
1397 #define EXTI_SWIER_SWIER6 0x00000040U
1398 #define EXTI_SWIER_SWIER7 0x00000080U
1399 #define EXTI_SWIER_SWIER8 0x00000100U
1400 #define EXTI_SWIER_SWIER9 0x00000200U
1401 #define EXTI_SWIER_SWIER10 0x00000400U
1402 #define EXTI_SWIER_SWIER11 0x00000800U
1403 #define EXTI_SWIER_SWIER12 0x00001000U
1404 #define EXTI_SWIER_SWIER13 0x00002000U
1405 #define EXTI_SWIER_SWIER14 0x00004000U
1406 #define EXTI_SWIER_SWIER15 0x00008000U
1407 #define EXTI_SWIER_SWIER16 0x00010000U
1408 #define EXTI_SWIER_SWIER17 0x00020000U
1409 #define EXTI_SWIER_SWIER18 0x00040000U
1410 #define EXTI_SWIER_SWIER19 0x00080000U
1411 #define EXTI_SWIER_SWIER20 0x00100000U
1412 #define EXTI_SWIER_SWIER21 0x00200000U
1413 #define EXTI_SWIER_SWIER22 0x00400000U
1414 #define EXTI_SWIER_SWIER23 0x00800000U
1416 /******************* Bit definition for EXTI_PR register ********************/
1417 #define EXTI_PR_PR0 0x00000001U
1418 #define EXTI_PR_PR1 0x00000002U
1419 #define EXTI_PR_PR2 0x00000004U
1420 #define EXTI_PR_PR3 0x00000008U
1421 #define EXTI_PR_PR4 0x00000010U
1422 #define EXTI_PR_PR5 0x00000020U
1423 #define EXTI_PR_PR6 0x00000040U
1424 #define EXTI_PR_PR7 0x00000080U
1425 #define EXTI_PR_PR8 0x00000100U
1426 #define EXTI_PR_PR9 0x00000200U
1427 #define EXTI_PR_PR10 0x00000400U
1428 #define EXTI_PR_PR11 0x00000800U
1429 #define EXTI_PR_PR12 0x00001000U
1430 #define EXTI_PR_PR13 0x00002000U
1431 #define EXTI_PR_PR14 0x00004000U
1432 #define EXTI_PR_PR15 0x00008000U
1433 #define EXTI_PR_PR16 0x00010000U
1434 #define EXTI_PR_PR17 0x00020000U
1435 #define EXTI_PR_PR18 0x00040000U
1436 #define EXTI_PR_PR19 0x00080000U
1437 #define EXTI_PR_PR20 0x00100000U
1438 #define EXTI_PR_PR21 0x00200000U
1439 #define EXTI_PR_PR22 0x00400000U
1440 #define EXTI_PR_PR23 0x00800000U
1442 /******************************************************************************/
1443 /* */
1444 /* FLASH */
1445 /* */
1446 /******************************************************************************/
1447 /******************* Bits definition for FLASH_ACR register *****************/
1448 #define FLASH_ACR_LATENCY 0x0000000FU
1449 #define FLASH_ACR_LATENCY_0WS 0x00000000U
1450 #define FLASH_ACR_LATENCY_1WS 0x00000001U
1451 #define FLASH_ACR_LATENCY_2WS 0x00000002U
1452 #define FLASH_ACR_LATENCY_3WS 0x00000003U
1453 #define FLASH_ACR_LATENCY_4WS 0x00000004U
1454 #define FLASH_ACR_LATENCY_5WS 0x00000005U
1455 #define FLASH_ACR_LATENCY_6WS 0x00000006U
1456 #define FLASH_ACR_LATENCY_7WS 0x00000007U
1457 
1458 #define FLASH_ACR_PRFTEN 0x00000100U
1459 #define FLASH_ACR_ICEN 0x00000200U
1460 #define FLASH_ACR_DCEN 0x00000400U
1461 #define FLASH_ACR_ICRST 0x00000800U
1462 #define FLASH_ACR_DCRST 0x00001000U
1463 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
1464 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
1465 
1466 /******************* Bits definition for FLASH_SR register ******************/
1467 #define FLASH_SR_EOP 0x00000001U
1468 #define FLASH_SR_SOP 0x00000002U
1469 #define FLASH_SR_WRPERR 0x00000010U
1470 #define FLASH_SR_PGAERR 0x00000020U
1471 #define FLASH_SR_PGPERR 0x00000040U
1472 #define FLASH_SR_PGSERR 0x00000080U
1473 #define FLASH_SR_BSY 0x00010000U
1474 
1475 /******************* Bits definition for FLASH_CR register ******************/
1476 #define FLASH_CR_PG 0x00000001U
1477 #define FLASH_CR_SER 0x00000002U
1478 #define FLASH_CR_MER 0x00000004U
1479 #define FLASH_CR_SNB 0x000000F8U
1480 #define FLASH_CR_SNB_0 0x00000008U
1481 #define FLASH_CR_SNB_1 0x00000010U
1482 #define FLASH_CR_SNB_2 0x00000020U
1483 #define FLASH_CR_SNB_3 0x00000040U
1484 #define FLASH_CR_SNB_4 0x00000080U
1485 #define FLASH_CR_PSIZE 0x00000300U
1486 #define FLASH_CR_PSIZE_0 0x00000100U
1487 #define FLASH_CR_PSIZE_1 0x00000200U
1488 #define FLASH_CR_STRT 0x00010000U
1489 #define FLASH_CR_EOPIE 0x01000000U
1490 #define FLASH_CR_LOCK 0x80000000U
1491 
1492 /******************* Bits definition for FLASH_OPTCR register ***************/
1493 #define FLASH_OPTCR_OPTLOCK 0x00000001U
1494 #define FLASH_OPTCR_OPTSTRT 0x00000002U
1495 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
1496 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
1497 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
1498 
1499 #define FLASH_OPTCR_WDG_SW 0x00000020U
1500 #define FLASH_OPTCR_nRST_STOP 0x00000040U
1501 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
1502 #define FLASH_OPTCR_RDP 0x0000FF00U
1503 #define FLASH_OPTCR_RDP_0 0x00000100U
1504 #define FLASH_OPTCR_RDP_1 0x00000200U
1505 #define FLASH_OPTCR_RDP_2 0x00000400U
1506 #define FLASH_OPTCR_RDP_3 0x00000800U
1507 #define FLASH_OPTCR_RDP_4 0x00001000U
1508 #define FLASH_OPTCR_RDP_5 0x00002000U
1509 #define FLASH_OPTCR_RDP_6 0x00004000U
1510 #define FLASH_OPTCR_RDP_7 0x00008000U
1511 #define FLASH_OPTCR_nWRP 0x0FFF0000U
1512 #define FLASH_OPTCR_nWRP_0 0x00010000U
1513 #define FLASH_OPTCR_nWRP_1 0x00020000U
1514 #define FLASH_OPTCR_nWRP_2 0x00040000U
1515 #define FLASH_OPTCR_nWRP_3 0x00080000U
1516 #define FLASH_OPTCR_nWRP_4 0x00100000U
1517 #define FLASH_OPTCR_nWRP_5 0x00200000U
1518 #define FLASH_OPTCR_nWRP_6 0x00400000U
1519 #define FLASH_OPTCR_nWRP_7 0x00800000U
1520 #define FLASH_OPTCR_nWRP_8 0x01000000U
1521 #define FLASH_OPTCR_nWRP_9 0x02000000U
1522 #define FLASH_OPTCR_nWRP_10 0x04000000U
1523 #define FLASH_OPTCR_nWRP_11 0x08000000U
1524 
1525 /****************** Bits definition for FLASH_OPTCR1 register ***************/
1526 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
1527 #define FLASH_OPTCR1_nWRP_0 0x00010000U
1528 #define FLASH_OPTCR1_nWRP_1 0x00020000U
1529 #define FLASH_OPTCR1_nWRP_2 0x00040000U
1530 #define FLASH_OPTCR1_nWRP_3 0x00080000U
1531 #define FLASH_OPTCR1_nWRP_4 0x00100000U
1532 #define FLASH_OPTCR1_nWRP_5 0x00200000U
1533 #define FLASH_OPTCR1_nWRP_6 0x00400000U
1534 #define FLASH_OPTCR1_nWRP_7 0x00800000U
1535 #define FLASH_OPTCR1_nWRP_8 0x01000000U
1536 #define FLASH_OPTCR1_nWRP_9 0x02000000U
1537 #define FLASH_OPTCR1_nWRP_10 0x04000000U
1538 #define FLASH_OPTCR1_nWRP_11 0x08000000U
1539 
1540 /******************************************************************************/
1541 /* */
1542 /* General Purpose I/O */
1543 /* */
1544 /******************************************************************************/
1545 /****************** Bits definition for GPIO_MODER register *****************/
1546 #define GPIO_MODER_MODER0 0x00000003U
1547 #define GPIO_MODER_MODER0_0 0x00000001U
1548 #define GPIO_MODER_MODER0_1 0x00000002U
1549 
1550 #define GPIO_MODER_MODER1 0x0000000CU
1551 #define GPIO_MODER_MODER1_0 0x00000004U
1552 #define GPIO_MODER_MODER1_1 0x00000008U
1553 
1554 #define GPIO_MODER_MODER2 0x00000030U
1555 #define GPIO_MODER_MODER2_0 0x00000010U
1556 #define GPIO_MODER_MODER2_1 0x00000020U
1557 
1558 #define GPIO_MODER_MODER3 0x000000C0U
1559 #define GPIO_MODER_MODER3_0 0x00000040U
1560 #define GPIO_MODER_MODER3_1 0x00000080U
1561 
1562 #define GPIO_MODER_MODER4 0x00000300U
1563 #define GPIO_MODER_MODER4_0 0x00000100U
1564 #define GPIO_MODER_MODER4_1 0x00000200U
1565 
1566 #define GPIO_MODER_MODER5 0x00000C00U
1567 #define GPIO_MODER_MODER5_0 0x00000400U
1568 #define GPIO_MODER_MODER5_1 0x00000800U
1569 
1570 #define GPIO_MODER_MODER6 0x00003000U
1571 #define GPIO_MODER_MODER6_0 0x00001000U
1572 #define GPIO_MODER_MODER6_1 0x00002000U
1573 
1574 #define GPIO_MODER_MODER7 0x0000C000U
1575 #define GPIO_MODER_MODER7_0 0x00004000U
1576 #define GPIO_MODER_MODER7_1 0x00008000U
1577 
1578 #define GPIO_MODER_MODER8 0x00030000U
1579 #define GPIO_MODER_MODER8_0 0x00010000U
1580 #define GPIO_MODER_MODER8_1 0x00020000U
1581 
1582 #define GPIO_MODER_MODER9 0x000C0000U
1583 #define GPIO_MODER_MODER9_0 0x00040000U
1584 #define GPIO_MODER_MODER9_1 0x00080000U
1585 
1586 #define GPIO_MODER_MODER10 0x00300000U
1587 #define GPIO_MODER_MODER10_0 0x00100000U
1588 #define GPIO_MODER_MODER10_1 0x00200000U
1589 
1590 #define GPIO_MODER_MODER11 0x00C00000U
1591 #define GPIO_MODER_MODER11_0 0x00400000U
1592 #define GPIO_MODER_MODER11_1 0x00800000U
1593 
1594 #define GPIO_MODER_MODER12 0x03000000U
1595 #define GPIO_MODER_MODER12_0 0x01000000U
1596 #define GPIO_MODER_MODER12_1 0x02000000U
1597 
1598 #define GPIO_MODER_MODER13 0x0C000000U
1599 #define GPIO_MODER_MODER13_0 0x04000000U
1600 #define GPIO_MODER_MODER13_1 0x08000000U
1601 
1602 #define GPIO_MODER_MODER14 0x30000000U
1603 #define GPIO_MODER_MODER14_0 0x10000000U
1604 #define GPIO_MODER_MODER14_1 0x20000000U
1605 
1606 #define GPIO_MODER_MODER15 0xC0000000U
1607 #define GPIO_MODER_MODER15_0 0x40000000U
1608 #define GPIO_MODER_MODER15_1 0x80000000U
1609 
1610 /****************** Bits definition for GPIO_OTYPER register ****************/
1611 #define GPIO_OTYPER_OT_0 0x00000001U
1612 #define GPIO_OTYPER_OT_1 0x00000002U
1613 #define GPIO_OTYPER_OT_2 0x00000004U
1614 #define GPIO_OTYPER_OT_3 0x00000008U
1615 #define GPIO_OTYPER_OT_4 0x00000010U
1616 #define GPIO_OTYPER_OT_5 0x00000020U
1617 #define GPIO_OTYPER_OT_6 0x00000040U
1618 #define GPIO_OTYPER_OT_7 0x00000080U
1619 #define GPIO_OTYPER_OT_8 0x00000100U
1620 #define GPIO_OTYPER_OT_9 0x00000200U
1621 #define GPIO_OTYPER_OT_10 0x00000400U
1622 #define GPIO_OTYPER_OT_11 0x00000800U
1623 #define GPIO_OTYPER_OT_12 0x00001000U
1624 #define GPIO_OTYPER_OT_13 0x00002000U
1625 #define GPIO_OTYPER_OT_14 0x00004000U
1626 #define GPIO_OTYPER_OT_15 0x00008000U
1627 
1628 /****************** Bits definition for GPIO_OSPEEDR register ***************/
1629 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
1630 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
1631 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
1632 
1633 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
1634 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
1635 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
1636 
1637 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
1638 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
1639 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
1640 
1641 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
1642 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
1643 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
1644 
1645 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
1646 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
1647 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
1648 
1649 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
1650 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
1651 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
1652 
1653 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
1654 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
1655 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
1656 
1657 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
1658 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
1659 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
1660 
1661 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
1662 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
1663 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
1664 
1665 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
1666 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
1667 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
1668 
1669 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
1670 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
1671 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
1672 
1673 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
1674 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
1675 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
1676 
1677 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
1678 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
1679 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
1680 
1681 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
1682 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
1683 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
1684 
1685 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
1686 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
1687 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
1688 
1689 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
1690 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
1691 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
1692 
1693 /****************** Bits definition for GPIO_PUPDR register *****************/
1694 #define GPIO_PUPDR_PUPDR0 0x00000003U
1695 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
1696 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
1697 
1698 #define GPIO_PUPDR_PUPDR1 0x0000000CU
1699 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
1700 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
1701 
1702 #define GPIO_PUPDR_PUPDR2 0x00000030U
1703 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
1704 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
1705 
1706 #define GPIO_PUPDR_PUPDR3 0x000000C0U
1707 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
1708 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
1709 
1710 #define GPIO_PUPDR_PUPDR4 0x00000300U
1711 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
1712 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
1713 
1714 #define GPIO_PUPDR_PUPDR5 0x00000C00U
1715 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
1716 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
1717 
1718 #define GPIO_PUPDR_PUPDR6 0x00003000U
1719 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
1720 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
1721 
1722 #define GPIO_PUPDR_PUPDR7 0x0000C000U
1723 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
1724 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
1725 
1726 #define GPIO_PUPDR_PUPDR8 0x00030000U
1727 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
1728 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
1729 
1730 #define GPIO_PUPDR_PUPDR9 0x000C0000U
1731 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
1732 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
1733 
1734 #define GPIO_PUPDR_PUPDR10 0x00300000U
1735 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
1736 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
1737 
1738 #define GPIO_PUPDR_PUPDR11 0x00C00000U
1739 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
1740 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
1741 
1742 #define GPIO_PUPDR_PUPDR12 0x03000000U
1743 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
1744 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
1745 
1746 #define GPIO_PUPDR_PUPDR13 0x0C000000U
1747 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
1748 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
1749 
1750 #define GPIO_PUPDR_PUPDR14 0x30000000U
1751 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
1752 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
1753 
1754 #define GPIO_PUPDR_PUPDR15 0xC0000000U
1755 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
1756 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
1757 
1758 /****************** Bits definition for GPIO_IDR register *******************/
1759 #define GPIO_IDR_IDR_0 0x00000001U
1760 #define GPIO_IDR_IDR_1 0x00000002U
1761 #define GPIO_IDR_IDR_2 0x00000004U
1762 #define GPIO_IDR_IDR_3 0x00000008U
1763 #define GPIO_IDR_IDR_4 0x00000010U
1764 #define GPIO_IDR_IDR_5 0x00000020U
1765 #define GPIO_IDR_IDR_6 0x00000040U
1766 #define GPIO_IDR_IDR_7 0x00000080U
1767 #define GPIO_IDR_IDR_8 0x00000100U
1768 #define GPIO_IDR_IDR_9 0x00000200U
1769 #define GPIO_IDR_IDR_10 0x00000400U
1770 #define GPIO_IDR_IDR_11 0x00000800U
1771 #define GPIO_IDR_IDR_12 0x00001000U
1772 #define GPIO_IDR_IDR_13 0x00002000U
1773 #define GPIO_IDR_IDR_14 0x00004000U
1774 #define GPIO_IDR_IDR_15 0x00008000U
1775 
1776 /****************** Bits definition for GPIO_ODR register *******************/
1777 #define GPIO_ODR_ODR_0 0x00000001U
1778 #define GPIO_ODR_ODR_1 0x00000002U
1779 #define GPIO_ODR_ODR_2 0x00000004U
1780 #define GPIO_ODR_ODR_3 0x00000008U
1781 #define GPIO_ODR_ODR_4 0x00000010U
1782 #define GPIO_ODR_ODR_5 0x00000020U
1783 #define GPIO_ODR_ODR_6 0x00000040U
1784 #define GPIO_ODR_ODR_7 0x00000080U
1785 #define GPIO_ODR_ODR_8 0x00000100U
1786 #define GPIO_ODR_ODR_9 0x00000200U
1787 #define GPIO_ODR_ODR_10 0x00000400U
1788 #define GPIO_ODR_ODR_11 0x00000800U
1789 #define GPIO_ODR_ODR_12 0x00001000U
1790 #define GPIO_ODR_ODR_13 0x00002000U
1791 #define GPIO_ODR_ODR_14 0x00004000U
1792 #define GPIO_ODR_ODR_15 0x00008000U
1793 
1794 /****************** Bits definition for GPIO_BSRR register ******************/
1795 #define GPIO_BSRR_BS_0 0x00000001U
1796 #define GPIO_BSRR_BS_1 0x00000002U
1797 #define GPIO_BSRR_BS_2 0x00000004U
1798 #define GPIO_BSRR_BS_3 0x00000008U
1799 #define GPIO_BSRR_BS_4 0x00000010U
1800 #define GPIO_BSRR_BS_5 0x00000020U
1801 #define GPIO_BSRR_BS_6 0x00000040U
1802 #define GPIO_BSRR_BS_7 0x00000080U
1803 #define GPIO_BSRR_BS_8 0x00000100U
1804 #define GPIO_BSRR_BS_9 0x00000200U
1805 #define GPIO_BSRR_BS_10 0x00000400U
1806 #define GPIO_BSRR_BS_11 0x00000800U
1807 #define GPIO_BSRR_BS_12 0x00001000U
1808 #define GPIO_BSRR_BS_13 0x00002000U
1809 #define GPIO_BSRR_BS_14 0x00004000U
1810 #define GPIO_BSRR_BS_15 0x00008000U
1811 #define GPIO_BSRR_BR_0 0x00010000U
1812 #define GPIO_BSRR_BR_1 0x00020000U
1813 #define GPIO_BSRR_BR_2 0x00040000U
1814 #define GPIO_BSRR_BR_3 0x00080000U
1815 #define GPIO_BSRR_BR_4 0x00100000U
1816 #define GPIO_BSRR_BR_5 0x00200000U
1817 #define GPIO_BSRR_BR_6 0x00400000U
1818 #define GPIO_BSRR_BR_7 0x00800000U
1819 #define GPIO_BSRR_BR_8 0x01000000U
1820 #define GPIO_BSRR_BR_9 0x02000000U
1821 #define GPIO_BSRR_BR_10 0x04000000U
1822 #define GPIO_BSRR_BR_11 0x08000000U
1823 #define GPIO_BSRR_BR_12 0x10000000U
1824 #define GPIO_BSRR_BR_13 0x20000000U
1825 #define GPIO_BSRR_BR_14 0x40000000U
1826 #define GPIO_BSRR_BR_15 0x80000000U
1827 
1828 /****************** Bit definition for GPIO_LCKR register *********************/
1829 #define GPIO_LCKR_LCK0 0x00000001U
1830 #define GPIO_LCKR_LCK1 0x00000002U
1831 #define GPIO_LCKR_LCK2 0x00000004U
1832 #define GPIO_LCKR_LCK3 0x00000008U
1833 #define GPIO_LCKR_LCK4 0x00000010U
1834 #define GPIO_LCKR_LCK5 0x00000020U
1835 #define GPIO_LCKR_LCK6 0x00000040U
1836 #define GPIO_LCKR_LCK7 0x00000080U
1837 #define GPIO_LCKR_LCK8 0x00000100U
1838 #define GPIO_LCKR_LCK9 0x00000200U
1839 #define GPIO_LCKR_LCK10 0x00000400U
1840 #define GPIO_LCKR_LCK11 0x00000800U
1841 #define GPIO_LCKR_LCK12 0x00001000U
1842 #define GPIO_LCKR_LCK13 0x00002000U
1843 #define GPIO_LCKR_LCK14 0x00004000U
1844 #define GPIO_LCKR_LCK15 0x00008000U
1845 #define GPIO_LCKR_LCKK 0x00010000U
1846 
1847 /******************************************************************************/
1848 /* */
1849 /* Inter-integrated Circuit Interface */
1850 /* */
1851 /******************************************************************************/
1852 /******************* Bit definition for I2C_CR1 register ********************/
1853 #define I2C_CR1_PE 0x00000001U
1854 #define I2C_CR1_SMBUS 0x00000002U
1855 #define I2C_CR1_SMBTYPE 0x00000008U
1856 #define I2C_CR1_ENARP 0x00000010U
1857 #define I2C_CR1_ENPEC 0x00000020U
1858 #define I2C_CR1_ENGC 0x00000040U
1859 #define I2C_CR1_NOSTRETCH 0x00000080U
1860 #define I2C_CR1_START 0x00000100U
1861 #define I2C_CR1_STOP 0x00000200U
1862 #define I2C_CR1_ACK 0x00000400U
1863 #define I2C_CR1_POS 0x00000800U
1864 #define I2C_CR1_PEC 0x00001000U
1865 #define I2C_CR1_ALERT 0x00002000U
1866 #define I2C_CR1_SWRST 0x00008000U
1868 /******************* Bit definition for I2C_CR2 register ********************/
1869 #define I2C_CR2_FREQ 0x0000003FU
1870 #define I2C_CR2_FREQ_0 0x00000001U
1871 #define I2C_CR2_FREQ_1 0x00000002U
1872 #define I2C_CR2_FREQ_2 0x00000004U
1873 #define I2C_CR2_FREQ_3 0x00000008U
1874 #define I2C_CR2_FREQ_4 0x00000010U
1875 #define I2C_CR2_FREQ_5 0x00000020U
1877 #define I2C_CR2_ITERREN 0x00000100U
1878 #define I2C_CR2_ITEVTEN 0x00000200U
1879 #define I2C_CR2_ITBUFEN 0x00000400U
1880 #define I2C_CR2_DMAEN 0x00000800U
1881 #define I2C_CR2_LAST 0x00001000U
1883 /******************* Bit definition for I2C_OAR1 register *******************/
1884 #define I2C_OAR1_ADD1_7 0x000000FEU
1885 #define I2C_OAR1_ADD8_9 0x00000300U
1887 #define I2C_OAR1_ADD0 0x00000001U
1888 #define I2C_OAR1_ADD1 0x00000002U
1889 #define I2C_OAR1_ADD2 0x00000004U
1890 #define I2C_OAR1_ADD3 0x00000008U
1891 #define I2C_OAR1_ADD4 0x00000010U
1892 #define I2C_OAR1_ADD5 0x00000020U
1893 #define I2C_OAR1_ADD6 0x00000040U
1894 #define I2C_OAR1_ADD7 0x00000080U
1895 #define I2C_OAR1_ADD8 0x00000100U
1896 #define I2C_OAR1_ADD9 0x00000200U
1898 #define I2C_OAR1_ADDMODE 0x00008000U
1900 /******************* Bit definition for I2C_OAR2 register *******************/
1901 #define I2C_OAR2_ENDUAL 0x00000001U
1902 #define I2C_OAR2_ADD2 0x000000FEU
1904 /******************** Bit definition for I2C_DR register ********************/
1905 #define I2C_DR_DR 0x000000FFU
1907 /******************* Bit definition for I2C_SR1 register ********************/
1908 #define I2C_SR1_SB 0x00000001U
1909 #define I2C_SR1_ADDR 0x00000002U
1910 #define I2C_SR1_BTF 0x00000004U
1911 #define I2C_SR1_ADD10 0x00000008U
1912 #define I2C_SR1_STOPF 0x00000010U
1913 #define I2C_SR1_RXNE 0x00000040U
1914 #define I2C_SR1_TXE 0x00000080U
1915 #define I2C_SR1_BERR 0x00000100U
1916 #define I2C_SR1_ARLO 0x00000200U
1917 #define I2C_SR1_AF 0x00000400U
1918 #define I2C_SR1_OVR 0x00000800U
1919 #define I2C_SR1_PECERR 0x00001000U
1920 #define I2C_SR1_TIMEOUT 0x00004000U
1921 #define I2C_SR1_SMBALERT 0x00008000U
1923 /******************* Bit definition for I2C_SR2 register ********************/
1924 #define I2C_SR2_MSL 0x00000001U
1925 #define I2C_SR2_BUSY 0x00000002U
1926 #define I2C_SR2_TRA 0x00000004U
1927 #define I2C_SR2_GENCALL 0x00000010U
1928 #define I2C_SR2_SMBDEFAULT 0x00000020U
1929 #define I2C_SR2_SMBHOST 0x00000040U
1930 #define I2C_SR2_DUALF 0x00000080U
1931 #define I2C_SR2_PEC 0x0000FF00U
1933 /******************* Bit definition for I2C_CCR register ********************/
1934 #define I2C_CCR_CCR 0x00000FFFU
1935 #define I2C_CCR_DUTY 0x00004000U
1936 #define I2C_CCR_FS 0x00008000U
1938 /****************** Bit definition for I2C_TRISE register *******************/
1939 #define I2C_TRISE_TRISE 0x0000003FU
1941 /****************** Bit definition for I2C_FLTR register *******************/
1942 #define I2C_FLTR_DNF 0x0000000FU
1943 #define I2C_FLTR_ANOFF 0x00000010U
1945 /******************************************************************************/
1946 /* */
1947 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
1948 /* */
1949 /******************************************************************************/
1950 /******************* Bit definition for I2C_CR1 register *******************/
1951 #define FMPI2C_CR1_PE 0x00000001U
1952 #define FMPI2C_CR1_TXIE 0x00000002U
1953 #define FMPI2C_CR1_RXIE 0x00000004U
1954 #define FMPI2C_CR1_ADDRIE 0x00000008U
1955 #define FMPI2C_CR1_NACKIE 0x00000010U
1956 #define FMPI2C_CR1_STOPIE 0x00000020U
1957 #define FMPI2C_CR1_TCIE 0x00000040U
1958 #define FMPI2C_CR1_ERRIE 0x00000080U
1959 #define FMPI2C_CR1_DFN 0x00000F00U
1960 #define FMPI2C_CR1_ANFOFF 0x00001000U
1961 #define FMPI2C_CR1_TXDMAEN 0x00004000U
1962 #define FMPI2C_CR1_RXDMAEN 0x00008000U
1963 #define FMPI2C_CR1_SBC 0x00010000U
1964 #define FMPI2C_CR1_NOSTRETCH 0x00020000U
1965 #define FMPI2C_CR1_GCEN 0x00080000U
1966 #define FMPI2C_CR1_SMBHEN 0x00100000U
1967 #define FMPI2C_CR1_SMBDEN 0x00200000U
1968 #define FMPI2C_CR1_ALERTEN 0x00400000U
1969 #define FMPI2C_CR1_PECEN 0x00800000U
1971 /****************** Bit definition for I2C_CR2 register ********************/
1972 #define FMPI2C_CR2_SADD 0x000003FFU
1973 #define FMPI2C_CR2_RD_WRN 0x00000400U
1974 #define FMPI2C_CR2_ADD10 0x00000800U
1975 #define FMPI2C_CR2_HEAD10R 0x00001000U
1976 #define FMPI2C_CR2_START 0x00002000U
1977 #define FMPI2C_CR2_STOP 0x00004000U
1978 #define FMPI2C_CR2_NACK 0x00008000U
1979 #define FMPI2C_CR2_NBYTES 0x00FF0000U
1980 #define FMPI2C_CR2_RELOAD 0x01000000U
1981 #define FMPI2C_CR2_AUTOEND 0x02000000U
1982 #define FMPI2C_CR2_PECBYTE 0x04000000U
1984 /******************* Bit definition for I2C_OAR1 register ******************/
1985 #define FMPI2C_OAR1_OA1 0x000003FFU
1986 #define FMPI2C_OAR1_OA1MODE 0x00000400U
1987 #define FMPI2C_OAR1_OA1EN 0x00008000U
1989 /******************* Bit definition for I2C_OAR2 register ******************/
1990 #define FMPI2C_OAR2_OA2 0x000000FEU
1991 #define FMPI2C_OAR2_OA2MSK 0x00000700U
1992 #define FMPI2C_OAR2_OA2EN 0x00008000U
1994 /******************* Bit definition for I2C_TIMINGR register *******************/
1995 #define FMPI2C_TIMINGR_SCLL 0x000000FFU
1996 #define FMPI2C_TIMINGR_SCLH 0x0000FF00U
1997 #define FMPI2C_TIMINGR_SDADEL 0x000F0000U
1998 #define FMPI2C_TIMINGR_SCLDEL 0x00F00000U
1999 #define FMPI2C_TIMINGR_PRESC 0xF0000000U
2001 /******************* Bit definition for I2C_TIMEOUTR register *******************/
2002 #define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
2003 #define FMPI2C_TIMEOUTR_TIDLE 0x00001000U
2004 #define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U
2005 #define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
2006 #define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U
2008 /****************** Bit definition for I2C_ISR register *********************/
2009 #define FMPI2C_ISR_TXE 0x00000001U
2010 #define FMPI2C_ISR_TXIS 0x00000002U
2011 #define FMPI2C_ISR_RXNE 0x00000004U
2012 #define FMPI2C_ISR_ADDR 0x00000008U
2013 #define FMPI2C_ISR_NACKF 0x00000010U
2014 #define FMPI2C_ISR_STOPF 0x00000020U
2015 #define FMPI2C_ISR_TC 0x00000040U
2016 #define FMPI2C_ISR_TCR 0x00000080U
2017 #define FMPI2C_ISR_BERR 0x00000100U
2018 #define FMPI2C_ISR_ARLO 0x00000200U
2019 #define FMPI2C_ISR_OVR 0x00000400U
2020 #define FMPI2C_ISR_PECERR 0x00000800U
2021 #define FMPI2C_ISR_TIMEOUT 0x00001000U
2022 #define FMPI2C_ISR_ALERT 0x00002000U
2023 #define FMPI2C_ISR_BUSY 0x00008000U
2024 #define FMPI2C_ISR_DIR 0x00010000U
2025 #define FMPI2C_ISR_ADDCODE 0x00FE0000U
2027 /****************** Bit definition for I2C_ICR register *********************/
2028 #define FMPI2C_ICR_ADDRCF 0x00000008U
2029 #define FMPI2C_ICR_NACKCF 0x00000010U
2030 #define FMPI2C_ICR_STOPCF 0x00000020U
2031 #define FMPI2C_ICR_BERRCF 0x00000100U
2032 #define FMPI2C_ICR_ARLOCF 0x00000200U
2033 #define FMPI2C_ICR_OVRCF 0x00000400U
2034 #define FMPI2C_ICR_PECCF 0x00000800U
2035 #define FMPI2C_ICR_TIMOUTCF 0x00001000U
2036 #define FMPI2C_ICR_ALERTCF 0x00002000U
2038 /****************** Bit definition for I2C_PECR register *********************/
2039 #define FMPI2C_PECR_PEC 0x000000FFU
2041 /****************** Bit definition for I2C_RXDR register *********************/
2042 #define FMPI2C_RXDR_RXDATA 0x000000FFU
2044 /****************** Bit definition for I2C_TXDR register *********************/
2045 #define FMPI2C_TXDR_TXDATA 0x000000FFU
2047 /******************************************************************************/
2048 /* */
2049 /* Independent WATCHDOG */
2050 /* */
2051 /******************************************************************************/
2052 /******************* Bit definition for IWDG_KR register ********************/
2053 #define IWDG_KR_KEY 0xFFFFU
2055 /******************* Bit definition for IWDG_PR register ********************/
2056 #define IWDG_PR_PR 0x07U
2057 #define IWDG_PR_PR_0 0x01U
2058 #define IWDG_PR_PR_1 0x02U
2059 #define IWDG_PR_PR_2 0x04U
2061 /******************* Bit definition for IWDG_RLR register *******************/
2062 #define IWDG_RLR_RL 0x0FFFU
2064 /******************* Bit definition for IWDG_SR register ********************/
2065 #define IWDG_SR_PVU 0x01U
2066 #define IWDG_SR_RVU 0x02U
2069 /******************************************************************************/
2070 /* */
2071 /* Power Control */
2072 /* */
2073 /******************************************************************************/
2074 /******************** Bit definition for PWR_CR register ********************/
2075 #define PWR_CR_LPDS 0x00000001U
2076 #define PWR_CR_PDDS 0x00000002U
2077 #define PWR_CR_CWUF 0x00000004U
2078 #define PWR_CR_CSBF 0x00000008U
2079 #define PWR_CR_PVDE 0x00000010U
2081 #define PWR_CR_PLS 0x000000E0U
2082 #define PWR_CR_PLS_0 0x00000020U
2083 #define PWR_CR_PLS_1 0x00000040U
2084 #define PWR_CR_PLS_2 0x00000080U
2087 #define PWR_CR_PLS_LEV0 0x00000000U
2088 #define PWR_CR_PLS_LEV1 0x00000020U
2089 #define PWR_CR_PLS_LEV2 0x00000040U
2090 #define PWR_CR_PLS_LEV3 0x00000060U
2091 #define PWR_CR_PLS_LEV4 0x00000080U
2092 #define PWR_CR_PLS_LEV5 0x000000A0U
2093 #define PWR_CR_PLS_LEV6 0x000000C0U
2094 #define PWR_CR_PLS_LEV7 0x000000E0U
2096 #define PWR_CR_DBP 0x00000100U
2097 #define PWR_CR_FPDS 0x00000200U
2098 #define PWR_CR_LPLVDS 0x00000400U
2099 #define PWR_CR_MRLVDS 0x00000800U
2100 #define PWR_CR_ADCDC1 0x00002000U
2102 #define PWR_CR_VOS 0x0000C000U
2103 #define PWR_CR_VOS_0 0x00004000U
2104 #define PWR_CR_VOS_1 0x00008000U
2106 #define PWR_CR_FMSSR 0x00100000U
2107 #define PWR_CR_FISSR 0x00200000U
2108 /* Legacy define */
2109 #define PWR_CR_PMODE PWR_CR_VOS
2110 
2111 /******************* Bit definition for PWR_CSR register ********************/
2112 #define PWR_CSR_WUF 0x00000001U
2113 #define PWR_CSR_SBF 0x00000002U
2114 #define PWR_CSR_PVDO 0x00000004U
2115 #define PWR_CSR_BRR 0x00000008U
2116 #define PWR_CSR_EWUP 0x00000100U
2117 #define PWR_CSR_BRE 0x00000200U
2118 #define PWR_CSR_VOSRDY 0x00004000U
2120 /* Legacy define */
2121 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
2122 
2123 /******************************************************************************/
2124 /* */
2125 /* Reset and Clock Control */
2126 /* */
2127 /******************************************************************************/
2128 /******************** Bit definition for RCC_CR register ********************/
2129 #define RCC_CR_HSION 0x00000001U
2130 #define RCC_CR_HSIRDY 0x00000002U
2131 
2132 #define RCC_CR_HSITRIM 0x000000F8U
2133 #define RCC_CR_HSITRIM_0 0x00000008U
2134 #define RCC_CR_HSITRIM_1 0x00000010U
2135 #define RCC_CR_HSITRIM_2 0x00000020U
2136 #define RCC_CR_HSITRIM_3 0x00000040U
2137 #define RCC_CR_HSITRIM_4 0x00000080U
2139 #define RCC_CR_HSICAL 0x0000FF00U
2140 #define RCC_CR_HSICAL_0 0x00000100U
2141 #define RCC_CR_HSICAL_1 0x00000200U
2142 #define RCC_CR_HSICAL_2 0x00000400U
2143 #define RCC_CR_HSICAL_3 0x00000800U
2144 #define RCC_CR_HSICAL_4 0x00001000U
2145 #define RCC_CR_HSICAL_5 0x00002000U
2146 #define RCC_CR_HSICAL_6 0x00004000U
2147 #define RCC_CR_HSICAL_7 0x00008000U
2149 #define RCC_CR_HSEON 0x00010000U
2150 #define RCC_CR_HSERDY 0x00020000U
2151 #define RCC_CR_HSEBYP 0x00040000U
2152 #define RCC_CR_CSSON 0x00080000U
2153 #define RCC_CR_PLLON 0x01000000U
2154 #define RCC_CR_PLLRDY 0x02000000U
2155 
2156 /******************** Bit definition for RCC_PLLCFGR register ***************/
2157 #define RCC_PLLCFGR_PLLM 0x0000003FU
2158 #define RCC_PLLCFGR_PLLM_0 0x00000001U
2159 #define RCC_PLLCFGR_PLLM_1 0x00000002U
2160 #define RCC_PLLCFGR_PLLM_2 0x00000004U
2161 #define RCC_PLLCFGR_PLLM_3 0x00000008U
2162 #define RCC_PLLCFGR_PLLM_4 0x00000010U
2163 #define RCC_PLLCFGR_PLLM_5 0x00000020U
2164 
2165 #define RCC_PLLCFGR_PLLN 0x00007FC0U
2166 #define RCC_PLLCFGR_PLLN_0 0x00000040U
2167 #define RCC_PLLCFGR_PLLN_1 0x00000080U
2168 #define RCC_PLLCFGR_PLLN_2 0x00000100U
2169 #define RCC_PLLCFGR_PLLN_3 0x00000200U
2170 #define RCC_PLLCFGR_PLLN_4 0x00000400U
2171 #define RCC_PLLCFGR_PLLN_5 0x00000800U
2172 #define RCC_PLLCFGR_PLLN_6 0x00001000U
2173 #define RCC_PLLCFGR_PLLN_7 0x00002000U
2174 #define RCC_PLLCFGR_PLLN_8 0x00004000U
2175 
2176 #define RCC_PLLCFGR_PLLP 0x00030000U
2177 #define RCC_PLLCFGR_PLLP_0 0x00010000U
2178 #define RCC_PLLCFGR_PLLP_1 0x00020000U
2179 
2180 #define RCC_PLLCFGR_PLLSRC 0x00400000U
2181 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
2182 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
2183 
2184 #define RCC_PLLCFGR_PLLQ 0x0F000000U
2185 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
2186 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
2187 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
2188 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
2189 
2190 #define RCC_PLLCFGR_PLLR 0x70000000U
2191 #define RCC_PLLCFGR_PLLR_0 0x10000000U
2192 #define RCC_PLLCFGR_PLLR_1 0x20000000U
2193 #define RCC_PLLCFGR_PLLR_2 0x40000000U
2194 /******************** Bit definition for RCC_CFGR register ******************/
2196 #define RCC_CFGR_SW 0x00000003U
2197 #define RCC_CFGR_SW_0 0x00000001U
2198 #define RCC_CFGR_SW_1 0x00000002U
2200 #define RCC_CFGR_SW_HSI 0x00000000U
2201 #define RCC_CFGR_SW_HSE 0x00000001U
2202 #define RCC_CFGR_SW_PLL 0x00000002U
2205 #define RCC_CFGR_SWS 0x0000000CU
2206 #define RCC_CFGR_SWS_0 0x00000004U
2207 #define RCC_CFGR_SWS_1 0x00000008U
2209 #define RCC_CFGR_SWS_HSI 0x00000000U
2210 #define RCC_CFGR_SWS_HSE 0x00000004U
2211 #define RCC_CFGR_SWS_PLL 0x00000008U
2214 #define RCC_CFGR_HPRE 0x000000F0U
2215 #define RCC_CFGR_HPRE_0 0x00000010U
2216 #define RCC_CFGR_HPRE_1 0x00000020U
2217 #define RCC_CFGR_HPRE_2 0x00000040U
2218 #define RCC_CFGR_HPRE_3 0x00000080U
2220 #define RCC_CFGR_HPRE_DIV1 0x00000000U
2221 #define RCC_CFGR_HPRE_DIV2 0x00000080U
2222 #define RCC_CFGR_HPRE_DIV4 0x00000090U
2223 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
2224 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
2225 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
2226 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
2227 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
2228 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
2231 #define RCC_CFGR_MCO1EN 0x00000100U
2234 #define RCC_CFGR_PPRE1 0x00001C00U
2235 #define RCC_CFGR_PPRE1_0 0x00000400U
2236 #define RCC_CFGR_PPRE1_1 0x00000800U
2237 #define RCC_CFGR_PPRE1_2 0x00001000U
2239 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
2240 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
2241 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
2242 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
2243 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
2246 #define RCC_CFGR_PPRE2 0x0000E000U
2247 #define RCC_CFGR_PPRE2_0 0x00002000U
2248 #define RCC_CFGR_PPRE2_1 0x00004000U
2249 #define RCC_CFGR_PPRE2_2 0x00008000U
2251 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
2252 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
2253 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
2254 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
2255 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
2258 #define RCC_CFGR_RTCPRE 0x001F0000U
2259 #define RCC_CFGR_RTCPRE_0 0x00010000U
2260 #define RCC_CFGR_RTCPRE_1 0x00020000U
2261 #define RCC_CFGR_RTCPRE_2 0x00040000U
2262 #define RCC_CFGR_RTCPRE_3 0x00080000U
2263 #define RCC_CFGR_RTCPRE_4 0x00100000U
2264 
2266 #define RCC_CFGR_MCO1 0x00600000U
2267 #define RCC_CFGR_MCO1_0 0x00200000U
2268 #define RCC_CFGR_MCO1_1 0x00400000U
2269 
2270 #define RCC_CFGR_MCO1PRE 0x07000000U
2271 #define RCC_CFGR_MCO1PRE_0 0x01000000U
2272 #define RCC_CFGR_MCO1PRE_1 0x02000000U
2273 #define RCC_CFGR_MCO1PRE_2 0x04000000U
2274 
2275 #define RCC_CFGR_MCO2PRE 0x38000000U
2276 #define RCC_CFGR_MCO2PRE_0 0x08000000U
2277 #define RCC_CFGR_MCO2PRE_1 0x10000000U
2278 #define RCC_CFGR_MCO2PRE_2 0x20000000U
2279 
2280 #define RCC_CFGR_MCO2 0xC0000000U
2281 #define RCC_CFGR_MCO2_0 0x40000000U
2282 #define RCC_CFGR_MCO2_1 0x80000000U
2283 
2284 /******************** Bit definition for RCC_CIR register *******************/
2285 #define RCC_CIR_LSIRDYF 0x00000001U
2286 #define RCC_CIR_LSERDYF 0x00000002U
2287 #define RCC_CIR_HSIRDYF 0x00000004U
2288 #define RCC_CIR_HSERDYF 0x00000008U
2289 #define RCC_CIR_PLLRDYF 0x00000010U
2290 
2291 #define RCC_CIR_CSSF 0x00000080U
2292 #define RCC_CIR_LSIRDYIE 0x00000100U
2293 #define RCC_CIR_LSERDYIE 0x00000200U
2294 #define RCC_CIR_HSIRDYIE 0x00000400U
2295 #define RCC_CIR_HSERDYIE 0x00000800U
2296 #define RCC_CIR_PLLRDYIE 0x00001000U
2297 
2298 #define RCC_CIR_LSIRDYC 0x00010000U
2299 #define RCC_CIR_LSERDYC 0x00020000U
2300 #define RCC_CIR_HSIRDYC 0x00040000U
2301 #define RCC_CIR_HSERDYC 0x00080000U
2302 #define RCC_CIR_PLLRDYC 0x00100000U
2303 
2304 #define RCC_CIR_CSSC 0x00800000U
2305 
2306 /******************** Bit definition for RCC_AHB1RSTR register **************/
2307 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
2308 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
2309 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
2310 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
2311 #define RCC_AHB1RSTR_CRCRST 0x00001000U
2312 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
2313 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
2314 #define RCC_AHB1RSTR_RNGRST 0x80000000U
2315 
2316 /******************** Bit definition for RCC_APB1RSTR register **************/
2317 #define RCC_APB1RSTR_TIM5RST 0x00000008U
2318 #define RCC_APB1RSTR_TIM6RST 0x00000010U
2319 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
2320 #define RCC_APB1RSTR_WWDGRST 0x00000800U
2321 #define RCC_APB1RSTR_SPI2RST 0x00004000U
2322 #define RCC_APB1RSTR_USART2RST 0x00020000U
2323 #define RCC_APB1RSTR_I2C1RST 0x00200000U
2324 #define RCC_APB1RSTR_I2C2RST 0x00400000U
2325 #define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
2326 #define RCC_APB1RSTR_PWRRST 0x10000000U
2327 #define RCC_APB1RSTR_DACRST 0x20000000U
2328 
2329 /******************** Bit definition for RCC_APB2RSTR register **************/
2330 #define RCC_APB2RSTR_TIM1RST 0x00000001U
2331 #define RCC_APB2RSTR_USART1RST 0x00000010U
2332 #define RCC_APB2RSTR_USART6RST 0x00000020U
2333 #define RCC_APB2RSTR_ADCRST 0x00000100U
2334 #define RCC_APB2RSTR_SPI1RST 0x00001000U
2335 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
2336 #define RCC_APB2RSTR_TIM9RST 0x00010000U
2337 #define RCC_APB2RSTR_TIM11RST 0x00040000U
2338 #define RCC_APB2RSTR_SPI5RST 0x00100000U
2339 
2340 /******************** Bit definition for RCC_AHB1ENR register ***************/
2341 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
2342 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
2343 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
2344 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
2345 #define RCC_AHB1ENR_CRCEN 0x00001000U
2346 #define RCC_AHB1ENR_DMA1EN 0x00200000U
2347 #define RCC_AHB1ENR_DMA2EN 0x00400000U
2348 #define RCC_AHB1ENR_RNGEN 0x80000000U
2349 
2350 /******************** Bit definition for RCC_APB1ENR register ***************/
2351 #define RCC_APB1ENR_TIM5EN 0x00000008U
2352 #define RCC_APB1ENR_TIM6EN 0x00000010U
2353 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
2354 #define RCC_APB1ENR_RTCAPBEN 0x00000400U
2355 #define RCC_APB1ENR_WWDGEN 0x00000800U
2356 #define RCC_APB1ENR_SPI2EN 0x00004000U
2357 #define RCC_APB1ENR_USART2EN 0x00020000U
2358 #define RCC_APB1ENR_I2C1EN 0x00200000U
2359 #define RCC_APB1ENR_I2C2EN 0x00400000U
2360 #define RCC_APB1ENR_FMPI2C1EN 0x01000000U
2361 #define RCC_APB1ENR_PWREN 0x10000000U
2362 #define RCC_APB1ENR_DACEN 0x20000000U
2363 
2364 /******************** Bit definition for RCC_APB2ENR register ***************/
2365 #define RCC_APB2ENR_TIM1EN 0x00000001U
2366 #define RCC_APB2ENR_USART1EN 0x00000010U
2367 #define RCC_APB2ENR_USART6EN 0x00000020U
2368 #define RCC_APB2ENR_ADC1EN 0x00000100U
2369 #define RCC_APB2ENR_SPI1EN 0x00001000U
2370 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
2371 #define RCC_APB2ENR_EXTITEN 0x00008000U
2372 #define RCC_APB2ENR_TIM9EN 0x00010000U
2373 #define RCC_APB2ENR_TIM11EN 0x00040000U
2374 #define RCC_APB2ENR_SPI5EN 0x00100000U
2375 
2376 /******************** Bit definition for RCC_AHB1LPENR register *************/
2377 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
2378 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
2379 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
2380 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
2381 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
2382 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
2383 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
2384 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
2385 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
2386 #define RCC_AHB1LPENR_RNGLPEN 0x80000000U
2387 
2388 /******************** Bit definition for RCC_APB1LPENR register *************/
2389 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
2390 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
2391 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
2392 #define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
2393 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
2394 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
2395 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
2396 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
2397 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
2398 #define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
2399 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
2400 #define RCC_APB1LPENR_DACLPEN 0x20000000U
2401 
2402 /******************** Bit definition for RCC_APB2LPENR register *************/
2403 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
2404 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
2405 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
2406 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
2407 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
2408 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
2409 #define RCC_APB2LPENR_EXTITLPEN 0x00008000U
2410 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
2411 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
2412 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
2413 
2414 /******************** Bit definition for RCC_BDCR register ******************/
2415 #define RCC_BDCR_LSEON 0x00000001U
2416 #define RCC_BDCR_LSERDY 0x00000002U
2417 #define RCC_BDCR_LSEBYP 0x00000004U
2418 #define RCC_BDCR_LSEMOD 0x00000008U
2419 
2420 #define RCC_BDCR_RTCSEL 0x00000300U
2421 #define RCC_BDCR_RTCSEL_0 0x00000100U
2422 #define RCC_BDCR_RTCSEL_1 0x00000200U
2423 
2424 #define RCC_BDCR_RTCEN 0x00008000U
2425 #define RCC_BDCR_BDRST 0x00010000U
2426 
2427 /******************** Bit definition for RCC_CSR register *******************/
2428 #define RCC_CSR_LSION 0x00000001U
2429 #define RCC_CSR_LSIRDY 0x00000002U
2430 #define RCC_CSR_RMVF 0x01000000U
2431 #define RCC_CSR_BORRSTF 0x02000000U
2432 #define RCC_CSR_PADRSTF 0x04000000U
2433 #define RCC_CSR_PORRSTF 0x08000000U
2434 #define RCC_CSR_SFTRSTF 0x10000000U
2435 #define RCC_CSR_WDGRSTF 0x20000000U
2436 #define RCC_CSR_WWDGRSTF 0x40000000U
2437 #define RCC_CSR_LPWRRSTF 0x80000000U
2438 
2439 /******************** Bit definition for RCC_SSCGR register *****************/
2440 #define RCC_SSCGR_MODPER 0x00001FFFU
2441 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
2442 #define RCC_SSCGR_SPREADSEL 0x40000000U
2443 #define RCC_SSCGR_SSCGEN 0x80000000U
2444 
2445 /******************** Bit definition for RCC_DCKCFGR register ***************/
2446 #define RCC_DCKCFGR_TIMPRE 0x01000000U
2447 #define RCC_DCKCFGR_I2SSRC 0x06000000U
2448 #define RCC_DCKCFGR_I2SSRC_0 0x02000000U
2449 #define RCC_DCKCFGR_I2SSRC_1 0x04000000U
2450 
2451 /******************** Bit definition for RCC_CKGATENR register **************/
2452 #define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
2453 #define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
2454 #define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
2455 #define RCC_CKGATENR_SPARE_CKEN 0x00000008U
2456 #define RCC_CKGATENR_SRAM_CKEN 0x00000010U
2457 #define RCC_CKGATENR_FLITF_CKEN 0x00000020U
2458 #define RCC_CKGATENR_RCC_CKEN 0x00000040U
2459 
2460 /******************** Bit definition for RCC_DCKCFGR2 register **************/
2461 #define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
2462 #define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
2463 #define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
2464 #define RCC_DCKCFGR2_LPTIM1SEL 0xC0000000U
2465 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x40000000U
2466 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x80000000U
2467 
2468 /******************************************************************************/
2469 /* */
2470 /* RNG */
2471 /* */
2472 /******************************************************************************/
2473 /******************** Bits definition for RNG_CR register *******************/
2474 #define RNG_CR_RNGEN 0x00000004U
2475 #define RNG_CR_IE 0x00000008U
2476 
2477 /******************** Bits definition for RNG_SR register *******************/
2478 #define RNG_SR_DRDY 0x00000001U
2479 #define RNG_SR_CECS 0x00000002U
2480 #define RNG_SR_SECS 0x00000004U
2481 #define RNG_SR_CEIS 0x00000020U
2482 #define RNG_SR_SEIS 0x00000040U
2483 
2484 /******************************************************************************/
2485 /* */
2486 /* Real-Time Clock (RTC) */
2487 /* */
2488 /******************************************************************************/
2489 /******************** Bits definition for RTC_TR register *******************/
2490 #define RTC_TR_PM 0x00400000U
2491 #define RTC_TR_HT 0x00300000U
2492 #define RTC_TR_HT_0 0x00100000U
2493 #define RTC_TR_HT_1 0x00200000U
2494 #define RTC_TR_HU 0x000F0000U
2495 #define RTC_TR_HU_0 0x00010000U
2496 #define RTC_TR_HU_1 0x00020000U
2497 #define RTC_TR_HU_2 0x00040000U
2498 #define RTC_TR_HU_3 0x00080000U
2499 #define RTC_TR_MNT 0x00007000U
2500 #define RTC_TR_MNT_0 0x00001000U
2501 #define RTC_TR_MNT_1 0x00002000U
2502 #define RTC_TR_MNT_2 0x00004000U
2503 #define RTC_TR_MNU 0x00000F00U
2504 #define RTC_TR_MNU_0 0x00000100U
2505 #define RTC_TR_MNU_1 0x00000200U
2506 #define RTC_TR_MNU_2 0x00000400U
2507 #define RTC_TR_MNU_3 0x00000800U
2508 #define RTC_TR_ST 0x00000070U
2509 #define RTC_TR_ST_0 0x00000010U
2510 #define RTC_TR_ST_1 0x00000020U
2511 #define RTC_TR_ST_2 0x00000040U
2512 #define RTC_TR_SU 0x0000000FU
2513 #define RTC_TR_SU_0 0x00000001U
2514 #define RTC_TR_SU_1 0x00000002U
2515 #define RTC_TR_SU_2 0x00000004U
2516 #define RTC_TR_SU_3 0x00000008U
2517 
2518 /******************** Bits definition for RTC_DR register *******************/
2519 #define RTC_DR_YT 0x00F00000U
2520 #define RTC_DR_YT_0 0x00100000U
2521 #define RTC_DR_YT_1 0x00200000U
2522 #define RTC_DR_YT_2 0x00400000U
2523 #define RTC_DR_YT_3 0x00800000U
2524 #define RTC_DR_YU 0x000F0000U
2525 #define RTC_DR_YU_0 0x00010000U
2526 #define RTC_DR_YU_1 0x00020000U
2527 #define RTC_DR_YU_2 0x00040000U
2528 #define RTC_DR_YU_3 0x00080000U
2529 #define RTC_DR_WDU 0x0000E000U
2530 #define RTC_DR_WDU_0 0x00002000U
2531 #define RTC_DR_WDU_1 0x00004000U
2532 #define RTC_DR_WDU_2 0x00008000U
2533 #define RTC_DR_MT 0x00001000U
2534 #define RTC_DR_MU 0x00000F00U
2535 #define RTC_DR_MU_0 0x00000100U
2536 #define RTC_DR_MU_1 0x00000200U
2537 #define RTC_DR_MU_2 0x00000400U
2538 #define RTC_DR_MU_3 0x00000800U
2539 #define RTC_DR_DT 0x00000030U
2540 #define RTC_DR_DT_0 0x00000010U
2541 #define RTC_DR_DT_1 0x00000020U
2542 #define RTC_DR_DU 0x0000000FU
2543 #define RTC_DR_DU_0 0x00000001U
2544 #define RTC_DR_DU_1 0x00000002U
2545 #define RTC_DR_DU_2 0x00000004U
2546 #define RTC_DR_DU_3 0x00000008U
2547 
2548 /******************** Bits definition for RTC_CR register *******************/
2549 #define RTC_CR_COE 0x00800000U
2550 #define RTC_CR_OSEL 0x00600000U
2551 #define RTC_CR_OSEL_0 0x00200000U
2552 #define RTC_CR_OSEL_1 0x00400000U
2553 #define RTC_CR_POL 0x00100000U
2554 #define RTC_CR_COSEL 0x00080000U
2555 #define RTC_CR_BCK 0x00040000U
2556 #define RTC_CR_SUB1H 0x00020000U
2557 #define RTC_CR_ADD1H 0x00010000U
2558 #define RTC_CR_TSIE 0x00008000U
2559 #define RTC_CR_WUTIE 0x00004000U
2560 #define RTC_CR_ALRBIE 0x00002000U
2561 #define RTC_CR_ALRAIE 0x00001000U
2562 #define RTC_CR_TSE 0x00000800U
2563 #define RTC_CR_WUTE 0x00000400U
2564 #define RTC_CR_ALRBE 0x00000200U
2565 #define RTC_CR_ALRAE 0x00000100U
2566 #define RTC_CR_DCE 0x00000080U
2567 #define RTC_CR_FMT 0x00000040U
2568 #define RTC_CR_BYPSHAD 0x00000020U
2569 #define RTC_CR_REFCKON 0x00000010U
2570 #define RTC_CR_TSEDGE 0x00000008U
2571 #define RTC_CR_WUCKSEL 0x00000007U
2572 #define RTC_CR_WUCKSEL_0 0x00000001U
2573 #define RTC_CR_WUCKSEL_1 0x00000002U
2574 #define RTC_CR_WUCKSEL_2 0x00000004U
2575 
2576 /******************** Bits definition for RTC_ISR register ******************/
2577 #define RTC_ISR_RECALPF 0x00010000U
2578 #define RTC_ISR_TAMP1F 0x00002000U
2579 #define RTC_ISR_TAMP2F 0x00004000U
2580 #define RTC_ISR_TSOVF 0x00001000U
2581 #define RTC_ISR_TSF 0x00000800U
2582 #define RTC_ISR_WUTF 0x00000400U
2583 #define RTC_ISR_ALRBF 0x00000200U
2584 #define RTC_ISR_ALRAF 0x00000100U
2585 #define RTC_ISR_INIT 0x00000080U
2586 #define RTC_ISR_INITF 0x00000040U
2587 #define RTC_ISR_RSF 0x00000020U
2588 #define RTC_ISR_INITS 0x00000010U
2589 #define RTC_ISR_SHPF 0x00000008U
2590 #define RTC_ISR_WUTWF 0x00000004U
2591 #define RTC_ISR_ALRBWF 0x00000002U
2592 #define RTC_ISR_ALRAWF 0x00000001U
2593 
2594 /******************** Bits definition for RTC_PRER register *****************/
2595 #define RTC_PRER_PREDIV_A 0x007F0000U
2596 #define RTC_PRER_PREDIV_S 0x00007FFFU
2597 
2598 /******************** Bits definition for RTC_WUTR register *****************/
2599 #define RTC_WUTR_WUT 0x0000FFFFU
2600 
2601 /******************** Bits definition for RTC_CALIBR register ***************/
2602 #define RTC_CALIBR_DCS 0x00000080U
2603 #define RTC_CALIBR_DC 0x0000001FU
2604 
2605 /******************** Bits definition for RTC_ALRMAR register ***************/
2606 #define RTC_ALRMAR_MSK4 0x80000000U
2607 #define RTC_ALRMAR_WDSEL 0x40000000U
2608 #define RTC_ALRMAR_DT 0x30000000U
2609 #define RTC_ALRMAR_DT_0 0x10000000U
2610 #define RTC_ALRMAR_DT_1 0x20000000U
2611 #define RTC_ALRMAR_DU 0x0F000000U
2612 #define RTC_ALRMAR_DU_0 0x01000000U
2613 #define RTC_ALRMAR_DU_1 0x02000000U
2614 #define RTC_ALRMAR_DU_2 0x04000000U
2615 #define RTC_ALRMAR_DU_3 0x08000000U
2616 #define RTC_ALRMAR_MSK3 0x00800000U
2617 #define RTC_ALRMAR_PM 0x00400000U
2618 #define RTC_ALRMAR_HT 0x00300000U
2619 #define RTC_ALRMAR_HT_0 0x00100000U
2620 #define RTC_ALRMAR_HT_1 0x00200000U
2621 #define RTC_ALRMAR_HU 0x000F0000U
2622 #define RTC_ALRMAR_HU_0 0x00010000U
2623 #define RTC_ALRMAR_HU_1 0x00020000U
2624 #define RTC_ALRMAR_HU_2 0x00040000U
2625 #define RTC_ALRMAR_HU_3 0x00080000U
2626 #define RTC_ALRMAR_MSK2 0x00008000U
2627 #define RTC_ALRMAR_MNT 0x00007000U
2628 #define RTC_ALRMAR_MNT_0 0x00001000U
2629 #define RTC_ALRMAR_MNT_1 0x00002000U
2630 #define RTC_ALRMAR_MNT_2 0x00004000U
2631 #define RTC_ALRMAR_MNU 0x00000F00U
2632 #define RTC_ALRMAR_MNU_0 0x00000100U
2633 #define RTC_ALRMAR_MNU_1 0x00000200U
2634 #define RTC_ALRMAR_MNU_2 0x00000400U
2635 #define RTC_ALRMAR_MNU_3 0x00000800U
2636 #define RTC_ALRMAR_MSK1 0x00000080U
2637 #define RTC_ALRMAR_ST 0x00000070U
2638 #define RTC_ALRMAR_ST_0 0x00000010U
2639 #define RTC_ALRMAR_ST_1 0x00000020U
2640 #define RTC_ALRMAR_ST_2 0x00000040U
2641 #define RTC_ALRMAR_SU 0x0000000FU
2642 #define RTC_ALRMAR_SU_0 0x00000001U
2643 #define RTC_ALRMAR_SU_1 0x00000002U
2644 #define RTC_ALRMAR_SU_2 0x00000004U
2645 #define RTC_ALRMAR_SU_3 0x00000008U
2646 
2647 /******************** Bits definition for RTC_ALRMBR register ***************/
2648 #define RTC_ALRMBR_MSK4 0x80000000U
2649 #define RTC_ALRMBR_WDSEL 0x40000000U
2650 #define RTC_ALRMBR_DT 0x30000000U
2651 #define RTC_ALRMBR_DT_0 0x10000000U
2652 #define RTC_ALRMBR_DT_1 0x20000000U
2653 #define RTC_ALRMBR_DU 0x0F000000U
2654 #define RTC_ALRMBR_DU_0 0x01000000U
2655 #define RTC_ALRMBR_DU_1 0x02000000U
2656 #define RTC_ALRMBR_DU_2 0x04000000U
2657 #define RTC_ALRMBR_DU_3 0x08000000U
2658 #define RTC_ALRMBR_MSK3 0x00800000U
2659 #define RTC_ALRMBR_PM 0x00400000U
2660 #define RTC_ALRMBR_HT 0x00300000U
2661 #define RTC_ALRMBR_HT_0 0x00100000U
2662 #define RTC_ALRMBR_HT_1 0x00200000U
2663 #define RTC_ALRMBR_HU 0x000F0000U
2664 #define RTC_ALRMBR_HU_0 0x00010000U
2665 #define RTC_ALRMBR_HU_1 0x00020000U
2666 #define RTC_ALRMBR_HU_2 0x00040000U
2667 #define RTC_ALRMBR_HU_3 0x00080000U
2668 #define RTC_ALRMBR_MSK2 0x00008000U
2669 #define RTC_ALRMBR_MNT 0x00007000U
2670 #define RTC_ALRMBR_MNT_0 0x00001000U
2671 #define RTC_ALRMBR_MNT_1 0x00002000U
2672 #define RTC_ALRMBR_MNT_2 0x00004000U
2673 #define RTC_ALRMBR_MNU 0x00000F00U
2674 #define RTC_ALRMBR_MNU_0 0x00000100U
2675 #define RTC_ALRMBR_MNU_1 0x00000200U
2676 #define RTC_ALRMBR_MNU_2 0x00000400U
2677 #define RTC_ALRMBR_MNU_3 0x00000800U
2678 #define RTC_ALRMBR_MSK1 0x00000080U
2679 #define RTC_ALRMBR_ST 0x00000070U
2680 #define RTC_ALRMBR_ST_0 0x00000010U
2681 #define RTC_ALRMBR_ST_1 0x00000020U
2682 #define RTC_ALRMBR_ST_2 0x00000040U
2683 #define RTC_ALRMBR_SU 0x0000000FU
2684 #define RTC_ALRMBR_SU_0 0x00000001U
2685 #define RTC_ALRMBR_SU_1 0x00000002U
2686 #define RTC_ALRMBR_SU_2 0x00000004U
2687 #define RTC_ALRMBR_SU_3 0x00000008U
2688 
2689 /******************** Bits definition for RTC_WPR register ******************/
2690 #define RTC_WPR_KEY 0x000000FFU
2691 
2692 /******************** Bits definition for RTC_SSR register ******************/
2693 #define RTC_SSR_SS 0x0000FFFFU
2694 
2695 /******************** Bits definition for RTC_SHIFTR register ***************/
2696 #define RTC_SHIFTR_SUBFS 0x00007FFFU
2697 #define RTC_SHIFTR_ADD1S 0x80000000U
2698 
2699 /******************** Bits definition for RTC_TSTR register *****************/
2700 #define RTC_TSTR_PM 0x00400000U
2701 #define RTC_TSTR_HT 0x00300000U
2702 #define RTC_TSTR_HT_0 0x00100000U
2703 #define RTC_TSTR_HT_1 0x00200000U
2704 #define RTC_TSTR_HU 0x000F0000U
2705 #define RTC_TSTR_HU_0 0x00010000U
2706 #define RTC_TSTR_HU_1 0x00020000U
2707 #define RTC_TSTR_HU_2 0x00040000U
2708 #define RTC_TSTR_HU_3 0x00080000U
2709 #define RTC_TSTR_MNT 0x00007000U
2710 #define RTC_TSTR_MNT_0 0x00001000U
2711 #define RTC_TSTR_MNT_1 0x00002000U
2712 #define RTC_TSTR_MNT_2 0x00004000U
2713 #define RTC_TSTR_MNU 0x00000F00U
2714 #define RTC_TSTR_MNU_0 0x00000100U
2715 #define RTC_TSTR_MNU_1 0x00000200U
2716 #define RTC_TSTR_MNU_2 0x00000400U
2717 #define RTC_TSTR_MNU_3 0x00000800U
2718 #define RTC_TSTR_ST 0x00000070U
2719 #define RTC_TSTR_ST_0 0x00000010U
2720 #define RTC_TSTR_ST_1 0x00000020U
2721 #define RTC_TSTR_ST_2 0x00000040U
2722 #define RTC_TSTR_SU 0x0000000FU
2723 #define RTC_TSTR_SU_0 0x00000001U
2724 #define RTC_TSTR_SU_1 0x00000002U
2725 #define RTC_TSTR_SU_2 0x00000004U
2726 #define RTC_TSTR_SU_3 0x00000008U
2727 
2728 /******************** Bits definition for RTC_TSDR register *****************/
2729 #define RTC_TSDR_WDU 0x0000E000U
2730 #define RTC_TSDR_WDU_0 0x00002000U
2731 #define RTC_TSDR_WDU_1 0x00004000U
2732 #define RTC_TSDR_WDU_2 0x00008000U
2733 #define RTC_TSDR_MT 0x00001000U
2734 #define RTC_TSDR_MU 0x00000F00U
2735 #define RTC_TSDR_MU_0 0x00000100U
2736 #define RTC_TSDR_MU_1 0x00000200U
2737 #define RTC_TSDR_MU_2 0x00000400U
2738 #define RTC_TSDR_MU_3 0x00000800U
2739 #define RTC_TSDR_DT 0x00000030U
2740 #define RTC_TSDR_DT_0 0x00000010U
2741 #define RTC_TSDR_DT_1 0x00000020U
2742 #define RTC_TSDR_DU 0x0000000FU
2743 #define RTC_TSDR_DU_0 0x00000001U
2744 #define RTC_TSDR_DU_1 0x00000002U
2745 #define RTC_TSDR_DU_2 0x00000004U
2746 #define RTC_TSDR_DU_3 0x00000008U
2747 
2748 /******************** Bits definition for RTC_TSSSR register ****************/
2749 #define RTC_TSSSR_SS 0x0000FFFFU
2750 
2751 /******************** Bits definition for RTC_CAL register *****************/
2752 #define RTC_CALR_CALP 0x00008000U
2753 #define RTC_CALR_CALW8 0x00004000U
2754 #define RTC_CALR_CALW16 0x00002000U
2755 #define RTC_CALR_CALM 0x000001FFU
2756 #define RTC_CALR_CALM_0 0x00000001U
2757 #define RTC_CALR_CALM_1 0x00000002U
2758 #define RTC_CALR_CALM_2 0x00000004U
2759 #define RTC_CALR_CALM_3 0x00000008U
2760 #define RTC_CALR_CALM_4 0x00000010U
2761 #define RTC_CALR_CALM_5 0x00000020U
2762 #define RTC_CALR_CALM_6 0x00000040U
2763 #define RTC_CALR_CALM_7 0x00000080U
2764 #define RTC_CALR_CALM_8 0x00000100U
2765 
2766 /******************** Bits definition for RTC_TAFCR register ****************/
2767 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
2768 #define RTC_TAFCR_TSINSEL 0x00020000U
2769 #define RTC_TAFCR_TAMPINSEL 0x00010000U
2770 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
2771 #define RTC_TAFCR_TAMPPRCH 0x00006000U
2772 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
2773 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
2774 #define RTC_TAFCR_TAMPFLT 0x00001800U
2775 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
2776 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
2777 #define RTC_TAFCR_TAMPFREQ 0x00000700U
2778 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
2779 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
2780 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
2781 #define RTC_TAFCR_TAMPTS 0x00000080U
2782 #define RTC_TAFCR_TAMP2TRG 0x00000010U
2783 #define RTC_TAFCR_TAMP2E 0x00000008U
2784 #define RTC_TAFCR_TAMPIE 0x00000004U
2785 #define RTC_TAFCR_TAMP1TRG 0x00000002U
2786 #define RTC_TAFCR_TAMP1E 0x00000001U
2787 
2788 /******************** Bits definition for RTC_ALRMASSR register *************/
2789 #define RTC_ALRMASSR_MASKSS 0x0F000000U
2790 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
2791 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
2792 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
2793 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
2794 #define RTC_ALRMASSR_SS 0x00007FFFU
2795 
2796 /******************** Bits definition for RTC_ALRMBSSR register *************/
2797 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
2798 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
2799 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
2800 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
2801 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
2802 #define RTC_ALRMBSSR_SS 0x00007FFFU
2803 
2804 /******************** Bits definition for RTC_BKP0R register ****************/
2805 #define RTC_BKP0R 0xFFFFFFFFU
2806 
2807 /******************** Bits definition for RTC_BKP1R register ****************/
2808 #define RTC_BKP1R 0xFFFFFFFFU
2809 
2810 /******************** Bits definition for RTC_BKP2R register ****************/
2811 #define RTC_BKP2R 0xFFFFFFFFU
2812 
2813 /******************** Bits definition for RTC_BKP3R register ****************/
2814 #define RTC_BKP3R 0xFFFFFFFFU
2815 
2816 /******************** Bits definition for RTC_BKP4R register ****************/
2817 #define RTC_BKP4R 0xFFFFFFFFU
2818 
2819 /******************** Bits definition for RTC_BKP5R register ****************/
2820 #define RTC_BKP5R 0xFFFFFFFFU
2821 
2822 /******************** Bits definition for RTC_BKP6R register ****************/
2823 #define RTC_BKP6R 0xFFFFFFFFU
2824 
2825 /******************** Bits definition for RTC_BKP7R register ****************/
2826 #define RTC_BKP7R 0xFFFFFFFFU
2827 
2828 /******************** Bits definition for RTC_BKP8R register ****************/
2829 #define RTC_BKP8R 0xFFFFFFFFU
2830 
2831 /******************** Bits definition for RTC_BKP9R register ****************/
2832 #define RTC_BKP9R 0xFFFFFFFFU
2833 
2834 /******************** Bits definition for RTC_BKP10R register ***************/
2835 #define RTC_BKP10R 0xFFFFFFFFU
2836 
2837 /******************** Bits definition for RTC_BKP11R register ***************/
2838 #define RTC_BKP11R 0xFFFFFFFFU
2839 
2840 /******************** Bits definition for RTC_BKP12R register ***************/
2841 #define RTC_BKP12R 0xFFFFFFFFU
2842 
2843 /******************** Bits definition for RTC_BKP13R register ***************/
2844 #define RTC_BKP13R 0xFFFFFFFFU
2845 
2846 /******************** Bits definition for RTC_BKP14R register ***************/
2847 #define RTC_BKP14R 0xFFFFFFFFU
2848 
2849 /******************** Bits definition for RTC_BKP15R register ***************/
2850 #define RTC_BKP15R 0xFFFFFFFFU
2851 
2852 /******************** Bits definition for RTC_BKP16R register ***************/
2853 #define RTC_BKP16R 0xFFFFFFFFU
2854 
2855 /******************** Bits definition for RTC_BKP17R register ***************/
2856 #define RTC_BKP17R 0xFFFFFFFFU
2857 
2858 /******************** Bits definition for RTC_BKP18R register ***************/
2859 #define RTC_BKP18R 0xFFFFFFFFU
2860 
2861 /******************** Bits definition for RTC_BKP19R register ***************/
2862 #define RTC_BKP19R 0xFFFFFFFFU
2863 
2864 /******************************************************************************/
2865 /* */
2866 /* Serial Peripheral Interface */
2867 /* */
2868 /******************************************************************************/
2869 /******************* Bit definition for SPI_CR1 register ********************/
2870 #define SPI_CR1_CPHA 0x00000001U
2871 #define SPI_CR1_CPOL 0x00000002U
2872 #define SPI_CR1_MSTR 0x00000004U
2874 #define SPI_CR1_BR 0x00000038U
2875 #define SPI_CR1_BR_0 0x00000008U
2876 #define SPI_CR1_BR_1 0x00000010U
2877 #define SPI_CR1_BR_2 0x00000020U
2879 #define SPI_CR1_SPE 0x00000040U
2880 #define SPI_CR1_LSBFIRST 0x00000080U
2881 #define SPI_CR1_SSI 0x00000100U
2882 #define SPI_CR1_SSM 0x00000200U
2883 #define SPI_CR1_RXONLY 0x00000400U
2884 #define SPI_CR1_DFF 0x00000800U
2885 #define SPI_CR1_CRCNEXT 0x00001000U
2886 #define SPI_CR1_CRCEN 0x00002000U
2887 #define SPI_CR1_BIDIOE 0x00004000U
2888 #define SPI_CR1_BIDIMODE 0x00008000U
2890 /******************* Bit definition for SPI_CR2 register ********************/
2891 #define SPI_CR2_RXDMAEN 0x00000001U
2892 #define SPI_CR2_TXDMAEN 0x00000002U
2893 #define SPI_CR2_SSOE 0x00000004U
2894 #define SPI_CR2_FRF 0x00000010U
2895 #define SPI_CR2_ERRIE 0x00000020U
2896 #define SPI_CR2_RXNEIE 0x00000040U
2897 #define SPI_CR2_TXEIE 0x00000080U
2899 /******************** Bit definition for SPI_SR register ********************/
2900 #define SPI_SR_RXNE 0x00000001U
2901 #define SPI_SR_TXE 0x00000002U
2902 #define SPI_SR_CHSIDE 0x00000004U
2903 #define SPI_SR_UDR 0x00000008U
2904 #define SPI_SR_CRCERR 0x00000010U
2905 #define SPI_SR_MODF 0x00000020U
2906 #define SPI_SR_OVR 0x00000040U
2907 #define SPI_SR_BSY 0x00000080U
2908 #define SPI_SR_FRE 0x00000100U
2910 /******************** Bit definition for SPI_DR register ********************/
2911 #define SPI_DR_DR 0x0000FFFFU
2913 /******************* Bit definition for SPI_CRCPR register ******************/
2914 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
2916 /****************** Bit definition for SPI_RXCRCR register ******************/
2917 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
2919 /****************** Bit definition for SPI_TXCRCR register ******************/
2920 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
2922 /****************** Bit definition for SPI_I2SCFGR register *****************/
2923 #define SPI_I2SCFGR_CHLEN 0x00000001U
2925 #define SPI_I2SCFGR_DATLEN 0x00000006U
2926 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
2927 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
2929 #define SPI_I2SCFGR_CKPOL 0x00000008U
2931 #define SPI_I2SCFGR_I2SSTD 0x00000030U
2932 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
2933 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
2935 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
2937 #define SPI_I2SCFGR_I2SCFG 0x00000300U
2938 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
2939 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
2941 #define SPI_I2SCFGR_I2SE 0x00000400U
2942 #define SPI_I2SCFGR_I2SMOD 0x00000800U
2944 /****************** Bit definition for SPI_I2SPR register *******************/
2945 #define SPI_I2SPR_I2SDIV 0x000000FFU
2946 #define SPI_I2SPR_ODD 0x00000100U
2947 #define SPI_I2SPR_MCKOE 0x00000200U
2949 /******************************************************************************/
2950 /* */
2951 /* SYSCFG */
2952 /* */
2953 /******************************************************************************/
2954 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
2955 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
2956 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
2957 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
2958 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
2959 
2960 /****************** Bit definition for SYSCFG_PMC register ******************/
2961 #define SYSCFG_PMC_ADC1DC2 0x00010000U
2963 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
2964 #define SYSCFG_EXTICR1_EXTI0 0x000FU
2965 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
2966 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
2967 #define SYSCFG_EXTICR1_EXTI3 0xF000U
2971 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
2972 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
2973 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
2974 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
2979 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
2980 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
2981 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
2982 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
2987 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
2988 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
2989 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
2990 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
2995 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
2996 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
2997 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
2998 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
3000 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
3001 #define SYSCFG_EXTICR2_EXTI4 0x000FU
3002 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
3003 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
3004 #define SYSCFG_EXTICR2_EXTI7 0xF000U
3008 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
3009 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
3010 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
3011 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
3016 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
3017 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
3018 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
3019 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
3024 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
3025 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
3026 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
3027 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
3032 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
3033 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
3034 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
3035 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
3038 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
3039 #define SYSCFG_EXTICR3_EXTI8 0x000FU
3040 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
3041 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
3042 #define SYSCFG_EXTICR3_EXTI11 0xF000U
3047 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
3048 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
3049 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
3050 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
3055 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
3056 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
3057 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
3058 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
3063 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
3064 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
3065 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
3066 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
3071 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
3072 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
3073 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
3074 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
3076 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
3077 #define SYSCFG_EXTICR4_EXTI12 0x000FU
3078 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
3079 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
3080 #define SYSCFG_EXTICR4_EXTI15 0xF000U
3084 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
3085 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
3086 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
3087 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
3092 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
3093 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
3094 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
3095 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
3100 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
3101 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
3102 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
3103 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
3108 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
3109 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
3110 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
3111 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
3113 /****************** Bit definition for SYSCFG_CMPCR register ****************/
3114 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
3115 #define SYSCFG_CMPCR_READY 0x00000100U
3117 /****************** Bit definition for SYSCFG_CFGR register *****************/
3118 #define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U
3119 #define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U
3121 /****************** Bit definition for SYSCFG_CFGR2 register *****************/
3122 #define SYSCFG_CFGR2_LOCKUP_LOCK 0x00000001U
3123 #define SYSCFG_CFGR2_PVD_LOCK 0x00000004U
3125 /******************************************************************************/
3126 /* */
3127 /* TIM */
3128 /* */
3129 /******************************************************************************/
3130 /******************* Bit definition for TIM_CR1 register ********************/
3131 #define TIM_CR1_CEN 0x0001U
3132 #define TIM_CR1_UDIS 0x0002U
3133 #define TIM_CR1_URS 0x0004U
3134 #define TIM_CR1_OPM 0x0008U
3135 #define TIM_CR1_DIR 0x0010U
3137 #define TIM_CR1_CMS 0x0060U
3138 #define TIM_CR1_CMS_0 0x0020U
3139 #define TIM_CR1_CMS_1 0x0040U
3141 #define TIM_CR1_ARPE 0x0080U
3143 #define TIM_CR1_CKD 0x0300U
3144 #define TIM_CR1_CKD_0 0x0100U
3145 #define TIM_CR1_CKD_1 0x0200U
3147 /******************* Bit definition for TIM_CR2 register ********************/
3148 #define TIM_CR2_CCPC 0x0001U
3149 #define TIM_CR2_CCUS 0x0004U
3150 #define TIM_CR2_CCDS 0x0008U
3152 #define TIM_CR2_MMS 0x0070U
3153 #define TIM_CR2_MMS_0 0x0010U
3154 #define TIM_CR2_MMS_1 0x0020U
3155 #define TIM_CR2_MMS_2 0x0040U
3157 #define TIM_CR2_TI1S 0x0080U
3158 #define TIM_CR2_OIS1 0x0100U
3159 #define TIM_CR2_OIS1N 0x0200U
3160 #define TIM_CR2_OIS2 0x0400U
3161 #define TIM_CR2_OIS2N 0x0800U
3162 #define TIM_CR2_OIS3 0x1000U
3163 #define TIM_CR2_OIS3N 0x2000U
3164 #define TIM_CR2_OIS4 0x4000U
3166 /******************* Bit definition for TIM_SMCR register *******************/
3167 #define TIM_SMCR_SMS 0x0007U
3168 #define TIM_SMCR_SMS_0 0x0001U
3169 #define TIM_SMCR_SMS_1 0x0002U
3170 #define TIM_SMCR_SMS_2 0x0004U
3172 #define TIM_SMCR_TS 0x0070U
3173 #define TIM_SMCR_TS_0 0x0010U
3174 #define TIM_SMCR_TS_1 0x0020U
3175 #define TIM_SMCR_TS_2 0x0040U
3177 #define TIM_SMCR_MSM 0x0080U
3179 #define TIM_SMCR_ETF 0x0F00U
3180 #define TIM_SMCR_ETF_0 0x0100U
3181 #define TIM_SMCR_ETF_1 0x0200U
3182 #define TIM_SMCR_ETF_2 0x0400U
3183 #define TIM_SMCR_ETF_3 0x0800U
3185 #define TIM_SMCR_ETPS 0x3000U
3186 #define TIM_SMCR_ETPS_0 0x1000U
3187 #define TIM_SMCR_ETPS_1 0x2000U
3189 #define TIM_SMCR_ECE 0x4000U
3190 #define TIM_SMCR_ETP 0x8000U
3192 /******************* Bit definition for TIM_DIER register *******************/
3193 #define TIM_DIER_UIE 0x0001U
3194 #define TIM_DIER_CC1IE 0x0002U
3195 #define TIM_DIER_CC2IE 0x0004U
3196 #define TIM_DIER_CC3IE 0x0008U
3197 #define TIM_DIER_CC4IE 0x0010U
3198 #define TIM_DIER_COMIE 0x0020U
3199 #define TIM_DIER_TIE 0x0040U
3200 #define TIM_DIER_BIE 0x0080U
3201 #define TIM_DIER_UDE 0x0100U
3202 #define TIM_DIER_CC1DE 0x0200U
3203 #define TIM_DIER_CC2DE 0x0400U
3204 #define TIM_DIER_CC3DE 0x0800U
3205 #define TIM_DIER_CC4DE 0x1000U
3206 #define TIM_DIER_COMDE 0x2000U
3207 #define TIM_DIER_TDE 0x4000U
3209 /******************** Bit definition for TIM_SR register ********************/
3210 #define TIM_SR_UIF 0x0001U
3211 #define TIM_SR_CC1IF 0x0002U
3212 #define TIM_SR_CC2IF 0x0004U
3213 #define TIM_SR_CC3IF 0x0008U
3214 #define TIM_SR_CC4IF 0x0010U
3215 #define TIM_SR_COMIF 0x0020U
3216 #define TIM_SR_TIF 0x0040U
3217 #define TIM_SR_BIF 0x0080U
3218 #define TIM_SR_CC1OF 0x0200U
3219 #define TIM_SR_CC2OF 0x0400U
3220 #define TIM_SR_CC3OF 0x0800U
3221 #define TIM_SR_CC4OF 0x1000U
3223 /******************* Bit definition for TIM_EGR register ********************/
3224 #define TIM_EGR_UG 0x01U
3225 #define TIM_EGR_CC1G 0x02U
3226 #define TIM_EGR_CC2G 0x04U
3227 #define TIM_EGR_CC3G 0x08U
3228 #define TIM_EGR_CC4G 0x10U
3229 #define TIM_EGR_COMG 0x20U
3230 #define TIM_EGR_TG 0x40U
3231 #define TIM_EGR_BG 0x80U
3233 /****************** Bit definition for TIM_CCMR1 register *******************/
3234 #define TIM_CCMR1_CC1S 0x0003U
3235 #define TIM_CCMR1_CC1S_0 0x0001U
3236 #define TIM_CCMR1_CC1S_1 0x0002U
3238 #define TIM_CCMR1_OC1FE 0x0004U
3239 #define TIM_CCMR1_OC1PE 0x0008U
3241 #define TIM_CCMR1_OC1M 0x0070U
3242 #define TIM_CCMR1_OC1M_0 0x0010U
3243 #define TIM_CCMR1_OC1M_1 0x0020U
3244 #define TIM_CCMR1_OC1M_2 0x0040U
3246 #define TIM_CCMR1_OC1CE 0x0080U
3248 #define TIM_CCMR1_CC2S 0x0300U
3249 #define TIM_CCMR1_CC2S_0 0x0100U
3250 #define TIM_CCMR1_CC2S_1 0x0200U
3252 #define TIM_CCMR1_OC2FE 0x0400U
3253 #define TIM_CCMR1_OC2PE 0x0800U
3255 #define TIM_CCMR1_OC2M 0x7000U
3256 #define TIM_CCMR1_OC2M_0 0x1000U
3257 #define TIM_CCMR1_OC2M_1 0x2000U
3258 #define TIM_CCMR1_OC2M_2 0x4000U
3260 #define TIM_CCMR1_OC2CE 0x8000U
3262 /*----------------------------------------------------------------------------*/
3263 
3264 #define TIM_CCMR1_IC1PSC 0x000CU
3265 #define TIM_CCMR1_IC1PSC_0 0x0004U
3266 #define TIM_CCMR1_IC1PSC_1 0x0008U
3268 #define TIM_CCMR1_IC1F 0x00F0U
3269 #define TIM_CCMR1_IC1F_0 0x0010U
3270 #define TIM_CCMR1_IC1F_1 0x0020U
3271 #define TIM_CCMR1_IC1F_2 0x0040U
3272 #define TIM_CCMR1_IC1F_3 0x0080U
3274 #define TIM_CCMR1_IC2PSC 0x0C00U
3275 #define TIM_CCMR1_IC2PSC_0 0x0400U
3276 #define TIM_CCMR1_IC2PSC_1 0x0800U
3278 #define TIM_CCMR1_IC2F 0xF000U
3279 #define TIM_CCMR1_IC2F_0 0x1000U
3280 #define TIM_CCMR1_IC2F_1 0x2000U
3281 #define TIM_CCMR1_IC2F_2 0x4000U
3282 #define TIM_CCMR1_IC2F_3 0x8000U
3284 /****************** Bit definition for TIM_CCMR2 register *******************/
3285 #define TIM_CCMR2_CC3S 0x0003U
3286 #define TIM_CCMR2_CC3S_0 0x0001U
3287 #define TIM_CCMR2_CC3S_1 0x0002U
3289 #define TIM_CCMR2_OC3FE 0x0004U
3290 #define TIM_CCMR2_OC3PE 0x0008U
3292 #define TIM_CCMR2_OC3M 0x0070U
3293 #define TIM_CCMR2_OC3M_0 0x0010U
3294 #define TIM_CCMR2_OC3M_1 0x0020U
3295 #define TIM_CCMR2_OC3M_2 0x0040U
3297 #define TIM_CCMR2_OC3CE 0x0080U
3299 #define TIM_CCMR2_CC4S 0x0300U
3300 #define TIM_CCMR2_CC4S_0 0x0100U
3301 #define TIM_CCMR2_CC4S_1 0x0200U
3303 #define TIM_CCMR2_OC4FE 0x0400U
3304 #define TIM_CCMR2_OC4PE 0x0800U
3306 #define TIM_CCMR2_OC4M 0x7000U
3307 #define TIM_CCMR2_OC4M_0 0x1000U
3308 #define TIM_CCMR2_OC4M_1 0x2000U
3309 #define TIM_CCMR2_OC4M_2 0x4000U
3311 #define TIM_CCMR2_OC4CE 0x8000U
3313 /*----------------------------------------------------------------------------*/
3314 
3315 #define TIM_CCMR2_IC3PSC 0x000CU
3316 #define TIM_CCMR2_IC3PSC_0 0x0004U
3317 #define TIM_CCMR2_IC3PSC_1 0x0008U
3319 #define TIM_CCMR2_IC3F 0x00F0U
3320 #define TIM_CCMR2_IC3F_0 0x0010U
3321 #define TIM_CCMR2_IC3F_1 0x0020U
3322 #define TIM_CCMR2_IC3F_2 0x0040U
3323 #define TIM_CCMR2_IC3F_3 0x0080U
3325 #define TIM_CCMR2_IC4PSC 0x0C00U
3326 #define TIM_CCMR2_IC4PSC_0 0x0400U
3327 #define TIM_CCMR2_IC4PSC_1 0x0800U
3329 #define TIM_CCMR2_IC4F 0xF000U
3330 #define TIM_CCMR2_IC4F_0 0x1000U
3331 #define TIM_CCMR2_IC4F_1 0x2000U
3332 #define TIM_CCMR2_IC4F_2 0x4000U
3333 #define TIM_CCMR2_IC4F_3 0x8000U
3335 /******************* Bit definition for TIM_CCER register *******************/
3336 #define TIM_CCER_CC1E 0x0001U
3337 #define TIM_CCER_CC1P 0x0002U
3338 #define TIM_CCER_CC1NE 0x0004U
3339 #define TIM_CCER_CC1NP 0x0008U
3340 #define TIM_CCER_CC2E 0x0010U
3341 #define TIM_CCER_CC2P 0x0020U
3342 #define TIM_CCER_CC2NE 0x0040U
3343 #define TIM_CCER_CC2NP 0x0080U
3344 #define TIM_CCER_CC3E 0x0100U
3345 #define TIM_CCER_CC3P 0x0200U
3346 #define TIM_CCER_CC3NE 0x0400U
3347 #define TIM_CCER_CC3NP 0x0800U
3348 #define TIM_CCER_CC4E 0x1000U
3349 #define TIM_CCER_CC4P 0x2000U
3350 #define TIM_CCER_CC4NP 0x8000U
3352 /******************* Bit definition for TIM_CNT register ********************/
3353 #define TIM_CNT_CNT 0xFFFFU
3355 /******************* Bit definition for TIM_PSC register ********************/
3356 #define TIM_PSC_PSC 0xFFFFU
3358 /******************* Bit definition for TIM_ARR register ********************/
3359 #define TIM_ARR_ARR 0xFFFFU
3361 /******************* Bit definition for TIM_RCR register ********************/
3362 #define TIM_RCR_REP 0xFFU
3364 /******************* Bit definition for TIM_CCR1 register *******************/
3365 #define TIM_CCR1_CCR1 0xFFFFU
3367 /******************* Bit definition for TIM_CCR2 register *******************/
3368 #define TIM_CCR2_CCR2 0xFFFFU
3370 /******************* Bit definition for TIM_CCR3 register *******************/
3371 #define TIM_CCR3_CCR3 0xFFFFU
3373 /******************* Bit definition for TIM_CCR4 register *******************/
3374 #define TIM_CCR4_CCR4 0xFFFFU
3376 /******************* Bit definition for TIM_BDTR register *******************/
3377 #define TIM_BDTR_DTG 0x00FFU
3378 #define TIM_BDTR_DTG_0 0x0001U
3379 #define TIM_BDTR_DTG_1 0x0002U
3380 #define TIM_BDTR_DTG_2 0x0004U
3381 #define TIM_BDTR_DTG_3 0x0008U
3382 #define TIM_BDTR_DTG_4 0x0010U
3383 #define TIM_BDTR_DTG_5 0x0020U
3384 #define TIM_BDTR_DTG_6 0x0040U
3385 #define TIM_BDTR_DTG_7 0x0080U
3387 #define TIM_BDTR_LOCK 0x0300U
3388 #define TIM_BDTR_LOCK_0 0x0100U
3389 #define TIM_BDTR_LOCK_1 0x0200U
3391 #define TIM_BDTR_OSSI 0x0400U
3392 #define TIM_BDTR_OSSR 0x0800U
3393 #define TIM_BDTR_BKE 0x1000U
3394 #define TIM_BDTR_BKP 0x2000U
3395 #define TIM_BDTR_AOE 0x4000U
3396 #define TIM_BDTR_MOE 0x8000U
3398 /******************* Bit definition for TIM_DCR register ********************/
3399 #define TIM_DCR_DBA 0x001FU
3400 #define TIM_DCR_DBA_0 0x0001U
3401 #define TIM_DCR_DBA_1 0x0002U
3402 #define TIM_DCR_DBA_2 0x0004U
3403 #define TIM_DCR_DBA_3 0x0008U
3404 #define TIM_DCR_DBA_4 0x0010U
3406 #define TIM_DCR_DBL 0x1F00U
3407 #define TIM_DCR_DBL_0 0x0100U
3408 #define TIM_DCR_DBL_1 0x0200U
3409 #define TIM_DCR_DBL_2 0x0400U
3410 #define TIM_DCR_DBL_3 0x0800U
3411 #define TIM_DCR_DBL_4 0x1000U
3413 /******************* Bit definition for TIM_DMAR register *******************/
3414 #define TIM_DMAR_DMAB 0xFFFFU
3416 /******************* Bit definition for TIM_OR register *********************/
3417 #define TIM_OR_TI4_RMP 0x00C0U
3418 #define TIM_OR_TI4_RMP_0 0x0040U
3419 #define TIM_OR_TI4_RMP_1 0x0080U
3421 /******************************************************************************/
3422 /* */
3423 /* Low Power Timer (LPTIM) */
3424 /* */
3425 /******************************************************************************/
3426 /****************** Bit definition for LPTIM_ISR register *******************/
3427 #define LPTIM_ISR_CMPM 0x00000001U
3428 #define LPTIM_ISR_ARRM 0x00000002U
3429 #define LPTIM_ISR_EXTTRIG 0x00000004U
3430 #define LPTIM_ISR_CMPOK 0x00000008U
3431 #define LPTIM_ISR_ARROK 0x00000010U
3432 #define LPTIM_ISR_UP 0x00000020U
3433 #define LPTIM_ISR_DOWN 0x00000040U
3435 /****************** Bit definition for LPTIM_ICR register *******************/
3436 #define LPTIM_ICR_CMPMCF 0x00000001U
3437 #define LPTIM_ICR_ARRMCF 0x00000002U
3438 #define LPTIM_ICR_EXTTRIGCF 0x00000004U
3439 #define LPTIM_ICR_CMPOKCF 0x00000008U
3440 #define LPTIM_ICR_ARROKCF 0x00000010U
3441 #define LPTIM_ICR_UPCF 0x00000020U
3442 #define LPTIM_ICR_DOWNCF 0x00000040U
3444 /****************** Bit definition for LPTIM_IER register ********************/
3445 #define LPTIM_IER_CMPMIE 0x00000001U
3446 #define LPTIM_IER_ARRMIE 0x00000002U
3447 #define LPTIM_IER_EXTTRIGIE 0x00000004U
3448 #define LPTIM_IER_CMPOKIE 0x00000008U
3449 #define LPTIM_IER_ARROKIE 0x00000010U
3450 #define LPTIM_IER_UPIE 0x00000020U
3451 #define LPTIM_IER_DOWNIE 0x00000040U
3453 /****************** Bit definition for LPTIM_CFGR register *******************/
3454 #define LPTIM_CFGR_CKSEL 0x00000001U
3456 #define LPTIM_CFGR_CKPOL 0x00000006U
3457 #define LPTIM_CFGR_CKPOL_0 0x00000002U
3458 #define LPTIM_CFGR_CKPOL_1 0x00000004U
3460 #define LPTIM_CFGR_CKFLT 0x00000018U
3461 #define LPTIM_CFGR_CKFLT_0 0x00000008U
3462 #define LPTIM_CFGR_CKFLT_1 0x00000010U
3464 #define LPTIM_CFGR_TRGFLT 0x000000C0U
3465 #define LPTIM_CFGR_TRGFLT_0 0x00000040U
3466 #define LPTIM_CFGR_TRGFLT_1 0x00000080U
3468 #define LPTIM_CFGR_PRESC 0x00000E00U
3469 #define LPTIM_CFGR_PRESC_0 0x00000200U
3470 #define LPTIM_CFGR_PRESC_1 0x00000400U
3471 #define LPTIM_CFGR_PRESC_2 0x00000800U
3473 #define LPTIM_CFGR_TRIGSEL 0x0000E000U
3474 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U
3475 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U
3476 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U
3478 #define LPTIM_CFGR_TRIGEN 0x00060000U
3479 #define LPTIM_CFGR_TRIGEN_0 0x00020000U
3480 #define LPTIM_CFGR_TRIGEN_1 0x00040000U
3482 #define LPTIM_CFGR_TIMOUT 0x00080000U
3483 #define LPTIM_CFGR_WAVE 0x00100000U
3484 #define LPTIM_CFGR_WAVPOL 0x00200000U
3485 #define LPTIM_CFGR_PRELOAD 0x00400000U
3486 #define LPTIM_CFGR_COUNTMODE 0x00800000U
3487 #define LPTIM_CFGR_ENC 0x01000000U
3489 /****************** Bit definition for LPTIM_CR register ********************/
3490 #define LPTIM_CR_ENABLE 0x00000001U
3491 #define LPTIM_CR_SNGSTRT 0x00000002U
3492 #define LPTIM_CR_CNTSTRT 0x00000004U
3494 /****************** Bit definition for LPTIM_CMP register *******************/
3495 #define LPTIM_CMP_CMP 0x0000FFFFU
3497 /****************** Bit definition for LPTIM_ARR register *******************/
3498 #define LPTIM_ARR_ARR 0x0000FFFFU
3500 /****************** Bit definition for LPTIM_CNT register *******************/
3501 #define LPTIM_CNT_CNT 0x0000FFFFU
3503 /****************** Bit definition for LPTIM_OR register *******************/
3504 #define LPTIM_OR_OR 0x00000003U
3505 #define LPTIM_OR_OR_0 0x00000001U
3506 #define LPTIM_OR_OR_1 0x00000002U
3508 /******************************************************************************/
3509 /* */
3510 /* Universal Synchronous Asynchronous Receiver Transmitter */
3511 /* */
3512 /******************************************************************************/
3513 /******************* Bit definition for USART_SR register *******************/
3514 #define USART_SR_PE 0x0001U
3515 #define USART_SR_FE 0x0002U
3516 #define USART_SR_NE 0x0004U
3517 #define USART_SR_ORE 0x0008U
3518 #define USART_SR_IDLE 0x0010U
3519 #define USART_SR_RXNE 0x0020U
3520 #define USART_SR_TC 0x0040U
3521 #define USART_SR_TXE 0x0080U
3522 #define USART_SR_LBD 0x0100U
3523 #define USART_SR_CTS 0x0200U
3525 /******************* Bit definition for USART_DR register *******************/
3526 #define USART_DR_DR 0x01FFU
3528 /****************** Bit definition for USART_BRR register *******************/
3529 #define USART_BRR_DIV_Fraction 0x000FU
3530 #define USART_BRR_DIV_Mantissa 0xFFF0U
3532 /****************** Bit definition for USART_CR1 register *******************/
3533 #define USART_CR1_SBK 0x0001U
3534 #define USART_CR1_RWU 0x0002U
3535 #define USART_CR1_RE 0x0004U
3536 #define USART_CR1_TE 0x0008U
3537 #define USART_CR1_IDLEIE 0x0010U
3538 #define USART_CR1_RXNEIE 0x0020U
3539 #define USART_CR1_TCIE 0x0040U
3540 #define USART_CR1_TXEIE 0x0080U
3541 #define USART_CR1_PEIE 0x0100U
3542 #define USART_CR1_PS 0x0200U
3543 #define USART_CR1_PCE 0x0400U
3544 #define USART_CR1_WAKE 0x0800U
3545 #define USART_CR1_M 0x1000U
3546 #define USART_CR1_UE 0x2000U
3547 #define USART_CR1_OVER8 0x8000U
3549 /****************** Bit definition for USART_CR2 register *******************/
3550 #define USART_CR2_ADD 0x000FU
3551 #define USART_CR2_LBDL 0x0020U
3552 #define USART_CR2_LBDIE 0x0040U
3553 #define USART_CR2_LBCL 0x0100U
3554 #define USART_CR2_CPHA 0x0200U
3555 #define USART_CR2_CPOL 0x0400U
3556 #define USART_CR2_CLKEN 0x0800U
3558 #define USART_CR2_STOP 0x3000U
3559 #define USART_CR2_STOP_0 0x1000U
3560 #define USART_CR2_STOP_1 0x2000U
3562 #define USART_CR2_LINEN 0x4000U
3564 /****************** Bit definition for USART_CR3 register *******************/
3565 #define USART_CR3_EIE 0x0001U
3566 #define USART_CR3_IREN 0x0002U
3567 #define USART_CR3_IRLP 0x0004U
3568 #define USART_CR3_HDSEL 0x0008U
3569 #define USART_CR3_NACK 0x0010U
3570 #define USART_CR3_SCEN 0x0020U
3571 #define USART_CR3_DMAR 0x0040U
3572 #define USART_CR3_DMAT 0x0080U
3573 #define USART_CR3_RTSE 0x0100U
3574 #define USART_CR3_CTSE 0x0200U
3575 #define USART_CR3_CTSIE 0x0400U
3576 #define USART_CR3_ONEBIT 0x0800U
3578 /****************** Bit definition for USART_GTPR register ******************/
3579 #define USART_GTPR_PSC 0x00FFU
3580 #define USART_GTPR_PSC_0 0x0001U
3581 #define USART_GTPR_PSC_1 0x0002U
3582 #define USART_GTPR_PSC_2 0x0004U
3583 #define USART_GTPR_PSC_3 0x0008U
3584 #define USART_GTPR_PSC_4 0x0010U
3585 #define USART_GTPR_PSC_5 0x0020U
3586 #define USART_GTPR_PSC_6 0x0040U
3587 #define USART_GTPR_PSC_7 0x0080U
3589 #define USART_GTPR_GT 0xFF00U
3591 /******************************************************************************/
3592 /* */
3593 /* Window WATCHDOG */
3594 /* */
3595 /******************************************************************************/
3596 /******************* Bit definition for WWDG_CR register ********************/
3597 #define WWDG_CR_T 0x7FU
3598 #define WWDG_CR_T_0 0x01U
3599 #define WWDG_CR_T_1 0x02U
3600 #define WWDG_CR_T_2 0x04U
3601 #define WWDG_CR_T_3 0x08U
3602 #define WWDG_CR_T_4 0x10U
3603 #define WWDG_CR_T_5 0x20U
3604 #define WWDG_CR_T_6 0x40U
3605 /* Legacy defines */
3606 #define WWDG_CR_T0 WWDG_CR_T_0
3607 #define WWDG_CR_T1 WWDG_CR_T_1
3608 #define WWDG_CR_T2 WWDG_CR_T_2
3609 #define WWDG_CR_T3 WWDG_CR_T_3
3610 #define WWDG_CR_T4 WWDG_CR_T_4
3611 #define WWDG_CR_T5 WWDG_CR_T_5
3612 #define WWDG_CR_T6 WWDG_CR_T_6
3613 
3614 #define WWDG_CR_WDGA 0x80U
3616 /******************* Bit definition for WWDG_CFR register *******************/
3617 #define WWDG_CFR_W 0x007FU
3618 #define WWDG_CFR_W_0 0x0001U
3619 #define WWDG_CFR_W_1 0x0002U
3620 #define WWDG_CFR_W_2 0x0004U
3621 #define WWDG_CFR_W_3 0x0008U
3622 #define WWDG_CFR_W_4 0x0010U
3623 #define WWDG_CFR_W_5 0x0020U
3624 #define WWDG_CFR_W_6 0x0040U
3625 /* Legacy defines */
3626 #define WWDG_CFR_W0 WWDG_CFR_W_0
3627 #define WWDG_CFR_W1 WWDG_CFR_W_1
3628 #define WWDG_CFR_W2 WWDG_CFR_W_2
3629 #define WWDG_CFR_W3 WWDG_CFR_W_3
3630 #define WWDG_CFR_W4 WWDG_CFR_W_4
3631 #define WWDG_CFR_W5 WWDG_CFR_W_5
3632 #define WWDG_CFR_W6 WWDG_CFR_W_6
3633 
3634 #define WWDG_CFR_WDGTB 0x0180U
3635 #define WWDG_CFR_WDGTB_0 0x0080U
3636 #define WWDG_CFR_WDGTB_1 0x0100U
3637 /* Legacy defines */
3638 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
3639 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
3640 
3641 #define WWDG_CFR_EWI 0x0200U
3643 /******************* Bit definition for WWDG_SR register ********************/
3644 #define WWDG_SR_EWIF 0x01U
3646 /******************************************************************************/
3647 /* */
3648 /* Digital to Analog Converter */
3649 /* */
3650 /******************************************************************************/
3651 /******************** Bit definition for DAC_CR register ********************/
3652 #define DAC_CR_EN1 0x00000001U
3653 #define DAC_CR_BOFF1 0x00000002U
3654 #define DAC_CR_TEN1 0x00000004U
3656 #define DAC_CR_TSEL1 0x00000038U
3657 #define DAC_CR_TSEL1_0 0x00000008U
3658 #define DAC_CR_TSEL1_1 0x00000010U
3659 #define DAC_CR_TSEL1_2 0x00000020U
3661 #define DAC_CR_WAVE1 0x000000C0U
3662 #define DAC_CR_WAVE1_0 0x00000040U
3663 #define DAC_CR_WAVE1_1 0x00000080U
3665 #define DAC_CR_MAMP1 0x00000F00U
3666 #define DAC_CR_MAMP1_0 0x00000100U
3667 #define DAC_CR_MAMP1_1 0x00000200U
3668 #define DAC_CR_MAMP1_2 0x00000400U
3669 #define DAC_CR_MAMP1_3 0x00000800U
3671 #define DAC_CR_DMAEN1 0x00001000U
3672 #define DAC_CR_DMAUDRIE1 0x00002000U
3673 #define DAC_CR_EN2 0x00010000U
3674 #define DAC_CR_BOFF2 0x00020000U
3675 #define DAC_CR_TEN2 0x00040000U
3677 #define DAC_CR_TSEL2 0x00380000U
3678 #define DAC_CR_TSEL2_0 0x00080000U
3679 #define DAC_CR_TSEL2_1 0x00100000U
3680 #define DAC_CR_TSEL2_2 0x00200000U
3682 #define DAC_CR_WAVE2 0x00C00000U
3683 #define DAC_CR_WAVE2_0 0x00400000U
3684 #define DAC_CR_WAVE2_1 0x00800000U
3686 #define DAC_CR_MAMP2 0x0F000000U
3687 #define DAC_CR_MAMP2_0 0x01000000U
3688 #define DAC_CR_MAMP2_1 0x02000000U
3689 #define DAC_CR_MAMP2_2 0x04000000U
3690 #define DAC_CR_MAMP2_3 0x08000000U
3692 #define DAC_CR_DMAEN2 0x10000000U
3693 #define DAC_CR_DMAUDRIE2 0x20000000U
3695 /***************** Bit definition for DAC_SWTRIGR register ******************/
3696 #define DAC_SWTRIGR_SWTRIG1 0x01U
3697 #define DAC_SWTRIGR_SWTRIG2 0x02U
3699 /***************** Bit definition for DAC_DHR12R1 register ******************/
3700 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3702 /***************** Bit definition for DAC_DHR12L1 register ******************/
3703 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3705 /****************** Bit definition for DAC_DHR8R1 register ******************/
3706 #define DAC_DHR8R1_DACC1DHR 0xFFU
3708 /***************** Bit definition for DAC_DHR12R2 register ******************/
3709 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3711 /***************** Bit definition for DAC_DHR12L2 register ******************/
3712 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3714 /****************** Bit definition for DAC_DHR8R2 register ******************/
3715 #define DAC_DHR8R2_DACC2DHR 0xFFU
3717 /***************** Bit definition for DAC_DHR12RD register ******************/
3718 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3719 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3721 /***************** Bit definition for DAC_DHR12LD register ******************/
3722 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3723 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3725 /****************** Bit definition for DAC_DHR8RD register ******************/
3726 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3727 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3729 /******************* Bit definition for DAC_DOR1 register *******************/
3730 #define DAC_DOR1_DACC1DOR 0x0FFFU
3732 /******************* Bit definition for DAC_DOR2 register *******************/
3733 #define DAC_DOR2_DACC2DOR 0x0FFFU
3735 /******************** Bit definition for DAC_SR register ********************/
3736 #define DAC_SR_DMAUDR1 0x00002000U
3737 #define DAC_SR_DMAUDR2 0x20000000U
3738 /******************************************************************************/
3739 /* */
3740 /* DBG */
3741 /* */
3742 /******************************************************************************/
3743 /******************** Bit definition for DBGMCU_IDCODE register *************/
3744 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
3745 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
3746 
3747 /******************** Bit definition for DBGMCU_CR register *****************/
3748 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
3749 #define DBGMCU_CR_DBG_STOP 0x00000002U
3750 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
3751 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
3752 
3753 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
3754 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
3755 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
3757 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
3758 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
3759 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
3760 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
3761 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
3762 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
3763 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
3764 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
3765 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
3766 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
3767 
3768 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
3769 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
3770 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
3771 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
3772 
3785 /******************************* ADC Instances ********************************/
3786 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
3787 
3788 /******************************* CRC Instances ********************************/
3789 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
3790 
3791 /******************************* DAC Instances ********************************/
3792 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
3793 
3794 /******************************** DMA Instances *******************************/
3795 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
3796  ((INSTANCE) == DMA1_Stream1) || \
3797  ((INSTANCE) == DMA1_Stream2) || \
3798  ((INSTANCE) == DMA1_Stream3) || \
3799  ((INSTANCE) == DMA1_Stream4) || \
3800  ((INSTANCE) == DMA1_Stream5) || \
3801  ((INSTANCE) == DMA1_Stream6) || \
3802  ((INSTANCE) == DMA1_Stream7) || \
3803  ((INSTANCE) == DMA2_Stream0) || \
3804  ((INSTANCE) == DMA2_Stream1) || \
3805  ((INSTANCE) == DMA2_Stream2) || \
3806  ((INSTANCE) == DMA2_Stream3) || \
3807  ((INSTANCE) == DMA2_Stream4) || \
3808  ((INSTANCE) == DMA2_Stream5) || \
3809  ((INSTANCE) == DMA2_Stream6) || \
3810  ((INSTANCE) == DMA2_Stream7))
3811 
3812 /******************************* GPIO Instances *******************************/
3813 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
3814  ((INSTANCE) == GPIOB) || \
3815  ((INSTANCE) == GPIOC) || \
3816  ((INSTANCE) == GPIOH))
3817 
3818 /******************************** I2C Instances *******************************/
3819 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
3820  ((INSTANCE) == I2C2))
3821 /******************************** I2S Instances *******************************/
3822 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
3823  ((INSTANCE) == SPI2) || \
3824  ((INSTANCE) == SPI5))
3825 
3826 /******************************* LPTIM Instances ******************************/
3827 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
3828 
3829 /******************************* RNG Instances ********************************/
3830 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
3831 
3832 /****************************** RTC Instances *********************************/
3833 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
3834 
3835 /******************************** SPI Instances *******************************/
3836 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
3837  ((INSTANCE) == SPI2) || \
3838  ((INSTANCE) == SPI5))
3839 /*************************** SPI Extended Instances ***************************/
3840 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
3841  ((INSTANCE) == SPI2) || \
3842  ((INSTANCE) == SPI5))
3843 
3844 /****************** TIM Instances : All supported instances *******************/
3845 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3846  ((INSTANCE) == TIM5) || \
3847  ((INSTANCE) == TIM6) || \
3848  ((INSTANCE) == TIM9) || \
3849  ((INSTANCE) == TIM11))
3850 
3851 /************* TIM Instances : at least 1 capture/compare channel *************/
3852 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3853  ((INSTANCE) == TIM5) || \
3854  ((INSTANCE) == TIM9) || \
3855  ((INSTANCE) == TIM11))
3856 
3857 /************ TIM Instances : at least 2 capture/compare channels *************/
3858 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3859  ((INSTANCE) == TIM5) || \
3860  ((INSTANCE) == TIM9))
3861 
3862 /************ TIM Instances : at least 3 capture/compare channels *************/
3863 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3864  ((INSTANCE) == TIM5))
3865 
3866 /************ TIM Instances : at least 4 capture/compare channels *************/
3867 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3868  ((INSTANCE) == TIM5))
3869 
3870 /******************** TIM Instances : Advanced-control timers *****************/
3871 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
3872 
3873 /******************* TIM Instances : Timer input XOR function *****************/
3874 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3875  ((INSTANCE) == TIM5))
3876 
3877 /****************** TIM Instances : DMA requests generation (UDE) *************/
3878 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3879  ((INSTANCE) == TIM5) || \
3880  ((INSTANCE) == TIM6))
3881 
3882 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
3883 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3884  ((INSTANCE) == TIM5))
3885 
3886 /************ TIM Instances : DMA requests generation (COMDE) *****************/
3887 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3888  ((INSTANCE) == TIM5))
3889 
3890 /******************** TIM Instances : DMA burst feature ***********************/
3891 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3892  ((INSTANCE) == TIM5))
3893 
3894 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
3895 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3896  ((INSTANCE) == TIM5) || \
3897  ((INSTANCE) == TIM6) || \
3898  ((INSTANCE) == TIM9))
3899 
3900 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
3901 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3902  ((INSTANCE) == TIM5) || \
3903  ((INSTANCE) == TIM9))
3904 
3905 /********************** TIM Instances : 32 bit Counter ************************/
3906 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
3907 
3908 /***************** TIM Instances : external trigger input availabe ************/
3909 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3910  ((INSTANCE) == TIM5))
3911 
3912 /****************** TIM Instances : remapping capability **********************/
3913 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
3914  ((INSTANCE) == TIM11))
3915 
3916 /******************* TIM Instances : output(s) available **********************/
3917 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
3918  ((((INSTANCE) == TIM1) && \
3919  (((CHANNEL) == TIM_CHANNEL_1) || \
3920  ((CHANNEL) == TIM_CHANNEL_2) || \
3921  ((CHANNEL) == TIM_CHANNEL_3) || \
3922  ((CHANNEL) == TIM_CHANNEL_4))) \
3923  || \
3924  (((INSTANCE) == TIM5) && \
3925  (((CHANNEL) == TIM_CHANNEL_1) || \
3926  ((CHANNEL) == TIM_CHANNEL_2) || \
3927  ((CHANNEL) == TIM_CHANNEL_3) || \
3928  ((CHANNEL) == TIM_CHANNEL_4))) \
3929  || \
3930  (((INSTANCE) == TIM9) && \
3931  (((CHANNEL) == TIM_CHANNEL_1) || \
3932  ((CHANNEL) == TIM_CHANNEL_2))) \
3933  || \
3934  (((INSTANCE) == TIM11) && \
3935  (((CHANNEL) == TIM_CHANNEL_1))))
3936 
3937 /************ TIM Instances : complementary output(s) available ***************/
3938 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
3939  ((((INSTANCE) == TIM1) && \
3940  (((CHANNEL) == TIM_CHANNEL_1) || \
3941  ((CHANNEL) == TIM_CHANNEL_2) || \
3942  ((CHANNEL) == TIM_CHANNEL_3))))
3943 
3944 /******************** USART Instances : Synchronous mode **********************/
3945 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3946  ((INSTANCE) == USART2) || \
3947  ((INSTANCE) == USART6))
3948 
3949 /******************** UART Instances : Asynchronous mode **********************/
3950 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3951  ((INSTANCE) == USART2) || \
3952  ((INSTANCE) == USART6))
3953 
3954 /****************** UART Instances : Hardware Flow control ********************/
3955 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3956  ((INSTANCE) == USART2))
3957 
3958 /********************* UART Instances : Smard card mode ***********************/
3959 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3960  ((INSTANCE) == USART2) || \
3961  ((INSTANCE) == USART6))
3962 
3963 /*********************** UART Instances : IRDA mode ***************************/
3964 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3965  ((INSTANCE) == USART2) || \
3966  ((INSTANCE) == USART6))
3967 
3968 /****************************** IWDG Instances ********************************/
3969 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
3970 
3971 /****************************** WWDG Instances ********************************/
3972 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
3973 
3974 /***************************** FMPI2C Instances *******************************/
3975 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
3976 
3989 #ifdef __cplusplus
3990 }
3991 #endif /* __cplusplus */
3992 
3993 #endif /* __STM32F410Cx_H */
3994 
3995 
3996 
3997 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
TAMP_STAMP_IRQn
Definition: stm32f410cx.h:99
FMPI2C_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f410cx.h:363
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f410cx.h:119
EXTI2_IRQn
Definition: stm32f410cx.h:105
EXTI4_IRQn
Definition: stm32f410cx.h:107
USART1_IRQn
Definition: stm32f410cx.h:127
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
FMPI2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f410cx.h:358
RTC_Alarm_IRQn
Definition: stm32f410cx.h:130
PendSV_IRQn
Definition: stm32f410cx.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f410cx.h:100
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition: stm32f410cx.h:570
TIM6_DAC_IRQn
Definition: stm32f410cx.h:133
FMPI2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32f410cx.h:360
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f410cx.h:566
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition: stm32f410cx.h:569
SPI1_IRQn
Definition: stm32f410cx.h:125
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
DMA_TypeDef
Definition: stm32f401xc.h:243
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f410cx.h:565
DMA1_Stream2_IRQn
Definition: stm32f410cx.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f410cx.h:126
FMPI2C1_ER_IRQn
Definition: stm32f410cx.h:147
FMPI2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f410cx.h:359
RNG_IRQn
Definition: stm32f410cx.h:143
SYSCFG_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f410cx.h:329
DMA2_Stream5_IRQn
Definition: stm32f410cx.h:139
ADC_IRQn
Definition: stm32f410cx.h:115
FMPI2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f410cx.h:366
FMPI2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f410cx.h:362
RCC_IRQn
Definition: stm32f410cx.h:102
TIM1_UP_IRQn
Definition: stm32f410cx.h:118
DebugMonitor_IRQn
Definition: stm32f410cx.h:93
DMA2_Stream3_IRQn
Definition: stm32f410cx.h:137
RCC_TypeDef::DCKCFGR2
__IO uint32_t DCKCFGR2
Definition: stm32f410cx.h:423
NonMaskableInt_IRQn
Definition: stm32f410cx.h:88
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f410cx.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
DMA1_Stream1_IRQn
Definition: stm32f410cx.h:109
DMA2_Stream7_IRQn
Definition: stm32f410cx.h:141
DMA2_Stream6_IRQn
Definition: stm32f410cx.h:140
BusFault_IRQn
Definition: stm32f410cx.h:90
RCC_TypeDef::CKGATENR
__IO uint32_t CKGATENR
Definition: stm32f410cx.h:422
LPTIM_TypeDef
LPTIMER.
Definition: stm32f410cx.h:563
FMPI2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition: stm32f410cx.h:361
USART6_IRQn
Definition: stm32f410cx.h:142
PVD_IRQn
Definition: stm32f410cx.h:98
LPTIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f410cx.h:573
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f410cx.h:112
FMPI2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f410cx.h:365
DMA1_Stream0_IRQn
Definition: stm32f410cx.h:108
FMPI2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f410cx.h:357
DMA1_Stream3_IRQn
Definition: stm32f410cx.h:111
FPU_IRQn
Definition: stm32f410cx.h:144
DMA2_Stream2_IRQn
Definition: stm32f410cx.h:136
SYSCFG_TypeDef::CFGR2
uint32_t CFGR2
Definition: stm32f410cx.h:326
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
FMPI2C1_EV_IRQn
Definition: stm32f410cx.h:146
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f410cx.h:128
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
I2C2_EV_IRQn
Definition: stm32f410cx.h:123
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f410cx.h:104
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f410cx.h:92
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f410cx.h:120
FLASH_IRQn
Definition: stm32f410cx.h:101
DMA1_Stream5_IRQn
Definition: stm32f410cx.h:113
SysTick_IRQn
Definition: stm32f410cx.h:95
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f410cx.h:124
UsageFault_IRQn
Definition: stm32f410cx.h:91
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f410cx.h:572
DMA2_Stream1_IRQn
Definition: stm32f410cx.h:135
EXTI9_5_IRQn
Definition: stm32f410cx.h:116
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f410cx.h:121
DMA1_Stream6_IRQn
Definition: stm32f410cx.h:114
FMPI2C_TypeDef::PECR
__IO uint32_t PECR
Definition: stm32f410cx.h:364
I2C1_ER_IRQn
Definition: stm32f410cx.h:122
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
FMPI2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f410cx.h:354
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f410cx.h:571
DMA2_Stream4_IRQn
Definition: stm32f410cx.h:138
WWDG_IRQn
Definition: stm32f410cx.h:97
LPTIM1_IRQn
Definition: stm32f410cx.h:148
DMA1_Stream7_IRQn
Definition: stm32f410cx.h:131
SPI5_IRQn
Definition: stm32f410cx.h:145
EXTI15_10_IRQn
Definition: stm32f410cx.h:129
EXTI0_IRQn
Definition: stm32f410cx.h:103
DMA2_Stream0_IRQn
Definition: stm32f410cx.h:134
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f410cx.h:568
TIM1_BRK_TIM9_IRQn
Definition: stm32f410cx.h:117
TIM5_IRQn
Definition: stm32f410cx.h:132
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition: stm32f410cx.h:567
EXTI3_IRQn
Definition: stm32f410cx.h:106
MemoryManagement_IRQn
Definition: stm32f410cx.h:89
FMPI2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f410cx.h:356