STM CMSIS
stm32f410tx.h
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1 
52 #ifndef __STM32F410Tx_H
53 #define __STM32F410Tx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  EXTI9_5_IRQn = 23,
117  TIM1_BRK_TIM9_IRQn = 24,
118  TIM1_UP_IRQn = 25,
119  TIM1_TRG_COM_TIM11_IRQn = 26,
120  TIM1_CC_IRQn = 27,
121  I2C1_EV_IRQn = 31,
122  I2C1_ER_IRQn = 32,
123  I2C2_EV_IRQn = 33,
124  I2C2_ER_IRQn = 34,
125  SPI1_IRQn = 35,
126  USART1_IRQn = 37,
127  USART2_IRQn = 38,
128  EXTI15_10_IRQn = 40,
129  RTC_Alarm_IRQn = 41,
130  DMA1_Stream7_IRQn = 47,
131  TIM5_IRQn = 50,
132  TIM6_DAC_IRQn = 54,
133  DMA2_Stream0_IRQn = 56,
134  DMA2_Stream1_IRQn = 57,
135  DMA2_Stream2_IRQn = 58,
136  DMA2_Stream3_IRQn = 59,
137  DMA2_Stream4_IRQn = 60,
138  DMA2_Stream5_IRQn = 68,
139  DMA2_Stream6_IRQn = 69,
140  DMA2_Stream7_IRQn = 70,
141  RNG_IRQn = 80,
142  FPU_IRQn = 81,
143  FMPI2C1_EV_IRQn = 95,
144  FMPI2C1_ER_IRQn = 96,
145  LPTIM1_IRQn = 97
146 } IRQn_Type;
147 
152 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
153 #include "system_stm32f4xx.h"
154 #include <stdint.h>
155 
164 typedef struct
165 {
166  __IO uint32_t SR;
167  __IO uint32_t CR1;
168  __IO uint32_t CR2;
169  __IO uint32_t SMPR1;
170  __IO uint32_t SMPR2;
171  __IO uint32_t JOFR1;
172  __IO uint32_t JOFR2;
173  __IO uint32_t JOFR3;
174  __IO uint32_t JOFR4;
175  __IO uint32_t HTR;
176  __IO uint32_t LTR;
177  __IO uint32_t SQR1;
178  __IO uint32_t SQR2;
179  __IO uint32_t SQR3;
180  __IO uint32_t JSQR;
181  __IO uint32_t JDR1;
182  __IO uint32_t JDR2;
183  __IO uint32_t JDR3;
184  __IO uint32_t JDR4;
185  __IO uint32_t DR;
186 } ADC_TypeDef;
187 
188 typedef struct
189 {
190  __IO uint32_t CSR;
191  __IO uint32_t CCR;
192  __IO uint32_t CDR;
194 } ADC_Common_TypeDef;
195 
200 typedef struct
201 {
202  __IO uint32_t DR;
203  __IO uint8_t IDR;
204  uint8_t RESERVED0;
205  uint16_t RESERVED1;
206  __IO uint32_t CR;
207 } CRC_TypeDef;
208 
213 typedef struct
214 {
215  __IO uint32_t CR;
216  __IO uint32_t SWTRIGR;
217  __IO uint32_t DHR12R1;
218  __IO uint32_t DHR12L1;
219  __IO uint32_t DHR8R1;
220  __IO uint32_t DHR12R2;
221  __IO uint32_t DHR12L2;
222  __IO uint32_t DHR8R2;
223  __IO uint32_t DHR12RD;
224  __IO uint32_t DHR12LD;
225  __IO uint32_t DHR8RD;
226  __IO uint32_t DOR1;
227  __IO uint32_t DOR2;
228  __IO uint32_t SR;
229 } DAC_TypeDef;
230 
235 typedef struct
236 {
237  __IO uint32_t IDCODE;
238  __IO uint32_t CR;
239  __IO uint32_t APB1FZ;
240  __IO uint32_t APB2FZ;
241 }DBGMCU_TypeDef;
242 
243 
248 typedef struct
249 {
250  __IO uint32_t CR;
251  __IO uint32_t NDTR;
252  __IO uint32_t PAR;
253  __IO uint32_t M0AR;
254  __IO uint32_t M1AR;
255  __IO uint32_t FCR;
256 } DMA_Stream_TypeDef;
257 
258 typedef struct
259 {
260  __IO uint32_t LISR;
261  __IO uint32_t HISR;
262  __IO uint32_t LIFCR;
263  __IO uint32_t HIFCR;
264 } DMA_TypeDef;
265 
266 
271 typedef struct
272 {
273  __IO uint32_t IMR;
274  __IO uint32_t EMR;
275  __IO uint32_t RTSR;
276  __IO uint32_t FTSR;
277  __IO uint32_t SWIER;
278  __IO uint32_t PR;
279 } EXTI_TypeDef;
280 
285 typedef struct
286 {
287  __IO uint32_t ACR;
288  __IO uint32_t KEYR;
289  __IO uint32_t OPTKEYR;
290  __IO uint32_t SR;
291  __IO uint32_t CR;
292  __IO uint32_t OPTCR;
293  __IO uint32_t OPTCR1;
294 } FLASH_TypeDef;
295 
300 typedef struct
301 {
302  __IO uint32_t MODER;
303  __IO uint32_t OTYPER;
304  __IO uint32_t OSPEEDR;
305  __IO uint32_t PUPDR;
306  __IO uint32_t IDR;
307  __IO uint32_t ODR;
308  __IO uint32_t BSRR;
309  __IO uint32_t LCKR;
310  __IO uint32_t AFR[2];
311 } GPIO_TypeDef;
312 
317 typedef struct
318 {
319  __IO uint32_t MEMRMP;
320  __IO uint32_t PMC;
321  __IO uint32_t EXTICR[4];
322  uint32_t RESERVED;
323  uint32_t CFGR2;
324  __IO uint32_t CMPCR;
325  uint32_t RESERVED1[2];
326  __IO uint32_t CFGR;
327 } SYSCFG_TypeDef;
328 
333 typedef struct
334 {
335  __IO uint32_t CR1;
336  __IO uint32_t CR2;
337  __IO uint32_t OAR1;
338  __IO uint32_t OAR2;
339  __IO uint32_t DR;
340  __IO uint32_t SR1;
341  __IO uint32_t SR2;
342  __IO uint32_t CCR;
343  __IO uint32_t TRISE;
344  __IO uint32_t FLTR;
345 } I2C_TypeDef;
346 
351 typedef struct
352 {
353  __IO uint32_t CR1;
354  __IO uint32_t CR2;
355  __IO uint32_t OAR1;
356  __IO uint32_t OAR2;
357  __IO uint32_t TIMINGR;
358  __IO uint32_t TIMEOUTR;
359  __IO uint32_t ISR;
360  __IO uint32_t ICR;
361  __IO uint32_t PECR;
362  __IO uint32_t RXDR;
363  __IO uint32_t TXDR;
364 } FMPI2C_TypeDef;
365 
370 typedef struct
371 {
372  __IO uint32_t KR;
373  __IO uint32_t PR;
374  __IO uint32_t RLR;
375  __IO uint32_t SR;
376 } IWDG_TypeDef;
377 
382 typedef struct
383 {
384  __IO uint32_t CR;
385  __IO uint32_t CSR;
386 } PWR_TypeDef;
387 
392 typedef struct
393 {
394  __IO uint32_t CR;
395  __IO uint32_t PLLCFGR;
396  __IO uint32_t CFGR;
397  __IO uint32_t CIR;
398  __IO uint32_t AHB1RSTR;
399  uint32_t RESERVED0[3];
400  __IO uint32_t APB1RSTR;
401  __IO uint32_t APB2RSTR;
402  uint32_t RESERVED1[2];
403  __IO uint32_t AHB1ENR;
404  uint32_t RESERVED2[3];
405  __IO uint32_t APB1ENR;
406  __IO uint32_t APB2ENR;
407  uint32_t RESERVED3[2];
408  __IO uint32_t AHB1LPENR;
409  uint32_t RESERVED4[3];
410  __IO uint32_t APB1LPENR;
411  __IO uint32_t APB2LPENR;
412  uint32_t RESERVED5[2];
413  __IO uint32_t BDCR;
414  __IO uint32_t CSR;
415  uint32_t RESERVED6[2];
416  __IO uint32_t SSCGR;
417  uint32_t RESERVED7[2];
418  __IO uint32_t DCKCFGR;
419  __IO uint32_t CKGATENR;
420  __IO uint32_t DCKCFGR2;
422 } RCC_TypeDef;
423 
428 typedef struct
429 {
430  __IO uint32_t TR;
431  __IO uint32_t DR;
432  __IO uint32_t CR;
433  __IO uint32_t ISR;
434  __IO uint32_t PRER;
435  __IO uint32_t WUTR;
436  __IO uint32_t CALIBR;
437  __IO uint32_t ALRMAR;
438  __IO uint32_t ALRMBR;
439  __IO uint32_t WPR;
440  __IO uint32_t SSR;
441  __IO uint32_t SHIFTR;
442  __IO uint32_t TSTR;
443  __IO uint32_t TSDR;
444  __IO uint32_t TSSSR;
445  __IO uint32_t CALR;
446  __IO uint32_t TAFCR;
447  __IO uint32_t ALRMASSR;
448  __IO uint32_t ALRMBSSR;
449  uint32_t RESERVED7;
450  __IO uint32_t BKP0R;
451  __IO uint32_t BKP1R;
452  __IO uint32_t BKP2R;
453  __IO uint32_t BKP3R;
454  __IO uint32_t BKP4R;
455  __IO uint32_t BKP5R;
456  __IO uint32_t BKP6R;
457  __IO uint32_t BKP7R;
458  __IO uint32_t BKP8R;
459  __IO uint32_t BKP9R;
460  __IO uint32_t BKP10R;
461  __IO uint32_t BKP11R;
462  __IO uint32_t BKP12R;
463  __IO uint32_t BKP13R;
464  __IO uint32_t BKP14R;
465  __IO uint32_t BKP15R;
466  __IO uint32_t BKP16R;
467  __IO uint32_t BKP17R;
468  __IO uint32_t BKP18R;
469  __IO uint32_t BKP19R;
470 } RTC_TypeDef;
471 
476 typedef struct
477 {
478  __IO uint32_t CR1;
479  __IO uint32_t CR2;
480  __IO uint32_t SR;
481  __IO uint32_t DR;
482  __IO uint32_t CRCPR;
483  __IO uint32_t RXCRCR;
484  __IO uint32_t TXCRCR;
485  __IO uint32_t I2SCFGR;
486  __IO uint32_t I2SPR;
487 } SPI_TypeDef;
488 
493 typedef struct
494 {
495  __IO uint32_t CR1;
496  __IO uint32_t CR2;
497  __IO uint32_t SMCR;
498  __IO uint32_t DIER;
499  __IO uint32_t SR;
500  __IO uint32_t EGR;
501  __IO uint32_t CCMR1;
502  __IO uint32_t CCMR2;
503  __IO uint32_t CCER;
504  __IO uint32_t CNT;
505  __IO uint32_t PSC;
506  __IO uint32_t ARR;
507  __IO uint32_t RCR;
508  __IO uint32_t CCR1;
509  __IO uint32_t CCR2;
510  __IO uint32_t CCR3;
511  __IO uint32_t CCR4;
512  __IO uint32_t BDTR;
513  __IO uint32_t DCR;
514  __IO uint32_t DMAR;
515  __IO uint32_t OR;
516 } TIM_TypeDef;
517 
522 typedef struct
523 {
524  __IO uint32_t SR;
525  __IO uint32_t DR;
526  __IO uint32_t BRR;
527  __IO uint32_t CR1;
528  __IO uint32_t CR2;
529  __IO uint32_t CR3;
530  __IO uint32_t GTPR;
531 } USART_TypeDef;
532 
537 typedef struct
538 {
539  __IO uint32_t CR;
540  __IO uint32_t CFR;
541  __IO uint32_t SR;
542 } WWDG_TypeDef;
543 
544 
549 typedef struct
550 {
551  __IO uint32_t CR;
552  __IO uint32_t SR;
553  __IO uint32_t DR;
554 } RNG_TypeDef;
555 
556 
560 typedef struct
561 {
562  __IO uint32_t ISR;
563  __IO uint32_t ICR;
564  __IO uint32_t IER;
565  __IO uint32_t CFGR;
566  __IO uint32_t CR;
567  __IO uint32_t CMP;
568  __IO uint32_t ARR;
569  __IO uint32_t CNT;
570  __IO uint32_t OR;
571 } LPTIM_TypeDef;
572 
576 #define FLASH_BASE 0x08000000U
577 #define SRAM1_BASE 0x20000000U
578 #define PERIPH_BASE 0x40000000U
579 #define SRAM1_BB_BASE 0x22000000U
580 #define PERIPH_BB_BASE 0x42000000U
581 #define FLASH_END 0x0801FFFFU
583 /* Legacy defines */
584 #define SRAM_BASE SRAM1_BASE
585 #define SRAM_BB_BASE SRAM1_BB_BASE
586 
588 #define APB1PERIPH_BASE PERIPH_BASE
589 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
590 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
591 
593 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
594 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
595 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
596 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
597 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
598 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
599 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
600 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
601 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
602 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
603 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
604 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
605 
606 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
607 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
608 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
609 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
610 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
611 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
612 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
613 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
614 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
615 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
616 
618 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
619 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
620 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
621 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
622 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
623 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
624 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
625 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
626 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
627 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
628 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
629 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
630 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
631 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
632 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
633 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
634 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
635 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
636 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
637 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
638 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
639 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
640 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
641 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
642 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
643 #define RNG_BASE (PERIPH_BASE + 0x80000U)
644 
645 /* Debug MCU registers base address */
646 #define DBGMCU_BASE 0xE0042000U
647 
655 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
656 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
657 #define RTC ((RTC_TypeDef *) RTC_BASE)
658 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
659 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
660 #define USART2 ((USART_TypeDef *) USART2_BASE)
661 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
662 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
663 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
664 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
665 #define PWR ((PWR_TypeDef *) PWR_BASE)
666 #define DAC ((DAC_TypeDef *) DAC_BASE)
667 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
668 #define USART1 ((USART_TypeDef *) USART1_BASE)
669 #define USART6 ((USART_TypeDef *) USART6_BASE)
670 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
671 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
672 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
673 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
674 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
675 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
676 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
677 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
678 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
679 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
680 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
681 #define CRC ((CRC_TypeDef *) CRC_BASE)
682 #define RCC ((RCC_TypeDef *) RCC_BASE)
683 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
684 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
685 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
686 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
687 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
688 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
689 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
690 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
691 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
692 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
693 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
694 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
695 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
696 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
697 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
698 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
699 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
700 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
701 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
702 #define RNG ((RNG_TypeDef *) RNG_BASE)
703 
704 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
705 
718 /******************************************************************************/
719 /* Peripheral Registers_Bits_Definition */
720 /******************************************************************************/
721 
722 /******************************************************************************/
723 /* */
724 /* Analog to Digital Converter */
725 /* */
726 /******************************************************************************/
727 /******************** Bit definition for ADC_SR register ********************/
728 #define ADC_SR_AWD 0x00000001U
729 #define ADC_SR_EOC 0x00000002U
730 #define ADC_SR_JEOC 0x00000004U
731 #define ADC_SR_JSTRT 0x00000008U
732 #define ADC_SR_STRT 0x00000010U
733 #define ADC_SR_OVR 0x00000020U
735 /******************* Bit definition for ADC_CR1 register ********************/
736 #define ADC_CR1_AWDCH 0x0000001FU
737 #define ADC_CR1_AWDCH_0 0x00000001U
738 #define ADC_CR1_AWDCH_1 0x00000002U
739 #define ADC_CR1_AWDCH_2 0x00000004U
740 #define ADC_CR1_AWDCH_3 0x00000008U
741 #define ADC_CR1_AWDCH_4 0x00000010U
742 #define ADC_CR1_EOCIE 0x00000020U
743 #define ADC_CR1_AWDIE 0x00000040U
744 #define ADC_CR1_JEOCIE 0x00000080U
745 #define ADC_CR1_SCAN 0x00000100U
746 #define ADC_CR1_AWDSGL 0x00000200U
747 #define ADC_CR1_JAUTO 0x00000400U
748 #define ADC_CR1_DISCEN 0x00000800U
749 #define ADC_CR1_JDISCEN 0x00001000U
750 #define ADC_CR1_DISCNUM 0x0000E000U
751 #define ADC_CR1_DISCNUM_0 0x00002000U
752 #define ADC_CR1_DISCNUM_1 0x00004000U
753 #define ADC_CR1_DISCNUM_2 0x00008000U
754 #define ADC_CR1_JAWDEN 0x00400000U
755 #define ADC_CR1_AWDEN 0x00800000U
756 #define ADC_CR1_RES 0x03000000U
757 #define ADC_CR1_RES_0 0x01000000U
758 #define ADC_CR1_RES_1 0x02000000U
759 #define ADC_CR1_OVRIE 0x04000000U
761 /******************* Bit definition for ADC_CR2 register ********************/
762 #define ADC_CR2_ADON 0x00000001U
763 #define ADC_CR2_CONT 0x00000002U
764 #define ADC_CR2_DMA 0x00000100U
765 #define ADC_CR2_DDS 0x00000200U
766 #define ADC_CR2_EOCS 0x00000400U
767 #define ADC_CR2_ALIGN 0x00000800U
768 #define ADC_CR2_JEXTSEL 0x000F0000U
769 #define ADC_CR2_JEXTSEL_0 0x00010000U
770 #define ADC_CR2_JEXTSEL_1 0x00020000U
771 #define ADC_CR2_JEXTSEL_2 0x00040000U
772 #define ADC_CR2_JEXTSEL_3 0x00080000U
773 #define ADC_CR2_JEXTEN 0x00300000U
774 #define ADC_CR2_JEXTEN_0 0x00100000U
775 #define ADC_CR2_JEXTEN_1 0x00200000U
776 #define ADC_CR2_JSWSTART 0x00400000U
777 #define ADC_CR2_EXTSEL 0x0F000000U
778 #define ADC_CR2_EXTSEL_0 0x01000000U
779 #define ADC_CR2_EXTSEL_1 0x02000000U
780 #define ADC_CR2_EXTSEL_2 0x04000000U
781 #define ADC_CR2_EXTSEL_3 0x08000000U
782 #define ADC_CR2_EXTEN 0x30000000U
783 #define ADC_CR2_EXTEN_0 0x10000000U
784 #define ADC_CR2_EXTEN_1 0x20000000U
785 #define ADC_CR2_SWSTART 0x40000000U
787 /****************** Bit definition for ADC_SMPR1 register *******************/
788 #define ADC_SMPR1_SMP10 0x00000007U
789 #define ADC_SMPR1_SMP10_0 0x00000001U
790 #define ADC_SMPR1_SMP10_1 0x00000002U
791 #define ADC_SMPR1_SMP10_2 0x00000004U
792 #define ADC_SMPR1_SMP11 0x00000038U
793 #define ADC_SMPR1_SMP11_0 0x00000008U
794 #define ADC_SMPR1_SMP11_1 0x00000010U
795 #define ADC_SMPR1_SMP11_2 0x00000020U
796 #define ADC_SMPR1_SMP12 0x000001C0U
797 #define ADC_SMPR1_SMP12_0 0x00000040U
798 #define ADC_SMPR1_SMP12_1 0x00000080U
799 #define ADC_SMPR1_SMP12_2 0x00000100U
800 #define ADC_SMPR1_SMP13 0x00000E00U
801 #define ADC_SMPR1_SMP13_0 0x00000200U
802 #define ADC_SMPR1_SMP13_1 0x00000400U
803 #define ADC_SMPR1_SMP13_2 0x00000800U
804 #define ADC_SMPR1_SMP14 0x00007000U
805 #define ADC_SMPR1_SMP14_0 0x00001000U
806 #define ADC_SMPR1_SMP14_1 0x00002000U
807 #define ADC_SMPR1_SMP14_2 0x00004000U
808 #define ADC_SMPR1_SMP15 0x00038000U
809 #define ADC_SMPR1_SMP15_0 0x00008000U
810 #define ADC_SMPR1_SMP15_1 0x00010000U
811 #define ADC_SMPR1_SMP15_2 0x00020000U
812 #define ADC_SMPR1_SMP16 0x001C0000U
813 #define ADC_SMPR1_SMP16_0 0x00040000U
814 #define ADC_SMPR1_SMP16_1 0x00080000U
815 #define ADC_SMPR1_SMP16_2 0x00100000U
816 #define ADC_SMPR1_SMP17 0x00E00000U
817 #define ADC_SMPR1_SMP17_0 0x00200000U
818 #define ADC_SMPR1_SMP17_1 0x00400000U
819 #define ADC_SMPR1_SMP17_2 0x00800000U
820 #define ADC_SMPR1_SMP18 0x07000000U
821 #define ADC_SMPR1_SMP18_0 0x01000000U
822 #define ADC_SMPR1_SMP18_1 0x02000000U
823 #define ADC_SMPR1_SMP18_2 0x04000000U
825 /****************** Bit definition for ADC_SMPR2 register *******************/
826 #define ADC_SMPR2_SMP0 0x00000007U
827 #define ADC_SMPR2_SMP0_0 0x00000001U
828 #define ADC_SMPR2_SMP0_1 0x00000002U
829 #define ADC_SMPR2_SMP0_2 0x00000004U
830 #define ADC_SMPR2_SMP1 0x00000038U
831 #define ADC_SMPR2_SMP1_0 0x00000008U
832 #define ADC_SMPR2_SMP1_1 0x00000010U
833 #define ADC_SMPR2_SMP1_2 0x00000020U
834 #define ADC_SMPR2_SMP2 0x000001C0U
835 #define ADC_SMPR2_SMP2_0 0x00000040U
836 #define ADC_SMPR2_SMP2_1 0x00000080U
837 #define ADC_SMPR2_SMP2_2 0x00000100U
838 #define ADC_SMPR2_SMP3 0x00000E00U
839 #define ADC_SMPR2_SMP3_0 0x00000200U
840 #define ADC_SMPR2_SMP3_1 0x00000400U
841 #define ADC_SMPR2_SMP3_2 0x00000800U
842 #define ADC_SMPR2_SMP4 0x00007000U
843 #define ADC_SMPR2_SMP4_0 0x00001000U
844 #define ADC_SMPR2_SMP4_1 0x00002000U
845 #define ADC_SMPR2_SMP4_2 0x00004000U
846 #define ADC_SMPR2_SMP5 0x00038000U
847 #define ADC_SMPR2_SMP5_0 0x00008000U
848 #define ADC_SMPR2_SMP5_1 0x00010000U
849 #define ADC_SMPR2_SMP5_2 0x00020000U
850 #define ADC_SMPR2_SMP6 0x001C0000U
851 #define ADC_SMPR2_SMP6_0 0x00040000U
852 #define ADC_SMPR2_SMP6_1 0x00080000U
853 #define ADC_SMPR2_SMP6_2 0x00100000U
854 #define ADC_SMPR2_SMP7 0x00E00000U
855 #define ADC_SMPR2_SMP7_0 0x00200000U
856 #define ADC_SMPR2_SMP7_1 0x00400000U
857 #define ADC_SMPR2_SMP7_2 0x00800000U
858 #define ADC_SMPR2_SMP8 0x07000000U
859 #define ADC_SMPR2_SMP8_0 0x01000000U
860 #define ADC_SMPR2_SMP8_1 0x02000000U
861 #define ADC_SMPR2_SMP8_2 0x04000000U
862 #define ADC_SMPR2_SMP9 0x38000000U
863 #define ADC_SMPR2_SMP9_0 0x08000000U
864 #define ADC_SMPR2_SMP9_1 0x10000000U
865 #define ADC_SMPR2_SMP9_2 0x20000000U
867 /****************** Bit definition for ADC_JOFR1 register *******************/
868 #define ADC_JOFR1_JOFFSET1 0x0FFFU
870 /****************** Bit definition for ADC_JOFR2 register *******************/
871 #define ADC_JOFR2_JOFFSET2 0x0FFFU
873 /****************** Bit definition for ADC_JOFR3 register *******************/
874 #define ADC_JOFR3_JOFFSET3 0x0FFFU
876 /****************** Bit definition for ADC_JOFR4 register *******************/
877 #define ADC_JOFR4_JOFFSET4 0x0FFFU
879 /******************* Bit definition for ADC_HTR register ********************/
880 #define ADC_HTR_HT 0x0FFFU
882 /******************* Bit definition for ADC_LTR register ********************/
883 #define ADC_LTR_LT 0x0FFFU
885 /******************* Bit definition for ADC_SQR1 register *******************/
886 #define ADC_SQR1_SQ13 0x0000001FU
887 #define ADC_SQR1_SQ13_0 0x00000001U
888 #define ADC_SQR1_SQ13_1 0x00000002U
889 #define ADC_SQR1_SQ13_2 0x00000004U
890 #define ADC_SQR1_SQ13_3 0x00000008U
891 #define ADC_SQR1_SQ13_4 0x00000010U
892 #define ADC_SQR1_SQ14 0x000003E0U
893 #define ADC_SQR1_SQ14_0 0x00000020U
894 #define ADC_SQR1_SQ14_1 0x00000040U
895 #define ADC_SQR1_SQ14_2 0x00000080U
896 #define ADC_SQR1_SQ14_3 0x00000100U
897 #define ADC_SQR1_SQ14_4 0x00000200U
898 #define ADC_SQR1_SQ15 0x00007C00U
899 #define ADC_SQR1_SQ15_0 0x00000400U
900 #define ADC_SQR1_SQ15_1 0x00000800U
901 #define ADC_SQR1_SQ15_2 0x00001000U
902 #define ADC_SQR1_SQ15_3 0x00002000U
903 #define ADC_SQR1_SQ15_4 0x00004000U
904 #define ADC_SQR1_SQ16 0x000F8000U
905 #define ADC_SQR1_SQ16_0 0x00008000U
906 #define ADC_SQR1_SQ16_1 0x00010000U
907 #define ADC_SQR1_SQ16_2 0x00020000U
908 #define ADC_SQR1_SQ16_3 0x00040000U
909 #define ADC_SQR1_SQ16_4 0x00080000U
910 #define ADC_SQR1_L 0x00F00000U
911 #define ADC_SQR1_L_0 0x00100000U
912 #define ADC_SQR1_L_1 0x00200000U
913 #define ADC_SQR1_L_2 0x00400000U
914 #define ADC_SQR1_L_3 0x00800000U
916 /******************* Bit definition for ADC_SQR2 register *******************/
917 #define ADC_SQR2_SQ7 0x0000001FU
918 #define ADC_SQR2_SQ7_0 0x00000001U
919 #define ADC_SQR2_SQ7_1 0x00000002U
920 #define ADC_SQR2_SQ7_2 0x00000004U
921 #define ADC_SQR2_SQ7_3 0x00000008U
922 #define ADC_SQR2_SQ7_4 0x00000010U
923 #define ADC_SQR2_SQ8 0x000003E0U
924 #define ADC_SQR2_SQ8_0 0x00000020U
925 #define ADC_SQR2_SQ8_1 0x00000040U
926 #define ADC_SQR2_SQ8_2 0x00000080U
927 #define ADC_SQR2_SQ8_3 0x00000100U
928 #define ADC_SQR2_SQ8_4 0x00000200U
929 #define ADC_SQR2_SQ9 0x00007C00U
930 #define ADC_SQR2_SQ9_0 0x00000400U
931 #define ADC_SQR2_SQ9_1 0x00000800U
932 #define ADC_SQR2_SQ9_2 0x00001000U
933 #define ADC_SQR2_SQ9_3 0x00002000U
934 #define ADC_SQR2_SQ9_4 0x00004000U
935 #define ADC_SQR2_SQ10 0x000F8000U
936 #define ADC_SQR2_SQ10_0 0x00008000U
937 #define ADC_SQR2_SQ10_1 0x00010000U
938 #define ADC_SQR2_SQ10_2 0x00020000U
939 #define ADC_SQR2_SQ10_3 0x00040000U
940 #define ADC_SQR2_SQ10_4 0x00080000U
941 #define ADC_SQR2_SQ11 0x01F00000U
942 #define ADC_SQR2_SQ11_0 0x00100000U
943 #define ADC_SQR2_SQ11_1 0x00200000U
944 #define ADC_SQR2_SQ11_2 0x00400000U
945 #define ADC_SQR2_SQ11_3 0x00800000U
946 #define ADC_SQR2_SQ11_4 0x01000000U
947 #define ADC_SQR2_SQ12 0x3E000000U
948 #define ADC_SQR2_SQ12_0 0x02000000U
949 #define ADC_SQR2_SQ12_1 0x04000000U
950 #define ADC_SQR2_SQ12_2 0x08000000U
951 #define ADC_SQR2_SQ12_3 0x10000000U
952 #define ADC_SQR2_SQ12_4 0x20000000U
954 /******************* Bit definition for ADC_SQR3 register *******************/
955 #define ADC_SQR3_SQ1 0x0000001FU
956 #define ADC_SQR3_SQ1_0 0x00000001U
957 #define ADC_SQR3_SQ1_1 0x00000002U
958 #define ADC_SQR3_SQ1_2 0x00000004U
959 #define ADC_SQR3_SQ1_3 0x00000008U
960 #define ADC_SQR3_SQ1_4 0x00000010U
961 #define ADC_SQR3_SQ2 0x000003E0U
962 #define ADC_SQR3_SQ2_0 0x00000020U
963 #define ADC_SQR3_SQ2_1 0x00000040U
964 #define ADC_SQR3_SQ2_2 0x00000080U
965 #define ADC_SQR3_SQ2_3 0x00000100U
966 #define ADC_SQR3_SQ2_4 0x00000200U
967 #define ADC_SQR3_SQ3 0x00007C00U
968 #define ADC_SQR3_SQ3_0 0x00000400U
969 #define ADC_SQR3_SQ3_1 0x00000800U
970 #define ADC_SQR3_SQ3_2 0x00001000U
971 #define ADC_SQR3_SQ3_3 0x00002000U
972 #define ADC_SQR3_SQ3_4 0x00004000U
973 #define ADC_SQR3_SQ4 0x000F8000U
974 #define ADC_SQR3_SQ4_0 0x00008000U
975 #define ADC_SQR3_SQ4_1 0x00010000U
976 #define ADC_SQR3_SQ4_2 0x00020000U
977 #define ADC_SQR3_SQ4_3 0x00040000U
978 #define ADC_SQR3_SQ4_4 0x00080000U
979 #define ADC_SQR3_SQ5 0x01F00000U
980 #define ADC_SQR3_SQ5_0 0x00100000U
981 #define ADC_SQR3_SQ5_1 0x00200000U
982 #define ADC_SQR3_SQ5_2 0x00400000U
983 #define ADC_SQR3_SQ5_3 0x00800000U
984 #define ADC_SQR3_SQ5_4 0x01000000U
985 #define ADC_SQR3_SQ6 0x3E000000U
986 #define ADC_SQR3_SQ6_0 0x02000000U
987 #define ADC_SQR3_SQ6_1 0x04000000U
988 #define ADC_SQR3_SQ6_2 0x08000000U
989 #define ADC_SQR3_SQ6_3 0x10000000U
990 #define ADC_SQR3_SQ6_4 0x20000000U
992 /******************* Bit definition for ADC_JSQR register *******************/
993 #define ADC_JSQR_JSQ1 0x0000001FU
994 #define ADC_JSQR_JSQ1_0 0x00000001U
995 #define ADC_JSQR_JSQ1_1 0x00000002U
996 #define ADC_JSQR_JSQ1_2 0x00000004U
997 #define ADC_JSQR_JSQ1_3 0x00000008U
998 #define ADC_JSQR_JSQ1_4 0x00000010U
999 #define ADC_JSQR_JSQ2 0x000003E0U
1000 #define ADC_JSQR_JSQ2_0 0x00000020U
1001 #define ADC_JSQR_JSQ2_1 0x00000040U
1002 #define ADC_JSQR_JSQ2_2 0x00000080U
1003 #define ADC_JSQR_JSQ2_3 0x00000100U
1004 #define ADC_JSQR_JSQ2_4 0x00000200U
1005 #define ADC_JSQR_JSQ3 0x00007C00U
1006 #define ADC_JSQR_JSQ3_0 0x00000400U
1007 #define ADC_JSQR_JSQ3_1 0x00000800U
1008 #define ADC_JSQR_JSQ3_2 0x00001000U
1009 #define ADC_JSQR_JSQ3_3 0x00002000U
1010 #define ADC_JSQR_JSQ3_4 0x00004000U
1011 #define ADC_JSQR_JSQ4 0x000F8000U
1012 #define ADC_JSQR_JSQ4_0 0x00008000U
1013 #define ADC_JSQR_JSQ4_1 0x00010000U
1014 #define ADC_JSQR_JSQ4_2 0x00020000U
1015 #define ADC_JSQR_JSQ4_3 0x00040000U
1016 #define ADC_JSQR_JSQ4_4 0x00080000U
1017 #define ADC_JSQR_JL 0x00300000U
1018 #define ADC_JSQR_JL_0 0x00100000U
1019 #define ADC_JSQR_JL_1 0x00200000U
1021 /******************* Bit definition for ADC_JDR1 register *******************/
1022 #define ADC_JDR1_JDATA 0xFFFFU
1024 /******************* Bit definition for ADC_JDR2 register *******************/
1025 #define ADC_JDR2_JDATA 0xFFFFU
1027 /******************* Bit definition for ADC_JDR3 register *******************/
1028 #define ADC_JDR3_JDATA 0xFFFFU
1030 /******************* Bit definition for ADC_JDR4 register *******************/
1031 #define ADC_JDR4_JDATA 0xFFFFU
1033 /******************** Bit definition for ADC_DR register ********************/
1034 #define ADC_DR_DATA 0x0000FFFFU
1035 #define ADC_DR_ADC2DATA 0xFFFF0000U
1037 /******************* Bit definition for ADC_CSR register ********************/
1038 #define ADC_CSR_AWD1 0x00000001U
1039 #define ADC_CSR_EOC1 0x00000002U
1040 #define ADC_CSR_JEOC1 0x00000004U
1041 #define ADC_CSR_JSTRT1 0x00000008U
1042 #define ADC_CSR_STRT1 0x00000010U
1043 #define ADC_CSR_OVR1 0x00000020U
1044 #define ADC_CSR_AWD2 0x00000100U
1045 #define ADC_CSR_EOC2 0x00000200U
1046 #define ADC_CSR_JEOC2 0x00000400U
1047 #define ADC_CSR_JSTRT2 0x00000800U
1048 #define ADC_CSR_STRT2 0x00001000U
1049 #define ADC_CSR_OVR2 0x00002000U
1050 #define ADC_CSR_AWD3 0x00010000U
1051 #define ADC_CSR_EOC3 0x00020000U
1052 #define ADC_CSR_JEOC3 0x00040000U
1053 #define ADC_CSR_JSTRT3 0x00080000U
1054 #define ADC_CSR_STRT3 0x00100000U
1055 #define ADC_CSR_OVR3 0x00200000U
1057 /* Legacy defines */
1058 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1059 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1060 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1061 
1062 /******************* Bit definition for ADC_CCR register ********************/
1063 #define ADC_CCR_MULTI 0x0000001FU
1064 #define ADC_CCR_MULTI_0 0x00000001U
1065 #define ADC_CCR_MULTI_1 0x00000002U
1066 #define ADC_CCR_MULTI_2 0x00000004U
1067 #define ADC_CCR_MULTI_3 0x00000008U
1068 #define ADC_CCR_MULTI_4 0x00000010U
1069 #define ADC_CCR_DELAY 0x00000F00U
1070 #define ADC_CCR_DELAY_0 0x00000100U
1071 #define ADC_CCR_DELAY_1 0x00000200U
1072 #define ADC_CCR_DELAY_2 0x00000400U
1073 #define ADC_CCR_DELAY_3 0x00000800U
1074 #define ADC_CCR_DDS 0x00002000U
1075 #define ADC_CCR_DMA 0x0000C000U
1076 #define ADC_CCR_DMA_0 0x00004000U
1077 #define ADC_CCR_DMA_1 0x00008000U
1078 #define ADC_CCR_ADCPRE 0x00030000U
1079 #define ADC_CCR_ADCPRE_0 0x00010000U
1080 #define ADC_CCR_ADCPRE_1 0x00020000U
1081 #define ADC_CCR_VBATE 0x00400000U
1082 #define ADC_CCR_TSVREFE 0x00800000U
1084 /******************* Bit definition for ADC_CDR register ********************/
1085 #define ADC_CDR_DATA1 0x0000FFFFU
1086 #define ADC_CDR_DATA2 0xFFFF0000U
1088 /******************************************************************************/
1089 /* */
1090 /* CRC calculation unit */
1091 /* */
1092 /******************************************************************************/
1093 /******************* Bit definition for CRC_DR register *********************/
1094 #define CRC_DR_DR 0xFFFFFFFFU
1097 /******************* Bit definition for CRC_IDR register ********************/
1098 #define CRC_IDR_IDR 0xFFU
1101 /******************** Bit definition for CRC_CR register ********************/
1102 #define CRC_CR_RESET 0x01U
1104 /******************************************************************************/
1105 /* */
1106 /* Debug MCU */
1107 /* */
1108 /******************************************************************************/
1109 
1110 /******************************************************************************/
1111 /* */
1112 /* DMA Controller */
1113 /* */
1114 /******************************************************************************/
1115 /******************** Bits definition for DMA_SxCR register *****************/
1116 #define DMA_SxCR_CHSEL 0x0E000000U
1117 #define DMA_SxCR_CHSEL_0 0x02000000U
1118 #define DMA_SxCR_CHSEL_1 0x04000000U
1119 #define DMA_SxCR_CHSEL_2 0x08000000U
1120 #define DMA_SxCR_MBURST 0x01800000U
1121 #define DMA_SxCR_MBURST_0 0x00800000U
1122 #define DMA_SxCR_MBURST_1 0x01000000U
1123 #define DMA_SxCR_PBURST 0x00600000U
1124 #define DMA_SxCR_PBURST_0 0x00200000U
1125 #define DMA_SxCR_PBURST_1 0x00400000U
1126 #define DMA_SxCR_CT 0x00080000U
1127 #define DMA_SxCR_DBM 0x00040000U
1128 #define DMA_SxCR_PL 0x00030000U
1129 #define DMA_SxCR_PL_0 0x00010000U
1130 #define DMA_SxCR_PL_1 0x00020000U
1131 #define DMA_SxCR_PINCOS 0x00008000U
1132 #define DMA_SxCR_MSIZE 0x00006000U
1133 #define DMA_SxCR_MSIZE_0 0x00002000U
1134 #define DMA_SxCR_MSIZE_1 0x00004000U
1135 #define DMA_SxCR_PSIZE 0x00001800U
1136 #define DMA_SxCR_PSIZE_0 0x00000800U
1137 #define DMA_SxCR_PSIZE_1 0x00001000U
1138 #define DMA_SxCR_MINC 0x00000400U
1139 #define DMA_SxCR_PINC 0x00000200U
1140 #define DMA_SxCR_CIRC 0x00000100U
1141 #define DMA_SxCR_DIR 0x000000C0U
1142 #define DMA_SxCR_DIR_0 0x00000040U
1143 #define DMA_SxCR_DIR_1 0x00000080U
1144 #define DMA_SxCR_PFCTRL 0x00000020U
1145 #define DMA_SxCR_TCIE 0x00000010U
1146 #define DMA_SxCR_HTIE 0x00000008U
1147 #define DMA_SxCR_TEIE 0x00000004U
1148 #define DMA_SxCR_DMEIE 0x00000002U
1149 #define DMA_SxCR_EN 0x00000001U
1150 
1151 /* Legacy defines */
1152 #define DMA_SxCR_ACK 0x00100000U
1153 
1154 /******************** Bits definition for DMA_SxCNDTR register **************/
1155 #define DMA_SxNDT 0x0000FFFFU
1156 #define DMA_SxNDT_0 0x00000001U
1157 #define DMA_SxNDT_1 0x00000002U
1158 #define DMA_SxNDT_2 0x00000004U
1159 #define DMA_SxNDT_3 0x00000008U
1160 #define DMA_SxNDT_4 0x00000010U
1161 #define DMA_SxNDT_5 0x00000020U
1162 #define DMA_SxNDT_6 0x00000040U
1163 #define DMA_SxNDT_7 0x00000080U
1164 #define DMA_SxNDT_8 0x00000100U
1165 #define DMA_SxNDT_9 0x00000200U
1166 #define DMA_SxNDT_10 0x00000400U
1167 #define DMA_SxNDT_11 0x00000800U
1168 #define DMA_SxNDT_12 0x00001000U
1169 #define DMA_SxNDT_13 0x00002000U
1170 #define DMA_SxNDT_14 0x00004000U
1171 #define DMA_SxNDT_15 0x00008000U
1172 
1173 /******************** Bits definition for DMA_SxFCR register ****************/
1174 #define DMA_SxFCR_FEIE 0x00000080U
1175 #define DMA_SxFCR_FS 0x00000038U
1176 #define DMA_SxFCR_FS_0 0x00000008U
1177 #define DMA_SxFCR_FS_1 0x00000010U
1178 #define DMA_SxFCR_FS_2 0x00000020U
1179 #define DMA_SxFCR_DMDIS 0x00000004U
1180 #define DMA_SxFCR_FTH 0x00000003U
1181 #define DMA_SxFCR_FTH_0 0x00000001U
1182 #define DMA_SxFCR_FTH_1 0x00000002U
1183 
1184 /******************** Bits definition for DMA_LISR register *****************/
1185 #define DMA_LISR_TCIF3 0x08000000U
1186 #define DMA_LISR_HTIF3 0x04000000U
1187 #define DMA_LISR_TEIF3 0x02000000U
1188 #define DMA_LISR_DMEIF3 0x01000000U
1189 #define DMA_LISR_FEIF3 0x00400000U
1190 #define DMA_LISR_TCIF2 0x00200000U
1191 #define DMA_LISR_HTIF2 0x00100000U
1192 #define DMA_LISR_TEIF2 0x00080000U
1193 #define DMA_LISR_DMEIF2 0x00040000U
1194 #define DMA_LISR_FEIF2 0x00010000U
1195 #define DMA_LISR_TCIF1 0x00000800U
1196 #define DMA_LISR_HTIF1 0x00000400U
1197 #define DMA_LISR_TEIF1 0x00000200U
1198 #define DMA_LISR_DMEIF1 0x00000100U
1199 #define DMA_LISR_FEIF1 0x00000040U
1200 #define DMA_LISR_TCIF0 0x00000020U
1201 #define DMA_LISR_HTIF0 0x00000010U
1202 #define DMA_LISR_TEIF0 0x00000008U
1203 #define DMA_LISR_DMEIF0 0x00000004U
1204 #define DMA_LISR_FEIF0 0x00000001U
1205 
1206 /******************** Bits definition for DMA_HISR register *****************/
1207 #define DMA_HISR_TCIF7 0x08000000U
1208 #define DMA_HISR_HTIF7 0x04000000U
1209 #define DMA_HISR_TEIF7 0x02000000U
1210 #define DMA_HISR_DMEIF7 0x01000000U
1211 #define DMA_HISR_FEIF7 0x00400000U
1212 #define DMA_HISR_TCIF6 0x00200000U
1213 #define DMA_HISR_HTIF6 0x00100000U
1214 #define DMA_HISR_TEIF6 0x00080000U
1215 #define DMA_HISR_DMEIF6 0x00040000U
1216 #define DMA_HISR_FEIF6 0x00010000U
1217 #define DMA_HISR_TCIF5 0x00000800U
1218 #define DMA_HISR_HTIF5 0x00000400U
1219 #define DMA_HISR_TEIF5 0x00000200U
1220 #define DMA_HISR_DMEIF5 0x00000100U
1221 #define DMA_HISR_FEIF5 0x00000040U
1222 #define DMA_HISR_TCIF4 0x00000020U
1223 #define DMA_HISR_HTIF4 0x00000010U
1224 #define DMA_HISR_TEIF4 0x00000008U
1225 #define DMA_HISR_DMEIF4 0x00000004U
1226 #define DMA_HISR_FEIF4 0x00000001U
1227 
1228 /******************** Bits definition for DMA_LIFCR register ****************/
1229 #define DMA_LIFCR_CTCIF3 0x08000000U
1230 #define DMA_LIFCR_CHTIF3 0x04000000U
1231 #define DMA_LIFCR_CTEIF3 0x02000000U
1232 #define DMA_LIFCR_CDMEIF3 0x01000000U
1233 #define DMA_LIFCR_CFEIF3 0x00400000U
1234 #define DMA_LIFCR_CTCIF2 0x00200000U
1235 #define DMA_LIFCR_CHTIF2 0x00100000U
1236 #define DMA_LIFCR_CTEIF2 0x00080000U
1237 #define DMA_LIFCR_CDMEIF2 0x00040000U
1238 #define DMA_LIFCR_CFEIF2 0x00010000U
1239 #define DMA_LIFCR_CTCIF1 0x00000800U
1240 #define DMA_LIFCR_CHTIF1 0x00000400U
1241 #define DMA_LIFCR_CTEIF1 0x00000200U
1242 #define DMA_LIFCR_CDMEIF1 0x00000100U
1243 #define DMA_LIFCR_CFEIF1 0x00000040U
1244 #define DMA_LIFCR_CTCIF0 0x00000020U
1245 #define DMA_LIFCR_CHTIF0 0x00000010U
1246 #define DMA_LIFCR_CTEIF0 0x00000008U
1247 #define DMA_LIFCR_CDMEIF0 0x00000004U
1248 #define DMA_LIFCR_CFEIF0 0x00000001U
1249 
1250 /******************** Bits definition for DMA_HIFCR register ****************/
1251 #define DMA_HIFCR_CTCIF7 0x08000000U
1252 #define DMA_HIFCR_CHTIF7 0x04000000U
1253 #define DMA_HIFCR_CTEIF7 0x02000000U
1254 #define DMA_HIFCR_CDMEIF7 0x01000000U
1255 #define DMA_HIFCR_CFEIF7 0x00400000U
1256 #define DMA_HIFCR_CTCIF6 0x00200000U
1257 #define DMA_HIFCR_CHTIF6 0x00100000U
1258 #define DMA_HIFCR_CTEIF6 0x00080000U
1259 #define DMA_HIFCR_CDMEIF6 0x00040000U
1260 #define DMA_HIFCR_CFEIF6 0x00010000U
1261 #define DMA_HIFCR_CTCIF5 0x00000800U
1262 #define DMA_HIFCR_CHTIF5 0x00000400U
1263 #define DMA_HIFCR_CTEIF5 0x00000200U
1264 #define DMA_HIFCR_CDMEIF5 0x00000100U
1265 #define DMA_HIFCR_CFEIF5 0x00000040U
1266 #define DMA_HIFCR_CTCIF4 0x00000020U
1267 #define DMA_HIFCR_CHTIF4 0x00000010U
1268 #define DMA_HIFCR_CTEIF4 0x00000008U
1269 #define DMA_HIFCR_CDMEIF4 0x00000004U
1270 #define DMA_HIFCR_CFEIF4 0x00000001U
1271 
1272 
1273 /******************************************************************************/
1274 /* */
1275 /* External Interrupt/Event Controller */
1276 /* */
1277 /******************************************************************************/
1278 /******************* Bit definition for EXTI_IMR register *******************/
1279 #define EXTI_IMR_MR0 0x00000001U
1280 #define EXTI_IMR_MR1 0x00000002U
1281 #define EXTI_IMR_MR2 0x00000004U
1282 #define EXTI_IMR_MR3 0x00000008U
1283 #define EXTI_IMR_MR4 0x00000010U
1284 #define EXTI_IMR_MR5 0x00000020U
1285 #define EXTI_IMR_MR6 0x00000040U
1286 #define EXTI_IMR_MR7 0x00000080U
1287 #define EXTI_IMR_MR8 0x00000100U
1288 #define EXTI_IMR_MR9 0x00000200U
1289 #define EXTI_IMR_MR10 0x00000400U
1290 #define EXTI_IMR_MR11 0x00000800U
1291 #define EXTI_IMR_MR12 0x00001000U
1292 #define EXTI_IMR_MR13 0x00002000U
1293 #define EXTI_IMR_MR14 0x00004000U
1294 #define EXTI_IMR_MR15 0x00008000U
1295 #define EXTI_IMR_MR16 0x00010000U
1296 #define EXTI_IMR_MR17 0x00020000U
1297 #define EXTI_IMR_MR18 0x00040000U
1298 #define EXTI_IMR_MR19 0x00080000U
1299 #define EXTI_IMR_MR20 0x00100000U
1300 #define EXTI_IMR_MR21 0x00200000U
1301 #define EXTI_IMR_MR22 0x00400000U
1302 #define EXTI_IMR_MR23 0x00800000U
1304 /******************* Bit definition for EXTI_EMR register *******************/
1305 #define EXTI_EMR_MR0 0x00000001U
1306 #define EXTI_EMR_MR1 0x00000002U
1307 #define EXTI_EMR_MR2 0x00000004U
1308 #define EXTI_EMR_MR3 0x00000008U
1309 #define EXTI_EMR_MR4 0x00000010U
1310 #define EXTI_EMR_MR5 0x00000020U
1311 #define EXTI_EMR_MR6 0x00000040U
1312 #define EXTI_EMR_MR7 0x00000080U
1313 #define EXTI_EMR_MR8 0x00000100U
1314 #define EXTI_EMR_MR9 0x00000200U
1315 #define EXTI_EMR_MR10 0x00000400U
1316 #define EXTI_EMR_MR11 0x00000800U
1317 #define EXTI_EMR_MR12 0x00001000U
1318 #define EXTI_EMR_MR13 0x00002000U
1319 #define EXTI_EMR_MR14 0x00004000U
1320 #define EXTI_EMR_MR15 0x00008000U
1321 #define EXTI_EMR_MR16 0x00010000U
1322 #define EXTI_EMR_MR17 0x00020000U
1323 #define EXTI_EMR_MR18 0x00040000U
1324 #define EXTI_EMR_MR19 0x00080000U
1325 #define EXTI_EMR_MR20 0x00100000U
1326 #define EXTI_EMR_MR21 0x00200000U
1327 #define EXTI_EMR_MR22 0x00400000U
1328 #define EXTI_EMR_MR23 0x00800000U
1330 /****************** Bit definition for EXTI_RTSR register *******************/
1331 #define EXTI_RTSR_TR0 0x00000001U
1332 #define EXTI_RTSR_TR1 0x00000002U
1333 #define EXTI_RTSR_TR2 0x00000004U
1334 #define EXTI_RTSR_TR3 0x00000008U
1335 #define EXTI_RTSR_TR4 0x00000010U
1336 #define EXTI_RTSR_TR5 0x00000020U
1337 #define EXTI_RTSR_TR6 0x00000040U
1338 #define EXTI_RTSR_TR7 0x00000080U
1339 #define EXTI_RTSR_TR8 0x00000100U
1340 #define EXTI_RTSR_TR9 0x00000200U
1341 #define EXTI_RTSR_TR10 0x00000400U
1342 #define EXTI_RTSR_TR11 0x00000800U
1343 #define EXTI_RTSR_TR12 0x00001000U
1344 #define EXTI_RTSR_TR13 0x00002000U
1345 #define EXTI_RTSR_TR14 0x00004000U
1346 #define EXTI_RTSR_TR15 0x00008000U
1347 #define EXTI_RTSR_TR16 0x00010000U
1348 #define EXTI_RTSR_TR17 0x00020000U
1349 #define EXTI_RTSR_TR18 0x00040000U
1350 #define EXTI_RTSR_TR19 0x00080000U
1351 #define EXTI_RTSR_TR20 0x00100000U
1352 #define EXTI_RTSR_TR21 0x00200000U
1353 #define EXTI_RTSR_TR22 0x00400000U
1354 #define EXTI_RTSR_TR23 0x00800000U
1356 /****************** Bit definition for EXTI_FTSR register *******************/
1357 #define EXTI_FTSR_TR0 0x00000001U
1358 #define EXTI_FTSR_TR1 0x00000002U
1359 #define EXTI_FTSR_TR2 0x00000004U
1360 #define EXTI_FTSR_TR3 0x00000008U
1361 #define EXTI_FTSR_TR4 0x00000010U
1362 #define EXTI_FTSR_TR5 0x00000020U
1363 #define EXTI_FTSR_TR6 0x00000040U
1364 #define EXTI_FTSR_TR7 0x00000080U
1365 #define EXTI_FTSR_TR8 0x00000100U
1366 #define EXTI_FTSR_TR9 0x00000200U
1367 #define EXTI_FTSR_TR10 0x00000400U
1368 #define EXTI_FTSR_TR11 0x00000800U
1369 #define EXTI_FTSR_TR12 0x00001000U
1370 #define EXTI_FTSR_TR13 0x00002000U
1371 #define EXTI_FTSR_TR14 0x00004000U
1372 #define EXTI_FTSR_TR15 0x00008000U
1373 #define EXTI_FTSR_TR16 0x00010000U
1374 #define EXTI_FTSR_TR17 0x00020000U
1375 #define EXTI_FTSR_TR18 0x00040000U
1376 #define EXTI_FTSR_TR19 0x00080000U
1377 #define EXTI_FTSR_TR20 0x00100000U
1378 #define EXTI_FTSR_TR21 0x00200000U
1379 #define EXTI_FTSR_TR22 0x00400000U
1380 #define EXTI_FTSR_TR23 0x00800000U
1382 /****************** Bit definition for EXTI_SWIER register ******************/
1383 #define EXTI_SWIER_SWIER0 0x00000001U
1384 #define EXTI_SWIER_SWIER1 0x00000002U
1385 #define EXTI_SWIER_SWIER2 0x00000004U
1386 #define EXTI_SWIER_SWIER3 0x00000008U
1387 #define EXTI_SWIER_SWIER4 0x00000010U
1388 #define EXTI_SWIER_SWIER5 0x00000020U
1389 #define EXTI_SWIER_SWIER6 0x00000040U
1390 #define EXTI_SWIER_SWIER7 0x00000080U
1391 #define EXTI_SWIER_SWIER8 0x00000100U
1392 #define EXTI_SWIER_SWIER9 0x00000200U
1393 #define EXTI_SWIER_SWIER10 0x00000400U
1394 #define EXTI_SWIER_SWIER11 0x00000800U
1395 #define EXTI_SWIER_SWIER12 0x00001000U
1396 #define EXTI_SWIER_SWIER13 0x00002000U
1397 #define EXTI_SWIER_SWIER14 0x00004000U
1398 #define EXTI_SWIER_SWIER15 0x00008000U
1399 #define EXTI_SWIER_SWIER16 0x00010000U
1400 #define EXTI_SWIER_SWIER17 0x00020000U
1401 #define EXTI_SWIER_SWIER18 0x00040000U
1402 #define EXTI_SWIER_SWIER19 0x00080000U
1403 #define EXTI_SWIER_SWIER20 0x00100000U
1404 #define EXTI_SWIER_SWIER21 0x00200000U
1405 #define EXTI_SWIER_SWIER22 0x00400000U
1406 #define EXTI_SWIER_SWIER23 0x00800000U
1408 /******************* Bit definition for EXTI_PR register ********************/
1409 #define EXTI_PR_PR0 0x00000001U
1410 #define EXTI_PR_PR1 0x00000002U
1411 #define EXTI_PR_PR2 0x00000004U
1412 #define EXTI_PR_PR3 0x00000008U
1413 #define EXTI_PR_PR4 0x00000010U
1414 #define EXTI_PR_PR5 0x00000020U
1415 #define EXTI_PR_PR6 0x00000040U
1416 #define EXTI_PR_PR7 0x00000080U
1417 #define EXTI_PR_PR8 0x00000100U
1418 #define EXTI_PR_PR9 0x00000200U
1419 #define EXTI_PR_PR10 0x00000400U
1420 #define EXTI_PR_PR11 0x00000800U
1421 #define EXTI_PR_PR12 0x00001000U
1422 #define EXTI_PR_PR13 0x00002000U
1423 #define EXTI_PR_PR14 0x00004000U
1424 #define EXTI_PR_PR15 0x00008000U
1425 #define EXTI_PR_PR16 0x00010000U
1426 #define EXTI_PR_PR17 0x00020000U
1427 #define EXTI_PR_PR18 0x00040000U
1428 #define EXTI_PR_PR19 0x00080000U
1429 #define EXTI_PR_PR20 0x00100000U
1430 #define EXTI_PR_PR21 0x00200000U
1431 #define EXTI_PR_PR22 0x00400000U
1432 #define EXTI_PR_PR23 0x00800000U
1434 /******************************************************************************/
1435 /* */
1436 /* FLASH */
1437 /* */
1438 /******************************************************************************/
1439 /******************* Bits definition for FLASH_ACR register *****************/
1440 #define FLASH_ACR_LATENCY 0x0000000FU
1441 #define FLASH_ACR_LATENCY_0WS 0x00000000U
1442 #define FLASH_ACR_LATENCY_1WS 0x00000001U
1443 #define FLASH_ACR_LATENCY_2WS 0x00000002U
1444 #define FLASH_ACR_LATENCY_3WS 0x00000003U
1445 #define FLASH_ACR_LATENCY_4WS 0x00000004U
1446 #define FLASH_ACR_LATENCY_5WS 0x00000005U
1447 #define FLASH_ACR_LATENCY_6WS 0x00000006U
1448 #define FLASH_ACR_LATENCY_7WS 0x00000007U
1449 
1450 #define FLASH_ACR_PRFTEN 0x00000100U
1451 #define FLASH_ACR_ICEN 0x00000200U
1452 #define FLASH_ACR_DCEN 0x00000400U
1453 #define FLASH_ACR_ICRST 0x00000800U
1454 #define FLASH_ACR_DCRST 0x00001000U
1455 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
1456 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
1457 
1458 /******************* Bits definition for FLASH_SR register ******************/
1459 #define FLASH_SR_EOP 0x00000001U
1460 #define FLASH_SR_SOP 0x00000002U
1461 #define FLASH_SR_WRPERR 0x00000010U
1462 #define FLASH_SR_PGAERR 0x00000020U
1463 #define FLASH_SR_PGPERR 0x00000040U
1464 #define FLASH_SR_PGSERR 0x00000080U
1465 #define FLASH_SR_BSY 0x00010000U
1466 
1467 /******************* Bits definition for FLASH_CR register ******************/
1468 #define FLASH_CR_PG 0x00000001U
1469 #define FLASH_CR_SER 0x00000002U
1470 #define FLASH_CR_MER 0x00000004U
1471 #define FLASH_CR_SNB 0x000000F8U
1472 #define FLASH_CR_SNB_0 0x00000008U
1473 #define FLASH_CR_SNB_1 0x00000010U
1474 #define FLASH_CR_SNB_2 0x00000020U
1475 #define FLASH_CR_SNB_3 0x00000040U
1476 #define FLASH_CR_SNB_4 0x00000080U
1477 #define FLASH_CR_PSIZE 0x00000300U
1478 #define FLASH_CR_PSIZE_0 0x00000100U
1479 #define FLASH_CR_PSIZE_1 0x00000200U
1480 #define FLASH_CR_STRT 0x00010000U
1481 #define FLASH_CR_EOPIE 0x01000000U
1482 #define FLASH_CR_LOCK 0x80000000U
1483 
1484 /******************* Bits definition for FLASH_OPTCR register ***************/
1485 #define FLASH_OPTCR_OPTLOCK 0x00000001U
1486 #define FLASH_OPTCR_OPTSTRT 0x00000002U
1487 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
1488 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
1489 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
1490 
1491 #define FLASH_OPTCR_WDG_SW 0x00000020U
1492 #define FLASH_OPTCR_nRST_STOP 0x00000040U
1493 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
1494 #define FLASH_OPTCR_RDP 0x0000FF00U
1495 #define FLASH_OPTCR_RDP_0 0x00000100U
1496 #define FLASH_OPTCR_RDP_1 0x00000200U
1497 #define FLASH_OPTCR_RDP_2 0x00000400U
1498 #define FLASH_OPTCR_RDP_3 0x00000800U
1499 #define FLASH_OPTCR_RDP_4 0x00001000U
1500 #define FLASH_OPTCR_RDP_5 0x00002000U
1501 #define FLASH_OPTCR_RDP_6 0x00004000U
1502 #define FLASH_OPTCR_RDP_7 0x00008000U
1503 #define FLASH_OPTCR_nWRP 0x0FFF0000U
1504 #define FLASH_OPTCR_nWRP_0 0x00010000U
1505 #define FLASH_OPTCR_nWRP_1 0x00020000U
1506 #define FLASH_OPTCR_nWRP_2 0x00040000U
1507 #define FLASH_OPTCR_nWRP_3 0x00080000U
1508 #define FLASH_OPTCR_nWRP_4 0x00100000U
1509 #define FLASH_OPTCR_nWRP_5 0x00200000U
1510 #define FLASH_OPTCR_nWRP_6 0x00400000U
1511 #define FLASH_OPTCR_nWRP_7 0x00800000U
1512 #define FLASH_OPTCR_nWRP_8 0x01000000U
1513 #define FLASH_OPTCR_nWRP_9 0x02000000U
1514 #define FLASH_OPTCR_nWRP_10 0x04000000U
1515 #define FLASH_OPTCR_nWRP_11 0x08000000U
1516 
1517 /****************** Bits definition for FLASH_OPTCR1 register ***************/
1518 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
1519 #define FLASH_OPTCR1_nWRP_0 0x00010000U
1520 #define FLASH_OPTCR1_nWRP_1 0x00020000U
1521 #define FLASH_OPTCR1_nWRP_2 0x00040000U
1522 #define FLASH_OPTCR1_nWRP_3 0x00080000U
1523 #define FLASH_OPTCR1_nWRP_4 0x00100000U
1524 #define FLASH_OPTCR1_nWRP_5 0x00200000U
1525 #define FLASH_OPTCR1_nWRP_6 0x00400000U
1526 #define FLASH_OPTCR1_nWRP_7 0x00800000U
1527 #define FLASH_OPTCR1_nWRP_8 0x01000000U
1528 #define FLASH_OPTCR1_nWRP_9 0x02000000U
1529 #define FLASH_OPTCR1_nWRP_10 0x04000000U
1530 #define FLASH_OPTCR1_nWRP_11 0x08000000U
1531 
1532 /******************************************************************************/
1533 /* */
1534 /* General Purpose I/O */
1535 /* */
1536 /******************************************************************************/
1537 /****************** Bits definition for GPIO_MODER register *****************/
1538 #define GPIO_MODER_MODER0 0x00000003U
1539 #define GPIO_MODER_MODER0_0 0x00000001U
1540 #define GPIO_MODER_MODER0_1 0x00000002U
1541 
1542 #define GPIO_MODER_MODER1 0x0000000CU
1543 #define GPIO_MODER_MODER1_0 0x00000004U
1544 #define GPIO_MODER_MODER1_1 0x00000008U
1545 
1546 #define GPIO_MODER_MODER2 0x00000030U
1547 #define GPIO_MODER_MODER2_0 0x00000010U
1548 #define GPIO_MODER_MODER2_1 0x00000020U
1549 
1550 #define GPIO_MODER_MODER3 0x000000C0U
1551 #define GPIO_MODER_MODER3_0 0x00000040U
1552 #define GPIO_MODER_MODER3_1 0x00000080U
1553 
1554 #define GPIO_MODER_MODER4 0x00000300U
1555 #define GPIO_MODER_MODER4_0 0x00000100U
1556 #define GPIO_MODER_MODER4_1 0x00000200U
1557 
1558 #define GPIO_MODER_MODER5 0x00000C00U
1559 #define GPIO_MODER_MODER5_0 0x00000400U
1560 #define GPIO_MODER_MODER5_1 0x00000800U
1561 
1562 #define GPIO_MODER_MODER6 0x00003000U
1563 #define GPIO_MODER_MODER6_0 0x00001000U
1564 #define GPIO_MODER_MODER6_1 0x00002000U
1565 
1566 #define GPIO_MODER_MODER7 0x0000C000U
1567 #define GPIO_MODER_MODER7_0 0x00004000U
1568 #define GPIO_MODER_MODER7_1 0x00008000U
1569 
1570 #define GPIO_MODER_MODER8 0x00030000U
1571 #define GPIO_MODER_MODER8_0 0x00010000U
1572 #define GPIO_MODER_MODER8_1 0x00020000U
1573 
1574 #define GPIO_MODER_MODER9 0x000C0000U
1575 #define GPIO_MODER_MODER9_0 0x00040000U
1576 #define GPIO_MODER_MODER9_1 0x00080000U
1577 
1578 #define GPIO_MODER_MODER10 0x00300000U
1579 #define GPIO_MODER_MODER10_0 0x00100000U
1580 #define GPIO_MODER_MODER10_1 0x00200000U
1581 
1582 #define GPIO_MODER_MODER11 0x00C00000U
1583 #define GPIO_MODER_MODER11_0 0x00400000U
1584 #define GPIO_MODER_MODER11_1 0x00800000U
1585 
1586 #define GPIO_MODER_MODER12 0x03000000U
1587 #define GPIO_MODER_MODER12_0 0x01000000U
1588 #define GPIO_MODER_MODER12_1 0x02000000U
1589 
1590 #define GPIO_MODER_MODER13 0x0C000000U
1591 #define GPIO_MODER_MODER13_0 0x04000000U
1592 #define GPIO_MODER_MODER13_1 0x08000000U
1593 
1594 #define GPIO_MODER_MODER14 0x30000000U
1595 #define GPIO_MODER_MODER14_0 0x10000000U
1596 #define GPIO_MODER_MODER14_1 0x20000000U
1597 
1598 #define GPIO_MODER_MODER15 0xC0000000U
1599 #define GPIO_MODER_MODER15_0 0x40000000U
1600 #define GPIO_MODER_MODER15_1 0x80000000U
1601 
1602 /****************** Bits definition for GPIO_OTYPER register ****************/
1603 #define GPIO_OTYPER_OT_0 0x00000001U
1604 #define GPIO_OTYPER_OT_1 0x00000002U
1605 #define GPIO_OTYPER_OT_2 0x00000004U
1606 #define GPIO_OTYPER_OT_3 0x00000008U
1607 #define GPIO_OTYPER_OT_4 0x00000010U
1608 #define GPIO_OTYPER_OT_5 0x00000020U
1609 #define GPIO_OTYPER_OT_6 0x00000040U
1610 #define GPIO_OTYPER_OT_7 0x00000080U
1611 #define GPIO_OTYPER_OT_8 0x00000100U
1612 #define GPIO_OTYPER_OT_9 0x00000200U
1613 #define GPIO_OTYPER_OT_10 0x00000400U
1614 #define GPIO_OTYPER_OT_11 0x00000800U
1615 #define GPIO_OTYPER_OT_12 0x00001000U
1616 #define GPIO_OTYPER_OT_13 0x00002000U
1617 #define GPIO_OTYPER_OT_14 0x00004000U
1618 #define GPIO_OTYPER_OT_15 0x00008000U
1619 
1620 /****************** Bits definition for GPIO_OSPEEDR register ***************/
1621 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
1622 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
1623 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
1624 
1625 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
1626 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
1627 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
1628 
1629 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
1630 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
1631 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
1632 
1633 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
1634 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
1635 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
1636 
1637 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
1638 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
1639 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
1640 
1641 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
1642 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
1643 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
1644 
1645 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
1646 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
1647 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
1648 
1649 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
1650 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
1651 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
1652 
1653 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
1654 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
1655 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
1656 
1657 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
1658 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
1659 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
1660 
1661 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
1662 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
1663 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
1664 
1665 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
1666 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
1667 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
1668 
1669 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
1670 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
1671 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
1672 
1673 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
1674 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
1675 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
1676 
1677 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
1678 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
1679 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
1680 
1681 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
1682 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
1683 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
1684 
1685 /****************** Bits definition for GPIO_PUPDR register *****************/
1686 #define GPIO_PUPDR_PUPDR0 0x00000003U
1687 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
1688 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
1689 
1690 #define GPIO_PUPDR_PUPDR1 0x0000000CU
1691 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
1692 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
1693 
1694 #define GPIO_PUPDR_PUPDR2 0x00000030U
1695 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
1696 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
1697 
1698 #define GPIO_PUPDR_PUPDR3 0x000000C0U
1699 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
1700 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
1701 
1702 #define GPIO_PUPDR_PUPDR4 0x00000300U
1703 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
1704 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
1705 
1706 #define GPIO_PUPDR_PUPDR5 0x00000C00U
1707 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
1708 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
1709 
1710 #define GPIO_PUPDR_PUPDR6 0x00003000U
1711 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
1712 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
1713 
1714 #define GPIO_PUPDR_PUPDR7 0x0000C000U
1715 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
1716 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
1717 
1718 #define GPIO_PUPDR_PUPDR8 0x00030000U
1719 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
1720 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
1721 
1722 #define GPIO_PUPDR_PUPDR9 0x000C0000U
1723 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
1724 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
1725 
1726 #define GPIO_PUPDR_PUPDR10 0x00300000U
1727 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
1728 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
1729 
1730 #define GPIO_PUPDR_PUPDR11 0x00C00000U
1731 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
1732 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
1733 
1734 #define GPIO_PUPDR_PUPDR12 0x03000000U
1735 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
1736 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
1737 
1738 #define GPIO_PUPDR_PUPDR13 0x0C000000U
1739 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
1740 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
1741 
1742 #define GPIO_PUPDR_PUPDR14 0x30000000U
1743 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
1744 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
1745 
1746 #define GPIO_PUPDR_PUPDR15 0xC0000000U
1747 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
1748 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
1749 
1750 /****************** Bits definition for GPIO_IDR register *******************/
1751 #define GPIO_IDR_IDR_0 0x00000001U
1752 #define GPIO_IDR_IDR_1 0x00000002U
1753 #define GPIO_IDR_IDR_2 0x00000004U
1754 #define GPIO_IDR_IDR_3 0x00000008U
1755 #define GPIO_IDR_IDR_4 0x00000010U
1756 #define GPIO_IDR_IDR_5 0x00000020U
1757 #define GPIO_IDR_IDR_6 0x00000040U
1758 #define GPIO_IDR_IDR_7 0x00000080U
1759 #define GPIO_IDR_IDR_8 0x00000100U
1760 #define GPIO_IDR_IDR_9 0x00000200U
1761 #define GPIO_IDR_IDR_10 0x00000400U
1762 #define GPIO_IDR_IDR_11 0x00000800U
1763 #define GPIO_IDR_IDR_12 0x00001000U
1764 #define GPIO_IDR_IDR_13 0x00002000U
1765 #define GPIO_IDR_IDR_14 0x00004000U
1766 #define GPIO_IDR_IDR_15 0x00008000U
1767 
1768 /****************** Bits definition for GPIO_ODR register *******************/
1769 #define GPIO_ODR_ODR_0 0x00000001U
1770 #define GPIO_ODR_ODR_1 0x00000002U
1771 #define GPIO_ODR_ODR_2 0x00000004U
1772 #define GPIO_ODR_ODR_3 0x00000008U
1773 #define GPIO_ODR_ODR_4 0x00000010U
1774 #define GPIO_ODR_ODR_5 0x00000020U
1775 #define GPIO_ODR_ODR_6 0x00000040U
1776 #define GPIO_ODR_ODR_7 0x00000080U
1777 #define GPIO_ODR_ODR_8 0x00000100U
1778 #define GPIO_ODR_ODR_9 0x00000200U
1779 #define GPIO_ODR_ODR_10 0x00000400U
1780 #define GPIO_ODR_ODR_11 0x00000800U
1781 #define GPIO_ODR_ODR_12 0x00001000U
1782 #define GPIO_ODR_ODR_13 0x00002000U
1783 #define GPIO_ODR_ODR_14 0x00004000U
1784 #define GPIO_ODR_ODR_15 0x00008000U
1785 
1786 /****************** Bits definition for GPIO_BSRR register ******************/
1787 #define GPIO_BSRR_BS_0 0x00000001U
1788 #define GPIO_BSRR_BS_1 0x00000002U
1789 #define GPIO_BSRR_BS_2 0x00000004U
1790 #define GPIO_BSRR_BS_3 0x00000008U
1791 #define GPIO_BSRR_BS_4 0x00000010U
1792 #define GPIO_BSRR_BS_5 0x00000020U
1793 #define GPIO_BSRR_BS_6 0x00000040U
1794 #define GPIO_BSRR_BS_7 0x00000080U
1795 #define GPIO_BSRR_BS_8 0x00000100U
1796 #define GPIO_BSRR_BS_9 0x00000200U
1797 #define GPIO_BSRR_BS_10 0x00000400U
1798 #define GPIO_BSRR_BS_11 0x00000800U
1799 #define GPIO_BSRR_BS_12 0x00001000U
1800 #define GPIO_BSRR_BS_13 0x00002000U
1801 #define GPIO_BSRR_BS_14 0x00004000U
1802 #define GPIO_BSRR_BS_15 0x00008000U
1803 #define GPIO_BSRR_BR_0 0x00010000U
1804 #define GPIO_BSRR_BR_1 0x00020000U
1805 #define GPIO_BSRR_BR_2 0x00040000U
1806 #define GPIO_BSRR_BR_3 0x00080000U
1807 #define GPIO_BSRR_BR_4 0x00100000U
1808 #define GPIO_BSRR_BR_5 0x00200000U
1809 #define GPIO_BSRR_BR_6 0x00400000U
1810 #define GPIO_BSRR_BR_7 0x00800000U
1811 #define GPIO_BSRR_BR_8 0x01000000U
1812 #define GPIO_BSRR_BR_9 0x02000000U
1813 #define GPIO_BSRR_BR_10 0x04000000U
1814 #define GPIO_BSRR_BR_11 0x08000000U
1815 #define GPIO_BSRR_BR_12 0x10000000U
1816 #define GPIO_BSRR_BR_13 0x20000000U
1817 #define GPIO_BSRR_BR_14 0x40000000U
1818 #define GPIO_BSRR_BR_15 0x80000000U
1819 
1820 /****************** Bit definition for GPIO_LCKR register *********************/
1821 #define GPIO_LCKR_LCK0 0x00000001U
1822 #define GPIO_LCKR_LCK1 0x00000002U
1823 #define GPIO_LCKR_LCK2 0x00000004U
1824 #define GPIO_LCKR_LCK3 0x00000008U
1825 #define GPIO_LCKR_LCK4 0x00000010U
1826 #define GPIO_LCKR_LCK5 0x00000020U
1827 #define GPIO_LCKR_LCK6 0x00000040U
1828 #define GPIO_LCKR_LCK7 0x00000080U
1829 #define GPIO_LCKR_LCK8 0x00000100U
1830 #define GPIO_LCKR_LCK9 0x00000200U
1831 #define GPIO_LCKR_LCK10 0x00000400U
1832 #define GPIO_LCKR_LCK11 0x00000800U
1833 #define GPIO_LCKR_LCK12 0x00001000U
1834 #define GPIO_LCKR_LCK13 0x00002000U
1835 #define GPIO_LCKR_LCK14 0x00004000U
1836 #define GPIO_LCKR_LCK15 0x00008000U
1837 #define GPIO_LCKR_LCKK 0x00010000U
1838 
1839 /******************************************************************************/
1840 /* */
1841 /* Inter-integrated Circuit Interface */
1842 /* */
1843 /******************************************************************************/
1844 /******************* Bit definition for I2C_CR1 register ********************/
1845 #define I2C_CR1_PE 0x00000001U
1846 #define I2C_CR1_SMBUS 0x00000002U
1847 #define I2C_CR1_SMBTYPE 0x00000008U
1848 #define I2C_CR1_ENARP 0x00000010U
1849 #define I2C_CR1_ENPEC 0x00000020U
1850 #define I2C_CR1_ENGC 0x00000040U
1851 #define I2C_CR1_NOSTRETCH 0x00000080U
1852 #define I2C_CR1_START 0x00000100U
1853 #define I2C_CR1_STOP 0x00000200U
1854 #define I2C_CR1_ACK 0x00000400U
1855 #define I2C_CR1_POS 0x00000800U
1856 #define I2C_CR1_PEC 0x00001000U
1857 #define I2C_CR1_ALERT 0x00002000U
1858 #define I2C_CR1_SWRST 0x00008000U
1860 /******************* Bit definition for I2C_CR2 register ********************/
1861 #define I2C_CR2_FREQ 0x0000003FU
1862 #define I2C_CR2_FREQ_0 0x00000001U
1863 #define I2C_CR2_FREQ_1 0x00000002U
1864 #define I2C_CR2_FREQ_2 0x00000004U
1865 #define I2C_CR2_FREQ_3 0x00000008U
1866 #define I2C_CR2_FREQ_4 0x00000010U
1867 #define I2C_CR2_FREQ_5 0x00000020U
1869 #define I2C_CR2_ITERREN 0x00000100U
1870 #define I2C_CR2_ITEVTEN 0x00000200U
1871 #define I2C_CR2_ITBUFEN 0x00000400U
1872 #define I2C_CR2_DMAEN 0x00000800U
1873 #define I2C_CR2_LAST 0x00001000U
1875 /******************* Bit definition for I2C_OAR1 register *******************/
1876 #define I2C_OAR1_ADD1_7 0x000000FEU
1877 #define I2C_OAR1_ADD8_9 0x00000300U
1879 #define I2C_OAR1_ADD0 0x00000001U
1880 #define I2C_OAR1_ADD1 0x00000002U
1881 #define I2C_OAR1_ADD2 0x00000004U
1882 #define I2C_OAR1_ADD3 0x00000008U
1883 #define I2C_OAR1_ADD4 0x00000010U
1884 #define I2C_OAR1_ADD5 0x00000020U
1885 #define I2C_OAR1_ADD6 0x00000040U
1886 #define I2C_OAR1_ADD7 0x00000080U
1887 #define I2C_OAR1_ADD8 0x00000100U
1888 #define I2C_OAR1_ADD9 0x00000200U
1890 #define I2C_OAR1_ADDMODE 0x00008000U
1892 /******************* Bit definition for I2C_OAR2 register *******************/
1893 #define I2C_OAR2_ENDUAL 0x00000001U
1894 #define I2C_OAR2_ADD2 0x000000FEU
1896 /******************** Bit definition for I2C_DR register ********************/
1897 #define I2C_DR_DR 0x000000FFU
1899 /******************* Bit definition for I2C_SR1 register ********************/
1900 #define I2C_SR1_SB 0x00000001U
1901 #define I2C_SR1_ADDR 0x00000002U
1902 #define I2C_SR1_BTF 0x00000004U
1903 #define I2C_SR1_ADD10 0x00000008U
1904 #define I2C_SR1_STOPF 0x00000010U
1905 #define I2C_SR1_RXNE 0x00000040U
1906 #define I2C_SR1_TXE 0x00000080U
1907 #define I2C_SR1_BERR 0x00000100U
1908 #define I2C_SR1_ARLO 0x00000200U
1909 #define I2C_SR1_AF 0x00000400U
1910 #define I2C_SR1_OVR 0x00000800U
1911 #define I2C_SR1_PECERR 0x00001000U
1912 #define I2C_SR1_TIMEOUT 0x00004000U
1913 #define I2C_SR1_SMBALERT 0x00008000U
1915 /******************* Bit definition for I2C_SR2 register ********************/
1916 #define I2C_SR2_MSL 0x00000001U
1917 #define I2C_SR2_BUSY 0x00000002U
1918 #define I2C_SR2_TRA 0x00000004U
1919 #define I2C_SR2_GENCALL 0x00000010U
1920 #define I2C_SR2_SMBDEFAULT 0x00000020U
1921 #define I2C_SR2_SMBHOST 0x00000040U
1922 #define I2C_SR2_DUALF 0x00000080U
1923 #define I2C_SR2_PEC 0x0000FF00U
1925 /******************* Bit definition for I2C_CCR register ********************/
1926 #define I2C_CCR_CCR 0x00000FFFU
1927 #define I2C_CCR_DUTY 0x00004000U
1928 #define I2C_CCR_FS 0x00008000U
1930 /****************** Bit definition for I2C_TRISE register *******************/
1931 #define I2C_TRISE_TRISE 0x0000003FU
1933 /****************** Bit definition for I2C_FLTR register *******************/
1934 #define I2C_FLTR_DNF 0x0000000FU
1935 #define I2C_FLTR_ANOFF 0x00000010U
1937 /******************************************************************************/
1938 /* */
1939 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
1940 /* */
1941 /******************************************************************************/
1942 /******************* Bit definition for I2C_CR1 register *******************/
1943 #define FMPI2C_CR1_PE 0x00000001U
1944 #define FMPI2C_CR1_TXIE 0x00000002U
1945 #define FMPI2C_CR1_RXIE 0x00000004U
1946 #define FMPI2C_CR1_ADDRIE 0x00000008U
1947 #define FMPI2C_CR1_NACKIE 0x00000010U
1948 #define FMPI2C_CR1_STOPIE 0x00000020U
1949 #define FMPI2C_CR1_TCIE 0x00000040U
1950 #define FMPI2C_CR1_ERRIE 0x00000080U
1951 #define FMPI2C_CR1_DFN 0x00000F00U
1952 #define FMPI2C_CR1_ANFOFF 0x00001000U
1953 #define FMPI2C_CR1_TXDMAEN 0x00004000U
1954 #define FMPI2C_CR1_RXDMAEN 0x00008000U
1955 #define FMPI2C_CR1_SBC 0x00010000U
1956 #define FMPI2C_CR1_NOSTRETCH 0x00020000U
1957 #define FMPI2C_CR1_GCEN 0x00080000U
1958 #define FMPI2C_CR1_ALERTEN 0x00400000U
1959 #define FMPI2C_CR1_PECEN 0x00800000U
1961 /****************** Bit definition for I2C_CR2 register ********************/
1962 #define FMPI2C_CR2_SADD 0x000003FFU
1963 #define FMPI2C_CR2_RD_WRN 0x00000400U
1964 #define FMPI2C_CR2_ADD10 0x00000800U
1965 #define FMPI2C_CR2_HEAD10R 0x00001000U
1966 #define FMPI2C_CR2_START 0x00002000U
1967 #define FMPI2C_CR2_STOP 0x00004000U
1968 #define FMPI2C_CR2_NACK 0x00008000U
1969 #define FMPI2C_CR2_NBYTES 0x00FF0000U
1970 #define FMPI2C_CR2_RELOAD 0x01000000U
1971 #define FMPI2C_CR2_AUTOEND 0x02000000U
1972 #define FMPI2C_CR2_PECBYTE 0x04000000U
1974 /******************* Bit definition for I2C_OAR1 register ******************/
1975 #define FMPI2C_OAR1_OA1 0x000003FFU
1976 #define FMPI2C_OAR1_OA1MODE 0x00000400U
1977 #define FMPI2C_OAR1_OA1EN 0x00008000U
1979 /******************* Bit definition for I2C_OAR2 register ******************/
1980 #define FMPI2C_OAR2_OA2 0x000000FEU
1981 #define FMPI2C_OAR2_OA2MSK 0x00000700U
1982 #define FMPI2C_OAR2_OA2EN 0x00008000U
1984 /******************* Bit definition for I2C_TIMINGR register *******************/
1985 #define FMPI2C_TIMINGR_SCLL 0x000000FFU
1986 #define FMPI2C_TIMINGR_SCLH 0x0000FF00U
1987 #define FMPI2C_TIMINGR_SDADEL 0x000F0000U
1988 #define FMPI2C_TIMINGR_SCLDEL 0x00F00000U
1989 #define FMPI2C_TIMINGR_PRESC 0xF0000000U
1991 /******************* Bit definition for I2C_TIMEOUTR register *******************/
1992 #define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
1993 #define FMPI2C_TIMEOUTR_TIDLE 0x00001000U
1994 #define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U
1995 #define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
1996 #define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U
1998 /****************** Bit definition for I2C_ISR register *********************/
1999 #define FMPI2C_ISR_TXE 0x00000001U
2000 #define FMPI2C_ISR_TXIS 0x00000002U
2001 #define FMPI2C_ISR_RXNE 0x00000004U
2002 #define FMPI2C_ISR_ADDR 0x00000008U
2003 #define FMPI2C_ISR_NACKF 0x00000010U
2004 #define FMPI2C_ISR_STOPF 0x00000020U
2005 #define FMPI2C_ISR_TC 0x00000040U
2006 #define FMPI2C_ISR_TCR 0x00000080U
2007 #define FMPI2C_ISR_BERR 0x00000100U
2008 #define FMPI2C_ISR_ARLO 0x00000200U
2009 #define FMPI2C_ISR_OVR 0x00000400U
2010 #define FMPI2C_ISR_PECERR 0x00000800U
2011 #define FMPI2C_ISR_TIMEOUT 0x00001000U
2012 #define FMPI2C_ISR_ALERT 0x00002000U
2013 #define FMPI2C_ISR_BUSY 0x00008000U
2014 #define FMPI2C_ISR_DIR 0x00010000U
2015 #define FMPI2C_ISR_ADDCODE 0x00FE0000U
2017 /****************** Bit definition for I2C_ICR register *********************/
2018 #define FMPI2C_ICR_ADDRCF 0x00000008U
2019 #define FMPI2C_ICR_NACKCF 0x00000010U
2020 #define FMPI2C_ICR_STOPCF 0x00000020U
2021 #define FMPI2C_ICR_BERRCF 0x00000100U
2022 #define FMPI2C_ICR_ARLOCF 0x00000200U
2023 #define FMPI2C_ICR_OVRCF 0x00000400U
2024 #define FMPI2C_ICR_PECCF 0x00000800U
2025 #define FMPI2C_ICR_TIMOUTCF 0x00001000U
2026 #define FMPI2C_ICR_ALERTCF 0x00002000U
2028 /****************** Bit definition for I2C_PECR register *********************/
2029 #define FMPI2C_PECR_PEC 0x000000FFU
2031 /****************** Bit definition for I2C_RXDR register *********************/
2032 #define FMPI2C_RXDR_RXDATA 0x000000FFU
2034 /****************** Bit definition for I2C_TXDR register *********************/
2035 #define FMPI2C_TXDR_TXDATA 0x000000FFU
2037 /******************************************************************************/
2038 /* */
2039 /* Independent WATCHDOG */
2040 /* */
2041 /******************************************************************************/
2042 /******************* Bit definition for IWDG_KR register ********************/
2043 #define IWDG_KR_KEY 0xFFFFU
2045 /******************* Bit definition for IWDG_PR register ********************/
2046 #define IWDG_PR_PR 0x07U
2047 #define IWDG_PR_PR_0 0x01U
2048 #define IWDG_PR_PR_1 0x02U
2049 #define IWDG_PR_PR_2 0x04U
2051 /******************* Bit definition for IWDG_RLR register *******************/
2052 #define IWDG_RLR_RL 0x0FFFU
2054 /******************* Bit definition for IWDG_SR register ********************/
2055 #define IWDG_SR_PVU 0x01U
2056 #define IWDG_SR_RVU 0x02U
2059 /******************************************************************************/
2060 /* */
2061 /* Power Control */
2062 /* */
2063 /******************************************************************************/
2064 /******************** Bit definition for PWR_CR register ********************/
2065 #define PWR_CR_LPDS 0x00000001U
2066 #define PWR_CR_PDDS 0x00000002U
2067 #define PWR_CR_CWUF 0x00000004U
2068 #define PWR_CR_CSBF 0x00000008U
2069 #define PWR_CR_PVDE 0x00000010U
2071 #define PWR_CR_PLS 0x000000E0U
2072 #define PWR_CR_PLS_0 0x00000020U
2073 #define PWR_CR_PLS_1 0x00000040U
2074 #define PWR_CR_PLS_2 0x00000080U
2077 #define PWR_CR_PLS_LEV0 0x00000000U
2078 #define PWR_CR_PLS_LEV1 0x00000020U
2079 #define PWR_CR_PLS_LEV2 0x00000040U
2080 #define PWR_CR_PLS_LEV3 0x00000060U
2081 #define PWR_CR_PLS_LEV4 0x00000080U
2082 #define PWR_CR_PLS_LEV5 0x000000A0U
2083 #define PWR_CR_PLS_LEV6 0x000000C0U
2084 #define PWR_CR_PLS_LEV7 0x000000E0U
2086 #define PWR_CR_DBP 0x00000100U
2087 #define PWR_CR_FPDS 0x00000200U
2088 #define PWR_CR_LPLVDS 0x00000400U
2089 #define PWR_CR_MRLVDS 0x00000800U
2090 #define PWR_CR_ADCDC1 0x00002000U
2092 #define PWR_CR_VOS 0x0000C000U
2093 #define PWR_CR_VOS_0 0x00004000U
2094 #define PWR_CR_VOS_1 0x00008000U
2096 #define PWR_CR_FMSSR 0x00100000U
2097 #define PWR_CR_FISSR 0x00200000U
2098 /* Legacy define */
2099 #define PWR_CR_PMODE PWR_CR_VOS
2100 
2101 /******************* Bit definition for PWR_CSR register ********************/
2102 #define PWR_CSR_WUF 0x00000001U
2103 #define PWR_CSR_SBF 0x00000002U
2104 #define PWR_CSR_PVDO 0x00000004U
2105 #define PWR_CSR_BRR 0x00000008U
2106 #define PWR_CSR_EWUP 0x00000100U
2107 #define PWR_CSR_BRE 0x00000200U
2108 #define PWR_CSR_VOSRDY 0x00004000U
2110 /* Legacy define */
2111 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
2112 
2113 /******************************************************************************/
2114 /* */
2115 /* Reset and Clock Control */
2116 /* */
2117 /******************************************************************************/
2118 /******************** Bit definition for RCC_CR register ********************/
2119 #define RCC_CR_HSION 0x00000001U
2120 #define RCC_CR_HSIRDY 0x00000002U
2121 
2122 #define RCC_CR_HSITRIM 0x000000F8U
2123 #define RCC_CR_HSITRIM_0 0x00000008U
2124 #define RCC_CR_HSITRIM_1 0x00000010U
2125 #define RCC_CR_HSITRIM_2 0x00000020U
2126 #define RCC_CR_HSITRIM_3 0x00000040U
2127 #define RCC_CR_HSITRIM_4 0x00000080U
2129 #define RCC_CR_HSICAL 0x0000FF00U
2130 #define RCC_CR_HSICAL_0 0x00000100U
2131 #define RCC_CR_HSICAL_1 0x00000200U
2132 #define RCC_CR_HSICAL_2 0x00000400U
2133 #define RCC_CR_HSICAL_3 0x00000800U
2134 #define RCC_CR_HSICAL_4 0x00001000U
2135 #define RCC_CR_HSICAL_5 0x00002000U
2136 #define RCC_CR_HSICAL_6 0x00004000U
2137 #define RCC_CR_HSICAL_7 0x00008000U
2139 #define RCC_CR_HSEON 0x00010000U
2140 #define RCC_CR_HSERDY 0x00020000U
2141 #define RCC_CR_HSEBYP 0x00040000U
2142 #define RCC_CR_CSSON 0x00080000U
2143 #define RCC_CR_PLLON 0x01000000U
2144 #define RCC_CR_PLLRDY 0x02000000U
2145 
2146 /******************** Bit definition for RCC_PLLCFGR register ***************/
2147 #define RCC_PLLCFGR_PLLM 0x0000003FU
2148 #define RCC_PLLCFGR_PLLM_0 0x00000001U
2149 #define RCC_PLLCFGR_PLLM_1 0x00000002U
2150 #define RCC_PLLCFGR_PLLM_2 0x00000004U
2151 #define RCC_PLLCFGR_PLLM_3 0x00000008U
2152 #define RCC_PLLCFGR_PLLM_4 0x00000010U
2153 #define RCC_PLLCFGR_PLLM_5 0x00000020U
2154 
2155 #define RCC_PLLCFGR_PLLN 0x00007FC0U
2156 #define RCC_PLLCFGR_PLLN_0 0x00000040U
2157 #define RCC_PLLCFGR_PLLN_1 0x00000080U
2158 #define RCC_PLLCFGR_PLLN_2 0x00000100U
2159 #define RCC_PLLCFGR_PLLN_3 0x00000200U
2160 #define RCC_PLLCFGR_PLLN_4 0x00000400U
2161 #define RCC_PLLCFGR_PLLN_5 0x00000800U
2162 #define RCC_PLLCFGR_PLLN_6 0x00001000U
2163 #define RCC_PLLCFGR_PLLN_7 0x00002000U
2164 #define RCC_PLLCFGR_PLLN_8 0x00004000U
2165 
2166 #define RCC_PLLCFGR_PLLP 0x00030000U
2167 #define RCC_PLLCFGR_PLLP_0 0x00010000U
2168 #define RCC_PLLCFGR_PLLP_1 0x00020000U
2169 
2170 #define RCC_PLLCFGR_PLLSRC 0x00400000U
2171 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
2172 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
2173 
2174 #define RCC_PLLCFGR_PLLQ 0x0F000000U
2175 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
2176 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
2177 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
2178 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
2179 
2180 #define RCC_PLLCFGR_PLLR 0x70000000U
2181 #define RCC_PLLCFGR_PLLR_0 0x10000000U
2182 #define RCC_PLLCFGR_PLLR_1 0x20000000U
2183 #define RCC_PLLCFGR_PLLR_2 0x40000000U
2184 /******************** Bit definition for RCC_CFGR register ******************/
2186 #define RCC_CFGR_SW 0x00000003U
2187 #define RCC_CFGR_SW_0 0x00000001U
2188 #define RCC_CFGR_SW_1 0x00000002U
2190 #define RCC_CFGR_SW_HSI 0x00000000U
2191 #define RCC_CFGR_SW_HSE 0x00000001U
2192 #define RCC_CFGR_SW_PLL 0x00000002U
2195 #define RCC_CFGR_SWS 0x0000000CU
2196 #define RCC_CFGR_SWS_0 0x00000004U
2197 #define RCC_CFGR_SWS_1 0x00000008U
2199 #define RCC_CFGR_SWS_HSI 0x00000000U
2200 #define RCC_CFGR_SWS_HSE 0x00000004U
2201 #define RCC_CFGR_SWS_PLL 0x00000008U
2204 #define RCC_CFGR_HPRE 0x000000F0U
2205 #define RCC_CFGR_HPRE_0 0x00000010U
2206 #define RCC_CFGR_HPRE_1 0x00000020U
2207 #define RCC_CFGR_HPRE_2 0x00000040U
2208 #define RCC_CFGR_HPRE_3 0x00000080U
2210 #define RCC_CFGR_HPRE_DIV1 0x00000000U
2211 #define RCC_CFGR_HPRE_DIV2 0x00000080U
2212 #define RCC_CFGR_HPRE_DIV4 0x00000090U
2213 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
2214 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
2215 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
2216 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
2217 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
2218 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
2221 #define RCC_CFGR_MCO1EN 0x00000100U
2224 #define RCC_CFGR_PPRE1 0x00001C00U
2225 #define RCC_CFGR_PPRE1_0 0x00000400U
2226 #define RCC_CFGR_PPRE1_1 0x00000800U
2227 #define RCC_CFGR_PPRE1_2 0x00001000U
2229 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
2230 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
2231 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
2232 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
2233 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
2236 #define RCC_CFGR_PPRE2 0x0000E000U
2237 #define RCC_CFGR_PPRE2_0 0x00002000U
2238 #define RCC_CFGR_PPRE2_1 0x00004000U
2239 #define RCC_CFGR_PPRE2_2 0x00008000U
2241 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
2242 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
2243 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
2244 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
2245 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
2248 #define RCC_CFGR_RTCPRE 0x001F0000U
2249 #define RCC_CFGR_RTCPRE_0 0x00010000U
2250 #define RCC_CFGR_RTCPRE_1 0x00020000U
2251 #define RCC_CFGR_RTCPRE_2 0x00040000U
2252 #define RCC_CFGR_RTCPRE_3 0x00080000U
2253 #define RCC_CFGR_RTCPRE_4 0x00100000U
2254 
2256 #define RCC_CFGR_MCO1 0x00600000U
2257 #define RCC_CFGR_MCO1_0 0x00200000U
2258 #define RCC_CFGR_MCO1_1 0x00400000U
2259 
2260 #define RCC_CFGR_MCO1PRE 0x07000000U
2261 #define RCC_CFGR_MCO1PRE_0 0x01000000U
2262 #define RCC_CFGR_MCO1PRE_1 0x02000000U
2263 #define RCC_CFGR_MCO1PRE_2 0x04000000U
2264 
2265 #define RCC_CFGR_MCO2PRE 0x38000000U
2266 #define RCC_CFGR_MCO2PRE_0 0x08000000U
2267 #define RCC_CFGR_MCO2PRE_1 0x10000000U
2268 #define RCC_CFGR_MCO2PRE_2 0x20000000U
2269 
2270 #define RCC_CFGR_MCO2 0xC0000000U
2271 #define RCC_CFGR_MCO2_0 0x40000000U
2272 #define RCC_CFGR_MCO2_1 0x80000000U
2273 
2274 /******************** Bit definition for RCC_CIR register *******************/
2275 #define RCC_CIR_LSIRDYF 0x00000001U
2276 #define RCC_CIR_LSERDYF 0x00000002U
2277 #define RCC_CIR_HSIRDYF 0x00000004U
2278 #define RCC_CIR_HSERDYF 0x00000008U
2279 #define RCC_CIR_PLLRDYF 0x00000010U
2280 
2281 #define RCC_CIR_CSSF 0x00000080U
2282 #define RCC_CIR_LSIRDYIE 0x00000100U
2283 #define RCC_CIR_LSERDYIE 0x00000200U
2284 #define RCC_CIR_HSIRDYIE 0x00000400U
2285 #define RCC_CIR_HSERDYIE 0x00000800U
2286 #define RCC_CIR_PLLRDYIE 0x00001000U
2287 
2288 #define RCC_CIR_LSIRDYC 0x00010000U
2289 #define RCC_CIR_LSERDYC 0x00020000U
2290 #define RCC_CIR_HSIRDYC 0x00040000U
2291 #define RCC_CIR_HSERDYC 0x00080000U
2292 #define RCC_CIR_PLLRDYC 0x00100000U
2293 
2294 #define RCC_CIR_CSSC 0x00800000U
2295 
2296 /******************** Bit definition for RCC_AHB1RSTR register **************/
2297 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
2298 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
2299 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
2300 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
2301 #define RCC_AHB1RSTR_CRCRST 0x00001000U
2302 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
2303 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
2304 #define RCC_AHB1RSTR_RNGRST 0x80000000U
2305 
2306 /******************** Bit definition for RCC_APB1RSTR register **************/
2307 #define RCC_APB1RSTR_TIM5RST 0x00000008U
2308 #define RCC_APB1RSTR_TIM6RST 0x00000010U
2309 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
2310 #define RCC_APB1RSTR_WWDGRST 0x00000800U
2311 #define RCC_APB1RSTR_USART2RST 0x00020000U
2312 #define RCC_APB1RSTR_I2C1RST 0x00200000U
2313 #define RCC_APB1RSTR_I2C2RST 0x00400000U
2314 #define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
2315 #define RCC_APB1RSTR_PWRRST 0x10000000U
2316 #define RCC_APB1RSTR_DACRST 0x20000000U
2317 
2318 /******************** Bit definition for RCC_APB2RSTR register **************/
2319 #define RCC_APB2RSTR_TIM1RST 0x00000001U
2320 #define RCC_APB2RSTR_USART1RST 0x00000010U
2321 #define RCC_APB2RSTR_ADCRST 0x00000100U
2322 #define RCC_APB2RSTR_SPI1RST 0x00001000U
2323 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
2324 #define RCC_APB2RSTR_TIM9RST 0x00010000U
2325 #define RCC_APB2RSTR_TIM11RST 0x00040000U
2326 
2327 /******************** Bit definition for RCC_AHB1ENR register ***************/
2328 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
2329 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
2330 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
2331 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
2332 #define RCC_AHB1ENR_CRCEN 0x00001000U
2333 #define RCC_AHB1ENR_DMA1EN 0x00200000U
2334 #define RCC_AHB1ENR_DMA2EN 0x00400000U
2335 #define RCC_AHB1ENR_RNGEN 0x80000000U
2336 
2337 /******************** Bit definition for RCC_APB1ENR register ***************/
2338 #define RCC_APB1ENR_TIM5EN 0x00000008U
2339 #define RCC_APB1ENR_TIM6EN 0x00000010U
2340 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
2341 #define RCC_APB1ENR_RTCAPBEN 0x00000400U
2342 #define RCC_APB1ENR_WWDGEN 0x00000800U
2343 #define RCC_APB1ENR_USART2EN 0x00020000U
2344 #define RCC_APB1ENR_I2C1EN 0x00200000U
2345 #define RCC_APB1ENR_I2C2EN 0x00400000U
2346 #define RCC_APB1ENR_FMPI2C1EN 0x01000000U
2347 #define RCC_APB1ENR_PWREN 0x10000000U
2348 #define RCC_APB1ENR_DACEN 0x20000000U
2349 
2350 /******************** Bit definition for RCC_APB2ENR register ***************/
2351 #define RCC_APB2ENR_TIM1EN 0x00000001U
2352 #define RCC_APB2ENR_USART1EN 0x00000010U
2353 #define RCC_APB2ENR_ADC1EN 0x00000100U
2354 #define RCC_APB2ENR_SPI1EN 0x00001000U
2355 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
2356 #define RCC_APB2ENR_EXTITEN 0x00008000U
2357 #define RCC_APB2ENR_TIM9EN 0x00010000U
2358 #define RCC_APB2ENR_TIM11EN 0x00040000U
2359 
2360 /******************** Bit definition for RCC_AHB1LPENR register *************/
2361 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
2362 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
2363 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
2364 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
2365 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
2366 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
2367 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
2368 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
2369 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
2370 #define RCC_AHB1LPENR_RNGLPEN 0x80000000U
2371 
2372 /******************** Bit definition for RCC_APB1LPENR register *************/
2373 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
2374 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
2375 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
2376 #define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
2377 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
2378 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
2379 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
2380 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
2381 #define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
2382 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
2383 #define RCC_APB1LPENR_DACLPEN 0x20000000U
2384 
2385 /******************** Bit definition for RCC_APB2LPENR register *************/
2386 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
2387 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
2388 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
2389 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
2390 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
2391 #define RCC_APB2LPENR_EXTITLPEN 0x00008000U
2392 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
2393 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
2394 
2395 /******************** Bit definition for RCC_BDCR register ******************/
2396 #define RCC_BDCR_LSEON 0x00000001U
2397 #define RCC_BDCR_LSERDY 0x00000002U
2398 #define RCC_BDCR_LSEBYP 0x00000004U
2399 #define RCC_BDCR_LSEMOD 0x00000008U
2400 
2401 #define RCC_BDCR_RTCSEL 0x00000300U
2402 #define RCC_BDCR_RTCSEL_0 0x00000100U
2403 #define RCC_BDCR_RTCSEL_1 0x00000200U
2404 
2405 #define RCC_BDCR_RTCEN 0x00008000U
2406 #define RCC_BDCR_BDRST 0x00010000U
2407 
2408 /******************** Bit definition for RCC_CSR register *******************/
2409 #define RCC_CSR_LSION 0x00000001U
2410 #define RCC_CSR_LSIRDY 0x00000002U
2411 #define RCC_CSR_RMVF 0x01000000U
2412 #define RCC_CSR_BORRSTF 0x02000000U
2413 #define RCC_CSR_PADRSTF 0x04000000U
2414 #define RCC_CSR_PORRSTF 0x08000000U
2415 #define RCC_CSR_SFTRSTF 0x10000000U
2416 #define RCC_CSR_WDGRSTF 0x20000000U
2417 #define RCC_CSR_WWDGRSTF 0x40000000U
2418 #define RCC_CSR_LPWRRSTF 0x80000000U
2419 
2420 /******************** Bit definition for RCC_SSCGR register *****************/
2421 #define RCC_SSCGR_MODPER 0x00001FFFU
2422 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
2423 #define RCC_SSCGR_SPREADSEL 0x40000000U
2424 #define RCC_SSCGR_SSCGEN 0x80000000U
2425 
2426 /******************** Bit definition for RCC_DCKCFGR register ***************/
2427 #define RCC_DCKCFGR_TIMPRE 0x01000000U
2428 #define RCC_DCKCFGR_I2SSRC 0x06000000U
2429 #define RCC_DCKCFGR_I2SSRC_0 0x02000000U
2430 #define RCC_DCKCFGR_I2SSRC_1 0x04000000U
2431 
2432 /******************** Bit definition for RCC_CKGATENR register **************/
2433 #define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
2434 #define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
2435 #define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
2436 #define RCC_CKGATENR_SPARE_CKEN 0x00000008U
2437 #define RCC_CKGATENR_SRAM_CKEN 0x00000010U
2438 #define RCC_CKGATENR_FLITF_CKEN 0x00000020U
2439 #define RCC_CKGATENR_RCC_CKEN 0x00000040U
2440 
2441 /******************** Bit definition for RCC_DCKCFGR2 register **************/
2442 #define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
2443 #define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
2444 #define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
2445 #define RCC_DCKCFGR2_LPTIM1SEL 0xC0000000U
2446 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x40000000U
2447 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x80000000U
2448 
2449 /******************************************************************************/
2450 /* */
2451 /* RNG */
2452 /* */
2453 /******************************************************************************/
2454 /******************** Bits definition for RNG_CR register *******************/
2455 #define RNG_CR_RNGEN 0x00000004U
2456 #define RNG_CR_IE 0x00000008U
2457 
2458 /******************** Bits definition for RNG_SR register *******************/
2459 #define RNG_SR_DRDY 0x00000001U
2460 #define RNG_SR_CECS 0x00000002U
2461 #define RNG_SR_SECS 0x00000004U
2462 #define RNG_SR_CEIS 0x00000020U
2463 #define RNG_SR_SEIS 0x00000040U
2464 
2465 /******************************************************************************/
2466 /* */
2467 /* Real-Time Clock (RTC) */
2468 /* */
2469 /******************************************************************************/
2470 /******************** Bits definition for RTC_TR register *******************/
2471 #define RTC_TR_PM 0x00400000U
2472 #define RTC_TR_HT 0x00300000U
2473 #define RTC_TR_HT_0 0x00100000U
2474 #define RTC_TR_HT_1 0x00200000U
2475 #define RTC_TR_HU 0x000F0000U
2476 #define RTC_TR_HU_0 0x00010000U
2477 #define RTC_TR_HU_1 0x00020000U
2478 #define RTC_TR_HU_2 0x00040000U
2479 #define RTC_TR_HU_3 0x00080000U
2480 #define RTC_TR_MNT 0x00007000U
2481 #define RTC_TR_MNT_0 0x00001000U
2482 #define RTC_TR_MNT_1 0x00002000U
2483 #define RTC_TR_MNT_2 0x00004000U
2484 #define RTC_TR_MNU 0x00000F00U
2485 #define RTC_TR_MNU_0 0x00000100U
2486 #define RTC_TR_MNU_1 0x00000200U
2487 #define RTC_TR_MNU_2 0x00000400U
2488 #define RTC_TR_MNU_3 0x00000800U
2489 #define RTC_TR_ST 0x00000070U
2490 #define RTC_TR_ST_0 0x00000010U
2491 #define RTC_TR_ST_1 0x00000020U
2492 #define RTC_TR_ST_2 0x00000040U
2493 #define RTC_TR_SU 0x0000000FU
2494 #define RTC_TR_SU_0 0x00000001U
2495 #define RTC_TR_SU_1 0x00000002U
2496 #define RTC_TR_SU_2 0x00000004U
2497 #define RTC_TR_SU_3 0x00000008U
2498 
2499 /******************** Bits definition for RTC_DR register *******************/
2500 #define RTC_DR_YT 0x00F00000U
2501 #define RTC_DR_YT_0 0x00100000U
2502 #define RTC_DR_YT_1 0x00200000U
2503 #define RTC_DR_YT_2 0x00400000U
2504 #define RTC_DR_YT_3 0x00800000U
2505 #define RTC_DR_YU 0x000F0000U
2506 #define RTC_DR_YU_0 0x00010000U
2507 #define RTC_DR_YU_1 0x00020000U
2508 #define RTC_DR_YU_2 0x00040000U
2509 #define RTC_DR_YU_3 0x00080000U
2510 #define RTC_DR_WDU 0x0000E000U
2511 #define RTC_DR_WDU_0 0x00002000U
2512 #define RTC_DR_WDU_1 0x00004000U
2513 #define RTC_DR_WDU_2 0x00008000U
2514 #define RTC_DR_MT 0x00001000U
2515 #define RTC_DR_MU 0x00000F00U
2516 #define RTC_DR_MU_0 0x00000100U
2517 #define RTC_DR_MU_1 0x00000200U
2518 #define RTC_DR_MU_2 0x00000400U
2519 #define RTC_DR_MU_3 0x00000800U
2520 #define RTC_DR_DT 0x00000030U
2521 #define RTC_DR_DT_0 0x00000010U
2522 #define RTC_DR_DT_1 0x00000020U
2523 #define RTC_DR_DU 0x0000000FU
2524 #define RTC_DR_DU_0 0x00000001U
2525 #define RTC_DR_DU_1 0x00000002U
2526 #define RTC_DR_DU_2 0x00000004U
2527 #define RTC_DR_DU_3 0x00000008U
2528 
2529 /******************** Bits definition for RTC_CR register *******************/
2530 #define RTC_CR_COE 0x00800000U
2531 #define RTC_CR_OSEL 0x00600000U
2532 #define RTC_CR_OSEL_0 0x00200000U
2533 #define RTC_CR_OSEL_1 0x00400000U
2534 #define RTC_CR_POL 0x00100000U
2535 #define RTC_CR_COSEL 0x00080000U
2536 #define RTC_CR_BCK 0x00040000U
2537 #define RTC_CR_SUB1H 0x00020000U
2538 #define RTC_CR_ADD1H 0x00010000U
2539 #define RTC_CR_TSIE 0x00008000U
2540 #define RTC_CR_WUTIE 0x00004000U
2541 #define RTC_CR_ALRBIE 0x00002000U
2542 #define RTC_CR_ALRAIE 0x00001000U
2543 #define RTC_CR_TSE 0x00000800U
2544 #define RTC_CR_WUTE 0x00000400U
2545 #define RTC_CR_ALRBE 0x00000200U
2546 #define RTC_CR_ALRAE 0x00000100U
2547 #define RTC_CR_DCE 0x00000080U
2548 #define RTC_CR_FMT 0x00000040U
2549 #define RTC_CR_BYPSHAD 0x00000020U
2550 #define RTC_CR_REFCKON 0x00000010U
2551 #define RTC_CR_TSEDGE 0x00000008U
2552 #define RTC_CR_WUCKSEL 0x00000007U
2553 #define RTC_CR_WUCKSEL_0 0x00000001U
2554 #define RTC_CR_WUCKSEL_1 0x00000002U
2555 #define RTC_CR_WUCKSEL_2 0x00000004U
2556 
2557 /******************** Bits definition for RTC_ISR register ******************/
2558 #define RTC_ISR_RECALPF 0x00010000U
2559 #define RTC_ISR_TAMP1F 0x00002000U
2560 #define RTC_ISR_TAMP2F 0x00004000U
2561 #define RTC_ISR_TSOVF 0x00001000U
2562 #define RTC_ISR_TSF 0x00000800U
2563 #define RTC_ISR_WUTF 0x00000400U
2564 #define RTC_ISR_ALRBF 0x00000200U
2565 #define RTC_ISR_ALRAF 0x00000100U
2566 #define RTC_ISR_INIT 0x00000080U
2567 #define RTC_ISR_INITF 0x00000040U
2568 #define RTC_ISR_RSF 0x00000020U
2569 #define RTC_ISR_INITS 0x00000010U
2570 #define RTC_ISR_SHPF 0x00000008U
2571 #define RTC_ISR_WUTWF 0x00000004U
2572 #define RTC_ISR_ALRBWF 0x00000002U
2573 #define RTC_ISR_ALRAWF 0x00000001U
2574 
2575 /******************** Bits definition for RTC_PRER register *****************/
2576 #define RTC_PRER_PREDIV_A 0x007F0000U
2577 #define RTC_PRER_PREDIV_S 0x00007FFFU
2578 
2579 /******************** Bits definition for RTC_WUTR register *****************/
2580 #define RTC_WUTR_WUT 0x0000FFFFU
2581 
2582 /******************** Bits definition for RTC_CALIBR register ***************/
2583 #define RTC_CALIBR_DCS 0x00000080U
2584 #define RTC_CALIBR_DC 0x0000001FU
2585 
2586 /******************** Bits definition for RTC_ALRMAR register ***************/
2587 #define RTC_ALRMAR_MSK4 0x80000000U
2588 #define RTC_ALRMAR_WDSEL 0x40000000U
2589 #define RTC_ALRMAR_DT 0x30000000U
2590 #define RTC_ALRMAR_DT_0 0x10000000U
2591 #define RTC_ALRMAR_DT_1 0x20000000U
2592 #define RTC_ALRMAR_DU 0x0F000000U
2593 #define RTC_ALRMAR_DU_0 0x01000000U
2594 #define RTC_ALRMAR_DU_1 0x02000000U
2595 #define RTC_ALRMAR_DU_2 0x04000000U
2596 #define RTC_ALRMAR_DU_3 0x08000000U
2597 #define RTC_ALRMAR_MSK3 0x00800000U
2598 #define RTC_ALRMAR_PM 0x00400000U
2599 #define RTC_ALRMAR_HT 0x00300000U
2600 #define RTC_ALRMAR_HT_0 0x00100000U
2601 #define RTC_ALRMAR_HT_1 0x00200000U
2602 #define RTC_ALRMAR_HU 0x000F0000U
2603 #define RTC_ALRMAR_HU_0 0x00010000U
2604 #define RTC_ALRMAR_HU_1 0x00020000U
2605 #define RTC_ALRMAR_HU_2 0x00040000U
2606 #define RTC_ALRMAR_HU_3 0x00080000U
2607 #define RTC_ALRMAR_MSK2 0x00008000U
2608 #define RTC_ALRMAR_MNT 0x00007000U
2609 #define RTC_ALRMAR_MNT_0 0x00001000U
2610 #define RTC_ALRMAR_MNT_1 0x00002000U
2611 #define RTC_ALRMAR_MNT_2 0x00004000U
2612 #define RTC_ALRMAR_MNU 0x00000F00U
2613 #define RTC_ALRMAR_MNU_0 0x00000100U
2614 #define RTC_ALRMAR_MNU_1 0x00000200U
2615 #define RTC_ALRMAR_MNU_2 0x00000400U
2616 #define RTC_ALRMAR_MNU_3 0x00000800U
2617 #define RTC_ALRMAR_MSK1 0x00000080U
2618 #define RTC_ALRMAR_ST 0x00000070U
2619 #define RTC_ALRMAR_ST_0 0x00000010U
2620 #define RTC_ALRMAR_ST_1 0x00000020U
2621 #define RTC_ALRMAR_ST_2 0x00000040U
2622 #define RTC_ALRMAR_SU 0x0000000FU
2623 #define RTC_ALRMAR_SU_0 0x00000001U
2624 #define RTC_ALRMAR_SU_1 0x00000002U
2625 #define RTC_ALRMAR_SU_2 0x00000004U
2626 #define RTC_ALRMAR_SU_3 0x00000008U
2627 
2628 /******************** Bits definition for RTC_ALRMBR register ***************/
2629 #define RTC_ALRMBR_MSK4 0x80000000U
2630 #define RTC_ALRMBR_WDSEL 0x40000000U
2631 #define RTC_ALRMBR_DT 0x30000000U
2632 #define RTC_ALRMBR_DT_0 0x10000000U
2633 #define RTC_ALRMBR_DT_1 0x20000000U
2634 #define RTC_ALRMBR_DU 0x0F000000U
2635 #define RTC_ALRMBR_DU_0 0x01000000U
2636 #define RTC_ALRMBR_DU_1 0x02000000U
2637 #define RTC_ALRMBR_DU_2 0x04000000U
2638 #define RTC_ALRMBR_DU_3 0x08000000U
2639 #define RTC_ALRMBR_MSK3 0x00800000U
2640 #define RTC_ALRMBR_PM 0x00400000U
2641 #define RTC_ALRMBR_HT 0x00300000U
2642 #define RTC_ALRMBR_HT_0 0x00100000U
2643 #define RTC_ALRMBR_HT_1 0x00200000U
2644 #define RTC_ALRMBR_HU 0x000F0000U
2645 #define RTC_ALRMBR_HU_0 0x00010000U
2646 #define RTC_ALRMBR_HU_1 0x00020000U
2647 #define RTC_ALRMBR_HU_2 0x00040000U
2648 #define RTC_ALRMBR_HU_3 0x00080000U
2649 #define RTC_ALRMBR_MSK2 0x00008000U
2650 #define RTC_ALRMBR_MNT 0x00007000U
2651 #define RTC_ALRMBR_MNT_0 0x00001000U
2652 #define RTC_ALRMBR_MNT_1 0x00002000U
2653 #define RTC_ALRMBR_MNT_2 0x00004000U
2654 #define RTC_ALRMBR_MNU 0x00000F00U
2655 #define RTC_ALRMBR_MNU_0 0x00000100U
2656 #define RTC_ALRMBR_MNU_1 0x00000200U
2657 #define RTC_ALRMBR_MNU_2 0x00000400U
2658 #define RTC_ALRMBR_MNU_3 0x00000800U
2659 #define RTC_ALRMBR_MSK1 0x00000080U
2660 #define RTC_ALRMBR_ST 0x00000070U
2661 #define RTC_ALRMBR_ST_0 0x00000010U
2662 #define RTC_ALRMBR_ST_1 0x00000020U
2663 #define RTC_ALRMBR_ST_2 0x00000040U
2664 #define RTC_ALRMBR_SU 0x0000000FU
2665 #define RTC_ALRMBR_SU_0 0x00000001U
2666 #define RTC_ALRMBR_SU_1 0x00000002U
2667 #define RTC_ALRMBR_SU_2 0x00000004U
2668 #define RTC_ALRMBR_SU_3 0x00000008U
2669 
2670 /******************** Bits definition for RTC_WPR register ******************/
2671 #define RTC_WPR_KEY 0x000000FFU
2672 
2673 /******************** Bits definition for RTC_SSR register ******************/
2674 #define RTC_SSR_SS 0x0000FFFFU
2675 
2676 /******************** Bits definition for RTC_SHIFTR register ***************/
2677 #define RTC_SHIFTR_SUBFS 0x00007FFFU
2678 #define RTC_SHIFTR_ADD1S 0x80000000U
2679 
2680 /******************** Bits definition for RTC_TSTR register *****************/
2681 #define RTC_TSTR_PM 0x00400000U
2682 #define RTC_TSTR_HT 0x00300000U
2683 #define RTC_TSTR_HT_0 0x00100000U
2684 #define RTC_TSTR_HT_1 0x00200000U
2685 #define RTC_TSTR_HU 0x000F0000U
2686 #define RTC_TSTR_HU_0 0x00010000U
2687 #define RTC_TSTR_HU_1 0x00020000U
2688 #define RTC_TSTR_HU_2 0x00040000U
2689 #define RTC_TSTR_HU_3 0x00080000U
2690 #define RTC_TSTR_MNT 0x00007000U
2691 #define RTC_TSTR_MNT_0 0x00001000U
2692 #define RTC_TSTR_MNT_1 0x00002000U
2693 #define RTC_TSTR_MNT_2 0x00004000U
2694 #define RTC_TSTR_MNU 0x00000F00U
2695 #define RTC_TSTR_MNU_0 0x00000100U
2696 #define RTC_TSTR_MNU_1 0x00000200U
2697 #define RTC_TSTR_MNU_2 0x00000400U
2698 #define RTC_TSTR_MNU_3 0x00000800U
2699 #define RTC_TSTR_ST 0x00000070U
2700 #define RTC_TSTR_ST_0 0x00000010U
2701 #define RTC_TSTR_ST_1 0x00000020U
2702 #define RTC_TSTR_ST_2 0x00000040U
2703 #define RTC_TSTR_SU 0x0000000FU
2704 #define RTC_TSTR_SU_0 0x00000001U
2705 #define RTC_TSTR_SU_1 0x00000002U
2706 #define RTC_TSTR_SU_2 0x00000004U
2707 #define RTC_TSTR_SU_3 0x00000008U
2708 
2709 /******************** Bits definition for RTC_TSDR register *****************/
2710 #define RTC_TSDR_WDU 0x0000E000U
2711 #define RTC_TSDR_WDU_0 0x00002000U
2712 #define RTC_TSDR_WDU_1 0x00004000U
2713 #define RTC_TSDR_WDU_2 0x00008000U
2714 #define RTC_TSDR_MT 0x00001000U
2715 #define RTC_TSDR_MU 0x00000F00U
2716 #define RTC_TSDR_MU_0 0x00000100U
2717 #define RTC_TSDR_MU_1 0x00000200U
2718 #define RTC_TSDR_MU_2 0x00000400U
2719 #define RTC_TSDR_MU_3 0x00000800U
2720 #define RTC_TSDR_DT 0x00000030U
2721 #define RTC_TSDR_DT_0 0x00000010U
2722 #define RTC_TSDR_DT_1 0x00000020U
2723 #define RTC_TSDR_DU 0x0000000FU
2724 #define RTC_TSDR_DU_0 0x00000001U
2725 #define RTC_TSDR_DU_1 0x00000002U
2726 #define RTC_TSDR_DU_2 0x00000004U
2727 #define RTC_TSDR_DU_3 0x00000008U
2728 
2729 /******************** Bits definition for RTC_TSSSR register ****************/
2730 #define RTC_TSSSR_SS 0x0000FFFFU
2731 
2732 /******************** Bits definition for RTC_CAL register *****************/
2733 #define RTC_CALR_CALP 0x00008000U
2734 #define RTC_CALR_CALW8 0x00004000U
2735 #define RTC_CALR_CALW16 0x00002000U
2736 #define RTC_CALR_CALM 0x000001FFU
2737 #define RTC_CALR_CALM_0 0x00000001U
2738 #define RTC_CALR_CALM_1 0x00000002U
2739 #define RTC_CALR_CALM_2 0x00000004U
2740 #define RTC_CALR_CALM_3 0x00000008U
2741 #define RTC_CALR_CALM_4 0x00000010U
2742 #define RTC_CALR_CALM_5 0x00000020U
2743 #define RTC_CALR_CALM_6 0x00000040U
2744 #define RTC_CALR_CALM_7 0x00000080U
2745 #define RTC_CALR_CALM_8 0x00000100U
2746 
2747 /******************** Bits definition for RTC_TAFCR register ****************/
2748 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
2749 #define RTC_TAFCR_TSINSEL 0x00020000U
2750 #define RTC_TAFCR_TAMPINSEL 0x00010000U
2751 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
2752 #define RTC_TAFCR_TAMPPRCH 0x00006000U
2753 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
2754 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
2755 #define RTC_TAFCR_TAMPFLT 0x00001800U
2756 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
2757 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
2758 #define RTC_TAFCR_TAMPFREQ 0x00000700U
2759 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
2760 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
2761 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
2762 #define RTC_TAFCR_TAMPTS 0x00000080U
2763 #define RTC_TAFCR_TAMP2TRG 0x00000010U
2764 #define RTC_TAFCR_TAMP2E 0x00000008U
2765 #define RTC_TAFCR_TAMPIE 0x00000004U
2766 #define RTC_TAFCR_TAMP1TRG 0x00000002U
2767 #define RTC_TAFCR_TAMP1E 0x00000001U
2768 
2769 /******************** Bits definition for RTC_ALRMASSR register *************/
2770 #define RTC_ALRMASSR_MASKSS 0x0F000000U
2771 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
2772 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
2773 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
2774 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
2775 #define RTC_ALRMASSR_SS 0x00007FFFU
2776 
2777 /******************** Bits definition for RTC_ALRMBSSR register *************/
2778 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
2779 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
2780 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
2781 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
2782 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
2783 #define RTC_ALRMBSSR_SS 0x00007FFFU
2784 
2785 /******************** Bits definition for RTC_BKP0R register ****************/
2786 #define RTC_BKP0R 0xFFFFFFFFU
2787 
2788 /******************** Bits definition for RTC_BKP1R register ****************/
2789 #define RTC_BKP1R 0xFFFFFFFFU
2790 
2791 /******************** Bits definition for RTC_BKP2R register ****************/
2792 #define RTC_BKP2R 0xFFFFFFFFU
2793 
2794 /******************** Bits definition for RTC_BKP3R register ****************/
2795 #define RTC_BKP3R 0xFFFFFFFFU
2796 
2797 /******************** Bits definition for RTC_BKP4R register ****************/
2798 #define RTC_BKP4R 0xFFFFFFFFU
2799 
2800 /******************** Bits definition for RTC_BKP5R register ****************/
2801 #define RTC_BKP5R 0xFFFFFFFFU
2802 
2803 /******************** Bits definition for RTC_BKP6R register ****************/
2804 #define RTC_BKP6R 0xFFFFFFFFU
2805 
2806 /******************** Bits definition for RTC_BKP7R register ****************/
2807 #define RTC_BKP7R 0xFFFFFFFFU
2808 
2809 /******************** Bits definition for RTC_BKP8R register ****************/
2810 #define RTC_BKP8R 0xFFFFFFFFU
2811 
2812 /******************** Bits definition for RTC_BKP9R register ****************/
2813 #define RTC_BKP9R 0xFFFFFFFFU
2814 
2815 /******************** Bits definition for RTC_BKP10R register ***************/
2816 #define RTC_BKP10R 0xFFFFFFFFU
2817 
2818 /******************** Bits definition for RTC_BKP11R register ***************/
2819 #define RTC_BKP11R 0xFFFFFFFFU
2820 
2821 /******************** Bits definition for RTC_BKP12R register ***************/
2822 #define RTC_BKP12R 0xFFFFFFFFU
2823 
2824 /******************** Bits definition for RTC_BKP13R register ***************/
2825 #define RTC_BKP13R 0xFFFFFFFFU
2826 
2827 /******************** Bits definition for RTC_BKP14R register ***************/
2828 #define RTC_BKP14R 0xFFFFFFFFU
2829 
2830 /******************** Bits definition for RTC_BKP15R register ***************/
2831 #define RTC_BKP15R 0xFFFFFFFFU
2832 
2833 /******************** Bits definition for RTC_BKP16R register ***************/
2834 #define RTC_BKP16R 0xFFFFFFFFU
2835 
2836 /******************** Bits definition for RTC_BKP17R register ***************/
2837 #define RTC_BKP17R 0xFFFFFFFFU
2838 
2839 /******************** Bits definition for RTC_BKP18R register ***************/
2840 #define RTC_BKP18R 0xFFFFFFFFU
2841 
2842 /******************** Bits definition for RTC_BKP19R register ***************/
2843 #define RTC_BKP19R 0xFFFFFFFFU
2844 
2845 /******************************************************************************/
2846 /* */
2847 /* Serial Peripheral Interface */
2848 /* */
2849 /******************************************************************************/
2850 /******************* Bit definition for SPI_CR1 register ********************/
2851 #define SPI_CR1_CPHA 0x00000001U
2852 #define SPI_CR1_CPOL 0x00000002U
2853 #define SPI_CR1_MSTR 0x00000004U
2855 #define SPI_CR1_BR 0x00000038U
2856 #define SPI_CR1_BR_0 0x00000008U
2857 #define SPI_CR1_BR_1 0x00000010U
2858 #define SPI_CR1_BR_2 0x00000020U
2860 #define SPI_CR1_SPE 0x00000040U
2861 #define SPI_CR1_LSBFIRST 0x00000080U
2862 #define SPI_CR1_SSI 0x00000100U
2863 #define SPI_CR1_SSM 0x00000200U
2864 #define SPI_CR1_RXONLY 0x00000400U
2865 #define SPI_CR1_DFF 0x00000800U
2866 #define SPI_CR1_CRCNEXT 0x00001000U
2867 #define SPI_CR1_CRCEN 0x00002000U
2868 #define SPI_CR1_BIDIOE 0x00004000U
2869 #define SPI_CR1_BIDIMODE 0x00008000U
2871 /******************* Bit definition for SPI_CR2 register ********************/
2872 #define SPI_CR2_RXDMAEN 0x00000001U
2873 #define SPI_CR2_TXDMAEN 0x00000002U
2874 #define SPI_CR2_SSOE 0x00000004U
2875 #define SPI_CR2_FRF 0x00000010U
2876 #define SPI_CR2_ERRIE 0x00000020U
2877 #define SPI_CR2_RXNEIE 0x00000040U
2878 #define SPI_CR2_TXEIE 0x00000080U
2880 /******************** Bit definition for SPI_SR register ********************/
2881 #define SPI_SR_RXNE 0x00000001U
2882 #define SPI_SR_TXE 0x00000002U
2883 #define SPI_SR_CHSIDE 0x00000004U
2884 #define SPI_SR_UDR 0x00000008U
2885 #define SPI_SR_CRCERR 0x00000010U
2886 #define SPI_SR_MODF 0x00000020U
2887 #define SPI_SR_OVR 0x00000040U
2888 #define SPI_SR_BSY 0x00000080U
2889 #define SPI_SR_FRE 0x00000100U
2891 /******************** Bit definition for SPI_DR register ********************/
2892 #define SPI_DR_DR 0x0000FFFFU
2894 /******************* Bit definition for SPI_CRCPR register ******************/
2895 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
2897 /****************** Bit definition for SPI_RXCRCR register ******************/
2898 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
2900 /****************** Bit definition for SPI_TXCRCR register ******************/
2901 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
2903 /****************** Bit definition for SPI_I2SCFGR register *****************/
2904 #define SPI_I2SCFGR_CHLEN 0x00000001U
2906 #define SPI_I2SCFGR_DATLEN 0x00000006U
2907 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
2908 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
2910 #define SPI_I2SCFGR_CKPOL 0x00000008U
2912 #define SPI_I2SCFGR_I2SSTD 0x00000030U
2913 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
2914 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
2916 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
2918 #define SPI_I2SCFGR_I2SCFG 0x00000300U
2919 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
2920 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
2922 #define SPI_I2SCFGR_I2SE 0x00000400U
2923 #define SPI_I2SCFGR_I2SMOD 0x00000800U
2925 /****************** Bit definition for SPI_I2SPR register *******************/
2926 #define SPI_I2SPR_I2SDIV 0x000000FFU
2927 #define SPI_I2SPR_ODD 0x00000100U
2928 #define SPI_I2SPR_MCKOE 0x00000200U
2930 /******************************************************************************/
2931 /* */
2932 /* SYSCFG */
2933 /* */
2934 /******************************************************************************/
2935 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
2936 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
2937 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
2938 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
2939 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
2940 
2941 /****************** Bit definition for SYSCFG_PMC register ******************/
2942 #define SYSCFG_PMC_ADC1DC2 0x00010000U
2944 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
2945 #define SYSCFG_EXTICR1_EXTI0 0x000FU
2946 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
2947 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
2948 #define SYSCFG_EXTICR1_EXTI3 0xF000U
2952 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
2953 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
2954 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
2955 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
2960 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
2961 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
2962 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
2963 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
2968 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
2969 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
2970 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
2971 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
2976 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
2977 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
2978 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
2979 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
2981 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
2982 #define SYSCFG_EXTICR2_EXTI4 0x000FU
2983 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
2984 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
2985 #define SYSCFG_EXTICR2_EXTI7 0xF000U
2989 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
2990 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
2991 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
2992 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
2997 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
2998 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
2999 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
3000 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
3005 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
3006 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
3007 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
3008 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
3013 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
3014 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
3015 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
3016 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
3019 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
3020 #define SYSCFG_EXTICR3_EXTI8 0x000FU
3021 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
3022 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
3023 #define SYSCFG_EXTICR3_EXTI11 0xF000U
3028 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
3029 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
3030 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
3031 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
3036 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
3037 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
3038 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
3039 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
3044 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
3045 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
3046 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
3047 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
3052 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
3053 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
3054 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
3055 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
3057 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
3058 #define SYSCFG_EXTICR4_EXTI12 0x000FU
3059 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
3060 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
3061 #define SYSCFG_EXTICR4_EXTI15 0xF000U
3065 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
3066 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
3067 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
3068 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
3073 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
3074 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
3075 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
3076 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
3081 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
3082 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
3083 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
3084 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
3089 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
3090 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
3091 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
3092 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
3094 /****************** Bit definition for SYSCFG_CMPCR register ****************/
3095 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
3096 #define SYSCFG_CMPCR_READY 0x00000100U
3098 /****************** Bit definition for SYSCFG_CFGR register *****************/
3099 #define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U
3100 #define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U
3102 /****************** Bit definition for SYSCFG_CFGR2 register *****************/
3103 #define SYSCFG_CFGR2_LOCKUP_LOCK 0x00000001U
3104 #define SYSCFG_CFGR2_PVD_LOCK 0x00000004U
3106 /******************************************************************************/
3107 /* */
3108 /* TIM */
3109 /* */
3110 /******************************************************************************/
3111 /******************* Bit definition for TIM_CR1 register ********************/
3112 #define TIM_CR1_CEN 0x0001U
3113 #define TIM_CR1_UDIS 0x0002U
3114 #define TIM_CR1_URS 0x0004U
3115 #define TIM_CR1_OPM 0x0008U
3116 #define TIM_CR1_DIR 0x0010U
3118 #define TIM_CR1_CMS 0x0060U
3119 #define TIM_CR1_CMS_0 0x0020U
3120 #define TIM_CR1_CMS_1 0x0040U
3122 #define TIM_CR1_ARPE 0x0080U
3124 #define TIM_CR1_CKD 0x0300U
3125 #define TIM_CR1_CKD_0 0x0100U
3126 #define TIM_CR1_CKD_1 0x0200U
3128 /******************* Bit definition for TIM_CR2 register ********************/
3129 #define TIM_CR2_CCPC 0x0001U
3130 #define TIM_CR2_CCUS 0x0004U
3131 #define TIM_CR2_CCDS 0x0008U
3133 #define TIM_CR2_MMS 0x0070U
3134 #define TIM_CR2_MMS_0 0x0010U
3135 #define TIM_CR2_MMS_1 0x0020U
3136 #define TIM_CR2_MMS_2 0x0040U
3138 #define TIM_CR2_TI1S 0x0080U
3139 #define TIM_CR2_OIS1 0x0100U
3140 #define TIM_CR2_OIS1N 0x0200U
3141 #define TIM_CR2_OIS2 0x0400U
3142 #define TIM_CR2_OIS2N 0x0800U
3143 #define TIM_CR2_OIS3 0x1000U
3144 #define TIM_CR2_OIS3N 0x2000U
3145 #define TIM_CR2_OIS4 0x4000U
3147 /******************* Bit definition for TIM_SMCR register *******************/
3148 #define TIM_SMCR_SMS 0x0007U
3149 #define TIM_SMCR_SMS_0 0x0001U
3150 #define TIM_SMCR_SMS_1 0x0002U
3151 #define TIM_SMCR_SMS_2 0x0004U
3153 #define TIM_SMCR_TS 0x0070U
3154 #define TIM_SMCR_TS_0 0x0010U
3155 #define TIM_SMCR_TS_1 0x0020U
3156 #define TIM_SMCR_TS_2 0x0040U
3158 #define TIM_SMCR_MSM 0x0080U
3160 #define TIM_SMCR_ETF 0x0F00U
3161 #define TIM_SMCR_ETF_0 0x0100U
3162 #define TIM_SMCR_ETF_1 0x0200U
3163 #define TIM_SMCR_ETF_2 0x0400U
3164 #define TIM_SMCR_ETF_3 0x0800U
3166 #define TIM_SMCR_ETPS 0x3000U
3167 #define TIM_SMCR_ETPS_0 0x1000U
3168 #define TIM_SMCR_ETPS_1 0x2000U
3170 #define TIM_SMCR_ECE 0x4000U
3171 #define TIM_SMCR_ETP 0x8000U
3173 /******************* Bit definition for TIM_DIER register *******************/
3174 #define TIM_DIER_UIE 0x0001U
3175 #define TIM_DIER_CC1IE 0x0002U
3176 #define TIM_DIER_CC2IE 0x0004U
3177 #define TIM_DIER_CC3IE 0x0008U
3178 #define TIM_DIER_CC4IE 0x0010U
3179 #define TIM_DIER_COMIE 0x0020U
3180 #define TIM_DIER_TIE 0x0040U
3181 #define TIM_DIER_BIE 0x0080U
3182 #define TIM_DIER_UDE 0x0100U
3183 #define TIM_DIER_CC1DE 0x0200U
3184 #define TIM_DIER_CC2DE 0x0400U
3185 #define TIM_DIER_CC3DE 0x0800U
3186 #define TIM_DIER_CC4DE 0x1000U
3187 #define TIM_DIER_COMDE 0x2000U
3188 #define TIM_DIER_TDE 0x4000U
3190 /******************** Bit definition for TIM_SR register ********************/
3191 #define TIM_SR_UIF 0x0001U
3192 #define TIM_SR_CC1IF 0x0002U
3193 #define TIM_SR_CC2IF 0x0004U
3194 #define TIM_SR_CC3IF 0x0008U
3195 #define TIM_SR_CC4IF 0x0010U
3196 #define TIM_SR_COMIF 0x0020U
3197 #define TIM_SR_TIF 0x0040U
3198 #define TIM_SR_BIF 0x0080U
3199 #define TIM_SR_CC1OF 0x0200U
3200 #define TIM_SR_CC2OF 0x0400U
3201 #define TIM_SR_CC3OF 0x0800U
3202 #define TIM_SR_CC4OF 0x1000U
3204 /******************* Bit definition for TIM_EGR register ********************/
3205 #define TIM_EGR_UG 0x01U
3206 #define TIM_EGR_CC1G 0x02U
3207 #define TIM_EGR_CC2G 0x04U
3208 #define TIM_EGR_CC3G 0x08U
3209 #define TIM_EGR_CC4G 0x10U
3210 #define TIM_EGR_COMG 0x20U
3211 #define TIM_EGR_TG 0x40U
3212 #define TIM_EGR_BG 0x80U
3214 /****************** Bit definition for TIM_CCMR1 register *******************/
3215 #define TIM_CCMR1_CC1S 0x0003U
3216 #define TIM_CCMR1_CC1S_0 0x0001U
3217 #define TIM_CCMR1_CC1S_1 0x0002U
3219 #define TIM_CCMR1_OC1FE 0x0004U
3220 #define TIM_CCMR1_OC1PE 0x0008U
3222 #define TIM_CCMR1_OC1M 0x0070U
3223 #define TIM_CCMR1_OC1M_0 0x0010U
3224 #define TIM_CCMR1_OC1M_1 0x0020U
3225 #define TIM_CCMR1_OC1M_2 0x0040U
3227 #define TIM_CCMR1_OC1CE 0x0080U
3229 #define TIM_CCMR1_CC2S 0x0300U
3230 #define TIM_CCMR1_CC2S_0 0x0100U
3231 #define TIM_CCMR1_CC2S_1 0x0200U
3233 #define TIM_CCMR1_OC2FE 0x0400U
3234 #define TIM_CCMR1_OC2PE 0x0800U
3236 #define TIM_CCMR1_OC2M 0x7000U
3237 #define TIM_CCMR1_OC2M_0 0x1000U
3238 #define TIM_CCMR1_OC2M_1 0x2000U
3239 #define TIM_CCMR1_OC2M_2 0x4000U
3241 #define TIM_CCMR1_OC2CE 0x8000U
3243 /*----------------------------------------------------------------------------*/
3244 
3245 #define TIM_CCMR1_IC1PSC 0x000CU
3246 #define TIM_CCMR1_IC1PSC_0 0x0004U
3247 #define TIM_CCMR1_IC1PSC_1 0x0008U
3249 #define TIM_CCMR1_IC1F 0x00F0U
3250 #define TIM_CCMR1_IC1F_0 0x0010U
3251 #define TIM_CCMR1_IC1F_1 0x0020U
3252 #define TIM_CCMR1_IC1F_2 0x0040U
3253 #define TIM_CCMR1_IC1F_3 0x0080U
3255 #define TIM_CCMR1_IC2PSC 0x0C00U
3256 #define TIM_CCMR1_IC2PSC_0 0x0400U
3257 #define TIM_CCMR1_IC2PSC_1 0x0800U
3259 #define TIM_CCMR1_IC2F 0xF000U
3260 #define TIM_CCMR1_IC2F_0 0x1000U
3261 #define TIM_CCMR1_IC2F_1 0x2000U
3262 #define TIM_CCMR1_IC2F_2 0x4000U
3263 #define TIM_CCMR1_IC2F_3 0x8000U
3265 /****************** Bit definition for TIM_CCMR2 register *******************/
3266 #define TIM_CCMR2_CC3S 0x0003U
3267 #define TIM_CCMR2_CC3S_0 0x0001U
3268 #define TIM_CCMR2_CC3S_1 0x0002U
3270 #define TIM_CCMR2_OC3FE 0x0004U
3271 #define TIM_CCMR2_OC3PE 0x0008U
3273 #define TIM_CCMR2_OC3M 0x0070U
3274 #define TIM_CCMR2_OC3M_0 0x0010U
3275 #define TIM_CCMR2_OC3M_1 0x0020U
3276 #define TIM_CCMR2_OC3M_2 0x0040U
3278 #define TIM_CCMR2_OC3CE 0x0080U
3280 #define TIM_CCMR2_CC4S 0x0300U
3281 #define TIM_CCMR2_CC4S_0 0x0100U
3282 #define TIM_CCMR2_CC4S_1 0x0200U
3284 #define TIM_CCMR2_OC4FE 0x0400U
3285 #define TIM_CCMR2_OC4PE 0x0800U
3287 #define TIM_CCMR2_OC4M 0x7000U
3288 #define TIM_CCMR2_OC4M_0 0x1000U
3289 #define TIM_CCMR2_OC4M_1 0x2000U
3290 #define TIM_CCMR2_OC4M_2 0x4000U
3292 #define TIM_CCMR2_OC4CE 0x8000U
3294 /*----------------------------------------------------------------------------*/
3295 
3296 #define TIM_CCMR2_IC3PSC 0x000CU
3297 #define TIM_CCMR2_IC3PSC_0 0x0004U
3298 #define TIM_CCMR2_IC3PSC_1 0x0008U
3300 #define TIM_CCMR2_IC3F 0x00F0U
3301 #define TIM_CCMR2_IC3F_0 0x0010U
3302 #define TIM_CCMR2_IC3F_1 0x0020U
3303 #define TIM_CCMR2_IC3F_2 0x0040U
3304 #define TIM_CCMR2_IC3F_3 0x0080U
3306 #define TIM_CCMR2_IC4PSC 0x0C00U
3307 #define TIM_CCMR2_IC4PSC_0 0x0400U
3308 #define TIM_CCMR2_IC4PSC_1 0x0800U
3310 #define TIM_CCMR2_IC4F 0xF000U
3311 #define TIM_CCMR2_IC4F_0 0x1000U
3312 #define TIM_CCMR2_IC4F_1 0x2000U
3313 #define TIM_CCMR2_IC4F_2 0x4000U
3314 #define TIM_CCMR2_IC4F_3 0x8000U
3316 /******************* Bit definition for TIM_CCER register *******************/
3317 #define TIM_CCER_CC1E 0x0001U
3318 #define TIM_CCER_CC1P 0x0002U
3319 #define TIM_CCER_CC1NE 0x0004U
3320 #define TIM_CCER_CC1NP 0x0008U
3321 #define TIM_CCER_CC2E 0x0010U
3322 #define TIM_CCER_CC2P 0x0020U
3323 #define TIM_CCER_CC2NE 0x0040U
3324 #define TIM_CCER_CC2NP 0x0080U
3325 #define TIM_CCER_CC3E 0x0100U
3326 #define TIM_CCER_CC3P 0x0200U
3327 #define TIM_CCER_CC3NE 0x0400U
3328 #define TIM_CCER_CC3NP 0x0800U
3329 #define TIM_CCER_CC4E 0x1000U
3330 #define TIM_CCER_CC4P 0x2000U
3331 #define TIM_CCER_CC4NP 0x8000U
3333 /******************* Bit definition for TIM_CNT register ********************/
3334 #define TIM_CNT_CNT 0xFFFFU
3336 /******************* Bit definition for TIM_PSC register ********************/
3337 #define TIM_PSC_PSC 0xFFFFU
3339 /******************* Bit definition for TIM_ARR register ********************/
3340 #define TIM_ARR_ARR 0xFFFFU
3342 /******************* Bit definition for TIM_RCR register ********************/
3343 #define TIM_RCR_REP 0xFFU
3345 /******************* Bit definition for TIM_CCR1 register *******************/
3346 #define TIM_CCR1_CCR1 0xFFFFU
3348 /******************* Bit definition for TIM_CCR2 register *******************/
3349 #define TIM_CCR2_CCR2 0xFFFFU
3351 /******************* Bit definition for TIM_CCR3 register *******************/
3352 #define TIM_CCR3_CCR3 0xFFFFU
3354 /******************* Bit definition for TIM_CCR4 register *******************/
3355 #define TIM_CCR4_CCR4 0xFFFFU
3357 /******************* Bit definition for TIM_BDTR register *******************/
3358 #define TIM_BDTR_DTG 0x00FFU
3359 #define TIM_BDTR_DTG_0 0x0001U
3360 #define TIM_BDTR_DTG_1 0x0002U
3361 #define TIM_BDTR_DTG_2 0x0004U
3362 #define TIM_BDTR_DTG_3 0x0008U
3363 #define TIM_BDTR_DTG_4 0x0010U
3364 #define TIM_BDTR_DTG_5 0x0020U
3365 #define TIM_BDTR_DTG_6 0x0040U
3366 #define TIM_BDTR_DTG_7 0x0080U
3368 #define TIM_BDTR_LOCK 0x0300U
3369 #define TIM_BDTR_LOCK_0 0x0100U
3370 #define TIM_BDTR_LOCK_1 0x0200U
3372 #define TIM_BDTR_OSSI 0x0400U
3373 #define TIM_BDTR_OSSR 0x0800U
3374 #define TIM_BDTR_BKE 0x1000U
3375 #define TIM_BDTR_BKP 0x2000U
3376 #define TIM_BDTR_AOE 0x4000U
3377 #define TIM_BDTR_MOE 0x8000U
3379 /******************* Bit definition for TIM_DCR register ********************/
3380 #define TIM_DCR_DBA 0x001FU
3381 #define TIM_DCR_DBA_0 0x0001U
3382 #define TIM_DCR_DBA_1 0x0002U
3383 #define TIM_DCR_DBA_2 0x0004U
3384 #define TIM_DCR_DBA_3 0x0008U
3385 #define TIM_DCR_DBA_4 0x0010U
3387 #define TIM_DCR_DBL 0x1F00U
3388 #define TIM_DCR_DBL_0 0x0100U
3389 #define TIM_DCR_DBL_1 0x0200U
3390 #define TIM_DCR_DBL_2 0x0400U
3391 #define TIM_DCR_DBL_3 0x0800U
3392 #define TIM_DCR_DBL_4 0x1000U
3394 /******************* Bit definition for TIM_DMAR register *******************/
3395 #define TIM_DMAR_DMAB 0xFFFFU
3397 /******************* Bit definition for TIM_OR register *********************/
3398 #define TIM_OR_TI4_RMP 0x00C0U
3399 #define TIM_OR_TI4_RMP_0 0x0040U
3400 #define TIM_OR_TI4_RMP_1 0x0080U
3402 /******************************************************************************/
3403 /* */
3404 /* Low Power Timer (LPTIM) */
3405 /* */
3406 /******************************************************************************/
3407 /****************** Bit definition for LPTIM_ISR register *******************/
3408 #define LPTIM_ISR_CMPM 0x00000001U
3409 #define LPTIM_ISR_ARRM 0x00000002U
3410 #define LPTIM_ISR_EXTTRIG 0x00000004U
3411 #define LPTIM_ISR_CMPOK 0x00000008U
3412 #define LPTIM_ISR_ARROK 0x00000010U
3413 #define LPTIM_ISR_UP 0x00000020U
3414 #define LPTIM_ISR_DOWN 0x00000040U
3416 /****************** Bit definition for LPTIM_ICR register *******************/
3417 #define LPTIM_ICR_CMPMCF 0x00000001U
3418 #define LPTIM_ICR_ARRMCF 0x00000002U
3419 #define LPTIM_ICR_EXTTRIGCF 0x00000004U
3420 #define LPTIM_ICR_CMPOKCF 0x00000008U
3421 #define LPTIM_ICR_ARROKCF 0x00000010U
3422 #define LPTIM_ICR_UPCF 0x00000020U
3423 #define LPTIM_ICR_DOWNCF 0x00000040U
3425 /****************** Bit definition for LPTIM_IER register ********************/
3426 #define LPTIM_IER_CMPMIE 0x00000001U
3427 #define LPTIM_IER_ARRMIE 0x00000002U
3428 #define LPTIM_IER_EXTTRIGIE 0x00000004U
3429 #define LPTIM_IER_CMPOKIE 0x00000008U
3430 #define LPTIM_IER_ARROKIE 0x00000010U
3431 #define LPTIM_IER_UPIE 0x00000020U
3432 #define LPTIM_IER_DOWNIE 0x00000040U
3434 /****************** Bit definition for LPTIM_CFGR register *******************/
3435 #define LPTIM_CFGR_CKSEL 0x00000001U
3437 #define LPTIM_CFGR_CKPOL 0x00000006U
3438 #define LPTIM_CFGR_CKPOL_0 0x00000002U
3439 #define LPTIM_CFGR_CKPOL_1 0x00000004U
3441 #define LPTIM_CFGR_CKFLT 0x00000018U
3442 #define LPTIM_CFGR_CKFLT_0 0x00000008U
3443 #define LPTIM_CFGR_CKFLT_1 0x00000010U
3445 #define LPTIM_CFGR_TRGFLT 0x000000C0U
3446 #define LPTIM_CFGR_TRGFLT_0 0x00000040U
3447 #define LPTIM_CFGR_TRGFLT_1 0x00000080U
3449 #define LPTIM_CFGR_PRESC 0x00000E00U
3450 #define LPTIM_CFGR_PRESC_0 0x00000200U
3451 #define LPTIM_CFGR_PRESC_1 0x00000400U
3452 #define LPTIM_CFGR_PRESC_2 0x00000800U
3454 #define LPTIM_CFGR_TRIGSEL 0x0000E000U
3455 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U
3456 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U
3457 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U
3459 #define LPTIM_CFGR_TRIGEN 0x00060000U
3460 #define LPTIM_CFGR_TRIGEN_0 0x00020000U
3461 #define LPTIM_CFGR_TRIGEN_1 0x00040000U
3463 #define LPTIM_CFGR_TIMOUT 0x00080000U
3464 #define LPTIM_CFGR_WAVE 0x00100000U
3465 #define LPTIM_CFGR_WAVPOL 0x00200000U
3466 #define LPTIM_CFGR_PRELOAD 0x00400000U
3467 #define LPTIM_CFGR_COUNTMODE 0x00800000U
3468 #define LPTIM_CFGR_ENC 0x01000000U
3470 /****************** Bit definition for LPTIM_CR register ********************/
3471 #define LPTIM_CR_ENABLE 0x00000001U
3472 #define LPTIM_CR_SNGSTRT 0x00000002U
3473 #define LPTIM_CR_CNTSTRT 0x00000004U
3475 /****************** Bit definition for LPTIM_CMP register *******************/
3476 #define LPTIM_CMP_CMP 0x0000FFFFU
3478 /****************** Bit definition for LPTIM_ARR register *******************/
3479 #define LPTIM_ARR_ARR 0x0000FFFFU
3481 /****************** Bit definition for LPTIM_CNT register *******************/
3482 #define LPTIM_CNT_CNT 0x0000FFFFU
3484 /****************** Bit definition for LPTIM_OR register *******************/
3485 #define LPTIM_OR_OR 0x00000003U
3486 #define LPTIM_OR_OR_0 0x00000001U
3487 #define LPTIM_OR_OR_1 0x00000002U
3489 /******************************************************************************/
3490 /* */
3491 /* Universal Synchronous Asynchronous Receiver Transmitter */
3492 /* */
3493 /******************************************************************************/
3494 /******************* Bit definition for USART_SR register *******************/
3495 #define USART_SR_PE 0x0001U
3496 #define USART_SR_FE 0x0002U
3497 #define USART_SR_NE 0x0004U
3498 #define USART_SR_ORE 0x0008U
3499 #define USART_SR_IDLE 0x0010U
3500 #define USART_SR_RXNE 0x0020U
3501 #define USART_SR_TC 0x0040U
3502 #define USART_SR_TXE 0x0080U
3503 #define USART_SR_LBD 0x0100U
3504 #define USART_SR_CTS 0x0200U
3506 /******************* Bit definition for USART_DR register *******************/
3507 #define USART_DR_DR 0x01FFU
3509 /****************** Bit definition for USART_BRR register *******************/
3510 #define USART_BRR_DIV_Fraction 0x000FU
3511 #define USART_BRR_DIV_Mantissa 0xFFF0U
3513 /****************** Bit definition for USART_CR1 register *******************/
3514 #define USART_CR1_SBK 0x0001U
3515 #define USART_CR1_RWU 0x0002U
3516 #define USART_CR1_RE 0x0004U
3517 #define USART_CR1_TE 0x0008U
3518 #define USART_CR1_IDLEIE 0x0010U
3519 #define USART_CR1_RXNEIE 0x0020U
3520 #define USART_CR1_TCIE 0x0040U
3521 #define USART_CR1_TXEIE 0x0080U
3522 #define USART_CR1_PEIE 0x0100U
3523 #define USART_CR1_PS 0x0200U
3524 #define USART_CR1_PCE 0x0400U
3525 #define USART_CR1_WAKE 0x0800U
3526 #define USART_CR1_M 0x1000U
3527 #define USART_CR1_UE 0x2000U
3528 #define USART_CR1_OVER8 0x8000U
3530 /****************** Bit definition for USART_CR2 register *******************/
3531 #define USART_CR2_ADD 0x000FU
3532 #define USART_CR2_LBDL 0x0020U
3533 #define USART_CR2_LBDIE 0x0040U
3534 #define USART_CR2_LBCL 0x0100U
3535 #define USART_CR2_CPHA 0x0200U
3536 #define USART_CR2_CPOL 0x0400U
3537 #define USART_CR2_CLKEN 0x0800U
3539 #define USART_CR2_STOP 0x3000U
3540 #define USART_CR2_STOP_0 0x1000U
3541 #define USART_CR2_STOP_1 0x2000U
3543 #define USART_CR2_LINEN 0x4000U
3545 /****************** Bit definition for USART_CR3 register *******************/
3546 #define USART_CR3_EIE 0x0001U
3547 #define USART_CR3_IREN 0x0002U
3548 #define USART_CR3_IRLP 0x0004U
3549 #define USART_CR3_HDSEL 0x0008U
3550 #define USART_CR3_NACK 0x0010U
3551 #define USART_CR3_SCEN 0x0020U
3552 #define USART_CR3_DMAR 0x0040U
3553 #define USART_CR3_DMAT 0x0080U
3554 #define USART_CR3_RTSE 0x0100U
3555 #define USART_CR3_CTSE 0x0200U
3556 #define USART_CR3_CTSIE 0x0400U
3557 #define USART_CR3_ONEBIT 0x0800U
3559 /****************** Bit definition for USART_GTPR register ******************/
3560 #define USART_GTPR_PSC 0x00FFU
3561 #define USART_GTPR_PSC_0 0x0001U
3562 #define USART_GTPR_PSC_1 0x0002U
3563 #define USART_GTPR_PSC_2 0x0004U
3564 #define USART_GTPR_PSC_3 0x0008U
3565 #define USART_GTPR_PSC_4 0x0010U
3566 #define USART_GTPR_PSC_5 0x0020U
3567 #define USART_GTPR_PSC_6 0x0040U
3568 #define USART_GTPR_PSC_7 0x0080U
3570 #define USART_GTPR_GT 0xFF00U
3572 /******************************************************************************/
3573 /* */
3574 /* Window WATCHDOG */
3575 /* */
3576 /******************************************************************************/
3577 /******************* Bit definition for WWDG_CR register ********************/
3578 #define WWDG_CR_T 0x7FU
3579 #define WWDG_CR_T_0 0x01U
3580 #define WWDG_CR_T_1 0x02U
3581 #define WWDG_CR_T_2 0x04U
3582 #define WWDG_CR_T_3 0x08U
3583 #define WWDG_CR_T_4 0x10U
3584 #define WWDG_CR_T_5 0x20U
3585 #define WWDG_CR_T_6 0x40U
3586 /* Legacy defines */
3587 #define WWDG_CR_T0 WWDG_CR_T_0
3588 #define WWDG_CR_T1 WWDG_CR_T_1
3589 #define WWDG_CR_T2 WWDG_CR_T_2
3590 #define WWDG_CR_T3 WWDG_CR_T_3
3591 #define WWDG_CR_T4 WWDG_CR_T_4
3592 #define WWDG_CR_T5 WWDG_CR_T_5
3593 #define WWDG_CR_T6 WWDG_CR_T_6
3594 
3595 #define WWDG_CR_WDGA 0x80U
3597 /******************* Bit definition for WWDG_CFR register *******************/
3598 #define WWDG_CFR_W 0x007FU
3599 #define WWDG_CFR_W_0 0x0001U
3600 #define WWDG_CFR_W_1 0x0002U
3601 #define WWDG_CFR_W_2 0x0004U
3602 #define WWDG_CFR_W_3 0x0008U
3603 #define WWDG_CFR_W_4 0x0010U
3604 #define WWDG_CFR_W_5 0x0020U
3605 #define WWDG_CFR_W_6 0x0040U
3606 /* Legacy defines */
3607 #define WWDG_CFR_W0 WWDG_CFR_W_0
3608 #define WWDG_CFR_W1 WWDG_CFR_W_1
3609 #define WWDG_CFR_W2 WWDG_CFR_W_2
3610 #define WWDG_CFR_W3 WWDG_CFR_W_3
3611 #define WWDG_CFR_W4 WWDG_CFR_W_4
3612 #define WWDG_CFR_W5 WWDG_CFR_W_5
3613 #define WWDG_CFR_W6 WWDG_CFR_W_6
3614 
3615 #define WWDG_CFR_WDGTB 0x0180U
3616 #define WWDG_CFR_WDGTB_0 0x0080U
3617 #define WWDG_CFR_WDGTB_1 0x0100U
3618 /* Legacy defines */
3619 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
3620 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
3621 
3622 #define WWDG_CFR_EWI 0x0200U
3624 /******************* Bit definition for WWDG_SR register ********************/
3625 #define WWDG_SR_EWIF 0x01U
3627 /******************************************************************************/
3628 /* */
3629 /* Digital to Analog Converter */
3630 /* */
3631 /******************************************************************************/
3632 /******************** Bit definition for DAC_CR register ********************/
3633 #define DAC_CR_EN1 0x00000001U
3634 #define DAC_CR_BOFF1 0x00000002U
3635 #define DAC_CR_TEN1 0x00000004U
3637 #define DAC_CR_TSEL1 0x00000038U
3638 #define DAC_CR_TSEL1_0 0x00000008U
3639 #define DAC_CR_TSEL1_1 0x00000010U
3640 #define DAC_CR_TSEL1_2 0x00000020U
3642 #define DAC_CR_WAVE1 0x000000C0U
3643 #define DAC_CR_WAVE1_0 0x00000040U
3644 #define DAC_CR_WAVE1_1 0x00000080U
3646 #define DAC_CR_MAMP1 0x00000F00U
3647 #define DAC_CR_MAMP1_0 0x00000100U
3648 #define DAC_CR_MAMP1_1 0x00000200U
3649 #define DAC_CR_MAMP1_2 0x00000400U
3650 #define DAC_CR_MAMP1_3 0x00000800U
3652 #define DAC_CR_DMAEN1 0x00001000U
3653 #define DAC_CR_DMAUDRIE1 0x00002000U
3654 #define DAC_CR_EN2 0x00010000U
3655 #define DAC_CR_BOFF2 0x00020000U
3656 #define DAC_CR_TEN2 0x00040000U
3658 #define DAC_CR_TSEL2 0x00380000U
3659 #define DAC_CR_TSEL2_0 0x00080000U
3660 #define DAC_CR_TSEL2_1 0x00100000U
3661 #define DAC_CR_TSEL2_2 0x00200000U
3663 #define DAC_CR_WAVE2 0x00C00000U
3664 #define DAC_CR_WAVE2_0 0x00400000U
3665 #define DAC_CR_WAVE2_1 0x00800000U
3667 #define DAC_CR_MAMP2 0x0F000000U
3668 #define DAC_CR_MAMP2_0 0x01000000U
3669 #define DAC_CR_MAMP2_1 0x02000000U
3670 #define DAC_CR_MAMP2_2 0x04000000U
3671 #define DAC_CR_MAMP2_3 0x08000000U
3673 #define DAC_CR_DMAEN2 0x10000000U
3674 #define DAC_CR_DMAUDRIE2 0x20000000U
3676 /***************** Bit definition for DAC_SWTRIGR register ******************/
3677 #define DAC_SWTRIGR_SWTRIG1 0x01U
3678 #define DAC_SWTRIGR_SWTRIG2 0x02U
3680 /***************** Bit definition for DAC_DHR12R1 register ******************/
3681 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3683 /***************** Bit definition for DAC_DHR12L1 register ******************/
3684 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3686 /****************** Bit definition for DAC_DHR8R1 register ******************/
3687 #define DAC_DHR8R1_DACC1DHR 0xFFU
3689 /***************** Bit definition for DAC_DHR12R2 register ******************/
3690 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3692 /***************** Bit definition for DAC_DHR12L2 register ******************/
3693 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3695 /****************** Bit definition for DAC_DHR8R2 register ******************/
3696 #define DAC_DHR8R2_DACC2DHR 0xFFU
3698 /***************** Bit definition for DAC_DHR12RD register ******************/
3699 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3700 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3702 /***************** Bit definition for DAC_DHR12LD register ******************/
3703 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3704 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3706 /****************** Bit definition for DAC_DHR8RD register ******************/
3707 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3708 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3710 /******************* Bit definition for DAC_DOR1 register *******************/
3711 #define DAC_DOR1_DACC1DOR 0x0FFFU
3713 /******************* Bit definition for DAC_DOR2 register *******************/
3714 #define DAC_DOR2_DACC2DOR 0x0FFFU
3716 /******************** Bit definition for DAC_SR register ********************/
3717 #define DAC_SR_DMAUDR1 0x00002000U
3718 #define DAC_SR_DMAUDR2 0x20000000U
3719 /******************************************************************************/
3720 /* */
3721 /* DBG */
3722 /* */
3723 /******************************************************************************/
3724 /******************** Bit definition for DBGMCU_IDCODE register *************/
3725 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
3726 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
3727 
3728 /******************** Bit definition for DBGMCU_CR register *****************/
3729 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
3730 #define DBGMCU_CR_DBG_STOP 0x00000002U
3731 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
3732 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
3733 
3734 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
3735 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
3736 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
3738 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
3739 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
3740 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
3741 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
3742 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
3743 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
3744 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
3745 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
3746 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
3747 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
3748 
3749 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
3750 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
3751 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
3752 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
3753 
3766 /******************************* ADC Instances ********************************/
3767 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
3768 
3769 /******************************* CRC Instances ********************************/
3770 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
3771 
3772 /******************************* DAC Instances ********************************/
3773 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
3774 
3775 /******************************** DMA Instances *******************************/
3776 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
3777  ((INSTANCE) == DMA1_Stream1) || \
3778  ((INSTANCE) == DMA1_Stream2) || \
3779  ((INSTANCE) == DMA1_Stream3) || \
3780  ((INSTANCE) == DMA1_Stream4) || \
3781  ((INSTANCE) == DMA1_Stream5) || \
3782  ((INSTANCE) == DMA1_Stream6) || \
3783  ((INSTANCE) == DMA1_Stream7) || \
3784  ((INSTANCE) == DMA2_Stream0) || \
3785  ((INSTANCE) == DMA2_Stream1) || \
3786  ((INSTANCE) == DMA2_Stream2) || \
3787  ((INSTANCE) == DMA2_Stream3) || \
3788  ((INSTANCE) == DMA2_Stream4) || \
3789  ((INSTANCE) == DMA2_Stream5) || \
3790  ((INSTANCE) == DMA2_Stream6) || \
3791  ((INSTANCE) == DMA2_Stream7))
3792 
3793 /******************************* GPIO Instances *******************************/
3794 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
3795  ((INSTANCE) == GPIOB) || \
3796  ((INSTANCE) == GPIOC) || \
3797  ((INSTANCE) == GPIOH))
3798 
3799 /******************************** I2C Instances *******************************/
3800 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
3801  ((INSTANCE) == I2C2))
3802 /******************************** I2S Instances *******************************/
3803 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
3804 
3805 /******************************* LPTIM Instances ******************************/
3806 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
3807 
3808 /******************************* RNG Instances ********************************/
3809 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
3810 
3811 /****************************** RTC Instances *********************************/
3812 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
3813 
3814 /******************************** SPI Instances *******************************/
3815 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
3816 /*************************** SPI Extended Instances ***************************/
3817 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) ((INSTANCE) == SPI1)
3818 
3819 /****************** TIM Instances : All supported instances *******************/
3820 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3821  ((INSTANCE) == TIM5) || \
3822  ((INSTANCE) == TIM6) || \
3823  ((INSTANCE) == TIM9) || \
3824  ((INSTANCE) == TIM11))
3825 
3826 /************* TIM Instances : at least 1 capture/compare channel *************/
3827 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3828  ((INSTANCE) == TIM5) || \
3829  ((INSTANCE) == TIM9) || \
3830  ((INSTANCE) == TIM11))
3831 
3832 /************ TIM Instances : at least 2 capture/compare channels *************/
3833 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3834  ((INSTANCE) == TIM5) || \
3835  ((INSTANCE) == TIM9))
3836 
3837 /************ TIM Instances : at least 3 capture/compare channels *************/
3838 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3839  ((INSTANCE) == TIM5))
3840 
3841 /************ TIM Instances : at least 4 capture/compare channels *************/
3842 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3843  ((INSTANCE) == TIM5))
3844 
3845 /******************** TIM Instances : Advanced-control timers *****************/
3846 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
3847 
3848 /******************* TIM Instances : Timer input XOR function *****************/
3849 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3850  ((INSTANCE) == TIM5))
3851 
3852 /****************** TIM Instances : DMA requests generation (UDE) *************/
3853 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3854  ((INSTANCE) == TIM5) || \
3855  ((INSTANCE) == TIM6))
3856 
3857 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
3858 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3859  ((INSTANCE) == TIM5))
3860 
3861 /************ TIM Instances : DMA requests generation (COMDE) *****************/
3862 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3863  ((INSTANCE) == TIM5))
3864 
3865 /******************** TIM Instances : DMA burst feature ***********************/
3866 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3867  ((INSTANCE) == TIM5))
3868 
3869 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
3870 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3871  ((INSTANCE) == TIM5) || \
3872  ((INSTANCE) == TIM6) || \
3873  ((INSTANCE) == TIM9))
3874 
3875 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
3876 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3877  ((INSTANCE) == TIM5) || \
3878  ((INSTANCE) == TIM9))
3879 
3880 /********************** TIM Instances : 32 bit Counter ************************/
3881 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
3882 
3883 /***************** TIM Instances : external trigger input availabe ************/
3884 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
3885  ((INSTANCE) == TIM5))
3886 
3887 /****************** TIM Instances : remapping capability **********************/
3888 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
3889  ((INSTANCE) == TIM11))
3890 
3891 /******************* TIM Instances : output(s) available **********************/
3892 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
3893  ((((INSTANCE) == TIM1) && \
3894  (((CHANNEL) == TIM_CHANNEL_1) || \
3895  ((CHANNEL) == TIM_CHANNEL_2) || \
3896  ((CHANNEL) == TIM_CHANNEL_3) || \
3897  ((CHANNEL) == TIM_CHANNEL_4))) \
3898  || \
3899  (((INSTANCE) == TIM5) && \
3900  (((CHANNEL) == TIM_CHANNEL_1) || \
3901  ((CHANNEL) == TIM_CHANNEL_2) || \
3902  ((CHANNEL) == TIM_CHANNEL_3) || \
3903  ((CHANNEL) == TIM_CHANNEL_4))) \
3904  || \
3905  (((INSTANCE) == TIM9) && \
3906  (((CHANNEL) == TIM_CHANNEL_1) || \
3907  ((CHANNEL) == TIM_CHANNEL_2))) \
3908  || \
3909  (((INSTANCE) == TIM11) && \
3910  (((CHANNEL) == TIM_CHANNEL_1))))
3911 
3912 /************ TIM Instances : complementary output(s) available ***************/
3913 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
3914  ((((INSTANCE) == TIM1) && \
3915  (((CHANNEL) == TIM_CHANNEL_1) || \
3916  ((CHANNEL) == TIM_CHANNEL_2) || \
3917  ((CHANNEL) == TIM_CHANNEL_3))))
3918 
3919 /******************** USART Instances : Synchronous mode **********************/
3920 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3921  ((INSTANCE) == USART2))
3922 
3923 /******************** UART Instances : Asynchronous mode **********************/
3924 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3925  ((INSTANCE) == USART2))
3926 
3927 /****************** UART Instances : Hardware Flow control ********************/
3928 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (0)
3929 
3930 /********************* UART Instances : Smard card mode ***********************/
3931 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3932  ((INSTANCE) == USART2))
3933 
3934 /*********************** UART Instances : IRDA mode ***************************/
3935 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3936  ((INSTANCE) == USART2))
3937 
3938 /****************************** IWDG Instances ********************************/
3939 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
3940 
3941 /****************************** WWDG Instances ********************************/
3942 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
3943 
3944 /***************************** FMPI2C Instances *******************************/
3945 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
3946 
3959 #ifdef __cplusplus
3960 }
3961 #endif /* __cplusplus */
3962 
3963 #endif /* __STM32F410Tx_H */
3964 
3965 
3966 
3967 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
TAMP_STAMP_IRQn
Definition: stm32f410tx.h:99
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f410tx.h:119
EXTI2_IRQn
Definition: stm32f410tx.h:105
EXTI4_IRQn
Definition: stm32f410tx.h:107
USART1_IRQn
Definition: stm32f410tx.h:126
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
RTC_Alarm_IRQn
Definition: stm32f410tx.h:129
PendSV_IRQn
Definition: stm32f410tx.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f410tx.h:100
TIM6_DAC_IRQn
Definition: stm32f410tx.h:132
SPI1_IRQn
Definition: stm32f410tx.h:125
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
DMA_TypeDef
Definition: stm32f401xc.h:243
DMA1_Stream2_IRQn
Definition: stm32f410tx.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
FMPI2C1_ER_IRQn
Definition: stm32f410tx.h:144
RNG_IRQn
Definition: stm32f410tx.h:141
DMA2_Stream5_IRQn
Definition: stm32f410tx.h:138
ADC_IRQn
Definition: stm32f410tx.h:115
RCC_IRQn
Definition: stm32f410tx.h:102
TIM1_UP_IRQn
Definition: stm32f410tx.h:118
DebugMonitor_IRQn
Definition: stm32f410tx.h:93
DMA2_Stream3_IRQn
Definition: stm32f410tx.h:136
NonMaskableInt_IRQn
Definition: stm32f410tx.h:88
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f410tx.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
DMA1_Stream1_IRQn
Definition: stm32f410tx.h:109
DMA2_Stream7_IRQn
Definition: stm32f410tx.h:140
DMA2_Stream6_IRQn
Definition: stm32f410tx.h:139
BusFault_IRQn
Definition: stm32f410tx.h:90
LPTIM_TypeDef
LPTIMER.
Definition: stm32f410cx.h:563
PVD_IRQn
Definition: stm32f410tx.h:98
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f410tx.h:112
DMA1_Stream0_IRQn
Definition: stm32f410tx.h:108
DMA1_Stream3_IRQn
Definition: stm32f410tx.h:111
FPU_IRQn
Definition: stm32f410tx.h:142
DMA2_Stream2_IRQn
Definition: stm32f410tx.h:135
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
FMPI2C1_EV_IRQn
Definition: stm32f410tx.h:143
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f410tx.h:127
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
I2C2_EV_IRQn
Definition: stm32f410tx.h:123
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f410tx.h:104
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f410tx.h:92
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f410tx.h:120
FLASH_IRQn
Definition: stm32f410tx.h:101
DMA1_Stream5_IRQn
Definition: stm32f410tx.h:113
SysTick_IRQn
Definition: stm32f410tx.h:95
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f410tx.h:124
UsageFault_IRQn
Definition: stm32f410tx.h:91
DMA2_Stream1_IRQn
Definition: stm32f410tx.h:134
EXTI9_5_IRQn
Definition: stm32f410tx.h:116
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f410tx.h:121
DMA1_Stream6_IRQn
Definition: stm32f410tx.h:114
I2C1_ER_IRQn
Definition: stm32f410tx.h:122
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
FMPI2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f410cx.h:354
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
DMA2_Stream4_IRQn
Definition: stm32f410tx.h:137
WWDG_IRQn
Definition: stm32f410tx.h:97
LPTIM1_IRQn
Definition: stm32f410tx.h:145
DMA1_Stream7_IRQn
Definition: stm32f410tx.h:130
EXTI15_10_IRQn
Definition: stm32f410tx.h:128
EXTI0_IRQn
Definition: stm32f410tx.h:103
DMA2_Stream0_IRQn
Definition: stm32f410tx.h:133
TIM1_BRK_TIM9_IRQn
Definition: stm32f410tx.h:117
TIM5_IRQn
Definition: stm32f410tx.h:131
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
EXTI3_IRQn
Definition: stm32f410tx.h:106
MemoryManagement_IRQn
Definition: stm32f410tx.h:89