STM CMSIS
stm32f411xe.h
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1 
52 #ifndef __STM32F411xE_H
53 #define __STM32F411xE_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  EXTI9_5_IRQn = 23,
117  TIM1_BRK_TIM9_IRQn = 24,
118  TIM1_UP_TIM10_IRQn = 25,
119  TIM1_TRG_COM_TIM11_IRQn = 26,
120  TIM1_CC_IRQn = 27,
121  TIM2_IRQn = 28,
122  TIM3_IRQn = 29,
123  TIM4_IRQn = 30,
124  I2C1_EV_IRQn = 31,
125  I2C1_ER_IRQn = 32,
126  I2C2_EV_IRQn = 33,
127  I2C2_ER_IRQn = 34,
128  SPI1_IRQn = 35,
129  SPI2_IRQn = 36,
130  USART1_IRQn = 37,
131  USART2_IRQn = 38,
132  EXTI15_10_IRQn = 40,
133  RTC_Alarm_IRQn = 41,
134  OTG_FS_WKUP_IRQn = 42,
135  DMA1_Stream7_IRQn = 47,
136  SDIO_IRQn = 49,
137  TIM5_IRQn = 50,
138  SPI3_IRQn = 51,
139  DMA2_Stream0_IRQn = 56,
140  DMA2_Stream1_IRQn = 57,
141  DMA2_Stream2_IRQn = 58,
142  DMA2_Stream3_IRQn = 59,
143  DMA2_Stream4_IRQn = 60,
144  OTG_FS_IRQn = 67,
145  DMA2_Stream5_IRQn = 68,
146  DMA2_Stream6_IRQn = 69,
147  DMA2_Stream7_IRQn = 70,
148  USART6_IRQn = 71,
149  I2C3_EV_IRQn = 72,
150  I2C3_ER_IRQn = 73,
151  FPU_IRQn = 81,
152  SPI4_IRQn = 84,
153  SPI5_IRQn = 85
154 } IRQn_Type;
155 
160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
161 #include "system_stm32f4xx.h"
162 #include <stdint.h>
163 
172 typedef struct
173 {
174  __IO uint32_t SR;
175  __IO uint32_t CR1;
176  __IO uint32_t CR2;
177  __IO uint32_t SMPR1;
178  __IO uint32_t SMPR2;
179  __IO uint32_t JOFR1;
180  __IO uint32_t JOFR2;
181  __IO uint32_t JOFR3;
182  __IO uint32_t JOFR4;
183  __IO uint32_t HTR;
184  __IO uint32_t LTR;
185  __IO uint32_t SQR1;
186  __IO uint32_t SQR2;
187  __IO uint32_t SQR3;
188  __IO uint32_t JSQR;
189  __IO uint32_t JDR1;
190  __IO uint32_t JDR2;
191  __IO uint32_t JDR3;
192  __IO uint32_t JDR4;
193  __IO uint32_t DR;
194 } ADC_TypeDef;
195 
196 typedef struct
197 {
198  __IO uint32_t CSR;
199  __IO uint32_t CCR;
200  __IO uint32_t CDR;
202 } ADC_Common_TypeDef;
203 
208 typedef struct
209 {
210  __IO uint32_t DR;
211  __IO uint8_t IDR;
212  uint8_t RESERVED0;
213  uint16_t RESERVED1;
214  __IO uint32_t CR;
215 } CRC_TypeDef;
216 
221 typedef struct
222 {
223  __IO uint32_t IDCODE;
224  __IO uint32_t CR;
225  __IO uint32_t APB1FZ;
226  __IO uint32_t APB2FZ;
227 }DBGMCU_TypeDef;
228 
229 
234 typedef struct
235 {
236  __IO uint32_t CR;
237  __IO uint32_t NDTR;
238  __IO uint32_t PAR;
239  __IO uint32_t M0AR;
240  __IO uint32_t M1AR;
241  __IO uint32_t FCR;
242 } DMA_Stream_TypeDef;
243 
244 typedef struct
245 {
246  __IO uint32_t LISR;
247  __IO uint32_t HISR;
248  __IO uint32_t LIFCR;
249  __IO uint32_t HIFCR;
250 } DMA_TypeDef;
251 
252 
257 typedef struct
258 {
259  __IO uint32_t IMR;
260  __IO uint32_t EMR;
261  __IO uint32_t RTSR;
262  __IO uint32_t FTSR;
263  __IO uint32_t SWIER;
264  __IO uint32_t PR;
265 } EXTI_TypeDef;
266 
271 typedef struct
272 {
273  __IO uint32_t ACR;
274  __IO uint32_t KEYR;
275  __IO uint32_t OPTKEYR;
276  __IO uint32_t SR;
277  __IO uint32_t CR;
278  __IO uint32_t OPTCR;
279  __IO uint32_t OPTCR1;
280 } FLASH_TypeDef;
281 
286 typedef struct
287 {
288  __IO uint32_t MODER;
289  __IO uint32_t OTYPER;
290  __IO uint32_t OSPEEDR;
291  __IO uint32_t PUPDR;
292  __IO uint32_t IDR;
293  __IO uint32_t ODR;
294  __IO uint32_t BSRR;
295  __IO uint32_t LCKR;
296  __IO uint32_t AFR[2];
297 } GPIO_TypeDef;
298 
303 typedef struct
304 {
305  __IO uint32_t MEMRMP;
306  __IO uint32_t PMC;
307  __IO uint32_t EXTICR[4];
308  uint32_t RESERVED[2];
309  __IO uint32_t CMPCR;
310 } SYSCFG_TypeDef;
311 
316 typedef struct
317 {
318  __IO uint32_t CR1;
319  __IO uint32_t CR2;
320  __IO uint32_t OAR1;
321  __IO uint32_t OAR2;
322  __IO uint32_t DR;
323  __IO uint32_t SR1;
324  __IO uint32_t SR2;
325  __IO uint32_t CCR;
326  __IO uint32_t TRISE;
327  __IO uint32_t FLTR;
328 } I2C_TypeDef;
329 
334 typedef struct
335 {
336  __IO uint32_t KR;
337  __IO uint32_t PR;
338  __IO uint32_t RLR;
339  __IO uint32_t SR;
340 } IWDG_TypeDef;
341 
346 typedef struct
347 {
348  __IO uint32_t CR;
349  __IO uint32_t CSR;
350 } PWR_TypeDef;
351 
356 typedef struct
357 {
358  __IO uint32_t CR;
359  __IO uint32_t PLLCFGR;
360  __IO uint32_t CFGR;
361  __IO uint32_t CIR;
362  __IO uint32_t AHB1RSTR;
363  __IO uint32_t AHB2RSTR;
364  __IO uint32_t AHB3RSTR;
365  uint32_t RESERVED0;
366  __IO uint32_t APB1RSTR;
367  __IO uint32_t APB2RSTR;
368  uint32_t RESERVED1[2];
369  __IO uint32_t AHB1ENR;
370  __IO uint32_t AHB2ENR;
371  __IO uint32_t AHB3ENR;
372  uint32_t RESERVED2;
373  __IO uint32_t APB1ENR;
374  __IO uint32_t APB2ENR;
375  uint32_t RESERVED3[2];
376  __IO uint32_t AHB1LPENR;
377  __IO uint32_t AHB2LPENR;
378  __IO uint32_t AHB3LPENR;
379  uint32_t RESERVED4;
380  __IO uint32_t APB1LPENR;
381  __IO uint32_t APB2LPENR;
382  uint32_t RESERVED5[2];
383  __IO uint32_t BDCR;
384  __IO uint32_t CSR;
385  uint32_t RESERVED6[2];
386  __IO uint32_t SSCGR;
387  __IO uint32_t PLLI2SCFGR;
388  uint32_t RESERVED7[1];
389  __IO uint32_t DCKCFGR;
390 } RCC_TypeDef;
391 
396 typedef struct
397 {
398  __IO uint32_t TR;
399  __IO uint32_t DR;
400  __IO uint32_t CR;
401  __IO uint32_t ISR;
402  __IO uint32_t PRER;
403  __IO uint32_t WUTR;
404  __IO uint32_t CALIBR;
405  __IO uint32_t ALRMAR;
406  __IO uint32_t ALRMBR;
407  __IO uint32_t WPR;
408  __IO uint32_t SSR;
409  __IO uint32_t SHIFTR;
410  __IO uint32_t TSTR;
411  __IO uint32_t TSDR;
412  __IO uint32_t TSSSR;
413  __IO uint32_t CALR;
414  __IO uint32_t TAFCR;
415  __IO uint32_t ALRMASSR;
416  __IO uint32_t ALRMBSSR;
417  uint32_t RESERVED7;
418  __IO uint32_t BKP0R;
419  __IO uint32_t BKP1R;
420  __IO uint32_t BKP2R;
421  __IO uint32_t BKP3R;
422  __IO uint32_t BKP4R;
423  __IO uint32_t BKP5R;
424  __IO uint32_t BKP6R;
425  __IO uint32_t BKP7R;
426  __IO uint32_t BKP8R;
427  __IO uint32_t BKP9R;
428  __IO uint32_t BKP10R;
429  __IO uint32_t BKP11R;
430  __IO uint32_t BKP12R;
431  __IO uint32_t BKP13R;
432  __IO uint32_t BKP14R;
433  __IO uint32_t BKP15R;
434  __IO uint32_t BKP16R;
435  __IO uint32_t BKP17R;
436  __IO uint32_t BKP18R;
437  __IO uint32_t BKP19R;
438 } RTC_TypeDef;
439 
440 
445 typedef struct
446 {
447  __IO uint32_t POWER;
448  __IO uint32_t CLKCR;
449  __IO uint32_t ARG;
450  __IO uint32_t CMD;
451  __I uint32_t RESPCMD;
452  __I uint32_t RESP1;
453  __I uint32_t RESP2;
454  __I uint32_t RESP3;
455  __I uint32_t RESP4;
456  __IO uint32_t DTIMER;
457  __IO uint32_t DLEN;
458  __IO uint32_t DCTRL;
459  __I uint32_t DCOUNT;
460  __I uint32_t STA;
461  __IO uint32_t ICR;
462  __IO uint32_t MASK;
463  uint32_t RESERVED0[2];
464  __I uint32_t FIFOCNT;
465  uint32_t RESERVED1[13];
466  __IO uint32_t FIFO;
467 } SDIO_TypeDef;
468 
473 typedef struct
474 {
475  __IO uint32_t CR1;
476  __IO uint32_t CR2;
477  __IO uint32_t SR;
478  __IO uint32_t DR;
479  __IO uint32_t CRCPR;
480  __IO uint32_t RXCRCR;
481  __IO uint32_t TXCRCR;
482  __IO uint32_t I2SCFGR;
483  __IO uint32_t I2SPR;
484 } SPI_TypeDef;
485 
490 typedef struct
491 {
492  __IO uint32_t CR1;
493  __IO uint32_t CR2;
494  __IO uint32_t SMCR;
495  __IO uint32_t DIER;
496  __IO uint32_t SR;
497  __IO uint32_t EGR;
498  __IO uint32_t CCMR1;
499  __IO uint32_t CCMR2;
500  __IO uint32_t CCER;
501  __IO uint32_t CNT;
502  __IO uint32_t PSC;
503  __IO uint32_t ARR;
504  __IO uint32_t RCR;
505  __IO uint32_t CCR1;
506  __IO uint32_t CCR2;
507  __IO uint32_t CCR3;
508  __IO uint32_t CCR4;
509  __IO uint32_t BDTR;
510  __IO uint32_t DCR;
511  __IO uint32_t DMAR;
512  __IO uint32_t OR;
513 } TIM_TypeDef;
514 
519 typedef struct
520 {
521  __IO uint32_t SR;
522  __IO uint32_t DR;
523  __IO uint32_t BRR;
524  __IO uint32_t CR1;
525  __IO uint32_t CR2;
526  __IO uint32_t CR3;
527  __IO uint32_t GTPR;
528 } USART_TypeDef;
529 
534 typedef struct
535 {
536  __IO uint32_t CR;
537  __IO uint32_t CFR;
538  __IO uint32_t SR;
539 } WWDG_TypeDef;
540 
541 
545 typedef struct
546 {
547  __IO uint32_t GOTGCTL;
548  __IO uint32_t GOTGINT;
549  __IO uint32_t GAHBCFG;
550  __IO uint32_t GUSBCFG;
551  __IO uint32_t GRSTCTL;
552  __IO uint32_t GINTSTS;
553  __IO uint32_t GINTMSK;
554  __IO uint32_t GRXSTSR;
555  __IO uint32_t GRXSTSP;
556  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
557  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
558  __IO uint32_t HNPTXSTS;
559  uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
560  __IO uint32_t GCCFG;
561  __IO uint32_t CID;
562  uint32_t Reserved40[48];
563  __IO uint32_t HPTXFSIZ;
564  __IO uint32_t DIEPTXF[0x0F];
565 }
566 USB_OTG_GlobalTypeDef;
567 
568 
569 
573 typedef struct
574 {
575  __IO uint32_t DCFG;
576  __IO uint32_t DCTL;
577  __IO uint32_t DSTS;
578  uint32_t Reserved0C;
579  __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
580  __IO uint32_t DOEPMSK;
581  __IO uint32_t DAINT;
582  __IO uint32_t DAINTMSK;
583  uint32_t Reserved20;
584  uint32_t Reserved9;
585  __IO uint32_t DVBUSDIS;
586  __IO uint32_t DVBUSPULSE;
587  __IO uint32_t DTHRCTL;
588  __IO uint32_t DIEPEMPMSK;
589  __IO uint32_t DEACHINT;
590  __IO uint32_t DEACHMSK;
591  uint32_t Reserved40;
592  __IO uint32_t DINEP1MSK;
593  uint32_t Reserved44[15];
594  __IO uint32_t DOUTEP1MSK;
595 }
596 USB_OTG_DeviceTypeDef;
597 
598 
602 typedef struct
603 {
604  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
605  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
606  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
607  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
608  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
609  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
610  __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
611  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
612 }
613 USB_OTG_INEndpointTypeDef;
614 
615 
619 typedef struct
620 {
621  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
622  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
623  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
624  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
625  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
626  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
627  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
628 }
629 USB_OTG_OUTEndpointTypeDef;
630 
631 
635 typedef struct
636 {
637  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
638  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
639  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
640  uint32_t Reserved40C; /* Reserved 40Ch*/
641  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
642  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
643  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
644 }
645 USB_OTG_HostTypeDef;
646 
647 
651 typedef struct
652 {
653  __IO uint32_t HCCHAR;
654  __IO uint32_t HCSPLT;
655  __IO uint32_t HCINT;
656  __IO uint32_t HCINTMSK;
657  __IO uint32_t HCTSIZ;
658  __IO uint32_t HCDMA;
659  uint32_t Reserved[2];
660 }
661 USB_OTG_HostChannelTypeDef;
662 
663 
667 #define FLASH_BASE 0x08000000U
668 #define SRAM1_BASE 0x20000000U
669 #define PERIPH_BASE 0x40000000U
670 #define BKPSRAM_BASE 0x40024000U
671 #define SRAM1_BB_BASE 0x22000000U
672 #define PERIPH_BB_BASE 0x42000000U
673 #define BKPSRAM_BB_BASE 0x42480000U
674 #define FLASH_END 0x0807FFFFU
676 /* Legacy defines */
677 #define SRAM_BASE SRAM1_BASE
678 #define SRAM_BB_BASE SRAM1_BB_BASE
679 
680 
682 #define APB1PERIPH_BASE PERIPH_BASE
683 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
684 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
685 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
686 
688 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
689 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
690 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
691 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
692 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
693 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
694 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
695 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
696 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
697 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
698 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
699 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
700 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
701 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
702 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
703 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
704 
706 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
707 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
708 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
709 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
710 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
711 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
712 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
713 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
714 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
715 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
716 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
717 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
718 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
719 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
720 
722 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
723 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
724 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
725 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
726 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
727 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
728 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
729 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
730 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
731 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
732 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
733 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
734 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
735 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
736 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
737 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
738 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
739 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
740 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
741 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
742 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
743 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
744 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
745 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
746 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
747 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
748 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
749 
750 /* Debug MCU registers base address */
751 #define DBGMCU_BASE 0xE0042000U
752 
754 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
755 
756 #define USB_OTG_GLOBAL_BASE 0x000U
757 #define USB_OTG_DEVICE_BASE 0x800U
758 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
759 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
760 #define USB_OTG_EP_REG_SIZE 0x20U
761 #define USB_OTG_HOST_BASE 0x400U
762 #define USB_OTG_HOST_PORT_BASE 0x440U
763 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
764 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
765 #define USB_OTG_PCGCCTL_BASE 0xE00U
766 #define USB_OTG_FIFO_BASE 0x1000U
767 #define USB_OTG_FIFO_SIZE 0x1000U
768 
776 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
777 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
778 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
779 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
780 #define RTC ((RTC_TypeDef *) RTC_BASE)
781 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
782 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
783 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
784 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
785 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
786 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
787 #define USART2 ((USART_TypeDef *) USART2_BASE)
788 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
789 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
790 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
791 #define PWR ((PWR_TypeDef *) PWR_BASE)
792 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
793 #define USART1 ((USART_TypeDef *) USART1_BASE)
794 #define USART6 ((USART_TypeDef *) USART6_BASE)
795 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
796 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
797 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
798 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
799 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
800 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
801 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
802 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
803 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
804 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
805 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
806 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
807 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
808 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
809 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
810 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
811 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
812 #define CRC ((CRC_TypeDef *) CRC_BASE)
813 #define RCC ((RCC_TypeDef *) RCC_BASE)
814 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
815 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
816 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
817 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
818 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
819 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
820 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
821 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
822 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
823 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
824 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
825 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
826 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
827 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
828 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
829 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
830 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
831 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
832 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
833 
834 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
835 
836 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
837 
850 /******************************************************************************/
851 /* Peripheral Registers_Bits_Definition */
852 /******************************************************************************/
853 
854 /******************************************************************************/
855 /* */
856 /* Analog to Digital Converter */
857 /* */
858 /******************************************************************************/
859 /******************** Bit definition for ADC_SR register ********************/
860 #define ADC_SR_AWD 0x00000001U
861 #define ADC_SR_EOC 0x00000002U
862 #define ADC_SR_JEOC 0x00000004U
863 #define ADC_SR_JSTRT 0x00000008U
864 #define ADC_SR_STRT 0x00000010U
865 #define ADC_SR_OVR 0x00000020U
867 /******************* Bit definition for ADC_CR1 register ********************/
868 #define ADC_CR1_AWDCH 0x0000001FU
869 #define ADC_CR1_AWDCH_0 0x00000001U
870 #define ADC_CR1_AWDCH_1 0x00000002U
871 #define ADC_CR1_AWDCH_2 0x00000004U
872 #define ADC_CR1_AWDCH_3 0x00000008U
873 #define ADC_CR1_AWDCH_4 0x00000010U
874 #define ADC_CR1_EOCIE 0x00000020U
875 #define ADC_CR1_AWDIE 0x00000040U
876 #define ADC_CR1_JEOCIE 0x00000080U
877 #define ADC_CR1_SCAN 0x00000100U
878 #define ADC_CR1_AWDSGL 0x00000200U
879 #define ADC_CR1_JAUTO 0x00000400U
880 #define ADC_CR1_DISCEN 0x00000800U
881 #define ADC_CR1_JDISCEN 0x00001000U
882 #define ADC_CR1_DISCNUM 0x0000E000U
883 #define ADC_CR1_DISCNUM_0 0x00002000U
884 #define ADC_CR1_DISCNUM_1 0x00004000U
885 #define ADC_CR1_DISCNUM_2 0x00008000U
886 #define ADC_CR1_JAWDEN 0x00400000U
887 #define ADC_CR1_AWDEN 0x00800000U
888 #define ADC_CR1_RES 0x03000000U
889 #define ADC_CR1_RES_0 0x01000000U
890 #define ADC_CR1_RES_1 0x02000000U
891 #define ADC_CR1_OVRIE 0x04000000U
893 /******************* Bit definition for ADC_CR2 register ********************/
894 #define ADC_CR2_ADON 0x00000001U
895 #define ADC_CR2_CONT 0x00000002U
896 #define ADC_CR2_DMA 0x00000100U
897 #define ADC_CR2_DDS 0x00000200U
898 #define ADC_CR2_EOCS 0x00000400U
899 #define ADC_CR2_ALIGN 0x00000800U
900 #define ADC_CR2_JEXTSEL 0x000F0000U
901 #define ADC_CR2_JEXTSEL_0 0x00010000U
902 #define ADC_CR2_JEXTSEL_1 0x00020000U
903 #define ADC_CR2_JEXTSEL_2 0x00040000U
904 #define ADC_CR2_JEXTSEL_3 0x00080000U
905 #define ADC_CR2_JEXTEN 0x00300000U
906 #define ADC_CR2_JEXTEN_0 0x00100000U
907 #define ADC_CR2_JEXTEN_1 0x00200000U
908 #define ADC_CR2_JSWSTART 0x00400000U
909 #define ADC_CR2_EXTSEL 0x0F000000U
910 #define ADC_CR2_EXTSEL_0 0x01000000U
911 #define ADC_CR2_EXTSEL_1 0x02000000U
912 #define ADC_CR2_EXTSEL_2 0x04000000U
913 #define ADC_CR2_EXTSEL_3 0x08000000U
914 #define ADC_CR2_EXTEN 0x30000000U
915 #define ADC_CR2_EXTEN_0 0x10000000U
916 #define ADC_CR2_EXTEN_1 0x20000000U
917 #define ADC_CR2_SWSTART 0x40000000U
919 /****************** Bit definition for ADC_SMPR1 register *******************/
920 #define ADC_SMPR1_SMP10 0x00000007U
921 #define ADC_SMPR1_SMP10_0 0x00000001U
922 #define ADC_SMPR1_SMP10_1 0x00000002U
923 #define ADC_SMPR1_SMP10_2 0x00000004U
924 #define ADC_SMPR1_SMP11 0x00000038U
925 #define ADC_SMPR1_SMP11_0 0x00000008U
926 #define ADC_SMPR1_SMP11_1 0x00000010U
927 #define ADC_SMPR1_SMP11_2 0x00000020U
928 #define ADC_SMPR1_SMP12 0x000001C0U
929 #define ADC_SMPR1_SMP12_0 0x00000040U
930 #define ADC_SMPR1_SMP12_1 0x00000080U
931 #define ADC_SMPR1_SMP12_2 0x00000100U
932 #define ADC_SMPR1_SMP13 0x00000E00U
933 #define ADC_SMPR1_SMP13_0 0x00000200U
934 #define ADC_SMPR1_SMP13_1 0x00000400U
935 #define ADC_SMPR1_SMP13_2 0x00000800U
936 #define ADC_SMPR1_SMP14 0x00007000U
937 #define ADC_SMPR1_SMP14_0 0x00001000U
938 #define ADC_SMPR1_SMP14_1 0x00002000U
939 #define ADC_SMPR1_SMP14_2 0x00004000U
940 #define ADC_SMPR1_SMP15 0x00038000U
941 #define ADC_SMPR1_SMP15_0 0x00008000U
942 #define ADC_SMPR1_SMP15_1 0x00010000U
943 #define ADC_SMPR1_SMP15_2 0x00020000U
944 #define ADC_SMPR1_SMP16 0x001C0000U
945 #define ADC_SMPR1_SMP16_0 0x00040000U
946 #define ADC_SMPR1_SMP16_1 0x00080000U
947 #define ADC_SMPR1_SMP16_2 0x00100000U
948 #define ADC_SMPR1_SMP17 0x00E00000U
949 #define ADC_SMPR1_SMP17_0 0x00200000U
950 #define ADC_SMPR1_SMP17_1 0x00400000U
951 #define ADC_SMPR1_SMP17_2 0x00800000U
952 #define ADC_SMPR1_SMP18 0x07000000U
953 #define ADC_SMPR1_SMP18_0 0x01000000U
954 #define ADC_SMPR1_SMP18_1 0x02000000U
955 #define ADC_SMPR1_SMP18_2 0x04000000U
957 /****************** Bit definition for ADC_SMPR2 register *******************/
958 #define ADC_SMPR2_SMP0 0x00000007U
959 #define ADC_SMPR2_SMP0_0 0x00000001U
960 #define ADC_SMPR2_SMP0_1 0x00000002U
961 #define ADC_SMPR2_SMP0_2 0x00000004U
962 #define ADC_SMPR2_SMP1 0x00000038U
963 #define ADC_SMPR2_SMP1_0 0x00000008U
964 #define ADC_SMPR2_SMP1_1 0x00000010U
965 #define ADC_SMPR2_SMP1_2 0x00000020U
966 #define ADC_SMPR2_SMP2 0x000001C0U
967 #define ADC_SMPR2_SMP2_0 0x00000040U
968 #define ADC_SMPR2_SMP2_1 0x00000080U
969 #define ADC_SMPR2_SMP2_2 0x00000100U
970 #define ADC_SMPR2_SMP3 0x00000E00U
971 #define ADC_SMPR2_SMP3_0 0x00000200U
972 #define ADC_SMPR2_SMP3_1 0x00000400U
973 #define ADC_SMPR2_SMP3_2 0x00000800U
974 #define ADC_SMPR2_SMP4 0x00007000U
975 #define ADC_SMPR2_SMP4_0 0x00001000U
976 #define ADC_SMPR2_SMP4_1 0x00002000U
977 #define ADC_SMPR2_SMP4_2 0x00004000U
978 #define ADC_SMPR2_SMP5 0x00038000U
979 #define ADC_SMPR2_SMP5_0 0x00008000U
980 #define ADC_SMPR2_SMP5_1 0x00010000U
981 #define ADC_SMPR2_SMP5_2 0x00020000U
982 #define ADC_SMPR2_SMP6 0x001C0000U
983 #define ADC_SMPR2_SMP6_0 0x00040000U
984 #define ADC_SMPR2_SMP6_1 0x00080000U
985 #define ADC_SMPR2_SMP6_2 0x00100000U
986 #define ADC_SMPR2_SMP7 0x00E00000U
987 #define ADC_SMPR2_SMP7_0 0x00200000U
988 #define ADC_SMPR2_SMP7_1 0x00400000U
989 #define ADC_SMPR2_SMP7_2 0x00800000U
990 #define ADC_SMPR2_SMP8 0x07000000U
991 #define ADC_SMPR2_SMP8_0 0x01000000U
992 #define ADC_SMPR2_SMP8_1 0x02000000U
993 #define ADC_SMPR2_SMP8_2 0x04000000U
994 #define ADC_SMPR2_SMP9 0x38000000U
995 #define ADC_SMPR2_SMP9_0 0x08000000U
996 #define ADC_SMPR2_SMP9_1 0x10000000U
997 #define ADC_SMPR2_SMP9_2 0x20000000U
999 /****************** Bit definition for ADC_JOFR1 register *******************/
1000 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1002 /****************** Bit definition for ADC_JOFR2 register *******************/
1003 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1005 /****************** Bit definition for ADC_JOFR3 register *******************/
1006 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1008 /****************** Bit definition for ADC_JOFR4 register *******************/
1009 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1011 /******************* Bit definition for ADC_HTR register ********************/
1012 #define ADC_HTR_HT 0x0FFFU
1014 /******************* Bit definition for ADC_LTR register ********************/
1015 #define ADC_LTR_LT 0x0FFFU
1017 /******************* Bit definition for ADC_SQR1 register *******************/
1018 #define ADC_SQR1_SQ13 0x0000001FU
1019 #define ADC_SQR1_SQ13_0 0x00000001U
1020 #define ADC_SQR1_SQ13_1 0x00000002U
1021 #define ADC_SQR1_SQ13_2 0x00000004U
1022 #define ADC_SQR1_SQ13_3 0x00000008U
1023 #define ADC_SQR1_SQ13_4 0x00000010U
1024 #define ADC_SQR1_SQ14 0x000003E0U
1025 #define ADC_SQR1_SQ14_0 0x00000020U
1026 #define ADC_SQR1_SQ14_1 0x00000040U
1027 #define ADC_SQR1_SQ14_2 0x00000080U
1028 #define ADC_SQR1_SQ14_3 0x00000100U
1029 #define ADC_SQR1_SQ14_4 0x00000200U
1030 #define ADC_SQR1_SQ15 0x00007C00U
1031 #define ADC_SQR1_SQ15_0 0x00000400U
1032 #define ADC_SQR1_SQ15_1 0x00000800U
1033 #define ADC_SQR1_SQ15_2 0x00001000U
1034 #define ADC_SQR1_SQ15_3 0x00002000U
1035 #define ADC_SQR1_SQ15_4 0x00004000U
1036 #define ADC_SQR1_SQ16 0x000F8000U
1037 #define ADC_SQR1_SQ16_0 0x00008000U
1038 #define ADC_SQR1_SQ16_1 0x00010000U
1039 #define ADC_SQR1_SQ16_2 0x00020000U
1040 #define ADC_SQR1_SQ16_3 0x00040000U
1041 #define ADC_SQR1_SQ16_4 0x00080000U
1042 #define ADC_SQR1_L 0x00F00000U
1043 #define ADC_SQR1_L_0 0x00100000U
1044 #define ADC_SQR1_L_1 0x00200000U
1045 #define ADC_SQR1_L_2 0x00400000U
1046 #define ADC_SQR1_L_3 0x00800000U
1048 /******************* Bit definition for ADC_SQR2 register *******************/
1049 #define ADC_SQR2_SQ7 0x0000001FU
1050 #define ADC_SQR2_SQ7_0 0x00000001U
1051 #define ADC_SQR2_SQ7_1 0x00000002U
1052 #define ADC_SQR2_SQ7_2 0x00000004U
1053 #define ADC_SQR2_SQ7_3 0x00000008U
1054 #define ADC_SQR2_SQ7_4 0x00000010U
1055 #define ADC_SQR2_SQ8 0x000003E0U
1056 #define ADC_SQR2_SQ8_0 0x00000020U
1057 #define ADC_SQR2_SQ8_1 0x00000040U
1058 #define ADC_SQR2_SQ8_2 0x00000080U
1059 #define ADC_SQR2_SQ8_3 0x00000100U
1060 #define ADC_SQR2_SQ8_4 0x00000200U
1061 #define ADC_SQR2_SQ9 0x00007C00U
1062 #define ADC_SQR2_SQ9_0 0x00000400U
1063 #define ADC_SQR2_SQ9_1 0x00000800U
1064 #define ADC_SQR2_SQ9_2 0x00001000U
1065 #define ADC_SQR2_SQ9_3 0x00002000U
1066 #define ADC_SQR2_SQ9_4 0x00004000U
1067 #define ADC_SQR2_SQ10 0x000F8000U
1068 #define ADC_SQR2_SQ10_0 0x00008000U
1069 #define ADC_SQR2_SQ10_1 0x00010000U
1070 #define ADC_SQR2_SQ10_2 0x00020000U
1071 #define ADC_SQR2_SQ10_3 0x00040000U
1072 #define ADC_SQR2_SQ10_4 0x00080000U
1073 #define ADC_SQR2_SQ11 0x01F00000U
1074 #define ADC_SQR2_SQ11_0 0x00100000U
1075 #define ADC_SQR2_SQ11_1 0x00200000U
1076 #define ADC_SQR2_SQ11_2 0x00400000U
1077 #define ADC_SQR2_SQ11_3 0x00800000U
1078 #define ADC_SQR2_SQ11_4 0x01000000U
1079 #define ADC_SQR2_SQ12 0x3E000000U
1080 #define ADC_SQR2_SQ12_0 0x02000000U
1081 #define ADC_SQR2_SQ12_1 0x04000000U
1082 #define ADC_SQR2_SQ12_2 0x08000000U
1083 #define ADC_SQR2_SQ12_3 0x10000000U
1084 #define ADC_SQR2_SQ12_4 0x20000000U
1086 /******************* Bit definition for ADC_SQR3 register *******************/
1087 #define ADC_SQR3_SQ1 0x0000001FU
1088 #define ADC_SQR3_SQ1_0 0x00000001U
1089 #define ADC_SQR3_SQ1_1 0x00000002U
1090 #define ADC_SQR3_SQ1_2 0x00000004U
1091 #define ADC_SQR3_SQ1_3 0x00000008U
1092 #define ADC_SQR3_SQ1_4 0x00000010U
1093 #define ADC_SQR3_SQ2 0x000003E0U
1094 #define ADC_SQR3_SQ2_0 0x00000020U
1095 #define ADC_SQR3_SQ2_1 0x00000040U
1096 #define ADC_SQR3_SQ2_2 0x00000080U
1097 #define ADC_SQR3_SQ2_3 0x00000100U
1098 #define ADC_SQR3_SQ2_4 0x00000200U
1099 #define ADC_SQR3_SQ3 0x00007C00U
1100 #define ADC_SQR3_SQ3_0 0x00000400U
1101 #define ADC_SQR3_SQ3_1 0x00000800U
1102 #define ADC_SQR3_SQ3_2 0x00001000U
1103 #define ADC_SQR3_SQ3_3 0x00002000U
1104 #define ADC_SQR3_SQ3_4 0x00004000U
1105 #define ADC_SQR3_SQ4 0x000F8000U
1106 #define ADC_SQR3_SQ4_0 0x00008000U
1107 #define ADC_SQR3_SQ4_1 0x00010000U
1108 #define ADC_SQR3_SQ4_2 0x00020000U
1109 #define ADC_SQR3_SQ4_3 0x00040000U
1110 #define ADC_SQR3_SQ4_4 0x00080000U
1111 #define ADC_SQR3_SQ5 0x01F00000U
1112 #define ADC_SQR3_SQ5_0 0x00100000U
1113 #define ADC_SQR3_SQ5_1 0x00200000U
1114 #define ADC_SQR3_SQ5_2 0x00400000U
1115 #define ADC_SQR3_SQ5_3 0x00800000U
1116 #define ADC_SQR3_SQ5_4 0x01000000U
1117 #define ADC_SQR3_SQ6 0x3E000000U
1118 #define ADC_SQR3_SQ6_0 0x02000000U
1119 #define ADC_SQR3_SQ6_1 0x04000000U
1120 #define ADC_SQR3_SQ6_2 0x08000000U
1121 #define ADC_SQR3_SQ6_3 0x10000000U
1122 #define ADC_SQR3_SQ6_4 0x20000000U
1124 /******************* Bit definition for ADC_JSQR register *******************/
1125 #define ADC_JSQR_JSQ1 0x0000001FU
1126 #define ADC_JSQR_JSQ1_0 0x00000001U
1127 #define ADC_JSQR_JSQ1_1 0x00000002U
1128 #define ADC_JSQR_JSQ1_2 0x00000004U
1129 #define ADC_JSQR_JSQ1_3 0x00000008U
1130 #define ADC_JSQR_JSQ1_4 0x00000010U
1131 #define ADC_JSQR_JSQ2 0x000003E0U
1132 #define ADC_JSQR_JSQ2_0 0x00000020U
1133 #define ADC_JSQR_JSQ2_1 0x00000040U
1134 #define ADC_JSQR_JSQ2_2 0x00000080U
1135 #define ADC_JSQR_JSQ2_3 0x00000100U
1136 #define ADC_JSQR_JSQ2_4 0x00000200U
1137 #define ADC_JSQR_JSQ3 0x00007C00U
1138 #define ADC_JSQR_JSQ3_0 0x00000400U
1139 #define ADC_JSQR_JSQ3_1 0x00000800U
1140 #define ADC_JSQR_JSQ3_2 0x00001000U
1141 #define ADC_JSQR_JSQ3_3 0x00002000U
1142 #define ADC_JSQR_JSQ3_4 0x00004000U
1143 #define ADC_JSQR_JSQ4 0x000F8000U
1144 #define ADC_JSQR_JSQ4_0 0x00008000U
1145 #define ADC_JSQR_JSQ4_1 0x00010000U
1146 #define ADC_JSQR_JSQ4_2 0x00020000U
1147 #define ADC_JSQR_JSQ4_3 0x00040000U
1148 #define ADC_JSQR_JSQ4_4 0x00080000U
1149 #define ADC_JSQR_JL 0x00300000U
1150 #define ADC_JSQR_JL_0 0x00100000U
1151 #define ADC_JSQR_JL_1 0x00200000U
1153 /******************* Bit definition for ADC_JDR1 register *******************/
1154 #define ADC_JDR1_JDATA 0xFFFFU
1156 /******************* Bit definition for ADC_JDR2 register *******************/
1157 #define ADC_JDR2_JDATA 0xFFFFU
1159 /******************* Bit definition for ADC_JDR3 register *******************/
1160 #define ADC_JDR3_JDATA 0xFFFFU
1162 /******************* Bit definition for ADC_JDR4 register *******************/
1163 #define ADC_JDR4_JDATA 0xFFFFU
1165 /******************** Bit definition for ADC_DR register ********************/
1166 #define ADC_DR_DATA 0x0000FFFFU
1167 #define ADC_DR_ADC2DATA 0xFFFF0000U
1169 /******************* Bit definition for ADC_CSR register ********************/
1170 #define ADC_CSR_AWD1 0x00000001U
1171 #define ADC_CSR_EOC1 0x00000002U
1172 #define ADC_CSR_JEOC1 0x00000004U
1173 #define ADC_CSR_JSTRT1 0x00000008U
1174 #define ADC_CSR_STRT1 0x00000010U
1175 #define ADC_CSR_OVR1 0x00000020U
1176 #define ADC_CSR_AWD2 0x00000100U
1177 #define ADC_CSR_EOC2 0x00000200U
1178 #define ADC_CSR_JEOC2 0x00000400U
1179 #define ADC_CSR_JSTRT2 0x00000800U
1180 #define ADC_CSR_STRT2 0x00001000U
1181 #define ADC_CSR_OVR2 0x00002000U
1182 #define ADC_CSR_AWD3 0x00010000U
1183 #define ADC_CSR_EOC3 0x00020000U
1184 #define ADC_CSR_JEOC3 0x00040000U
1185 #define ADC_CSR_JSTRT3 0x00080000U
1186 #define ADC_CSR_STRT3 0x00100000U
1187 #define ADC_CSR_OVR3 0x00200000U
1189 /* Legacy defines */
1190 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1191 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1192 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1193 
1194 /******************* Bit definition for ADC_CCR register ********************/
1195 #define ADC_CCR_MULTI 0x0000001FU
1196 #define ADC_CCR_MULTI_0 0x00000001U
1197 #define ADC_CCR_MULTI_1 0x00000002U
1198 #define ADC_CCR_MULTI_2 0x00000004U
1199 #define ADC_CCR_MULTI_3 0x00000008U
1200 #define ADC_CCR_MULTI_4 0x00000010U
1201 #define ADC_CCR_DELAY 0x00000F00U
1202 #define ADC_CCR_DELAY_0 0x00000100U
1203 #define ADC_CCR_DELAY_1 0x00000200U
1204 #define ADC_CCR_DELAY_2 0x00000400U
1205 #define ADC_CCR_DELAY_3 0x00000800U
1206 #define ADC_CCR_DDS 0x00002000U
1207 #define ADC_CCR_DMA 0x0000C000U
1208 #define ADC_CCR_DMA_0 0x00004000U
1209 #define ADC_CCR_DMA_1 0x00008000U
1210 #define ADC_CCR_ADCPRE 0x00030000U
1211 #define ADC_CCR_ADCPRE_0 0x00010000U
1212 #define ADC_CCR_ADCPRE_1 0x00020000U
1213 #define ADC_CCR_VBATE 0x00400000U
1214 #define ADC_CCR_TSVREFE 0x00800000U
1216 /******************* Bit definition for ADC_CDR register ********************/
1217 #define ADC_CDR_DATA1 0x0000FFFFU
1218 #define ADC_CDR_DATA2 0xFFFF0000U
1220 /******************************************************************************/
1221 /* */
1222 /* CRC calculation unit */
1223 /* */
1224 /******************************************************************************/
1225 /******************* Bit definition for CRC_DR register *********************/
1226 #define CRC_DR_DR 0xFFFFFFFFU
1229 /******************* Bit definition for CRC_IDR register ********************/
1230 #define CRC_IDR_IDR 0xFFU
1233 /******************** Bit definition for CRC_CR register ********************/
1234 #define CRC_CR_RESET 0x01U
1236 /******************************************************************************/
1237 /* */
1238 /* Debug MCU */
1239 /* */
1240 /******************************************************************************/
1241 
1242 /******************************************************************************/
1243 /* */
1244 /* DMA Controller */
1245 /* */
1246 /******************************************************************************/
1247 /******************** Bits definition for DMA_SxCR register *****************/
1248 #define DMA_SxCR_CHSEL 0x0E000000U
1249 #define DMA_SxCR_CHSEL_0 0x02000000U
1250 #define DMA_SxCR_CHSEL_1 0x04000000U
1251 #define DMA_SxCR_CHSEL_2 0x08000000U
1252 #define DMA_SxCR_MBURST 0x01800000U
1253 #define DMA_SxCR_MBURST_0 0x00800000U
1254 #define DMA_SxCR_MBURST_1 0x01000000U
1255 #define DMA_SxCR_PBURST 0x00600000U
1256 #define DMA_SxCR_PBURST_0 0x00200000U
1257 #define DMA_SxCR_PBURST_1 0x00400000U
1258 #define DMA_SxCR_CT 0x00080000U
1259 #define DMA_SxCR_DBM 0x00040000U
1260 #define DMA_SxCR_PL 0x00030000U
1261 #define DMA_SxCR_PL_0 0x00010000U
1262 #define DMA_SxCR_PL_1 0x00020000U
1263 #define DMA_SxCR_PINCOS 0x00008000U
1264 #define DMA_SxCR_MSIZE 0x00006000U
1265 #define DMA_SxCR_MSIZE_0 0x00002000U
1266 #define DMA_SxCR_MSIZE_1 0x00004000U
1267 #define DMA_SxCR_PSIZE 0x00001800U
1268 #define DMA_SxCR_PSIZE_0 0x00000800U
1269 #define DMA_SxCR_PSIZE_1 0x00001000U
1270 #define DMA_SxCR_MINC 0x00000400U
1271 #define DMA_SxCR_PINC 0x00000200U
1272 #define DMA_SxCR_CIRC 0x00000100U
1273 #define DMA_SxCR_DIR 0x000000C0U
1274 #define DMA_SxCR_DIR_0 0x00000040U
1275 #define DMA_SxCR_DIR_1 0x00000080U
1276 #define DMA_SxCR_PFCTRL 0x00000020U
1277 #define DMA_SxCR_TCIE 0x00000010U
1278 #define DMA_SxCR_HTIE 0x00000008U
1279 #define DMA_SxCR_TEIE 0x00000004U
1280 #define DMA_SxCR_DMEIE 0x00000002U
1281 #define DMA_SxCR_EN 0x00000001U
1282 
1283 /* Legacy defines */
1284 #define DMA_SxCR_ACK 0x00100000U
1285 
1286 /******************** Bits definition for DMA_SxCNDTR register **************/
1287 #define DMA_SxNDT 0x0000FFFFU
1288 #define DMA_SxNDT_0 0x00000001U
1289 #define DMA_SxNDT_1 0x00000002U
1290 #define DMA_SxNDT_2 0x00000004U
1291 #define DMA_SxNDT_3 0x00000008U
1292 #define DMA_SxNDT_4 0x00000010U
1293 #define DMA_SxNDT_5 0x00000020U
1294 #define DMA_SxNDT_6 0x00000040U
1295 #define DMA_SxNDT_7 0x00000080U
1296 #define DMA_SxNDT_8 0x00000100U
1297 #define DMA_SxNDT_9 0x00000200U
1298 #define DMA_SxNDT_10 0x00000400U
1299 #define DMA_SxNDT_11 0x00000800U
1300 #define DMA_SxNDT_12 0x00001000U
1301 #define DMA_SxNDT_13 0x00002000U
1302 #define DMA_SxNDT_14 0x00004000U
1303 #define DMA_SxNDT_15 0x00008000U
1304 
1305 /******************** Bits definition for DMA_SxFCR register ****************/
1306 #define DMA_SxFCR_FEIE 0x00000080U
1307 #define DMA_SxFCR_FS 0x00000038U
1308 #define DMA_SxFCR_FS_0 0x00000008U
1309 #define DMA_SxFCR_FS_1 0x00000010U
1310 #define DMA_SxFCR_FS_2 0x00000020U
1311 #define DMA_SxFCR_DMDIS 0x00000004U
1312 #define DMA_SxFCR_FTH 0x00000003U
1313 #define DMA_SxFCR_FTH_0 0x00000001U
1314 #define DMA_SxFCR_FTH_1 0x00000002U
1315 
1316 /******************** Bits definition for DMA_LISR register *****************/
1317 #define DMA_LISR_TCIF3 0x08000000U
1318 #define DMA_LISR_HTIF3 0x04000000U
1319 #define DMA_LISR_TEIF3 0x02000000U
1320 #define DMA_LISR_DMEIF3 0x01000000U
1321 #define DMA_LISR_FEIF3 0x00400000U
1322 #define DMA_LISR_TCIF2 0x00200000U
1323 #define DMA_LISR_HTIF2 0x00100000U
1324 #define DMA_LISR_TEIF2 0x00080000U
1325 #define DMA_LISR_DMEIF2 0x00040000U
1326 #define DMA_LISR_FEIF2 0x00010000U
1327 #define DMA_LISR_TCIF1 0x00000800U
1328 #define DMA_LISR_HTIF1 0x00000400U
1329 #define DMA_LISR_TEIF1 0x00000200U
1330 #define DMA_LISR_DMEIF1 0x00000100U
1331 #define DMA_LISR_FEIF1 0x00000040U
1332 #define DMA_LISR_TCIF0 0x00000020U
1333 #define DMA_LISR_HTIF0 0x00000010U
1334 #define DMA_LISR_TEIF0 0x00000008U
1335 #define DMA_LISR_DMEIF0 0x00000004U
1336 #define DMA_LISR_FEIF0 0x00000001U
1337 
1338 /******************** Bits definition for DMA_HISR register *****************/
1339 #define DMA_HISR_TCIF7 0x08000000U
1340 #define DMA_HISR_HTIF7 0x04000000U
1341 #define DMA_HISR_TEIF7 0x02000000U
1342 #define DMA_HISR_DMEIF7 0x01000000U
1343 #define DMA_HISR_FEIF7 0x00400000U
1344 #define DMA_HISR_TCIF6 0x00200000U
1345 #define DMA_HISR_HTIF6 0x00100000U
1346 #define DMA_HISR_TEIF6 0x00080000U
1347 #define DMA_HISR_DMEIF6 0x00040000U
1348 #define DMA_HISR_FEIF6 0x00010000U
1349 #define DMA_HISR_TCIF5 0x00000800U
1350 #define DMA_HISR_HTIF5 0x00000400U
1351 #define DMA_HISR_TEIF5 0x00000200U
1352 #define DMA_HISR_DMEIF5 0x00000100U
1353 #define DMA_HISR_FEIF5 0x00000040U
1354 #define DMA_HISR_TCIF4 0x00000020U
1355 #define DMA_HISR_HTIF4 0x00000010U
1356 #define DMA_HISR_TEIF4 0x00000008U
1357 #define DMA_HISR_DMEIF4 0x00000004U
1358 #define DMA_HISR_FEIF4 0x00000001U
1359 
1360 /******************** Bits definition for DMA_LIFCR register ****************/
1361 #define DMA_LIFCR_CTCIF3 0x08000000U
1362 #define DMA_LIFCR_CHTIF3 0x04000000U
1363 #define DMA_LIFCR_CTEIF3 0x02000000U
1364 #define DMA_LIFCR_CDMEIF3 0x01000000U
1365 #define DMA_LIFCR_CFEIF3 0x00400000U
1366 #define DMA_LIFCR_CTCIF2 0x00200000U
1367 #define DMA_LIFCR_CHTIF2 0x00100000U
1368 #define DMA_LIFCR_CTEIF2 0x00080000U
1369 #define DMA_LIFCR_CDMEIF2 0x00040000U
1370 #define DMA_LIFCR_CFEIF2 0x00010000U
1371 #define DMA_LIFCR_CTCIF1 0x00000800U
1372 #define DMA_LIFCR_CHTIF1 0x00000400U
1373 #define DMA_LIFCR_CTEIF1 0x00000200U
1374 #define DMA_LIFCR_CDMEIF1 0x00000100U
1375 #define DMA_LIFCR_CFEIF1 0x00000040U
1376 #define DMA_LIFCR_CTCIF0 0x00000020U
1377 #define DMA_LIFCR_CHTIF0 0x00000010U
1378 #define DMA_LIFCR_CTEIF0 0x00000008U
1379 #define DMA_LIFCR_CDMEIF0 0x00000004U
1380 #define DMA_LIFCR_CFEIF0 0x00000001U
1381 
1382 /******************** Bits definition for DMA_HIFCR register ****************/
1383 #define DMA_HIFCR_CTCIF7 0x08000000U
1384 #define DMA_HIFCR_CHTIF7 0x04000000U
1385 #define DMA_HIFCR_CTEIF7 0x02000000U
1386 #define DMA_HIFCR_CDMEIF7 0x01000000U
1387 #define DMA_HIFCR_CFEIF7 0x00400000U
1388 #define DMA_HIFCR_CTCIF6 0x00200000U
1389 #define DMA_HIFCR_CHTIF6 0x00100000U
1390 #define DMA_HIFCR_CTEIF6 0x00080000U
1391 #define DMA_HIFCR_CDMEIF6 0x00040000U
1392 #define DMA_HIFCR_CFEIF6 0x00010000U
1393 #define DMA_HIFCR_CTCIF5 0x00000800U
1394 #define DMA_HIFCR_CHTIF5 0x00000400U
1395 #define DMA_HIFCR_CTEIF5 0x00000200U
1396 #define DMA_HIFCR_CDMEIF5 0x00000100U
1397 #define DMA_HIFCR_CFEIF5 0x00000040U
1398 #define DMA_HIFCR_CTCIF4 0x00000020U
1399 #define DMA_HIFCR_CHTIF4 0x00000010U
1400 #define DMA_HIFCR_CTEIF4 0x00000008U
1401 #define DMA_HIFCR_CDMEIF4 0x00000004U
1402 #define DMA_HIFCR_CFEIF4 0x00000001U
1403 
1404 
1405 /******************************************************************************/
1406 /* */
1407 /* External Interrupt/Event Controller */
1408 /* */
1409 /******************************************************************************/
1410 /******************* Bit definition for EXTI_IMR register *******************/
1411 #define EXTI_IMR_MR0 0x00000001U
1412 #define EXTI_IMR_MR1 0x00000002U
1413 #define EXTI_IMR_MR2 0x00000004U
1414 #define EXTI_IMR_MR3 0x00000008U
1415 #define EXTI_IMR_MR4 0x00000010U
1416 #define EXTI_IMR_MR5 0x00000020U
1417 #define EXTI_IMR_MR6 0x00000040U
1418 #define EXTI_IMR_MR7 0x00000080U
1419 #define EXTI_IMR_MR8 0x00000100U
1420 #define EXTI_IMR_MR9 0x00000200U
1421 #define EXTI_IMR_MR10 0x00000400U
1422 #define EXTI_IMR_MR11 0x00000800U
1423 #define EXTI_IMR_MR12 0x00001000U
1424 #define EXTI_IMR_MR13 0x00002000U
1425 #define EXTI_IMR_MR14 0x00004000U
1426 #define EXTI_IMR_MR15 0x00008000U
1427 #define EXTI_IMR_MR16 0x00010000U
1428 #define EXTI_IMR_MR17 0x00020000U
1429 #define EXTI_IMR_MR18 0x00040000U
1430 #define EXTI_IMR_MR19 0x00080000U
1431 #define EXTI_IMR_MR20 0x00100000U
1432 #define EXTI_IMR_MR21 0x00200000U
1433 #define EXTI_IMR_MR22 0x00400000U
1435 /******************* Bit definition for EXTI_EMR register *******************/
1436 #define EXTI_EMR_MR0 0x00000001U
1437 #define EXTI_EMR_MR1 0x00000002U
1438 #define EXTI_EMR_MR2 0x00000004U
1439 #define EXTI_EMR_MR3 0x00000008U
1440 #define EXTI_EMR_MR4 0x00000010U
1441 #define EXTI_EMR_MR5 0x00000020U
1442 #define EXTI_EMR_MR6 0x00000040U
1443 #define EXTI_EMR_MR7 0x00000080U
1444 #define EXTI_EMR_MR8 0x00000100U
1445 #define EXTI_EMR_MR9 0x00000200U
1446 #define EXTI_EMR_MR10 0x00000400U
1447 #define EXTI_EMR_MR11 0x00000800U
1448 #define EXTI_EMR_MR12 0x00001000U
1449 #define EXTI_EMR_MR13 0x00002000U
1450 #define EXTI_EMR_MR14 0x00004000U
1451 #define EXTI_EMR_MR15 0x00008000U
1452 #define EXTI_EMR_MR16 0x00010000U
1453 #define EXTI_EMR_MR17 0x00020000U
1454 #define EXTI_EMR_MR18 0x00040000U
1455 #define EXTI_EMR_MR19 0x00080000U
1456 #define EXTI_EMR_MR20 0x00100000U
1457 #define EXTI_EMR_MR21 0x00200000U
1458 #define EXTI_EMR_MR22 0x00400000U
1460 /****************** Bit definition for EXTI_RTSR register *******************/
1461 #define EXTI_RTSR_TR0 0x00000001U
1462 #define EXTI_RTSR_TR1 0x00000002U
1463 #define EXTI_RTSR_TR2 0x00000004U
1464 #define EXTI_RTSR_TR3 0x00000008U
1465 #define EXTI_RTSR_TR4 0x00000010U
1466 #define EXTI_RTSR_TR5 0x00000020U
1467 #define EXTI_RTSR_TR6 0x00000040U
1468 #define EXTI_RTSR_TR7 0x00000080U
1469 #define EXTI_RTSR_TR8 0x00000100U
1470 #define EXTI_RTSR_TR9 0x00000200U
1471 #define EXTI_RTSR_TR10 0x00000400U
1472 #define EXTI_RTSR_TR11 0x00000800U
1473 #define EXTI_RTSR_TR12 0x00001000U
1474 #define EXTI_RTSR_TR13 0x00002000U
1475 #define EXTI_RTSR_TR14 0x00004000U
1476 #define EXTI_RTSR_TR15 0x00008000U
1477 #define EXTI_RTSR_TR16 0x00010000U
1478 #define EXTI_RTSR_TR17 0x00020000U
1479 #define EXTI_RTSR_TR18 0x00040000U
1480 #define EXTI_RTSR_TR19 0x00080000U
1481 #define EXTI_RTSR_TR20 0x00100000U
1482 #define EXTI_RTSR_TR21 0x00200000U
1483 #define EXTI_RTSR_TR22 0x00400000U
1485 /****************** Bit definition for EXTI_FTSR register *******************/
1486 #define EXTI_FTSR_TR0 0x00000001U
1487 #define EXTI_FTSR_TR1 0x00000002U
1488 #define EXTI_FTSR_TR2 0x00000004U
1489 #define EXTI_FTSR_TR3 0x00000008U
1490 #define EXTI_FTSR_TR4 0x00000010U
1491 #define EXTI_FTSR_TR5 0x00000020U
1492 #define EXTI_FTSR_TR6 0x00000040U
1493 #define EXTI_FTSR_TR7 0x00000080U
1494 #define EXTI_FTSR_TR8 0x00000100U
1495 #define EXTI_FTSR_TR9 0x00000200U
1496 #define EXTI_FTSR_TR10 0x00000400U
1497 #define EXTI_FTSR_TR11 0x00000800U
1498 #define EXTI_FTSR_TR12 0x00001000U
1499 #define EXTI_FTSR_TR13 0x00002000U
1500 #define EXTI_FTSR_TR14 0x00004000U
1501 #define EXTI_FTSR_TR15 0x00008000U
1502 #define EXTI_FTSR_TR16 0x00010000U
1503 #define EXTI_FTSR_TR17 0x00020000U
1504 #define EXTI_FTSR_TR18 0x00040000U
1505 #define EXTI_FTSR_TR19 0x00080000U
1506 #define EXTI_FTSR_TR20 0x00100000U
1507 #define EXTI_FTSR_TR21 0x00200000U
1508 #define EXTI_FTSR_TR22 0x00400000U
1510 /****************** Bit definition for EXTI_SWIER register ******************/
1511 #define EXTI_SWIER_SWIER0 0x00000001U
1512 #define EXTI_SWIER_SWIER1 0x00000002U
1513 #define EXTI_SWIER_SWIER2 0x00000004U
1514 #define EXTI_SWIER_SWIER3 0x00000008U
1515 #define EXTI_SWIER_SWIER4 0x00000010U
1516 #define EXTI_SWIER_SWIER5 0x00000020U
1517 #define EXTI_SWIER_SWIER6 0x00000040U
1518 #define EXTI_SWIER_SWIER7 0x00000080U
1519 #define EXTI_SWIER_SWIER8 0x00000100U
1520 #define EXTI_SWIER_SWIER9 0x00000200U
1521 #define EXTI_SWIER_SWIER10 0x00000400U
1522 #define EXTI_SWIER_SWIER11 0x00000800U
1523 #define EXTI_SWIER_SWIER12 0x00001000U
1524 #define EXTI_SWIER_SWIER13 0x00002000U
1525 #define EXTI_SWIER_SWIER14 0x00004000U
1526 #define EXTI_SWIER_SWIER15 0x00008000U
1527 #define EXTI_SWIER_SWIER16 0x00010000U
1528 #define EXTI_SWIER_SWIER17 0x00020000U
1529 #define EXTI_SWIER_SWIER18 0x00040000U
1530 #define EXTI_SWIER_SWIER19 0x00080000U
1531 #define EXTI_SWIER_SWIER20 0x00100000U
1532 #define EXTI_SWIER_SWIER21 0x00200000U
1533 #define EXTI_SWIER_SWIER22 0x00400000U
1535 /******************* Bit definition for EXTI_PR register ********************/
1536 #define EXTI_PR_PR0 0x00000001U
1537 #define EXTI_PR_PR1 0x00000002U
1538 #define EXTI_PR_PR2 0x00000004U
1539 #define EXTI_PR_PR3 0x00000008U
1540 #define EXTI_PR_PR4 0x00000010U
1541 #define EXTI_PR_PR5 0x00000020U
1542 #define EXTI_PR_PR6 0x00000040U
1543 #define EXTI_PR_PR7 0x00000080U
1544 #define EXTI_PR_PR8 0x00000100U
1545 #define EXTI_PR_PR9 0x00000200U
1546 #define EXTI_PR_PR10 0x00000400U
1547 #define EXTI_PR_PR11 0x00000800U
1548 #define EXTI_PR_PR12 0x00001000U
1549 #define EXTI_PR_PR13 0x00002000U
1550 #define EXTI_PR_PR14 0x00004000U
1551 #define EXTI_PR_PR15 0x00008000U
1552 #define EXTI_PR_PR16 0x00010000U
1553 #define EXTI_PR_PR17 0x00020000U
1554 #define EXTI_PR_PR18 0x00040000U
1555 #define EXTI_PR_PR19 0x00080000U
1556 #define EXTI_PR_PR20 0x00100000U
1557 #define EXTI_PR_PR21 0x00200000U
1558 #define EXTI_PR_PR22 0x00400000U
1560 /******************************************************************************/
1561 /* */
1562 /* FLASH */
1563 /* */
1564 /******************************************************************************/
1565 /******************* Bits definition for FLASH_ACR register *****************/
1566 #define FLASH_ACR_LATENCY 0x0000000FU
1567 #define FLASH_ACR_LATENCY_0WS 0x00000000U
1568 #define FLASH_ACR_LATENCY_1WS 0x00000001U
1569 #define FLASH_ACR_LATENCY_2WS 0x00000002U
1570 #define FLASH_ACR_LATENCY_3WS 0x00000003U
1571 #define FLASH_ACR_LATENCY_4WS 0x00000004U
1572 #define FLASH_ACR_LATENCY_5WS 0x00000005U
1573 #define FLASH_ACR_LATENCY_6WS 0x00000006U
1574 #define FLASH_ACR_LATENCY_7WS 0x00000007U
1575 
1576 #define FLASH_ACR_PRFTEN 0x00000100U
1577 #define FLASH_ACR_ICEN 0x00000200U
1578 #define FLASH_ACR_DCEN 0x00000400U
1579 #define FLASH_ACR_ICRST 0x00000800U
1580 #define FLASH_ACR_DCRST 0x00001000U
1581 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
1582 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
1583 
1584 /******************* Bits definition for FLASH_SR register ******************/
1585 #define FLASH_SR_EOP 0x00000001U
1586 #define FLASH_SR_SOP 0x00000002U
1587 #define FLASH_SR_WRPERR 0x00000010U
1588 #define FLASH_SR_PGAERR 0x00000020U
1589 #define FLASH_SR_PGPERR 0x00000040U
1590 #define FLASH_SR_PGSERR 0x00000080U
1591 #define FLASH_SR_BSY 0x00010000U
1592 
1593 /******************* Bits definition for FLASH_CR register ******************/
1594 #define FLASH_CR_PG 0x00000001U
1595 #define FLASH_CR_SER 0x00000002U
1596 #define FLASH_CR_MER 0x00000004U
1597 #define FLASH_CR_SNB 0x000000F8U
1598 #define FLASH_CR_SNB_0 0x00000008U
1599 #define FLASH_CR_SNB_1 0x00000010U
1600 #define FLASH_CR_SNB_2 0x00000020U
1601 #define FLASH_CR_SNB_3 0x00000040U
1602 #define FLASH_CR_SNB_4 0x00000080U
1603 #define FLASH_CR_PSIZE 0x00000300U
1604 #define FLASH_CR_PSIZE_0 0x00000100U
1605 #define FLASH_CR_PSIZE_1 0x00000200U
1606 #define FLASH_CR_STRT 0x00010000U
1607 #define FLASH_CR_EOPIE 0x01000000U
1608 #define FLASH_CR_LOCK 0x80000000U
1609 
1610 /******************* Bits definition for FLASH_OPTCR register ***************/
1611 #define FLASH_OPTCR_OPTLOCK 0x00000001U
1612 #define FLASH_OPTCR_OPTSTRT 0x00000002U
1613 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
1614 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
1615 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
1616 
1617 #define FLASH_OPTCR_WDG_SW 0x00000020U
1618 #define FLASH_OPTCR_nRST_STOP 0x00000040U
1619 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
1620 #define FLASH_OPTCR_RDP 0x0000FF00U
1621 #define FLASH_OPTCR_RDP_0 0x00000100U
1622 #define FLASH_OPTCR_RDP_1 0x00000200U
1623 #define FLASH_OPTCR_RDP_2 0x00000400U
1624 #define FLASH_OPTCR_RDP_3 0x00000800U
1625 #define FLASH_OPTCR_RDP_4 0x00001000U
1626 #define FLASH_OPTCR_RDP_5 0x00002000U
1627 #define FLASH_OPTCR_RDP_6 0x00004000U
1628 #define FLASH_OPTCR_RDP_7 0x00008000U
1629 #define FLASH_OPTCR_nWRP 0x0FFF0000U
1630 #define FLASH_OPTCR_nWRP_0 0x00010000U
1631 #define FLASH_OPTCR_nWRP_1 0x00020000U
1632 #define FLASH_OPTCR_nWRP_2 0x00040000U
1633 #define FLASH_OPTCR_nWRP_3 0x00080000U
1634 #define FLASH_OPTCR_nWRP_4 0x00100000U
1635 #define FLASH_OPTCR_nWRP_5 0x00200000U
1636 #define FLASH_OPTCR_nWRP_6 0x00400000U
1637 #define FLASH_OPTCR_nWRP_7 0x00800000U
1638 #define FLASH_OPTCR_nWRP_8 0x01000000U
1639 #define FLASH_OPTCR_nWRP_9 0x02000000U
1640 #define FLASH_OPTCR_nWRP_10 0x04000000U
1641 #define FLASH_OPTCR_nWRP_11 0x08000000U
1642 
1643 /****************** Bits definition for FLASH_OPTCR1 register ***************/
1644 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
1645 #define FLASH_OPTCR1_nWRP_0 0x00010000U
1646 #define FLASH_OPTCR1_nWRP_1 0x00020000U
1647 #define FLASH_OPTCR1_nWRP_2 0x00040000U
1648 #define FLASH_OPTCR1_nWRP_3 0x00080000U
1649 #define FLASH_OPTCR1_nWRP_4 0x00100000U
1650 #define FLASH_OPTCR1_nWRP_5 0x00200000U
1651 #define FLASH_OPTCR1_nWRP_6 0x00400000U
1652 #define FLASH_OPTCR1_nWRP_7 0x00800000U
1653 #define FLASH_OPTCR1_nWRP_8 0x01000000U
1654 #define FLASH_OPTCR1_nWRP_9 0x02000000U
1655 #define FLASH_OPTCR1_nWRP_10 0x04000000U
1656 #define FLASH_OPTCR1_nWRP_11 0x08000000U
1657 
1658 /******************************************************************************/
1659 /* */
1660 /* General Purpose I/O */
1661 /* */
1662 /******************************************************************************/
1663 /****************** Bits definition for GPIO_MODER register *****************/
1664 #define GPIO_MODER_MODER0 0x00000003U
1665 #define GPIO_MODER_MODER0_0 0x00000001U
1666 #define GPIO_MODER_MODER0_1 0x00000002U
1667 
1668 #define GPIO_MODER_MODER1 0x0000000CU
1669 #define GPIO_MODER_MODER1_0 0x00000004U
1670 #define GPIO_MODER_MODER1_1 0x00000008U
1671 
1672 #define GPIO_MODER_MODER2 0x00000030U
1673 #define GPIO_MODER_MODER2_0 0x00000010U
1674 #define GPIO_MODER_MODER2_1 0x00000020U
1675 
1676 #define GPIO_MODER_MODER3 0x000000C0U
1677 #define GPIO_MODER_MODER3_0 0x00000040U
1678 #define GPIO_MODER_MODER3_1 0x00000080U
1679 
1680 #define GPIO_MODER_MODER4 0x00000300U
1681 #define GPIO_MODER_MODER4_0 0x00000100U
1682 #define GPIO_MODER_MODER4_1 0x00000200U
1683 
1684 #define GPIO_MODER_MODER5 0x00000C00U
1685 #define GPIO_MODER_MODER5_0 0x00000400U
1686 #define GPIO_MODER_MODER5_1 0x00000800U
1687 
1688 #define GPIO_MODER_MODER6 0x00003000U
1689 #define GPIO_MODER_MODER6_0 0x00001000U
1690 #define GPIO_MODER_MODER6_1 0x00002000U
1691 
1692 #define GPIO_MODER_MODER7 0x0000C000U
1693 #define GPIO_MODER_MODER7_0 0x00004000U
1694 #define GPIO_MODER_MODER7_1 0x00008000U
1695 
1696 #define GPIO_MODER_MODER8 0x00030000U
1697 #define GPIO_MODER_MODER8_0 0x00010000U
1698 #define GPIO_MODER_MODER8_1 0x00020000U
1699 
1700 #define GPIO_MODER_MODER9 0x000C0000U
1701 #define GPIO_MODER_MODER9_0 0x00040000U
1702 #define GPIO_MODER_MODER9_1 0x00080000U
1703 
1704 #define GPIO_MODER_MODER10 0x00300000U
1705 #define GPIO_MODER_MODER10_0 0x00100000U
1706 #define GPIO_MODER_MODER10_1 0x00200000U
1707 
1708 #define GPIO_MODER_MODER11 0x00C00000U
1709 #define GPIO_MODER_MODER11_0 0x00400000U
1710 #define GPIO_MODER_MODER11_1 0x00800000U
1711 
1712 #define GPIO_MODER_MODER12 0x03000000U
1713 #define GPIO_MODER_MODER12_0 0x01000000U
1714 #define GPIO_MODER_MODER12_1 0x02000000U
1715 
1716 #define GPIO_MODER_MODER13 0x0C000000U
1717 #define GPIO_MODER_MODER13_0 0x04000000U
1718 #define GPIO_MODER_MODER13_1 0x08000000U
1719 
1720 #define GPIO_MODER_MODER14 0x30000000U
1721 #define GPIO_MODER_MODER14_0 0x10000000U
1722 #define GPIO_MODER_MODER14_1 0x20000000U
1723 
1724 #define GPIO_MODER_MODER15 0xC0000000U
1725 #define GPIO_MODER_MODER15_0 0x40000000U
1726 #define GPIO_MODER_MODER15_1 0x80000000U
1727 
1728 /****************** Bits definition for GPIO_OTYPER register ****************/
1729 #define GPIO_OTYPER_OT_0 0x00000001U
1730 #define GPIO_OTYPER_OT_1 0x00000002U
1731 #define GPIO_OTYPER_OT_2 0x00000004U
1732 #define GPIO_OTYPER_OT_3 0x00000008U
1733 #define GPIO_OTYPER_OT_4 0x00000010U
1734 #define GPIO_OTYPER_OT_5 0x00000020U
1735 #define GPIO_OTYPER_OT_6 0x00000040U
1736 #define GPIO_OTYPER_OT_7 0x00000080U
1737 #define GPIO_OTYPER_OT_8 0x00000100U
1738 #define GPIO_OTYPER_OT_9 0x00000200U
1739 #define GPIO_OTYPER_OT_10 0x00000400U
1740 #define GPIO_OTYPER_OT_11 0x00000800U
1741 #define GPIO_OTYPER_OT_12 0x00001000U
1742 #define GPIO_OTYPER_OT_13 0x00002000U
1743 #define GPIO_OTYPER_OT_14 0x00004000U
1744 #define GPIO_OTYPER_OT_15 0x00008000U
1745 
1746 /****************** Bits definition for GPIO_OSPEEDR register ***************/
1747 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
1748 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
1749 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
1750 
1751 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
1752 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
1753 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
1754 
1755 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
1756 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
1757 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
1758 
1759 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
1760 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
1761 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
1762 
1763 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
1764 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
1765 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
1766 
1767 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
1768 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
1769 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
1770 
1771 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
1772 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
1773 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
1774 
1775 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
1776 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
1777 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
1778 
1779 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
1780 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
1781 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
1782 
1783 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
1784 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
1785 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
1786 
1787 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
1788 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
1789 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
1790 
1791 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
1792 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
1793 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
1794 
1795 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
1796 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
1797 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
1798 
1799 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
1800 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
1801 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
1802 
1803 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
1804 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
1805 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
1806 
1807 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
1808 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
1809 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
1810 
1811 /****************** Bits definition for GPIO_PUPDR register *****************/
1812 #define GPIO_PUPDR_PUPDR0 0x00000003U
1813 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
1814 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
1815 
1816 #define GPIO_PUPDR_PUPDR1 0x0000000CU
1817 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
1818 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
1819 
1820 #define GPIO_PUPDR_PUPDR2 0x00000030U
1821 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
1822 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
1823 
1824 #define GPIO_PUPDR_PUPDR3 0x000000C0U
1825 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
1826 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
1827 
1828 #define GPIO_PUPDR_PUPDR4 0x00000300U
1829 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
1830 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
1831 
1832 #define GPIO_PUPDR_PUPDR5 0x00000C00U
1833 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
1834 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
1835 
1836 #define GPIO_PUPDR_PUPDR6 0x00003000U
1837 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
1838 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
1839 
1840 #define GPIO_PUPDR_PUPDR7 0x0000C000U
1841 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
1842 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
1843 
1844 #define GPIO_PUPDR_PUPDR8 0x00030000U
1845 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
1846 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
1847 
1848 #define GPIO_PUPDR_PUPDR9 0x000C0000U
1849 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
1850 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
1851 
1852 #define GPIO_PUPDR_PUPDR10 0x00300000U
1853 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
1854 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
1855 
1856 #define GPIO_PUPDR_PUPDR11 0x00C00000U
1857 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
1858 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
1859 
1860 #define GPIO_PUPDR_PUPDR12 0x03000000U
1861 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
1862 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
1863 
1864 #define GPIO_PUPDR_PUPDR13 0x0C000000U
1865 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
1866 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
1867 
1868 #define GPIO_PUPDR_PUPDR14 0x30000000U
1869 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
1870 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
1871 
1872 #define GPIO_PUPDR_PUPDR15 0xC0000000U
1873 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
1874 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
1875 
1876 /****************** Bits definition for GPIO_IDR register *******************/
1877 #define GPIO_IDR_IDR_0 0x00000001U
1878 #define GPIO_IDR_IDR_1 0x00000002U
1879 #define GPIO_IDR_IDR_2 0x00000004U
1880 #define GPIO_IDR_IDR_3 0x00000008U
1881 #define GPIO_IDR_IDR_4 0x00000010U
1882 #define GPIO_IDR_IDR_5 0x00000020U
1883 #define GPIO_IDR_IDR_6 0x00000040U
1884 #define GPIO_IDR_IDR_7 0x00000080U
1885 #define GPIO_IDR_IDR_8 0x00000100U
1886 #define GPIO_IDR_IDR_9 0x00000200U
1887 #define GPIO_IDR_IDR_10 0x00000400U
1888 #define GPIO_IDR_IDR_11 0x00000800U
1889 #define GPIO_IDR_IDR_12 0x00001000U
1890 #define GPIO_IDR_IDR_13 0x00002000U
1891 #define GPIO_IDR_IDR_14 0x00004000U
1892 #define GPIO_IDR_IDR_15 0x00008000U
1893 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
1894 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
1895 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
1896 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
1897 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
1898 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
1899 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
1900 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
1901 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
1902 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
1903 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
1904 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
1905 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
1906 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
1907 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
1908 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
1909 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
1910 
1911 /****************** Bits definition for GPIO_ODR register *******************/
1912 #define GPIO_ODR_ODR_0 0x00000001U
1913 #define GPIO_ODR_ODR_1 0x00000002U
1914 #define GPIO_ODR_ODR_2 0x00000004U
1915 #define GPIO_ODR_ODR_3 0x00000008U
1916 #define GPIO_ODR_ODR_4 0x00000010U
1917 #define GPIO_ODR_ODR_5 0x00000020U
1918 #define GPIO_ODR_ODR_6 0x00000040U
1919 #define GPIO_ODR_ODR_7 0x00000080U
1920 #define GPIO_ODR_ODR_8 0x00000100U
1921 #define GPIO_ODR_ODR_9 0x00000200U
1922 #define GPIO_ODR_ODR_10 0x00000400U
1923 #define GPIO_ODR_ODR_11 0x00000800U
1924 #define GPIO_ODR_ODR_12 0x00001000U
1925 #define GPIO_ODR_ODR_13 0x00002000U
1926 #define GPIO_ODR_ODR_14 0x00004000U
1927 #define GPIO_ODR_ODR_15 0x00008000U
1928 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
1929 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
1930 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
1931 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
1932 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
1933 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
1934 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
1935 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
1936 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
1937 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
1938 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
1939 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
1940 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
1941 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
1942 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
1943 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
1944 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
1945 
1946 /****************** Bits definition for GPIO_BSRR register ******************/
1947 #define GPIO_BSRR_BS_0 0x00000001U
1948 #define GPIO_BSRR_BS_1 0x00000002U
1949 #define GPIO_BSRR_BS_2 0x00000004U
1950 #define GPIO_BSRR_BS_3 0x00000008U
1951 #define GPIO_BSRR_BS_4 0x00000010U
1952 #define GPIO_BSRR_BS_5 0x00000020U
1953 #define GPIO_BSRR_BS_6 0x00000040U
1954 #define GPIO_BSRR_BS_7 0x00000080U
1955 #define GPIO_BSRR_BS_8 0x00000100U
1956 #define GPIO_BSRR_BS_9 0x00000200U
1957 #define GPIO_BSRR_BS_10 0x00000400U
1958 #define GPIO_BSRR_BS_11 0x00000800U
1959 #define GPIO_BSRR_BS_12 0x00001000U
1960 #define GPIO_BSRR_BS_13 0x00002000U
1961 #define GPIO_BSRR_BS_14 0x00004000U
1962 #define GPIO_BSRR_BS_15 0x00008000U
1963 #define GPIO_BSRR_BR_0 0x00010000U
1964 #define GPIO_BSRR_BR_1 0x00020000U
1965 #define GPIO_BSRR_BR_2 0x00040000U
1966 #define GPIO_BSRR_BR_3 0x00080000U
1967 #define GPIO_BSRR_BR_4 0x00100000U
1968 #define GPIO_BSRR_BR_5 0x00200000U
1969 #define GPIO_BSRR_BR_6 0x00400000U
1970 #define GPIO_BSRR_BR_7 0x00800000U
1971 #define GPIO_BSRR_BR_8 0x01000000U
1972 #define GPIO_BSRR_BR_9 0x02000000U
1973 #define GPIO_BSRR_BR_10 0x04000000U
1974 #define GPIO_BSRR_BR_11 0x08000000U
1975 #define GPIO_BSRR_BR_12 0x10000000U
1976 #define GPIO_BSRR_BR_13 0x20000000U
1977 #define GPIO_BSRR_BR_14 0x40000000U
1978 #define GPIO_BSRR_BR_15 0x80000000U
1979 
1980 /****************** Bit definition for GPIO_LCKR register *********************/
1981 #define GPIO_LCKR_LCK0 0x00000001U
1982 #define GPIO_LCKR_LCK1 0x00000002U
1983 #define GPIO_LCKR_LCK2 0x00000004U
1984 #define GPIO_LCKR_LCK3 0x00000008U
1985 #define GPIO_LCKR_LCK4 0x00000010U
1986 #define GPIO_LCKR_LCK5 0x00000020U
1987 #define GPIO_LCKR_LCK6 0x00000040U
1988 #define GPIO_LCKR_LCK7 0x00000080U
1989 #define GPIO_LCKR_LCK8 0x00000100U
1990 #define GPIO_LCKR_LCK9 0x00000200U
1991 #define GPIO_LCKR_LCK10 0x00000400U
1992 #define GPIO_LCKR_LCK11 0x00000800U
1993 #define GPIO_LCKR_LCK12 0x00001000U
1994 #define GPIO_LCKR_LCK13 0x00002000U
1995 #define GPIO_LCKR_LCK14 0x00004000U
1996 #define GPIO_LCKR_LCK15 0x00008000U
1997 #define GPIO_LCKR_LCKK 0x00010000U
1998 
1999 /******************************************************************************/
2000 /* */
2001 /* Inter-integrated Circuit Interface */
2002 /* */
2003 /******************************************************************************/
2004 /******************* Bit definition for I2C_CR1 register ********************/
2005 #define I2C_CR1_PE 0x00000001U
2006 #define I2C_CR1_SMBUS 0x00000002U
2007 #define I2C_CR1_SMBTYPE 0x00000008U
2008 #define I2C_CR1_ENARP 0x00000010U
2009 #define I2C_CR1_ENPEC 0x00000020U
2010 #define I2C_CR1_ENGC 0x00000040U
2011 #define I2C_CR1_NOSTRETCH 0x00000080U
2012 #define I2C_CR1_START 0x00000100U
2013 #define I2C_CR1_STOP 0x00000200U
2014 #define I2C_CR1_ACK 0x00000400U
2015 #define I2C_CR1_POS 0x00000800U
2016 #define I2C_CR1_PEC 0x00001000U
2017 #define I2C_CR1_ALERT 0x00002000U
2018 #define I2C_CR1_SWRST 0x00008000U
2020 /******************* Bit definition for I2C_CR2 register ********************/
2021 #define I2C_CR2_FREQ 0x0000003FU
2022 #define I2C_CR2_FREQ_0 0x00000001U
2023 #define I2C_CR2_FREQ_1 0x00000002U
2024 #define I2C_CR2_FREQ_2 0x00000004U
2025 #define I2C_CR2_FREQ_3 0x00000008U
2026 #define I2C_CR2_FREQ_4 0x00000010U
2027 #define I2C_CR2_FREQ_5 0x00000020U
2029 #define I2C_CR2_ITERREN 0x00000100U
2030 #define I2C_CR2_ITEVTEN 0x00000200U
2031 #define I2C_CR2_ITBUFEN 0x00000400U
2032 #define I2C_CR2_DMAEN 0x00000800U
2033 #define I2C_CR2_LAST 0x00001000U
2035 /******************* Bit definition for I2C_OAR1 register *******************/
2036 #define I2C_OAR1_ADD1_7 0x000000FEU
2037 #define I2C_OAR1_ADD8_9 0x00000300U
2039 #define I2C_OAR1_ADD0 0x00000001U
2040 #define I2C_OAR1_ADD1 0x00000002U
2041 #define I2C_OAR1_ADD2 0x00000004U
2042 #define I2C_OAR1_ADD3 0x00000008U
2043 #define I2C_OAR1_ADD4 0x00000010U
2044 #define I2C_OAR1_ADD5 0x00000020U
2045 #define I2C_OAR1_ADD6 0x00000040U
2046 #define I2C_OAR1_ADD7 0x00000080U
2047 #define I2C_OAR1_ADD8 0x00000100U
2048 #define I2C_OAR1_ADD9 0x00000200U
2050 #define I2C_OAR1_ADDMODE 0x00008000U
2052 /******************* Bit definition for I2C_OAR2 register *******************/
2053 #define I2C_OAR2_ENDUAL 0x00000001U
2054 #define I2C_OAR2_ADD2 0x000000FEU
2056 /******************** Bit definition for I2C_DR register ********************/
2057 #define I2C_DR_DR 0x000000FFU
2059 /******************* Bit definition for I2C_SR1 register ********************/
2060 #define I2C_SR1_SB 0x00000001U
2061 #define I2C_SR1_ADDR 0x00000002U
2062 #define I2C_SR1_BTF 0x00000004U
2063 #define I2C_SR1_ADD10 0x00000008U
2064 #define I2C_SR1_STOPF 0x00000010U
2065 #define I2C_SR1_RXNE 0x00000040U
2066 #define I2C_SR1_TXE 0x00000080U
2067 #define I2C_SR1_BERR 0x00000100U
2068 #define I2C_SR1_ARLO 0x00000200U
2069 #define I2C_SR1_AF 0x00000400U
2070 #define I2C_SR1_OVR 0x00000800U
2071 #define I2C_SR1_PECERR 0x00001000U
2072 #define I2C_SR1_TIMEOUT 0x00004000U
2073 #define I2C_SR1_SMBALERT 0x00008000U
2075 /******************* Bit definition for I2C_SR2 register ********************/
2076 #define I2C_SR2_MSL 0x00000001U
2077 #define I2C_SR2_BUSY 0x00000002U
2078 #define I2C_SR2_TRA 0x00000004U
2079 #define I2C_SR2_GENCALL 0x00000010U
2080 #define I2C_SR2_SMBDEFAULT 0x00000020U
2081 #define I2C_SR2_SMBHOST 0x00000040U
2082 #define I2C_SR2_DUALF 0x00000080U
2083 #define I2C_SR2_PEC 0x0000FF00U
2085 /******************* Bit definition for I2C_CCR register ********************/
2086 #define I2C_CCR_CCR 0x00000FFFU
2087 #define I2C_CCR_DUTY 0x00004000U
2088 #define I2C_CCR_FS 0x00008000U
2090 /****************** Bit definition for I2C_TRISE register *******************/
2091 #define I2C_TRISE_TRISE 0x0000003FU
2093 /****************** Bit definition for I2C_FLTR register *******************/
2094 #define I2C_FLTR_DNF 0x0000000FU
2095 #define I2C_FLTR_ANOFF 0x00000010U
2097 /******************************************************************************/
2098 /* */
2099 /* Independent WATCHDOG */
2100 /* */
2101 /******************************************************************************/
2102 /******************* Bit definition for IWDG_KR register ********************/
2103 #define IWDG_KR_KEY 0xFFFFU
2105 /******************* Bit definition for IWDG_PR register ********************/
2106 #define IWDG_PR_PR 0x07U
2107 #define IWDG_PR_PR_0 0x01U
2108 #define IWDG_PR_PR_1 0x02U
2109 #define IWDG_PR_PR_2 0x04U
2111 /******************* Bit definition for IWDG_RLR register *******************/
2112 #define IWDG_RLR_RL 0x0FFFU
2114 /******************* Bit definition for IWDG_SR register ********************/
2115 #define IWDG_SR_PVU 0x01U
2116 #define IWDG_SR_RVU 0x02U
2119 /******************************************************************************/
2120 /* */
2121 /* Power Control */
2122 /* */
2123 /******************************************************************************/
2124 /******************** Bit definition for PWR_CR register ********************/
2125 #define PWR_CR_LPDS 0x00000001U
2126 #define PWR_CR_PDDS 0x00000002U
2127 #define PWR_CR_CWUF 0x00000004U
2128 #define PWR_CR_CSBF 0x00000008U
2129 #define PWR_CR_PVDE 0x00000010U
2131 #define PWR_CR_PLS 0x000000E0U
2132 #define PWR_CR_PLS_0 0x00000020U
2133 #define PWR_CR_PLS_1 0x00000040U
2134 #define PWR_CR_PLS_2 0x00000080U
2137 #define PWR_CR_PLS_LEV0 0x00000000U
2138 #define PWR_CR_PLS_LEV1 0x00000020U
2139 #define PWR_CR_PLS_LEV2 0x00000040U
2140 #define PWR_CR_PLS_LEV3 0x00000060U
2141 #define PWR_CR_PLS_LEV4 0x00000080U
2142 #define PWR_CR_PLS_LEV5 0x000000A0U
2143 #define PWR_CR_PLS_LEV6 0x000000C0U
2144 #define PWR_CR_PLS_LEV7 0x000000E0U
2146 #define PWR_CR_DBP 0x00000100U
2147 #define PWR_CR_FPDS 0x00000200U
2148 #define PWR_CR_LPLVDS 0x00000400U
2149 #define PWR_CR_MRLVDS 0x00000800U
2150 #define PWR_CR_ADCDC1 0x00002000U
2152 #define PWR_CR_VOS 0x0000C000U
2153 #define PWR_CR_VOS_0 0x00004000U
2154 #define PWR_CR_VOS_1 0x00008000U
2156 #define PWR_CR_FMSSR 0x00100000U
2157 #define PWR_CR_FISSR 0x00200000U
2158 /* Legacy define */
2159 #define PWR_CR_PMODE PWR_CR_VOS
2160 
2161 /******************* Bit definition for PWR_CSR register ********************/
2162 #define PWR_CSR_WUF 0x00000001U
2163 #define PWR_CSR_SBF 0x00000002U
2164 #define PWR_CSR_PVDO 0x00000004U
2165 #define PWR_CSR_BRR 0x00000008U
2166 #define PWR_CSR_EWUP 0x00000100U
2167 #define PWR_CSR_BRE 0x00000200U
2168 #define PWR_CSR_VOSRDY 0x00004000U
2170 /* Legacy define */
2171 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
2172 
2173 /******************************************************************************/
2174 /* */
2175 /* Reset and Clock Control */
2176 /* */
2177 /******************************************************************************/
2178 /******************** Bit definition for RCC_CR register ********************/
2179 #define RCC_CR_HSION 0x00000001U
2180 #define RCC_CR_HSIRDY 0x00000002U
2181 
2182 #define RCC_CR_HSITRIM 0x000000F8U
2183 #define RCC_CR_HSITRIM_0 0x00000008U
2184 #define RCC_CR_HSITRIM_1 0x00000010U
2185 #define RCC_CR_HSITRIM_2 0x00000020U
2186 #define RCC_CR_HSITRIM_3 0x00000040U
2187 #define RCC_CR_HSITRIM_4 0x00000080U
2189 #define RCC_CR_HSICAL 0x0000FF00U
2190 #define RCC_CR_HSICAL_0 0x00000100U
2191 #define RCC_CR_HSICAL_1 0x00000200U
2192 #define RCC_CR_HSICAL_2 0x00000400U
2193 #define RCC_CR_HSICAL_3 0x00000800U
2194 #define RCC_CR_HSICAL_4 0x00001000U
2195 #define RCC_CR_HSICAL_5 0x00002000U
2196 #define RCC_CR_HSICAL_6 0x00004000U
2197 #define RCC_CR_HSICAL_7 0x00008000U
2199 #define RCC_CR_HSEON 0x00010000U
2200 #define RCC_CR_HSERDY 0x00020000U
2201 #define RCC_CR_HSEBYP 0x00040000U
2202 #define RCC_CR_CSSON 0x00080000U
2203 #define RCC_CR_PLLON 0x01000000U
2204 #define RCC_CR_PLLRDY 0x02000000U
2205 #define RCC_CR_PLLI2SON 0x04000000U
2206 #define RCC_CR_PLLI2SRDY 0x08000000U
2207 
2208 /******************** Bit definition for RCC_PLLCFGR register ***************/
2209 #define RCC_PLLCFGR_PLLM 0x0000003FU
2210 #define RCC_PLLCFGR_PLLM_0 0x00000001U
2211 #define RCC_PLLCFGR_PLLM_1 0x00000002U
2212 #define RCC_PLLCFGR_PLLM_2 0x00000004U
2213 #define RCC_PLLCFGR_PLLM_3 0x00000008U
2214 #define RCC_PLLCFGR_PLLM_4 0x00000010U
2215 #define RCC_PLLCFGR_PLLM_5 0x00000020U
2216 
2217 #define RCC_PLLCFGR_PLLN 0x00007FC0U
2218 #define RCC_PLLCFGR_PLLN_0 0x00000040U
2219 #define RCC_PLLCFGR_PLLN_1 0x00000080U
2220 #define RCC_PLLCFGR_PLLN_2 0x00000100U
2221 #define RCC_PLLCFGR_PLLN_3 0x00000200U
2222 #define RCC_PLLCFGR_PLLN_4 0x00000400U
2223 #define RCC_PLLCFGR_PLLN_5 0x00000800U
2224 #define RCC_PLLCFGR_PLLN_6 0x00001000U
2225 #define RCC_PLLCFGR_PLLN_7 0x00002000U
2226 #define RCC_PLLCFGR_PLLN_8 0x00004000U
2227 
2228 #define RCC_PLLCFGR_PLLP 0x00030000U
2229 #define RCC_PLLCFGR_PLLP_0 0x00010000U
2230 #define RCC_PLLCFGR_PLLP_1 0x00020000U
2231 
2232 #define RCC_PLLCFGR_PLLSRC 0x00400000U
2233 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
2234 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
2235 
2236 #define RCC_PLLCFGR_PLLQ 0x0F000000U
2237 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
2238 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
2239 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
2240 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
2241 
2242 /******************** Bit definition for RCC_CFGR register ******************/
2244 #define RCC_CFGR_SW 0x00000003U
2245 #define RCC_CFGR_SW_0 0x00000001U
2246 #define RCC_CFGR_SW_1 0x00000002U
2248 #define RCC_CFGR_SW_HSI 0x00000000U
2249 #define RCC_CFGR_SW_HSE 0x00000001U
2250 #define RCC_CFGR_SW_PLL 0x00000002U
2253 #define RCC_CFGR_SWS 0x0000000CU
2254 #define RCC_CFGR_SWS_0 0x00000004U
2255 #define RCC_CFGR_SWS_1 0x00000008U
2257 #define RCC_CFGR_SWS_HSI 0x00000000U
2258 #define RCC_CFGR_SWS_HSE 0x00000004U
2259 #define RCC_CFGR_SWS_PLL 0x00000008U
2262 #define RCC_CFGR_HPRE 0x000000F0U
2263 #define RCC_CFGR_HPRE_0 0x00000010U
2264 #define RCC_CFGR_HPRE_1 0x00000020U
2265 #define RCC_CFGR_HPRE_2 0x00000040U
2266 #define RCC_CFGR_HPRE_3 0x00000080U
2268 #define RCC_CFGR_HPRE_DIV1 0x00000000U
2269 #define RCC_CFGR_HPRE_DIV2 0x00000080U
2270 #define RCC_CFGR_HPRE_DIV4 0x00000090U
2271 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
2272 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
2273 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
2274 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
2275 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
2276 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
2279 #define RCC_CFGR_PPRE1 0x00001C00U
2280 #define RCC_CFGR_PPRE1_0 0x00000400U
2281 #define RCC_CFGR_PPRE1_1 0x00000800U
2282 #define RCC_CFGR_PPRE1_2 0x00001000U
2284 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
2285 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
2286 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
2287 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
2288 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
2291 #define RCC_CFGR_PPRE2 0x0000E000U
2292 #define RCC_CFGR_PPRE2_0 0x00002000U
2293 #define RCC_CFGR_PPRE2_1 0x00004000U
2294 #define RCC_CFGR_PPRE2_2 0x00008000U
2296 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
2297 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
2298 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
2299 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
2300 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
2303 #define RCC_CFGR_RTCPRE 0x001F0000U
2304 #define RCC_CFGR_RTCPRE_0 0x00010000U
2305 #define RCC_CFGR_RTCPRE_1 0x00020000U
2306 #define RCC_CFGR_RTCPRE_2 0x00040000U
2307 #define RCC_CFGR_RTCPRE_3 0x00080000U
2308 #define RCC_CFGR_RTCPRE_4 0x00100000U
2309 
2311 #define RCC_CFGR_MCO1 0x00600000U
2312 #define RCC_CFGR_MCO1_0 0x00200000U
2313 #define RCC_CFGR_MCO1_1 0x00400000U
2314 
2315 #define RCC_CFGR_I2SSRC 0x00800000U
2316 
2317 #define RCC_CFGR_MCO1PRE 0x07000000U
2318 #define RCC_CFGR_MCO1PRE_0 0x01000000U
2319 #define RCC_CFGR_MCO1PRE_1 0x02000000U
2320 #define RCC_CFGR_MCO1PRE_2 0x04000000U
2321 
2322 #define RCC_CFGR_MCO2PRE 0x38000000U
2323 #define RCC_CFGR_MCO2PRE_0 0x08000000U
2324 #define RCC_CFGR_MCO2PRE_1 0x10000000U
2325 #define RCC_CFGR_MCO2PRE_2 0x20000000U
2326 
2327 #define RCC_CFGR_MCO2 0xC0000000U
2328 #define RCC_CFGR_MCO2_0 0x40000000U
2329 #define RCC_CFGR_MCO2_1 0x80000000U
2330 
2331 /******************** Bit definition for RCC_CIR register *******************/
2332 #define RCC_CIR_LSIRDYF 0x00000001U
2333 #define RCC_CIR_LSERDYF 0x00000002U
2334 #define RCC_CIR_HSIRDYF 0x00000004U
2335 #define RCC_CIR_HSERDYF 0x00000008U
2336 #define RCC_CIR_PLLRDYF 0x00000010U
2337 #define RCC_CIR_PLLI2SRDYF 0x00000020U
2338 
2339 #define RCC_CIR_CSSF 0x00000080U
2340 #define RCC_CIR_LSIRDYIE 0x00000100U
2341 #define RCC_CIR_LSERDYIE 0x00000200U
2342 #define RCC_CIR_HSIRDYIE 0x00000400U
2343 #define RCC_CIR_HSERDYIE 0x00000800U
2344 #define RCC_CIR_PLLRDYIE 0x00001000U
2345 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
2346 
2347 #define RCC_CIR_LSIRDYC 0x00010000U
2348 #define RCC_CIR_LSERDYC 0x00020000U
2349 #define RCC_CIR_HSIRDYC 0x00040000U
2350 #define RCC_CIR_HSERDYC 0x00080000U
2351 #define RCC_CIR_PLLRDYC 0x00100000U
2352 #define RCC_CIR_PLLI2SRDYC 0x00200000U
2353 
2354 #define RCC_CIR_CSSC 0x00800000U
2355 
2356 /******************** Bit definition for RCC_AHB1RSTR register **************/
2357 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
2358 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
2359 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
2360 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
2361 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
2362 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
2363 #define RCC_AHB1RSTR_CRCRST 0x00001000U
2364 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
2365 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
2366 
2367 /******************** Bit definition for RCC_AHB2RSTR register **************/
2368 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
2369 
2370 /******************** Bit definition for RCC_AHB3RSTR register **************/
2371 
2372 /******************** Bit definition for RCC_APB1RSTR register **************/
2373 #define RCC_APB1RSTR_TIM2RST 0x00000001U
2374 #define RCC_APB1RSTR_TIM3RST 0x00000002U
2375 #define RCC_APB1RSTR_TIM4RST 0x00000004U
2376 #define RCC_APB1RSTR_TIM5RST 0x00000008U
2377 #define RCC_APB1RSTR_WWDGRST 0x00000800U
2378 #define RCC_APB1RSTR_SPI2RST 0x00004000U
2379 #define RCC_APB1RSTR_SPI3RST 0x00008000U
2380 #define RCC_APB1RSTR_USART2RST 0x00020000U
2381 #define RCC_APB1RSTR_I2C1RST 0x00200000U
2382 #define RCC_APB1RSTR_I2C2RST 0x00400000U
2383 #define RCC_APB1RSTR_I2C3RST 0x00800000U
2384 #define RCC_APB1RSTR_PWRRST 0x10000000U
2385 
2386 /******************** Bit definition for RCC_APB2RSTR register **************/
2387 #define RCC_APB2RSTR_TIM1RST 0x00000001U
2388 #define RCC_APB2RSTR_USART1RST 0x00000010U
2389 #define RCC_APB2RSTR_USART6RST 0x00000020U
2390 #define RCC_APB2RSTR_ADCRST 0x00000100U
2391 #define RCC_APB2RSTR_SDIORST 0x00000800U
2392 #define RCC_APB2RSTR_SPI1RST 0x00001000U
2393 #define RCC_APB2RSTR_SPI4RST 0x00002000U
2394 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
2395 #define RCC_APB2RSTR_TIM9RST 0x00010000U
2396 #define RCC_APB2RSTR_TIM10RST 0x00020000U
2397 #define RCC_APB2RSTR_TIM11RST 0x00040000U
2398 #define RCC_APB2RSTR_SPI5RST 0x00100000U
2399 
2400 /* Old SPI1RST bit definition, maintained for legacy purpose */
2401 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
2402 
2403 /******************** Bit definition for RCC_AHB1ENR register ***************/
2404 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
2405 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
2406 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
2407 #define RCC_AHB1ENR_GPIODEN 0x00000008U
2408 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
2409 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
2410 #define RCC_AHB1ENR_CRCEN 0x00001000U
2411 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
2412 #define RCC_AHB1ENR_DMA1EN 0x00200000U
2413 #define RCC_AHB1ENR_DMA2EN 0x00400000U
2414 
2415 /******************** Bit definition for RCC_AHB2ENR register ***************/
2416 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
2417 
2418 /******************** Bit definition for RCC_AHB3ENR register ***************/
2419 
2420 /******************** Bit definition for RCC_APB1ENR register ***************/
2421 #define RCC_APB1ENR_TIM2EN 0x00000001U
2422 #define RCC_APB1ENR_TIM3EN 0x00000002U
2423 #define RCC_APB1ENR_TIM4EN 0x00000004U
2424 #define RCC_APB1ENR_TIM5EN 0x00000008U
2425 #define RCC_APB1ENR_WWDGEN 0x00000800U
2426 #define RCC_APB1ENR_SPI2EN 0x00004000U
2427 #define RCC_APB1ENR_SPI3EN 0x00008000U
2428 #define RCC_APB1ENR_USART2EN 0x00020000U
2429 #define RCC_APB1ENR_I2C1EN 0x00200000U
2430 #define RCC_APB1ENR_I2C2EN 0x00400000U
2431 #define RCC_APB1ENR_I2C3EN 0x00800000U
2432 #define RCC_APB1ENR_PWREN 0x10000000U
2433 
2434 /******************** Bit definition for RCC_APB2ENR register ***************/
2435 #define RCC_APB2ENR_TIM1EN 0x00000001U
2436 #define RCC_APB2ENR_USART1EN 0x00000010U
2437 #define RCC_APB2ENR_USART6EN 0x00000020U
2438 #define RCC_APB2ENR_ADC1EN 0x00000100U
2439 #define RCC_APB2ENR_SDIOEN 0x00000800U
2440 #define RCC_APB2ENR_SPI1EN 0x00001000U
2441 #define RCC_APB2ENR_SPI4EN 0x00002000U
2442 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
2443 #define RCC_APB2ENR_TIM9EN 0x00010000U
2444 #define RCC_APB2ENR_TIM10EN 0x00020000U
2445 #define RCC_APB2ENR_TIM11EN 0x00040000U
2446 #define RCC_APB2ENR_SPI5EN 0x00100000U
2447 
2448 /******************** Bit definition for RCC_AHB1LPENR register *************/
2449 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
2450 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
2451 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
2452 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
2453 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
2454 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
2455 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
2456 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
2457 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
2458 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
2459 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
2460 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
2461 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
2462 
2463 /******************** Bit definition for RCC_AHB2LPENR register *************/
2464 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
2465 
2466 /******************** Bit definition for RCC_AHB3LPENR register *************/
2467 
2468 /******************** Bit definition for RCC_APB1LPENR register *************/
2469 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
2470 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
2471 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
2472 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
2473 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
2474 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
2475 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
2476 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
2477 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
2478 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
2479 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
2480 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
2481 #define RCC_APB1LPENR_DACLPEN 0x20000000U
2482 
2483 /******************** Bit definition for RCC_APB2LPENR register *************/
2484 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
2485 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
2486 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
2487 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
2488 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
2489 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
2490 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
2491 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
2492 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
2493 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
2494 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
2495 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
2496 
2497 /******************** Bit definition for RCC_BDCR register ******************/
2498 #define RCC_BDCR_LSEON 0x00000001U
2499 #define RCC_BDCR_LSERDY 0x00000002U
2500 #define RCC_BDCR_LSEBYP 0x00000004U
2501 #define RCC_BDCR_LSEMOD 0x00000008U
2502 
2503 #define RCC_BDCR_RTCSEL 0x00000300U
2504 #define RCC_BDCR_RTCSEL_0 0x00000100U
2505 #define RCC_BDCR_RTCSEL_1 0x00000200U
2506 
2507 #define RCC_BDCR_RTCEN 0x00008000U
2508 #define RCC_BDCR_BDRST 0x00010000U
2509 
2510 /******************** Bit definition for RCC_CSR register *******************/
2511 #define RCC_CSR_LSION 0x00000001U
2512 #define RCC_CSR_LSIRDY 0x00000002U
2513 #define RCC_CSR_RMVF 0x01000000U
2514 #define RCC_CSR_BORRSTF 0x02000000U
2515 #define RCC_CSR_PADRSTF 0x04000000U
2516 #define RCC_CSR_PORRSTF 0x08000000U
2517 #define RCC_CSR_SFTRSTF 0x10000000U
2518 #define RCC_CSR_WDGRSTF 0x20000000U
2519 #define RCC_CSR_WWDGRSTF 0x40000000U
2520 #define RCC_CSR_LPWRRSTF 0x80000000U
2521 
2522 /******************** Bit definition for RCC_SSCGR register *****************/
2523 #define RCC_SSCGR_MODPER 0x00001FFFU
2524 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
2525 #define RCC_SSCGR_SPREADSEL 0x40000000U
2526 #define RCC_SSCGR_SSCGEN 0x80000000U
2527 
2528 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
2529 #define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
2530 #define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
2531 #define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
2532 #define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
2533 #define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
2534 #define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
2535 #define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
2536 
2537 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
2538 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
2539 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
2540 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
2541 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
2542 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
2543 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
2544 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
2545 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
2546 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
2547 
2548 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
2549 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
2550 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
2551 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
2552 
2553 /******************** Bit definition for RCC_DCKCFGR register ***************/
2554 #define RCC_DCKCFGR_TIMPRE 0x01000000U
2555 
2556 /******************************************************************************/
2557 /* */
2558 /* Real-Time Clock (RTC) */
2559 /* */
2560 /******************************************************************************/
2561 /******************** Bits definition for RTC_TR register *******************/
2562 #define RTC_TR_PM 0x00400000U
2563 #define RTC_TR_HT 0x00300000U
2564 #define RTC_TR_HT_0 0x00100000U
2565 #define RTC_TR_HT_1 0x00200000U
2566 #define RTC_TR_HU 0x000F0000U
2567 #define RTC_TR_HU_0 0x00010000U
2568 #define RTC_TR_HU_1 0x00020000U
2569 #define RTC_TR_HU_2 0x00040000U
2570 #define RTC_TR_HU_3 0x00080000U
2571 #define RTC_TR_MNT 0x00007000U
2572 #define RTC_TR_MNT_0 0x00001000U
2573 #define RTC_TR_MNT_1 0x00002000U
2574 #define RTC_TR_MNT_2 0x00004000U
2575 #define RTC_TR_MNU 0x00000F00U
2576 #define RTC_TR_MNU_0 0x00000100U
2577 #define RTC_TR_MNU_1 0x00000200U
2578 #define RTC_TR_MNU_2 0x00000400U
2579 #define RTC_TR_MNU_3 0x00000800U
2580 #define RTC_TR_ST 0x00000070U
2581 #define RTC_TR_ST_0 0x00000010U
2582 #define RTC_TR_ST_1 0x00000020U
2583 #define RTC_TR_ST_2 0x00000040U
2584 #define RTC_TR_SU 0x0000000FU
2585 #define RTC_TR_SU_0 0x00000001U
2586 #define RTC_TR_SU_1 0x00000002U
2587 #define RTC_TR_SU_2 0x00000004U
2588 #define RTC_TR_SU_3 0x00000008U
2589 
2590 /******************** Bits definition for RTC_DR register *******************/
2591 #define RTC_DR_YT 0x00F00000U
2592 #define RTC_DR_YT_0 0x00100000U
2593 #define RTC_DR_YT_1 0x00200000U
2594 #define RTC_DR_YT_2 0x00400000U
2595 #define RTC_DR_YT_3 0x00800000U
2596 #define RTC_DR_YU 0x000F0000U
2597 #define RTC_DR_YU_0 0x00010000U
2598 #define RTC_DR_YU_1 0x00020000U
2599 #define RTC_DR_YU_2 0x00040000U
2600 #define RTC_DR_YU_3 0x00080000U
2601 #define RTC_DR_WDU 0x0000E000U
2602 #define RTC_DR_WDU_0 0x00002000U
2603 #define RTC_DR_WDU_1 0x00004000U
2604 #define RTC_DR_WDU_2 0x00008000U
2605 #define RTC_DR_MT 0x00001000U
2606 #define RTC_DR_MU 0x00000F00U
2607 #define RTC_DR_MU_0 0x00000100U
2608 #define RTC_DR_MU_1 0x00000200U
2609 #define RTC_DR_MU_2 0x00000400U
2610 #define RTC_DR_MU_3 0x00000800U
2611 #define RTC_DR_DT 0x00000030U
2612 #define RTC_DR_DT_0 0x00000010U
2613 #define RTC_DR_DT_1 0x00000020U
2614 #define RTC_DR_DU 0x0000000FU
2615 #define RTC_DR_DU_0 0x00000001U
2616 #define RTC_DR_DU_1 0x00000002U
2617 #define RTC_DR_DU_2 0x00000004U
2618 #define RTC_DR_DU_3 0x00000008U
2619 
2620 /******************** Bits definition for RTC_CR register *******************/
2621 #define RTC_CR_COE 0x00800000U
2622 #define RTC_CR_OSEL 0x00600000U
2623 #define RTC_CR_OSEL_0 0x00200000U
2624 #define RTC_CR_OSEL_1 0x00400000U
2625 #define RTC_CR_POL 0x00100000U
2626 #define RTC_CR_COSEL 0x00080000U
2627 #define RTC_CR_BCK 0x00040000U
2628 #define RTC_CR_SUB1H 0x00020000U
2629 #define RTC_CR_ADD1H 0x00010000U
2630 #define RTC_CR_TSIE 0x00008000U
2631 #define RTC_CR_WUTIE 0x00004000U
2632 #define RTC_CR_ALRBIE 0x00002000U
2633 #define RTC_CR_ALRAIE 0x00001000U
2634 #define RTC_CR_TSE 0x00000800U
2635 #define RTC_CR_WUTE 0x00000400U
2636 #define RTC_CR_ALRBE 0x00000200U
2637 #define RTC_CR_ALRAE 0x00000100U
2638 #define RTC_CR_DCE 0x00000080U
2639 #define RTC_CR_FMT 0x00000040U
2640 #define RTC_CR_BYPSHAD 0x00000020U
2641 #define RTC_CR_REFCKON 0x00000010U
2642 #define RTC_CR_TSEDGE 0x00000008U
2643 #define RTC_CR_WUCKSEL 0x00000007U
2644 #define RTC_CR_WUCKSEL_0 0x00000001U
2645 #define RTC_CR_WUCKSEL_1 0x00000002U
2646 #define RTC_CR_WUCKSEL_2 0x00000004U
2647 
2648 /******************** Bits definition for RTC_ISR register ******************/
2649 #define RTC_ISR_RECALPF 0x00010000U
2650 #define RTC_ISR_TAMP1F 0x00002000U
2651 #define RTC_ISR_TAMP2F 0x00004000U
2652 #define RTC_ISR_TSOVF 0x00001000U
2653 #define RTC_ISR_TSF 0x00000800U
2654 #define RTC_ISR_WUTF 0x00000400U
2655 #define RTC_ISR_ALRBF 0x00000200U
2656 #define RTC_ISR_ALRAF 0x00000100U
2657 #define RTC_ISR_INIT 0x00000080U
2658 #define RTC_ISR_INITF 0x00000040U
2659 #define RTC_ISR_RSF 0x00000020U
2660 #define RTC_ISR_INITS 0x00000010U
2661 #define RTC_ISR_SHPF 0x00000008U
2662 #define RTC_ISR_WUTWF 0x00000004U
2663 #define RTC_ISR_ALRBWF 0x00000002U
2664 #define RTC_ISR_ALRAWF 0x00000001U
2665 
2666 /******************** Bits definition for RTC_PRER register *****************/
2667 #define RTC_PRER_PREDIV_A 0x007F0000U
2668 #define RTC_PRER_PREDIV_S 0x00007FFFU
2669 
2670 /******************** Bits definition for RTC_WUTR register *****************/
2671 #define RTC_WUTR_WUT 0x0000FFFFU
2672 
2673 /******************** Bits definition for RTC_CALIBR register ***************/
2674 #define RTC_CALIBR_DCS 0x00000080U
2675 #define RTC_CALIBR_DC 0x0000001FU
2676 
2677 /******************** Bits definition for RTC_ALRMAR register ***************/
2678 #define RTC_ALRMAR_MSK4 0x80000000U
2679 #define RTC_ALRMAR_WDSEL 0x40000000U
2680 #define RTC_ALRMAR_DT 0x30000000U
2681 #define RTC_ALRMAR_DT_0 0x10000000U
2682 #define RTC_ALRMAR_DT_1 0x20000000U
2683 #define RTC_ALRMAR_DU 0x0F000000U
2684 #define RTC_ALRMAR_DU_0 0x01000000U
2685 #define RTC_ALRMAR_DU_1 0x02000000U
2686 #define RTC_ALRMAR_DU_2 0x04000000U
2687 #define RTC_ALRMAR_DU_3 0x08000000U
2688 #define RTC_ALRMAR_MSK3 0x00800000U
2689 #define RTC_ALRMAR_PM 0x00400000U
2690 #define RTC_ALRMAR_HT 0x00300000U
2691 #define RTC_ALRMAR_HT_0 0x00100000U
2692 #define RTC_ALRMAR_HT_1 0x00200000U
2693 #define RTC_ALRMAR_HU 0x000F0000U
2694 #define RTC_ALRMAR_HU_0 0x00010000U
2695 #define RTC_ALRMAR_HU_1 0x00020000U
2696 #define RTC_ALRMAR_HU_2 0x00040000U
2697 #define RTC_ALRMAR_HU_3 0x00080000U
2698 #define RTC_ALRMAR_MSK2 0x00008000U
2699 #define RTC_ALRMAR_MNT 0x00007000U
2700 #define RTC_ALRMAR_MNT_0 0x00001000U
2701 #define RTC_ALRMAR_MNT_1 0x00002000U
2702 #define RTC_ALRMAR_MNT_2 0x00004000U
2703 #define RTC_ALRMAR_MNU 0x00000F00U
2704 #define RTC_ALRMAR_MNU_0 0x00000100U
2705 #define RTC_ALRMAR_MNU_1 0x00000200U
2706 #define RTC_ALRMAR_MNU_2 0x00000400U
2707 #define RTC_ALRMAR_MNU_3 0x00000800U
2708 #define RTC_ALRMAR_MSK1 0x00000080U
2709 #define RTC_ALRMAR_ST 0x00000070U
2710 #define RTC_ALRMAR_ST_0 0x00000010U
2711 #define RTC_ALRMAR_ST_1 0x00000020U
2712 #define RTC_ALRMAR_ST_2 0x00000040U
2713 #define RTC_ALRMAR_SU 0x0000000FU
2714 #define RTC_ALRMAR_SU_0 0x00000001U
2715 #define RTC_ALRMAR_SU_1 0x00000002U
2716 #define RTC_ALRMAR_SU_2 0x00000004U
2717 #define RTC_ALRMAR_SU_3 0x00000008U
2718 
2719 /******************** Bits definition for RTC_ALRMBR register ***************/
2720 #define RTC_ALRMBR_MSK4 0x80000000U
2721 #define RTC_ALRMBR_WDSEL 0x40000000U
2722 #define RTC_ALRMBR_DT 0x30000000U
2723 #define RTC_ALRMBR_DT_0 0x10000000U
2724 #define RTC_ALRMBR_DT_1 0x20000000U
2725 #define RTC_ALRMBR_DU 0x0F000000U
2726 #define RTC_ALRMBR_DU_0 0x01000000U
2727 #define RTC_ALRMBR_DU_1 0x02000000U
2728 #define RTC_ALRMBR_DU_2 0x04000000U
2729 #define RTC_ALRMBR_DU_3 0x08000000U
2730 #define RTC_ALRMBR_MSK3 0x00800000U
2731 #define RTC_ALRMBR_PM 0x00400000U
2732 #define RTC_ALRMBR_HT 0x00300000U
2733 #define RTC_ALRMBR_HT_0 0x00100000U
2734 #define RTC_ALRMBR_HT_1 0x00200000U
2735 #define RTC_ALRMBR_HU 0x000F0000U
2736 #define RTC_ALRMBR_HU_0 0x00010000U
2737 #define RTC_ALRMBR_HU_1 0x00020000U
2738 #define RTC_ALRMBR_HU_2 0x00040000U
2739 #define RTC_ALRMBR_HU_3 0x00080000U
2740 #define RTC_ALRMBR_MSK2 0x00008000U
2741 #define RTC_ALRMBR_MNT 0x00007000U
2742 #define RTC_ALRMBR_MNT_0 0x00001000U
2743 #define RTC_ALRMBR_MNT_1 0x00002000U
2744 #define RTC_ALRMBR_MNT_2 0x00004000U
2745 #define RTC_ALRMBR_MNU 0x00000F00U
2746 #define RTC_ALRMBR_MNU_0 0x00000100U
2747 #define RTC_ALRMBR_MNU_1 0x00000200U
2748 #define RTC_ALRMBR_MNU_2 0x00000400U
2749 #define RTC_ALRMBR_MNU_3 0x00000800U
2750 #define RTC_ALRMBR_MSK1 0x00000080U
2751 #define RTC_ALRMBR_ST 0x00000070U
2752 #define RTC_ALRMBR_ST_0 0x00000010U
2753 #define RTC_ALRMBR_ST_1 0x00000020U
2754 #define RTC_ALRMBR_ST_2 0x00000040U
2755 #define RTC_ALRMBR_SU 0x0000000FU
2756 #define RTC_ALRMBR_SU_0 0x00000001U
2757 #define RTC_ALRMBR_SU_1 0x00000002U
2758 #define RTC_ALRMBR_SU_2 0x00000004U
2759 #define RTC_ALRMBR_SU_3 0x00000008U
2760 
2761 /******************** Bits definition for RTC_WPR register ******************/
2762 #define RTC_WPR_KEY 0x000000FFU
2763 
2764 /******************** Bits definition for RTC_SSR register ******************/
2765 #define RTC_SSR_SS 0x0000FFFFU
2766 
2767 /******************** Bits definition for RTC_SHIFTR register ***************/
2768 #define RTC_SHIFTR_SUBFS 0x00007FFFU
2769 #define RTC_SHIFTR_ADD1S 0x80000000U
2770 
2771 /******************** Bits definition for RTC_TSTR register *****************/
2772 #define RTC_TSTR_PM 0x00400000U
2773 #define RTC_TSTR_HT 0x00300000U
2774 #define RTC_TSTR_HT_0 0x00100000U
2775 #define RTC_TSTR_HT_1 0x00200000U
2776 #define RTC_TSTR_HU 0x000F0000U
2777 #define RTC_TSTR_HU_0 0x00010000U
2778 #define RTC_TSTR_HU_1 0x00020000U
2779 #define RTC_TSTR_HU_2 0x00040000U
2780 #define RTC_TSTR_HU_3 0x00080000U
2781 #define RTC_TSTR_MNT 0x00007000U
2782 #define RTC_TSTR_MNT_0 0x00001000U
2783 #define RTC_TSTR_MNT_1 0x00002000U
2784 #define RTC_TSTR_MNT_2 0x00004000U
2785 #define RTC_TSTR_MNU 0x00000F00U
2786 #define RTC_TSTR_MNU_0 0x00000100U
2787 #define RTC_TSTR_MNU_1 0x00000200U
2788 #define RTC_TSTR_MNU_2 0x00000400U
2789 #define RTC_TSTR_MNU_3 0x00000800U
2790 #define RTC_TSTR_ST 0x00000070U
2791 #define RTC_TSTR_ST_0 0x00000010U
2792 #define RTC_TSTR_ST_1 0x00000020U
2793 #define RTC_TSTR_ST_2 0x00000040U
2794 #define RTC_TSTR_SU 0x0000000FU
2795 #define RTC_TSTR_SU_0 0x00000001U
2796 #define RTC_TSTR_SU_1 0x00000002U
2797 #define RTC_TSTR_SU_2 0x00000004U
2798 #define RTC_TSTR_SU_3 0x00000008U
2799 
2800 /******************** Bits definition for RTC_TSDR register *****************/
2801 #define RTC_TSDR_WDU 0x0000E000U
2802 #define RTC_TSDR_WDU_0 0x00002000U
2803 #define RTC_TSDR_WDU_1 0x00004000U
2804 #define RTC_TSDR_WDU_2 0x00008000U
2805 #define RTC_TSDR_MT 0x00001000U
2806 #define RTC_TSDR_MU 0x00000F00U
2807 #define RTC_TSDR_MU_0 0x00000100U
2808 #define RTC_TSDR_MU_1 0x00000200U
2809 #define RTC_TSDR_MU_2 0x00000400U
2810 #define RTC_TSDR_MU_3 0x00000800U
2811 #define RTC_TSDR_DT 0x00000030U
2812 #define RTC_TSDR_DT_0 0x00000010U
2813 #define RTC_TSDR_DT_1 0x00000020U
2814 #define RTC_TSDR_DU 0x0000000FU
2815 #define RTC_TSDR_DU_0 0x00000001U
2816 #define RTC_TSDR_DU_1 0x00000002U
2817 #define RTC_TSDR_DU_2 0x00000004U
2818 #define RTC_TSDR_DU_3 0x00000008U
2819 
2820 /******************** Bits definition for RTC_TSSSR register ****************/
2821 #define RTC_TSSSR_SS 0x0000FFFFU
2822 
2823 /******************** Bits definition for RTC_CAL register *****************/
2824 #define RTC_CALR_CALP 0x00008000U
2825 #define RTC_CALR_CALW8 0x00004000U
2826 #define RTC_CALR_CALW16 0x00002000U
2827 #define RTC_CALR_CALM 0x000001FFU
2828 #define RTC_CALR_CALM_0 0x00000001U
2829 #define RTC_CALR_CALM_1 0x00000002U
2830 #define RTC_CALR_CALM_2 0x00000004U
2831 #define RTC_CALR_CALM_3 0x00000008U
2832 #define RTC_CALR_CALM_4 0x00000010U
2833 #define RTC_CALR_CALM_5 0x00000020U
2834 #define RTC_CALR_CALM_6 0x00000040U
2835 #define RTC_CALR_CALM_7 0x00000080U
2836 #define RTC_CALR_CALM_8 0x00000100U
2837 
2838 /******************** Bits definition for RTC_TAFCR register ****************/
2839 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
2840 #define RTC_TAFCR_TSINSEL 0x00020000U
2841 #define RTC_TAFCR_TAMPINSEL 0x00010000U
2842 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
2843 #define RTC_TAFCR_TAMPPRCH 0x00006000U
2844 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
2845 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
2846 #define RTC_TAFCR_TAMPFLT 0x00001800U
2847 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
2848 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
2849 #define RTC_TAFCR_TAMPFREQ 0x00000700U
2850 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
2851 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
2852 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
2853 #define RTC_TAFCR_TAMPTS 0x00000080U
2854 #define RTC_TAFCR_TAMP2TRG 0x00000010U
2855 #define RTC_TAFCR_TAMP2E 0x00000008U
2856 #define RTC_TAFCR_TAMPIE 0x00000004U
2857 #define RTC_TAFCR_TAMP1TRG 0x00000002U
2858 #define RTC_TAFCR_TAMP1E 0x00000001U
2859 
2860 /******************** Bits definition for RTC_ALRMASSR register *************/
2861 #define RTC_ALRMASSR_MASKSS 0x0F000000U
2862 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
2863 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
2864 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
2865 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
2866 #define RTC_ALRMASSR_SS 0x00007FFFU
2867 
2868 /******************** Bits definition for RTC_ALRMBSSR register *************/
2869 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
2870 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
2871 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
2872 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
2873 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
2874 #define RTC_ALRMBSSR_SS 0x00007FFFU
2875 
2876 /******************** Bits definition for RTC_BKP0R register ****************/
2877 #define RTC_BKP0R 0xFFFFFFFFU
2878 
2879 /******************** Bits definition for RTC_BKP1R register ****************/
2880 #define RTC_BKP1R 0xFFFFFFFFU
2881 
2882 /******************** Bits definition for RTC_BKP2R register ****************/
2883 #define RTC_BKP2R 0xFFFFFFFFU
2884 
2885 /******************** Bits definition for RTC_BKP3R register ****************/
2886 #define RTC_BKP3R 0xFFFFFFFFU
2887 
2888 /******************** Bits definition for RTC_BKP4R register ****************/
2889 #define RTC_BKP4R 0xFFFFFFFFU
2890 
2891 /******************** Bits definition for RTC_BKP5R register ****************/
2892 #define RTC_BKP5R 0xFFFFFFFFU
2893 
2894 /******************** Bits definition for RTC_BKP6R register ****************/
2895 #define RTC_BKP6R 0xFFFFFFFFU
2896 
2897 /******************** Bits definition for RTC_BKP7R register ****************/
2898 #define RTC_BKP7R 0xFFFFFFFFU
2899 
2900 /******************** Bits definition for RTC_BKP8R register ****************/
2901 #define RTC_BKP8R 0xFFFFFFFFU
2902 
2903 /******************** Bits definition for RTC_BKP9R register ****************/
2904 #define RTC_BKP9R 0xFFFFFFFFU
2905 
2906 /******************** Bits definition for RTC_BKP10R register ***************/
2907 #define RTC_BKP10R 0xFFFFFFFFU
2908 
2909 /******************** Bits definition for RTC_BKP11R register ***************/
2910 #define RTC_BKP11R 0xFFFFFFFFU
2911 
2912 /******************** Bits definition for RTC_BKP12R register ***************/
2913 #define RTC_BKP12R 0xFFFFFFFFU
2914 
2915 /******************** Bits definition for RTC_BKP13R register ***************/
2916 #define RTC_BKP13R 0xFFFFFFFFU
2917 
2918 /******************** Bits definition for RTC_BKP14R register ***************/
2919 #define RTC_BKP14R 0xFFFFFFFFU
2920 
2921 /******************** Bits definition for RTC_BKP15R register ***************/
2922 #define RTC_BKP15R 0xFFFFFFFFU
2923 
2924 /******************** Bits definition for RTC_BKP16R register ***************/
2925 #define RTC_BKP16R 0xFFFFFFFFU
2926 
2927 /******************** Bits definition for RTC_BKP17R register ***************/
2928 #define RTC_BKP17R 0xFFFFFFFFU
2929 
2930 /******************** Bits definition for RTC_BKP18R register ***************/
2931 #define RTC_BKP18R 0xFFFFFFFFU
2932 
2933 /******************** Bits definition for RTC_BKP19R register ***************/
2934 #define RTC_BKP19R 0xFFFFFFFFU
2935 
2936 
2937 
2938 /******************************************************************************/
2939 /* */
2940 /* SD host Interface */
2941 /* */
2942 /******************************************************************************/
2943 /****************** Bit definition for SDIO_POWER register ******************/
2944 #define SDIO_POWER_PWRCTRL 0x03U
2945 #define SDIO_POWER_PWRCTRL_0 0x01U
2946 #define SDIO_POWER_PWRCTRL_1 0x02U
2948 /****************** Bit definition for SDIO_CLKCR register ******************/
2949 #define SDIO_CLKCR_CLKDIV 0x00FFU
2950 #define SDIO_CLKCR_CLKEN 0x0100U
2951 #define SDIO_CLKCR_PWRSAV 0x0200U
2952 #define SDIO_CLKCR_BYPASS 0x0400U
2954 #define SDIO_CLKCR_WIDBUS 0x1800U
2955 #define SDIO_CLKCR_WIDBUS_0 0x0800U
2956 #define SDIO_CLKCR_WIDBUS_1 0x1000U
2958 #define SDIO_CLKCR_NEGEDGE 0x2000U
2959 #define SDIO_CLKCR_HWFC_EN 0x4000U
2961 /******************* Bit definition for SDIO_ARG register *******************/
2962 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
2964 /******************* Bit definition for SDIO_CMD register *******************/
2965 #define SDIO_CMD_CMDINDEX 0x003FU
2967 #define SDIO_CMD_WAITRESP 0x00C0U
2968 #define SDIO_CMD_WAITRESP_0 0x0040U
2969 #define SDIO_CMD_WAITRESP_1 0x0080U
2971 #define SDIO_CMD_WAITINT 0x0100U
2972 #define SDIO_CMD_WAITPEND 0x0200U
2973 #define SDIO_CMD_CPSMEN 0x0400U
2974 #define SDIO_CMD_SDIOSUSPEND 0x0800U
2975 #define SDIO_CMD_ENCMDCOMPL 0x1000U
2976 #define SDIO_CMD_NIEN 0x2000U
2977 #define SDIO_CMD_CEATACMD 0x4000U
2979 /***************** Bit definition for SDIO_RESPCMD register *****************/
2980 #define SDIO_RESPCMD_RESPCMD 0x3FU
2982 /****************** Bit definition for SDIO_RESP0 register ******************/
2983 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
2985 /****************** Bit definition for SDIO_RESP1 register ******************/
2986 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
2988 /****************** Bit definition for SDIO_RESP2 register ******************/
2989 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
2991 /****************** Bit definition for SDIO_RESP3 register ******************/
2992 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
2994 /****************** Bit definition for SDIO_RESP4 register ******************/
2995 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
2997 /****************** Bit definition for SDIO_DTIMER register *****************/
2998 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
3000 /****************** Bit definition for SDIO_DLEN register *******************/
3001 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
3003 /****************** Bit definition for SDIO_DCTRL register ******************/
3004 #define SDIO_DCTRL_DTEN 0x0001U
3005 #define SDIO_DCTRL_DTDIR 0x0002U
3006 #define SDIO_DCTRL_DTMODE 0x0004U
3007 #define SDIO_DCTRL_DMAEN 0x0008U
3009 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
3010 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
3011 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
3012 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
3013 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
3015 #define SDIO_DCTRL_RWSTART 0x0100U
3016 #define SDIO_DCTRL_RWSTOP 0x0200U
3017 #define SDIO_DCTRL_RWMOD 0x0400U
3018 #define SDIO_DCTRL_SDIOEN 0x0800U
3020 /****************** Bit definition for SDIO_DCOUNT register *****************/
3021 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
3023 /****************** Bit definition for SDIO_STA register ********************/
3024 #define SDIO_STA_CCRCFAIL 0x00000001U
3025 #define SDIO_STA_DCRCFAIL 0x00000002U
3026 #define SDIO_STA_CTIMEOUT 0x00000004U
3027 #define SDIO_STA_DTIMEOUT 0x00000008U
3028 #define SDIO_STA_TXUNDERR 0x00000010U
3029 #define SDIO_STA_RXOVERR 0x00000020U
3030 #define SDIO_STA_CMDREND 0x00000040U
3031 #define SDIO_STA_CMDSENT 0x00000080U
3032 #define SDIO_STA_DATAEND 0x00000100U
3033 #define SDIO_STA_STBITERR 0x00000200U
3034 #define SDIO_STA_DBCKEND 0x00000400U
3035 #define SDIO_STA_CMDACT 0x00000800U
3036 #define SDIO_STA_TXACT 0x00001000U
3037 #define SDIO_STA_RXACT 0x00002000U
3038 #define SDIO_STA_TXFIFOHE 0x00004000U
3039 #define SDIO_STA_RXFIFOHF 0x00008000U
3040 #define SDIO_STA_TXFIFOF 0x00010000U
3041 #define SDIO_STA_RXFIFOF 0x00020000U
3042 #define SDIO_STA_TXFIFOE 0x00040000U
3043 #define SDIO_STA_RXFIFOE 0x00080000U
3044 #define SDIO_STA_TXDAVL 0x00100000U
3045 #define SDIO_STA_RXDAVL 0x00200000U
3046 #define SDIO_STA_SDIOIT 0x00400000U
3047 #define SDIO_STA_CEATAEND 0x00800000U
3049 /******************* Bit definition for SDIO_ICR register *******************/
3050 #define SDIO_ICR_CCRCFAILC 0x00000001U
3051 #define SDIO_ICR_DCRCFAILC 0x00000002U
3052 #define SDIO_ICR_CTIMEOUTC 0x00000004U
3053 #define SDIO_ICR_DTIMEOUTC 0x00000008U
3054 #define SDIO_ICR_TXUNDERRC 0x00000010U
3055 #define SDIO_ICR_RXOVERRC 0x00000020U
3056 #define SDIO_ICR_CMDRENDC 0x00000040U
3057 #define SDIO_ICR_CMDSENTC 0x00000080U
3058 #define SDIO_ICR_DATAENDC 0x00000100U
3059 #define SDIO_ICR_STBITERRC 0x00000200U
3060 #define SDIO_ICR_DBCKENDC 0x00000400U
3061 #define SDIO_ICR_SDIOITC 0x00400000U
3062 #define SDIO_ICR_CEATAENDC 0x00800000U
3064 /****************** Bit definition for SDIO_MASK register *******************/
3065 #define SDIO_MASK_CCRCFAILIE 0x00000001U
3066 #define SDIO_MASK_DCRCFAILIE 0x00000002U
3067 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
3068 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
3069 #define SDIO_MASK_TXUNDERRIE 0x00000010U
3070 #define SDIO_MASK_RXOVERRIE 0x00000020U
3071 #define SDIO_MASK_CMDRENDIE 0x00000040U
3072 #define SDIO_MASK_CMDSENTIE 0x00000080U
3073 #define SDIO_MASK_DATAENDIE 0x00000100U
3074 #define SDIO_MASK_STBITERRIE 0x00000200U
3075 #define SDIO_MASK_DBCKENDIE 0x00000400U
3076 #define SDIO_MASK_CMDACTIE 0x00000800U
3077 #define SDIO_MASK_TXACTIE 0x00001000U
3078 #define SDIO_MASK_RXACTIE 0x00002000U
3079 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
3080 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
3081 #define SDIO_MASK_TXFIFOFIE 0x00010000U
3082 #define SDIO_MASK_RXFIFOFIE 0x00020000U
3083 #define SDIO_MASK_TXFIFOEIE 0x00040000U
3084 #define SDIO_MASK_RXFIFOEIE 0x00080000U
3085 #define SDIO_MASK_TXDAVLIE 0x00100000U
3086 #define SDIO_MASK_RXDAVLIE 0x00200000U
3087 #define SDIO_MASK_SDIOITIE 0x00400000U
3088 #define SDIO_MASK_CEATAENDIE 0x00800000U
3090 /***************** Bit definition for SDIO_FIFOCNT register *****************/
3091 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
3093 /****************** Bit definition for SDIO_FIFO register *******************/
3094 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
3096 /******************************************************************************/
3097 /* */
3098 /* Serial Peripheral Interface */
3099 /* */
3100 /******************************************************************************/
3101 /******************* Bit definition for SPI_CR1 register ********************/
3102 #define SPI_CR1_CPHA 0x00000001U
3103 #define SPI_CR1_CPOL 0x00000002U
3104 #define SPI_CR1_MSTR 0x00000004U
3106 #define SPI_CR1_BR 0x00000038U
3107 #define SPI_CR1_BR_0 0x00000008U
3108 #define SPI_CR1_BR_1 0x00000010U
3109 #define SPI_CR1_BR_2 0x00000020U
3111 #define SPI_CR1_SPE 0x00000040U
3112 #define SPI_CR1_LSBFIRST 0x00000080U
3113 #define SPI_CR1_SSI 0x00000100U
3114 #define SPI_CR1_SSM 0x00000200U
3115 #define SPI_CR1_RXONLY 0x00000400U
3116 #define SPI_CR1_DFF 0x00000800U
3117 #define SPI_CR1_CRCNEXT 0x00001000U
3118 #define SPI_CR1_CRCEN 0x00002000U
3119 #define SPI_CR1_BIDIOE 0x00004000U
3120 #define SPI_CR1_BIDIMODE 0x00008000U
3122 /******************* Bit definition for SPI_CR2 register ********************/
3123 #define SPI_CR2_RXDMAEN 0x00000001U
3124 #define SPI_CR2_TXDMAEN 0x00000002U
3125 #define SPI_CR2_SSOE 0x00000004U
3126 #define SPI_CR2_FRF 0x00000010U
3127 #define SPI_CR2_ERRIE 0x00000020U
3128 #define SPI_CR2_RXNEIE 0x00000040U
3129 #define SPI_CR2_TXEIE 0x00000080U
3131 /******************** Bit definition for SPI_SR register ********************/
3132 #define SPI_SR_RXNE 0x00000001U
3133 #define SPI_SR_TXE 0x00000002U
3134 #define SPI_SR_CHSIDE 0x00000004U
3135 #define SPI_SR_UDR 0x00000008U
3136 #define SPI_SR_CRCERR 0x00000010U
3137 #define SPI_SR_MODF 0x00000020U
3138 #define SPI_SR_OVR 0x00000040U
3139 #define SPI_SR_BSY 0x00000080U
3140 #define SPI_SR_FRE 0x00000100U
3142 /******************** Bit definition for SPI_DR register ********************/
3143 #define SPI_DR_DR 0x0000FFFFU
3145 /******************* Bit definition for SPI_CRCPR register ******************/
3146 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
3148 /****************** Bit definition for SPI_RXCRCR register ******************/
3149 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
3151 /****************** Bit definition for SPI_TXCRCR register ******************/
3152 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
3154 /****************** Bit definition for SPI_I2SCFGR register *****************/
3155 #define SPI_I2SCFGR_CHLEN 0x00000001U
3157 #define SPI_I2SCFGR_DATLEN 0x00000006U
3158 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
3159 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
3161 #define SPI_I2SCFGR_CKPOL 0x00000008U
3163 #define SPI_I2SCFGR_I2SSTD 0x00000030U
3164 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
3165 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
3167 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
3169 #define SPI_I2SCFGR_I2SCFG 0x00000300U
3170 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
3171 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
3173 #define SPI_I2SCFGR_I2SE 0x00000400U
3174 #define SPI_I2SCFGR_I2SMOD 0x00000800U
3176 /****************** Bit definition for SPI_I2SPR register *******************/
3177 #define SPI_I2SPR_I2SDIV 0x000000FFU
3178 #define SPI_I2SPR_ODD 0x00000100U
3179 #define SPI_I2SPR_MCKOE 0x00000200U
3181 /******************************************************************************/
3182 /* */
3183 /* SYSCFG */
3184 /* */
3185 /******************************************************************************/
3186 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
3187 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
3188 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
3189 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
3190 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
3191 
3192 /****************** Bit definition for SYSCFG_PMC register ******************/
3193 #define SYSCFG_PMC_ADC1DC2 0x00010000U
3195 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
3196 #define SYSCFG_EXTICR1_EXTI0 0x000FU
3197 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
3198 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
3199 #define SYSCFG_EXTICR1_EXTI3 0xF000U
3203 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
3204 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
3205 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
3206 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
3207 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
3208 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
3213 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
3214 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
3215 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
3216 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
3217 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
3218 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
3223 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
3224 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
3225 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
3226 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
3227 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
3228 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
3233 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
3234 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
3235 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
3236 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
3237 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
3238 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
3240 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
3241 #define SYSCFG_EXTICR2_EXTI4 0x000FU
3242 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
3243 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
3244 #define SYSCFG_EXTICR2_EXTI7 0xF000U
3248 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
3249 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
3250 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
3251 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
3252 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
3253 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
3258 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
3259 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
3260 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
3261 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
3262 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
3263 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
3268 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
3269 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
3270 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
3271 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
3272 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
3273 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
3278 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
3279 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
3280 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
3281 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
3282 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
3283 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
3286 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
3287 #define SYSCFG_EXTICR3_EXTI8 0x000FU
3288 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
3289 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
3290 #define SYSCFG_EXTICR3_EXTI11 0xF000U
3295 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
3296 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
3297 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
3298 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
3299 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
3300 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
3305 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
3306 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
3307 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
3308 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
3309 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
3310 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
3315 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
3316 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
3317 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
3318 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
3319 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
3320 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
3325 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
3326 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
3327 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
3328 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
3329 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
3330 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
3332 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
3333 #define SYSCFG_EXTICR4_EXTI12 0x000FU
3334 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
3335 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
3336 #define SYSCFG_EXTICR4_EXTI15 0xF000U
3340 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
3341 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
3342 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
3343 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
3344 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
3345 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
3350 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
3351 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
3352 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
3353 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
3354 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
3355 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
3360 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
3361 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
3362 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
3363 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
3364 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
3365 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
3370 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
3371 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
3372 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
3373 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
3374 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
3375 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
3377 /****************** Bit definition for SYSCFG_CMPCR register ****************/
3378 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
3379 #define SYSCFG_CMPCR_READY 0x00000100U
3381 /******************************************************************************/
3382 /* */
3383 /* TIM */
3384 /* */
3385 /******************************************************************************/
3386 /******************* Bit definition for TIM_CR1 register ********************/
3387 #define TIM_CR1_CEN 0x0001U
3388 #define TIM_CR1_UDIS 0x0002U
3389 #define TIM_CR1_URS 0x0004U
3390 #define TIM_CR1_OPM 0x0008U
3391 #define TIM_CR1_DIR 0x0010U
3393 #define TIM_CR1_CMS 0x0060U
3394 #define TIM_CR1_CMS_0 0x0020U
3395 #define TIM_CR1_CMS_1 0x0040U
3397 #define TIM_CR1_ARPE 0x0080U
3399 #define TIM_CR1_CKD 0x0300U
3400 #define TIM_CR1_CKD_0 0x0100U
3401 #define TIM_CR1_CKD_1 0x0200U
3403 /******************* Bit definition for TIM_CR2 register ********************/
3404 #define TIM_CR2_CCPC 0x0001U
3405 #define TIM_CR2_CCUS 0x0004U
3406 #define TIM_CR2_CCDS 0x0008U
3408 #define TIM_CR2_MMS 0x0070U
3409 #define TIM_CR2_MMS_0 0x0010U
3410 #define TIM_CR2_MMS_1 0x0020U
3411 #define TIM_CR2_MMS_2 0x0040U
3413 #define TIM_CR2_TI1S 0x0080U
3414 #define TIM_CR2_OIS1 0x0100U
3415 #define TIM_CR2_OIS1N 0x0200U
3416 #define TIM_CR2_OIS2 0x0400U
3417 #define TIM_CR2_OIS2N 0x0800U
3418 #define TIM_CR2_OIS3 0x1000U
3419 #define TIM_CR2_OIS3N 0x2000U
3420 #define TIM_CR2_OIS4 0x4000U
3422 /******************* Bit definition for TIM_SMCR register *******************/
3423 #define TIM_SMCR_SMS 0x0007U
3424 #define TIM_SMCR_SMS_0 0x0001U
3425 #define TIM_SMCR_SMS_1 0x0002U
3426 #define TIM_SMCR_SMS_2 0x0004U
3428 #define TIM_SMCR_TS 0x0070U
3429 #define TIM_SMCR_TS_0 0x0010U
3430 #define TIM_SMCR_TS_1 0x0020U
3431 #define TIM_SMCR_TS_2 0x0040U
3433 #define TIM_SMCR_MSM 0x0080U
3435 #define TIM_SMCR_ETF 0x0F00U
3436 #define TIM_SMCR_ETF_0 0x0100U
3437 #define TIM_SMCR_ETF_1 0x0200U
3438 #define TIM_SMCR_ETF_2 0x0400U
3439 #define TIM_SMCR_ETF_3 0x0800U
3441 #define TIM_SMCR_ETPS 0x3000U
3442 #define TIM_SMCR_ETPS_0 0x1000U
3443 #define TIM_SMCR_ETPS_1 0x2000U
3445 #define TIM_SMCR_ECE 0x4000U
3446 #define TIM_SMCR_ETP 0x8000U
3448 /******************* Bit definition for TIM_DIER register *******************/
3449 #define TIM_DIER_UIE 0x0001U
3450 #define TIM_DIER_CC1IE 0x0002U
3451 #define TIM_DIER_CC2IE 0x0004U
3452 #define TIM_DIER_CC3IE 0x0008U
3453 #define TIM_DIER_CC4IE 0x0010U
3454 #define TIM_DIER_COMIE 0x0020U
3455 #define TIM_DIER_TIE 0x0040U
3456 #define TIM_DIER_BIE 0x0080U
3457 #define TIM_DIER_UDE 0x0100U
3458 #define TIM_DIER_CC1DE 0x0200U
3459 #define TIM_DIER_CC2DE 0x0400U
3460 #define TIM_DIER_CC3DE 0x0800U
3461 #define TIM_DIER_CC4DE 0x1000U
3462 #define TIM_DIER_COMDE 0x2000U
3463 #define TIM_DIER_TDE 0x4000U
3465 /******************** Bit definition for TIM_SR register ********************/
3466 #define TIM_SR_UIF 0x0001U
3467 #define TIM_SR_CC1IF 0x0002U
3468 #define TIM_SR_CC2IF 0x0004U
3469 #define TIM_SR_CC3IF 0x0008U
3470 #define TIM_SR_CC4IF 0x0010U
3471 #define TIM_SR_COMIF 0x0020U
3472 #define TIM_SR_TIF 0x0040U
3473 #define TIM_SR_BIF 0x0080U
3474 #define TIM_SR_CC1OF 0x0200U
3475 #define TIM_SR_CC2OF 0x0400U
3476 #define TIM_SR_CC3OF 0x0800U
3477 #define TIM_SR_CC4OF 0x1000U
3479 /******************* Bit definition for TIM_EGR register ********************/
3480 #define TIM_EGR_UG 0x01U
3481 #define TIM_EGR_CC1G 0x02U
3482 #define TIM_EGR_CC2G 0x04U
3483 #define TIM_EGR_CC3G 0x08U
3484 #define TIM_EGR_CC4G 0x10U
3485 #define TIM_EGR_COMG 0x20U
3486 #define TIM_EGR_TG 0x40U
3487 #define TIM_EGR_BG 0x80U
3489 /****************** Bit definition for TIM_CCMR1 register *******************/
3490 #define TIM_CCMR1_CC1S 0x0003U
3491 #define TIM_CCMR1_CC1S_0 0x0001U
3492 #define TIM_CCMR1_CC1S_1 0x0002U
3494 #define TIM_CCMR1_OC1FE 0x0004U
3495 #define TIM_CCMR1_OC1PE 0x0008U
3497 #define TIM_CCMR1_OC1M 0x0070U
3498 #define TIM_CCMR1_OC1M_0 0x0010U
3499 #define TIM_CCMR1_OC1M_1 0x0020U
3500 #define TIM_CCMR1_OC1M_2 0x0040U
3502 #define TIM_CCMR1_OC1CE 0x0080U
3504 #define TIM_CCMR1_CC2S 0x0300U
3505 #define TIM_CCMR1_CC2S_0 0x0100U
3506 #define TIM_CCMR1_CC2S_1 0x0200U
3508 #define TIM_CCMR1_OC2FE 0x0400U
3509 #define TIM_CCMR1_OC2PE 0x0800U
3511 #define TIM_CCMR1_OC2M 0x7000U
3512 #define TIM_CCMR1_OC2M_0 0x1000U
3513 #define TIM_CCMR1_OC2M_1 0x2000U
3514 #define TIM_CCMR1_OC2M_2 0x4000U
3516 #define TIM_CCMR1_OC2CE 0x8000U
3518 /*----------------------------------------------------------------------------*/
3519 
3520 #define TIM_CCMR1_IC1PSC 0x000CU
3521 #define TIM_CCMR1_IC1PSC_0 0x0004U
3522 #define TIM_CCMR1_IC1PSC_1 0x0008U
3524 #define TIM_CCMR1_IC1F 0x00F0U
3525 #define TIM_CCMR1_IC1F_0 0x0010U
3526 #define TIM_CCMR1_IC1F_1 0x0020U
3527 #define TIM_CCMR1_IC1F_2 0x0040U
3528 #define TIM_CCMR1_IC1F_3 0x0080U
3530 #define TIM_CCMR1_IC2PSC 0x0C00U
3531 #define TIM_CCMR1_IC2PSC_0 0x0400U
3532 #define TIM_CCMR1_IC2PSC_1 0x0800U
3534 #define TIM_CCMR1_IC2F 0xF000U
3535 #define TIM_CCMR1_IC2F_0 0x1000U
3536 #define TIM_CCMR1_IC2F_1 0x2000U
3537 #define TIM_CCMR1_IC2F_2 0x4000U
3538 #define TIM_CCMR1_IC2F_3 0x8000U
3540 /****************** Bit definition for TIM_CCMR2 register *******************/
3541 #define TIM_CCMR2_CC3S 0x0003U
3542 #define TIM_CCMR2_CC3S_0 0x0001U
3543 #define TIM_CCMR2_CC3S_1 0x0002U
3545 #define TIM_CCMR2_OC3FE 0x0004U
3546 #define TIM_CCMR2_OC3PE 0x0008U
3548 #define TIM_CCMR2_OC3M 0x0070U
3549 #define TIM_CCMR2_OC3M_0 0x0010U
3550 #define TIM_CCMR2_OC3M_1 0x0020U
3551 #define TIM_CCMR2_OC3M_2 0x0040U
3553 #define TIM_CCMR2_OC3CE 0x0080U
3555 #define TIM_CCMR2_CC4S 0x0300U
3556 #define TIM_CCMR2_CC4S_0 0x0100U
3557 #define TIM_CCMR2_CC4S_1 0x0200U
3559 #define TIM_CCMR2_OC4FE 0x0400U
3560 #define TIM_CCMR2_OC4PE 0x0800U
3562 #define TIM_CCMR2_OC4M 0x7000U
3563 #define TIM_CCMR2_OC4M_0 0x1000U
3564 #define TIM_CCMR2_OC4M_1 0x2000U
3565 #define TIM_CCMR2_OC4M_2 0x4000U
3567 #define TIM_CCMR2_OC4CE 0x8000U
3569 /*----------------------------------------------------------------------------*/
3570 
3571 #define TIM_CCMR2_IC3PSC 0x000CU
3572 #define TIM_CCMR2_IC3PSC_0 0x0004U
3573 #define TIM_CCMR2_IC3PSC_1 0x0008U
3575 #define TIM_CCMR2_IC3F 0x00F0U
3576 #define TIM_CCMR2_IC3F_0 0x0010U
3577 #define TIM_CCMR2_IC3F_1 0x0020U
3578 #define TIM_CCMR2_IC3F_2 0x0040U
3579 #define TIM_CCMR2_IC3F_3 0x0080U
3581 #define TIM_CCMR2_IC4PSC 0x0C00U
3582 #define TIM_CCMR2_IC4PSC_0 0x0400U
3583 #define TIM_CCMR2_IC4PSC_1 0x0800U
3585 #define TIM_CCMR2_IC4F 0xF000U
3586 #define TIM_CCMR2_IC4F_0 0x1000U
3587 #define TIM_CCMR2_IC4F_1 0x2000U
3588 #define TIM_CCMR2_IC4F_2 0x4000U
3589 #define TIM_CCMR2_IC4F_3 0x8000U
3591 /******************* Bit definition for TIM_CCER register *******************/
3592 #define TIM_CCER_CC1E 0x0001U
3593 #define TIM_CCER_CC1P 0x0002U
3594 #define TIM_CCER_CC1NE 0x0004U
3595 #define TIM_CCER_CC1NP 0x0008U
3596 #define TIM_CCER_CC2E 0x0010U
3597 #define TIM_CCER_CC2P 0x0020U
3598 #define TIM_CCER_CC2NE 0x0040U
3599 #define TIM_CCER_CC2NP 0x0080U
3600 #define TIM_CCER_CC3E 0x0100U
3601 #define TIM_CCER_CC3P 0x0200U
3602 #define TIM_CCER_CC3NE 0x0400U
3603 #define TIM_CCER_CC3NP 0x0800U
3604 #define TIM_CCER_CC4E 0x1000U
3605 #define TIM_CCER_CC4P 0x2000U
3606 #define TIM_CCER_CC4NP 0x8000U
3608 /******************* Bit definition for TIM_CNT register ********************/
3609 #define TIM_CNT_CNT 0xFFFFU
3611 /******************* Bit definition for TIM_PSC register ********************/
3612 #define TIM_PSC_PSC 0xFFFFU
3614 /******************* Bit definition for TIM_ARR register ********************/
3615 #define TIM_ARR_ARR 0xFFFFU
3617 /******************* Bit definition for TIM_RCR register ********************/
3618 #define TIM_RCR_REP 0xFFU
3620 /******************* Bit definition for TIM_CCR1 register *******************/
3621 #define TIM_CCR1_CCR1 0xFFFFU
3623 /******************* Bit definition for TIM_CCR2 register *******************/
3624 #define TIM_CCR2_CCR2 0xFFFFU
3626 /******************* Bit definition for TIM_CCR3 register *******************/
3627 #define TIM_CCR3_CCR3 0xFFFFU
3629 /******************* Bit definition for TIM_CCR4 register *******************/
3630 #define TIM_CCR4_CCR4 0xFFFFU
3632 /******************* Bit definition for TIM_BDTR register *******************/
3633 #define TIM_BDTR_DTG 0x00FFU
3634 #define TIM_BDTR_DTG_0 0x0001U
3635 #define TIM_BDTR_DTG_1 0x0002U
3636 #define TIM_BDTR_DTG_2 0x0004U
3637 #define TIM_BDTR_DTG_3 0x0008U
3638 #define TIM_BDTR_DTG_4 0x0010U
3639 #define TIM_BDTR_DTG_5 0x0020U
3640 #define TIM_BDTR_DTG_6 0x0040U
3641 #define TIM_BDTR_DTG_7 0x0080U
3643 #define TIM_BDTR_LOCK 0x0300U
3644 #define TIM_BDTR_LOCK_0 0x0100U
3645 #define TIM_BDTR_LOCK_1 0x0200U
3647 #define TIM_BDTR_OSSI 0x0400U
3648 #define TIM_BDTR_OSSR 0x0800U
3649 #define TIM_BDTR_BKE 0x1000U
3650 #define TIM_BDTR_BKP 0x2000U
3651 #define TIM_BDTR_AOE 0x4000U
3652 #define TIM_BDTR_MOE 0x8000U
3654 /******************* Bit definition for TIM_DCR register ********************/
3655 #define TIM_DCR_DBA 0x001FU
3656 #define TIM_DCR_DBA_0 0x0001U
3657 #define TIM_DCR_DBA_1 0x0002U
3658 #define TIM_DCR_DBA_2 0x0004U
3659 #define TIM_DCR_DBA_3 0x0008U
3660 #define TIM_DCR_DBA_4 0x0010U
3662 #define TIM_DCR_DBL 0x1F00U
3663 #define TIM_DCR_DBL_0 0x0100U
3664 #define TIM_DCR_DBL_1 0x0200U
3665 #define TIM_DCR_DBL_2 0x0400U
3666 #define TIM_DCR_DBL_3 0x0800U
3667 #define TIM_DCR_DBL_4 0x1000U
3669 /******************* Bit definition for TIM_DMAR register *******************/
3670 #define TIM_DMAR_DMAB 0xFFFFU
3672 /******************* Bit definition for TIM_OR register *********************/
3673 #define TIM_OR_TI4_RMP 0x00C0U
3674 #define TIM_OR_TI4_RMP_0 0x0040U
3675 #define TIM_OR_TI4_RMP_1 0x0080U
3676 #define TIM_OR_ITR1_RMP 0x0C00U
3677 #define TIM_OR_ITR1_RMP_0 0x0400U
3678 #define TIM_OR_ITR1_RMP_1 0x0800U
3681 /******************************************************************************/
3682 /* */
3683 /* Universal Synchronous Asynchronous Receiver Transmitter */
3684 /* */
3685 /******************************************************************************/
3686 /******************* Bit definition for USART_SR register *******************/
3687 #define USART_SR_PE 0x0001U
3688 #define USART_SR_FE 0x0002U
3689 #define USART_SR_NE 0x0004U
3690 #define USART_SR_ORE 0x0008U
3691 #define USART_SR_IDLE 0x0010U
3692 #define USART_SR_RXNE 0x0020U
3693 #define USART_SR_TC 0x0040U
3694 #define USART_SR_TXE 0x0080U
3695 #define USART_SR_LBD 0x0100U
3696 #define USART_SR_CTS 0x0200U
3698 /******************* Bit definition for USART_DR register *******************/
3699 #define USART_DR_DR 0x01FFU
3701 /****************** Bit definition for USART_BRR register *******************/
3702 #define USART_BRR_DIV_Fraction 0x000FU
3703 #define USART_BRR_DIV_Mantissa 0xFFF0U
3705 /****************** Bit definition for USART_CR1 register *******************/
3706 #define USART_CR1_SBK 0x0001U
3707 #define USART_CR1_RWU 0x0002U
3708 #define USART_CR1_RE 0x0004U
3709 #define USART_CR1_TE 0x0008U
3710 #define USART_CR1_IDLEIE 0x0010U
3711 #define USART_CR1_RXNEIE 0x0020U
3712 #define USART_CR1_TCIE 0x0040U
3713 #define USART_CR1_TXEIE 0x0080U
3714 #define USART_CR1_PEIE 0x0100U
3715 #define USART_CR1_PS 0x0200U
3716 #define USART_CR1_PCE 0x0400U
3717 #define USART_CR1_WAKE 0x0800U
3718 #define USART_CR1_M 0x1000U
3719 #define USART_CR1_UE 0x2000U
3720 #define USART_CR1_OVER8 0x8000U
3722 /****************** Bit definition for USART_CR2 register *******************/
3723 #define USART_CR2_ADD 0x000FU
3724 #define USART_CR2_LBDL 0x0020U
3725 #define USART_CR2_LBDIE 0x0040U
3726 #define USART_CR2_LBCL 0x0100U
3727 #define USART_CR2_CPHA 0x0200U
3728 #define USART_CR2_CPOL 0x0400U
3729 #define USART_CR2_CLKEN 0x0800U
3731 #define USART_CR2_STOP 0x3000U
3732 #define USART_CR2_STOP_0 0x1000U
3733 #define USART_CR2_STOP_1 0x2000U
3735 #define USART_CR2_LINEN 0x4000U
3737 /****************** Bit definition for USART_CR3 register *******************/
3738 #define USART_CR3_EIE 0x0001U
3739 #define USART_CR3_IREN 0x0002U
3740 #define USART_CR3_IRLP 0x0004U
3741 #define USART_CR3_HDSEL 0x0008U
3742 #define USART_CR3_NACK 0x0010U
3743 #define USART_CR3_SCEN 0x0020U
3744 #define USART_CR3_DMAR 0x0040U
3745 #define USART_CR3_DMAT 0x0080U
3746 #define USART_CR3_RTSE 0x0100U
3747 #define USART_CR3_CTSE 0x0200U
3748 #define USART_CR3_CTSIE 0x0400U
3749 #define USART_CR3_ONEBIT 0x0800U
3751 /****************** Bit definition for USART_GTPR register ******************/
3752 #define USART_GTPR_PSC 0x00FFU
3753 #define USART_GTPR_PSC_0 0x0001U
3754 #define USART_GTPR_PSC_1 0x0002U
3755 #define USART_GTPR_PSC_2 0x0004U
3756 #define USART_GTPR_PSC_3 0x0008U
3757 #define USART_GTPR_PSC_4 0x0010U
3758 #define USART_GTPR_PSC_5 0x0020U
3759 #define USART_GTPR_PSC_6 0x0040U
3760 #define USART_GTPR_PSC_7 0x0080U
3762 #define USART_GTPR_GT 0xFF00U
3764 /******************************************************************************/
3765 /* */
3766 /* Window WATCHDOG */
3767 /* */
3768 /******************************************************************************/
3769 /******************* Bit definition for WWDG_CR register ********************/
3770 #define WWDG_CR_T 0x7FU
3771 #define WWDG_CR_T_0 0x01U
3772 #define WWDG_CR_T_1 0x02U
3773 #define WWDG_CR_T_2 0x04U
3774 #define WWDG_CR_T_3 0x08U
3775 #define WWDG_CR_T_4 0x10U
3776 #define WWDG_CR_T_5 0x20U
3777 #define WWDG_CR_T_6 0x40U
3778 /* Legacy defines */
3779 #define WWDG_CR_T0 WWDG_CR_T_0
3780 #define WWDG_CR_T1 WWDG_CR_T_1
3781 #define WWDG_CR_T2 WWDG_CR_T_2
3782 #define WWDG_CR_T3 WWDG_CR_T_3
3783 #define WWDG_CR_T4 WWDG_CR_T_4
3784 #define WWDG_CR_T5 WWDG_CR_T_5
3785 #define WWDG_CR_T6 WWDG_CR_T_6
3786 
3787 #define WWDG_CR_WDGA 0x80U
3789 /******************* Bit definition for WWDG_CFR register *******************/
3790 #define WWDG_CFR_W 0x007FU
3791 #define WWDG_CFR_W_0 0x0001U
3792 #define WWDG_CFR_W_1 0x0002U
3793 #define WWDG_CFR_W_2 0x0004U
3794 #define WWDG_CFR_W_3 0x0008U
3795 #define WWDG_CFR_W_4 0x0010U
3796 #define WWDG_CFR_W_5 0x0020U
3797 #define WWDG_CFR_W_6 0x0040U
3798 /* Legacy defines */
3799 #define WWDG_CFR_W0 WWDG_CFR_W_0
3800 #define WWDG_CFR_W1 WWDG_CFR_W_1
3801 #define WWDG_CFR_W2 WWDG_CFR_W_2
3802 #define WWDG_CFR_W3 WWDG_CFR_W_3
3803 #define WWDG_CFR_W4 WWDG_CFR_W_4
3804 #define WWDG_CFR_W5 WWDG_CFR_W_5
3805 #define WWDG_CFR_W6 WWDG_CFR_W_6
3806 
3807 #define WWDG_CFR_WDGTB 0x0180U
3808 #define WWDG_CFR_WDGTB_0 0x0080U
3809 #define WWDG_CFR_WDGTB_1 0x0100U
3810 /* Legacy defines */
3811 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
3812 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
3813 
3814 #define WWDG_CFR_EWI 0x0200U
3816 /******************* Bit definition for WWDG_SR register ********************/
3817 #define WWDG_SR_EWIF 0x01U
3820 /******************************************************************************/
3821 /* */
3822 /* DBG */
3823 /* */
3824 /******************************************************************************/
3825 /******************** Bit definition for DBGMCU_IDCODE register *************/
3826 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
3827 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
3828 
3829 /******************** Bit definition for DBGMCU_CR register *****************/
3830 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
3831 #define DBGMCU_CR_DBG_STOP 0x00000002U
3832 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
3833 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
3834 
3835 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
3836 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
3837 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
3839 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
3840 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
3841 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
3842 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
3843 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
3844 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
3845 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
3846 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
3847 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
3848 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
3849 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
3850 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
3851 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
3852 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
3853 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
3854 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
3855 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
3856 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
3857 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
3858 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
3859 
3860 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
3861 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
3862 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
3863 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
3864 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
3865 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
3866 
3867 /******************************************************************************/
3868 /* */
3869 /* USB_OTG */
3870 /* */
3871 /******************************************************************************/
3872 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
3873 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
3874 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
3875 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
3876 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
3877 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
3878 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
3879 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
3880 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
3881 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
3882 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
3884 /******************** Bit definition forUSB_OTG_HCFG register ********************/
3885 
3886 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
3887 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
3888 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
3889 #define USB_OTG_HCFG_FSLSS 0x00000004U
3891 /******************** Bit definition forUSB_OTG_DCFG register ********************/
3892 
3893 #define USB_OTG_DCFG_DSPD 0x00000003U
3894 #define USB_OTG_DCFG_DSPD_0 0x00000001U
3895 #define USB_OTG_DCFG_DSPD_1 0x00000002U
3896 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
3898 #define USB_OTG_DCFG_DAD 0x000007F0U
3899 #define USB_OTG_DCFG_DAD_0 0x00000010U
3900 #define USB_OTG_DCFG_DAD_1 0x00000020U
3901 #define USB_OTG_DCFG_DAD_2 0x00000040U
3902 #define USB_OTG_DCFG_DAD_3 0x00000080U
3903 #define USB_OTG_DCFG_DAD_4 0x00000100U
3904 #define USB_OTG_DCFG_DAD_5 0x00000200U
3905 #define USB_OTG_DCFG_DAD_6 0x00000400U
3907 #define USB_OTG_DCFG_PFIVL 0x00001800U
3908 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
3909 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
3911 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
3912 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
3913 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
3915 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
3916 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
3917 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
3918 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
3920 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
3921 #define USB_OTG_GOTGINT_SEDET 0x00000004U
3922 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
3923 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
3924 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
3925 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
3926 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
3928 /******************** Bit definition forUSB_OTG_DCTL register ********************/
3929 #define USB_OTG_DCTL_RWUSIG 0x00000001U
3930 #define USB_OTG_DCTL_SDIS 0x00000002U
3931 #define USB_OTG_DCTL_GINSTS 0x00000004U
3932 #define USB_OTG_DCTL_GONSTS 0x00000008U
3934 #define USB_OTG_DCTL_TCTL 0x00000070U
3935 #define USB_OTG_DCTL_TCTL_0 0x00000010U
3936 #define USB_OTG_DCTL_TCTL_1 0x00000020U
3937 #define USB_OTG_DCTL_TCTL_2 0x00000040U
3938 #define USB_OTG_DCTL_SGINAK 0x00000080U
3939 #define USB_OTG_DCTL_CGINAK 0x00000100U
3940 #define USB_OTG_DCTL_SGONAK 0x00000200U
3941 #define USB_OTG_DCTL_CGONAK 0x00000400U
3942 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
3944 /******************** Bit definition forUSB_OTG_HFIR register ********************/
3945 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
3947 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
3948 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
3949 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
3951 /******************** Bit definition forUSB_OTG_DSTS register ********************/
3952 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
3954 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
3955 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
3956 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
3957 #define USB_OTG_DSTS_EERR 0x00000008U
3958 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
3960 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
3961 #define USB_OTG_GAHBCFG_GINT 0x00000001U
3963 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
3964 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
3965 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
3966 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
3967 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
3968 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
3969 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
3970 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
3972 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
3973 
3974 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
3975 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
3976 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
3977 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
3978 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
3979 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
3980 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
3982 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
3983 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
3984 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
3985 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
3986 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
3987 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
3988 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
3989 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
3990 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
3991 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
3992 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
3993 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
3994 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
3995 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
3996 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
3997 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
3998 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
3999 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
4001 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
4002 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
4003 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
4004 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
4005 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
4006 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
4008 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
4009 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
4010 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
4011 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
4012 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
4013 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
4014 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
4015 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
4017 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
4018 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
4019 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
4020 #define USB_OTG_DIEPMSK_TOM 0x00000008U
4021 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
4022 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
4023 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
4024 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
4025 #define USB_OTG_DIEPMSK_BIM 0x00000200U
4027 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
4028 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
4030 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
4031 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
4032 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
4033 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
4034 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
4035 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
4036 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
4037 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
4038 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
4040 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
4041 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
4042 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
4043 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
4044 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
4045 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
4046 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
4047 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
4048 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
4050 /******************** Bit definition forUSB_OTG_HAINT register ********************/
4051 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
4053 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
4054 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
4055 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
4056 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
4057 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
4058 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
4059 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
4060 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
4062 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
4063 #define USB_OTG_GINTSTS_CMOD 0x00000001U
4064 #define USB_OTG_GINTSTS_MMIS 0x00000002U
4065 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
4066 #define USB_OTG_GINTSTS_SOF 0x00000008U
4067 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
4068 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
4069 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
4070 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
4071 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
4072 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
4073 #define USB_OTG_GINTSTS_USBRST 0x00001000U
4074 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
4075 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
4076 #define USB_OTG_GINTSTS_EOPF 0x00008000U
4077 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
4078 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
4079 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
4080 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
4081 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
4082 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
4083 #define USB_OTG_GINTSTS_HCINT 0x02000000U
4084 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
4085 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
4086 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
4087 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
4088 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
4090 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
4091 #define USB_OTG_GINTMSK_MMISM 0x00000002U
4092 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
4093 #define USB_OTG_GINTMSK_SOFM 0x00000008U
4094 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
4095 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
4096 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
4097 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
4098 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
4099 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
4100 #define USB_OTG_GINTMSK_USBRST 0x00001000U
4101 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
4102 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
4103 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
4104 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
4105 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
4106 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
4107 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
4108 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
4109 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
4110 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
4111 #define USB_OTG_GINTMSK_HCIM 0x02000000U
4112 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
4113 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
4114 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
4115 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
4116 #define USB_OTG_GINTMSK_WUIM 0x80000000U
4118 /******************** Bit definition forUSB_OTG_DAINT register ********************/
4119 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
4120 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
4122 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
4123 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
4125 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
4126 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
4127 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
4128 #define USB_OTG_GRXSTSP_DPID 0x00018000U
4129 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
4131 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
4132 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
4133 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
4135 /******************** Bit definition for OTG register ********************/
4136 
4137 #define USB_OTG_CHNUM 0x0000000FU
4138 #define USB_OTG_CHNUM_0 0x00000001U
4139 #define USB_OTG_CHNUM_1 0x00000002U
4140 #define USB_OTG_CHNUM_2 0x00000004U
4141 #define USB_OTG_CHNUM_3 0x00000008U
4142 #define USB_OTG_BCNT 0x00007FF0U
4144 #define USB_OTG_DPID 0x00018000U
4145 #define USB_OTG_DPID_0 0x00008000U
4146 #define USB_OTG_DPID_1 0x00010000U
4148 #define USB_OTG_PKTSTS 0x001E0000U
4149 #define USB_OTG_PKTSTS_0 0x00020000U
4150 #define USB_OTG_PKTSTS_1 0x00040000U
4151 #define USB_OTG_PKTSTS_2 0x00080000U
4152 #define USB_OTG_PKTSTS_3 0x00100000U
4154 #define USB_OTG_EPNUM 0x0000000FU
4155 #define USB_OTG_EPNUM_0 0x00000001U
4156 #define USB_OTG_EPNUM_1 0x00000002U
4157 #define USB_OTG_EPNUM_2 0x00000004U
4158 #define USB_OTG_EPNUM_3 0x00000008U
4160 #define USB_OTG_FRMNUM 0x01E00000U
4161 #define USB_OTG_FRMNUM_0 0x00200000U
4162 #define USB_OTG_FRMNUM_1 0x00400000U
4163 #define USB_OTG_FRMNUM_2 0x00800000U
4164 #define USB_OTG_FRMNUM_3 0x01000000U
4166 /******************** Bit definition for OTG register ********************/
4167 
4168 #define USB_OTG_CHNUM 0x0000000FU
4169 #define USB_OTG_CHNUM_0 0x00000001U
4170 #define USB_OTG_CHNUM_1 0x00000002U
4171 #define USB_OTG_CHNUM_2 0x00000004U
4172 #define USB_OTG_CHNUM_3 0x00000008U
4173 #define USB_OTG_BCNT 0x00007FF0U
4175 #define USB_OTG_DPID 0x00018000U
4176 #define USB_OTG_DPID_0 0x00008000U
4177 #define USB_OTG_DPID_1 0x00010000U
4179 #define USB_OTG_PKTSTS 0x001E0000U
4180 #define USB_OTG_PKTSTS_0 0x00020000U
4181 #define USB_OTG_PKTSTS_1 0x00040000U
4182 #define USB_OTG_PKTSTS_2 0x00080000U
4183 #define USB_OTG_PKTSTS_3 0x00100000U
4185 #define USB_OTG_EPNUM 0x0000000FU
4186 #define USB_OTG_EPNUM_0 0x00000001U
4187 #define USB_OTG_EPNUM_1 0x00000002U
4188 #define USB_OTG_EPNUM_2 0x00000004U
4189 #define USB_OTG_EPNUM_3 0x00000008U
4191 #define USB_OTG_FRMNUM 0x01E00000U
4192 #define USB_OTG_FRMNUM_0 0x00200000U
4193 #define USB_OTG_FRMNUM_1 0x00400000U
4194 #define USB_OTG_FRMNUM_2 0x00800000U
4195 #define USB_OTG_FRMNUM_3 0x01000000U
4197 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
4198 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
4200 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
4201 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
4203 /******************** Bit definition for OTG register ********************/
4204 #define USB_OTG_NPTXFSA 0x0000FFFFU
4205 #define USB_OTG_NPTXFD 0xFFFF0000U
4206 #define USB_OTG_TX0FSA 0x0000FFFFU
4207 #define USB_OTG_TX0FD 0xFFFF0000U
4209 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
4210 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
4212 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
4213 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
4215 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
4216 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
4217 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
4218 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
4219 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
4220 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
4221 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
4222 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
4223 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
4225 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
4226 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
4227 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
4228 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
4229 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
4230 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
4231 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
4232 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
4234 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
4235 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
4236 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
4238 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
4239 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
4240 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
4241 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
4242 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
4243 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
4244 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
4245 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
4246 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
4247 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
4248 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
4250 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
4251 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
4252 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
4253 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
4254 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
4255 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
4256 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
4257 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
4258 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
4259 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
4260 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
4262 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
4263 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
4265 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
4266 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
4267 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
4269 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
4270 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
4271 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
4272 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
4273 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
4274 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
4275 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
4277 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
4278 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
4279 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
4281 /******************** Bit definition forUSB_OTG_CID register ********************/
4282 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
4284 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
4285 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
4286 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
4287 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
4288 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
4289 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
4290 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
4291 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
4292 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
4293 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
4295 /******************** Bit definition forUSB_OTG_HPRT register ********************/
4296 #define USB_OTG_HPRT_PCSTS 0x00000001U
4297 #define USB_OTG_HPRT_PCDET 0x00000002U
4298 #define USB_OTG_HPRT_PENA 0x00000004U
4299 #define USB_OTG_HPRT_PENCHNG 0x00000008U
4300 #define USB_OTG_HPRT_POCA 0x00000010U
4301 #define USB_OTG_HPRT_POCCHNG 0x00000020U
4302 #define USB_OTG_HPRT_PRES 0x00000040U
4303 #define USB_OTG_HPRT_PSUSP 0x00000080U
4304 #define USB_OTG_HPRT_PRST 0x00000100U
4306 #define USB_OTG_HPRT_PLSTS 0x00000C00U
4307 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
4308 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
4309 #define USB_OTG_HPRT_PPWR 0x00001000U
4311 #define USB_OTG_HPRT_PTCTL 0x0001E000U
4312 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
4313 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
4314 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
4315 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
4317 #define USB_OTG_HPRT_PSPD 0x00060000U
4318 #define USB_OTG_HPRT_PSPD_0 0x00020000U
4319 #define USB_OTG_HPRT_PSPD_1 0x00040000U
4321 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
4322 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
4323 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
4324 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
4325 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
4326 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
4327 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
4328 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
4329 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
4330 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
4331 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
4332 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
4334 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
4335 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
4336 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
4338 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
4339 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
4340 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
4341 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
4342 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
4344 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
4345 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
4346 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
4347 #define USB_OTG_DIEPCTL_STALL 0x00200000U
4349 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
4350 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
4351 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
4352 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
4353 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
4354 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
4355 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
4356 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
4357 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
4358 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
4359 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
4361 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
4362 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
4364 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
4365 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
4366 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
4367 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
4368 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
4369 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
4370 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
4372 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
4373 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
4374 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
4376 #define USB_OTG_HCCHAR_MC 0x00300000U
4377 #define USB_OTG_HCCHAR_MC_0 0x00100000U
4378 #define USB_OTG_HCCHAR_MC_1 0x00200000U
4380 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
4381 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
4382 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
4383 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
4384 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
4385 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
4386 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
4387 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
4388 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
4389 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
4390 #define USB_OTG_HCCHAR_CHENA 0x80000000U
4392 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
4393 
4394 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
4395 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
4396 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
4397 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
4398 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
4399 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
4400 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
4401 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
4403 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
4404 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
4405 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
4406 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
4407 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
4408 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
4409 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
4410 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
4412 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
4413 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
4414 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
4415 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
4416 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
4418 /******************** Bit definition forUSB_OTG_HCINT register ********************/
4419 #define USB_OTG_HCINT_XFRC 0x00000001U
4420 #define USB_OTG_HCINT_CHH 0x00000002U
4421 #define USB_OTG_HCINT_AHBERR 0x00000004U
4422 #define USB_OTG_HCINT_STALL 0x00000008U
4423 #define USB_OTG_HCINT_NAK 0x00000010U
4424 #define USB_OTG_HCINT_ACK 0x00000020U
4425 #define USB_OTG_HCINT_NYET 0x00000040U
4426 #define USB_OTG_HCINT_TXERR 0x00000080U
4427 #define USB_OTG_HCINT_BBERR 0x00000100U
4428 #define USB_OTG_HCINT_FRMOR 0x00000200U
4429 #define USB_OTG_HCINT_DTERR 0x00000400U
4431 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
4432 #define USB_OTG_DIEPINT_XFRC 0x00000001U
4433 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
4434 #define USB_OTG_DIEPINT_TOC 0x00000008U
4435 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
4436 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
4437 #define USB_OTG_DIEPINT_TXFE 0x00000080U
4438 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
4439 #define USB_OTG_DIEPINT_BNA 0x00000200U
4440 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
4441 #define USB_OTG_DIEPINT_BERR 0x00001000U
4442 #define USB_OTG_DIEPINT_NAK 0x00002000U
4444 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
4445 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
4446 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
4447 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
4448 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
4449 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
4450 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
4451 #define USB_OTG_HCINTMSK_NYET 0x00000040U
4452 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
4453 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
4454 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
4455 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
4457 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
4458 
4459 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
4460 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
4461 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
4462 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
4463 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
4464 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
4465 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
4466 #define USB_OTG_HCTSIZ_DPID 0x60000000U
4467 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
4468 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
4470 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
4471 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
4473 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
4474 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
4476 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
4477 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
4479 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
4480 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
4481 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
4483 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
4484 
4485 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
4486 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
4487 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
4488 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
4489 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
4490 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
4491 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
4492 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
4493 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
4494 #define USB_OTG_DOEPCTL_STALL 0x00200000U
4495 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
4496 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
4497 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
4498 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
4500 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
4501 #define USB_OTG_DOEPINT_XFRC 0x00000001U
4502 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
4503 #define USB_OTG_DOEPINT_STUP 0x00000008U
4504 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
4505 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
4506 #define USB_OTG_DOEPINT_NYET 0x00004000U
4508 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
4509 
4510 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
4511 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
4513 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
4514 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
4515 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
4517 /******************** Bit definition for PCGCCTL register ********************/
4518 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
4519 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
4520 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
4534 /******************************* ADC Instances ********************************/
4535 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
4536 
4537 /******************************* CRC Instances ********************************/
4538 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
4539 
4540 /******************************** DMA Instances *******************************/
4541 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
4542  ((INSTANCE) == DMA1_Stream1) || \
4543  ((INSTANCE) == DMA1_Stream2) || \
4544  ((INSTANCE) == DMA1_Stream3) || \
4545  ((INSTANCE) == DMA1_Stream4) || \
4546  ((INSTANCE) == DMA1_Stream5) || \
4547  ((INSTANCE) == DMA1_Stream6) || \
4548  ((INSTANCE) == DMA1_Stream7) || \
4549  ((INSTANCE) == DMA2_Stream0) || \
4550  ((INSTANCE) == DMA2_Stream1) || \
4551  ((INSTANCE) == DMA2_Stream2) || \
4552  ((INSTANCE) == DMA2_Stream3) || \
4553  ((INSTANCE) == DMA2_Stream4) || \
4554  ((INSTANCE) == DMA2_Stream5) || \
4555  ((INSTANCE) == DMA2_Stream6) || \
4556  ((INSTANCE) == DMA2_Stream7))
4557 
4558 /******************************* GPIO Instances *******************************/
4559 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
4560  ((INSTANCE) == GPIOB) || \
4561  ((INSTANCE) == GPIOC) || \
4562  ((INSTANCE) == GPIOD) || \
4563  ((INSTANCE) == GPIOE) || \
4564  ((INSTANCE) == GPIOH))
4565 
4566 /******************************** I2C Instances *******************************/
4567 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
4568  ((INSTANCE) == I2C2) || \
4569  ((INSTANCE) == I2C3))
4570 
4571 /******************************** I2S Instances *******************************/
4572 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
4573  ((INSTANCE) == SPI2) || \
4574  ((INSTANCE) == SPI3) || \
4575  ((INSTANCE) == SPI4) || \
4576  ((INSTANCE) == SPI5))
4577 
4578 /*************************** I2S Extended Instances ***************************/
4579 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
4580  ((INSTANCE) == SPI3) || \
4581  ((INSTANCE) == I2S2ext) || \
4582  ((INSTANCE) == I2S3ext))
4583 
4584 
4585 /****************************** RTC Instances *********************************/
4586 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
4587 
4588 /******************************** SPI Instances *******************************/
4589 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
4590  ((INSTANCE) == SPI2) || \
4591  ((INSTANCE) == SPI3) || \
4592  ((INSTANCE) == SPI4) || \
4593  ((INSTANCE) == SPI5))
4594 /*************************** SPI Extended Instances ***************************/
4595 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
4596  ((INSTANCE) == SPI2) || \
4597  ((INSTANCE) == SPI3) || \
4598  ((INSTANCE) == SPI4) || \
4599  ((INSTANCE) == SPI5) || \
4600  ((INSTANCE) == I2S2ext) || \
4601  ((INSTANCE) == I2S3ext))
4602 
4603 /****************** TIM Instances : All supported instances *******************/
4604 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4605  ((INSTANCE) == TIM2) || \
4606  ((INSTANCE) == TIM3) || \
4607  ((INSTANCE) == TIM4) || \
4608  ((INSTANCE) == TIM5) || \
4609  ((INSTANCE) == TIM9) || \
4610  ((INSTANCE) == TIM10) || \
4611  ((INSTANCE) == TIM11))
4612 
4613 /************* TIM Instances : at least 1 capture/compare channel *************/
4614 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4615  ((INSTANCE) == TIM2) || \
4616  ((INSTANCE) == TIM3) || \
4617  ((INSTANCE) == TIM4) || \
4618  ((INSTANCE) == TIM5) || \
4619  ((INSTANCE) == TIM9) || \
4620  ((INSTANCE) == TIM10) || \
4621  ((INSTANCE) == TIM11))
4622 
4623 /************ TIM Instances : at least 2 capture/compare channels *************/
4624 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4625  ((INSTANCE) == TIM2) || \
4626  ((INSTANCE) == TIM3) || \
4627  ((INSTANCE) == TIM4) || \
4628  ((INSTANCE) == TIM5) || \
4629  ((INSTANCE) == TIM9))
4630 
4631 /************ TIM Instances : at least 3 capture/compare channels *************/
4632 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4633  ((INSTANCE) == TIM2) || \
4634  ((INSTANCE) == TIM3) || \
4635  ((INSTANCE) == TIM4) || \
4636  ((INSTANCE) == TIM5))
4637 
4638 /************ TIM Instances : at least 4 capture/compare channels *************/
4639 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4640  ((INSTANCE) == TIM2) || \
4641  ((INSTANCE) == TIM3) || \
4642  ((INSTANCE) == TIM4) || \
4643  ((INSTANCE) == TIM5))
4644 
4645 /******************** TIM Instances : Advanced-control timers *****************/
4646 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
4647 
4648 /******************* TIM Instances : Timer input XOR function *****************/
4649 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4650  ((INSTANCE) == TIM2) || \
4651  ((INSTANCE) == TIM3) || \
4652  ((INSTANCE) == TIM4) || \
4653  ((INSTANCE) == TIM5))
4654 
4655 /****************** TIM Instances : DMA requests generation (UDE) *************/
4656 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4657  ((INSTANCE) == TIM2) || \
4658  ((INSTANCE) == TIM3) || \
4659  ((INSTANCE) == TIM4) || \
4660  ((INSTANCE) == TIM5))
4661 
4662 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
4663 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4664  ((INSTANCE) == TIM2) || \
4665  ((INSTANCE) == TIM3) || \
4666  ((INSTANCE) == TIM4) || \
4667  ((INSTANCE) == TIM5))
4668 
4669 /************ TIM Instances : DMA requests generation (COMDE) *****************/
4670 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4671  ((INSTANCE) == TIM2) || \
4672  ((INSTANCE) == TIM3) || \
4673  ((INSTANCE) == TIM4) || \
4674  ((INSTANCE) == TIM5))
4675 
4676 /******************** TIM Instances : DMA burst feature ***********************/
4677 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4678  ((INSTANCE) == TIM2) || \
4679  ((INSTANCE) == TIM3) || \
4680  ((INSTANCE) == TIM4) || \
4681  ((INSTANCE) == TIM5))
4682 
4683 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
4684 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4685  ((INSTANCE) == TIM2) || \
4686  ((INSTANCE) == TIM3) || \
4687  ((INSTANCE) == TIM4) || \
4688  ((INSTANCE) == TIM5) || \
4689  ((INSTANCE) == TIM9))
4690 
4691 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
4692 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4693  ((INSTANCE) == TIM2) || \
4694  ((INSTANCE) == TIM3) || \
4695  ((INSTANCE) == TIM4) || \
4696  ((INSTANCE) == TIM5) || \
4697  ((INSTANCE) == TIM9))
4698 
4699 /********************** TIM Instances : 32 bit Counter ************************/
4700 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
4701  ((INSTANCE) == TIM5))
4702 
4703 /***************** TIM Instances : external trigger input availabe ************/
4704 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
4705  ((INSTANCE) == TIM2) || \
4706  ((INSTANCE) == TIM3) || \
4707  ((INSTANCE) == TIM4) || \
4708  ((INSTANCE) == TIM5))
4709 
4710 /****************** TIM Instances : remapping capability **********************/
4711 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
4712  ((INSTANCE) == TIM5) || \
4713  ((INSTANCE) == TIM11))
4714 
4715 /******************* TIM Instances : output(s) available **********************/
4716 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
4717  ((((INSTANCE) == TIM1) && \
4718  (((CHANNEL) == TIM_CHANNEL_1) || \
4719  ((CHANNEL) == TIM_CHANNEL_2) || \
4720  ((CHANNEL) == TIM_CHANNEL_3) || \
4721  ((CHANNEL) == TIM_CHANNEL_4))) \
4722  || \
4723  (((INSTANCE) == TIM2) && \
4724  (((CHANNEL) == TIM_CHANNEL_1) || \
4725  ((CHANNEL) == TIM_CHANNEL_2) || \
4726  ((CHANNEL) == TIM_CHANNEL_3) || \
4727  ((CHANNEL) == TIM_CHANNEL_4))) \
4728  || \
4729  (((INSTANCE) == TIM3) && \
4730  (((CHANNEL) == TIM_CHANNEL_1) || \
4731  ((CHANNEL) == TIM_CHANNEL_2) || \
4732  ((CHANNEL) == TIM_CHANNEL_3) || \
4733  ((CHANNEL) == TIM_CHANNEL_4))) \
4734  || \
4735  (((INSTANCE) == TIM4) && \
4736  (((CHANNEL) == TIM_CHANNEL_1) || \
4737  ((CHANNEL) == TIM_CHANNEL_2) || \
4738  ((CHANNEL) == TIM_CHANNEL_3) || \
4739  ((CHANNEL) == TIM_CHANNEL_4))) \
4740  || \
4741  (((INSTANCE) == TIM5) && \
4742  (((CHANNEL) == TIM_CHANNEL_1) || \
4743  ((CHANNEL) == TIM_CHANNEL_2) || \
4744  ((CHANNEL) == TIM_CHANNEL_3) || \
4745  ((CHANNEL) == TIM_CHANNEL_4))) \
4746  || \
4747  (((INSTANCE) == TIM9) && \
4748  (((CHANNEL) == TIM_CHANNEL_1) || \
4749  ((CHANNEL) == TIM_CHANNEL_2))) \
4750  || \
4751  (((INSTANCE) == TIM10) && \
4752  (((CHANNEL) == TIM_CHANNEL_1))) \
4753  || \
4754  (((INSTANCE) == TIM11) && \
4755  (((CHANNEL) == TIM_CHANNEL_1))))
4756 
4757 /************ TIM Instances : complementary output(s) available ***************/
4758 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
4759  ((((INSTANCE) == TIM1) && \
4760  (((CHANNEL) == TIM_CHANNEL_1) || \
4761  ((CHANNEL) == TIM_CHANNEL_2) || \
4762  ((CHANNEL) == TIM_CHANNEL_3))))
4763 
4764 /******************** USART Instances : Synchronous mode **********************/
4765 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4766  ((INSTANCE) == USART2) || \
4767  ((INSTANCE) == USART6))
4768 
4769 /******************** UART Instances : Asynchronous mode **********************/
4770 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4771  ((INSTANCE) == USART2) || \
4772  ((INSTANCE) == USART6))
4773 
4774 /****************** UART Instances : Hardware Flow control ********************/
4775 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4776  ((INSTANCE) == USART2) || \
4777  ((INSTANCE) == USART6))
4778 
4779 /********************* UART Instances : Smard card mode ***********************/
4780 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4781  ((INSTANCE) == USART2) || \
4782  ((INSTANCE) == USART6))
4783 
4784 /*********************** UART Instances : IRDA mode ***************************/
4785 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
4786  ((INSTANCE) == USART2) || \
4787  ((INSTANCE) == USART6))
4788 
4789 /*********************** PCD Instances ****************************************/
4790 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
4791 
4792 /*********************** HCD Instances ****************************************/
4793 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
4794 
4795 /****************************** IWDG Instances ********************************/
4796 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
4797 
4798 /****************************** WWDG Instances ********************************/
4799 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
4800 
4801 /****************************** SDIO Instances ********************************/
4802 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
4803 
4804 /****************************** USB Exported Constants ************************/
4805 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
4806 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
4807 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
4808 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
4809 
4822 #ifdef __cplusplus
4823 }
4824 #endif /* __cplusplus */
4825 
4826 #endif /* __STM32F411xE_H */
4827 
4828 
4829 
4830 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
TAMP_STAMP_IRQn
Definition: stm32f411xe.h:99
TIM2_IRQn
Definition: stm32f411xe.h:121
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f411xe.h:119
EXTI2_IRQn
Definition: stm32f411xe.h:105
EXTI4_IRQn
Definition: stm32f411xe.h:107
USART1_IRQn
Definition: stm32f411xe.h:130
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
TIM4_IRQn
Definition: stm32f411xe.h:123
RTC_Alarm_IRQn
Definition: stm32f411xe.h:133
PendSV_IRQn
Definition: stm32f411xe.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f411xe.h:100
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f411xe.h:128
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
OTG_FS_WKUP_IRQn
Definition: stm32f411xe.h:134
DMA_TypeDef
Definition: stm32f401xc.h:243
DMA1_Stream2_IRQn
Definition: stm32f411xe.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f411xe.h:129
__I
#define __I
Definition: core_cm0.h:210
DMA2_Stream5_IRQn
Definition: stm32f411xe.h:145
ADC_IRQn
Definition: stm32f411xe.h:115
RCC_IRQn
Definition: stm32f411xe.h:102
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f411xe.h:93
DMA2_Stream3_IRQn
Definition: stm32f411xe.h:142
NonMaskableInt_IRQn
Definition: stm32f411xe.h:88
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f411xe.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
DMA1_Stream1_IRQn
Definition: stm32f411xe.h:109
DMA2_Stream7_IRQn
Definition: stm32f411xe.h:147
DMA2_Stream6_IRQn
Definition: stm32f411xe.h:146
BusFault_IRQn
Definition: stm32f411xe.h:90
I2C3_ER_IRQn
Definition: stm32f411xe.h:150
USART6_IRQn
Definition: stm32f411xe.h:148
PVD_IRQn
Definition: stm32f411xe.h:98
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f411xe.h:112
DMA1_Stream0_IRQn
Definition: stm32f411xe.h:108
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f411xe.h:152
DMA1_Stream3_IRQn
Definition: stm32f411xe.h:111
FPU_IRQn
Definition: stm32f411xe.h:151
OTG_FS_IRQn
Definition: stm32f411xe.h:144
DMA2_Stream2_IRQn
Definition: stm32f411xe.h:141
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f411xe.h:136
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f411xe.h:149
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f411xe.h:131
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
I2C2_EV_IRQn
Definition: stm32f411xe.h:126
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f411xe.h:122
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f411xe.h:104
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f411xe.h:92
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f411xe.h:120
FLASH_IRQn
Definition: stm32f411xe.h:101
DMA1_Stream5_IRQn
Definition: stm32f411xe.h:113
SysTick_IRQn
Definition: stm32f411xe.h:95
TIM1_UP_TIM10_IRQn
Definition: stm32f411xe.h:118
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f411xe.h:127
UsageFault_IRQn
Definition: stm32f411xe.h:91
SPI3_IRQn
Definition: stm32f411xe.h:138
DMA2_Stream1_IRQn
Definition: stm32f411xe.h:140
EXTI9_5_IRQn
Definition: stm32f411xe.h:116
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f411xe.h:124
DMA1_Stream6_IRQn
Definition: stm32f411xe.h:114
I2C1_ER_IRQn
Definition: stm32f411xe.h:125
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
DMA2_Stream4_IRQn
Definition: stm32f411xe.h:143
WWDG_IRQn
Definition: stm32f411xe.h:97
DMA1_Stream7_IRQn
Definition: stm32f411xe.h:135
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
SPI5_IRQn
Definition: stm32f411xe.h:153
EXTI15_10_IRQn
Definition: stm32f411xe.h:132
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f411xe.h:103
DMA2_Stream0_IRQn
Definition: stm32f411xe.h:139
TIM1_BRK_TIM9_IRQn
Definition: stm32f411xe.h:117
TIM5_IRQn
Definition: stm32f411xe.h:137
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f411xe.h:106
MemoryManagement_IRQn
Definition: stm32f411xe.h:89