STM CMSIS
stm32f412cx.h
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1 
52 #ifndef __STM32F412Cx_H
53 #define __STM32F412Cx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  CAN1_TX_IRQn = 19,
117  CAN1_RX0_IRQn = 20,
118  CAN1_RX1_IRQn = 21,
119  CAN1_SCE_IRQn = 22,
120  EXTI9_5_IRQn = 23,
121  TIM1_BRK_TIM9_IRQn = 24,
122  TIM1_UP_TIM10_IRQn = 25,
123  TIM1_TRG_COM_TIM11_IRQn = 26,
124  TIM1_CC_IRQn = 27,
125  TIM2_IRQn = 28,
126  TIM3_IRQn = 29,
127  TIM4_IRQn = 30,
128  I2C1_EV_IRQn = 31,
129  I2C1_ER_IRQn = 32,
130  I2C2_EV_IRQn = 33,
131  I2C2_ER_IRQn = 34,
132  SPI1_IRQn = 35,
133  SPI2_IRQn = 36,
134  USART1_IRQn = 37,
135  USART2_IRQn = 38,
136  EXTI15_10_IRQn = 40,
137  RTC_Alarm_IRQn = 41,
138  OTG_FS_WKUP_IRQn = 42,
139  TIM8_BRK_TIM12_IRQn = 43,
140  TIM8_UP_TIM13_IRQn = 44,
141  TIM8_TRG_COM_TIM14_IRQn = 45,
142  TIM8_CC_IRQn = 46,
143  DMA1_Stream7_IRQn = 47,
144  SDIO_IRQn = 49,
145  TIM5_IRQn = 50,
146  SPI3_IRQn = 51,
147  TIM6_IRQn = 54,
148  TIM7_IRQn = 55,
149  DMA2_Stream0_IRQn = 56,
150  DMA2_Stream1_IRQn = 57,
151  DMA2_Stream2_IRQn = 58,
152  DMA2_Stream3_IRQn = 59,
153  DMA2_Stream4_IRQn = 60,
154  DFSDM1_FLT0_IRQn = 61,
155  DFSDM1_FLT1_IRQn = 62,
156  CAN2_TX_IRQn = 63,
157  CAN2_RX0_IRQn = 64,
158  CAN2_RX1_IRQn = 65,
159  CAN2_SCE_IRQn = 66,
160  OTG_FS_IRQn = 67,
161  DMA2_Stream5_IRQn = 68,
162  DMA2_Stream6_IRQn = 69,
163  DMA2_Stream7_IRQn = 70,
164  USART6_IRQn = 71,
165  I2C3_EV_IRQn = 72,
166  I2C3_ER_IRQn = 73,
167  RNG_IRQn = 80,
168  FPU_IRQn = 81,
169  SPI4_IRQn = 84,
170  SPI5_IRQn = 85,
171  FMPI2C1_EV_IRQn = 95,
172  FMPI2C1_ER_IRQn = 96
173 } IRQn_Type;
174 
179 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
180 #include "system_stm32f4xx.h"
181 #include <stdint.h>
182 
191 typedef struct
192 {
193  __IO uint32_t SR;
194  __IO uint32_t CR1;
195  __IO uint32_t CR2;
196  __IO uint32_t SMPR1;
197  __IO uint32_t SMPR2;
198  __IO uint32_t JOFR1;
199  __IO uint32_t JOFR2;
200  __IO uint32_t JOFR3;
201  __IO uint32_t JOFR4;
202  __IO uint32_t HTR;
203  __IO uint32_t LTR;
204  __IO uint32_t SQR1;
205  __IO uint32_t SQR2;
206  __IO uint32_t SQR3;
207  __IO uint32_t JSQR;
208  __IO uint32_t JDR1;
209  __IO uint32_t JDR2;
210  __IO uint32_t JDR3;
211  __IO uint32_t JDR4;
212  __IO uint32_t DR;
213 } ADC_TypeDef;
214 
215 typedef struct
216 {
217  __IO uint32_t CSR;
218  __IO uint32_t CCR;
219  __IO uint32_t CDR;
221 } ADC_Common_TypeDef;
222 
227 typedef struct
228 {
229  __IO uint32_t TIR;
230  __IO uint32_t TDTR;
231  __IO uint32_t TDLR;
232  __IO uint32_t TDHR;
233 } CAN_TxMailBox_TypeDef;
234 
239 typedef struct
240 {
241  __IO uint32_t RIR;
242  __IO uint32_t RDTR;
243  __IO uint32_t RDLR;
244  __IO uint32_t RDHR;
245 } CAN_FIFOMailBox_TypeDef;
246 
251 typedef struct
252 {
253  __IO uint32_t FR1;
254  __IO uint32_t FR2;
255 } CAN_FilterRegister_TypeDef;
256 
257 typedef struct
258 {
259  __IO uint32_t MCR;
260  __IO uint32_t MSR;
261  __IO uint32_t TSR;
262  __IO uint32_t RF0R;
263  __IO uint32_t RF1R;
264  __IO uint32_t IER;
265  __IO uint32_t ESR;
266  __IO uint32_t BTR;
267  uint32_t RESERVED0[88];
268  CAN_TxMailBox_TypeDef sTxMailBox[3];
269  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
270  uint32_t RESERVED1[12];
271  __IO uint32_t FMR;
272  __IO uint32_t FM1R;
273  uint32_t RESERVED2;
274  __IO uint32_t FS1R;
275  uint32_t RESERVED3;
276  __IO uint32_t FFA1R;
277  uint32_t RESERVED4;
278  __IO uint32_t FA1R;
279  uint32_t RESERVED5[8];
280  CAN_FilterRegister_TypeDef sFilterRegister[28];
281 } CAN_TypeDef;
282 
287 typedef struct
288 {
289  __IO uint32_t DR;
290  __IO uint8_t IDR;
291  uint8_t RESERVED0;
292  uint16_t RESERVED1;
293  __IO uint32_t CR;
294 }CRC_TypeDef;
295 
299 typedef struct
300 {
301  __IO uint32_t FLTCR1;
302  __IO uint32_t FLTCR2;
303  __IO uint32_t FLTISR;
304  __IO uint32_t FLTICR;
305  __IO uint32_t FLTJCHGR;
306  __IO uint32_t FLTFCR;
307  __IO uint32_t FLTJDATAR;
308  __IO uint32_t FLTRDATAR;
309  __IO uint32_t FLTAWHTR;
310  __IO uint32_t FLTAWLTR;
311  __IO uint32_t FLTAWSR;
312  __IO uint32_t FLTAWCFR;
313  __IO uint32_t FLTEXMAX;
314  __IO uint32_t FLTEXMIN;
315  __IO uint32_t FLTCNVTIMR;
316 } DFSDM_Filter_TypeDef;
317 
321 typedef struct
322 {
323  __IO uint32_t CHCFGR1;
324  __IO uint32_t CHCFGR2;
325  __IO uint32_t CHAWSCDR;
327  __IO uint32_t CHWDATAR;
328  __IO uint32_t CHDATINR;
329 } DFSDM_Channel_TypeDef;
330 
334 typedef struct
335 {
336  __IO uint32_t IDCODE;
337  __IO uint32_t CR;
338  __IO uint32_t APB1FZ;
339  __IO uint32_t APB2FZ;
340 }DBGMCU_TypeDef;
341 
342 
347 typedef struct
348 {
349  __IO uint32_t CR;
350  __IO uint32_t NDTR;
351  __IO uint32_t PAR;
352  __IO uint32_t M0AR;
353  __IO uint32_t M1AR;
354  __IO uint32_t FCR;
355 } DMA_Stream_TypeDef;
356 
357 typedef struct
358 {
359  __IO uint32_t LISR;
360  __IO uint32_t HISR;
361  __IO uint32_t LIFCR;
362  __IO uint32_t HIFCR;
363 } DMA_TypeDef;
364 
365 
370 typedef struct
371 {
372  __IO uint32_t IMR;
373  __IO uint32_t EMR;
374  __IO uint32_t RTSR;
375  __IO uint32_t FTSR;
376  __IO uint32_t SWIER;
377  __IO uint32_t PR;
378 } EXTI_TypeDef;
379 
384 typedef struct
385 {
386  __IO uint32_t ACR;
387  __IO uint32_t KEYR;
388  __IO uint32_t OPTKEYR;
389  __IO uint32_t SR;
390  __IO uint32_t CR;
391  __IO uint32_t OPTCR;
392  __IO uint32_t OPTCR1;
393 } FLASH_TypeDef;
394 
399 typedef struct
400 {
401  __IO uint32_t MODER;
402  __IO uint32_t OTYPER;
403  __IO uint32_t OSPEEDR;
404  __IO uint32_t PUPDR;
405  __IO uint32_t IDR;
406  __IO uint32_t ODR;
407  __IO uint32_t BSRR;
408  __IO uint32_t LCKR;
409  __IO uint32_t AFR[2];
410 } GPIO_TypeDef;
411 
415 typedef struct
416 {
417  __IO uint32_t MEMRMP;
418  __IO uint32_t PMC;
419  __IO uint32_t EXTICR[4];
420  uint32_t RESERVED[2];
421  __IO uint32_t CMPCR;
422  uint32_t RESERVED1[2];
423  __IO uint32_t CFGR;
424 } SYSCFG_TypeDef;
425 
430 typedef struct
431 {
432  __IO uint32_t CR1;
433  __IO uint32_t CR2;
434  __IO uint32_t OAR1;
435  __IO uint32_t OAR2;
436  __IO uint32_t DR;
437  __IO uint32_t SR1;
438  __IO uint32_t SR2;
439  __IO uint32_t CCR;
440  __IO uint32_t TRISE;
441  __IO uint32_t FLTR;
442 } I2C_TypeDef;
443 
448 typedef struct
449 {
450  __IO uint32_t CR1;
451  __IO uint32_t CR2;
452  __IO uint32_t OAR1;
453  __IO uint32_t OAR2;
454  __IO uint32_t TIMINGR;
455  __IO uint32_t TIMEOUTR;
456  __IO uint32_t ISR;
457  __IO uint32_t ICR;
458  __IO uint32_t PECR;
459  __IO uint32_t RXDR;
460  __IO uint32_t TXDR;
461 } FMPI2C_TypeDef;
462 
467 typedef struct
468 {
469  __IO uint32_t KR;
470  __IO uint32_t PR;
471  __IO uint32_t RLR;
472  __IO uint32_t SR;
473 } IWDG_TypeDef;
474 
479 typedef struct
480 {
481  __IO uint32_t CR;
482  __IO uint32_t CSR;
483 } PWR_TypeDef;
484 
489 typedef struct
490 {
491  __IO uint32_t CR;
492  __IO uint32_t PLLCFGR;
493  __IO uint32_t CFGR;
494  __IO uint32_t CIR;
495  __IO uint32_t AHB1RSTR;
496  __IO uint32_t AHB2RSTR;
497  uint32_t RESERVED0[2];
498  __IO uint32_t APB1RSTR;
499  __IO uint32_t APB2RSTR;
500  uint32_t RESERVED1[2];
501  __IO uint32_t AHB1ENR;
502  __IO uint32_t AHB2ENR;
503  uint32_t RESERVED2[2];
504  __IO uint32_t APB1ENR;
505  __IO uint32_t APB2ENR;
506  uint32_t RESERVED3[2];
507  __IO uint32_t AHB1LPENR;
508  __IO uint32_t AHB2LPENR;
509  uint32_t RESERVED4[2];
510  __IO uint32_t APB1LPENR;
511  __IO uint32_t APB2LPENR;
512  uint32_t RESERVED5[2];
513  __IO uint32_t BDCR;
514  __IO uint32_t CSR;
515  uint32_t RESERVED6[2];
516  __IO uint32_t SSCGR;
517  __IO uint32_t PLLI2SCFGR;
518  uint32_t RESERVED7;
519  __IO uint32_t DCKCFGR;
520  __IO uint32_t CKGATENR;
521  __IO uint32_t DCKCFGR2;
522 } RCC_TypeDef;
523 
528 typedef struct
529 {
530  __IO uint32_t TR;
531  __IO uint32_t DR;
532  __IO uint32_t CR;
533  __IO uint32_t ISR;
534  __IO uint32_t PRER;
535  __IO uint32_t WUTR;
536  __IO uint32_t CALIBR;
537  __IO uint32_t ALRMAR;
538  __IO uint32_t ALRMBR;
539  __IO uint32_t WPR;
540  __IO uint32_t SSR;
541  __IO uint32_t SHIFTR;
542  __IO uint32_t TSTR;
543  __IO uint32_t TSDR;
544  __IO uint32_t TSSSR;
545  __IO uint32_t CALR;
546  __IO uint32_t TAFCR;
547  __IO uint32_t ALRMASSR;
548  __IO uint32_t ALRMBSSR;
549  uint32_t RESERVED7;
550  __IO uint32_t BKP0R;
551  __IO uint32_t BKP1R;
552  __IO uint32_t BKP2R;
553  __IO uint32_t BKP3R;
554  __IO uint32_t BKP4R;
555  __IO uint32_t BKP5R;
556  __IO uint32_t BKP6R;
557  __IO uint32_t BKP7R;
558  __IO uint32_t BKP8R;
559  __IO uint32_t BKP9R;
560  __IO uint32_t BKP10R;
561  __IO uint32_t BKP11R;
562  __IO uint32_t BKP12R;
563  __IO uint32_t BKP13R;
564  __IO uint32_t BKP14R;
565  __IO uint32_t BKP15R;
566  __IO uint32_t BKP16R;
567  __IO uint32_t BKP17R;
568  __IO uint32_t BKP18R;
569  __IO uint32_t BKP19R;
570 } RTC_TypeDef;
571 
572 
577 typedef struct
578 {
579  __IO uint32_t POWER;
580  __IO uint32_t CLKCR;
581  __IO uint32_t ARG;
582  __IO uint32_t CMD;
583  __I uint32_t RESPCMD;
584  __I uint32_t RESP1;
585  __I uint32_t RESP2;
586  __I uint32_t RESP3;
587  __I uint32_t RESP4;
588  __IO uint32_t DTIMER;
589  __IO uint32_t DLEN;
590  __IO uint32_t DCTRL;
591  __I uint32_t DCOUNT;
592  __I uint32_t STA;
593  __IO uint32_t ICR;
594  __IO uint32_t MASK;
595  uint32_t RESERVED0[2];
596  __I uint32_t FIFOCNT;
597  uint32_t RESERVED1[13];
598  __IO uint32_t FIFO;
599 } SDIO_TypeDef;
600 
605 typedef struct
606 {
607  __IO uint32_t CR1;
608  __IO uint32_t CR2;
609  __IO uint32_t SR;
610  __IO uint32_t DR;
611  __IO uint32_t CRCPR;
612  __IO uint32_t RXCRCR;
613  __IO uint32_t TXCRCR;
614  __IO uint32_t I2SCFGR;
615  __IO uint32_t I2SPR;
616 } SPI_TypeDef;
617 
622 typedef struct
623 {
624  __IO uint32_t CR1;
625  __IO uint32_t CR2;
626  __IO uint32_t SMCR;
627  __IO uint32_t DIER;
628  __IO uint32_t SR;
629  __IO uint32_t EGR;
630  __IO uint32_t CCMR1;
631  __IO uint32_t CCMR2;
632  __IO uint32_t CCER;
633  __IO uint32_t CNT;
634  __IO uint32_t PSC;
635  __IO uint32_t ARR;
636  __IO uint32_t RCR;
637  __IO uint32_t CCR1;
638  __IO uint32_t CCR2;
639  __IO uint32_t CCR3;
640  __IO uint32_t CCR4;
641  __IO uint32_t BDTR;
642  __IO uint32_t DCR;
643  __IO uint32_t DMAR;
644  __IO uint32_t OR;
645 } TIM_TypeDef;
646 
651 typedef struct
652 {
653  __IO uint32_t SR;
654  __IO uint32_t DR;
655  __IO uint32_t BRR;
656  __IO uint32_t CR1;
657  __IO uint32_t CR2;
658  __IO uint32_t CR3;
659  __IO uint32_t GTPR;
660 } USART_TypeDef;
661 
666 typedef struct
667 {
668  __IO uint32_t CR;
669  __IO uint32_t CFR;
670  __IO uint32_t SR;
671 } WWDG_TypeDef;
672 
673 
678 typedef struct
679 {
680  __IO uint32_t CR;
681  __IO uint32_t SR;
682  __IO uint32_t DR;
683 } RNG_TypeDef;
684 
685 
689 typedef struct
690 {
691  __IO uint32_t GOTGCTL;
692  __IO uint32_t GOTGINT;
693  __IO uint32_t GAHBCFG;
694  __IO uint32_t GUSBCFG;
695  __IO uint32_t GRSTCTL;
696  __IO uint32_t GINTSTS;
697  __IO uint32_t GINTMSK;
698  __IO uint32_t GRXSTSR;
699  __IO uint32_t GRXSTSP;
700  __IO uint32_t GRXFSIZ;
701  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
702  __IO uint32_t HNPTXSTS;
703  uint32_t Reserved30[2];
704  __IO uint32_t GCCFG;
705  __IO uint32_t CID;
706  uint32_t Reserved5[3];
707  __IO uint32_t GHWCFG3;
708  uint32_t Reserved6;
709  __IO uint32_t GLPMCFG;
710  uint32_t Reserved;
711  __IO uint32_t GDFIFOCFG;
712  uint32_t Reserved43[40];
713  __IO uint32_t HPTXFSIZ;
714  __IO uint32_t DIEPTXF[0x0F];
715 } USB_OTG_GlobalTypeDef;
716 
717 
721 typedef struct
722 {
723  __IO uint32_t DCFG;
724  __IO uint32_t DCTL;
725  __IO uint32_t DSTS;
726  uint32_t Reserved0C;
727  __IO uint32_t DIEPMSK;
728  __IO uint32_t DOEPMSK;
729  __IO uint32_t DAINT;
730  __IO uint32_t DAINTMSK;
731  uint32_t Reserved20;
732  uint32_t Reserved9;
733  __IO uint32_t DVBUSDIS;
734  __IO uint32_t DVBUSPULSE;
735  __IO uint32_t DTHRCTL;
736  __IO uint32_t DIEPEMPMSK;
737  __IO uint32_t DEACHINT;
738  __IO uint32_t DEACHMSK;
739  uint32_t Reserved40;
740  __IO uint32_t DINEP1MSK;
741  uint32_t Reserved44[15];
742  __IO uint32_t DOUTEP1MSK;
743 } USB_OTG_DeviceTypeDef;
744 
745 
749 typedef struct
750 {
751  __IO uint32_t DIEPCTL;
752  uint32_t Reserved04;
753  __IO uint32_t DIEPINT;
754  uint32_t Reserved0C;
755  __IO uint32_t DIEPTSIZ;
756  __IO uint32_t DIEPDMA;
757  __IO uint32_t DTXFSTS;
758  uint32_t Reserved18;
759 } USB_OTG_INEndpointTypeDef;
760 
761 
765 typedef struct
766 {
767  __IO uint32_t DOEPCTL;
768  uint32_t Reserved04;
769  __IO uint32_t DOEPINT;
770  uint32_t Reserved0C;
771  __IO uint32_t DOEPTSIZ;
772  __IO uint32_t DOEPDMA;
773  uint32_t Reserved18[2];
774 } USB_OTG_OUTEndpointTypeDef;
775 
776 
780 typedef struct
781 {
782  __IO uint32_t HCFG;
783  __IO uint32_t HFIR;
784  __IO uint32_t HFNUM;
785  uint32_t Reserved40C;
786  __IO uint32_t HPTXSTS;
787  __IO uint32_t HAINT;
788  __IO uint32_t HAINTMSK;
789 } USB_OTG_HostTypeDef;
790 
791 
795 typedef struct
796 {
797  __IO uint32_t HCCHAR;
798  __IO uint32_t HCSPLT;
799  __IO uint32_t HCINT;
800  __IO uint32_t HCINTMSK;
801  __IO uint32_t HCTSIZ;
802  __IO uint32_t HCDMA;
803  uint32_t Reserved[2];
804 } USB_OTG_HostChannelTypeDef;
805 
806 
810 #define FLASH_BASE 0x08000000U
811 #define SRAM1_BASE 0x20000000U
812 #define PERIPH_BASE 0x40000000U
814 #define SRAM1_BB_BASE 0x22000000U
815 #define PERIPH_BB_BASE 0x42000000U
816 #define FLASH_END 0x080FFFFFU
818 /* Legacy defines */
819 #define SRAM_BASE SRAM1_BASE
820 #define SRAM_BB_BASE SRAM1_BB_BASE
821 
823 #define APB1PERIPH_BASE PERIPH_BASE
824 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
825 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
826 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
827 
829 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
830 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
831 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
832 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
833 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
834 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
835 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
836 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
837 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
838 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
839 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
840 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
841 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
842 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
843 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
844 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
845 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
846 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
847 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
848 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
849 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
850 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
851 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
852 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
853 
855 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
856 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
857 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
858 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
859 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
860 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
861 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
862 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
863 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
864 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
865 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
866 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
867 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
868 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
869 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
870 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
871 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
872 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
873 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
874 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
875 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
876 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
877 
879 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
880 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
881 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
882 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
883 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
884 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
885 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
886 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
887 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
888 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
889 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
890 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
891 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
892 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
893 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
894 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
895 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
896 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
897 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
898 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
899 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
900 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
901 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
902 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
903 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
904 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
905 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
906 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
907 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
908 
910 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
911 
912 /* Debug MCU registers base address */
913 #define DBGMCU_BASE 0xE0042000U
914 
916 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
917 
918 #define USB_OTG_GLOBAL_BASE 0x000U
919 #define USB_OTG_DEVICE_BASE 0x800U
920 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
921 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
922 #define USB_OTG_EP_REG_SIZE 0x20U
923 #define USB_OTG_HOST_BASE 0x400U
924 #define USB_OTG_HOST_PORT_BASE 0x440U
925 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
926 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
927 #define USB_OTG_PCGCCTL_BASE 0xE00U
928 #define USB_OTG_FIFO_BASE 0x1000U
929 #define USB_OTG_FIFO_SIZE 0x1000U
930 
938 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
939 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
940 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
941 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
942 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
943 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
944 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
945 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
946 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
947 #define RTC ((RTC_TypeDef *) RTC_BASE)
948 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
949 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
950 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
951 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
952 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
953 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
954 #define USART2 ((USART_TypeDef *) USART2_BASE)
955 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
956 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
957 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
958 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
959 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
960 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
961 #define PWR ((PWR_TypeDef *) PWR_BASE)
962 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
963 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
964 #define USART1 ((USART_TypeDef *) USART1_BASE)
965 #define USART6 ((USART_TypeDef *) USART6_BASE)
966 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
967 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
968 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
969 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
970 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
971 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
972 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
973 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
974 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
975 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
976 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
977 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
978 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
979 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
980 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
981 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
982 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
983 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
984 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
985 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
986 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
987 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
988 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
989 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
990 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
991 #define CRC ((CRC_TypeDef *) CRC_BASE)
992 #define RCC ((RCC_TypeDef *) RCC_BASE)
993 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
994 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
995 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
996 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
997 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
998 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
999 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1000 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1001 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1002 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1003 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1004 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1005 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1006 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1007 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1008 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1009 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1010 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1011 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1012 #define RNG ((RNG_TypeDef *) RNG_BASE)
1013 
1014 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1015 
1016 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1017 
1030 /******************************************************************************/
1031 /* Peripheral Registers_Bits_Definition */
1032 /******************************************************************************/
1033 
1034 /******************************************************************************/
1035 /* */
1036 /* Analog to Digital Converter */
1037 /* */
1038 /******************************************************************************/
1039 /******************** Bit definition for ADC_SR register ********************/
1040 #define ADC_SR_AWD 0x00000001U
1041 #define ADC_SR_EOC 0x00000002U
1042 #define ADC_SR_JEOC 0x00000004U
1043 #define ADC_SR_JSTRT 0x00000008U
1044 #define ADC_SR_STRT 0x00000010U
1045 #define ADC_SR_OVR 0x00000020U
1047 /******************* Bit definition for ADC_CR1 register ********************/
1048 #define ADC_CR1_AWDCH 0x0000001FU
1049 #define ADC_CR1_AWDCH_0 0x00000001U
1050 #define ADC_CR1_AWDCH_1 0x00000002U
1051 #define ADC_CR1_AWDCH_2 0x00000004U
1052 #define ADC_CR1_AWDCH_3 0x00000008U
1053 #define ADC_CR1_AWDCH_4 0x00000010U
1054 #define ADC_CR1_EOCIE 0x00000020U
1055 #define ADC_CR1_AWDIE 0x00000040U
1056 #define ADC_CR1_JEOCIE 0x00000080U
1057 #define ADC_CR1_SCAN 0x00000100U
1058 #define ADC_CR1_AWDSGL 0x00000200U
1059 #define ADC_CR1_JAUTO 0x00000400U
1060 #define ADC_CR1_DISCEN 0x00000800U
1061 #define ADC_CR1_JDISCEN 0x00001000U
1062 #define ADC_CR1_DISCNUM 0x0000E000U
1063 #define ADC_CR1_DISCNUM_0 0x00002000U
1064 #define ADC_CR1_DISCNUM_1 0x00004000U
1065 #define ADC_CR1_DISCNUM_2 0x00008000U
1066 #define ADC_CR1_JAWDEN 0x00400000U
1067 #define ADC_CR1_AWDEN 0x00800000U
1068 #define ADC_CR1_RES 0x03000000U
1069 #define ADC_CR1_RES_0 0x01000000U
1070 #define ADC_CR1_RES_1 0x02000000U
1071 #define ADC_CR1_OVRIE 0x04000000U
1073 /******************* Bit definition for ADC_CR2 register ********************/
1074 #define ADC_CR2_ADON 0x00000001U
1075 #define ADC_CR2_CONT 0x00000002U
1076 #define ADC_CR2_DMA 0x00000100U
1077 #define ADC_CR2_DDS 0x00000200U
1078 #define ADC_CR2_EOCS 0x00000400U
1079 #define ADC_CR2_ALIGN 0x00000800U
1080 #define ADC_CR2_JEXTSEL 0x000F0000U
1081 #define ADC_CR2_JEXTSEL_0 0x00010000U
1082 #define ADC_CR2_JEXTSEL_1 0x00020000U
1083 #define ADC_CR2_JEXTSEL_2 0x00040000U
1084 #define ADC_CR2_JEXTSEL_3 0x00080000U
1085 #define ADC_CR2_JEXTEN 0x00300000U
1086 #define ADC_CR2_JEXTEN_0 0x00100000U
1087 #define ADC_CR2_JEXTEN_1 0x00200000U
1088 #define ADC_CR2_JSWSTART 0x00400000U
1089 #define ADC_CR2_EXTSEL 0x0F000000U
1090 #define ADC_CR2_EXTSEL_0 0x01000000U
1091 #define ADC_CR2_EXTSEL_1 0x02000000U
1092 #define ADC_CR2_EXTSEL_2 0x04000000U
1093 #define ADC_CR2_EXTSEL_3 0x08000000U
1094 #define ADC_CR2_EXTEN 0x30000000U
1095 #define ADC_CR2_EXTEN_0 0x10000000U
1096 #define ADC_CR2_EXTEN_1 0x20000000U
1097 #define ADC_CR2_SWSTART 0x40000000U
1099 /****************** Bit definition for ADC_SMPR1 register *******************/
1100 #define ADC_SMPR1_SMP10 0x00000007U
1101 #define ADC_SMPR1_SMP10_0 0x00000001U
1102 #define ADC_SMPR1_SMP10_1 0x00000002U
1103 #define ADC_SMPR1_SMP10_2 0x00000004U
1104 #define ADC_SMPR1_SMP11 0x00000038U
1105 #define ADC_SMPR1_SMP11_0 0x00000008U
1106 #define ADC_SMPR1_SMP11_1 0x00000010U
1107 #define ADC_SMPR1_SMP11_2 0x00000020U
1108 #define ADC_SMPR1_SMP12 0x000001C0U
1109 #define ADC_SMPR1_SMP12_0 0x00000040U
1110 #define ADC_SMPR1_SMP12_1 0x00000080U
1111 #define ADC_SMPR1_SMP12_2 0x00000100U
1112 #define ADC_SMPR1_SMP13 0x00000E00U
1113 #define ADC_SMPR1_SMP13_0 0x00000200U
1114 #define ADC_SMPR1_SMP13_1 0x00000400U
1115 #define ADC_SMPR1_SMP13_2 0x00000800U
1116 #define ADC_SMPR1_SMP14 0x00007000U
1117 #define ADC_SMPR1_SMP14_0 0x00001000U
1118 #define ADC_SMPR1_SMP14_1 0x00002000U
1119 #define ADC_SMPR1_SMP14_2 0x00004000U
1120 #define ADC_SMPR1_SMP15 0x00038000U
1121 #define ADC_SMPR1_SMP15_0 0x00008000U
1122 #define ADC_SMPR1_SMP15_1 0x00010000U
1123 #define ADC_SMPR1_SMP15_2 0x00020000U
1124 #define ADC_SMPR1_SMP16 0x001C0000U
1125 #define ADC_SMPR1_SMP16_0 0x00040000U
1126 #define ADC_SMPR1_SMP16_1 0x00080000U
1127 #define ADC_SMPR1_SMP16_2 0x00100000U
1128 #define ADC_SMPR1_SMP17 0x00E00000U
1129 #define ADC_SMPR1_SMP17_0 0x00200000U
1130 #define ADC_SMPR1_SMP17_1 0x00400000U
1131 #define ADC_SMPR1_SMP17_2 0x00800000U
1132 #define ADC_SMPR1_SMP18 0x07000000U
1133 #define ADC_SMPR1_SMP18_0 0x01000000U
1134 #define ADC_SMPR1_SMP18_1 0x02000000U
1135 #define ADC_SMPR1_SMP18_2 0x04000000U
1137 /****************** Bit definition for ADC_SMPR2 register *******************/
1138 #define ADC_SMPR2_SMP0 0x00000007U
1139 #define ADC_SMPR2_SMP0_0 0x00000001U
1140 #define ADC_SMPR2_SMP0_1 0x00000002U
1141 #define ADC_SMPR2_SMP0_2 0x00000004U
1142 #define ADC_SMPR2_SMP1 0x00000038U
1143 #define ADC_SMPR2_SMP1_0 0x00000008U
1144 #define ADC_SMPR2_SMP1_1 0x00000010U
1145 #define ADC_SMPR2_SMP1_2 0x00000020U
1146 #define ADC_SMPR2_SMP2 0x000001C0U
1147 #define ADC_SMPR2_SMP2_0 0x00000040U
1148 #define ADC_SMPR2_SMP2_1 0x00000080U
1149 #define ADC_SMPR2_SMP2_2 0x00000100U
1150 #define ADC_SMPR2_SMP3 0x00000E00U
1151 #define ADC_SMPR2_SMP3_0 0x00000200U
1152 #define ADC_SMPR2_SMP3_1 0x00000400U
1153 #define ADC_SMPR2_SMP3_2 0x00000800U
1154 #define ADC_SMPR2_SMP4 0x00007000U
1155 #define ADC_SMPR2_SMP4_0 0x00001000U
1156 #define ADC_SMPR2_SMP4_1 0x00002000U
1157 #define ADC_SMPR2_SMP4_2 0x00004000U
1158 #define ADC_SMPR2_SMP5 0x00038000U
1159 #define ADC_SMPR2_SMP5_0 0x00008000U
1160 #define ADC_SMPR2_SMP5_1 0x00010000U
1161 #define ADC_SMPR2_SMP5_2 0x00020000U
1162 #define ADC_SMPR2_SMP6 0x001C0000U
1163 #define ADC_SMPR2_SMP6_0 0x00040000U
1164 #define ADC_SMPR2_SMP6_1 0x00080000U
1165 #define ADC_SMPR2_SMP6_2 0x00100000U
1166 #define ADC_SMPR2_SMP7 0x00E00000U
1167 #define ADC_SMPR2_SMP7_0 0x00200000U
1168 #define ADC_SMPR2_SMP7_1 0x00400000U
1169 #define ADC_SMPR2_SMP7_2 0x00800000U
1170 #define ADC_SMPR2_SMP8 0x07000000U
1171 #define ADC_SMPR2_SMP8_0 0x01000000U
1172 #define ADC_SMPR2_SMP8_1 0x02000000U
1173 #define ADC_SMPR2_SMP8_2 0x04000000U
1174 #define ADC_SMPR2_SMP9 0x38000000U
1175 #define ADC_SMPR2_SMP9_0 0x08000000U
1176 #define ADC_SMPR2_SMP9_1 0x10000000U
1177 #define ADC_SMPR2_SMP9_2 0x20000000U
1179 /****************** Bit definition for ADC_JOFR1 register *******************/
1180 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1182 /****************** Bit definition for ADC_JOFR2 register *******************/
1183 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1185 /****************** Bit definition for ADC_JOFR3 register *******************/
1186 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1188 /****************** Bit definition for ADC_JOFR4 register *******************/
1189 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1191 /******************* Bit definition for ADC_HTR register ********************/
1192 #define ADC_HTR_HT 0x0FFFU
1194 /******************* Bit definition for ADC_LTR register ********************/
1195 #define ADC_LTR_LT 0x0FFFU
1197 /******************* Bit definition for ADC_SQR1 register *******************/
1198 #define ADC_SQR1_SQ13 0x0000001FU
1199 #define ADC_SQR1_SQ13_0 0x00000001U
1200 #define ADC_SQR1_SQ13_1 0x00000002U
1201 #define ADC_SQR1_SQ13_2 0x00000004U
1202 #define ADC_SQR1_SQ13_3 0x00000008U
1203 #define ADC_SQR1_SQ13_4 0x00000010U
1204 #define ADC_SQR1_SQ14 0x000003E0U
1205 #define ADC_SQR1_SQ14_0 0x00000020U
1206 #define ADC_SQR1_SQ14_1 0x00000040U
1207 #define ADC_SQR1_SQ14_2 0x00000080U
1208 #define ADC_SQR1_SQ14_3 0x00000100U
1209 #define ADC_SQR1_SQ14_4 0x00000200U
1210 #define ADC_SQR1_SQ15 0x00007C00U
1211 #define ADC_SQR1_SQ15_0 0x00000400U
1212 #define ADC_SQR1_SQ15_1 0x00000800U
1213 #define ADC_SQR1_SQ15_2 0x00001000U
1214 #define ADC_SQR1_SQ15_3 0x00002000U
1215 #define ADC_SQR1_SQ15_4 0x00004000U
1216 #define ADC_SQR1_SQ16 0x000F8000U
1217 #define ADC_SQR1_SQ16_0 0x00008000U
1218 #define ADC_SQR1_SQ16_1 0x00010000U
1219 #define ADC_SQR1_SQ16_2 0x00020000U
1220 #define ADC_SQR1_SQ16_3 0x00040000U
1221 #define ADC_SQR1_SQ16_4 0x00080000U
1222 #define ADC_SQR1_L 0x00F00000U
1223 #define ADC_SQR1_L_0 0x00100000U
1224 #define ADC_SQR1_L_1 0x00200000U
1225 #define ADC_SQR1_L_2 0x00400000U
1226 #define ADC_SQR1_L_3 0x00800000U
1228 /******************* Bit definition for ADC_SQR2 register *******************/
1229 #define ADC_SQR2_SQ7 0x0000001FU
1230 #define ADC_SQR2_SQ7_0 0x00000001U
1231 #define ADC_SQR2_SQ7_1 0x00000002U
1232 #define ADC_SQR2_SQ7_2 0x00000004U
1233 #define ADC_SQR2_SQ7_3 0x00000008U
1234 #define ADC_SQR2_SQ7_4 0x00000010U
1235 #define ADC_SQR2_SQ8 0x000003E0U
1236 #define ADC_SQR2_SQ8_0 0x00000020U
1237 #define ADC_SQR2_SQ8_1 0x00000040U
1238 #define ADC_SQR2_SQ8_2 0x00000080U
1239 #define ADC_SQR2_SQ8_3 0x00000100U
1240 #define ADC_SQR2_SQ8_4 0x00000200U
1241 #define ADC_SQR2_SQ9 0x00007C00U
1242 #define ADC_SQR2_SQ9_0 0x00000400U
1243 #define ADC_SQR2_SQ9_1 0x00000800U
1244 #define ADC_SQR2_SQ9_2 0x00001000U
1245 #define ADC_SQR2_SQ9_3 0x00002000U
1246 #define ADC_SQR2_SQ9_4 0x00004000U
1247 #define ADC_SQR2_SQ10 0x000F8000U
1248 #define ADC_SQR2_SQ10_0 0x00008000U
1249 #define ADC_SQR2_SQ10_1 0x00010000U
1250 #define ADC_SQR2_SQ10_2 0x00020000U
1251 #define ADC_SQR2_SQ10_3 0x00040000U
1252 #define ADC_SQR2_SQ10_4 0x00080000U
1253 #define ADC_SQR2_SQ11 0x01F00000U
1254 #define ADC_SQR2_SQ11_0 0x00100000U
1255 #define ADC_SQR2_SQ11_1 0x00200000U
1256 #define ADC_SQR2_SQ11_2 0x00400000U
1257 #define ADC_SQR2_SQ11_3 0x00800000U
1258 #define ADC_SQR2_SQ11_4 0x01000000U
1259 #define ADC_SQR2_SQ12 0x3E000000U
1260 #define ADC_SQR2_SQ12_0 0x02000000U
1261 #define ADC_SQR2_SQ12_1 0x04000000U
1262 #define ADC_SQR2_SQ12_2 0x08000000U
1263 #define ADC_SQR2_SQ12_3 0x10000000U
1264 #define ADC_SQR2_SQ12_4 0x20000000U
1266 /******************* Bit definition for ADC_SQR3 register *******************/
1267 #define ADC_SQR3_SQ1 0x0000001FU
1268 #define ADC_SQR3_SQ1_0 0x00000001U
1269 #define ADC_SQR3_SQ1_1 0x00000002U
1270 #define ADC_SQR3_SQ1_2 0x00000004U
1271 #define ADC_SQR3_SQ1_3 0x00000008U
1272 #define ADC_SQR3_SQ1_4 0x00000010U
1273 #define ADC_SQR3_SQ2 0x000003E0U
1274 #define ADC_SQR3_SQ2_0 0x00000020U
1275 #define ADC_SQR3_SQ2_1 0x00000040U
1276 #define ADC_SQR3_SQ2_2 0x00000080U
1277 #define ADC_SQR3_SQ2_3 0x00000100U
1278 #define ADC_SQR3_SQ2_4 0x00000200U
1279 #define ADC_SQR3_SQ3 0x00007C00U
1280 #define ADC_SQR3_SQ3_0 0x00000400U
1281 #define ADC_SQR3_SQ3_1 0x00000800U
1282 #define ADC_SQR3_SQ3_2 0x00001000U
1283 #define ADC_SQR3_SQ3_3 0x00002000U
1284 #define ADC_SQR3_SQ3_4 0x00004000U
1285 #define ADC_SQR3_SQ4 0x000F8000U
1286 #define ADC_SQR3_SQ4_0 0x00008000U
1287 #define ADC_SQR3_SQ4_1 0x00010000U
1288 #define ADC_SQR3_SQ4_2 0x00020000U
1289 #define ADC_SQR3_SQ4_3 0x00040000U
1290 #define ADC_SQR3_SQ4_4 0x00080000U
1291 #define ADC_SQR3_SQ5 0x01F00000U
1292 #define ADC_SQR3_SQ5_0 0x00100000U
1293 #define ADC_SQR3_SQ5_1 0x00200000U
1294 #define ADC_SQR3_SQ5_2 0x00400000U
1295 #define ADC_SQR3_SQ5_3 0x00800000U
1296 #define ADC_SQR3_SQ5_4 0x01000000U
1297 #define ADC_SQR3_SQ6 0x3E000000U
1298 #define ADC_SQR3_SQ6_0 0x02000000U
1299 #define ADC_SQR3_SQ6_1 0x04000000U
1300 #define ADC_SQR3_SQ6_2 0x08000000U
1301 #define ADC_SQR3_SQ6_3 0x10000000U
1302 #define ADC_SQR3_SQ6_4 0x20000000U
1304 /******************* Bit definition for ADC_JSQR register *******************/
1305 #define ADC_JSQR_JSQ1 0x0000001FU
1306 #define ADC_JSQR_JSQ1_0 0x00000001U
1307 #define ADC_JSQR_JSQ1_1 0x00000002U
1308 #define ADC_JSQR_JSQ1_2 0x00000004U
1309 #define ADC_JSQR_JSQ1_3 0x00000008U
1310 #define ADC_JSQR_JSQ1_4 0x00000010U
1311 #define ADC_JSQR_JSQ2 0x000003E0U
1312 #define ADC_JSQR_JSQ2_0 0x00000020U
1313 #define ADC_JSQR_JSQ2_1 0x00000040U
1314 #define ADC_JSQR_JSQ2_2 0x00000080U
1315 #define ADC_JSQR_JSQ2_3 0x00000100U
1316 #define ADC_JSQR_JSQ2_4 0x00000200U
1317 #define ADC_JSQR_JSQ3 0x00007C00U
1318 #define ADC_JSQR_JSQ3_0 0x00000400U
1319 #define ADC_JSQR_JSQ3_1 0x00000800U
1320 #define ADC_JSQR_JSQ3_2 0x00001000U
1321 #define ADC_JSQR_JSQ3_3 0x00002000U
1322 #define ADC_JSQR_JSQ3_4 0x00004000U
1323 #define ADC_JSQR_JSQ4 0x000F8000U
1324 #define ADC_JSQR_JSQ4_0 0x00008000U
1325 #define ADC_JSQR_JSQ4_1 0x00010000U
1326 #define ADC_JSQR_JSQ4_2 0x00020000U
1327 #define ADC_JSQR_JSQ4_3 0x00040000U
1328 #define ADC_JSQR_JSQ4_4 0x00080000U
1329 #define ADC_JSQR_JL 0x00300000U
1330 #define ADC_JSQR_JL_0 0x00100000U
1331 #define ADC_JSQR_JL_1 0x00200000U
1333 /******************* Bit definition for ADC_JDR1 register *******************/
1334 #define ADC_JDR1_JDATA 0xFFFFU
1336 /******************* Bit definition for ADC_JDR2 register *******************/
1337 #define ADC_JDR2_JDATA 0xFFFFU
1339 /******************* Bit definition for ADC_JDR3 register *******************/
1340 #define ADC_JDR3_JDATA 0xFFFFU
1342 /******************* Bit definition for ADC_JDR4 register *******************/
1343 #define ADC_JDR4_JDATA 0xFFFFU
1345 /******************** Bit definition for ADC_DR register ********************/
1346 #define ADC_DR_DATA 0x0000FFFFU
1347 #define ADC_DR_ADC2DATA 0xFFFF0000U
1349 /******************* Bit definition for ADC_CSR register ********************/
1350 #define ADC_CSR_AWD1 0x00000001U
1351 #define ADC_CSR_EOC1 0x00000002U
1352 #define ADC_CSR_JEOC1 0x00000004U
1353 #define ADC_CSR_JSTRT1 0x00000008U
1354 #define ADC_CSR_STRT1 0x00000010U
1355 #define ADC_CSR_DOVR1 0x00000020U
1356 #define ADC_CSR_AWD2 0x00000100U
1357 #define ADC_CSR_EOC2 0x00000200U
1358 #define ADC_CSR_JEOC2 0x00000400U
1359 #define ADC_CSR_JSTRT2 0x00000800U
1360 #define ADC_CSR_STRT2 0x00001000U
1361 #define ADC_CSR_DOVR2 0x00002000U
1363 /******************* Bit definition for ADC_CCR register ********************/
1364 #define ADC_CCR_MULTI 0x0000001FU
1365 #define ADC_CCR_MULTI_0 0x00000001U
1366 #define ADC_CCR_MULTI_1 0x00000002U
1367 #define ADC_CCR_MULTI_2 0x00000004U
1368 #define ADC_CCR_MULTI_3 0x00000008U
1369 #define ADC_CCR_MULTI_4 0x00000010U
1370 #define ADC_CCR_DELAY 0x00000F00U
1371 #define ADC_CCR_DELAY_0 0x00000100U
1372 #define ADC_CCR_DELAY_1 0x00000200U
1373 #define ADC_CCR_DELAY_2 0x00000400U
1374 #define ADC_CCR_DELAY_3 0x00000800U
1375 #define ADC_CCR_DDS 0x00002000U
1376 #define ADC_CCR_DMA 0x0000C000U
1377 #define ADC_CCR_DMA_0 0x00004000U
1378 #define ADC_CCR_DMA_1 0x00008000U
1379 #define ADC_CCR_ADCPRE 0x00030000U
1380 #define ADC_CCR_ADCPRE_0 0x00010000U
1381 #define ADC_CCR_ADCPRE_1 0x00020000U
1382 #define ADC_CCR_VBATE 0x00400000U
1383 #define ADC_CCR_TSVREFE 0x00800000U
1385 /******************* Bit definition for ADC_CDR register ********************/
1386 #define ADC_CDR_DATA1 0x0000FFFFU
1387 #define ADC_CDR_DATA2 0xFFFF0000U
1389 /******************************************************************************/
1390 /* */
1391 /* Controller Area Network */
1392 /* */
1393 /******************************************************************************/
1395 /******************* Bit definition for CAN_MCR register ********************/
1396 #define CAN_MCR_INRQ 0x00000001U
1397 #define CAN_MCR_SLEEP 0x00000002U
1398 #define CAN_MCR_TXFP 0x00000004U
1399 #define CAN_MCR_RFLM 0x00000008U
1400 #define CAN_MCR_NART 0x00000010U
1401 #define CAN_MCR_AWUM 0x00000020U
1402 #define CAN_MCR_ABOM 0x00000040U
1403 #define CAN_MCR_TTCM 0x00000080U
1404 #define CAN_MCR_RESET 0x00008000U
1405 #define CAN_MCR_DBF 0x00010000U
1406 /******************* Bit definition for CAN_MSR register ********************/
1407 #define CAN_MSR_INAK 0x0001U
1408 #define CAN_MSR_SLAK 0x0002U
1409 #define CAN_MSR_ERRI 0x0004U
1410 #define CAN_MSR_WKUI 0x0008U
1411 #define CAN_MSR_SLAKI 0x0010U
1412 #define CAN_MSR_TXM 0x0100U
1413 #define CAN_MSR_RXM 0x0200U
1414 #define CAN_MSR_SAMP 0x0400U
1415 #define CAN_MSR_RX 0x0800U
1417 /******************* Bit definition for CAN_TSR register ********************/
1418 #define CAN_TSR_RQCP0 0x00000001U
1419 #define CAN_TSR_TXOK0 0x00000002U
1420 #define CAN_TSR_ALST0 0x00000004U
1421 #define CAN_TSR_TERR0 0x00000008U
1422 #define CAN_TSR_ABRQ0 0x00000080U
1423 #define CAN_TSR_RQCP1 0x00000100U
1424 #define CAN_TSR_TXOK1 0x00000200U
1425 #define CAN_TSR_ALST1 0x00000400U
1426 #define CAN_TSR_TERR1 0x00000800U
1427 #define CAN_TSR_ABRQ1 0x00008000U
1428 #define CAN_TSR_RQCP2 0x00010000U
1429 #define CAN_TSR_TXOK2 0x00020000U
1430 #define CAN_TSR_ALST2 0x00040000U
1431 #define CAN_TSR_TERR2 0x00080000U
1432 #define CAN_TSR_ABRQ2 0x00800000U
1433 #define CAN_TSR_CODE 0x03000000U
1435 #define CAN_TSR_TME 0x1C000000U
1436 #define CAN_TSR_TME0 0x04000000U
1437 #define CAN_TSR_TME1 0x08000000U
1438 #define CAN_TSR_TME2 0x10000000U
1440 #define CAN_TSR_LOW 0xE0000000U
1441 #define CAN_TSR_LOW0 0x20000000U
1442 #define CAN_TSR_LOW1 0x40000000U
1443 #define CAN_TSR_LOW2 0x80000000U
1445 /******************* Bit definition for CAN_RF0R register *******************/
1446 #define CAN_RF0R_FMP0 0x03U
1447 #define CAN_RF0R_FULL0 0x08U
1448 #define CAN_RF0R_FOVR0 0x10U
1449 #define CAN_RF0R_RFOM0 0x20U
1451 /******************* Bit definition for CAN_RF1R register *******************/
1452 #define CAN_RF1R_FMP1 0x03U
1453 #define CAN_RF1R_FULL1 0x08U
1454 #define CAN_RF1R_FOVR1 0x10U
1455 #define CAN_RF1R_RFOM1 0x20U
1457 /******************** Bit definition for CAN_IER register *******************/
1458 #define CAN_IER_TMEIE 0x00000001U
1459 #define CAN_IER_FMPIE0 0x00000002U
1460 #define CAN_IER_FFIE0 0x00000004U
1461 #define CAN_IER_FOVIE0 0x00000008U
1462 #define CAN_IER_FMPIE1 0x00000010U
1463 #define CAN_IER_FFIE1 0x00000020U
1464 #define CAN_IER_FOVIE1 0x00000040U
1465 #define CAN_IER_EWGIE 0x00000100U
1466 #define CAN_IER_EPVIE 0x00000200U
1467 #define CAN_IER_BOFIE 0x00000400U
1468 #define CAN_IER_LECIE 0x00000800U
1469 #define CAN_IER_ERRIE 0x00008000U
1470 #define CAN_IER_WKUIE 0x00010000U
1471 #define CAN_IER_SLKIE 0x00020000U
1472 #define CAN_IER_EWGIE 0x00000100U
1473 #define CAN_IER_EPVIE 0x00000200U
1474 #define CAN_IER_BOFIE 0x00000400U
1475 #define CAN_IER_LECIE 0x00000800U
1476 #define CAN_IER_ERRIE 0x00008000U
1479 /******************** Bit definition for CAN_ESR register *******************/
1480 #define CAN_ESR_EWGF 0x00000001U
1481 #define CAN_ESR_EPVF 0x00000002U
1482 #define CAN_ESR_BOFF 0x00000004U
1484 #define CAN_ESR_LEC 0x00000070U
1485 #define CAN_ESR_LEC_0 0x00000010U
1486 #define CAN_ESR_LEC_1 0x00000020U
1487 #define CAN_ESR_LEC_2 0x00000040U
1489 #define CAN_ESR_TEC 0x00FF0000U
1490 #define CAN_ESR_REC 0xFF000000U
1492 /******************* Bit definition for CAN_BTR register ********************/
1493 #define CAN_BTR_BRP 0x000003FFU
1494 #define CAN_BTR_TS1 0x000F0000U
1495 #define CAN_BTR_TS1_0 0x00010000U
1496 #define CAN_BTR_TS1_1 0x00020000U
1497 #define CAN_BTR_TS1_2 0x00040000U
1498 #define CAN_BTR_TS1_3 0x00080000U
1499 #define CAN_BTR_TS2 0x00700000U
1500 #define CAN_BTR_TS2_0 0x00100000U
1501 #define CAN_BTR_TS2_1 0x00200000U
1502 #define CAN_BTR_TS2_2 0x00400000U
1503 #define CAN_BTR_SJW 0x03000000U
1504 #define CAN_BTR_SJW_0 0x01000000U
1505 #define CAN_BTR_SJW_1 0x02000000U
1506 #define CAN_BTR_LBKM 0x40000000U
1507 #define CAN_BTR_SILM 0x80000000U
1511 /****************** Bit definition for CAN_TI0R register ********************/
1512 #define CAN_TI0R_TXRQ 0x00000001U
1513 #define CAN_TI0R_RTR 0x00000002U
1514 #define CAN_TI0R_IDE 0x00000004U
1515 #define CAN_TI0R_EXID 0x001FFFF8U
1516 #define CAN_TI0R_STID 0xFFE00000U
1518 /****************** Bit definition for CAN_TDT0R register *******************/
1519 #define CAN_TDT0R_DLC 0x0000000FU
1520 #define CAN_TDT0R_TGT 0x00000100U
1521 #define CAN_TDT0R_TIME 0xFFFF0000U
1523 /****************** Bit definition for CAN_TDL0R register *******************/
1524 #define CAN_TDL0R_DATA0 0x000000FFU
1525 #define CAN_TDL0R_DATA1 0x0000FF00U
1526 #define CAN_TDL0R_DATA2 0x00FF0000U
1527 #define CAN_TDL0R_DATA3 0xFF000000U
1529 /****************** Bit definition for CAN_TDH0R register *******************/
1530 #define CAN_TDH0R_DATA4 0x000000FFU
1531 #define CAN_TDH0R_DATA5 0x0000FF00U
1532 #define CAN_TDH0R_DATA6 0x00FF0000U
1533 #define CAN_TDH0R_DATA7 0xFF000000U
1535 /******************* Bit definition for CAN_TI1R register *******************/
1536 #define CAN_TI1R_TXRQ 0x00000001U
1537 #define CAN_TI1R_RTR 0x00000002U
1538 #define CAN_TI1R_IDE 0x00000004U
1539 #define CAN_TI1R_EXID 0x001FFFF8U
1540 #define CAN_TI1R_STID 0xFFE00000U
1542 /******************* Bit definition for CAN_TDT1R register ******************/
1543 #define CAN_TDT1R_DLC 0x0000000FU
1544 #define CAN_TDT1R_TGT 0x00000100U
1545 #define CAN_TDT1R_TIME 0xFFFF0000U
1547 /******************* Bit definition for CAN_TDL1R register ******************/
1548 #define CAN_TDL1R_DATA0 0x000000FFU
1549 #define CAN_TDL1R_DATA1 0x0000FF00U
1550 #define CAN_TDL1R_DATA2 0x00FF0000U
1551 #define CAN_TDL1R_DATA3 0xFF000000U
1553 /******************* Bit definition for CAN_TDH1R register ******************/
1554 #define CAN_TDH1R_DATA4 0x000000FFU
1555 #define CAN_TDH1R_DATA5 0x0000FF00U
1556 #define CAN_TDH1R_DATA6 0x00FF0000U
1557 #define CAN_TDH1R_DATA7 0xFF000000U
1559 /******************* Bit definition for CAN_TI2R register *******************/
1560 #define CAN_TI2R_TXRQ 0x00000001U
1561 #define CAN_TI2R_RTR 0x00000002U
1562 #define CAN_TI2R_IDE 0x00000004U
1563 #define CAN_TI2R_EXID 0x001FFFF8U
1564 #define CAN_TI2R_STID 0xFFE00000U
1566 /******************* Bit definition for CAN_TDT2R register ******************/
1567 #define CAN_TDT2R_DLC 0x0000000FU
1568 #define CAN_TDT2R_TGT 0x00000100U
1569 #define CAN_TDT2R_TIME 0xFFFF0000U
1571 /******************* Bit definition for CAN_TDL2R register ******************/
1572 #define CAN_TDL2R_DATA0 0x000000FFU
1573 #define CAN_TDL2R_DATA1 0x0000FF00U
1574 #define CAN_TDL2R_DATA2 0x00FF0000U
1575 #define CAN_TDL2R_DATA3 0xFF000000U
1577 /******************* Bit definition for CAN_TDH2R register ******************/
1578 #define CAN_TDH2R_DATA4 0x000000FFU
1579 #define CAN_TDH2R_DATA5 0x0000FF00U
1580 #define CAN_TDH2R_DATA6 0x00FF0000U
1581 #define CAN_TDH2R_DATA7 0xFF000000U
1583 /******************* Bit definition for CAN_RI0R register *******************/
1584 #define CAN_RI0R_RTR 0x00000002U
1585 #define CAN_RI0R_IDE 0x00000004U
1586 #define CAN_RI0R_EXID 0x001FFFF8U
1587 #define CAN_RI0R_STID 0xFFE00000U
1589 /******************* Bit definition for CAN_RDT0R register ******************/
1590 #define CAN_RDT0R_DLC 0x0000000FU
1591 #define CAN_RDT0R_FMI 0x0000FF00U
1592 #define CAN_RDT0R_TIME 0xFFFF0000U
1594 /******************* Bit definition for CAN_RDL0R register ******************/
1595 #define CAN_RDL0R_DATA0 0x000000FFU
1596 #define CAN_RDL0R_DATA1 0x0000FF00U
1597 #define CAN_RDL0R_DATA2 0x00FF0000U
1598 #define CAN_RDL0R_DATA3 0xFF000000U
1600 /******************* Bit definition for CAN_RDH0R register ******************/
1601 #define CAN_RDH0R_DATA4 0x000000FFU
1602 #define CAN_RDH0R_DATA5 0x0000FF00U
1603 #define CAN_RDH0R_DATA6 0x00FF0000U
1604 #define CAN_RDH0R_DATA7 0xFF000000U
1606 /******************* Bit definition for CAN_RI1R register *******************/
1607 #define CAN_RI1R_RTR 0x00000002U
1608 #define CAN_RI1R_IDE 0x00000004U
1609 #define CAN_RI1R_EXID 0x001FFFF8U
1610 #define CAN_RI1R_STID 0xFFE00000U
1612 /******************* Bit definition for CAN_RDT1R register ******************/
1613 #define CAN_RDT1R_DLC 0x0000000FU
1614 #define CAN_RDT1R_FMI 0x0000FF00U
1615 #define CAN_RDT1R_TIME 0xFFFF0000U
1617 /******************* Bit definition for CAN_RDL1R register ******************/
1618 #define CAN_RDL1R_DATA0 0x000000FFU
1619 #define CAN_RDL1R_DATA1 0x0000FF00U
1620 #define CAN_RDL1R_DATA2 0x00FF0000U
1621 #define CAN_RDL1R_DATA3 0xFF000000U
1623 /******************* Bit definition for CAN_RDH1R register ******************/
1624 #define CAN_RDH1R_DATA4 0x000000FFU
1625 #define CAN_RDH1R_DATA5 0x0000FF00U
1626 #define CAN_RDH1R_DATA6 0x00FF0000U
1627 #define CAN_RDH1R_DATA7 0xFF000000U
1630 /******************* Bit definition for CAN_FMR register ********************/
1631 #define CAN_FMR_FINIT 0x01U
1632 #define CAN_FMR_CAN2SB 0x00003F00U
1634 /******************* Bit definition for CAN_FM1R register *******************/
1635 #define CAN_FM1R_FBM 0x0FFFFFFFU
1636 #define CAN_FM1R_FBM0 0x00000001U
1637 #define CAN_FM1R_FBM1 0x00000002U
1638 #define CAN_FM1R_FBM2 0x00000004U
1639 #define CAN_FM1R_FBM3 0x00000008U
1640 #define CAN_FM1R_FBM4 0x00000010U
1641 #define CAN_FM1R_FBM5 0x00000020U
1642 #define CAN_FM1R_FBM6 0x00000040U
1643 #define CAN_FM1R_FBM7 0x00000080U
1644 #define CAN_FM1R_FBM8 0x00000100U
1645 #define CAN_FM1R_FBM9 0x00000200U
1646 #define CAN_FM1R_FBM10 0x00000400U
1647 #define CAN_FM1R_FBM11 0x00000800U
1648 #define CAN_FM1R_FBM12 0x00001000U
1649 #define CAN_FM1R_FBM13 0x00002000U
1650 #define CAN_FM1R_FBM14 0x00004000U
1651 #define CAN_FM1R_FBM15 0x00008000U
1652 #define CAN_FM1R_FBM16 0x00010000U
1653 #define CAN_FM1R_FBM17 0x00020000U
1654 #define CAN_FM1R_FBM18 0x00040000U
1655 #define CAN_FM1R_FBM19 0x00080000U
1656 #define CAN_FM1R_FBM20 0x00100000U
1657 #define CAN_FM1R_FBM21 0x00200000U
1658 #define CAN_FM1R_FBM22 0x00400000U
1659 #define CAN_FM1R_FBM23 0x00800000U
1660 #define CAN_FM1R_FBM24 0x01000000U
1661 #define CAN_FM1R_FBM25 0x02000000U
1662 #define CAN_FM1R_FBM26 0x04000000U
1663 #define CAN_FM1R_FBM27 0x08000000U
1665 /******************* Bit definition for CAN_FS1R register *******************/
1666 #define CAN_FS1R_FSC 0x0FFFFFFFU
1667 #define CAN_FS1R_FSC0 0x00000001U
1668 #define CAN_FS1R_FSC1 0x00000002U
1669 #define CAN_FS1R_FSC2 0x00000004U
1670 #define CAN_FS1R_FSC3 0x00000008U
1671 #define CAN_FS1R_FSC4 0x00000010U
1672 #define CAN_FS1R_FSC5 0x00000020U
1673 #define CAN_FS1R_FSC6 0x00000040U
1674 #define CAN_FS1R_FSC7 0x00000080U
1675 #define CAN_FS1R_FSC8 0x00000100U
1676 #define CAN_FS1R_FSC9 0x00000200U
1677 #define CAN_FS1R_FSC10 0x00000400U
1678 #define CAN_FS1R_FSC11 0x00000800U
1679 #define CAN_FS1R_FSC12 0x00001000U
1680 #define CAN_FS1R_FSC13 0x00002000U
1681 #define CAN_FS1R_FSC14 0x00004000U
1682 #define CAN_FS1R_FSC15 0x00008000U
1683 #define CAN_FS1R_FSC16 0x00010000U
1684 #define CAN_FS1R_FSC17 0x00020000U
1685 #define CAN_FS1R_FSC18 0x00040000U
1686 #define CAN_FS1R_FSC19 0x00080000U
1687 #define CAN_FS1R_FSC20 0x00100000U
1688 #define CAN_FS1R_FSC21 0x00200000U
1689 #define CAN_FS1R_FSC22 0x00400000U
1690 #define CAN_FS1R_FSC23 0x00800000U
1691 #define CAN_FS1R_FSC24 0x01000000U
1692 #define CAN_FS1R_FSC25 0x02000000U
1693 #define CAN_FS1R_FSC26 0x04000000U
1694 #define CAN_FS1R_FSC27 0x08000000U
1696 /****************** Bit definition for CAN_FFA1R register *******************/
1697 #define CAN_FFA1R_FFA 0x0FFFFFFFU
1698 #define CAN_FFA1R_FFA0 0x00000001U
1699 #define CAN_FFA1R_FFA1 0x00000002U
1700 #define CAN_FFA1R_FFA2 0x00000004U
1701 #define CAN_FFA1R_FFA3 0x00000008U
1702 #define CAN_FFA1R_FFA4 0x00000010U
1703 #define CAN_FFA1R_FFA5 0x00000020U
1704 #define CAN_FFA1R_FFA6 0x00000040U
1705 #define CAN_FFA1R_FFA7 0x00000080U
1706 #define CAN_FFA1R_FFA8 0x00000100U
1707 #define CAN_FFA1R_FFA9 0x00000200U
1708 #define CAN_FFA1R_FFA10 0x00000400U
1709 #define CAN_FFA1R_FFA11 0x00000800U
1710 #define CAN_FFA1R_FFA12 0x00001000U
1711 #define CAN_FFA1R_FFA13 0x00002000U
1712 #define CAN_FFA1R_FFA14 0x00004000U
1713 #define CAN_FFA1R_FFA15 0x00008000U
1714 #define CAN_FFA1R_FFA16 0x00010000U
1715 #define CAN_FFA1R_FFA17 0x00020000U
1716 #define CAN_FFA1R_FFA18 0x00040000U
1717 #define CAN_FFA1R_FFA19 0x00080000U
1718 #define CAN_FFA1R_FFA20 0x00100000U
1719 #define CAN_FFA1R_FFA21 0x00200000U
1720 #define CAN_FFA1R_FFA22 0x00400000U
1721 #define CAN_FFA1R_FFA23 0x00800000U
1722 #define CAN_FFA1R_FFA24 0x01000000U
1723 #define CAN_FFA1R_FFA25 0x02000000U
1724 #define CAN_FFA1R_FFA26 0x04000000U
1725 #define CAN_FFA1R_FFA27 0x08000000U
1727 /******************* Bit definition for CAN_FA1R register *******************/
1728 #define CAN_FA1R_FACT 0x0FFFFFFFU
1729 #define CAN_FA1R_FACT0 0x00000001U
1730 #define CAN_FA1R_FACT1 0x00000002U
1731 #define CAN_FA1R_FACT2 0x00000004U
1732 #define CAN_FA1R_FACT3 0x00000008U
1733 #define CAN_FA1R_FACT4 0x00000010U
1734 #define CAN_FA1R_FACT5 0x00000020U
1735 #define CAN_FA1R_FACT6 0x00000040U
1736 #define CAN_FA1R_FACT7 0x00000080U
1737 #define CAN_FA1R_FACT8 0x00000100U
1738 #define CAN_FA1R_FACT9 0x00000200U
1739 #define CAN_FA1R_FACT10 0x00000400U
1740 #define CAN_FA1R_FACT11 0x00000800U
1741 #define CAN_FA1R_FACT12 0x00001000U
1742 #define CAN_FA1R_FACT13 0x00002000U
1743 #define CAN_FA1R_FACT14 0x00004000U
1744 #define CAN_FA1R_FACT15 0x00008000U
1745 #define CAN_FA1R_FACT16 0x00010000U
1746 #define CAN_FA1R_FACT17 0x00020000U
1747 #define CAN_FA1R_FACT18 0x00040000U
1748 #define CAN_FA1R_FACT19 0x00080000U
1749 #define CAN_FA1R_FACT20 0x00100000U
1750 #define CAN_FA1R_FACT21 0x00200000U
1751 #define CAN_FA1R_FACT22 0x00400000U
1752 #define CAN_FA1R_FACT23 0x00800000U
1753 #define CAN_FA1R_FACT24 0x01000000U
1754 #define CAN_FA1R_FACT25 0x02000000U
1755 #define CAN_FA1R_FACT26 0x04000000U
1756 #define CAN_FA1R_FACT27 0x08000000U
1758 /******************* Bit definition for CAN_F0R1 register *******************/
1759 #define CAN_F0R1_FB0 0x00000001U
1760 #define CAN_F0R1_FB1 0x00000002U
1761 #define CAN_F0R1_FB2 0x00000004U
1762 #define CAN_F0R1_FB3 0x00000008U
1763 #define CAN_F0R1_FB4 0x00000010U
1764 #define CAN_F0R1_FB5 0x00000020U
1765 #define CAN_F0R1_FB6 0x00000040U
1766 #define CAN_F0R1_FB7 0x00000080U
1767 #define CAN_F0R1_FB8 0x00000100U
1768 #define CAN_F0R1_FB9 0x00000200U
1769 #define CAN_F0R1_FB10 0x00000400U
1770 #define CAN_F0R1_FB11 0x00000800U
1771 #define CAN_F0R1_FB12 0x00001000U
1772 #define CAN_F0R1_FB13 0x00002000U
1773 #define CAN_F0R1_FB14 0x00004000U
1774 #define CAN_F0R1_FB15 0x00008000U
1775 #define CAN_F0R1_FB16 0x00010000U
1776 #define CAN_F0R1_FB17 0x00020000U
1777 #define CAN_F0R1_FB18 0x00040000U
1778 #define CAN_F0R1_FB19 0x00080000U
1779 #define CAN_F0R1_FB20 0x00100000U
1780 #define CAN_F0R1_FB21 0x00200000U
1781 #define CAN_F0R1_FB22 0x00400000U
1782 #define CAN_F0R1_FB23 0x00800000U
1783 #define CAN_F0R1_FB24 0x01000000U
1784 #define CAN_F0R1_FB25 0x02000000U
1785 #define CAN_F0R1_FB26 0x04000000U
1786 #define CAN_F0R1_FB27 0x08000000U
1787 #define CAN_F0R1_FB28 0x10000000U
1788 #define CAN_F0R1_FB29 0x20000000U
1789 #define CAN_F0R1_FB30 0x40000000U
1790 #define CAN_F0R1_FB31 0x80000000U
1792 /******************* Bit definition for CAN_F1R1 register *******************/
1793 #define CAN_F1R1_FB0 0x00000001U
1794 #define CAN_F1R1_FB1 0x00000002U
1795 #define CAN_F1R1_FB2 0x00000004U
1796 #define CAN_F1R1_FB3 0x00000008U
1797 #define CAN_F1R1_FB4 0x00000010U
1798 #define CAN_F1R1_FB5 0x00000020U
1799 #define CAN_F1R1_FB6 0x00000040U
1800 #define CAN_F1R1_FB7 0x00000080U
1801 #define CAN_F1R1_FB8 0x00000100U
1802 #define CAN_F1R1_FB9 0x00000200U
1803 #define CAN_F1R1_FB10 0x00000400U
1804 #define CAN_F1R1_FB11 0x00000800U
1805 #define CAN_F1R1_FB12 0x00001000U
1806 #define CAN_F1R1_FB13 0x00002000U
1807 #define CAN_F1R1_FB14 0x00004000U
1808 #define CAN_F1R1_FB15 0x00008000U
1809 #define CAN_F1R1_FB16 0x00010000U
1810 #define CAN_F1R1_FB17 0x00020000U
1811 #define CAN_F1R1_FB18 0x00040000U
1812 #define CAN_F1R1_FB19 0x00080000U
1813 #define CAN_F1R1_FB20 0x00100000U
1814 #define CAN_F1R1_FB21 0x00200000U
1815 #define CAN_F1R1_FB22 0x00400000U
1816 #define CAN_F1R1_FB23 0x00800000U
1817 #define CAN_F1R1_FB24 0x01000000U
1818 #define CAN_F1R1_FB25 0x02000000U
1819 #define CAN_F1R1_FB26 0x04000000U
1820 #define CAN_F1R1_FB27 0x08000000U
1821 #define CAN_F1R1_FB28 0x10000000U
1822 #define CAN_F1R1_FB29 0x20000000U
1823 #define CAN_F1R1_FB30 0x40000000U
1824 #define CAN_F1R1_FB31 0x80000000U
1826 /******************* Bit definition for CAN_F2R1 register *******************/
1827 #define CAN_F2R1_FB0 0x00000001U
1828 #define CAN_F2R1_FB1 0x00000002U
1829 #define CAN_F2R1_FB2 0x00000004U
1830 #define CAN_F2R1_FB3 0x00000008U
1831 #define CAN_F2R1_FB4 0x00000010U
1832 #define CAN_F2R1_FB5 0x00000020U
1833 #define CAN_F2R1_FB6 0x00000040U
1834 #define CAN_F2R1_FB7 0x00000080U
1835 #define CAN_F2R1_FB8 0x00000100U
1836 #define CAN_F2R1_FB9 0x00000200U
1837 #define CAN_F2R1_FB10 0x00000400U
1838 #define CAN_F2R1_FB11 0x00000800U
1839 #define CAN_F2R1_FB12 0x00001000U
1840 #define CAN_F2R1_FB13 0x00002000U
1841 #define CAN_F2R1_FB14 0x00004000U
1842 #define CAN_F2R1_FB15 0x00008000U
1843 #define CAN_F2R1_FB16 0x00010000U
1844 #define CAN_F2R1_FB17 0x00020000U
1845 #define CAN_F2R1_FB18 0x00040000U
1846 #define CAN_F2R1_FB19 0x00080000U
1847 #define CAN_F2R1_FB20 0x00100000U
1848 #define CAN_F2R1_FB21 0x00200000U
1849 #define CAN_F2R1_FB22 0x00400000U
1850 #define CAN_F2R1_FB23 0x00800000U
1851 #define CAN_F2R1_FB24 0x01000000U
1852 #define CAN_F2R1_FB25 0x02000000U
1853 #define CAN_F2R1_FB26 0x04000000U
1854 #define CAN_F2R1_FB27 0x08000000U
1855 #define CAN_F2R1_FB28 0x10000000U
1856 #define CAN_F2R1_FB29 0x20000000U
1857 #define CAN_F2R1_FB30 0x40000000U
1858 #define CAN_F2R1_FB31 0x80000000U
1860 /******************* Bit definition for CAN_F3R1 register *******************/
1861 #define CAN_F3R1_FB0 0x00000001U
1862 #define CAN_F3R1_FB1 0x00000002U
1863 #define CAN_F3R1_FB2 0x00000004U
1864 #define CAN_F3R1_FB3 0x00000008U
1865 #define CAN_F3R1_FB4 0x00000010U
1866 #define CAN_F3R1_FB5 0x00000020U
1867 #define CAN_F3R1_FB6 0x00000040U
1868 #define CAN_F3R1_FB7 0x00000080U
1869 #define CAN_F3R1_FB8 0x00000100U
1870 #define CAN_F3R1_FB9 0x00000200U
1871 #define CAN_F3R1_FB10 0x00000400U
1872 #define CAN_F3R1_FB11 0x00000800U
1873 #define CAN_F3R1_FB12 0x00001000U
1874 #define CAN_F3R1_FB13 0x00002000U
1875 #define CAN_F3R1_FB14 0x00004000U
1876 #define CAN_F3R1_FB15 0x00008000U
1877 #define CAN_F3R1_FB16 0x00010000U
1878 #define CAN_F3R1_FB17 0x00020000U
1879 #define CAN_F3R1_FB18 0x00040000U
1880 #define CAN_F3R1_FB19 0x00080000U
1881 #define CAN_F3R1_FB20 0x00100000U
1882 #define CAN_F3R1_FB21 0x00200000U
1883 #define CAN_F3R1_FB22 0x00400000U
1884 #define CAN_F3R1_FB23 0x00800000U
1885 #define CAN_F3R1_FB24 0x01000000U
1886 #define CAN_F3R1_FB25 0x02000000U
1887 #define CAN_F3R1_FB26 0x04000000U
1888 #define CAN_F3R1_FB27 0x08000000U
1889 #define CAN_F3R1_FB28 0x10000000U
1890 #define CAN_F3R1_FB29 0x20000000U
1891 #define CAN_F3R1_FB30 0x40000000U
1892 #define CAN_F3R1_FB31 0x80000000U
1894 /******************* Bit definition for CAN_F4R1 register *******************/
1895 #define CAN_F4R1_FB0 0x00000001U
1896 #define CAN_F4R1_FB1 0x00000002U
1897 #define CAN_F4R1_FB2 0x00000004U
1898 #define CAN_F4R1_FB3 0x00000008U
1899 #define CAN_F4R1_FB4 0x00000010U
1900 #define CAN_F4R1_FB5 0x00000020U
1901 #define CAN_F4R1_FB6 0x00000040U
1902 #define CAN_F4R1_FB7 0x00000080U
1903 #define CAN_F4R1_FB8 0x00000100U
1904 #define CAN_F4R1_FB9 0x00000200U
1905 #define CAN_F4R1_FB10 0x00000400U
1906 #define CAN_F4R1_FB11 0x00000800U
1907 #define CAN_F4R1_FB12 0x00001000U
1908 #define CAN_F4R1_FB13 0x00002000U
1909 #define CAN_F4R1_FB14 0x00004000U
1910 #define CAN_F4R1_FB15 0x00008000U
1911 #define CAN_F4R1_FB16 0x00010000U
1912 #define CAN_F4R1_FB17 0x00020000U
1913 #define CAN_F4R1_FB18 0x00040000U
1914 #define CAN_F4R1_FB19 0x00080000U
1915 #define CAN_F4R1_FB20 0x00100000U
1916 #define CAN_F4R1_FB21 0x00200000U
1917 #define CAN_F4R1_FB22 0x00400000U
1918 #define CAN_F4R1_FB23 0x00800000U
1919 #define CAN_F4R1_FB24 0x01000000U
1920 #define CAN_F4R1_FB25 0x02000000U
1921 #define CAN_F4R1_FB26 0x04000000U
1922 #define CAN_F4R1_FB27 0x08000000U
1923 #define CAN_F4R1_FB28 0x10000000U
1924 #define CAN_F4R1_FB29 0x20000000U
1925 #define CAN_F4R1_FB30 0x40000000U
1926 #define CAN_F4R1_FB31 0x80000000U
1928 /******************* Bit definition for CAN_F5R1 register *******************/
1929 #define CAN_F5R1_FB0 0x00000001U
1930 #define CAN_F5R1_FB1 0x00000002U
1931 #define CAN_F5R1_FB2 0x00000004U
1932 #define CAN_F5R1_FB3 0x00000008U
1933 #define CAN_F5R1_FB4 0x00000010U
1934 #define CAN_F5R1_FB5 0x00000020U
1935 #define CAN_F5R1_FB6 0x00000040U
1936 #define CAN_F5R1_FB7 0x00000080U
1937 #define CAN_F5R1_FB8 0x00000100U
1938 #define CAN_F5R1_FB9 0x00000200U
1939 #define CAN_F5R1_FB10 0x00000400U
1940 #define CAN_F5R1_FB11 0x00000800U
1941 #define CAN_F5R1_FB12 0x00001000U
1942 #define CAN_F5R1_FB13 0x00002000U
1943 #define CAN_F5R1_FB14 0x00004000U
1944 #define CAN_F5R1_FB15 0x00008000U
1945 #define CAN_F5R1_FB16 0x00010000U
1946 #define CAN_F5R1_FB17 0x00020000U
1947 #define CAN_F5R1_FB18 0x00040000U
1948 #define CAN_F5R1_FB19 0x00080000U
1949 #define CAN_F5R1_FB20 0x00100000U
1950 #define CAN_F5R1_FB21 0x00200000U
1951 #define CAN_F5R1_FB22 0x00400000U
1952 #define CAN_F5R1_FB23 0x00800000U
1953 #define CAN_F5R1_FB24 0x01000000U
1954 #define CAN_F5R1_FB25 0x02000000U
1955 #define CAN_F5R1_FB26 0x04000000U
1956 #define CAN_F5R1_FB27 0x08000000U
1957 #define CAN_F5R1_FB28 0x10000000U
1958 #define CAN_F5R1_FB29 0x20000000U
1959 #define CAN_F5R1_FB30 0x40000000U
1960 #define CAN_F5R1_FB31 0x80000000U
1962 /******************* Bit definition for CAN_F6R1 register *******************/
1963 #define CAN_F6R1_FB0 0x00000001U
1964 #define CAN_F6R1_FB1 0x00000002U
1965 #define CAN_F6R1_FB2 0x00000004U
1966 #define CAN_F6R1_FB3 0x00000008U
1967 #define CAN_F6R1_FB4 0x00000010U
1968 #define CAN_F6R1_FB5 0x00000020U
1969 #define CAN_F6R1_FB6 0x00000040U
1970 #define CAN_F6R1_FB7 0x00000080U
1971 #define CAN_F6R1_FB8 0x00000100U
1972 #define CAN_F6R1_FB9 0x00000200U
1973 #define CAN_F6R1_FB10 0x00000400U
1974 #define CAN_F6R1_FB11 0x00000800U
1975 #define CAN_F6R1_FB12 0x00001000U
1976 #define CAN_F6R1_FB13 0x00002000U
1977 #define CAN_F6R1_FB14 0x00004000U
1978 #define CAN_F6R1_FB15 0x00008000U
1979 #define CAN_F6R1_FB16 0x00010000U
1980 #define CAN_F6R1_FB17 0x00020000U
1981 #define CAN_F6R1_FB18 0x00040000U
1982 #define CAN_F6R1_FB19 0x00080000U
1983 #define CAN_F6R1_FB20 0x00100000U
1984 #define CAN_F6R1_FB21 0x00200000U
1985 #define CAN_F6R1_FB22 0x00400000U
1986 #define CAN_F6R1_FB23 0x00800000U
1987 #define CAN_F6R1_FB24 0x01000000U
1988 #define CAN_F6R1_FB25 0x02000000U
1989 #define CAN_F6R1_FB26 0x04000000U
1990 #define CAN_F6R1_FB27 0x08000000U
1991 #define CAN_F6R1_FB28 0x10000000U
1992 #define CAN_F6R1_FB29 0x20000000U
1993 #define CAN_F6R1_FB30 0x40000000U
1994 #define CAN_F6R1_FB31 0x80000000U
1996 /******************* Bit definition for CAN_F7R1 register *******************/
1997 #define CAN_F7R1_FB0 0x00000001U
1998 #define CAN_F7R1_FB1 0x00000002U
1999 #define CAN_F7R1_FB2 0x00000004U
2000 #define CAN_F7R1_FB3 0x00000008U
2001 #define CAN_F7R1_FB4 0x00000010U
2002 #define CAN_F7R1_FB5 0x00000020U
2003 #define CAN_F7R1_FB6 0x00000040U
2004 #define CAN_F7R1_FB7 0x00000080U
2005 #define CAN_F7R1_FB8 0x00000100U
2006 #define CAN_F7R1_FB9 0x00000200U
2007 #define CAN_F7R1_FB10 0x00000400U
2008 #define CAN_F7R1_FB11 0x00000800U
2009 #define CAN_F7R1_FB12 0x00001000U
2010 #define CAN_F7R1_FB13 0x00002000U
2011 #define CAN_F7R1_FB14 0x00004000U
2012 #define CAN_F7R1_FB15 0x00008000U
2013 #define CAN_F7R1_FB16 0x00010000U
2014 #define CAN_F7R1_FB17 0x00020000U
2015 #define CAN_F7R1_FB18 0x00040000U
2016 #define CAN_F7R1_FB19 0x00080000U
2017 #define CAN_F7R1_FB20 0x00100000U
2018 #define CAN_F7R1_FB21 0x00200000U
2019 #define CAN_F7R1_FB22 0x00400000U
2020 #define CAN_F7R1_FB23 0x00800000U
2021 #define CAN_F7R1_FB24 0x01000000U
2022 #define CAN_F7R1_FB25 0x02000000U
2023 #define CAN_F7R1_FB26 0x04000000U
2024 #define CAN_F7R1_FB27 0x08000000U
2025 #define CAN_F7R1_FB28 0x10000000U
2026 #define CAN_F7R1_FB29 0x20000000U
2027 #define CAN_F7R1_FB30 0x40000000U
2028 #define CAN_F7R1_FB31 0x80000000U
2030 /******************* Bit definition for CAN_F8R1 register *******************/
2031 #define CAN_F8R1_FB0 0x00000001U
2032 #define CAN_F8R1_FB1 0x00000002U
2033 #define CAN_F8R1_FB2 0x00000004U
2034 #define CAN_F8R1_FB3 0x00000008U
2035 #define CAN_F8R1_FB4 0x00000010U
2036 #define CAN_F8R1_FB5 0x00000020U
2037 #define CAN_F8R1_FB6 0x00000040U
2038 #define CAN_F8R1_FB7 0x00000080U
2039 #define CAN_F8R1_FB8 0x00000100U
2040 #define CAN_F8R1_FB9 0x00000200U
2041 #define CAN_F8R1_FB10 0x00000400U
2042 #define CAN_F8R1_FB11 0x00000800U
2043 #define CAN_F8R1_FB12 0x00001000U
2044 #define CAN_F8R1_FB13 0x00002000U
2045 #define CAN_F8R1_FB14 0x00004000U
2046 #define CAN_F8R1_FB15 0x00008000U
2047 #define CAN_F8R1_FB16 0x00010000U
2048 #define CAN_F8R1_FB17 0x00020000U
2049 #define CAN_F8R1_FB18 0x00040000U
2050 #define CAN_F8R1_FB19 0x00080000U
2051 #define CAN_F8R1_FB20 0x00100000U
2052 #define CAN_F8R1_FB21 0x00200000U
2053 #define CAN_F8R1_FB22 0x00400000U
2054 #define CAN_F8R1_FB23 0x00800000U
2055 #define CAN_F8R1_FB24 0x01000000U
2056 #define CAN_F8R1_FB25 0x02000000U
2057 #define CAN_F8R1_FB26 0x04000000U
2058 #define CAN_F8R1_FB27 0x08000000U
2059 #define CAN_F8R1_FB28 0x10000000U
2060 #define CAN_F8R1_FB29 0x20000000U
2061 #define CAN_F8R1_FB30 0x40000000U
2062 #define CAN_F8R1_FB31 0x80000000U
2064 /******************* Bit definition for CAN_F9R1 register *******************/
2065 #define CAN_F9R1_FB0 0x00000001U
2066 #define CAN_F9R1_FB1 0x00000002U
2067 #define CAN_F9R1_FB2 0x00000004U
2068 #define CAN_F9R1_FB3 0x00000008U
2069 #define CAN_F9R1_FB4 0x00000010U
2070 #define CAN_F9R1_FB5 0x00000020U
2071 #define CAN_F9R1_FB6 0x00000040U
2072 #define CAN_F9R1_FB7 0x00000080U
2073 #define CAN_F9R1_FB8 0x00000100U
2074 #define CAN_F9R1_FB9 0x00000200U
2075 #define CAN_F9R1_FB10 0x00000400U
2076 #define CAN_F9R1_FB11 0x00000800U
2077 #define CAN_F9R1_FB12 0x00001000U
2078 #define CAN_F9R1_FB13 0x00002000U
2079 #define CAN_F9R1_FB14 0x00004000U
2080 #define CAN_F9R1_FB15 0x00008000U
2081 #define CAN_F9R1_FB16 0x00010000U
2082 #define CAN_F9R1_FB17 0x00020000U
2083 #define CAN_F9R1_FB18 0x00040000U
2084 #define CAN_F9R1_FB19 0x00080000U
2085 #define CAN_F9R1_FB20 0x00100000U
2086 #define CAN_F9R1_FB21 0x00200000U
2087 #define CAN_F9R1_FB22 0x00400000U
2088 #define CAN_F9R1_FB23 0x00800000U
2089 #define CAN_F9R1_FB24 0x01000000U
2090 #define CAN_F9R1_FB25 0x02000000U
2091 #define CAN_F9R1_FB26 0x04000000U
2092 #define CAN_F9R1_FB27 0x08000000U
2093 #define CAN_F9R1_FB28 0x10000000U
2094 #define CAN_F9R1_FB29 0x20000000U
2095 #define CAN_F9R1_FB30 0x40000000U
2096 #define CAN_F9R1_FB31 0x80000000U
2098 /******************* Bit definition for CAN_F10R1 register ******************/
2099 #define CAN_F10R1_FB0 0x00000001U
2100 #define CAN_F10R1_FB1 0x00000002U
2101 #define CAN_F10R1_FB2 0x00000004U
2102 #define CAN_F10R1_FB3 0x00000008U
2103 #define CAN_F10R1_FB4 0x00000010U
2104 #define CAN_F10R1_FB5 0x00000020U
2105 #define CAN_F10R1_FB6 0x00000040U
2106 #define CAN_F10R1_FB7 0x00000080U
2107 #define CAN_F10R1_FB8 0x00000100U
2108 #define CAN_F10R1_FB9 0x00000200U
2109 #define CAN_F10R1_FB10 0x00000400U
2110 #define CAN_F10R1_FB11 0x00000800U
2111 #define CAN_F10R1_FB12 0x00001000U
2112 #define CAN_F10R1_FB13 0x00002000U
2113 #define CAN_F10R1_FB14 0x00004000U
2114 #define CAN_F10R1_FB15 0x00008000U
2115 #define CAN_F10R1_FB16 0x00010000U
2116 #define CAN_F10R1_FB17 0x00020000U
2117 #define CAN_F10R1_FB18 0x00040000U
2118 #define CAN_F10R1_FB19 0x00080000U
2119 #define CAN_F10R1_FB20 0x00100000U
2120 #define CAN_F10R1_FB21 0x00200000U
2121 #define CAN_F10R1_FB22 0x00400000U
2122 #define CAN_F10R1_FB23 0x00800000U
2123 #define CAN_F10R1_FB24 0x01000000U
2124 #define CAN_F10R1_FB25 0x02000000U
2125 #define CAN_F10R1_FB26 0x04000000U
2126 #define CAN_F10R1_FB27 0x08000000U
2127 #define CAN_F10R1_FB28 0x10000000U
2128 #define CAN_F10R1_FB29 0x20000000U
2129 #define CAN_F10R1_FB30 0x40000000U
2130 #define CAN_F10R1_FB31 0x80000000U
2132 /******************* Bit definition for CAN_F11R1 register ******************/
2133 #define CAN_F11R1_FB0 0x00000001U
2134 #define CAN_F11R1_FB1 0x00000002U
2135 #define CAN_F11R1_FB2 0x00000004U
2136 #define CAN_F11R1_FB3 0x00000008U
2137 #define CAN_F11R1_FB4 0x00000010U
2138 #define CAN_F11R1_FB5 0x00000020U
2139 #define CAN_F11R1_FB6 0x00000040U
2140 #define CAN_F11R1_FB7 0x00000080U
2141 #define CAN_F11R1_FB8 0x00000100U
2142 #define CAN_F11R1_FB9 0x00000200U
2143 #define CAN_F11R1_FB10 0x00000400U
2144 #define CAN_F11R1_FB11 0x00000800U
2145 #define CAN_F11R1_FB12 0x00001000U
2146 #define CAN_F11R1_FB13 0x00002000U
2147 #define CAN_F11R1_FB14 0x00004000U
2148 #define CAN_F11R1_FB15 0x00008000U
2149 #define CAN_F11R1_FB16 0x00010000U
2150 #define CAN_F11R1_FB17 0x00020000U
2151 #define CAN_F11R1_FB18 0x00040000U
2152 #define CAN_F11R1_FB19 0x00080000U
2153 #define CAN_F11R1_FB20 0x00100000U
2154 #define CAN_F11R1_FB21 0x00200000U
2155 #define CAN_F11R1_FB22 0x00400000U
2156 #define CAN_F11R1_FB23 0x00800000U
2157 #define CAN_F11R1_FB24 0x01000000U
2158 #define CAN_F11R1_FB25 0x02000000U
2159 #define CAN_F11R1_FB26 0x04000000U
2160 #define CAN_F11R1_FB27 0x08000000U
2161 #define CAN_F11R1_FB28 0x10000000U
2162 #define CAN_F11R1_FB29 0x20000000U
2163 #define CAN_F11R1_FB30 0x40000000U
2164 #define CAN_F11R1_FB31 0x80000000U
2166 /******************* Bit definition for CAN_F12R1 register ******************/
2167 #define CAN_F12R1_FB0 0x00000001U
2168 #define CAN_F12R1_FB1 0x00000002U
2169 #define CAN_F12R1_FB2 0x00000004U
2170 #define CAN_F12R1_FB3 0x00000008U
2171 #define CAN_F12R1_FB4 0x00000010U
2172 #define CAN_F12R1_FB5 0x00000020U
2173 #define CAN_F12R1_FB6 0x00000040U
2174 #define CAN_F12R1_FB7 0x00000080U
2175 #define CAN_F12R1_FB8 0x00000100U
2176 #define CAN_F12R1_FB9 0x00000200U
2177 #define CAN_F12R1_FB10 0x00000400U
2178 #define CAN_F12R1_FB11 0x00000800U
2179 #define CAN_F12R1_FB12 0x00001000U
2180 #define CAN_F12R1_FB13 0x00002000U
2181 #define CAN_F12R1_FB14 0x00004000U
2182 #define CAN_F12R1_FB15 0x00008000U
2183 #define CAN_F12R1_FB16 0x00010000U
2184 #define CAN_F12R1_FB17 0x00020000U
2185 #define CAN_F12R1_FB18 0x00040000U
2186 #define CAN_F12R1_FB19 0x00080000U
2187 #define CAN_F12R1_FB20 0x00100000U
2188 #define CAN_F12R1_FB21 0x00200000U
2189 #define CAN_F12R1_FB22 0x00400000U
2190 #define CAN_F12R1_FB23 0x00800000U
2191 #define CAN_F12R1_FB24 0x01000000U
2192 #define CAN_F12R1_FB25 0x02000000U
2193 #define CAN_F12R1_FB26 0x04000000U
2194 #define CAN_F12R1_FB27 0x08000000U
2195 #define CAN_F12R1_FB28 0x10000000U
2196 #define CAN_F12R1_FB29 0x20000000U
2197 #define CAN_F12R1_FB30 0x40000000U
2198 #define CAN_F12R1_FB31 0x80000000U
2200 /******************* Bit definition for CAN_F13R1 register ******************/
2201 #define CAN_F13R1_FB0 0x00000001U
2202 #define CAN_F13R1_FB1 0x00000002U
2203 #define CAN_F13R1_FB2 0x00000004U
2204 #define CAN_F13R1_FB3 0x00000008U
2205 #define CAN_F13R1_FB4 0x00000010U
2206 #define CAN_F13R1_FB5 0x00000020U
2207 #define CAN_F13R1_FB6 0x00000040U
2208 #define CAN_F13R1_FB7 0x00000080U
2209 #define CAN_F13R1_FB8 0x00000100U
2210 #define CAN_F13R1_FB9 0x00000200U
2211 #define CAN_F13R1_FB10 0x00000400U
2212 #define CAN_F13R1_FB11 0x00000800U
2213 #define CAN_F13R1_FB12 0x00001000U
2214 #define CAN_F13R1_FB13 0x00002000U
2215 #define CAN_F13R1_FB14 0x00004000U
2216 #define CAN_F13R1_FB15 0x00008000U
2217 #define CAN_F13R1_FB16 0x00010000U
2218 #define CAN_F13R1_FB17 0x00020000U
2219 #define CAN_F13R1_FB18 0x00040000U
2220 #define CAN_F13R1_FB19 0x00080000U
2221 #define CAN_F13R1_FB20 0x00100000U
2222 #define CAN_F13R1_FB21 0x00200000U
2223 #define CAN_F13R1_FB22 0x00400000U
2224 #define CAN_F13R1_FB23 0x00800000U
2225 #define CAN_F13R1_FB24 0x01000000U
2226 #define CAN_F13R1_FB25 0x02000000U
2227 #define CAN_F13R1_FB26 0x04000000U
2228 #define CAN_F13R1_FB27 0x08000000U
2229 #define CAN_F13R1_FB28 0x10000000U
2230 #define CAN_F13R1_FB29 0x20000000U
2231 #define CAN_F13R1_FB30 0x40000000U
2232 #define CAN_F13R1_FB31 0x80000000U
2234 /******************* Bit definition for CAN_F0R2 register *******************/
2235 #define CAN_F0R2_FB0 0x00000001U
2236 #define CAN_F0R2_FB1 0x00000002U
2237 #define CAN_F0R2_FB2 0x00000004U
2238 #define CAN_F0R2_FB3 0x00000008U
2239 #define CAN_F0R2_FB4 0x00000010U
2240 #define CAN_F0R2_FB5 0x00000020U
2241 #define CAN_F0R2_FB6 0x00000040U
2242 #define CAN_F0R2_FB7 0x00000080U
2243 #define CAN_F0R2_FB8 0x00000100U
2244 #define CAN_F0R2_FB9 0x00000200U
2245 #define CAN_F0R2_FB10 0x00000400U
2246 #define CAN_F0R2_FB11 0x00000800U
2247 #define CAN_F0R2_FB12 0x00001000U
2248 #define CAN_F0R2_FB13 0x00002000U
2249 #define CAN_F0R2_FB14 0x00004000U
2250 #define CAN_F0R2_FB15 0x00008000U
2251 #define CAN_F0R2_FB16 0x00010000U
2252 #define CAN_F0R2_FB17 0x00020000U
2253 #define CAN_F0R2_FB18 0x00040000U
2254 #define CAN_F0R2_FB19 0x00080000U
2255 #define CAN_F0R2_FB20 0x00100000U
2256 #define CAN_F0R2_FB21 0x00200000U
2257 #define CAN_F0R2_FB22 0x00400000U
2258 #define CAN_F0R2_FB23 0x00800000U
2259 #define CAN_F0R2_FB24 0x01000000U
2260 #define CAN_F0R2_FB25 0x02000000U
2261 #define CAN_F0R2_FB26 0x04000000U
2262 #define CAN_F0R2_FB27 0x08000000U
2263 #define CAN_F0R2_FB28 0x10000000U
2264 #define CAN_F0R2_FB29 0x20000000U
2265 #define CAN_F0R2_FB30 0x40000000U
2266 #define CAN_F0R2_FB31 0x80000000U
2268 /******************* Bit definition for CAN_F1R2 register *******************/
2269 #define CAN_F1R2_FB0 0x00000001U
2270 #define CAN_F1R2_FB1 0x00000002U
2271 #define CAN_F1R2_FB2 0x00000004U
2272 #define CAN_F1R2_FB3 0x00000008U
2273 #define CAN_F1R2_FB4 0x00000010U
2274 #define CAN_F1R2_FB5 0x00000020U
2275 #define CAN_F1R2_FB6 0x00000040U
2276 #define CAN_F1R2_FB7 0x00000080U
2277 #define CAN_F1R2_FB8 0x00000100U
2278 #define CAN_F1R2_FB9 0x00000200U
2279 #define CAN_F1R2_FB10 0x00000400U
2280 #define CAN_F1R2_FB11 0x00000800U
2281 #define CAN_F1R2_FB12 0x00001000U
2282 #define CAN_F1R2_FB13 0x00002000U
2283 #define CAN_F1R2_FB14 0x00004000U
2284 #define CAN_F1R2_FB15 0x00008000U
2285 #define CAN_F1R2_FB16 0x00010000U
2286 #define CAN_F1R2_FB17 0x00020000U
2287 #define CAN_F1R2_FB18 0x00040000U
2288 #define CAN_F1R2_FB19 0x00080000U
2289 #define CAN_F1R2_FB20 0x00100000U
2290 #define CAN_F1R2_FB21 0x00200000U
2291 #define CAN_F1R2_FB22 0x00400000U
2292 #define CAN_F1R2_FB23 0x00800000U
2293 #define CAN_F1R2_FB24 0x01000000U
2294 #define CAN_F1R2_FB25 0x02000000U
2295 #define CAN_F1R2_FB26 0x04000000U
2296 #define CAN_F1R2_FB27 0x08000000U
2297 #define CAN_F1R2_FB28 0x10000000U
2298 #define CAN_F1R2_FB29 0x20000000U
2299 #define CAN_F1R2_FB30 0x40000000U
2300 #define CAN_F1R2_FB31 0x80000000U
2302 /******************* Bit definition for CAN_F2R2 register *******************/
2303 #define CAN_F2R2_FB0 0x00000001U
2304 #define CAN_F2R2_FB1 0x00000002U
2305 #define CAN_F2R2_FB2 0x00000004U
2306 #define CAN_F2R2_FB3 0x00000008U
2307 #define CAN_F2R2_FB4 0x00000010U
2308 #define CAN_F2R2_FB5 0x00000020U
2309 #define CAN_F2R2_FB6 0x00000040U
2310 #define CAN_F2R2_FB7 0x00000080U
2311 #define CAN_F2R2_FB8 0x00000100U
2312 #define CAN_F2R2_FB9 0x00000200U
2313 #define CAN_F2R2_FB10 0x00000400U
2314 #define CAN_F2R2_FB11 0x00000800U
2315 #define CAN_F2R2_FB12 0x00001000U
2316 #define CAN_F2R2_FB13 0x00002000U
2317 #define CAN_F2R2_FB14 0x00004000U
2318 #define CAN_F2R2_FB15 0x00008000U
2319 #define CAN_F2R2_FB16 0x00010000U
2320 #define CAN_F2R2_FB17 0x00020000U
2321 #define CAN_F2R2_FB18 0x00040000U
2322 #define CAN_F2R2_FB19 0x00080000U
2323 #define CAN_F2R2_FB20 0x00100000U
2324 #define CAN_F2R2_FB21 0x00200000U
2325 #define CAN_F2R2_FB22 0x00400000U
2326 #define CAN_F2R2_FB23 0x00800000U
2327 #define CAN_F2R2_FB24 0x01000000U
2328 #define CAN_F2R2_FB25 0x02000000U
2329 #define CAN_F2R2_FB26 0x04000000U
2330 #define CAN_F2R2_FB27 0x08000000U
2331 #define CAN_F2R2_FB28 0x10000000U
2332 #define CAN_F2R2_FB29 0x20000000U
2333 #define CAN_F2R2_FB30 0x40000000U
2334 #define CAN_F2R2_FB31 0x80000000U
2336 /******************* Bit definition for CAN_F3R2 register *******************/
2337 #define CAN_F3R2_FB0 0x00000001U
2338 #define CAN_F3R2_FB1 0x00000002U
2339 #define CAN_F3R2_FB2 0x00000004U
2340 #define CAN_F3R2_FB3 0x00000008U
2341 #define CAN_F3R2_FB4 0x00000010U
2342 #define CAN_F3R2_FB5 0x00000020U
2343 #define CAN_F3R2_FB6 0x00000040U
2344 #define CAN_F3R2_FB7 0x00000080U
2345 #define CAN_F3R2_FB8 0x00000100U
2346 #define CAN_F3R2_FB9 0x00000200U
2347 #define CAN_F3R2_FB10 0x00000400U
2348 #define CAN_F3R2_FB11 0x00000800U
2349 #define CAN_F3R2_FB12 0x00001000U
2350 #define CAN_F3R2_FB13 0x00002000U
2351 #define CAN_F3R2_FB14 0x00004000U
2352 #define CAN_F3R2_FB15 0x00008000U
2353 #define CAN_F3R2_FB16 0x00010000U
2354 #define CAN_F3R2_FB17 0x00020000U
2355 #define CAN_F3R2_FB18 0x00040000U
2356 #define CAN_F3R2_FB19 0x00080000U
2357 #define CAN_F3R2_FB20 0x00100000U
2358 #define CAN_F3R2_FB21 0x00200000U
2359 #define CAN_F3R2_FB22 0x00400000U
2360 #define CAN_F3R2_FB23 0x00800000U
2361 #define CAN_F3R2_FB24 0x01000000U
2362 #define CAN_F3R2_FB25 0x02000000U
2363 #define CAN_F3R2_FB26 0x04000000U
2364 #define CAN_F3R2_FB27 0x08000000U
2365 #define CAN_F3R2_FB28 0x10000000U
2366 #define CAN_F3R2_FB29 0x20000000U
2367 #define CAN_F3R2_FB30 0x40000000U
2368 #define CAN_F3R2_FB31 0x80000000U
2370 /******************* Bit definition for CAN_F4R2 register *******************/
2371 #define CAN_F4R2_FB0 0x00000001U
2372 #define CAN_F4R2_FB1 0x00000002U
2373 #define CAN_F4R2_FB2 0x00000004U
2374 #define CAN_F4R2_FB3 0x00000008U
2375 #define CAN_F4R2_FB4 0x00000010U
2376 #define CAN_F4R2_FB5 0x00000020U
2377 #define CAN_F4R2_FB6 0x00000040U
2378 #define CAN_F4R2_FB7 0x00000080U
2379 #define CAN_F4R2_FB8 0x00000100U
2380 #define CAN_F4R2_FB9 0x00000200U
2381 #define CAN_F4R2_FB10 0x00000400U
2382 #define CAN_F4R2_FB11 0x00000800U
2383 #define CAN_F4R2_FB12 0x00001000U
2384 #define CAN_F4R2_FB13 0x00002000U
2385 #define CAN_F4R2_FB14 0x00004000U
2386 #define CAN_F4R2_FB15 0x00008000U
2387 #define CAN_F4R2_FB16 0x00010000U
2388 #define CAN_F4R2_FB17 0x00020000U
2389 #define CAN_F4R2_FB18 0x00040000U
2390 #define CAN_F4R2_FB19 0x00080000U
2391 #define CAN_F4R2_FB20 0x00100000U
2392 #define CAN_F4R2_FB21 0x00200000U
2393 #define CAN_F4R2_FB22 0x00400000U
2394 #define CAN_F4R2_FB23 0x00800000U
2395 #define CAN_F4R2_FB24 0x01000000U
2396 #define CAN_F4R2_FB25 0x02000000U
2397 #define CAN_F4R2_FB26 0x04000000U
2398 #define CAN_F4R2_FB27 0x08000000U
2399 #define CAN_F4R2_FB28 0x10000000U
2400 #define CAN_F4R2_FB29 0x20000000U
2401 #define CAN_F4R2_FB30 0x40000000U
2402 #define CAN_F4R2_FB31 0x80000000U
2404 /******************* Bit definition for CAN_F5R2 register *******************/
2405 #define CAN_F5R2_FB0 0x00000001U
2406 #define CAN_F5R2_FB1 0x00000002U
2407 #define CAN_F5R2_FB2 0x00000004U
2408 #define CAN_F5R2_FB3 0x00000008U
2409 #define CAN_F5R2_FB4 0x00000010U
2410 #define CAN_F5R2_FB5 0x00000020U
2411 #define CAN_F5R2_FB6 0x00000040U
2412 #define CAN_F5R2_FB7 0x00000080U
2413 #define CAN_F5R2_FB8 0x00000100U
2414 #define CAN_F5R2_FB9 0x00000200U
2415 #define CAN_F5R2_FB10 0x00000400U
2416 #define CAN_F5R2_FB11 0x00000800U
2417 #define CAN_F5R2_FB12 0x00001000U
2418 #define CAN_F5R2_FB13 0x00002000U
2419 #define CAN_F5R2_FB14 0x00004000U
2420 #define CAN_F5R2_FB15 0x00008000U
2421 #define CAN_F5R2_FB16 0x00010000U
2422 #define CAN_F5R2_FB17 0x00020000U
2423 #define CAN_F5R2_FB18 0x00040000U
2424 #define CAN_F5R2_FB19 0x00080000U
2425 #define CAN_F5R2_FB20 0x00100000U
2426 #define CAN_F5R2_FB21 0x00200000U
2427 #define CAN_F5R2_FB22 0x00400000U
2428 #define CAN_F5R2_FB23 0x00800000U
2429 #define CAN_F5R2_FB24 0x01000000U
2430 #define CAN_F5R2_FB25 0x02000000U
2431 #define CAN_F5R2_FB26 0x04000000U
2432 #define CAN_F5R2_FB27 0x08000000U
2433 #define CAN_F5R2_FB28 0x10000000U
2434 #define CAN_F5R2_FB29 0x20000000U
2435 #define CAN_F5R2_FB30 0x40000000U
2436 #define CAN_F5R2_FB31 0x80000000U
2438 /******************* Bit definition for CAN_F6R2 register *******************/
2439 #define CAN_F6R2_FB0 0x00000001U
2440 #define CAN_F6R2_FB1 0x00000002U
2441 #define CAN_F6R2_FB2 0x00000004U
2442 #define CAN_F6R2_FB3 0x00000008U
2443 #define CAN_F6R2_FB4 0x00000010U
2444 #define CAN_F6R2_FB5 0x00000020U
2445 #define CAN_F6R2_FB6 0x00000040U
2446 #define CAN_F6R2_FB7 0x00000080U
2447 #define CAN_F6R2_FB8 0x00000100U
2448 #define CAN_F6R2_FB9 0x00000200U
2449 #define CAN_F6R2_FB10 0x00000400U
2450 #define CAN_F6R2_FB11 0x00000800U
2451 #define CAN_F6R2_FB12 0x00001000U
2452 #define CAN_F6R2_FB13 0x00002000U
2453 #define CAN_F6R2_FB14 0x00004000U
2454 #define CAN_F6R2_FB15 0x00008000U
2455 #define CAN_F6R2_FB16 0x00010000U
2456 #define CAN_F6R2_FB17 0x00020000U
2457 #define CAN_F6R2_FB18 0x00040000U
2458 #define CAN_F6R2_FB19 0x00080000U
2459 #define CAN_F6R2_FB20 0x00100000U
2460 #define CAN_F6R2_FB21 0x00200000U
2461 #define CAN_F6R2_FB22 0x00400000U
2462 #define CAN_F6R2_FB23 0x00800000U
2463 #define CAN_F6R2_FB24 0x01000000U
2464 #define CAN_F6R2_FB25 0x02000000U
2465 #define CAN_F6R2_FB26 0x04000000U
2466 #define CAN_F6R2_FB27 0x08000000U
2467 #define CAN_F6R2_FB28 0x10000000U
2468 #define CAN_F6R2_FB29 0x20000000U
2469 #define CAN_F6R2_FB30 0x40000000U
2470 #define CAN_F6R2_FB31 0x80000000U
2472 /******************* Bit definition for CAN_F7R2 register *******************/
2473 #define CAN_F7R2_FB0 0x00000001U
2474 #define CAN_F7R2_FB1 0x00000002U
2475 #define CAN_F7R2_FB2 0x00000004U
2476 #define CAN_F7R2_FB3 0x00000008U
2477 #define CAN_F7R2_FB4 0x00000010U
2478 #define CAN_F7R2_FB5 0x00000020U
2479 #define CAN_F7R2_FB6 0x00000040U
2480 #define CAN_F7R2_FB7 0x00000080U
2481 #define CAN_F7R2_FB8 0x00000100U
2482 #define CAN_F7R2_FB9 0x00000200U
2483 #define CAN_F7R2_FB10 0x00000400U
2484 #define CAN_F7R2_FB11 0x00000800U
2485 #define CAN_F7R2_FB12 0x00001000U
2486 #define CAN_F7R2_FB13 0x00002000U
2487 #define CAN_F7R2_FB14 0x00004000U
2488 #define CAN_F7R2_FB15 0x00008000U
2489 #define CAN_F7R2_FB16 0x00010000U
2490 #define CAN_F7R2_FB17 0x00020000U
2491 #define CAN_F7R2_FB18 0x00040000U
2492 #define CAN_F7R2_FB19 0x00080000U
2493 #define CAN_F7R2_FB20 0x00100000U
2494 #define CAN_F7R2_FB21 0x00200000U
2495 #define CAN_F7R2_FB22 0x00400000U
2496 #define CAN_F7R2_FB23 0x00800000U
2497 #define CAN_F7R2_FB24 0x01000000U
2498 #define CAN_F7R2_FB25 0x02000000U
2499 #define CAN_F7R2_FB26 0x04000000U
2500 #define CAN_F7R2_FB27 0x08000000U
2501 #define CAN_F7R2_FB28 0x10000000U
2502 #define CAN_F7R2_FB29 0x20000000U
2503 #define CAN_F7R2_FB30 0x40000000U
2504 #define CAN_F7R2_FB31 0x80000000U
2506 /******************* Bit definition for CAN_F8R2 register *******************/
2507 #define CAN_F8R2_FB0 0x00000001U
2508 #define CAN_F8R2_FB1 0x00000002U
2509 #define CAN_F8R2_FB2 0x00000004U
2510 #define CAN_F8R2_FB3 0x00000008U
2511 #define CAN_F8R2_FB4 0x00000010U
2512 #define CAN_F8R2_FB5 0x00000020U
2513 #define CAN_F8R2_FB6 0x00000040U
2514 #define CAN_F8R2_FB7 0x00000080U
2515 #define CAN_F8R2_FB8 0x00000100U
2516 #define CAN_F8R2_FB9 0x00000200U
2517 #define CAN_F8R2_FB10 0x00000400U
2518 #define CAN_F8R2_FB11 0x00000800U
2519 #define CAN_F8R2_FB12 0x00001000U
2520 #define CAN_F8R2_FB13 0x00002000U
2521 #define CAN_F8R2_FB14 0x00004000U
2522 #define CAN_F8R2_FB15 0x00008000U
2523 #define CAN_F8R2_FB16 0x00010000U
2524 #define CAN_F8R2_FB17 0x00020000U
2525 #define CAN_F8R2_FB18 0x00040000U
2526 #define CAN_F8R2_FB19 0x00080000U
2527 #define CAN_F8R2_FB20 0x00100000U
2528 #define CAN_F8R2_FB21 0x00200000U
2529 #define CAN_F8R2_FB22 0x00400000U
2530 #define CAN_F8R2_FB23 0x00800000U
2531 #define CAN_F8R2_FB24 0x01000000U
2532 #define CAN_F8R2_FB25 0x02000000U
2533 #define CAN_F8R2_FB26 0x04000000U
2534 #define CAN_F8R2_FB27 0x08000000U
2535 #define CAN_F8R2_FB28 0x10000000U
2536 #define CAN_F8R2_FB29 0x20000000U
2537 #define CAN_F8R2_FB30 0x40000000U
2538 #define CAN_F8R2_FB31 0x80000000U
2540 /******************* Bit definition for CAN_F9R2 register *******************/
2541 #define CAN_F9R2_FB0 0x00000001U
2542 #define CAN_F9R2_FB1 0x00000002U
2543 #define CAN_F9R2_FB2 0x00000004U
2544 #define CAN_F9R2_FB3 0x00000008U
2545 #define CAN_F9R2_FB4 0x00000010U
2546 #define CAN_F9R2_FB5 0x00000020U
2547 #define CAN_F9R2_FB6 0x00000040U
2548 #define CAN_F9R2_FB7 0x00000080U
2549 #define CAN_F9R2_FB8 0x00000100U
2550 #define CAN_F9R2_FB9 0x00000200U
2551 #define CAN_F9R2_FB10 0x00000400U
2552 #define CAN_F9R2_FB11 0x00000800U
2553 #define CAN_F9R2_FB12 0x00001000U
2554 #define CAN_F9R2_FB13 0x00002000U
2555 #define CAN_F9R2_FB14 0x00004000U
2556 #define CAN_F9R2_FB15 0x00008000U
2557 #define CAN_F9R2_FB16 0x00010000U
2558 #define CAN_F9R2_FB17 0x00020000U
2559 #define CAN_F9R2_FB18 0x00040000U
2560 #define CAN_F9R2_FB19 0x00080000U
2561 #define CAN_F9R2_FB20 0x00100000U
2562 #define CAN_F9R2_FB21 0x00200000U
2563 #define CAN_F9R2_FB22 0x00400000U
2564 #define CAN_F9R2_FB23 0x00800000U
2565 #define CAN_F9R2_FB24 0x01000000U
2566 #define CAN_F9R2_FB25 0x02000000U
2567 #define CAN_F9R2_FB26 0x04000000U
2568 #define CAN_F9R2_FB27 0x08000000U
2569 #define CAN_F9R2_FB28 0x10000000U
2570 #define CAN_F9R2_FB29 0x20000000U
2571 #define CAN_F9R2_FB30 0x40000000U
2572 #define CAN_F9R2_FB31 0x80000000U
2574 /******************* Bit definition for CAN_F10R2 register ******************/
2575 #define CAN_F10R2_FB0 0x00000001U
2576 #define CAN_F10R2_FB1 0x00000002U
2577 #define CAN_F10R2_FB2 0x00000004U
2578 #define CAN_F10R2_FB3 0x00000008U
2579 #define CAN_F10R2_FB4 0x00000010U
2580 #define CAN_F10R2_FB5 0x00000020U
2581 #define CAN_F10R2_FB6 0x00000040U
2582 #define CAN_F10R2_FB7 0x00000080U
2583 #define CAN_F10R2_FB8 0x00000100U
2584 #define CAN_F10R2_FB9 0x00000200U
2585 #define CAN_F10R2_FB10 0x00000400U
2586 #define CAN_F10R2_FB11 0x00000800U
2587 #define CAN_F10R2_FB12 0x00001000U
2588 #define CAN_F10R2_FB13 0x00002000U
2589 #define CAN_F10R2_FB14 0x00004000U
2590 #define CAN_F10R2_FB15 0x00008000U
2591 #define CAN_F10R2_FB16 0x00010000U
2592 #define CAN_F10R2_FB17 0x00020000U
2593 #define CAN_F10R2_FB18 0x00040000U
2594 #define CAN_F10R2_FB19 0x00080000U
2595 #define CAN_F10R2_FB20 0x00100000U
2596 #define CAN_F10R2_FB21 0x00200000U
2597 #define CAN_F10R2_FB22 0x00400000U
2598 #define CAN_F10R2_FB23 0x00800000U
2599 #define CAN_F10R2_FB24 0x01000000U
2600 #define CAN_F10R2_FB25 0x02000000U
2601 #define CAN_F10R2_FB26 0x04000000U
2602 #define CAN_F10R2_FB27 0x08000000U
2603 #define CAN_F10R2_FB28 0x10000000U
2604 #define CAN_F10R2_FB29 0x20000000U
2605 #define CAN_F10R2_FB30 0x40000000U
2606 #define CAN_F10R2_FB31 0x80000000U
2608 /******************* Bit definition for CAN_F11R2 register ******************/
2609 #define CAN_F11R2_FB0 0x00000001U
2610 #define CAN_F11R2_FB1 0x00000002U
2611 #define CAN_F11R2_FB2 0x00000004U
2612 #define CAN_F11R2_FB3 0x00000008U
2613 #define CAN_F11R2_FB4 0x00000010U
2614 #define CAN_F11R2_FB5 0x00000020U
2615 #define CAN_F11R2_FB6 0x00000040U
2616 #define CAN_F11R2_FB7 0x00000080U
2617 #define CAN_F11R2_FB8 0x00000100U
2618 #define CAN_F11R2_FB9 0x00000200U
2619 #define CAN_F11R2_FB10 0x00000400U
2620 #define CAN_F11R2_FB11 0x00000800U
2621 #define CAN_F11R2_FB12 0x00001000U
2622 #define CAN_F11R2_FB13 0x00002000U
2623 #define CAN_F11R2_FB14 0x00004000U
2624 #define CAN_F11R2_FB15 0x00008000U
2625 #define CAN_F11R2_FB16 0x00010000U
2626 #define CAN_F11R2_FB17 0x00020000U
2627 #define CAN_F11R2_FB18 0x00040000U
2628 #define CAN_F11R2_FB19 0x00080000U
2629 #define CAN_F11R2_FB20 0x00100000U
2630 #define CAN_F11R2_FB21 0x00200000U
2631 #define CAN_F11R2_FB22 0x00400000U
2632 #define CAN_F11R2_FB23 0x00800000U
2633 #define CAN_F11R2_FB24 0x01000000U
2634 #define CAN_F11R2_FB25 0x02000000U
2635 #define CAN_F11R2_FB26 0x04000000U
2636 #define CAN_F11R2_FB27 0x08000000U
2637 #define CAN_F11R2_FB28 0x10000000U
2638 #define CAN_F11R2_FB29 0x20000000U
2639 #define CAN_F11R2_FB30 0x40000000U
2640 #define CAN_F11R2_FB31 0x80000000U
2642 /******************* Bit definition for CAN_F12R2 register ******************/
2643 #define CAN_F12R2_FB0 0x00000001U
2644 #define CAN_F12R2_FB1 0x00000002U
2645 #define CAN_F12R2_FB2 0x00000004U
2646 #define CAN_F12R2_FB3 0x00000008U
2647 #define CAN_F12R2_FB4 0x00000010U
2648 #define CAN_F12R2_FB5 0x00000020U
2649 #define CAN_F12R2_FB6 0x00000040U
2650 #define CAN_F12R2_FB7 0x00000080U
2651 #define CAN_F12R2_FB8 0x00000100U
2652 #define CAN_F12R2_FB9 0x00000200U
2653 #define CAN_F12R2_FB10 0x00000400U
2654 #define CAN_F12R2_FB11 0x00000800U
2655 #define CAN_F12R2_FB12 0x00001000U
2656 #define CAN_F12R2_FB13 0x00002000U
2657 #define CAN_F12R2_FB14 0x00004000U
2658 #define CAN_F12R2_FB15 0x00008000U
2659 #define CAN_F12R2_FB16 0x00010000U
2660 #define CAN_F12R2_FB17 0x00020000U
2661 #define CAN_F12R2_FB18 0x00040000U
2662 #define CAN_F12R2_FB19 0x00080000U
2663 #define CAN_F12R2_FB20 0x00100000U
2664 #define CAN_F12R2_FB21 0x00200000U
2665 #define CAN_F12R2_FB22 0x00400000U
2666 #define CAN_F12R2_FB23 0x00800000U
2667 #define CAN_F12R2_FB24 0x01000000U
2668 #define CAN_F12R2_FB25 0x02000000U
2669 #define CAN_F12R2_FB26 0x04000000U
2670 #define CAN_F12R2_FB27 0x08000000U
2671 #define CAN_F12R2_FB28 0x10000000U
2672 #define CAN_F12R2_FB29 0x20000000U
2673 #define CAN_F12R2_FB30 0x40000000U
2674 #define CAN_F12R2_FB31 0x80000000U
2676 /******************* Bit definition for CAN_F13R2 register ******************/
2677 #define CAN_F13R2_FB0 0x00000001U
2678 #define CAN_F13R2_FB1 0x00000002U
2679 #define CAN_F13R2_FB2 0x00000004U
2680 #define CAN_F13R2_FB3 0x00000008U
2681 #define CAN_F13R2_FB4 0x00000010U
2682 #define CAN_F13R2_FB5 0x00000020U
2683 #define CAN_F13R2_FB6 0x00000040U
2684 #define CAN_F13R2_FB7 0x00000080U
2685 #define CAN_F13R2_FB8 0x00000100U
2686 #define CAN_F13R2_FB9 0x00000200U
2687 #define CAN_F13R2_FB10 0x00000400U
2688 #define CAN_F13R2_FB11 0x00000800U
2689 #define CAN_F13R2_FB12 0x00001000U
2690 #define CAN_F13R2_FB13 0x00002000U
2691 #define CAN_F13R2_FB14 0x00004000U
2692 #define CAN_F13R2_FB15 0x00008000U
2693 #define CAN_F13R2_FB16 0x00010000U
2694 #define CAN_F13R2_FB17 0x00020000U
2695 #define CAN_F13R2_FB18 0x00040000U
2696 #define CAN_F13R2_FB19 0x00080000U
2697 #define CAN_F13R2_FB20 0x00100000U
2698 #define CAN_F13R2_FB21 0x00200000U
2699 #define CAN_F13R2_FB22 0x00400000U
2700 #define CAN_F13R2_FB23 0x00800000U
2701 #define CAN_F13R2_FB24 0x01000000U
2702 #define CAN_F13R2_FB25 0x02000000U
2703 #define CAN_F13R2_FB26 0x04000000U
2704 #define CAN_F13R2_FB27 0x08000000U
2705 #define CAN_F13R2_FB28 0x10000000U
2706 #define CAN_F13R2_FB29 0x20000000U
2707 #define CAN_F13R2_FB30 0x40000000U
2708 #define CAN_F13R2_FB31 0x80000000U
2710 /******************************************************************************/
2711 /* */
2712 /* CRC calculation unit */
2713 /* */
2714 /******************************************************************************/
2715 /******************* Bit definition for CRC_DR register *********************/
2716 #define CRC_DR_DR 0xFFFFFFFFU
2719 /******************* Bit definition for CRC_IDR register ********************/
2720 #define CRC_IDR_IDR 0xFFU
2723 /******************** Bit definition for CRC_CR register ********************/
2724 #define CRC_CR_RESET 0x01U
2726 /******************************************************************************/
2727 /* */
2728 /* Debug MCU */
2729 /* */
2730 /******************************************************************************/
2731 
2732 /******************************************************************************/
2733 /* */
2734 /* Digital Filter for Sigma Delta Modulators */
2735 /* */
2736 /******************************************************************************/
2737 
2738 /**************** DFSDM channel configuration registers ********************/
2739 
2740 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
2741 #define DFSDM_CHCFGR1_DFSDMEN 0x80000000U
2742 #define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U
2743 #define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U
2744 #define DFSDM_CHCFGR1_DATPACK 0x0000C000U
2745 #define DFSDM_CHCFGR1_DATPACK_1 0x00008000U
2746 #define DFSDM_CHCFGR1_DATPACK_0 0x00004000U
2747 #define DFSDM_CHCFGR1_DATMPX 0x00003000U
2748 #define DFSDM_CHCFGR1_DATMPX_1 0x00002000U
2749 #define DFSDM_CHCFGR1_DATMPX_0 0x00001000U
2750 #define DFSDM_CHCFGR1_CHINSEL 0x00000100U
2751 #define DFSDM_CHCFGR1_CHEN 0x00000080U
2752 #define DFSDM_CHCFGR1_CKABEN 0x00000040U
2753 #define DFSDM_CHCFGR1_SCDEN 0x00000020U
2754 #define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU
2755 #define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U
2756 #define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U
2757 #define DFSDM_CHCFGR1_SITP 0x00000003U
2758 #define DFSDM_CHCFGR1_SITP_1 0x00000002U
2759 #define DFSDM_CHCFGR1_SITP_0 0x00000001U
2761 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
2762 #define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U
2763 #define DFSDM_CHCFGR2_DTRBS 0x000000F8U
2765 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
2766 #define DFSDM_CHAWSCDR_AWFORD 0x00C00000U
2767 #define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U
2768 #define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U
2769 #define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U
2770 #define DFSDM_CHAWSCDR_BKSCD 0x0000F000U
2771 #define DFSDM_CHAWSCDR_SCDT 0x000000FFU
2773 /**************** Bit definition for DFSDM_CHWDATR register *******************/
2774 #define DFSDM_CHWDATR_WDATA 0x0000FFFFU
2776 /**************** Bit definition for DFSDM_CHDATINR register *****************/
2777 #define DFSDM_CHDATINR_INDAT0 0x0000FFFFU
2778 #define DFSDM_CHDATINR_INDAT1 0xFFFF0000U
2780 /************************ DFSDM module registers ****************************/
2781 
2782 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
2783 #define DFSDM_FLTCR1_AWFSEL 0x40000000U
2784 #define DFSDM_FLTCR1_FAST 0x20000000U
2785 #define DFSDM_FLTCR1_RCH 0x07000000U
2786 #define DFSDM_FLTCR1_RDMAEN 0x00200000U
2787 #define DFSDM_FLTCR1_RSYNC 0x00080000U
2788 #define DFSDM_FLTCR1_RCONT 0x00040000U
2789 #define DFSDM_FLTCR1_RSWSTART 0x00020000U
2790 #define DFSDM_FLTCR1_JEXTEN 0x00006000U
2791 #define DFSDM_FLTCR1_JEXTEN_1 0x00004000U
2792 #define DFSDM_FLTCR1_JEXTEN_0 0x00002000U
2793 #define DFSDM_FLTCR1_JEXTSEL 0x00000700U
2794 #define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U
2795 #define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U
2796 #define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U
2797 #define DFSDM_FLTCR1_JDMAEN 0x00000020U
2798 #define DFSDM_FLTCR1_JSCAN 0x00000010U
2799 #define DFSDM_FLTCR1_JSYNC 0x00000008U
2800 #define DFSDM_FLTCR1_JSWSTART 0x00000002U
2801 #define DFSDM_FLTCR1_DFEN 0x00000001U
2803 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
2804 #define DFSDM_FLTCR2_AWDCH 0x000F0000U
2805 #define DFSDM_FLTCR2_EXCH 0x00000F00U
2806 #define DFSDM_FLTCR2_CKABIE 0x00000040U
2807 #define DFSDM_FLTCR2_SCDIE 0x00000020U
2808 #define DFSDM_FLTCR2_AWDIE 0x00000010U
2809 #define DFSDM_FLTCR2_ROVRIE 0x00000008U
2810 #define DFSDM_FLTCR2_JOVRIE 0x00000004U
2811 #define DFSDM_FLTCR2_REOCIE 0x00000002U
2812 #define DFSDM_FLTCR2_JEOCIE 0x00000001U
2814 /***************** Bit definition for DFSDM_FLTISR register *******************/
2815 #define DFSDM_FLTISR_SCDF 0x0F000000U
2816 #define DFSDM_FLTISR_CKABF 0x000F0000U
2817 #define DFSDM_FLTISR_RCIP 0x00004000U
2818 #define DFSDM_FLTISR_JCIP 0x00002000U
2819 #define DFSDM_FLTISR_AWDF 0x00000010U
2820 #define DFSDM_FLTISR_ROVRF 0x00000008U
2821 #define DFSDM_FLTISR_JOVRF 0x00000004U
2822 #define DFSDM_FLTISR_REOCF 0x00000002U
2823 #define DFSDM_FLTISR_JEOCF 0x00000001U
2825 /***************** Bit definition for DFSDM_FLTICR register *******************/
2826 #define DFSDM_FLTICR_CLRSCSDF 0x0F000000U
2827 #define DFSDM_FLTICR_CLRCKABF 0x000F0000U
2828 #define DFSDM_FLTICR_CLRROVRF 0x00000008U
2829 #define DFSDM_FLTICR_CLRJOVRF 0x00000004U
2831 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
2832 #define DFSDM_FLTJCHGR_JCHG 0x0000000FU
2834 /***************** Bit definition for DFSDM_FLTFCR register *******************/
2835 #define DFSDM_FLTFCR_FORD 0xE0000000U
2836 #define DFSDM_FLTFCR_FORD_2 0x80000000U
2837 #define DFSDM_FLTFCR_FORD_1 0x40000000U
2838 #define DFSDM_FLTFCR_FORD_0 0x20000000U
2839 #define DFSDM_FLTFCR_FOSR 0x03FF0000U
2840 #define DFSDM_FLTFCR_IOSR 0x000000FFU
2842 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
2843 #define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U
2844 #define DFSDM_FLTJDATAR_JDATACH 0x00000007U
2846 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
2847 #define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U
2848 #define DFSDM_FLTRDATAR_RPEND 0x00000010U
2849 #define DFSDM_FLTRDATAR_RDATACH 0x00000007U
2851 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
2852 #define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U
2853 #define DFSDM_FLTAWHTR_BKAWH 0x0000000FU
2855 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
2856 #define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U
2857 #define DFSDM_FLTAWLTR_BKAWL 0x0000000FU
2859 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
2860 #define DFSDM_FLTAWSR_AWHTF 0x00000F00U
2861 #define DFSDM_FLTAWSR_AWLTF 0x0000000FU
2863 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
2864 #define DFSDM_FLTAWCFR_CLRAWHTF 0x00000F00U
2865 #define DFSDM_FLTAWCFR_CLRAWLTF 0x0000000FU
2867 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
2868 #define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U
2869 #define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U
2871 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
2872 #define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U
2873 #define DFSDM_FLTEXMIN_EXMINCH 0x00000007U
2875 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
2876 #define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U
2878 /******************************************************************************/
2879 /* */
2880 /* DMA Controller */
2881 /* */
2882 /******************************************************************************/
2883 /******************** Bits definition for DMA_SxCR register *****************/
2884 #define DMA_SxCR_CHSEL 0x0E000000U
2885 #define DMA_SxCR_CHSEL_0 0x02000000U
2886 #define DMA_SxCR_CHSEL_1 0x04000000U
2887 #define DMA_SxCR_CHSEL_2 0x08000000U
2888 #define DMA_SxCR_MBURST 0x01800000U
2889 #define DMA_SxCR_MBURST_0 0x00800000U
2890 #define DMA_SxCR_MBURST_1 0x01000000U
2891 #define DMA_SxCR_PBURST 0x00600000U
2892 #define DMA_SxCR_PBURST_0 0x00200000U
2893 #define DMA_SxCR_PBURST_1 0x00400000U
2894 #define DMA_SxCR_CT 0x00080000U
2895 #define DMA_SxCR_DBM 0x00040000U
2896 #define DMA_SxCR_PL 0x00030000U
2897 #define DMA_SxCR_PL_0 0x00010000U
2898 #define DMA_SxCR_PL_1 0x00020000U
2899 #define DMA_SxCR_PINCOS 0x00008000U
2900 #define DMA_SxCR_MSIZE 0x00006000U
2901 #define DMA_SxCR_MSIZE_0 0x00002000U
2902 #define DMA_SxCR_MSIZE_1 0x00004000U
2903 #define DMA_SxCR_PSIZE 0x00001800U
2904 #define DMA_SxCR_PSIZE_0 0x00000800U
2905 #define DMA_SxCR_PSIZE_1 0x00001000U
2906 #define DMA_SxCR_MINC 0x00000400U
2907 #define DMA_SxCR_PINC 0x00000200U
2908 #define DMA_SxCR_CIRC 0x00000100U
2909 #define DMA_SxCR_DIR 0x000000C0U
2910 #define DMA_SxCR_DIR_0 0x00000040U
2911 #define DMA_SxCR_DIR_1 0x00000080U
2912 #define DMA_SxCR_PFCTRL 0x00000020U
2913 #define DMA_SxCR_TCIE 0x00000010U
2914 #define DMA_SxCR_HTIE 0x00000008U
2915 #define DMA_SxCR_TEIE 0x00000004U
2916 #define DMA_SxCR_DMEIE 0x00000002U
2917 #define DMA_SxCR_EN 0x00000001U
2918 
2919 /* Legacy defines */
2920 #define DMA_SxCR_ACK 0x00100000U
2921 
2922 /******************** Bits definition for DMA_SxCNDTR register **************/
2923 #define DMA_SxNDT 0x0000FFFFU
2924 #define DMA_SxNDT_0 0x00000001U
2925 #define DMA_SxNDT_1 0x00000002U
2926 #define DMA_SxNDT_2 0x00000004U
2927 #define DMA_SxNDT_3 0x00000008U
2928 #define DMA_SxNDT_4 0x00000010U
2929 #define DMA_SxNDT_5 0x00000020U
2930 #define DMA_SxNDT_6 0x00000040U
2931 #define DMA_SxNDT_7 0x00000080U
2932 #define DMA_SxNDT_8 0x00000100U
2933 #define DMA_SxNDT_9 0x00000200U
2934 #define DMA_SxNDT_10 0x00000400U
2935 #define DMA_SxNDT_11 0x00000800U
2936 #define DMA_SxNDT_12 0x00001000U
2937 #define DMA_SxNDT_13 0x00002000U
2938 #define DMA_SxNDT_14 0x00004000U
2939 #define DMA_SxNDT_15 0x00008000U
2940 
2941 /******************** Bits definition for DMA_SxFCR register ****************/
2942 #define DMA_SxFCR_FEIE 0x00000080U
2943 #define DMA_SxFCR_FS 0x00000038U
2944 #define DMA_SxFCR_FS_0 0x00000008U
2945 #define DMA_SxFCR_FS_1 0x00000010U
2946 #define DMA_SxFCR_FS_2 0x00000020U
2947 #define DMA_SxFCR_DMDIS 0x00000004U
2948 #define DMA_SxFCR_FTH 0x00000003U
2949 #define DMA_SxFCR_FTH_0 0x00000001U
2950 #define DMA_SxFCR_FTH_1 0x00000002U
2951 
2952 /******************** Bits definition for DMA_LISR register *****************/
2953 #define DMA_LISR_TCIF3 0x08000000U
2954 #define DMA_LISR_HTIF3 0x04000000U
2955 #define DMA_LISR_TEIF3 0x02000000U
2956 #define DMA_LISR_DMEIF3 0x01000000U
2957 #define DMA_LISR_FEIF3 0x00400000U
2958 #define DMA_LISR_TCIF2 0x00200000U
2959 #define DMA_LISR_HTIF2 0x00100000U
2960 #define DMA_LISR_TEIF2 0x00080000U
2961 #define DMA_LISR_DMEIF2 0x00040000U
2962 #define DMA_LISR_FEIF2 0x00010000U
2963 #define DMA_LISR_TCIF1 0x00000800U
2964 #define DMA_LISR_HTIF1 0x00000400U
2965 #define DMA_LISR_TEIF1 0x00000200U
2966 #define DMA_LISR_DMEIF1 0x00000100U
2967 #define DMA_LISR_FEIF1 0x00000040U
2968 #define DMA_LISR_TCIF0 0x00000020U
2969 #define DMA_LISR_HTIF0 0x00000010U
2970 #define DMA_LISR_TEIF0 0x00000008U
2971 #define DMA_LISR_DMEIF0 0x00000004U
2972 #define DMA_LISR_FEIF0 0x00000001U
2973 
2974 /******************** Bits definition for DMA_HISR register *****************/
2975 #define DMA_HISR_TCIF7 0x08000000U
2976 #define DMA_HISR_HTIF7 0x04000000U
2977 #define DMA_HISR_TEIF7 0x02000000U
2978 #define DMA_HISR_DMEIF7 0x01000000U
2979 #define DMA_HISR_FEIF7 0x00400000U
2980 #define DMA_HISR_TCIF6 0x00200000U
2981 #define DMA_HISR_HTIF6 0x00100000U
2982 #define DMA_HISR_TEIF6 0x00080000U
2983 #define DMA_HISR_DMEIF6 0x00040000U
2984 #define DMA_HISR_FEIF6 0x00010000U
2985 #define DMA_HISR_TCIF5 0x00000800U
2986 #define DMA_HISR_HTIF5 0x00000400U
2987 #define DMA_HISR_TEIF5 0x00000200U
2988 #define DMA_HISR_DMEIF5 0x00000100U
2989 #define DMA_HISR_FEIF5 0x00000040U
2990 #define DMA_HISR_TCIF4 0x00000020U
2991 #define DMA_HISR_HTIF4 0x00000010U
2992 #define DMA_HISR_TEIF4 0x00000008U
2993 #define DMA_HISR_DMEIF4 0x00000004U
2994 #define DMA_HISR_FEIF4 0x00000001U
2995 
2996 /******************** Bits definition for DMA_LIFCR register ****************/
2997 #define DMA_LIFCR_CTCIF3 0x08000000U
2998 #define DMA_LIFCR_CHTIF3 0x04000000U
2999 #define DMA_LIFCR_CTEIF3 0x02000000U
3000 #define DMA_LIFCR_CDMEIF3 0x01000000U
3001 #define DMA_LIFCR_CFEIF3 0x00400000U
3002 #define DMA_LIFCR_CTCIF2 0x00200000U
3003 #define DMA_LIFCR_CHTIF2 0x00100000U
3004 #define DMA_LIFCR_CTEIF2 0x00080000U
3005 #define DMA_LIFCR_CDMEIF2 0x00040000U
3006 #define DMA_LIFCR_CFEIF2 0x00010000U
3007 #define DMA_LIFCR_CTCIF1 0x00000800U
3008 #define DMA_LIFCR_CHTIF1 0x00000400U
3009 #define DMA_LIFCR_CTEIF1 0x00000200U
3010 #define DMA_LIFCR_CDMEIF1 0x00000100U
3011 #define DMA_LIFCR_CFEIF1 0x00000040U
3012 #define DMA_LIFCR_CTCIF0 0x00000020U
3013 #define DMA_LIFCR_CHTIF0 0x00000010U
3014 #define DMA_LIFCR_CTEIF0 0x00000008U
3015 #define DMA_LIFCR_CDMEIF0 0x00000004U
3016 #define DMA_LIFCR_CFEIF0 0x00000001U
3017 
3018 /******************** Bits definition for DMA_HIFCR register ****************/
3019 #define DMA_HIFCR_CTCIF7 0x08000000U
3020 #define DMA_HIFCR_CHTIF7 0x04000000U
3021 #define DMA_HIFCR_CTEIF7 0x02000000U
3022 #define DMA_HIFCR_CDMEIF7 0x01000000U
3023 #define DMA_HIFCR_CFEIF7 0x00400000U
3024 #define DMA_HIFCR_CTCIF6 0x00200000U
3025 #define DMA_HIFCR_CHTIF6 0x00100000U
3026 #define DMA_HIFCR_CTEIF6 0x00080000U
3027 #define DMA_HIFCR_CDMEIF6 0x00040000U
3028 #define DMA_HIFCR_CFEIF6 0x00010000U
3029 #define DMA_HIFCR_CTCIF5 0x00000800U
3030 #define DMA_HIFCR_CHTIF5 0x00000400U
3031 #define DMA_HIFCR_CTEIF5 0x00000200U
3032 #define DMA_HIFCR_CDMEIF5 0x00000100U
3033 #define DMA_HIFCR_CFEIF5 0x00000040U
3034 #define DMA_HIFCR_CTCIF4 0x00000020U
3035 #define DMA_HIFCR_CHTIF4 0x00000010U
3036 #define DMA_HIFCR_CTEIF4 0x00000008U
3037 #define DMA_HIFCR_CDMEIF4 0x00000004U
3038 #define DMA_HIFCR_CFEIF4 0x00000001U
3039 
3040 
3041 /******************************************************************************/
3042 /* */
3043 /* External Interrupt/Event Controller */
3044 /* */
3045 /******************************************************************************/
3046 /******************* Bit definition for EXTI_IMR register *******************/
3047 #define EXTI_IMR_MR0 0x00000001U
3048 #define EXTI_IMR_MR1 0x00000002U
3049 #define EXTI_IMR_MR2 0x00000004U
3050 #define EXTI_IMR_MR3 0x00000008U
3051 #define EXTI_IMR_MR4 0x00000010U
3052 #define EXTI_IMR_MR5 0x00000020U
3053 #define EXTI_IMR_MR6 0x00000040U
3054 #define EXTI_IMR_MR7 0x00000080U
3055 #define EXTI_IMR_MR8 0x00000100U
3056 #define EXTI_IMR_MR9 0x00000200U
3057 #define EXTI_IMR_MR10 0x00000400U
3058 #define EXTI_IMR_MR11 0x00000800U
3059 #define EXTI_IMR_MR12 0x00001000U
3060 #define EXTI_IMR_MR13 0x00002000U
3061 #define EXTI_IMR_MR14 0x00004000U
3062 #define EXTI_IMR_MR15 0x00008000U
3063 #define EXTI_IMR_MR16 0x00010000U
3064 #define EXTI_IMR_MR17 0x00020000U
3065 #define EXTI_IMR_MR18 0x00040000U
3066 #define EXTI_IMR_MR19 0x00080000U
3067 #define EXTI_IMR_MR20 0x00100000U
3068 #define EXTI_IMR_MR21 0x00200000U
3069 #define EXTI_IMR_MR22 0x00400000U
3071 /******************* Bit definition for EXTI_EMR register *******************/
3072 #define EXTI_EMR_MR0 0x00000001U
3073 #define EXTI_EMR_MR1 0x00000002U
3074 #define EXTI_EMR_MR2 0x00000004U
3075 #define EXTI_EMR_MR3 0x00000008U
3076 #define EXTI_EMR_MR4 0x00000010U
3077 #define EXTI_EMR_MR5 0x00000020U
3078 #define EXTI_EMR_MR6 0x00000040U
3079 #define EXTI_EMR_MR7 0x00000080U
3080 #define EXTI_EMR_MR8 0x00000100U
3081 #define EXTI_EMR_MR9 0x00000200U
3082 #define EXTI_EMR_MR10 0x00000400U
3083 #define EXTI_EMR_MR11 0x00000800U
3084 #define EXTI_EMR_MR12 0x00001000U
3085 #define EXTI_EMR_MR13 0x00002000U
3086 #define EXTI_EMR_MR14 0x00004000U
3087 #define EXTI_EMR_MR15 0x00008000U
3088 #define EXTI_EMR_MR16 0x00010000U
3089 #define EXTI_EMR_MR17 0x00020000U
3090 #define EXTI_EMR_MR18 0x00040000U
3091 #define EXTI_EMR_MR19 0x00080000U
3092 #define EXTI_EMR_MR20 0x00100000U
3093 #define EXTI_EMR_MR21 0x00200000U
3094 #define EXTI_EMR_MR22 0x00400000U
3096 /****************** Bit definition for EXTI_RTSR register *******************/
3097 #define EXTI_RTSR_TR0 0x00000001U
3098 #define EXTI_RTSR_TR1 0x00000002U
3099 #define EXTI_RTSR_TR2 0x00000004U
3100 #define EXTI_RTSR_TR3 0x00000008U
3101 #define EXTI_RTSR_TR4 0x00000010U
3102 #define EXTI_RTSR_TR5 0x00000020U
3103 #define EXTI_RTSR_TR6 0x00000040U
3104 #define EXTI_RTSR_TR7 0x00000080U
3105 #define EXTI_RTSR_TR8 0x00000100U
3106 #define EXTI_RTSR_TR9 0x00000200U
3107 #define EXTI_RTSR_TR10 0x00000400U
3108 #define EXTI_RTSR_TR11 0x00000800U
3109 #define EXTI_RTSR_TR12 0x00001000U
3110 #define EXTI_RTSR_TR13 0x00002000U
3111 #define EXTI_RTSR_TR14 0x00004000U
3112 #define EXTI_RTSR_TR15 0x00008000U
3113 #define EXTI_RTSR_TR16 0x00010000U
3114 #define EXTI_RTSR_TR17 0x00020000U
3115 #define EXTI_RTSR_TR18 0x00040000U
3116 #define EXTI_RTSR_TR19 0x00080000U
3117 #define EXTI_RTSR_TR20 0x00100000U
3118 #define EXTI_RTSR_TR21 0x00200000U
3119 #define EXTI_RTSR_TR22 0x00400000U
3121 /****************** Bit definition for EXTI_FTSR register *******************/
3122 #define EXTI_FTSR_TR0 0x00000001U
3123 #define EXTI_FTSR_TR1 0x00000002U
3124 #define EXTI_FTSR_TR2 0x00000004U
3125 #define EXTI_FTSR_TR3 0x00000008U
3126 #define EXTI_FTSR_TR4 0x00000010U
3127 #define EXTI_FTSR_TR5 0x00000020U
3128 #define EXTI_FTSR_TR6 0x00000040U
3129 #define EXTI_FTSR_TR7 0x00000080U
3130 #define EXTI_FTSR_TR8 0x00000100U
3131 #define EXTI_FTSR_TR9 0x00000200U
3132 #define EXTI_FTSR_TR10 0x00000400U
3133 #define EXTI_FTSR_TR11 0x00000800U
3134 #define EXTI_FTSR_TR12 0x00001000U
3135 #define EXTI_FTSR_TR13 0x00002000U
3136 #define EXTI_FTSR_TR14 0x00004000U
3137 #define EXTI_FTSR_TR15 0x00008000U
3138 #define EXTI_FTSR_TR16 0x00010000U
3139 #define EXTI_FTSR_TR17 0x00020000U
3140 #define EXTI_FTSR_TR18 0x00040000U
3141 #define EXTI_FTSR_TR19 0x00080000U
3142 #define EXTI_FTSR_TR20 0x00100000U
3143 #define EXTI_FTSR_TR21 0x00200000U
3144 #define EXTI_FTSR_TR22 0x00400000U
3146 /****************** Bit definition for EXTI_SWIER register ******************/
3147 #define EXTI_SWIER_SWIER0 0x00000001U
3148 #define EXTI_SWIER_SWIER1 0x00000002U
3149 #define EXTI_SWIER_SWIER2 0x00000004U
3150 #define EXTI_SWIER_SWIER3 0x00000008U
3151 #define EXTI_SWIER_SWIER4 0x00000010U
3152 #define EXTI_SWIER_SWIER5 0x00000020U
3153 #define EXTI_SWIER_SWIER6 0x00000040U
3154 #define EXTI_SWIER_SWIER7 0x00000080U
3155 #define EXTI_SWIER_SWIER8 0x00000100U
3156 #define EXTI_SWIER_SWIER9 0x00000200U
3157 #define EXTI_SWIER_SWIER10 0x00000400U
3158 #define EXTI_SWIER_SWIER11 0x00000800U
3159 #define EXTI_SWIER_SWIER12 0x00001000U
3160 #define EXTI_SWIER_SWIER13 0x00002000U
3161 #define EXTI_SWIER_SWIER14 0x00004000U
3162 #define EXTI_SWIER_SWIER15 0x00008000U
3163 #define EXTI_SWIER_SWIER16 0x00010000U
3164 #define EXTI_SWIER_SWIER17 0x00020000U
3165 #define EXTI_SWIER_SWIER18 0x00040000U
3166 #define EXTI_SWIER_SWIER19 0x00080000U
3167 #define EXTI_SWIER_SWIER20 0x00100000U
3168 #define EXTI_SWIER_SWIER21 0x00200000U
3169 #define EXTI_SWIER_SWIER22 0x00400000U
3171 /******************* Bit definition for EXTI_PR register ********************/
3172 #define EXTI_PR_PR0 0x00000001U
3173 #define EXTI_PR_PR1 0x00000002U
3174 #define EXTI_PR_PR2 0x00000004U
3175 #define EXTI_PR_PR3 0x00000008U
3176 #define EXTI_PR_PR4 0x00000010U
3177 #define EXTI_PR_PR5 0x00000020U
3178 #define EXTI_PR_PR6 0x00000040U
3179 #define EXTI_PR_PR7 0x00000080U
3180 #define EXTI_PR_PR8 0x00000100U
3181 #define EXTI_PR_PR9 0x00000200U
3182 #define EXTI_PR_PR10 0x00000400U
3183 #define EXTI_PR_PR11 0x00000800U
3184 #define EXTI_PR_PR12 0x00001000U
3185 #define EXTI_PR_PR13 0x00002000U
3186 #define EXTI_PR_PR14 0x00004000U
3187 #define EXTI_PR_PR15 0x00008000U
3188 #define EXTI_PR_PR16 0x00010000U
3189 #define EXTI_PR_PR17 0x00020000U
3190 #define EXTI_PR_PR18 0x00040000U
3191 #define EXTI_PR_PR19 0x00080000U
3192 #define EXTI_PR_PR20 0x00100000U
3193 #define EXTI_PR_PR21 0x00200000U
3194 #define EXTI_PR_PR22 0x00400000U
3196 /******************************************************************************/
3197 /* */
3198 /* FLASH */
3199 /* */
3200 /******************************************************************************/
3201 /******************* Bits definition for FLASH_ACR register *****************/
3202 #define FLASH_ACR_LATENCY 0x0000000FU
3203 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3204 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3205 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3206 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3207 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3208 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3209 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3210 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3211 
3212 #define FLASH_ACR_PRFTEN 0x00000100U
3213 #define FLASH_ACR_ICEN 0x00000200U
3214 #define FLASH_ACR_DCEN 0x00000400U
3215 #define FLASH_ACR_ICRST 0x00000800U
3216 #define FLASH_ACR_DCRST 0x00001000U
3217 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3218 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3219 
3220 /******************* Bits definition for FLASH_SR register ******************/
3221 #define FLASH_SR_EOP 0x00000001U
3222 #define FLASH_SR_SOP 0x00000002U
3223 #define FLASH_SR_WRPERR 0x00000010U
3224 #define FLASH_SR_PGAERR 0x00000020U
3225 #define FLASH_SR_PGPERR 0x00000040U
3226 #define FLASH_SR_PGSERR 0x00000080U
3227 #define FLASH_SR_BSY 0x00010000U
3228 
3229 /******************* Bits definition for FLASH_CR register ******************/
3230 #define FLASH_CR_PG 0x00000001U
3231 #define FLASH_CR_SER 0x00000002U
3232 #define FLASH_CR_MER 0x00000004U
3233 #define FLASH_CR_SNB 0x000000F8U
3234 #define FLASH_CR_SNB_0 0x00000008U
3235 #define FLASH_CR_SNB_1 0x00000010U
3236 #define FLASH_CR_SNB_2 0x00000020U
3237 #define FLASH_CR_SNB_3 0x00000040U
3238 #define FLASH_CR_SNB_4 0x00000080U
3239 #define FLASH_CR_PSIZE 0x00000300U
3240 #define FLASH_CR_PSIZE_0 0x00000100U
3241 #define FLASH_CR_PSIZE_1 0x00000200U
3242 #define FLASH_CR_STRT 0x00010000U
3243 #define FLASH_CR_EOPIE 0x01000000U
3244 #define FLASH_CR_LOCK 0x80000000U
3245 
3246 /******************* Bits definition for FLASH_OPTCR register ***************/
3247 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3248 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3249 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3250 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3251 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3252 
3253 #define FLASH_OPTCR_WDG_SW 0x00000020U
3254 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3255 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3256 #define FLASH_OPTCR_RDP 0x0000FF00U
3257 #define FLASH_OPTCR_RDP_0 0x00000100U
3258 #define FLASH_OPTCR_RDP_1 0x00000200U
3259 #define FLASH_OPTCR_RDP_2 0x00000400U
3260 #define FLASH_OPTCR_RDP_3 0x00000800U
3261 #define FLASH_OPTCR_RDP_4 0x00001000U
3262 #define FLASH_OPTCR_RDP_5 0x00002000U
3263 #define FLASH_OPTCR_RDP_6 0x00004000U
3264 #define FLASH_OPTCR_RDP_7 0x00008000U
3265 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3266 #define FLASH_OPTCR_nWRP_0 0x00010000U
3267 #define FLASH_OPTCR_nWRP_1 0x00020000U
3268 #define FLASH_OPTCR_nWRP_2 0x00040000U
3269 #define FLASH_OPTCR_nWRP_3 0x00080000U
3270 #define FLASH_OPTCR_nWRP_4 0x00100000U
3271 #define FLASH_OPTCR_nWRP_5 0x00200000U
3272 #define FLASH_OPTCR_nWRP_6 0x00400000U
3273 #define FLASH_OPTCR_nWRP_7 0x00800000U
3274 #define FLASH_OPTCR_nWRP_8 0x01000000U
3275 #define FLASH_OPTCR_nWRP_9 0x02000000U
3276 #define FLASH_OPTCR_nWRP_10 0x04000000U
3277 #define FLASH_OPTCR_nWRP_11 0x08000000U
3278 
3279 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3280 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3281 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3282 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3283 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3284 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3285 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3286 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3287 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3288 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3289 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3290 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3291 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3292 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3293 
3294 /******************************************************************************/
3295 /* */
3296 /* General Purpose I/O */
3297 /* */
3298 /******************************************************************************/
3299 /****************** Bits definition for GPIO_MODER register *****************/
3300 #define GPIO_MODER_MODER0 0x00000003U
3301 #define GPIO_MODER_MODER0_0 0x00000001U
3302 #define GPIO_MODER_MODER0_1 0x00000002U
3303 
3304 #define GPIO_MODER_MODER1 0x0000000CU
3305 #define GPIO_MODER_MODER1_0 0x00000004U
3306 #define GPIO_MODER_MODER1_1 0x00000008U
3307 
3308 #define GPIO_MODER_MODER2 0x00000030U
3309 #define GPIO_MODER_MODER2_0 0x00000010U
3310 #define GPIO_MODER_MODER2_1 0x00000020U
3311 
3312 #define GPIO_MODER_MODER3 0x000000C0U
3313 #define GPIO_MODER_MODER3_0 0x00000040U
3314 #define GPIO_MODER_MODER3_1 0x00000080U
3315 
3316 #define GPIO_MODER_MODER4 0x00000300U
3317 #define GPIO_MODER_MODER4_0 0x00000100U
3318 #define GPIO_MODER_MODER4_1 0x00000200U
3319 
3320 #define GPIO_MODER_MODER5 0x00000C00U
3321 #define GPIO_MODER_MODER5_0 0x00000400U
3322 #define GPIO_MODER_MODER5_1 0x00000800U
3323 
3324 #define GPIO_MODER_MODER6 0x00003000U
3325 #define GPIO_MODER_MODER6_0 0x00001000U
3326 #define GPIO_MODER_MODER6_1 0x00002000U
3327 
3328 #define GPIO_MODER_MODER7 0x0000C000U
3329 #define GPIO_MODER_MODER7_0 0x00004000U
3330 #define GPIO_MODER_MODER7_1 0x00008000U
3331 
3332 #define GPIO_MODER_MODER8 0x00030000U
3333 #define GPIO_MODER_MODER8_0 0x00010000U
3334 #define GPIO_MODER_MODER8_1 0x00020000U
3335 
3336 #define GPIO_MODER_MODER9 0x000C0000U
3337 #define GPIO_MODER_MODER9_0 0x00040000U
3338 #define GPIO_MODER_MODER9_1 0x00080000U
3339 
3340 #define GPIO_MODER_MODER10 0x00300000U
3341 #define GPIO_MODER_MODER10_0 0x00100000U
3342 #define GPIO_MODER_MODER10_1 0x00200000U
3343 
3344 #define GPIO_MODER_MODER11 0x00C00000U
3345 #define GPIO_MODER_MODER11_0 0x00400000U
3346 #define GPIO_MODER_MODER11_1 0x00800000U
3347 
3348 #define GPIO_MODER_MODER12 0x03000000U
3349 #define GPIO_MODER_MODER12_0 0x01000000U
3350 #define GPIO_MODER_MODER12_1 0x02000000U
3351 
3352 #define GPIO_MODER_MODER13 0x0C000000U
3353 #define GPIO_MODER_MODER13_0 0x04000000U
3354 #define GPIO_MODER_MODER13_1 0x08000000U
3355 
3356 #define GPIO_MODER_MODER14 0x30000000U
3357 #define GPIO_MODER_MODER14_0 0x10000000U
3358 #define GPIO_MODER_MODER14_1 0x20000000U
3359 
3360 #define GPIO_MODER_MODER15 0xC0000000U
3361 #define GPIO_MODER_MODER15_0 0x40000000U
3362 #define GPIO_MODER_MODER15_1 0x80000000U
3363 
3364 /****************** Bits definition for GPIO_OTYPER register ****************/
3365 #define GPIO_OTYPER_OT_0 0x00000001U
3366 #define GPIO_OTYPER_OT_1 0x00000002U
3367 #define GPIO_OTYPER_OT_2 0x00000004U
3368 #define GPIO_OTYPER_OT_3 0x00000008U
3369 #define GPIO_OTYPER_OT_4 0x00000010U
3370 #define GPIO_OTYPER_OT_5 0x00000020U
3371 #define GPIO_OTYPER_OT_6 0x00000040U
3372 #define GPIO_OTYPER_OT_7 0x00000080U
3373 #define GPIO_OTYPER_OT_8 0x00000100U
3374 #define GPIO_OTYPER_OT_9 0x00000200U
3375 #define GPIO_OTYPER_OT_10 0x00000400U
3376 #define GPIO_OTYPER_OT_11 0x00000800U
3377 #define GPIO_OTYPER_OT_12 0x00001000U
3378 #define GPIO_OTYPER_OT_13 0x00002000U
3379 #define GPIO_OTYPER_OT_14 0x00004000U
3380 #define GPIO_OTYPER_OT_15 0x00008000U
3381 
3382 /****************** Bits definition for GPIO_OSPEEDR register ***************/
3383 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
3384 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
3385 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
3386 
3387 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
3388 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
3389 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
3390 
3391 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
3392 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
3393 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
3394 
3395 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
3396 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
3397 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
3398 
3399 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
3400 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
3401 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
3402 
3403 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
3404 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
3405 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
3406 
3407 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
3408 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
3409 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
3410 
3411 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
3412 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
3413 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
3414 
3415 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
3416 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
3417 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
3418 
3419 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
3420 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
3421 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
3422 
3423 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
3424 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
3425 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
3426 
3427 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
3428 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
3429 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
3430 
3431 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
3432 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
3433 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
3434 
3435 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
3436 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
3437 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
3438 
3439 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
3440 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
3441 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
3442 
3443 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
3444 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
3445 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
3446 
3447 /****************** Bits definition for GPIO_PUPDR register *****************/
3448 #define GPIO_PUPDR_PUPDR0 0x00000003U
3449 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
3450 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
3451 
3452 #define GPIO_PUPDR_PUPDR1 0x0000000CU
3453 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
3454 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
3455 
3456 #define GPIO_PUPDR_PUPDR2 0x00000030U
3457 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
3458 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
3459 
3460 #define GPIO_PUPDR_PUPDR3 0x000000C0U
3461 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
3462 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
3463 
3464 #define GPIO_PUPDR_PUPDR4 0x00000300U
3465 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
3466 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
3467 
3468 #define GPIO_PUPDR_PUPDR5 0x00000C00U
3469 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
3470 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
3471 
3472 #define GPIO_PUPDR_PUPDR6 0x00003000U
3473 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
3474 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
3475 
3476 #define GPIO_PUPDR_PUPDR7 0x0000C000U
3477 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
3478 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
3479 
3480 #define GPIO_PUPDR_PUPDR8 0x00030000U
3481 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
3482 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
3483 
3484 #define GPIO_PUPDR_PUPDR9 0x000C0000U
3485 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
3486 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
3487 
3488 #define GPIO_PUPDR_PUPDR10 0x00300000U
3489 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
3490 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
3491 
3492 #define GPIO_PUPDR_PUPDR11 0x00C00000U
3493 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
3494 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
3495 
3496 #define GPIO_PUPDR_PUPDR12 0x03000000U
3497 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
3498 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
3499 
3500 #define GPIO_PUPDR_PUPDR13 0x0C000000U
3501 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
3502 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
3503 
3504 #define GPIO_PUPDR_PUPDR14 0x30000000U
3505 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
3506 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
3507 
3508 #define GPIO_PUPDR_PUPDR15 0xC0000000U
3509 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
3510 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
3511 
3512 /****************** Bits definition for GPIO_IDR register *******************/
3513 #define GPIO_IDR_IDR_0 0x00000001U
3514 #define GPIO_IDR_IDR_1 0x00000002U
3515 #define GPIO_IDR_IDR_2 0x00000004U
3516 #define GPIO_IDR_IDR_3 0x00000008U
3517 #define GPIO_IDR_IDR_4 0x00000010U
3518 #define GPIO_IDR_IDR_5 0x00000020U
3519 #define GPIO_IDR_IDR_6 0x00000040U
3520 #define GPIO_IDR_IDR_7 0x00000080U
3521 #define GPIO_IDR_IDR_8 0x00000100U
3522 #define GPIO_IDR_IDR_9 0x00000200U
3523 #define GPIO_IDR_IDR_10 0x00000400U
3524 #define GPIO_IDR_IDR_11 0x00000800U
3525 #define GPIO_IDR_IDR_12 0x00001000U
3526 #define GPIO_IDR_IDR_13 0x00002000U
3527 #define GPIO_IDR_IDR_14 0x00004000U
3528 #define GPIO_IDR_IDR_15 0x00008000U
3529 
3530 /****************** Bits definition for GPIO_ODR register *******************/
3531 #define GPIO_ODR_ODR_0 0x00000001U
3532 #define GPIO_ODR_ODR_1 0x00000002U
3533 #define GPIO_ODR_ODR_2 0x00000004U
3534 #define GPIO_ODR_ODR_3 0x00000008U
3535 #define GPIO_ODR_ODR_4 0x00000010U
3536 #define GPIO_ODR_ODR_5 0x00000020U
3537 #define GPIO_ODR_ODR_6 0x00000040U
3538 #define GPIO_ODR_ODR_7 0x00000080U
3539 #define GPIO_ODR_ODR_8 0x00000100U
3540 #define GPIO_ODR_ODR_9 0x00000200U
3541 #define GPIO_ODR_ODR_10 0x00000400U
3542 #define GPIO_ODR_ODR_11 0x00000800U
3543 #define GPIO_ODR_ODR_12 0x00001000U
3544 #define GPIO_ODR_ODR_13 0x00002000U
3545 #define GPIO_ODR_ODR_14 0x00004000U
3546 #define GPIO_ODR_ODR_15 0x00008000U
3547 
3548 /****************** Bits definition for GPIO_BSRR register ******************/
3549 #define GPIO_BSRR_BS_0 0x00000001U
3550 #define GPIO_BSRR_BS_1 0x00000002U
3551 #define GPIO_BSRR_BS_2 0x00000004U
3552 #define GPIO_BSRR_BS_3 0x00000008U
3553 #define GPIO_BSRR_BS_4 0x00000010U
3554 #define GPIO_BSRR_BS_5 0x00000020U
3555 #define GPIO_BSRR_BS_6 0x00000040U
3556 #define GPIO_BSRR_BS_7 0x00000080U
3557 #define GPIO_BSRR_BS_8 0x00000100U
3558 #define GPIO_BSRR_BS_9 0x00000200U
3559 #define GPIO_BSRR_BS_10 0x00000400U
3560 #define GPIO_BSRR_BS_11 0x00000800U
3561 #define GPIO_BSRR_BS_12 0x00001000U
3562 #define GPIO_BSRR_BS_13 0x00002000U
3563 #define GPIO_BSRR_BS_14 0x00004000U
3564 #define GPIO_BSRR_BS_15 0x00008000U
3565 #define GPIO_BSRR_BR_0 0x00010000U
3566 #define GPIO_BSRR_BR_1 0x00020000U
3567 #define GPIO_BSRR_BR_2 0x00040000U
3568 #define GPIO_BSRR_BR_3 0x00080000U
3569 #define GPIO_BSRR_BR_4 0x00100000U
3570 #define GPIO_BSRR_BR_5 0x00200000U
3571 #define GPIO_BSRR_BR_6 0x00400000U
3572 #define GPIO_BSRR_BR_7 0x00800000U
3573 #define GPIO_BSRR_BR_8 0x01000000U
3574 #define GPIO_BSRR_BR_9 0x02000000U
3575 #define GPIO_BSRR_BR_10 0x04000000U
3576 #define GPIO_BSRR_BR_11 0x08000000U
3577 #define GPIO_BSRR_BR_12 0x10000000U
3578 #define GPIO_BSRR_BR_13 0x20000000U
3579 #define GPIO_BSRR_BR_14 0x40000000U
3580 #define GPIO_BSRR_BR_15 0x80000000U
3581 
3582 /****************** Bit definition for GPIO_LCKR register *********************/
3583 #define GPIO_LCKR_LCK0 0x00000001U
3584 #define GPIO_LCKR_LCK1 0x00000002U
3585 #define GPIO_LCKR_LCK2 0x00000004U
3586 #define GPIO_LCKR_LCK3 0x00000008U
3587 #define GPIO_LCKR_LCK4 0x00000010U
3588 #define GPIO_LCKR_LCK5 0x00000020U
3589 #define GPIO_LCKR_LCK6 0x00000040U
3590 #define GPIO_LCKR_LCK7 0x00000080U
3591 #define GPIO_LCKR_LCK8 0x00000100U
3592 #define GPIO_LCKR_LCK9 0x00000200U
3593 #define GPIO_LCKR_LCK10 0x00000400U
3594 #define GPIO_LCKR_LCK11 0x00000800U
3595 #define GPIO_LCKR_LCK12 0x00001000U
3596 #define GPIO_LCKR_LCK13 0x00002000U
3597 #define GPIO_LCKR_LCK14 0x00004000U
3598 #define GPIO_LCKR_LCK15 0x00008000U
3599 #define GPIO_LCKR_LCKK 0x00010000U
3600 
3601 /******************************************************************************/
3602 /* */
3603 /* Inter-integrated Circuit Interface */
3604 /* */
3605 /******************************************************************************/
3606 /******************* Bit definition for I2C_CR1 register ********************/
3607 #define I2C_CR1_PE 0x00000001U
3608 #define I2C_CR1_SMBUS 0x00000002U
3609 #define I2C_CR1_SMBTYPE 0x00000008U
3610 #define I2C_CR1_ENARP 0x00000010U
3611 #define I2C_CR1_ENPEC 0x00000020U
3612 #define I2C_CR1_ENGC 0x00000040U
3613 #define I2C_CR1_NOSTRETCH 0x00000080U
3614 #define I2C_CR1_START 0x00000100U
3615 #define I2C_CR1_STOP 0x00000200U
3616 #define I2C_CR1_ACK 0x00000400U
3617 #define I2C_CR1_POS 0x00000800U
3618 #define I2C_CR1_PEC 0x00001000U
3619 #define I2C_CR1_ALERT 0x00002000U
3620 #define I2C_CR1_SWRST 0x00008000U
3622 /******************* Bit definition for I2C_CR2 register ********************/
3623 #define I2C_CR2_FREQ 0x0000003FU
3624 #define I2C_CR2_FREQ_0 0x00000001U
3625 #define I2C_CR2_FREQ_1 0x00000002U
3626 #define I2C_CR2_FREQ_2 0x00000004U
3627 #define I2C_CR2_FREQ_3 0x00000008U
3628 #define I2C_CR2_FREQ_4 0x00000010U
3629 #define I2C_CR2_FREQ_5 0x00000020U
3631 #define I2C_CR2_ITERREN 0x00000100U
3632 #define I2C_CR2_ITEVTEN 0x00000200U
3633 #define I2C_CR2_ITBUFEN 0x00000400U
3634 #define I2C_CR2_DMAEN 0x00000800U
3635 #define I2C_CR2_LAST 0x00001000U
3637 /******************* Bit definition for I2C_OAR1 register *******************/
3638 #define I2C_OAR1_ADD1_7 0x000000FEU
3639 #define I2C_OAR1_ADD8_9 0x00000300U
3641 #define I2C_OAR1_ADD0 0x00000001U
3642 #define I2C_OAR1_ADD1 0x00000002U
3643 #define I2C_OAR1_ADD2 0x00000004U
3644 #define I2C_OAR1_ADD3 0x00000008U
3645 #define I2C_OAR1_ADD4 0x00000010U
3646 #define I2C_OAR1_ADD5 0x00000020U
3647 #define I2C_OAR1_ADD6 0x00000040U
3648 #define I2C_OAR1_ADD7 0x00000080U
3649 #define I2C_OAR1_ADD8 0x00000100U
3650 #define I2C_OAR1_ADD9 0x00000200U
3652 #define I2C_OAR1_ADDMODE 0x00008000U
3654 /******************* Bit definition for I2C_OAR2 register *******************/
3655 #define I2C_OAR2_ENDUAL 0x00000001U
3656 #define I2C_OAR2_ADD2 0x000000FEU
3658 /******************** Bit definition for I2C_DR register ********************/
3659 #define I2C_DR_DR 0x000000FFU
3661 /******************* Bit definition for I2C_SR1 register ********************/
3662 #define I2C_SR1_SB 0x00000001U
3663 #define I2C_SR1_ADDR 0x00000002U
3664 #define I2C_SR1_BTF 0x00000004U
3665 #define I2C_SR1_ADD10 0x00000008U
3666 #define I2C_SR1_STOPF 0x00000010U
3667 #define I2C_SR1_RXNE 0x00000040U
3668 #define I2C_SR1_TXE 0x00000080U
3669 #define I2C_SR1_BERR 0x00000100U
3670 #define I2C_SR1_ARLO 0x00000200U
3671 #define I2C_SR1_AF 0x00000400U
3672 #define I2C_SR1_OVR 0x00000800U
3673 #define I2C_SR1_PECERR 0x00001000U
3674 #define I2C_SR1_TIMEOUT 0x00004000U
3675 #define I2C_SR1_SMBALERT 0x00008000U
3677 /******************* Bit definition for I2C_SR2 register ********************/
3678 #define I2C_SR2_MSL 0x00000001U
3679 #define I2C_SR2_BUSY 0x00000002U
3680 #define I2C_SR2_TRA 0x00000004U
3681 #define I2C_SR2_GENCALL 0x00000010U
3682 #define I2C_SR2_SMBDEFAULT 0x00000020U
3683 #define I2C_SR2_SMBHOST 0x00000040U
3684 #define I2C_SR2_DUALF 0x00000080U
3685 #define I2C_SR2_PEC 0x0000FF00U
3687 /******************* Bit definition for I2C_CCR register ********************/
3688 #define I2C_CCR_CCR 0x00000FFFU
3689 #define I2C_CCR_DUTY 0x00004000U
3690 #define I2C_CCR_FS 0x00008000U
3692 /****************** Bit definition for I2C_TRISE register *******************/
3693 #define I2C_TRISE_TRISE 0x0000003FU
3695 /****************** Bit definition for I2C_FLTR register *******************/
3696 #define I2C_FLTR_DNF 0x0000000FU
3697 #define I2C_FLTR_ANOFF 0x00000010U
3699 /******************************************************************************/
3700 /* */
3701 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
3702 /* */
3703 /******************************************************************************/
3704 /******************* Bit definition for I2C_CR1 register *******************/
3705 #define FMPI2C_CR1_PE 0x00000001U
3706 #define FMPI2C_CR1_TXIE 0x00000002U
3707 #define FMPI2C_CR1_RXIE 0x00000004U
3708 #define FMPI2C_CR1_ADDRIE 0x00000008U
3709 #define FMPI2C_CR1_NACKIE 0x00000010U
3710 #define FMPI2C_CR1_STOPIE 0x00000020U
3711 #define FMPI2C_CR1_TCIE 0x00000040U
3712 #define FMPI2C_CR1_ERRIE 0x00000080U
3713 #define FMPI2C_CR1_DFN 0x00000F00U
3714 #define FMPI2C_CR1_ANFOFF 0x00001000U
3715 #define FMPI2C_CR1_TXDMAEN 0x00004000U
3716 #define FMPI2C_CR1_RXDMAEN 0x00008000U
3717 #define FMPI2C_CR1_SBC 0x00010000U
3718 #define FMPI2C_CR1_NOSTRETCH 0x00020000U
3719 #define FMPI2C_CR1_GCEN 0x00080000U
3720 #define FMPI2C_CR1_SMBHEN 0x00100000U
3721 #define FMPI2C_CR1_SMBDEN 0x00200000U
3722 #define FMPI2C_CR1_ALERTEN 0x00400000U
3723 #define FMPI2C_CR1_PECEN 0x00800000U
3725 /****************** Bit definition for I2C_CR2 register ********************/
3726 #define FMPI2C_CR2_SADD 0x000003FFU
3727 #define FMPI2C_CR2_RD_WRN 0x00000400U
3728 #define FMPI2C_CR2_ADD10 0x00000800U
3729 #define FMPI2C_CR2_HEAD10R 0x00001000U
3730 #define FMPI2C_CR2_START 0x00002000U
3731 #define FMPI2C_CR2_STOP 0x00004000U
3732 #define FMPI2C_CR2_NACK 0x00008000U
3733 #define FMPI2C_CR2_NBYTES 0x00FF0000U
3734 #define FMPI2C_CR2_RELOAD 0x01000000U
3735 #define FMPI2C_CR2_AUTOEND 0x02000000U
3736 #define FMPI2C_CR2_PECBYTE 0x04000000U
3738 /******************* Bit definition for I2C_OAR1 register ******************/
3739 #define FMPI2C_OAR1_OA1 0x000003FFU
3740 #define FMPI2C_OAR1_OA1MODE 0x00000400U
3741 #define FMPI2C_OAR1_OA1EN 0x00008000U
3743 /******************* Bit definition for I2C_OAR2 register ******************/
3744 #define FMPI2C_OAR2_OA2 0x000000FEU
3745 #define FMPI2C_OAR2_OA2MSK 0x00000700U
3746 #define FMPI2C_OAR2_OA2EN 0x00008000U
3748 /******************* Bit definition for I2C_TIMINGR register *******************/
3749 #define FMPI2C_TIMINGR_SCLL 0x000000FFU
3750 #define FMPI2C_TIMINGR_SCLH 0x0000FF00U
3751 #define FMPI2C_TIMINGR_SDADEL 0x000F0000U
3752 #define FMPI2C_TIMINGR_SCLDEL 0x00F00000U
3753 #define FMPI2C_TIMINGR_PRESC 0xF0000000U
3755 /******************* Bit definition for I2C_TIMEOUTR register *******************/
3756 #define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
3757 #define FMPI2C_TIMEOUTR_TIDLE 0x00001000U
3758 #define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U
3759 #define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
3760 #define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U
3762 /****************** Bit definition for I2C_ISR register *********************/
3763 #define FMPI2C_ISR_TXE 0x00000001U
3764 #define FMPI2C_ISR_TXIS 0x00000002U
3765 #define FMPI2C_ISR_RXNE 0x00000004U
3766 #define FMPI2C_ISR_ADDR 0x00000008U
3767 #define FMPI2C_ISR_NACKF 0x00000010U
3768 #define FMPI2C_ISR_STOPF 0x00000020U
3769 #define FMPI2C_ISR_TC 0x00000040U
3770 #define FMPI2C_ISR_TCR 0x00000080U
3771 #define FMPI2C_ISR_BERR 0x00000100U
3772 #define FMPI2C_ISR_ARLO 0x00000200U
3773 #define FMPI2C_ISR_OVR 0x00000400U
3774 #define FMPI2C_ISR_PECERR 0x00000800U
3775 #define FMPI2C_ISR_TIMEOUT 0x00001000U
3776 #define FMPI2C_ISR_ALERT 0x00002000U
3777 #define FMPI2C_ISR_BUSY 0x00008000U
3778 #define FMPI2C_ISR_DIR 0x00010000U
3779 #define FMPI2C_ISR_ADDCODE 0x00FE0000U
3781 /****************** Bit definition for I2C_ICR register *********************/
3782 #define FMPI2C_ICR_ADDRCF 0x00000008U
3783 #define FMPI2C_ICR_NACKCF 0x00000010U
3784 #define FMPI2C_ICR_STOPCF 0x00000020U
3785 #define FMPI2C_ICR_BERRCF 0x00000100U
3786 #define FMPI2C_ICR_ARLOCF 0x00000200U
3787 #define FMPI2C_ICR_OVRCF 0x00000400U
3788 #define FMPI2C_ICR_PECCF 0x00000800U
3789 #define FMPI2C_ICR_TIMOUTCF 0x00001000U
3790 #define FMPI2C_ICR_ALERTCF 0x00002000U
3792 /****************** Bit definition for I2C_PECR register *********************/
3793 #define FMPI2C_PECR_PEC 0x000000FFU
3795 /****************** Bit definition for I2C_RXDR register *********************/
3796 #define FMPI2C_RXDR_RXDATA 0x000000FFU
3798 /****************** Bit definition for I2C_TXDR register *********************/
3799 #define FMPI2C_TXDR_TXDATA 0x000000FFU
3801 /******************************************************************************/
3802 /* */
3803 /* Independent WATCHDOG */
3804 /* */
3805 /******************************************************************************/
3806 /******************* Bit definition for IWDG_KR register ********************/
3807 #define IWDG_KR_KEY 0xFFFFU
3809 /******************* Bit definition for IWDG_PR register ********************/
3810 #define IWDG_PR_PR 0x07U
3811 #define IWDG_PR_PR_0 0x01U
3812 #define IWDG_PR_PR_1 0x02U
3813 #define IWDG_PR_PR_2 0x04U
3815 /******************* Bit definition for IWDG_RLR register *******************/
3816 #define IWDG_RLR_RL 0x0FFFU
3818 /******************* Bit definition for IWDG_SR register ********************/
3819 #define IWDG_SR_PVU 0x01U
3820 #define IWDG_SR_RVU 0x02U
3823 /******************************************************************************/
3824 /* */
3825 /* Power Control */
3826 /* */
3827 /******************************************************************************/
3828 /******************** Bit definition for PWR_CR register ********************/
3829 #define PWR_CR_LPDS 0x00000001U
3830 #define PWR_CR_PDDS 0x00000002U
3831 #define PWR_CR_CWUF 0x00000004U
3832 #define PWR_CR_CSBF 0x00000008U
3833 #define PWR_CR_PVDE 0x00000010U
3835 #define PWR_CR_PLS 0x000000E0U
3836 #define PWR_CR_PLS_0 0x00000020U
3837 #define PWR_CR_PLS_1 0x00000040U
3838 #define PWR_CR_PLS_2 0x00000080U
3841 #define PWR_CR_PLS_LEV0 0x00000000U
3842 #define PWR_CR_PLS_LEV1 0x00000020U
3843 #define PWR_CR_PLS_LEV2 0x00000040U
3844 #define PWR_CR_PLS_LEV3 0x00000060U
3845 #define PWR_CR_PLS_LEV4 0x00000080U
3846 #define PWR_CR_PLS_LEV5 0x000000A0U
3847 #define PWR_CR_PLS_LEV6 0x000000C0U
3848 #define PWR_CR_PLS_LEV7 0x000000E0U
3850 #define PWR_CR_DBP 0x00000100U
3851 #define PWR_CR_FPDS 0x00000200U
3852 #define PWR_CR_LPLVDS 0x00000400U
3853 #define PWR_CR_MRLVDS 0x00000800U
3854 #define PWR_CR_ADCDC1 0x00002000U
3856 #define PWR_CR_VOS 0x0000C000U
3857 #define PWR_CR_VOS_0 0x00004000U
3858 #define PWR_CR_VOS_1 0x00008000U
3860 #define PWR_CR_FMSSR 0x00100000U
3861 #define PWR_CR_FISSR 0x00200000U
3863 /******************* Bit definition for PWR_CSR register ********************/
3864 #define PWR_CSR_WUF 0x00000001U
3865 #define PWR_CSR_SBF 0x00000002U
3866 #define PWR_CSR_PVDO 0x00000004U
3867 #define PWR_CSR_BRR 0x00000008U
3868 #define PWR_CSR_EWUP 0x00000100U
3869 #define PWR_CSR_BRE 0x00000200U
3870 #define PWR_CSR_VOSRDY 0x00004000U
3872 /******************************************************************************/
3873 /* */
3874 /* Reset and Clock Control */
3875 /* */
3876 /******************************************************************************/
3877 /******************** Bit definition for RCC_CR register ********************/
3878 #define RCC_CR_HSION 0x00000001U
3879 #define RCC_CR_HSIRDY 0x00000002U
3880 
3881 #define RCC_CR_HSITRIM 0x000000F8U
3882 #define RCC_CR_HSITRIM_0 0x00000008U
3883 #define RCC_CR_HSITRIM_1 0x00000010U
3884 #define RCC_CR_HSITRIM_2 0x00000020U
3885 #define RCC_CR_HSITRIM_3 0x00000040U
3886 #define RCC_CR_HSITRIM_4 0x00000080U
3888 #define RCC_CR_HSICAL 0x0000FF00U
3889 #define RCC_CR_HSICAL_0 0x00000100U
3890 #define RCC_CR_HSICAL_1 0x00000200U
3891 #define RCC_CR_HSICAL_2 0x00000400U
3892 #define RCC_CR_HSICAL_3 0x00000800U
3893 #define RCC_CR_HSICAL_4 0x00001000U
3894 #define RCC_CR_HSICAL_5 0x00002000U
3895 #define RCC_CR_HSICAL_6 0x00004000U
3896 #define RCC_CR_HSICAL_7 0x00008000U
3898 #define RCC_CR_HSEON 0x00010000U
3899 #define RCC_CR_HSERDY 0x00020000U
3900 #define RCC_CR_HSEBYP 0x00040000U
3901 #define RCC_CR_CSSON 0x00080000U
3902 #define RCC_CR_PLLON 0x01000000U
3903 #define RCC_CR_PLLRDY 0x02000000U
3904 #define RCC_CR_PLLI2SON 0x04000000U
3905 #define RCC_CR_PLLI2SRDY 0x08000000U
3906 
3907 /******************** Bit definition for RCC_PLLCFGR register ***************/
3908 #define RCC_PLLCFGR_PLLM 0x0000003FU
3909 #define RCC_PLLCFGR_PLLM_0 0x00000001U
3910 #define RCC_PLLCFGR_PLLM_1 0x00000002U
3911 #define RCC_PLLCFGR_PLLM_2 0x00000004U
3912 #define RCC_PLLCFGR_PLLM_3 0x00000008U
3913 #define RCC_PLLCFGR_PLLM_4 0x00000010U
3914 #define RCC_PLLCFGR_PLLM_5 0x00000020U
3915 
3916 #define RCC_PLLCFGR_PLLN 0x00007FC0U
3917 #define RCC_PLLCFGR_PLLN_0 0x00000040U
3918 #define RCC_PLLCFGR_PLLN_1 0x00000080U
3919 #define RCC_PLLCFGR_PLLN_2 0x00000100U
3920 #define RCC_PLLCFGR_PLLN_3 0x00000200U
3921 #define RCC_PLLCFGR_PLLN_4 0x00000400U
3922 #define RCC_PLLCFGR_PLLN_5 0x00000800U
3923 #define RCC_PLLCFGR_PLLN_6 0x00001000U
3924 #define RCC_PLLCFGR_PLLN_7 0x00002000U
3925 #define RCC_PLLCFGR_PLLN_8 0x00004000U
3926 
3927 #define RCC_PLLCFGR_PLLP 0x00030000U
3928 #define RCC_PLLCFGR_PLLP_0 0x00010000U
3929 #define RCC_PLLCFGR_PLLP_1 0x00020000U
3930 
3931 #define RCC_PLLCFGR_PLLSRC 0x00400000U
3932 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
3933 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
3934 
3935 #define RCC_PLLCFGR_PLLQ 0x0F000000U
3936 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
3937 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
3938 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
3939 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
3940 
3941 #define RCC_PLLCFGR_PLLR 0x70000000U
3942 #define RCC_PLLCFGR_PLLR_0 0x10000000U
3943 #define RCC_PLLCFGR_PLLR_1 0x20000000U
3944 #define RCC_PLLCFGR_PLLR_2 0x40000000U
3945 
3946 /******************** Bit definition for RCC_CFGR register ******************/
3948 #define RCC_CFGR_SW 0x00000003U
3949 #define RCC_CFGR_SW_0 0x00000001U
3950 #define RCC_CFGR_SW_1 0x00000002U
3952 #define RCC_CFGR_SW_HSI 0x00000000U
3953 #define RCC_CFGR_SW_HSE 0x00000001U
3954 #define RCC_CFGR_SW_PLL 0x00000002U
3955 #define RCC_CFGR_SW_PLLR 0x00000003U
3958 #define RCC_CFGR_SWS 0x0000000CU
3959 #define RCC_CFGR_SWS_0 0x00000004U
3960 #define RCC_CFGR_SWS_1 0x00000008U
3962 #define RCC_CFGR_SWS_HSI 0x00000000U
3963 #define RCC_CFGR_SWS_HSE 0x00000004U
3964 #define RCC_CFGR_SWS_PLL 0x00000008U
3965 #define RCC_CFGR_SWS_PLLR 0x0000000CU
3968 #define RCC_CFGR_HPRE 0x000000F0U
3969 #define RCC_CFGR_HPRE_0 0x00000010U
3970 #define RCC_CFGR_HPRE_1 0x00000020U
3971 #define RCC_CFGR_HPRE_2 0x00000040U
3972 #define RCC_CFGR_HPRE_3 0x00000080U
3974 #define RCC_CFGR_HPRE_DIV1 0x00000000U
3975 #define RCC_CFGR_HPRE_DIV2 0x00000080U
3976 #define RCC_CFGR_HPRE_DIV4 0x00000090U
3977 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
3978 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
3979 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
3980 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
3981 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
3982 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
3985 #define RCC_CFGR_PPRE1 0x00001C00U
3986 #define RCC_CFGR_PPRE1_0 0x00000400U
3987 #define RCC_CFGR_PPRE1_1 0x00000800U
3988 #define RCC_CFGR_PPRE1_2 0x00001000U
3990 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
3991 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
3992 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
3993 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
3994 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
3997 #define RCC_CFGR_PPRE2 0x0000E000U
3998 #define RCC_CFGR_PPRE2_0 0x00002000U
3999 #define RCC_CFGR_PPRE2_1 0x00004000U
4000 #define RCC_CFGR_PPRE2_2 0x00008000U
4002 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
4003 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
4004 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
4005 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
4006 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
4009 #define RCC_CFGR_RTCPRE 0x001F0000U
4010 #define RCC_CFGR_RTCPRE_0 0x00010000U
4011 #define RCC_CFGR_RTCPRE_1 0x00020000U
4012 #define RCC_CFGR_RTCPRE_2 0x00040000U
4013 #define RCC_CFGR_RTCPRE_3 0x00080000U
4014 #define RCC_CFGR_RTCPRE_4 0x00100000U
4015 
4017 #define RCC_CFGR_MCO1 0x00600000U
4018 #define RCC_CFGR_MCO1_0 0x00200000U
4019 #define RCC_CFGR_MCO1_1 0x00400000U
4020 
4021 #define RCC_CFGR_MCO1PRE 0x07000000U
4022 #define RCC_CFGR_MCO1PRE_0 0x01000000U
4023 #define RCC_CFGR_MCO1PRE_1 0x02000000U
4024 #define RCC_CFGR_MCO1PRE_2 0x04000000U
4025 
4026 /******************** Bit definition for RCC_CIR register *******************/
4027 #define RCC_CIR_LSIRDYF 0x00000001U
4028 #define RCC_CIR_LSERDYF 0x00000002U
4029 #define RCC_CIR_HSIRDYF 0x00000004U
4030 #define RCC_CIR_HSERDYF 0x00000008U
4031 #define RCC_CIR_PLLRDYF 0x00000010U
4032 #define RCC_CIR_PLLI2SRDYF 0x00000020U
4033 
4034 #define RCC_CIR_CSSF 0x00000080U
4035 #define RCC_CIR_LSIRDYIE 0x00000100U
4036 #define RCC_CIR_LSERDYIE 0x00000200U
4037 #define RCC_CIR_HSIRDYIE 0x00000400U
4038 #define RCC_CIR_HSERDYIE 0x00000800U
4039 #define RCC_CIR_PLLRDYIE 0x00001000U
4040 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
4041 
4042 #define RCC_CIR_LSIRDYC 0x00010000U
4043 #define RCC_CIR_LSERDYC 0x00020000U
4044 #define RCC_CIR_HSIRDYC 0x00040000U
4045 #define RCC_CIR_HSERDYC 0x00080000U
4046 #define RCC_CIR_PLLRDYC 0x00100000U
4047 #define RCC_CIR_PLLI2SRDYC 0x00200000U
4048 
4049 #define RCC_CIR_CSSC 0x00800000U
4050 
4051 /******************** Bit definition for RCC_AHB1RSTR register **************/
4052 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
4053 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
4054 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
4055 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
4056 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
4057 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
4058 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
4059 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
4060 #define RCC_AHB1RSTR_CRCRST 0x00001000U
4061 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
4062 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
4063 
4064 /******************** Bit definition for RCC_AHB2RSTR register **************/
4065 #define RCC_AHB2RSTR_RNGRST 0x00000040U
4066 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
4067 
4068 /******************** Bit definition for RCC_APB1RSTR register **************/
4069 #define RCC_APB1RSTR_TIM2RST 0x00000001U
4070 #define RCC_APB1RSTR_TIM3RST 0x00000002U
4071 #define RCC_APB1RSTR_TIM4RST 0x00000004U
4072 #define RCC_APB1RSTR_TIM5RST 0x00000008U
4073 #define RCC_APB1RSTR_TIM6RST 0x00000010U
4074 #define RCC_APB1RSTR_TIM7RST 0x00000020U
4075 #define RCC_APB1RSTR_TIM12RST 0x00000040U
4076 #define RCC_APB1RSTR_TIM13RST 0x00000080U
4077 #define RCC_APB1RSTR_TIM14RST 0x00000100U
4078 #define RCC_APB1RSTR_WWDGRST 0x00000800U
4079 #define RCC_APB1RSTR_SPI2RST 0x00004000U
4080 #define RCC_APB1RSTR_SPI3RST 0x00008000U
4081 #define RCC_APB1RSTR_USART2RST 0x00020000U
4082 #define RCC_APB1RSTR_I2C1RST 0x00200000U
4083 #define RCC_APB1RSTR_I2C2RST 0x00400000U
4084 #define RCC_APB1RSTR_I2C3RST 0x00800000U
4085 #define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
4086 #define RCC_APB1RSTR_CAN1RST 0x02000000U
4087 #define RCC_APB1RSTR_CAN2RST 0x04000000U
4088 #define RCC_APB1RSTR_PWRRST 0x10000000U
4089 
4090 /******************** Bit definition for RCC_APB2RSTR register **************/
4091 #define RCC_APB2RSTR_TIM1RST 0x00000001U
4092 #define RCC_APB2RSTR_TIM8RST 0x00000002U
4093 #define RCC_APB2RSTR_USART1RST 0x00000010U
4094 #define RCC_APB2RSTR_USART6RST 0x00000020U
4095 #define RCC_APB2RSTR_ADCRST 0x00000100U
4096 #define RCC_APB2RSTR_SDIORST 0x00000800U
4097 #define RCC_APB2RSTR_SPI1RST 0x00001000U
4098 #define RCC_APB2RSTR_SPI4RST 0x00002000U
4099 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
4100 #define RCC_APB2RSTR_TIM9RST 0x00010000U
4101 #define RCC_APB2RSTR_TIM10RST 0x00020000U
4102 #define RCC_APB2RSTR_TIM11RST 0x00040000U
4103 #define RCC_APB2RSTR_SPI5RST 0x00100000U
4104 #define RCC_APB2RSTR_DFSDM1RST 0x01000000U
4105 
4106 /******************** Bit definition for RCC_AHB1ENR register ***************/
4107 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
4108 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
4109 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
4110 #define RCC_AHB1ENR_GPIODEN 0x00000008U
4111 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
4112 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
4113 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
4114 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
4115 #define RCC_AHB1ENR_CRCEN 0x00001000U
4116 #define RCC_AHB1ENR_DMA1EN 0x00200000U
4117 #define RCC_AHB1ENR_DMA2EN 0x00400000U
4118 
4119 /******************** Bit definition for RCC_AHB2ENR register ***************/
4120 #define RCC_AHB2ENR_RNGEN 0x00000040U
4121 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
4122 
4123 /******************** Bit definition for RCC_APB1ENR register ***************/
4124 #define RCC_APB1ENR_TIM2EN 0x00000001U
4125 #define RCC_APB1ENR_TIM3EN 0x00000002U
4126 #define RCC_APB1ENR_TIM4EN 0x00000004U
4127 #define RCC_APB1ENR_TIM5EN 0x00000008U
4128 #define RCC_APB1ENR_TIM6EN 0x00000010U
4129 #define RCC_APB1ENR_TIM7EN 0x00000020U
4130 #define RCC_APB1ENR_TIM12EN 0x00000040U
4131 #define RCC_APB1ENR_TIM13EN 0x00000080U
4132 #define RCC_APB1ENR_TIM14EN 0x00000100U
4133 #define RCC_APB1ENR_RTCAPBEN 0x00000400U
4134 #define RCC_APB1ENR_WWDGEN 0x00000800U
4135 #define RCC_APB1ENR_SPI2EN 0x00004000U
4136 #define RCC_APB1ENR_SPI3EN 0x00008000U
4137 #define RCC_APB1ENR_USART2EN 0x00020000U
4138 #define RCC_APB1ENR_I2C1EN 0x00200000U
4139 #define RCC_APB1ENR_I2C2EN 0x00400000U
4140 #define RCC_APB1ENR_I2C3EN 0x00800000U
4141 #define RCC_APB1ENR_FMPI2C1EN 0x01000000U
4142 #define RCC_APB1ENR_CAN1EN 0x02000000U
4143 #define RCC_APB1ENR_CAN2EN 0x04000000U
4144 #define RCC_APB1ENR_PWREN 0x10000000U
4145 
4146 /******************** Bit definition for RCC_APB2ENR register ***************/
4147 #define RCC_APB2ENR_TIM1EN 0x00000001U
4148 #define RCC_APB2ENR_TIM8EN 0x00000002U
4149 #define RCC_APB2ENR_USART1EN 0x00000010U
4150 #define RCC_APB2ENR_USART6EN 0x00000020U
4151 #define RCC_APB2ENR_ADC1EN 0x00000100U
4152 #define RCC_APB2ENR_SDIOEN 0x00000800U
4153 #define RCC_APB2ENR_SPI1EN 0x00001000U
4154 #define RCC_APB2ENR_SPI4EN 0x00002000U
4155 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
4156 #define RCC_APB2ENR_EXTITEN 0x00008000U
4157 #define RCC_APB2ENR_TIM9EN 0x00010000U
4158 #define RCC_APB2ENR_TIM10EN 0x00020000U
4159 #define RCC_APB2ENR_TIM11EN 0x00040000U
4160 #define RCC_APB2ENR_SPI5EN 0x00100000U
4161 #define RCC_APB2ENR_DFSDM1EN 0x01000000U
4162 /******************** Bit definition for RCC_AHB1LPENR register *************/
4163 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
4164 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
4165 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
4166 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
4167 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
4168 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
4169 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
4170 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
4171 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
4172 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
4173 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
4174 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
4175 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
4176 
4177 /******************** Bit definition for RCC_AHB2LPENR register *************/
4178 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
4179 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
4180 
4181 /******************** Bit definition for RCC_APB1LPENR register *************/
4182 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
4183 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
4184 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
4185 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
4186 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
4187 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
4188 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
4189 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
4190 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
4191 #define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
4192 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
4193 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
4194 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
4195 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
4196 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
4197 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
4198 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
4199 #define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
4200 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
4201 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
4202 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
4203 
4204 /******************** Bit definition for RCC_APB2LPENR register *************/
4205 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
4206 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
4207 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
4208 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
4209 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
4210 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
4211 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
4212 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
4213 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
4214 #define RCC_APB2LPENR_EXTITLPEN 0x00008000U
4215 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
4216 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
4217 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
4218 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
4219 #define RCC_APB2LPENR_DFSDM1LPEN 0x01000000U
4220 
4221 /******************** Bit definition for RCC_BDCR register ******************/
4222 #define RCC_BDCR_LSEON 0x00000001U
4223 #define RCC_BDCR_LSERDY 0x00000002U
4224 #define RCC_BDCR_LSEBYP 0x00000004U
4225 #define RCC_BDCR_LSEMOD 0x00000008U
4226 
4227 #define RCC_BDCR_RTCSEL 0x00000300U
4228 #define RCC_BDCR_RTCSEL_0 0x00000100U
4229 #define RCC_BDCR_RTCSEL_1 0x00000200U
4230 
4231 #define RCC_BDCR_RTCEN 0x00008000U
4232 #define RCC_BDCR_BDRST 0x00010000U
4233 
4234 /******************** Bit definition for RCC_CSR register *******************/
4235 #define RCC_CSR_LSION 0x00000001U
4236 #define RCC_CSR_LSIRDY 0x00000002U
4237 #define RCC_CSR_RMVF 0x01000000U
4238 #define RCC_CSR_PADRSTF 0x04000000U
4239 #define RCC_CSR_PORRSTF 0x08000000U
4240 #define RCC_CSR_SFTRSTF 0x10000000U
4241 #define RCC_CSR_WDGRSTF 0x20000000U
4242 #define RCC_CSR_WWDGRSTF 0x40000000U
4243 #define RCC_CSR_LPWRRSTF 0x80000000U
4244 
4245 /******************** Bit definition for RCC_SSCGR register *****************/
4246 #define RCC_SSCGR_MODPER 0x00001FFFU
4247 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
4248 #define RCC_SSCGR_SPREADSEL 0x40000000U
4249 #define RCC_SSCGR_SSCGEN 0x80000000U
4250 
4251 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
4252 #define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
4253 #define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
4254 #define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
4255 #define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
4256 #define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
4257 #define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
4258 #define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
4259 
4260 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
4261 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
4262 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
4263 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
4264 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
4265 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
4266 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
4267 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
4268 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
4269 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
4270 
4271 #define RCC_PLLI2SCFGR_PLLI2SSRC 0x00400000U
4272 
4273 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
4274 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
4275 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
4276 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
4277 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
4278 
4279 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
4280 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
4281 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
4282 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
4283 
4284 /******************** Bit definition for RCC_DCKCFGR register ****************/
4285 #define RCC_DCKCFGR_CKDFSDM1ASEL 0x00008000U
4286 #define RCC_DCKCFGR_TIMPRE 0x01000000U
4287 
4288 #define RCC_DCKCFGR_I2S1SRC 0x06000000U
4289 #define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
4290 #define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
4291 
4292 #define RCC_DCKCFGR_I2S2SRC 0x18000000U
4293 #define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
4294 #define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
4295 
4296 #define RCC_DCKCFGR_CKDFSDM1SEL 0x80000000U
4297 
4298 /******************** Bit definition for RCC_CKGATENR register ***************/
4299 #define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
4300 #define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
4301 #define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
4302 #define RCC_CKGATENR_SPARE_CKEN 0x00000008U
4303 #define RCC_CKGATENR_SRAM_CKEN 0x00000010U
4304 #define RCC_CKGATENR_FLITF_CKEN 0x00000020U
4305 #define RCC_CKGATENR_RCC_CKEN 0x00000040U
4306 #define RCC_CKGATENR_RCC_EVTCTL 0x00000080U
4307 
4308 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
4309 #define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
4310 #define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
4311 #define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
4312 
4313 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
4314 #define RCC_DCKCFGR2_SDIOSEL 0x10000000U
4315 
4316 /******************************************************************************/
4317 /* */
4318 /* RNG */
4319 /* */
4320 /******************************************************************************/
4321 /******************** Bits definition for RNG_CR register *******************/
4322 #define RNG_CR_RNGEN 0x00000004U
4323 #define RNG_CR_IE 0x00000008U
4324 
4325 /******************** Bits definition for RNG_SR register *******************/
4326 #define RNG_SR_DRDY 0x00000001U
4327 #define RNG_SR_CECS 0x00000002U
4328 #define RNG_SR_SECS 0x00000004U
4329 #define RNG_SR_CEIS 0x00000020U
4330 #define RNG_SR_SEIS 0x00000040U
4331 
4332 /******************************************************************************/
4333 /* */
4334 /* Real-Time Clock (RTC) */
4335 /* */
4336 /******************************************************************************/
4337 /******************** Bits definition for RTC_TR register *******************/
4338 #define RTC_TR_PM 0x00400000U
4339 #define RTC_TR_HT 0x00300000U
4340 #define RTC_TR_HT_0 0x00100000U
4341 #define RTC_TR_HT_1 0x00200000U
4342 #define RTC_TR_HU 0x000F0000U
4343 #define RTC_TR_HU_0 0x00010000U
4344 #define RTC_TR_HU_1 0x00020000U
4345 #define RTC_TR_HU_2 0x00040000U
4346 #define RTC_TR_HU_3 0x00080000U
4347 #define RTC_TR_MNT 0x00007000U
4348 #define RTC_TR_MNT_0 0x00001000U
4349 #define RTC_TR_MNT_1 0x00002000U
4350 #define RTC_TR_MNT_2 0x00004000U
4351 #define RTC_TR_MNU 0x00000F00U
4352 #define RTC_TR_MNU_0 0x00000100U
4353 #define RTC_TR_MNU_1 0x00000200U
4354 #define RTC_TR_MNU_2 0x00000400U
4355 #define RTC_TR_MNU_3 0x00000800U
4356 #define RTC_TR_ST 0x00000070U
4357 #define RTC_TR_ST_0 0x00000010U
4358 #define RTC_TR_ST_1 0x00000020U
4359 #define RTC_TR_ST_2 0x00000040U
4360 #define RTC_TR_SU 0x0000000FU
4361 #define RTC_TR_SU_0 0x00000001U
4362 #define RTC_TR_SU_1 0x00000002U
4363 #define RTC_TR_SU_2 0x00000004U
4364 #define RTC_TR_SU_3 0x00000008U
4365 
4366 /******************** Bits definition for RTC_DR register *******************/
4367 #define RTC_DR_YT 0x00F00000U
4368 #define RTC_DR_YT_0 0x00100000U
4369 #define RTC_DR_YT_1 0x00200000U
4370 #define RTC_DR_YT_2 0x00400000U
4371 #define RTC_DR_YT_3 0x00800000U
4372 #define RTC_DR_YU 0x000F0000U
4373 #define RTC_DR_YU_0 0x00010000U
4374 #define RTC_DR_YU_1 0x00020000U
4375 #define RTC_DR_YU_2 0x00040000U
4376 #define RTC_DR_YU_3 0x00080000U
4377 #define RTC_DR_WDU 0x0000E000U
4378 #define RTC_DR_WDU_0 0x00002000U
4379 #define RTC_DR_WDU_1 0x00004000U
4380 #define RTC_DR_WDU_2 0x00008000U
4381 #define RTC_DR_MT 0x00001000U
4382 #define RTC_DR_MU 0x00000F00U
4383 #define RTC_DR_MU_0 0x00000100U
4384 #define RTC_DR_MU_1 0x00000200U
4385 #define RTC_DR_MU_2 0x00000400U
4386 #define RTC_DR_MU_3 0x00000800U
4387 #define RTC_DR_DT 0x00000030U
4388 #define RTC_DR_DT_0 0x00000010U
4389 #define RTC_DR_DT_1 0x00000020U
4390 #define RTC_DR_DU 0x0000000FU
4391 #define RTC_DR_DU_0 0x00000001U
4392 #define RTC_DR_DU_1 0x00000002U
4393 #define RTC_DR_DU_2 0x00000004U
4394 #define RTC_DR_DU_3 0x00000008U
4395 
4396 /******************** Bits definition for RTC_CR register *******************/
4397 #define RTC_CR_COE 0x00800000U
4398 #define RTC_CR_OSEL 0x00600000U
4399 #define RTC_CR_OSEL_0 0x00200000U
4400 #define RTC_CR_OSEL_1 0x00400000U
4401 #define RTC_CR_POL 0x00100000U
4402 #define RTC_CR_COSEL 0x00080000U
4403 #define RTC_CR_BCK 0x00040000U
4404 #define RTC_CR_SUB1H 0x00020000U
4405 #define RTC_CR_ADD1H 0x00010000U
4406 #define RTC_CR_TSIE 0x00008000U
4407 #define RTC_CR_WUTIE 0x00004000U
4408 #define RTC_CR_ALRBIE 0x00002000U
4409 #define RTC_CR_ALRAIE 0x00001000U
4410 #define RTC_CR_TSE 0x00000800U
4411 #define RTC_CR_WUTE 0x00000400U
4412 #define RTC_CR_ALRBE 0x00000200U
4413 #define RTC_CR_ALRAE 0x00000100U
4414 #define RTC_CR_DCE 0x00000080U
4415 #define RTC_CR_FMT 0x00000040U
4416 #define RTC_CR_BYPSHAD 0x00000020U
4417 #define RTC_CR_REFCKON 0x00000010U
4418 #define RTC_CR_TSEDGE 0x00000008U
4419 #define RTC_CR_WUCKSEL 0x00000007U
4420 #define RTC_CR_WUCKSEL_0 0x00000001U
4421 #define RTC_CR_WUCKSEL_1 0x00000002U
4422 #define RTC_CR_WUCKSEL_2 0x00000004U
4423 
4424 /******************** Bits definition for RTC_ISR register ******************/
4425 #define RTC_ISR_RECALPF 0x00010000U
4426 #define RTC_ISR_TAMP1F 0x00002000U
4427 #define RTC_ISR_TAMP2F 0x00004000U
4428 #define RTC_ISR_TSOVF 0x00001000U
4429 #define RTC_ISR_TSF 0x00000800U
4430 #define RTC_ISR_WUTF 0x00000400U
4431 #define RTC_ISR_ALRBF 0x00000200U
4432 #define RTC_ISR_ALRAF 0x00000100U
4433 #define RTC_ISR_INIT 0x00000080U
4434 #define RTC_ISR_INITF 0x00000040U
4435 #define RTC_ISR_RSF 0x00000020U
4436 #define RTC_ISR_INITS 0x00000010U
4437 #define RTC_ISR_SHPF 0x00000008U
4438 #define RTC_ISR_WUTWF 0x00000004U
4439 #define RTC_ISR_ALRBWF 0x00000002U
4440 #define RTC_ISR_ALRAWF 0x00000001U
4441 
4442 /******************** Bits definition for RTC_PRER register *****************/
4443 #define RTC_PRER_PREDIV_A 0x007F0000U
4444 #define RTC_PRER_PREDIV_S 0x00007FFFU
4445 
4446 /******************** Bits definition for RTC_WUTR register *****************/
4447 #define RTC_WUTR_WUT 0x0000FFFFU
4448 
4449 /******************** Bits definition for RTC_CALIBR register ***************/
4450 #define RTC_CALIBR_DCS 0x00000080U
4451 #define RTC_CALIBR_DC 0x0000001FU
4452 
4453 /******************** Bits definition for RTC_ALRMAR register ***************/
4454 #define RTC_ALRMAR_MSK4 0x80000000U
4455 #define RTC_ALRMAR_WDSEL 0x40000000U
4456 #define RTC_ALRMAR_DT 0x30000000U
4457 #define RTC_ALRMAR_DT_0 0x10000000U
4458 #define RTC_ALRMAR_DT_1 0x20000000U
4459 #define RTC_ALRMAR_DU 0x0F000000U
4460 #define RTC_ALRMAR_DU_0 0x01000000U
4461 #define RTC_ALRMAR_DU_1 0x02000000U
4462 #define RTC_ALRMAR_DU_2 0x04000000U
4463 #define RTC_ALRMAR_DU_3 0x08000000U
4464 #define RTC_ALRMAR_MSK3 0x00800000U
4465 #define RTC_ALRMAR_PM 0x00400000U
4466 #define RTC_ALRMAR_HT 0x00300000U
4467 #define RTC_ALRMAR_HT_0 0x00100000U
4468 #define RTC_ALRMAR_HT_1 0x00200000U
4469 #define RTC_ALRMAR_HU 0x000F0000U
4470 #define RTC_ALRMAR_HU_0 0x00010000U
4471 #define RTC_ALRMAR_HU_1 0x00020000U
4472 #define RTC_ALRMAR_HU_2 0x00040000U
4473 #define RTC_ALRMAR_HU_3 0x00080000U
4474 #define RTC_ALRMAR_MSK2 0x00008000U
4475 #define RTC_ALRMAR_MNT 0x00007000U
4476 #define RTC_ALRMAR_MNT_0 0x00001000U
4477 #define RTC_ALRMAR_MNT_1 0x00002000U
4478 #define RTC_ALRMAR_MNT_2 0x00004000U
4479 #define RTC_ALRMAR_MNU 0x00000F00U
4480 #define RTC_ALRMAR_MNU_0 0x00000100U
4481 #define RTC_ALRMAR_MNU_1 0x00000200U
4482 #define RTC_ALRMAR_MNU_2 0x00000400U
4483 #define RTC_ALRMAR_MNU_3 0x00000800U
4484 #define RTC_ALRMAR_MSK1 0x00000080U
4485 #define RTC_ALRMAR_ST 0x00000070U
4486 #define RTC_ALRMAR_ST_0 0x00000010U
4487 #define RTC_ALRMAR_ST_1 0x00000020U
4488 #define RTC_ALRMAR_ST_2 0x00000040U
4489 #define RTC_ALRMAR_SU 0x0000000FU
4490 #define RTC_ALRMAR_SU_0 0x00000001U
4491 #define RTC_ALRMAR_SU_1 0x00000002U
4492 #define RTC_ALRMAR_SU_2 0x00000004U
4493 #define RTC_ALRMAR_SU_3 0x00000008U
4494 
4495 /******************** Bits definition for RTC_ALRMBR register ***************/
4496 #define RTC_ALRMBR_MSK4 0x80000000U
4497 #define RTC_ALRMBR_WDSEL 0x40000000U
4498 #define RTC_ALRMBR_DT 0x30000000U
4499 #define RTC_ALRMBR_DT_0 0x10000000U
4500 #define RTC_ALRMBR_DT_1 0x20000000U
4501 #define RTC_ALRMBR_DU 0x0F000000U
4502 #define RTC_ALRMBR_DU_0 0x01000000U
4503 #define RTC_ALRMBR_DU_1 0x02000000U
4504 #define RTC_ALRMBR_DU_2 0x04000000U
4505 #define RTC_ALRMBR_DU_3 0x08000000U
4506 #define RTC_ALRMBR_MSK3 0x00800000U
4507 #define RTC_ALRMBR_PM 0x00400000U
4508 #define RTC_ALRMBR_HT 0x00300000U
4509 #define RTC_ALRMBR_HT_0 0x00100000U
4510 #define RTC_ALRMBR_HT_1 0x00200000U
4511 #define RTC_ALRMBR_HU 0x000F0000U
4512 #define RTC_ALRMBR_HU_0 0x00010000U
4513 #define RTC_ALRMBR_HU_1 0x00020000U
4514 #define RTC_ALRMBR_HU_2 0x00040000U
4515 #define RTC_ALRMBR_HU_3 0x00080000U
4516 #define RTC_ALRMBR_MSK2 0x00008000U
4517 #define RTC_ALRMBR_MNT 0x00007000U
4518 #define RTC_ALRMBR_MNT_0 0x00001000U
4519 #define RTC_ALRMBR_MNT_1 0x00002000U
4520 #define RTC_ALRMBR_MNT_2 0x00004000U
4521 #define RTC_ALRMBR_MNU 0x00000F00U
4522 #define RTC_ALRMBR_MNU_0 0x00000100U
4523 #define RTC_ALRMBR_MNU_1 0x00000200U
4524 #define RTC_ALRMBR_MNU_2 0x00000400U
4525 #define RTC_ALRMBR_MNU_3 0x00000800U
4526 #define RTC_ALRMBR_MSK1 0x00000080U
4527 #define RTC_ALRMBR_ST 0x00000070U
4528 #define RTC_ALRMBR_ST_0 0x00000010U
4529 #define RTC_ALRMBR_ST_1 0x00000020U
4530 #define RTC_ALRMBR_ST_2 0x00000040U
4531 #define RTC_ALRMBR_SU 0x0000000FU
4532 #define RTC_ALRMBR_SU_0 0x00000001U
4533 #define RTC_ALRMBR_SU_1 0x00000002U
4534 #define RTC_ALRMBR_SU_2 0x00000004U
4535 #define RTC_ALRMBR_SU_3 0x00000008U
4536 
4537 /******************** Bits definition for RTC_WPR register ******************/
4538 #define RTC_WPR_KEY 0x000000FFU
4539 
4540 /******************** Bits definition for RTC_SSR register ******************/
4541 #define RTC_SSR_SS 0x0000FFFFU
4542 
4543 /******************** Bits definition for RTC_SHIFTR register ***************/
4544 #define RTC_SHIFTR_SUBFS 0x00007FFFU
4545 #define RTC_SHIFTR_ADD1S 0x80000000U
4546 
4547 /******************** Bits definition for RTC_TSTR register *****************/
4548 #define RTC_TSTR_PM 0x00400000U
4549 #define RTC_TSTR_HT 0x00300000U
4550 #define RTC_TSTR_HT_0 0x00100000U
4551 #define RTC_TSTR_HT_1 0x00200000U
4552 #define RTC_TSTR_HU 0x000F0000U
4553 #define RTC_TSTR_HU_0 0x00010000U
4554 #define RTC_TSTR_HU_1 0x00020000U
4555 #define RTC_TSTR_HU_2 0x00040000U
4556 #define RTC_TSTR_HU_3 0x00080000U
4557 #define RTC_TSTR_MNT 0x00007000U
4558 #define RTC_TSTR_MNT_0 0x00001000U
4559 #define RTC_TSTR_MNT_1 0x00002000U
4560 #define RTC_TSTR_MNT_2 0x00004000U
4561 #define RTC_TSTR_MNU 0x00000F00U
4562 #define RTC_TSTR_MNU_0 0x00000100U
4563 #define RTC_TSTR_MNU_1 0x00000200U
4564 #define RTC_TSTR_MNU_2 0x00000400U
4565 #define RTC_TSTR_MNU_3 0x00000800U
4566 #define RTC_TSTR_ST 0x00000070U
4567 #define RTC_TSTR_ST_0 0x00000010U
4568 #define RTC_TSTR_ST_1 0x00000020U
4569 #define RTC_TSTR_ST_2 0x00000040U
4570 #define RTC_TSTR_SU 0x0000000FU
4571 #define RTC_TSTR_SU_0 0x00000001U
4572 #define RTC_TSTR_SU_1 0x00000002U
4573 #define RTC_TSTR_SU_2 0x00000004U
4574 #define RTC_TSTR_SU_3 0x00000008U
4575 
4576 /******************** Bits definition for RTC_TSDR register *****************/
4577 #define RTC_TSDR_WDU 0x0000E000U
4578 #define RTC_TSDR_WDU_0 0x00002000U
4579 #define RTC_TSDR_WDU_1 0x00004000U
4580 #define RTC_TSDR_WDU_2 0x00008000U
4581 #define RTC_TSDR_MT 0x00001000U
4582 #define RTC_TSDR_MU 0x00000F00U
4583 #define RTC_TSDR_MU_0 0x00000100U
4584 #define RTC_TSDR_MU_1 0x00000200U
4585 #define RTC_TSDR_MU_2 0x00000400U
4586 #define RTC_TSDR_MU_3 0x00000800U
4587 #define RTC_TSDR_DT 0x00000030U
4588 #define RTC_TSDR_DT_0 0x00000010U
4589 #define RTC_TSDR_DT_1 0x00000020U
4590 #define RTC_TSDR_DU 0x0000000FU
4591 #define RTC_TSDR_DU_0 0x00000001U
4592 #define RTC_TSDR_DU_1 0x00000002U
4593 #define RTC_TSDR_DU_2 0x00000004U
4594 #define RTC_TSDR_DU_3 0x00000008U
4595 
4596 /******************** Bits definition for RTC_TSSSR register ****************/
4597 #define RTC_TSSSR_SS 0x0000FFFFU
4598 
4599 /******************** Bits definition for RTC_CAL register *****************/
4600 #define RTC_CALR_CALP 0x00008000U
4601 #define RTC_CALR_CALW8 0x00004000U
4602 #define RTC_CALR_CALW16 0x00002000U
4603 #define RTC_CALR_CALM 0x000001FFU
4604 #define RTC_CALR_CALM_0 0x00000001U
4605 #define RTC_CALR_CALM_1 0x00000002U
4606 #define RTC_CALR_CALM_2 0x00000004U
4607 #define RTC_CALR_CALM_3 0x00000008U
4608 #define RTC_CALR_CALM_4 0x00000010U
4609 #define RTC_CALR_CALM_5 0x00000020U
4610 #define RTC_CALR_CALM_6 0x00000040U
4611 #define RTC_CALR_CALM_7 0x00000080U
4612 #define RTC_CALR_CALM_8 0x00000100U
4613 
4614 /******************** Bits definition for RTC_TAFCR register ****************/
4615 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
4616 #define RTC_TAFCR_TSINSEL 0x00020000U
4617 #define RTC_TAFCR_TAMPINSEL 0x00010000U
4618 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
4619 #define RTC_TAFCR_TAMPPRCH 0x00006000U
4620 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
4621 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
4622 #define RTC_TAFCR_TAMPFLT 0x00001800U
4623 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
4624 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
4625 #define RTC_TAFCR_TAMPFREQ 0x00000700U
4626 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
4627 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
4628 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
4629 #define RTC_TAFCR_TAMPTS 0x00000080U
4630 #define RTC_TAFCR_TAMP2TRG 0x00000010U
4631 #define RTC_TAFCR_TAMP2E 0x00000008U
4632 #define RTC_TAFCR_TAMPIE 0x00000004U
4633 #define RTC_TAFCR_TAMP1TRG 0x00000002U
4634 #define RTC_TAFCR_TAMP1E 0x00000001U
4635 
4636 /******************** Bits definition for RTC_ALRMASSR register *************/
4637 #define RTC_ALRMASSR_MASKSS 0x0F000000U
4638 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
4639 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
4640 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
4641 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
4642 #define RTC_ALRMASSR_SS 0x00007FFFU
4643 
4644 /******************** Bits definition for RTC_ALRMBSSR register *************/
4645 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
4646 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
4647 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
4648 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
4649 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
4650 #define RTC_ALRMBSSR_SS 0x00007FFFU
4651 
4652 /******************** Bits definition for RTC_BKP0R register ****************/
4653 #define RTC_BKP0R 0xFFFFFFFFU
4654 
4655 /******************** Bits definition for RTC_BKP1R register ****************/
4656 #define RTC_BKP1R 0xFFFFFFFFU
4657 
4658 /******************** Bits definition for RTC_BKP2R register ****************/
4659 #define RTC_BKP2R 0xFFFFFFFFU
4660 
4661 /******************** Bits definition for RTC_BKP3R register ****************/
4662 #define RTC_BKP3R 0xFFFFFFFFU
4663 
4664 /******************** Bits definition for RTC_BKP4R register ****************/
4665 #define RTC_BKP4R 0xFFFFFFFFU
4666 
4667 /******************** Bits definition for RTC_BKP5R register ****************/
4668 #define RTC_BKP5R 0xFFFFFFFFU
4669 
4670 /******************** Bits definition for RTC_BKP6R register ****************/
4671 #define RTC_BKP6R 0xFFFFFFFFU
4672 
4673 /******************** Bits definition for RTC_BKP7R register ****************/
4674 #define RTC_BKP7R 0xFFFFFFFFU
4675 
4676 /******************** Bits definition for RTC_BKP8R register ****************/
4677 #define RTC_BKP8R 0xFFFFFFFFU
4678 
4679 /******************** Bits definition for RTC_BKP9R register ****************/
4680 #define RTC_BKP9R 0xFFFFFFFFU
4681 
4682 /******************** Bits definition for RTC_BKP10R register ***************/
4683 #define RTC_BKP10R 0xFFFFFFFFU
4684 
4685 /******************** Bits definition for RTC_BKP11R register ***************/
4686 #define RTC_BKP11R 0xFFFFFFFFU
4687 
4688 /******************** Bits definition for RTC_BKP12R register ***************/
4689 #define RTC_BKP12R 0xFFFFFFFFU
4690 
4691 /******************** Bits definition for RTC_BKP13R register ***************/
4692 #define RTC_BKP13R 0xFFFFFFFFU
4693 
4694 /******************** Bits definition for RTC_BKP14R register ***************/
4695 #define RTC_BKP14R 0xFFFFFFFFU
4696 
4697 /******************** Bits definition for RTC_BKP15R register ***************/
4698 #define RTC_BKP15R 0xFFFFFFFFU
4699 
4700 /******************** Bits definition for RTC_BKP16R register ***************/
4701 #define RTC_BKP16R 0xFFFFFFFFU
4702 
4703 /******************** Bits definition for RTC_BKP17R register ***************/
4704 #define RTC_BKP17R 0xFFFFFFFFU
4705 
4706 /******************** Bits definition for RTC_BKP18R register ***************/
4707 #define RTC_BKP18R 0xFFFFFFFFU
4708 
4709 /******************** Bits definition for RTC_BKP19R register ***************/
4710 #define RTC_BKP19R 0xFFFFFFFFU
4711 
4712 
4713 
4714 /******************************************************************************/
4715 /* */
4716 /* SD host Interface */
4717 /* */
4718 /******************************************************************************/
4719 /****************** Bit definition for SDIO_POWER register ******************/
4720 #define SDIO_POWER_PWRCTRL 0x03U
4721 #define SDIO_POWER_PWRCTRL_0 0x01U
4722 #define SDIO_POWER_PWRCTRL_1 0x02U
4724 /****************** Bit definition for SDIO_CLKCR register ******************/
4725 #define SDIO_CLKCR_CLKDIV 0x00FFU
4726 #define SDIO_CLKCR_CLKEN 0x0100U
4727 #define SDIO_CLKCR_PWRSAV 0x0200U
4728 #define SDIO_CLKCR_BYPASS 0x0400U
4730 #define SDIO_CLKCR_WIDBUS 0x1800U
4731 #define SDIO_CLKCR_WIDBUS_0 0x0800U
4732 #define SDIO_CLKCR_WIDBUS_1 0x1000U
4734 #define SDIO_CLKCR_NEGEDGE 0x2000U
4735 #define SDIO_CLKCR_HWFC_EN 0x4000U
4737 /******************* Bit definition for SDIO_ARG register *******************/
4738 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
4740 /******************* Bit definition for SDIO_CMD register *******************/
4741 #define SDIO_CMD_CMDINDEX 0x003FU
4743 #define SDIO_CMD_WAITRESP 0x00C0U
4744 #define SDIO_CMD_WAITRESP_0 0x0040U
4745 #define SDIO_CMD_WAITRESP_1 0x0080U
4747 #define SDIO_CMD_WAITINT 0x0100U
4748 #define SDIO_CMD_WAITPEND 0x0200U
4749 #define SDIO_CMD_CPSMEN 0x0400U
4750 #define SDIO_CMD_SDIOSUSPEND 0x0800U
4751 #define SDIO_CMD_ENCMDCOMPL 0x1000U
4752 #define SDIO_CMD_NIEN 0x2000U
4753 #define SDIO_CMD_CEATACMD 0x4000U
4755 /***************** Bit definition for SDIO_RESPCMD register *****************/
4756 #define SDIO_RESPCMD_RESPCMD 0x3FU
4758 /****************** Bit definition for SDIO_RESP0 register ******************/
4759 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
4761 /****************** Bit definition for SDIO_RESP1 register ******************/
4762 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
4764 /****************** Bit definition for SDIO_RESP2 register ******************/
4765 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
4767 /****************** Bit definition for SDIO_RESP3 register ******************/
4768 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
4770 /****************** Bit definition for SDIO_RESP4 register ******************/
4771 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
4773 /****************** Bit definition for SDIO_DTIMER register *****************/
4774 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
4776 /****************** Bit definition for SDIO_DLEN register *******************/
4777 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
4779 /****************** Bit definition for SDIO_DCTRL register ******************/
4780 #define SDIO_DCTRL_DTEN 0x0001U
4781 #define SDIO_DCTRL_DTDIR 0x0002U
4782 #define SDIO_DCTRL_DTMODE 0x0004U
4783 #define SDIO_DCTRL_DMAEN 0x0008U
4785 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
4786 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
4787 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
4788 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
4789 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
4791 #define SDIO_DCTRL_RWSTART 0x0100U
4792 #define SDIO_DCTRL_RWSTOP 0x0200U
4793 #define SDIO_DCTRL_RWMOD 0x0400U
4794 #define SDIO_DCTRL_SDIOEN 0x0800U
4796 /****************** Bit definition for SDIO_DCOUNT register *****************/
4797 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
4799 /****************** Bit definition for SDIO_STA register ********************/
4800 #define SDIO_STA_CCRCFAIL 0x00000001U
4801 #define SDIO_STA_DCRCFAIL 0x00000002U
4802 #define SDIO_STA_CTIMEOUT 0x00000004U
4803 #define SDIO_STA_DTIMEOUT 0x00000008U
4804 #define SDIO_STA_TXUNDERR 0x00000010U
4805 #define SDIO_STA_RXOVERR 0x00000020U
4806 #define SDIO_STA_CMDREND 0x00000040U
4807 #define SDIO_STA_CMDSENT 0x00000080U
4808 #define SDIO_STA_DATAEND 0x00000100U
4809 #define SDIO_STA_STBITERR 0x00000200U
4810 #define SDIO_STA_DBCKEND 0x00000400U
4811 #define SDIO_STA_CMDACT 0x00000800U
4812 #define SDIO_STA_TXACT 0x00001000U
4813 #define SDIO_STA_RXACT 0x00002000U
4814 #define SDIO_STA_TXFIFOHE 0x00004000U
4815 #define SDIO_STA_RXFIFOHF 0x00008000U
4816 #define SDIO_STA_TXFIFOF 0x00010000U
4817 #define SDIO_STA_RXFIFOF 0x00020000U
4818 #define SDIO_STA_TXFIFOE 0x00040000U
4819 #define SDIO_STA_RXFIFOE 0x00080000U
4820 #define SDIO_STA_TXDAVL 0x00100000U
4821 #define SDIO_STA_RXDAVL 0x00200000U
4822 #define SDIO_STA_SDIOIT 0x00400000U
4823 #define SDIO_STA_CEATAEND 0x00800000U
4825 /******************* Bit definition for SDIO_ICR register *******************/
4826 #define SDIO_ICR_CCRCFAILC 0x00000001U
4827 #define SDIO_ICR_DCRCFAILC 0x00000002U
4828 #define SDIO_ICR_CTIMEOUTC 0x00000004U
4829 #define SDIO_ICR_DTIMEOUTC 0x00000008U
4830 #define SDIO_ICR_TXUNDERRC 0x00000010U
4831 #define SDIO_ICR_RXOVERRC 0x00000020U
4832 #define SDIO_ICR_CMDRENDC 0x00000040U
4833 #define SDIO_ICR_CMDSENTC 0x00000080U
4834 #define SDIO_ICR_DATAENDC 0x00000100U
4835 #define SDIO_ICR_STBITERRC 0x00000200U
4836 #define SDIO_ICR_DBCKENDC 0x00000400U
4837 #define SDIO_ICR_SDIOITC 0x00400000U
4838 #define SDIO_ICR_CEATAENDC 0x00800000U
4840 /****************** Bit definition for SDIO_MASK register *******************/
4841 #define SDIO_MASK_CCRCFAILIE 0x00000001U
4842 #define SDIO_MASK_DCRCFAILIE 0x00000002U
4843 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
4844 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
4845 #define SDIO_MASK_TXUNDERRIE 0x00000010U
4846 #define SDIO_MASK_RXOVERRIE 0x00000020U
4847 #define SDIO_MASK_CMDRENDIE 0x00000040U
4848 #define SDIO_MASK_CMDSENTIE 0x00000080U
4849 #define SDIO_MASK_DATAENDIE 0x00000100U
4850 #define SDIO_MASK_STBITERRIE 0x00000200U
4851 #define SDIO_MASK_DBCKENDIE 0x00000400U
4852 #define SDIO_MASK_CMDACTIE 0x00000800U
4853 #define SDIO_MASK_TXACTIE 0x00001000U
4854 #define SDIO_MASK_RXACTIE 0x00002000U
4855 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
4856 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
4857 #define SDIO_MASK_TXFIFOFIE 0x00010000U
4858 #define SDIO_MASK_RXFIFOFIE 0x00020000U
4859 #define SDIO_MASK_TXFIFOEIE 0x00040000U
4860 #define SDIO_MASK_RXFIFOEIE 0x00080000U
4861 #define SDIO_MASK_TXDAVLIE 0x00100000U
4862 #define SDIO_MASK_RXDAVLIE 0x00200000U
4863 #define SDIO_MASK_SDIOITIE 0x00400000U
4864 #define SDIO_MASK_CEATAENDIE 0x00800000U
4866 /***************** Bit definition for SDIO_FIFOCNT register *****************/
4867 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
4869 /****************** Bit definition for SDIO_FIFO register *******************/
4870 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
4872 /******************************************************************************/
4873 /* */
4874 /* Serial Peripheral Interface */
4875 /* */
4876 /******************************************************************************/
4877 /******************* Bit definition for SPI_CR1 register ********************/
4878 #define SPI_CR1_CPHA 0x00000001U
4879 #define SPI_CR1_CPOL 0x00000002U
4880 #define SPI_CR1_MSTR 0x00000004U
4882 #define SPI_CR1_BR 0x00000038U
4883 #define SPI_CR1_BR_0 0x00000008U
4884 #define SPI_CR1_BR_1 0x00000010U
4885 #define SPI_CR1_BR_2 0x00000020U
4887 #define SPI_CR1_SPE 0x00000040U
4888 #define SPI_CR1_LSBFIRST 0x00000080U
4889 #define SPI_CR1_SSI 0x00000100U
4890 #define SPI_CR1_SSM 0x00000200U
4891 #define SPI_CR1_RXONLY 0x00000400U
4892 #define SPI_CR1_DFF 0x00000800U
4893 #define SPI_CR1_CRCNEXT 0x00001000U
4894 #define SPI_CR1_CRCEN 0x00002000U
4895 #define SPI_CR1_BIDIOE 0x00004000U
4896 #define SPI_CR1_BIDIMODE 0x00008000U
4898 /******************* Bit definition for SPI_CR2 register ********************/
4899 #define SPI_CR2_RXDMAEN 0x00000001U
4900 #define SPI_CR2_TXDMAEN 0x00000002U
4901 #define SPI_CR2_SSOE 0x00000004U
4902 #define SPI_CR2_FRF 0x00000010U
4903 #define SPI_CR2_ERRIE 0x00000020U
4904 #define SPI_CR2_RXNEIE 0x00000040U
4905 #define SPI_CR2_TXEIE 0x00000080U
4907 /******************** Bit definition for SPI_SR register ********************/
4908 #define SPI_SR_RXNE 0x00000001U
4909 #define SPI_SR_TXE 0x00000002U
4910 #define SPI_SR_CHSIDE 0x00000004U
4911 #define SPI_SR_UDR 0x00000008U
4912 #define SPI_SR_CRCERR 0x00000010U
4913 #define SPI_SR_MODF 0x00000020U
4914 #define SPI_SR_OVR 0x00000040U
4915 #define SPI_SR_BSY 0x00000080U
4916 #define SPI_SR_FRE 0x00000100U
4918 /******************** Bit definition for SPI_DR register ********************/
4919 #define SPI_DR_DR 0x0000FFFFU
4921 /******************* Bit definition for SPI_CRCPR register ******************/
4922 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
4924 /****************** Bit definition for SPI_RXCRCR register ******************/
4925 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
4927 /****************** Bit definition for SPI_TXCRCR register ******************/
4928 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
4930 /****************** Bit definition for SPI_I2SCFGR register *****************/
4931 #define SPI_I2SCFGR_CHLEN 0x00000001U
4933 #define SPI_I2SCFGR_DATLEN 0x00000006U
4934 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
4935 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
4937 #define SPI_I2SCFGR_CKPOL 0x00000008U
4939 #define SPI_I2SCFGR_I2SSTD 0x00000030U
4940 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
4941 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
4943 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
4945 #define SPI_I2SCFGR_I2SCFG 0x00000300U
4946 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
4947 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
4949 #define SPI_I2SCFGR_I2SE 0x00000400U
4950 #define SPI_I2SCFGR_I2SMOD 0x00000800U
4952 /****************** Bit definition for SPI_I2SPR register *******************/
4953 #define SPI_I2SPR_I2SDIV 0x000000FFU
4954 #define SPI_I2SPR_ODD 0x00000100U
4955 #define SPI_I2SPR_MCKOE 0x00000200U
4957 /******************************************************************************/
4958 /* */
4959 /* SYSCFG */
4960 /* */
4961 /******************************************************************************/
4962 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
4963 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
4964 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
4965 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
4966 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
4967 
4968 /****************** Bit definition for SYSCFG_PMC register ******************/
4969 #define SYSCFG_PMC_ADC1DC2 0x00010000U
4971 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
4972 #define SYSCFG_EXTICR1_EXTI0 0x000FU
4973 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
4974 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
4975 #define SYSCFG_EXTICR1_EXTI3 0xF000U
4979 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
4980 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
4981 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
4982 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
4983 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
4984 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
4985 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
4986 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
4991 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
4992 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
4993 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
4994 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
4995 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
4996 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
4997 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
4998 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
5003 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
5004 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
5005 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
5006 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
5007 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
5008 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
5009 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
5010 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
5015 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
5016 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
5017 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
5018 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
5019 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
5020 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
5021 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
5022 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
5024 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5025 #define SYSCFG_EXTICR2_EXTI4 0x000FU
5026 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
5027 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
5028 #define SYSCFG_EXTICR2_EXTI7 0xF000U
5032 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
5033 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
5034 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
5035 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
5036 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
5037 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
5038 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
5039 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
5044 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
5045 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
5046 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
5047 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
5048 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
5049 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
5050 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
5051 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
5056 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
5057 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
5058 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
5059 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
5060 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
5061 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
5062 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
5063 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
5068 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
5069 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
5070 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
5071 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
5072 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
5073 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
5074 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
5075 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
5078 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5079 #define SYSCFG_EXTICR3_EXTI8 0x000FU
5080 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
5081 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
5082 #define SYSCFG_EXTICR3_EXTI11 0xF000U
5087 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
5088 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
5089 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
5090 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
5091 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
5092 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
5093 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
5094 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
5099 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
5100 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
5101 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
5102 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
5103 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
5104 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
5105 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
5106 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
5111 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
5112 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
5113 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
5114 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
5115 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
5116 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
5117 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
5118 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
5123 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
5124 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
5125 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
5126 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
5127 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
5128 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
5129 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
5130 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
5132 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5133 #define SYSCFG_EXTICR4_EXTI12 0x000FU
5134 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
5135 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
5136 #define SYSCFG_EXTICR4_EXTI15 0xF000U
5140 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
5141 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
5142 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
5143 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
5144 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
5145 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
5146 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
5147 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
5152 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
5153 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
5154 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
5155 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
5156 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
5157 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
5158 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
5159 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
5164 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
5165 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
5166 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
5167 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
5168 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
5169 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
5170 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
5171 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
5176 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
5177 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
5178 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
5179 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
5180 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
5181 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
5182 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
5183 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
5185 /****************** Bit definition for SYSCFG_CMPCR register ****************/
5186 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
5187 #define SYSCFG_CMPCR_READY 0x00000100U
5189 /****************** Bit definition for SYSCFG_CFGR register *****************/
5190 #define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U
5191 #define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U
5193 /******************************************************************************/
5194 /* */
5195 /* TIM */
5196 /* */
5197 /******************************************************************************/
5198 /******************* Bit definition for TIM_CR1 register ********************/
5199 #define TIM_CR1_CEN 0x0001U
5200 #define TIM_CR1_UDIS 0x0002U
5201 #define TIM_CR1_URS 0x0004U
5202 #define TIM_CR1_OPM 0x0008U
5203 #define TIM_CR1_DIR 0x0010U
5205 #define TIM_CR1_CMS 0x0060U
5206 #define TIM_CR1_CMS_0 0x0020U
5207 #define TIM_CR1_CMS_1 0x0040U
5209 #define TIM_CR1_ARPE 0x0080U
5211 #define TIM_CR1_CKD 0x0300U
5212 #define TIM_CR1_CKD_0 0x0100U
5213 #define TIM_CR1_CKD_1 0x0200U
5215 /******************* Bit definition for TIM_CR2 register ********************/
5216 #define TIM_CR2_CCPC 0x0001U
5217 #define TIM_CR2_CCUS 0x0004U
5218 #define TIM_CR2_CCDS 0x0008U
5220 #define TIM_CR2_MMS 0x0070U
5221 #define TIM_CR2_MMS_0 0x0010U
5222 #define TIM_CR2_MMS_1 0x0020U
5223 #define TIM_CR2_MMS_2 0x0040U
5225 #define TIM_CR2_TI1S 0x0080U
5226 #define TIM_CR2_OIS1 0x0100U
5227 #define TIM_CR2_OIS1N 0x0200U
5228 #define TIM_CR2_OIS2 0x0400U
5229 #define TIM_CR2_OIS2N 0x0800U
5230 #define TIM_CR2_OIS3 0x1000U
5231 #define TIM_CR2_OIS3N 0x2000U
5232 #define TIM_CR2_OIS4 0x4000U
5234 /******************* Bit definition for TIM_SMCR register *******************/
5235 #define TIM_SMCR_SMS 0x0007U
5236 #define TIM_SMCR_SMS_0 0x0001U
5237 #define TIM_SMCR_SMS_1 0x0002U
5238 #define TIM_SMCR_SMS_2 0x0004U
5240 #define TIM_SMCR_TS 0x0070U
5241 #define TIM_SMCR_TS_0 0x0010U
5242 #define TIM_SMCR_TS_1 0x0020U
5243 #define TIM_SMCR_TS_2 0x0040U
5245 #define TIM_SMCR_MSM 0x0080U
5247 #define TIM_SMCR_ETF 0x0F00U
5248 #define TIM_SMCR_ETF_0 0x0100U
5249 #define TIM_SMCR_ETF_1 0x0200U
5250 #define TIM_SMCR_ETF_2 0x0400U
5251 #define TIM_SMCR_ETF_3 0x0800U
5253 #define TIM_SMCR_ETPS 0x3000U
5254 #define TIM_SMCR_ETPS_0 0x1000U
5255 #define TIM_SMCR_ETPS_1 0x2000U
5257 #define TIM_SMCR_ECE 0x4000U
5258 #define TIM_SMCR_ETP 0x8000U
5260 /******************* Bit definition for TIM_DIER register *******************/
5261 #define TIM_DIER_UIE 0x0001U
5262 #define TIM_DIER_CC1IE 0x0002U
5263 #define TIM_DIER_CC2IE 0x0004U
5264 #define TIM_DIER_CC3IE 0x0008U
5265 #define TIM_DIER_CC4IE 0x0010U
5266 #define TIM_DIER_COMIE 0x0020U
5267 #define TIM_DIER_TIE 0x0040U
5268 #define TIM_DIER_BIE 0x0080U
5269 #define TIM_DIER_UDE 0x0100U
5270 #define TIM_DIER_CC1DE 0x0200U
5271 #define TIM_DIER_CC2DE 0x0400U
5272 #define TIM_DIER_CC3DE 0x0800U
5273 #define TIM_DIER_CC4DE 0x1000U
5274 #define TIM_DIER_COMDE 0x2000U
5275 #define TIM_DIER_TDE 0x4000U
5277 /******************** Bit definition for TIM_SR register ********************/
5278 #define TIM_SR_UIF 0x0001U
5279 #define TIM_SR_CC1IF 0x0002U
5280 #define TIM_SR_CC2IF 0x0004U
5281 #define TIM_SR_CC3IF 0x0008U
5282 #define TIM_SR_CC4IF 0x0010U
5283 #define TIM_SR_COMIF 0x0020U
5284 #define TIM_SR_TIF 0x0040U
5285 #define TIM_SR_BIF 0x0080U
5286 #define TIM_SR_CC1OF 0x0200U
5287 #define TIM_SR_CC2OF 0x0400U
5288 #define TIM_SR_CC3OF 0x0800U
5289 #define TIM_SR_CC4OF 0x1000U
5291 /******************* Bit definition for TIM_EGR register ********************/
5292 #define TIM_EGR_UG 0x01U
5293 #define TIM_EGR_CC1G 0x02U
5294 #define TIM_EGR_CC2G 0x04U
5295 #define TIM_EGR_CC3G 0x08U
5296 #define TIM_EGR_CC4G 0x10U
5297 #define TIM_EGR_COMG 0x20U
5298 #define TIM_EGR_TG 0x40U
5299 #define TIM_EGR_BG 0x80U
5301 /****************** Bit definition for TIM_CCMR1 register *******************/
5302 #define TIM_CCMR1_CC1S 0x0003U
5303 #define TIM_CCMR1_CC1S_0 0x0001U
5304 #define TIM_CCMR1_CC1S_1 0x0002U
5306 #define TIM_CCMR1_OC1FE 0x0004U
5307 #define TIM_CCMR1_OC1PE 0x0008U
5309 #define TIM_CCMR1_OC1M 0x0070U
5310 #define TIM_CCMR1_OC1M_0 0x0010U
5311 #define TIM_CCMR1_OC1M_1 0x0020U
5312 #define TIM_CCMR1_OC1M_2 0x0040U
5314 #define TIM_CCMR1_OC1CE 0x0080U
5316 #define TIM_CCMR1_CC2S 0x0300U
5317 #define TIM_CCMR1_CC2S_0 0x0100U
5318 #define TIM_CCMR1_CC2S_1 0x0200U
5320 #define TIM_CCMR1_OC2FE 0x0400U
5321 #define TIM_CCMR1_OC2PE 0x0800U
5323 #define TIM_CCMR1_OC2M 0x7000U
5324 #define TIM_CCMR1_OC2M_0 0x1000U
5325 #define TIM_CCMR1_OC2M_1 0x2000U
5326 #define TIM_CCMR1_OC2M_2 0x4000U
5328 #define TIM_CCMR1_OC2CE 0x8000U
5330 /*----------------------------------------------------------------------------*/
5331 
5332 #define TIM_CCMR1_IC1PSC 0x000CU
5333 #define TIM_CCMR1_IC1PSC_0 0x0004U
5334 #define TIM_CCMR1_IC1PSC_1 0x0008U
5336 #define TIM_CCMR1_IC1F 0x00F0U
5337 #define TIM_CCMR1_IC1F_0 0x0010U
5338 #define TIM_CCMR1_IC1F_1 0x0020U
5339 #define TIM_CCMR1_IC1F_2 0x0040U
5340 #define TIM_CCMR1_IC1F_3 0x0080U
5342 #define TIM_CCMR1_IC2PSC 0x0C00U
5343 #define TIM_CCMR1_IC2PSC_0 0x0400U
5344 #define TIM_CCMR1_IC2PSC_1 0x0800U
5346 #define TIM_CCMR1_IC2F 0xF000U
5347 #define TIM_CCMR1_IC2F_0 0x1000U
5348 #define TIM_CCMR1_IC2F_1 0x2000U
5349 #define TIM_CCMR1_IC2F_2 0x4000U
5350 #define TIM_CCMR1_IC2F_3 0x8000U
5352 /****************** Bit definition for TIM_CCMR2 register *******************/
5353 #define TIM_CCMR2_CC3S 0x0003U
5354 #define TIM_CCMR2_CC3S_0 0x0001U
5355 #define TIM_CCMR2_CC3S_1 0x0002U
5357 #define TIM_CCMR2_OC3FE 0x0004U
5358 #define TIM_CCMR2_OC3PE 0x0008U
5360 #define TIM_CCMR2_OC3M 0x0070U
5361 #define TIM_CCMR2_OC3M_0 0x0010U
5362 #define TIM_CCMR2_OC3M_1 0x0020U
5363 #define TIM_CCMR2_OC3M_2 0x0040U
5365 #define TIM_CCMR2_OC3CE 0x0080U
5367 #define TIM_CCMR2_CC4S 0x0300U
5368 #define TIM_CCMR2_CC4S_0 0x0100U
5369 #define TIM_CCMR2_CC4S_1 0x0200U
5371 #define TIM_CCMR2_OC4FE 0x0400U
5372 #define TIM_CCMR2_OC4PE 0x0800U
5374 #define TIM_CCMR2_OC4M 0x7000U
5375 #define TIM_CCMR2_OC4M_0 0x1000U
5376 #define TIM_CCMR2_OC4M_1 0x2000U
5377 #define TIM_CCMR2_OC4M_2 0x4000U
5379 #define TIM_CCMR2_OC4CE 0x8000U
5381 /*----------------------------------------------------------------------------*/
5382 
5383 #define TIM_CCMR2_IC3PSC 0x000CU
5384 #define TIM_CCMR2_IC3PSC_0 0x0004U
5385 #define TIM_CCMR2_IC3PSC_1 0x0008U
5387 #define TIM_CCMR2_IC3F 0x00F0U
5388 #define TIM_CCMR2_IC3F_0 0x0010U
5389 #define TIM_CCMR2_IC3F_1 0x0020U
5390 #define TIM_CCMR2_IC3F_2 0x0040U
5391 #define TIM_CCMR2_IC3F_3 0x0080U
5393 #define TIM_CCMR2_IC4PSC 0x0C00U
5394 #define TIM_CCMR2_IC4PSC_0 0x0400U
5395 #define TIM_CCMR2_IC4PSC_1 0x0800U
5397 #define TIM_CCMR2_IC4F 0xF000U
5398 #define TIM_CCMR2_IC4F_0 0x1000U
5399 #define TIM_CCMR2_IC4F_1 0x2000U
5400 #define TIM_CCMR2_IC4F_2 0x4000U
5401 #define TIM_CCMR2_IC4F_3 0x8000U
5403 /******************* Bit definition for TIM_CCER register *******************/
5404 #define TIM_CCER_CC1E 0x0001U
5405 #define TIM_CCER_CC1P 0x0002U
5406 #define TIM_CCER_CC1NE 0x0004U
5407 #define TIM_CCER_CC1NP 0x0008U
5408 #define TIM_CCER_CC2E 0x0010U
5409 #define TIM_CCER_CC2P 0x0020U
5410 #define TIM_CCER_CC2NE 0x0040U
5411 #define TIM_CCER_CC2NP 0x0080U
5412 #define TIM_CCER_CC3E 0x0100U
5413 #define TIM_CCER_CC3P 0x0200U
5414 #define TIM_CCER_CC3NE 0x0400U
5415 #define TIM_CCER_CC3NP 0x0800U
5416 #define TIM_CCER_CC4E 0x1000U
5417 #define TIM_CCER_CC4P 0x2000U
5418 #define TIM_CCER_CC4NP 0x8000U
5420 /******************* Bit definition for TIM_CNT register ********************/
5421 #define TIM_CNT_CNT 0xFFFFU
5423 /******************* Bit definition for TIM_PSC register ********************/
5424 #define TIM_PSC_PSC 0xFFFFU
5426 /******************* Bit definition for TIM_ARR register ********************/
5427 #define TIM_ARR_ARR 0xFFFFU
5429 /******************* Bit definition for TIM_RCR register ********************/
5430 #define TIM_RCR_REP 0xFFU
5432 /******************* Bit definition for TIM_CCR1 register *******************/
5433 #define TIM_CCR1_CCR1 0xFFFFU
5435 /******************* Bit definition for TIM_CCR2 register *******************/
5436 #define TIM_CCR2_CCR2 0xFFFFU
5438 /******************* Bit definition for TIM_CCR3 register *******************/
5439 #define TIM_CCR3_CCR3 0xFFFFU
5441 /******************* Bit definition for TIM_CCR4 register *******************/
5442 #define TIM_CCR4_CCR4 0xFFFFU
5444 /******************* Bit definition for TIM_BDTR register *******************/
5445 #define TIM_BDTR_DTG 0x00FFU
5446 #define TIM_BDTR_DTG_0 0x0001U
5447 #define TIM_BDTR_DTG_1 0x0002U
5448 #define TIM_BDTR_DTG_2 0x0004U
5449 #define TIM_BDTR_DTG_3 0x0008U
5450 #define TIM_BDTR_DTG_4 0x0010U
5451 #define TIM_BDTR_DTG_5 0x0020U
5452 #define TIM_BDTR_DTG_6 0x0040U
5453 #define TIM_BDTR_DTG_7 0x0080U
5455 #define TIM_BDTR_LOCK 0x0300U
5456 #define TIM_BDTR_LOCK_0 0x0100U
5457 #define TIM_BDTR_LOCK_1 0x0200U
5459 #define TIM_BDTR_OSSI 0x0400U
5460 #define TIM_BDTR_OSSR 0x0800U
5461 #define TIM_BDTR_BKE 0x1000U
5462 #define TIM_BDTR_BKP 0x2000U
5463 #define TIM_BDTR_AOE 0x4000U
5464 #define TIM_BDTR_MOE 0x8000U
5466 /******************* Bit definition for TIM_DCR register ********************/
5467 #define TIM_DCR_DBA 0x001FU
5468 #define TIM_DCR_DBA_0 0x0001U
5469 #define TIM_DCR_DBA_1 0x0002U
5470 #define TIM_DCR_DBA_2 0x0004U
5471 #define TIM_DCR_DBA_3 0x0008U
5472 #define TIM_DCR_DBA_4 0x0010U
5474 #define TIM_DCR_DBL 0x1F00U
5475 #define TIM_DCR_DBL_0 0x0100U
5476 #define TIM_DCR_DBL_1 0x0200U
5477 #define TIM_DCR_DBL_2 0x0400U
5478 #define TIM_DCR_DBL_3 0x0800U
5479 #define TIM_DCR_DBL_4 0x1000U
5481 /******************* Bit definition for TIM_DMAR register *******************/
5482 #define TIM_DMAR_DMAB 0xFFFFU
5484 /******************* Bit definition for TIM_OR register *********************/
5485 #define TIM_OR_TI4_RMP 0x00C0U
5486 #define TIM_OR_TI4_RMP_0 0x0040U
5487 #define TIM_OR_TI4_RMP_1 0x0080U
5488 #define TIM_OR_ITR1_RMP 0x0C00U
5489 #define TIM_OR_ITR1_RMP_0 0x0400U
5490 #define TIM_OR_ITR1_RMP_1 0x0800U
5493 /******************************************************************************/
5494 /* */
5495 /* Universal Synchronous Asynchronous Receiver Transmitter */
5496 /* */
5497 /******************************************************************************/
5498 /******************* Bit definition for USART_SR register *******************/
5499 #define USART_SR_PE 0x0001U
5500 #define USART_SR_FE 0x0002U
5501 #define USART_SR_NE 0x0004U
5502 #define USART_SR_ORE 0x0008U
5503 #define USART_SR_IDLE 0x0010U
5504 #define USART_SR_RXNE 0x0020U
5505 #define USART_SR_TC 0x0040U
5506 #define USART_SR_TXE 0x0080U
5507 #define USART_SR_LBD 0x0100U
5508 #define USART_SR_CTS 0x0200U
5510 /******************* Bit definition for USART_DR register *******************/
5511 #define USART_DR_DR 0x01FFU
5513 /****************** Bit definition for USART_BRR register *******************/
5514 #define USART_BRR_DIV_Fraction 0x000FU
5515 #define USART_BRR_DIV_Mantissa 0xFFF0U
5517 /****************** Bit definition for USART_CR1 register *******************/
5518 #define USART_CR1_SBK 0x0001U
5519 #define USART_CR1_RWU 0x0002U
5520 #define USART_CR1_RE 0x0004U
5521 #define USART_CR1_TE 0x0008U
5522 #define USART_CR1_IDLEIE 0x0010U
5523 #define USART_CR1_RXNEIE 0x0020U
5524 #define USART_CR1_TCIE 0x0040U
5525 #define USART_CR1_TXEIE 0x0080U
5526 #define USART_CR1_PEIE 0x0100U
5527 #define USART_CR1_PS 0x0200U
5528 #define USART_CR1_PCE 0x0400U
5529 #define USART_CR1_WAKE 0x0800U
5530 #define USART_CR1_M 0x1000U
5531 #define USART_CR1_UE 0x2000U
5532 #define USART_CR1_OVER8 0x8000U
5534 /****************** Bit definition for USART_CR2 register *******************/
5535 #define USART_CR2_ADD 0x000FU
5536 #define USART_CR2_LBDL 0x0020U
5537 #define USART_CR2_LBDIE 0x0040U
5538 #define USART_CR2_LBCL 0x0100U
5539 #define USART_CR2_CPHA 0x0200U
5540 #define USART_CR2_CPOL 0x0400U
5541 #define USART_CR2_CLKEN 0x0800U
5543 #define USART_CR2_STOP 0x3000U
5544 #define USART_CR2_STOP_0 0x1000U
5545 #define USART_CR2_STOP_1 0x2000U
5547 #define USART_CR2_LINEN 0x4000U
5549 /****************** Bit definition for USART_CR3 register *******************/
5550 #define USART_CR3_EIE 0x0001U
5551 #define USART_CR3_IREN 0x0002U
5552 #define USART_CR3_IRLP 0x0004U
5553 #define USART_CR3_HDSEL 0x0008U
5554 #define USART_CR3_NACK 0x0010U
5555 #define USART_CR3_SCEN 0x0020U
5556 #define USART_CR3_DMAR 0x0040U
5557 #define USART_CR3_DMAT 0x0080U
5558 #define USART_CR3_RTSE 0x0100U
5559 #define USART_CR3_CTSE 0x0200U
5560 #define USART_CR3_CTSIE 0x0400U
5561 #define USART_CR3_ONEBIT 0x0800U
5563 /****************** Bit definition for USART_GTPR register ******************/
5564 #define USART_GTPR_PSC 0x00FFU
5565 #define USART_GTPR_PSC_0 0x0001U
5566 #define USART_GTPR_PSC_1 0x0002U
5567 #define USART_GTPR_PSC_2 0x0004U
5568 #define USART_GTPR_PSC_3 0x0008U
5569 #define USART_GTPR_PSC_4 0x0010U
5570 #define USART_GTPR_PSC_5 0x0020U
5571 #define USART_GTPR_PSC_6 0x0040U
5572 #define USART_GTPR_PSC_7 0x0080U
5574 #define USART_GTPR_GT 0xFF00U
5576 /******************************************************************************/
5577 /* */
5578 /* Window WATCHDOG */
5579 /* */
5580 /******************************************************************************/
5581 /******************* Bit definition for WWDG_CR register ********************/
5582 #define WWDG_CR_T 0x7FU
5583 #define WWDG_CR_T_0 0x01U
5584 #define WWDG_CR_T_1 0x02U
5585 #define WWDG_CR_T_2 0x04U
5586 #define WWDG_CR_T_3 0x08U
5587 #define WWDG_CR_T_4 0x10U
5588 #define WWDG_CR_T_5 0x20U
5589 #define WWDG_CR_T_6 0x40U
5590 /* Legacy defines */
5591 #define WWDG_CR_T0 WWDG_CR_T_0
5592 #define WWDG_CR_T1 WWDG_CR_T_1
5593 #define WWDG_CR_T2 WWDG_CR_T_2
5594 #define WWDG_CR_T3 WWDG_CR_T_3
5595 #define WWDG_CR_T4 WWDG_CR_T_4
5596 #define WWDG_CR_T5 WWDG_CR_T_5
5597 #define WWDG_CR_T6 WWDG_CR_T_6
5598 
5599 #define WWDG_CR_WDGA 0x80U
5601 /******************* Bit definition for WWDG_CFR register *******************/
5602 #define WWDG_CFR_W 0x007FU
5603 #define WWDG_CFR_W_0 0x0001U
5604 #define WWDG_CFR_W_1 0x0002U
5605 #define WWDG_CFR_W_2 0x0004U
5606 #define WWDG_CFR_W_3 0x0008U
5607 #define WWDG_CFR_W_4 0x0010U
5608 #define WWDG_CFR_W_5 0x0020U
5609 #define WWDG_CFR_W_6 0x0040U
5610 /* Legacy defines */
5611 #define WWDG_CFR_W0 WWDG_CFR_W_0
5612 #define WWDG_CFR_W1 WWDG_CFR_W_1
5613 #define WWDG_CFR_W2 WWDG_CFR_W_2
5614 #define WWDG_CFR_W3 WWDG_CFR_W_3
5615 #define WWDG_CFR_W4 WWDG_CFR_W_4
5616 #define WWDG_CFR_W5 WWDG_CFR_W_5
5617 #define WWDG_CFR_W6 WWDG_CFR_W_6
5618 
5619 #define WWDG_CFR_WDGTB 0x0180U
5620 #define WWDG_CFR_WDGTB_0 0x0080U
5621 #define WWDG_CFR_WDGTB_1 0x0100U
5622 /* Legacy defines */
5623 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
5624 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
5625 
5626 #define WWDG_CFR_EWI 0x0200U
5628 /******************* Bit definition for WWDG_SR register ********************/
5629 #define WWDG_SR_EWIF 0x01U
5632 /******************************************************************************/
5633 /* */
5634 /* DBG */
5635 /* */
5636 /******************************************************************************/
5637 /******************** Bit definition for DBGMCU_IDCODE register *************/
5638 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
5639 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
5640 
5641 /******************** Bit definition for DBGMCU_CR register *****************/
5642 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
5643 #define DBGMCU_CR_DBG_STOP 0x00000002U
5644 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
5645 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
5646 
5647 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
5648 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
5649 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
5651 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
5652 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
5653 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
5654 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
5655 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
5656 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
5657 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
5658 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
5659 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
5660 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
5661 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
5662 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
5663 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
5664 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
5665 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
5666 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
5667 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
5668 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
5669 
5670 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
5671 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
5672 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
5673 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
5674 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
5675 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
5676 
5677 /******************************************************************************/
5678 /* */
5679 /* USB_OTG */
5680 /* */
5681 /******************************************************************************/
5682 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
5683 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
5684 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
5685 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
5686 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
5687 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
5688 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
5689 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
5690 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
5691 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
5692 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
5693 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
5694 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
5695 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
5696 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
5697 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
5698 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
5699 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
5700 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
5702 /******************** Bit definition for USB_OTG_HCFG register **************/
5703 
5704 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
5705 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
5706 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
5707 #define USB_OTG_HCFG_FSLSS 0x00000004U
5709 /******************** Bit definition for USB_OTG_DCFG register **************/
5710 
5711 #define USB_OTG_DCFG_DSPD 0x00000003U
5712 #define USB_OTG_DCFG_DSPD_0 0x00000001U
5713 #define USB_OTG_DCFG_DSPD_1 0x00000002U
5714 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
5716 #define USB_OTG_DCFG_DAD 0x000007F0U
5717 #define USB_OTG_DCFG_DAD_0 0x00000010U
5718 #define USB_OTG_DCFG_DAD_1 0x00000020U
5719 #define USB_OTG_DCFG_DAD_2 0x00000040U
5720 #define USB_OTG_DCFG_DAD_3 0x00000080U
5721 #define USB_OTG_DCFG_DAD_4 0x00000100U
5722 #define USB_OTG_DCFG_DAD_5 0x00000200U
5723 #define USB_OTG_DCFG_DAD_6 0x00000400U
5725 #define USB_OTG_DCFG_PFIVL 0x00001800U
5726 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
5727 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
5729 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
5730 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
5731 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
5733 /******************** Bit definition for USB_OTG_PCGCR register *************/
5734 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
5735 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
5736 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
5738 /******************** Bit definition for USB_OTG_GOTGINT register ***********/
5739 #define USB_OTG_GOTGINT_SEDET 0x00000004U
5740 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
5741 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
5742 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
5743 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
5744 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
5745 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
5747 /******************** Bit definition for USB_OTG_DCTL register **************/
5748 #define USB_OTG_DCTL_RWUSIG 0x00000001U
5749 #define USB_OTG_DCTL_SDIS 0x00000002U
5750 #define USB_OTG_DCTL_GINSTS 0x00000004U
5751 #define USB_OTG_DCTL_GONSTS 0x00000008U
5752 #define USB_OTG_DCTL_TCTL 0x00000070U
5753 #define USB_OTG_DCTL_TCTL_0 0x00000010U
5754 #define USB_OTG_DCTL_TCTL_1 0x00000020U
5755 #define USB_OTG_DCTL_TCTL_2 0x00000040U
5756 #define USB_OTG_DCTL_SGINAK 0x00000080U
5757 #define USB_OTG_DCTL_CGINAK 0x00000100U
5758 #define USB_OTG_DCTL_SGONAK 0x00000200U
5759 #define USB_OTG_DCTL_CGONAK 0x00000400U
5760 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
5762 /******************** Bit definition for USB_OTG_HFIR register **************/
5763 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
5765 /******************** Bit definition for USB_OTG_HFNUM register *************/
5766 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
5767 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
5769 /******************** Bit definition for USB_OTG_DSTS register **************/
5770 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
5772 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
5773 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
5774 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
5775 #define USB_OTG_DSTS_EERR 0x00000008U
5776 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
5778 /******************** Bit definition for USB_OTG_GAHBCFG register ***********/
5779 #define USB_OTG_GAHBCFG_GINT 0x00000001U
5780 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
5781 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
5782 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
5783 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
5784 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
5785 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
5786 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
5787 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
5789 /******************** Bit definition for USB_OTG_GUSBCFG register ***********/
5790 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
5791 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
5792 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
5793 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
5794 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
5795 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
5796 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
5798 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
5799 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
5800 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
5801 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
5802 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
5803 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
5804 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
5805 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
5806 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
5807 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
5808 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
5809 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
5810 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
5811 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
5812 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
5813 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
5814 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
5815 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
5817 /******************** Bit definition for USB_OTG_GRSTCTL register ***********/
5818 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
5819 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
5820 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
5821 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
5822 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
5824 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
5825 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
5826 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
5827 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
5828 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
5829 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
5830 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
5831 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
5833 /******************** Bit definition for USB_OTG_DIEPMSK register ***********/
5834 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
5835 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
5836 #define USB_OTG_DIEPMSK_TOM 0x00000008U
5837 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
5838 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
5839 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
5840 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
5841 #define USB_OTG_DIEPMSK_BIM 0x00000200U
5843 /******************** Bit definition for USB_OTG_HPTXSTS register ***********/
5844 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
5846 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
5847 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
5848 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
5849 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
5850 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
5851 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
5852 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
5853 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
5854 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
5856 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
5857 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
5858 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
5859 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
5860 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
5861 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
5862 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
5863 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
5864 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
5866 /******************** Bit definition for USB_OTG_HAINT register *************/
5867 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
5869 /******************** Bit definition for USB_OTG_DOEPMSK register ***********/
5870 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
5871 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
5872 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
5873 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
5874 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
5875 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
5876 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
5877 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
5879 /******************** Bit definition for USB_OTG_GINTSTS register ***********/
5880 #define USB_OTG_GINTSTS_CMOD 0x00000001U
5881 #define USB_OTG_GINTSTS_MMIS 0x00000002U
5882 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
5883 #define USB_OTG_GINTSTS_SOF 0x00000008U
5884 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
5885 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
5886 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
5887 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
5888 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
5889 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
5890 #define USB_OTG_GINTSTS_USBRST 0x00001000U
5891 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
5892 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
5893 #define USB_OTG_GINTSTS_EOPF 0x00008000U
5894 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
5895 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
5896 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
5897 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
5898 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
5899 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
5900 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
5901 #define USB_OTG_GINTSTS_HCINT 0x02000000U
5902 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
5903 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
5904 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
5905 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
5906 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
5907 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
5909 /******************** Bit definition for USB_OTG_GINTMSK register ***********/
5910 #define USB_OTG_GINTMSK_MMISM 0x00000002U
5911 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
5912 #define USB_OTG_GINTMSK_SOFM 0x00000008U
5913 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
5914 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
5915 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
5916 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
5917 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
5918 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
5919 #define USB_OTG_GINTMSK_USBRST 0x00001000U
5920 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
5921 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
5922 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
5923 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
5924 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
5925 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
5926 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
5927 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
5928 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
5929 #define USB_OTG_GINTMSK_RSTDETM 0x00800000U
5930 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
5931 #define USB_OTG_GINTMSK_HCIM 0x02000000U
5932 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
5933 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
5934 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
5935 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
5936 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
5937 #define USB_OTG_GINTMSK_WUIM 0x80000000U
5939 /******************** Bit definition for USB_OTG_DAINT register *************/
5940 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
5941 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
5943 /******************** Bit definition for USB_OTG_HAINTMSK register **********/
5944 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
5946 /******************** Bit definition for USB_OTG_GRXSTSP register ***********/
5947 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
5948 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
5949 #define USB_OTG_GRXSTSP_DPID 0x00018000U
5950 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
5952 /******************** Bit definition for USB_OTG_DAINTMSK register **********/
5953 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
5954 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
5956 /******************** Bit definition for OTG register ***********************/
5957 
5958 #define USB_OTG_CHNUM 0x0000000FU
5959 #define USB_OTG_CHNUM_0 0x00000001U
5960 #define USB_OTG_CHNUM_1 0x00000002U
5961 #define USB_OTG_CHNUM_2 0x00000004U
5962 #define USB_OTG_CHNUM_3 0x00000008U
5963 #define USB_OTG_BCNT 0x00007FF0U
5965 #define USB_OTG_DPID 0x00018000U
5966 #define USB_OTG_DPID_0 0x00008000U
5967 #define USB_OTG_DPID_1 0x00010000U
5969 #define USB_OTG_PKTSTS 0x001E0000U
5970 #define USB_OTG_PKTSTS_0 0x00020000U
5971 #define USB_OTG_PKTSTS_1 0x00040000U
5972 #define USB_OTG_PKTSTS_2 0x00080000U
5973 #define USB_OTG_PKTSTS_3 0x00100000U
5975 #define USB_OTG_EPNUM 0x0000000FU
5976 #define USB_OTG_EPNUM_0 0x00000001U
5977 #define USB_OTG_EPNUM_1 0x00000002U
5978 #define USB_OTG_EPNUM_2 0x00000004U
5979 #define USB_OTG_EPNUM_3 0x00000008U
5981 #define USB_OTG_FRMNUM 0x01E00000U
5982 #define USB_OTG_FRMNUM_0 0x00200000U
5983 #define USB_OTG_FRMNUM_1 0x00400000U
5984 #define USB_OTG_FRMNUM_2 0x00800000U
5985 #define USB_OTG_FRMNUM_3 0x01000000U
5987 /******************** Bit definition for OTG register ***********************/
5988 #define USB_OTG_CHNUM 0x0000000FU
5989 #define USB_OTG_CHNUM_0 0x00000001U
5990 #define USB_OTG_CHNUM_1 0x00000002U
5991 #define USB_OTG_CHNUM_2 0x00000004U
5992 #define USB_OTG_CHNUM_3 0x00000008U
5993 #define USB_OTG_BCNT 0x00007FF0U
5995 #define USB_OTG_DPID 0x00018000U
5996 #define USB_OTG_DPID_0 0x00008000U
5997 #define USB_OTG_DPID_1 0x00010000U
5999 #define USB_OTG_PKTSTS 0x001E0000U
6000 #define USB_OTG_PKTSTS_0 0x00020000U
6001 #define USB_OTG_PKTSTS_1 0x00040000U
6002 #define USB_OTG_PKTSTS_2 0x00080000U
6003 #define USB_OTG_PKTSTS_3 0x00100000U
6005 #define USB_OTG_EPNUM 0x0000000FU
6006 #define USB_OTG_EPNUM_0 0x00000001U
6007 #define USB_OTG_EPNUM_1 0x00000002U
6008 #define USB_OTG_EPNUM_2 0x00000004U
6009 #define USB_OTG_EPNUM_3 0x00000008U
6011 #define USB_OTG_FRMNUM 0x01E00000U
6012 #define USB_OTG_FRMNUM_0 0x00200000U
6013 #define USB_OTG_FRMNUM_1 0x00400000U
6014 #define USB_OTG_FRMNUM_2 0x00800000U
6015 #define USB_OTG_FRMNUM_3 0x01000000U
6017 /******************** Bit definition for USB_OTG_GRXFSIZ register ***********/
6018 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
6020 /******************** Bit definition for USB_OTG_DVBUSDIS register **********/
6021 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
6023 /******************** Bit definition for OTG register ***********************/
6024 #define USB_OTG_NPTXFSA 0x0000FFFFU
6025 #define USB_OTG_NPTXFD 0xFFFF0000U
6026 #define USB_OTG_TX0FSA 0x0000FFFFU
6027 #define USB_OTG_TX0FD 0xFFFF0000U
6029 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********/
6030 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
6032 /******************** Bit definition for USB_OTG_GNPTXSTS register **********/
6033 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
6035 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
6036 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
6037 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
6038 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
6039 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
6040 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
6041 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
6042 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
6043 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
6045 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
6046 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
6047 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
6048 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
6049 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
6050 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
6051 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
6052 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
6054 /******************** Bit definition for USB_OTG_DTHRCTL register ***********/
6055 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
6056 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
6058 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
6059 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
6060 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
6061 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
6062 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
6063 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
6064 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
6065 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
6066 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
6067 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
6068 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
6070 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
6071 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
6072 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
6073 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
6074 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
6075 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
6076 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
6077 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
6078 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
6079 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
6080 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
6082 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********/
6083 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
6085 /******************** Bit definition for USB_OTG_DEACHINT register **********/
6086 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
6087 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
6089 /******************** Bit definition for USB_OTG_GCCFG register *************/
6090 #define USB_OTG_GCCFG_DCDET 0x00000001U
6091 #define USB_OTG_GCCFG_PDET 0x00000002U
6092 #define USB_OTG_GCCFG_SDET 0x00000004U
6093 #define USB_OTG_GCCFG_PS2DET 0x00000008U
6094 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
6095 #define USB_OTG_GCCFG_BCDEN 0x00020000U
6096 #define USB_OTG_GCCFG_DCDEN 0x00040000U
6097 #define USB_OTG_GCCFG_PDEN 0x00080000U
6098 #define USB_OTG_GCCFG_SDEN 0x00100000U
6099 #define USB_OTG_GCCFG_VBDEN 0x00200000U
6101 /******************** Bit definition for USB_OTG_DEACHINTMSK register *******/
6102 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
6103 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
6105 /******************** Bit definition for USB_OTG_CID register ***************/
6106 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
6108 /******************** Bit definition for USB_OTG_GLPMCFG register ***********/
6109 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
6110 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
6111 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
6112 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
6113 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
6114 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
6115 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
6116 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
6117 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
6118 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
6119 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
6120 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
6121 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
6122 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
6123 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
6125 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******/
6126 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
6127 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
6128 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
6129 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
6130 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
6131 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
6132 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
6133 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
6134 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
6136 /******************** Bit definition for USB_OTG_HPRT register **************/
6137 #define USB_OTG_HPRT_PCSTS 0x00000001U
6138 #define USB_OTG_HPRT_PCDET 0x00000002U
6139 #define USB_OTG_HPRT_PENA 0x00000004U
6140 #define USB_OTG_HPRT_PENCHNG 0x00000008U
6141 #define USB_OTG_HPRT_POCA 0x00000010U
6142 #define USB_OTG_HPRT_POCCHNG 0x00000020U
6143 #define USB_OTG_HPRT_PRES 0x00000040U
6144 #define USB_OTG_HPRT_PSUSP 0x00000080U
6145 #define USB_OTG_HPRT_PRST 0x00000100U
6147 #define USB_OTG_HPRT_PLSTS 0x00000C00U
6148 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
6149 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
6150 #define USB_OTG_HPRT_PPWR 0x00001000U
6152 #define USB_OTG_HPRT_PTCTL 0x0001E000U
6153 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
6154 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
6155 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
6156 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
6158 #define USB_OTG_HPRT_PSPD 0x00060000U
6159 #define USB_OTG_HPRT_PSPD_0 0x00020000U
6160 #define USB_OTG_HPRT_PSPD_1 0x00040000U
6162 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******/
6163 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
6164 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
6165 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
6166 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
6167 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
6168 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
6169 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
6170 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
6171 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
6172 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
6173 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
6175 /******************** Bit definition for USB_OTG_HPTXFSIZ register **********/
6176 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
6177 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
6179 /******************** Bit definition for USB_OTG_DIEPCTL register ***********/
6180 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
6181 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
6182 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
6183 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
6185 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
6186 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
6187 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
6188 #define USB_OTG_DIEPCTL_STALL 0x00200000U
6190 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
6191 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
6192 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
6193 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
6194 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
6195 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
6196 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
6197 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
6198 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
6199 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
6200 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
6202 /******************** Bit definition for USB_OTG_HCCHAR register ************/
6203 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
6205 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
6206 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
6207 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
6208 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
6209 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
6210 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
6211 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
6213 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
6214 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
6215 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
6217 #define USB_OTG_HCCHAR_MC 0x00300000U
6218 #define USB_OTG_HCCHAR_MC_0 0x00100000U
6219 #define USB_OTG_HCCHAR_MC_1 0x00200000U
6221 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
6222 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
6223 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
6224 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
6225 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
6226 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
6227 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
6228 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
6229 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
6230 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
6231 #define USB_OTG_HCCHAR_CHENA 0x80000000U
6233 /******************** Bit definition for USB_OTG_HCSPLT register ************/
6234 
6235 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
6236 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
6237 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
6238 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
6239 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
6240 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
6241 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
6242 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
6244 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
6245 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
6246 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
6247 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
6248 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
6249 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
6250 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
6251 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
6253 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
6254 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
6255 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
6256 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
6257 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
6259 /******************** Bit definition for USB_OTG_HCINT register *************/
6260 #define USB_OTG_HCINT_XFRC 0x00000001U
6261 #define USB_OTG_HCINT_CHH 0x00000002U
6262 #define USB_OTG_HCINT_AHBERR 0x00000004U
6263 #define USB_OTG_HCINT_STALL 0x00000008U
6264 #define USB_OTG_HCINT_NAK 0x00000010U
6265 #define USB_OTG_HCINT_ACK 0x00000020U
6266 #define USB_OTG_HCINT_NYET 0x00000040U
6267 #define USB_OTG_HCINT_TXERR 0x00000080U
6268 #define USB_OTG_HCINT_BBERR 0x00000100U
6269 #define USB_OTG_HCINT_FRMOR 0x00000200U
6270 #define USB_OTG_HCINT_DTERR 0x00000400U
6272 /******************** Bit definition for USB_OTG_DIEPINT register ***********/
6273 #define USB_OTG_DIEPINT_XFRC 0x00000001U
6274 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
6275 #define USB_OTG_DIEPINT_TOC 0x00000008U
6276 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
6277 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
6278 #define USB_OTG_DIEPINT_TXFE 0x00000080U
6279 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
6280 #define USB_OTG_DIEPINT_BNA 0x00000200U
6281 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
6282 #define USB_OTG_DIEPINT_BERR 0x00001000U
6283 #define USB_OTG_DIEPINT_NAK 0x00002000U
6285 /******************** Bit definition for USB_OTG_HCINTMSK register **********/
6286 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
6287 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
6288 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
6289 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
6290 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
6291 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
6292 #define USB_OTG_HCINTMSK_NYET 0x00000040U
6293 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
6294 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
6295 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
6296 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
6298 /******************** Bit definition for USB_OTG_DIEPTSIZ register **********/
6299 
6300 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
6301 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
6302 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
6303 /******************** Bit definition for USB_OTG_HCTSIZ register ************/
6304 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
6305 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
6306 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
6307 #define USB_OTG_HCTSIZ_DPID 0x60000000U
6308 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
6309 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
6311 /******************** Bit definition for USB_OTG_DIEPDMA register ***********/
6312 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
6314 /******************** Bit definition for USB_OTG_HCDMA register *************/
6315 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
6317 /******************** Bit definition for USB_OTG_DTXFSTS register ***********/
6318 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
6320 /******************** Bit definition for USB_OTG_DIEPTXF register ***********/
6321 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
6322 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
6324 /******************** Bit definition for USB_OTG_DOEPCTL register ***********/
6325 
6326 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
6327 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
6328 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
6329 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
6330 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
6331 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
6332 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
6333 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
6334 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
6335 #define USB_OTG_DOEPCTL_STALL 0x00200000U
6336 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
6337 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
6338 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
6339 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
6341 /******************** Bit definition for USB_OTG_DOEPINT register ***********/
6342 #define USB_OTG_DOEPINT_XFRC 0x00000001U
6343 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
6344 #define USB_OTG_DOEPINT_STUP 0x00000008U
6345 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
6346 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
6347 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
6348 #define USB_OTG_DOEPINT_NYET 0x00004000U
6350 /******************** Bit definition for USB_OTG_DOEPTSIZ register **********/
6351 
6352 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
6353 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
6355 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
6356 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
6357 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
6359 /******************** Bit definition for PCGCCTL register *******************/
6360 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
6361 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
6362 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
6376 /******************************* ADC Instances ********************************/
6377 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
6378 
6379 /******************************* CAN Instances ********************************/
6380 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
6381  ((INSTANCE) == CAN2))
6382 /****************************** DFSDM Instances *******************************/
6383 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
6384  ((INSTANCE) == DFSDM1_Filter1))
6385 
6386 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
6387  ((INSTANCE) == DFSDM1_Channel1) || \
6388  ((INSTANCE) == DFSDM1_Channel2) || \
6389  ((INSTANCE) == DFSDM1_Channel3))
6390 
6391 /******************************* CRC Instances ********************************/
6392 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
6393 
6394 /******************************** DMA Instances *******************************/
6395 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
6396  ((INSTANCE) == DMA1_Stream1) || \
6397  ((INSTANCE) == DMA1_Stream2) || \
6398  ((INSTANCE) == DMA1_Stream3) || \
6399  ((INSTANCE) == DMA1_Stream4) || \
6400  ((INSTANCE) == DMA1_Stream5) || \
6401  ((INSTANCE) == DMA1_Stream6) || \
6402  ((INSTANCE) == DMA1_Stream7) || \
6403  ((INSTANCE) == DMA2_Stream0) || \
6404  ((INSTANCE) == DMA2_Stream1) || \
6405  ((INSTANCE) == DMA2_Stream2) || \
6406  ((INSTANCE) == DMA2_Stream3) || \
6407  ((INSTANCE) == DMA2_Stream4) || \
6408  ((INSTANCE) == DMA2_Stream5) || \
6409  ((INSTANCE) == DMA2_Stream6) || \
6410  ((INSTANCE) == DMA2_Stream7))
6411 
6412 /******************************* GPIO Instances *******************************/
6413 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
6414  ((INSTANCE) == GPIOB) || \
6415  ((INSTANCE) == GPIOC) || \
6416  ((INSTANCE) == GPIOD) || \
6417  ((INSTANCE) == GPIOE) || \
6418  ((INSTANCE) == GPIOF) || \
6419  ((INSTANCE) == GPIOG) || \
6420  ((INSTANCE) == GPIOH))
6421 
6422 /******************************** I2C Instances *******************************/
6423 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
6424  ((INSTANCE) == I2C2) || \
6425  ((INSTANCE) == I2C3))
6426 
6427 /******************************** I2S Instances *******************************/
6428 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
6429  ((INSTANCE) == SPI2) || \
6430  ((INSTANCE) == SPI3) || \
6431  ((INSTANCE) == SPI4) || \
6432  ((INSTANCE) == SPI5))
6433 
6434 /*************************** I2S Extended Instances ***************************/
6435 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
6436  ((INSTANCE) == SPI3) || \
6437  ((INSTANCE) == I2S2ext) || \
6438  ((INSTANCE) == I2S3ext))
6439 
6440 /******************************* RNG Instances ********************************/
6441 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
6442 
6443 /****************************** RTC Instances *********************************/
6444 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
6445 
6446 /******************************** SPI Instances *******************************/
6447 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
6448  ((INSTANCE) == SPI2) || \
6449  ((INSTANCE) == SPI3) || \
6450  ((INSTANCE) == SPI4) || \
6451  ((INSTANCE) == SPI5))
6452 /*************************** SPI Extended Instances ***************************/
6453 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
6454  ((INSTANCE) == SPI2) || \
6455  ((INSTANCE) == SPI3) || \
6456  ((INSTANCE) == SPI4) || \
6457  ((INSTANCE) == SPI5) || \
6458  ((INSTANCE) == I2S2ext) || \
6459  ((INSTANCE) == I2S3ext))
6460 
6461 /****************** TIM Instances : All supported instances *******************/
6462 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6463  ((INSTANCE) == TIM2) || \
6464  ((INSTANCE) == TIM3) || \
6465  ((INSTANCE) == TIM4) || \
6466  ((INSTANCE) == TIM5) || \
6467  ((INSTANCE) == TIM6) || \
6468  ((INSTANCE) == TIM7) || \
6469  ((INSTANCE) == TIM8) || \
6470  ((INSTANCE) == TIM9) || \
6471  ((INSTANCE) == TIM10) || \
6472  ((INSTANCE) == TIM11) || \
6473  ((INSTANCE) == TIM12) || \
6474  ((INSTANCE) == TIM13) || \
6475  ((INSTANCE) == TIM14))
6476 
6477 /************* TIM Instances : at least 1 capture/compare channel *************/
6478 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6479  ((INSTANCE) == TIM2) || \
6480  ((INSTANCE) == TIM3) || \
6481  ((INSTANCE) == TIM4) || \
6482  ((INSTANCE) == TIM5) || \
6483  ((INSTANCE) == TIM8) || \
6484  ((INSTANCE) == TIM9) || \
6485  ((INSTANCE) == TIM10) || \
6486  ((INSTANCE) == TIM11) || \
6487  ((INSTANCE) == TIM12) || \
6488  ((INSTANCE) == TIM13) || \
6489  ((INSTANCE) == TIM14))
6490 
6491 /************ TIM Instances : at least 2 capture/compare channels *************/
6492 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6493  ((INSTANCE) == TIM2) || \
6494  ((INSTANCE) == TIM3) || \
6495  ((INSTANCE) == TIM4) || \
6496  ((INSTANCE) == TIM5) || \
6497  ((INSTANCE) == TIM8) || \
6498  ((INSTANCE) == TIM9) || \
6499  ((INSTANCE) == TIM12))
6500 
6501 /************ TIM Instances : at least 3 capture/compare channels *************/
6502 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6503  ((INSTANCE) == TIM2) || \
6504  ((INSTANCE) == TIM3) || \
6505  ((INSTANCE) == TIM4) || \
6506  ((INSTANCE) == TIM5) || \
6507  ((INSTANCE) == TIM8))
6508 
6509 /************ TIM Instances : at least 4 capture/compare channels *************/
6510 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6511  ((INSTANCE) == TIM2) || \
6512  ((INSTANCE) == TIM3) || \
6513  ((INSTANCE) == TIM4) || \
6514  ((INSTANCE) == TIM5) || \
6515  ((INSTANCE) == TIM8))
6516 
6517 /******************** TIM Instances : Advanced-control timers *****************/
6518 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6519  ((INSTANCE) == TIM8))
6520 
6521 /******************* TIM Instances : Timer input XOR function *****************/
6522 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6523  ((INSTANCE) == TIM2) || \
6524  ((INSTANCE) == TIM3) || \
6525  ((INSTANCE) == TIM4) || \
6526  ((INSTANCE) == TIM5) || \
6527  ((INSTANCE) == TIM8))
6528 
6529 /****************** TIM Instances : DMA requests generation (UDE) *************/
6530 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6531  ((INSTANCE) == TIM2) || \
6532  ((INSTANCE) == TIM3) || \
6533  ((INSTANCE) == TIM4) || \
6534  ((INSTANCE) == TIM5) || \
6535  ((INSTANCE) == TIM6) || \
6536  ((INSTANCE) == TIM7) || \
6537  ((INSTANCE) == TIM8))
6538 
6539 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
6540 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6541  ((INSTANCE) == TIM2) || \
6542  ((INSTANCE) == TIM3) || \
6543  ((INSTANCE) == TIM4) || \
6544  ((INSTANCE) == TIM5) || \
6545  ((INSTANCE) == TIM8))
6546 
6547 /************ TIM Instances : DMA requests generation (COMDE) *****************/
6548 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6549  ((INSTANCE) == TIM2) || \
6550  ((INSTANCE) == TIM3) || \
6551  ((INSTANCE) == TIM4) || \
6552  ((INSTANCE) == TIM5) || \
6553  ((INSTANCE) == TIM8))
6554 
6555 /******************** TIM Instances : DMA burst feature ***********************/
6556 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6557  ((INSTANCE) == TIM2) || \
6558  ((INSTANCE) == TIM3) || \
6559  ((INSTANCE) == TIM4) || \
6560  ((INSTANCE) == TIM5) || \
6561  ((INSTANCE) == TIM8))
6562 
6563 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
6564 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6565  ((INSTANCE) == TIM2) || \
6566  ((INSTANCE) == TIM3) || \
6567  ((INSTANCE) == TIM4) || \
6568  ((INSTANCE) == TIM5) || \
6569  ((INSTANCE) == TIM6) || \
6570  ((INSTANCE) == TIM7) || \
6571  ((INSTANCE) == TIM8) || \
6572  ((INSTANCE) == TIM9) || \
6573  ((INSTANCE) == TIM12))
6574 
6575 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
6576 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6577  ((INSTANCE) == TIM2) || \
6578  ((INSTANCE) == TIM3) || \
6579  ((INSTANCE) == TIM4) || \
6580  ((INSTANCE) == TIM5) || \
6581  ((INSTANCE) == TIM8) || \
6582  ((INSTANCE) == TIM9) || \
6583  ((INSTANCE) == TIM12))
6584 
6585 /********************** TIM Instances : 32 bit Counter ************************/
6586 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
6587  ((INSTANCE) == TIM5))
6588 
6589 /***************** TIM Instances : external trigger input available ************/
6590 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
6591  ((INSTANCE) == TIM2) || \
6592  ((INSTANCE) == TIM3) || \
6593  ((INSTANCE) == TIM4) || \
6594  ((INSTANCE) == TIM5) || \
6595  ((INSTANCE) == TIM8))
6596 
6597 /****************** TIM Instances : remapping capability **********************/
6598 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
6599  ((INSTANCE) == TIM5) || \
6600  ((INSTANCE) == TIM11))
6601 
6602 /******************* TIM Instances : output(s) available **********************/
6603 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
6604  ((((INSTANCE) == TIM1) && \
6605  (((CHANNEL) == TIM_CHANNEL_1) || \
6606  ((CHANNEL) == TIM_CHANNEL_2) || \
6607  ((CHANNEL) == TIM_CHANNEL_3) || \
6608  ((CHANNEL) == TIM_CHANNEL_4))) \
6609  || \
6610  (((INSTANCE) == TIM2) && \
6611  (((CHANNEL) == TIM_CHANNEL_1) || \
6612  ((CHANNEL) == TIM_CHANNEL_2) || \
6613  ((CHANNEL) == TIM_CHANNEL_3) || \
6614  ((CHANNEL) == TIM_CHANNEL_4))) \
6615  || \
6616  (((INSTANCE) == TIM3) && \
6617  (((CHANNEL) == TIM_CHANNEL_1) || \
6618  ((CHANNEL) == TIM_CHANNEL_2) || \
6619  ((CHANNEL) == TIM_CHANNEL_3) || \
6620  ((CHANNEL) == TIM_CHANNEL_4))) \
6621  || \
6622  (((INSTANCE) == TIM4) && \
6623  (((CHANNEL) == TIM_CHANNEL_1) || \
6624  ((CHANNEL) == TIM_CHANNEL_2) || \
6625  ((CHANNEL) == TIM_CHANNEL_3) || \
6626  ((CHANNEL) == TIM_CHANNEL_4))) \
6627  || \
6628  (((INSTANCE) == TIM5) && \
6629  (((CHANNEL) == TIM_CHANNEL_1) || \
6630  ((CHANNEL) == TIM_CHANNEL_2) || \
6631  ((CHANNEL) == TIM_CHANNEL_3) || \
6632  ((CHANNEL) == TIM_CHANNEL_4))) \
6633  || \
6634  (((INSTANCE) == TIM8) && \
6635  (((CHANNEL) == TIM_CHANNEL_1) || \
6636  ((CHANNEL) == TIM_CHANNEL_2) || \
6637  ((CHANNEL) == TIM_CHANNEL_3) || \
6638  ((CHANNEL) == TIM_CHANNEL_4))) \
6639  || \
6640  (((INSTANCE) == TIM9) && \
6641  (((CHANNEL) == TIM_CHANNEL_1) || \
6642  ((CHANNEL) == TIM_CHANNEL_2))) \
6643  || \
6644  (((INSTANCE) == TIM10) && \
6645  (((CHANNEL) == TIM_CHANNEL_1))) \
6646  || \
6647  (((INSTANCE) == TIM11) && \
6648  (((CHANNEL) == TIM_CHANNEL_1))) \
6649  || \
6650  (((INSTANCE) == TIM12) && \
6651  (((CHANNEL) == TIM_CHANNEL_1) || \
6652  ((CHANNEL) == TIM_CHANNEL_2))) \
6653  || \
6654  (((INSTANCE) == TIM13) && \
6655  (((CHANNEL) == TIM_CHANNEL_1))) \
6656  || \
6657  (((INSTANCE) == TIM14) && \
6658  (((CHANNEL) == TIM_CHANNEL_1))))
6659 
6660 /************ TIM Instances : complementary output(s) available ***************/
6661 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
6662  ((((INSTANCE) == TIM1) && \
6663  (((CHANNEL) == TIM_CHANNEL_1) || \
6664  ((CHANNEL) == TIM_CHANNEL_2) || \
6665  ((CHANNEL) == TIM_CHANNEL_3))) \
6666  || \
6667  (((INSTANCE) == TIM8) && \
6668  (((CHANNEL) == TIM_CHANNEL_1) || \
6669  ((CHANNEL) == TIM_CHANNEL_2) || \
6670  ((CHANNEL) == TIM_CHANNEL_3))))
6671 
6672 /******************** USART Instances : Synchronous mode **********************/
6673 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6674  ((INSTANCE) == USART2))
6675 
6676 /******************** UART Instances : Asynchronous mode **********************/
6677 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6678  ((INSTANCE) == USART2) || \
6679  ((INSTANCE) == USART6))
6680 
6681 /****************** UART Instances : Hardware Flow control ********************/
6682 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6683  ((INSTANCE) == USART2))
6684 
6685 /********************* UART Instances : Smart card mode ***********************/
6686 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6687  ((INSTANCE) == USART2) || \
6688  ((INSTANCE) == USART6))
6689 
6690 /*********************** UART Instances : IRDA mode ***************************/
6691 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6692  ((INSTANCE) == USART2) || \
6693  ((INSTANCE) == USART6))
6694 
6695 /*********************** PCD Instances ****************************************/
6696 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
6697 
6698 /*********************** HCD Instances ****************************************/
6699 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
6700 
6701 /****************************** IWDG Instances ********************************/
6702 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
6703 
6704 /****************************** WWDG Instances ********************************/
6705 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
6706 
6707 /***************************** FMPI2C Instances *******************************/
6708 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
6709 
6710 /****************************** SDIO Instances ********************************/
6711 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
6712 
6713 /****************************** USB Instances ********************************/
6714 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
6715 
6716 /****************************** USB Exported Constants ************************/
6717 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
6718 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
6719 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
6720 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
6721 
6722 
6735 #ifdef __cplusplus
6736 }
6737 #endif /* __cplusplus */
6738 
6739 #endif /* __STM32F412Cx_H */
6740 
6741 
6742 
6743 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DFSDM_Filter_TypeDef::FLTICR
__IO uint32_t FLTICR
Definition: stm32f412cx.h:304
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
TAMP_STAMP_IRQn
Definition: stm32f412cx.h:99
USB_OTG_GlobalTypeDef::Reserved
uint32_t Reserved
Definition: stm32f412cx.h:710
TIM2_IRQn
Definition: stm32f412cx.h:125
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f412cx.h:123
EXTI2_IRQn
Definition: stm32f412cx.h:105
EXTI4_IRQn
Definition: stm32f412cx.h:107
USART1_IRQn
Definition: stm32f412cx.h:134
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
DFSDM1_FLT1_IRQn
Definition: stm32f412cx.h:155
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f412cx.h:141
TIM4_IRQn
Definition: stm32f412cx.h:127
DFSDM_Filter_TypeDef::FLTAWLTR
__IO uint32_t FLTAWLTR
Definition: stm32f412cx.h:310
RTC_Alarm_IRQn
Definition: stm32f412cx.h:137
CAN2_SCE_IRQn
Definition: stm32f412cx.h:159
DFSDM_Filter_TypeDef::FLTEXMAX
__IO uint32_t FLTEXMAX
Definition: stm32f412cx.h:313
PendSV_IRQn
Definition: stm32f412cx.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f412cx.h:100
CAN1_RX1_IRQn
Definition: stm32f412cx.h:118
USB_OTG_GlobalTypeDef::GLPMCFG
__IO uint32_t GLPMCFG
Definition: stm32f412cx.h:709
CAN1_TX_IRQn
Definition: stm32f412cx.h:116
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f412cx.h:132
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
OTG_FS_WKUP_IRQn
Definition: stm32f412cx.h:138
DMA_TypeDef
Definition: stm32f401xc.h:243
DMA1_Stream2_IRQn
Definition: stm32f412cx.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f412cx.h:133
FMPI2C1_ER_IRQn
Definition: stm32f412cx.h:172
DFSDM_Filter_TypeDef::FLTFCR
__IO uint32_t FLTFCR
Definition: stm32f412cx.h:306
__I
#define __I
Definition: core_cm0.h:210
RNG_IRQn
Definition: stm32f412cx.h:167
DMA2_Stream5_IRQn
Definition: stm32f412cx.h:161
ADC_IRQn
Definition: stm32f412cx.h:115
CAN1_RX0_IRQn
Definition: stm32f412cx.h:117
TIM6_IRQn
Definition: stm32f412cx.h:147
RCC_IRQn
Definition: stm32f412cx.h:102
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f412cx.h:93
DMA2_Stream3_IRQn
Definition: stm32f412cx.h:152
DFSDM_Channel_TypeDef::CHWDATAR
__IO uint32_t CHWDATAR
Definition: stm32f412cx.h:327
NonMaskableInt_IRQn
Definition: stm32f412cx.h:88
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f412cx.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f412cx.h:140
DMA1_Stream1_IRQn
Definition: stm32f412cx.h:109
DMA2_Stream7_IRQn
Definition: stm32f412cx.h:163
DMA2_Stream6_IRQn
Definition: stm32f412cx.h:162
DFSDM_Filter_TypeDef::FLTCR2
__IO uint32_t FLTCR2
Definition: stm32f412cx.h:302
BusFault_IRQn
Definition: stm32f412cx.h:90
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
DFSDM_Filter_TypeDef::FLTAWHTR
__IO uint32_t FLTAWHTR
Definition: stm32f412cx.h:309
I2C3_ER_IRQn
Definition: stm32f412cx.h:166
CAN2_RX0_IRQn
Definition: stm32f412cx.h:157
USART6_IRQn
Definition: stm32f412cx.h:164
PVD_IRQn
Definition: stm32f412cx.h:98
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f412cx.h:112
DFSDM_Filter_TypeDef::FLTISR
__IO uint32_t FLTISR
Definition: stm32f412cx.h:303
DFSDM_Channel_TypeDef::CHDATINR
__IO uint32_t CHDATINR
Definition: stm32f412cx.h:328
DMA1_Stream0_IRQn
Definition: stm32f412cx.h:108
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f412cx.h:169
TIM8_CC_IRQn
Definition: stm32f412cx.h:142
DMA1_Stream3_IRQn
Definition: stm32f412cx.h:111
FPU_IRQn
Definition: stm32f412cx.h:168
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
OTG_FS_IRQn
Definition: stm32f412cx.h:160
DMA2_Stream2_IRQn
Definition: stm32f412cx.h:151
DFSDM_Filter_TypeDef::FLTJCHGR
__IO uint32_t FLTJCHGR
Definition: stm32f412cx.h:305
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f412cx.h:144
FMPI2C1_EV_IRQn
Definition: stm32f412cx.h:171
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32f412cx.h:299
I2C3_EV_IRQn
Definition: stm32f412cx.h:165
DFSDM_Filter_TypeDef::FLTJDATAR
__IO uint32_t FLTJDATAR
Definition: stm32f412cx.h:307
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f412cx.h:135
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
DFSDM_Filter_TypeDef::FLTRDATAR
__IO uint32_t FLTRDATAR
Definition: stm32f412cx.h:308
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f412cx.h:148
I2C2_EV_IRQn
Definition: stm32f412cx.h:130
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f412cx.h:126
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f412cx.h:104
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32f412cx.h:321
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
USB_OTG_GlobalTypeDef::Reserved6
uint32_t Reserved6
Definition: stm32f412cx.h:708
SVCall_IRQn
Definition: stm32f412cx.h:92
DFSDM_Channel_TypeDef::CHCFGR2
__IO uint32_t CHCFGR2
Definition: stm32f412cx.h:324
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f412cx.h:124
DFSDM1_FLT0_IRQn
Definition: stm32f412cx.h:154
TIM8_BRK_TIM12_IRQn
Definition: stm32f412cx.h:139
DFSDM_Channel_TypeDef::CHAWSCDR
__IO uint32_t CHAWSCDR
Definition: stm32f412cx.h:325
FLASH_IRQn
Definition: stm32f412cx.h:101
DMA1_Stream5_IRQn
Definition: stm32f412cx.h:113
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f412cx.h:95
DFSDM_Filter_TypeDef::FLTEXMIN
__IO uint32_t FLTEXMIN
Definition: stm32f412cx.h:314
TIM1_UP_TIM10_IRQn
Definition: stm32f412cx.h:122
DFSDM_Filter_TypeDef::FLTAWCFR
__IO uint32_t FLTAWCFR
Definition: stm32f412cx.h:312
USB_OTG_GlobalTypeDef::GDFIFOCFG
__IO uint32_t GDFIFOCFG
Definition: stm32f412cx.h:711
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f412cx.h:131
UsageFault_IRQn
Definition: stm32f412cx.h:91
SPI3_IRQn
Definition: stm32f412cx.h:146
DFSDM_Channel_TypeDef::CHCFGR1
__IO uint32_t CHCFGR1
Definition: stm32f412cx.h:323
DMA2_Stream1_IRQn
Definition: stm32f412cx.h:150
EXTI9_5_IRQn
Definition: stm32f412cx.h:120
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f412cx.h:128
DMA1_Stream6_IRQn
Definition: stm32f412cx.h:114
DFSDM_Filter_TypeDef::FLTAWSR
__IO uint32_t FLTAWSR
Definition: stm32f412cx.h:311
I2C1_ER_IRQn
Definition: stm32f412cx.h:129
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
USB_OTG_GlobalTypeDef::GHWCFG3
__IO uint32_t GHWCFG3
Definition: stm32f412cx.h:707
FMPI2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f410cx.h:354
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
DFSDM_Filter_TypeDef::FLTCR1
__IO uint32_t FLTCR1
Definition: stm32f412cx.h:301
CAN2_RX1_IRQn
Definition: stm32f412cx.h:158
DMA2_Stream4_IRQn
Definition: stm32f412cx.h:153
WWDG_IRQn
Definition: stm32f412cx.h:97
DMA1_Stream7_IRQn
Definition: stm32f412cx.h:143
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
SPI5_IRQn
Definition: stm32f412cx.h:170
EXTI15_10_IRQn
Definition: stm32f412cx.h:136
DFSDM_Filter_TypeDef::FLTCNVTIMR
__IO uint32_t FLTCNVTIMR
Definition: stm32f412cx.h:315
CAN1_SCE_IRQn
Definition: stm32f412cx.h:119
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f412cx.h:103
DMA2_Stream0_IRQn
Definition: stm32f412cx.h:149
TIM1_BRK_TIM9_IRQn
Definition: stm32f412cx.h:121
CAN2_TX_IRQn
Definition: stm32f412cx.h:156
TIM5_IRQn
Definition: stm32f412cx.h:145
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f412cx.h:106
MemoryManagement_IRQn
Definition: stm32f412cx.h:89