STM CMSIS
stm32f412rx.h
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1 
52 #ifndef __STM32F412Rx_H
53 #define __STM32F412Rx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  CAN1_TX_IRQn = 19,
117  CAN1_RX0_IRQn = 20,
118  CAN1_RX1_IRQn = 21,
119  CAN1_SCE_IRQn = 22,
120  EXTI9_5_IRQn = 23,
121  TIM1_BRK_TIM9_IRQn = 24,
122  TIM1_UP_TIM10_IRQn = 25,
123  TIM1_TRG_COM_TIM11_IRQn = 26,
124  TIM1_CC_IRQn = 27,
125  TIM2_IRQn = 28,
126  TIM3_IRQn = 29,
127  TIM4_IRQn = 30,
128  I2C1_EV_IRQn = 31,
129  I2C1_ER_IRQn = 32,
130  I2C2_EV_IRQn = 33,
131  I2C2_ER_IRQn = 34,
132  SPI1_IRQn = 35,
133  SPI2_IRQn = 36,
134  USART1_IRQn = 37,
135  USART2_IRQn = 38,
136  USART3_IRQn = 39,
137  EXTI15_10_IRQn = 40,
138  RTC_Alarm_IRQn = 41,
139  OTG_FS_WKUP_IRQn = 42,
140  TIM8_BRK_TIM12_IRQn = 43,
141  TIM8_UP_TIM13_IRQn = 44,
142  TIM8_TRG_COM_TIM14_IRQn = 45,
143  TIM8_CC_IRQn = 46,
144  DMA1_Stream7_IRQn = 47,
145  SDIO_IRQn = 49,
146  TIM5_IRQn = 50,
147  SPI3_IRQn = 51,
148  TIM6_IRQn = 54,
149  TIM7_IRQn = 55,
150  DMA2_Stream0_IRQn = 56,
151  DMA2_Stream1_IRQn = 57,
152  DMA2_Stream2_IRQn = 58,
153  DMA2_Stream3_IRQn = 59,
154  DMA2_Stream4_IRQn = 60,
155  DFSDM1_FLT0_IRQn = 61,
156  DFSDM1_FLT1_IRQn = 62,
157  CAN2_TX_IRQn = 63,
158  CAN2_RX0_IRQn = 64,
159  CAN2_RX1_IRQn = 65,
160  CAN2_SCE_IRQn = 66,
161  OTG_FS_IRQn = 67,
162  DMA2_Stream5_IRQn = 68,
163  DMA2_Stream6_IRQn = 69,
164  DMA2_Stream7_IRQn = 70,
165  USART6_IRQn = 71,
166  I2C3_EV_IRQn = 72,
167  I2C3_ER_IRQn = 73,
168  RNG_IRQn = 80,
169  FPU_IRQn = 81,
170  SPI4_IRQn = 84,
171  SPI5_IRQn = 85,
172  QUADSPI_IRQn = 92,
173  FMPI2C1_EV_IRQn = 95,
174  FMPI2C1_ER_IRQn = 96
175 } IRQn_Type;
176 
181 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
182 #include "system_stm32f4xx.h"
183 #include <stdint.h>
184 
193 typedef struct
194 {
195  __IO uint32_t SR;
196  __IO uint32_t CR1;
197  __IO uint32_t CR2;
198  __IO uint32_t SMPR1;
199  __IO uint32_t SMPR2;
200  __IO uint32_t JOFR1;
201  __IO uint32_t JOFR2;
202  __IO uint32_t JOFR3;
203  __IO uint32_t JOFR4;
204  __IO uint32_t HTR;
205  __IO uint32_t LTR;
206  __IO uint32_t SQR1;
207  __IO uint32_t SQR2;
208  __IO uint32_t SQR3;
209  __IO uint32_t JSQR;
210  __IO uint32_t JDR1;
211  __IO uint32_t JDR2;
212  __IO uint32_t JDR3;
213  __IO uint32_t JDR4;
214  __IO uint32_t DR;
215 } ADC_TypeDef;
216 
217 typedef struct
218 {
219  __IO uint32_t CSR;
220  __IO uint32_t CCR;
221  __IO uint32_t CDR;
223 } ADC_Common_TypeDef;
224 
229 typedef struct
230 {
231  __IO uint32_t TIR;
232  __IO uint32_t TDTR;
233  __IO uint32_t TDLR;
234  __IO uint32_t TDHR;
235 } CAN_TxMailBox_TypeDef;
236 
241 typedef struct
242 {
243  __IO uint32_t RIR;
244  __IO uint32_t RDTR;
245  __IO uint32_t RDLR;
246  __IO uint32_t RDHR;
247 } CAN_FIFOMailBox_TypeDef;
248 
253 typedef struct
254 {
255  __IO uint32_t FR1;
256  __IO uint32_t FR2;
257 } CAN_FilterRegister_TypeDef;
258 
259 typedef struct
260 {
261  __IO uint32_t MCR;
262  __IO uint32_t MSR;
263  __IO uint32_t TSR;
264  __IO uint32_t RF0R;
265  __IO uint32_t RF1R;
266  __IO uint32_t IER;
267  __IO uint32_t ESR;
268  __IO uint32_t BTR;
269  uint32_t RESERVED0[88];
270  CAN_TxMailBox_TypeDef sTxMailBox[3];
271  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
272  uint32_t RESERVED1[12];
273  __IO uint32_t FMR;
274  __IO uint32_t FM1R;
275  uint32_t RESERVED2;
276  __IO uint32_t FS1R;
277  uint32_t RESERVED3;
278  __IO uint32_t FFA1R;
279  uint32_t RESERVED4;
280  __IO uint32_t FA1R;
281  uint32_t RESERVED5[8];
282  CAN_FilterRegister_TypeDef sFilterRegister[28];
283 } CAN_TypeDef;
284 
289 typedef struct
290 {
291  __IO uint32_t DR;
292  __IO uint8_t IDR;
293  uint8_t RESERVED0;
294  uint16_t RESERVED1;
295  __IO uint32_t CR;
296 }CRC_TypeDef;
297 
301 typedef struct
302 {
303  __IO uint32_t FLTCR1;
304  __IO uint32_t FLTCR2;
305  __IO uint32_t FLTISR;
306  __IO uint32_t FLTICR;
307  __IO uint32_t FLTJCHGR;
308  __IO uint32_t FLTFCR;
309  __IO uint32_t FLTJDATAR;
310  __IO uint32_t FLTRDATAR;
311  __IO uint32_t FLTAWHTR;
312  __IO uint32_t FLTAWLTR;
313  __IO uint32_t FLTAWSR;
314  __IO uint32_t FLTAWCFR;
315  __IO uint32_t FLTEXMAX;
316  __IO uint32_t FLTEXMIN;
317  __IO uint32_t FLTCNVTIMR;
318 } DFSDM_Filter_TypeDef;
319 
323 typedef struct
324 {
325  __IO uint32_t CHCFGR1;
326  __IO uint32_t CHCFGR2;
327  __IO uint32_t CHAWSCDR;
329  __IO uint32_t CHWDATAR;
330  __IO uint32_t CHDATINR;
331 } DFSDM_Channel_TypeDef;
332 
336 typedef struct
337 {
338  __IO uint32_t IDCODE;
339  __IO uint32_t CR;
340  __IO uint32_t APB1FZ;
341  __IO uint32_t APB2FZ;
342 }DBGMCU_TypeDef;
343 
344 
349 typedef struct
350 {
351  __IO uint32_t CR;
352  __IO uint32_t NDTR;
353  __IO uint32_t PAR;
354  __IO uint32_t M0AR;
355  __IO uint32_t M1AR;
356  __IO uint32_t FCR;
357 } DMA_Stream_TypeDef;
358 
359 typedef struct
360 {
361  __IO uint32_t LISR;
362  __IO uint32_t HISR;
363  __IO uint32_t LIFCR;
364  __IO uint32_t HIFCR;
365 } DMA_TypeDef;
366 
367 
372 typedef struct
373 {
374  __IO uint32_t IMR;
375  __IO uint32_t EMR;
376  __IO uint32_t RTSR;
377  __IO uint32_t FTSR;
378  __IO uint32_t SWIER;
379  __IO uint32_t PR;
380 } EXTI_TypeDef;
381 
386 typedef struct
387 {
388  __IO uint32_t ACR;
389  __IO uint32_t KEYR;
390  __IO uint32_t OPTKEYR;
391  __IO uint32_t SR;
392  __IO uint32_t CR;
393  __IO uint32_t OPTCR;
394  __IO uint32_t OPTCR1;
395 } FLASH_TypeDef;
396 
401 typedef struct
402 {
403  __IO uint32_t BTCR[8];
404 } FSMC_Bank1_TypeDef;
405 
410 typedef struct
411 {
412  __IO uint32_t BWTR[7];
413 } FSMC_Bank1E_TypeDef;
414 
419 typedef struct
420 {
421  __IO uint32_t MODER;
422  __IO uint32_t OTYPER;
423  __IO uint32_t OSPEEDR;
424  __IO uint32_t PUPDR;
425  __IO uint32_t IDR;
426  __IO uint32_t ODR;
427  __IO uint32_t BSRR;
428  __IO uint32_t LCKR;
429  __IO uint32_t AFR[2];
430 } GPIO_TypeDef;
431 
435 typedef struct
436 {
437  __IO uint32_t MEMRMP;
438  __IO uint32_t PMC;
439  __IO uint32_t EXTICR[4];
440  uint32_t RESERVED[2];
441  __IO uint32_t CMPCR;
442  uint32_t RESERVED1[2];
443  __IO uint32_t CFGR;
444 } SYSCFG_TypeDef;
445 
450 typedef struct
451 {
452  __IO uint32_t CR1;
453  __IO uint32_t CR2;
454  __IO uint32_t OAR1;
455  __IO uint32_t OAR2;
456  __IO uint32_t DR;
457  __IO uint32_t SR1;
458  __IO uint32_t SR2;
459  __IO uint32_t CCR;
460  __IO uint32_t TRISE;
461  __IO uint32_t FLTR;
462 } I2C_TypeDef;
463 
468 typedef struct
469 {
470  __IO uint32_t CR1;
471  __IO uint32_t CR2;
472  __IO uint32_t OAR1;
473  __IO uint32_t OAR2;
474  __IO uint32_t TIMINGR;
475  __IO uint32_t TIMEOUTR;
476  __IO uint32_t ISR;
477  __IO uint32_t ICR;
478  __IO uint32_t PECR;
479  __IO uint32_t RXDR;
480  __IO uint32_t TXDR;
481 } FMPI2C_TypeDef;
482 
487 typedef struct
488 {
489  __IO uint32_t KR;
490  __IO uint32_t PR;
491  __IO uint32_t RLR;
492  __IO uint32_t SR;
493 } IWDG_TypeDef;
494 
499 typedef struct
500 {
501  __IO uint32_t CR;
502  __IO uint32_t CSR;
503 } PWR_TypeDef;
504 
509 typedef struct
510 {
511  __IO uint32_t CR;
512  __IO uint32_t PLLCFGR;
513  __IO uint32_t CFGR;
514  __IO uint32_t CIR;
515  __IO uint32_t AHB1RSTR;
516  __IO uint32_t AHB2RSTR;
517  __IO uint32_t AHB3RSTR;
518  uint32_t RESERVED0;
519  __IO uint32_t APB1RSTR;
520  __IO uint32_t APB2RSTR;
521  uint32_t RESERVED1[2];
522  __IO uint32_t AHB1ENR;
523  __IO uint32_t AHB2ENR;
524  __IO uint32_t AHB3ENR;
525  uint32_t RESERVED2;
526  __IO uint32_t APB1ENR;
527  __IO uint32_t APB2ENR;
528  uint32_t RESERVED3[2];
529  __IO uint32_t AHB1LPENR;
530  __IO uint32_t AHB2LPENR;
531  __IO uint32_t AHB3LPENR;
532  uint32_t RESERVED4;
533  __IO uint32_t APB1LPENR;
534  __IO uint32_t APB2LPENR;
535  uint32_t RESERVED5[2];
536  __IO uint32_t BDCR;
537  __IO uint32_t CSR;
538  uint32_t RESERVED6[2];
539  __IO uint32_t SSCGR;
540  __IO uint32_t PLLI2SCFGR;
541  uint32_t RESERVED7;
542  __IO uint32_t DCKCFGR;
543  __IO uint32_t CKGATENR;
544  __IO uint32_t DCKCFGR2;
545 } RCC_TypeDef;
546 
551 typedef struct
552 {
553  __IO uint32_t TR;
554  __IO uint32_t DR;
555  __IO uint32_t CR;
556  __IO uint32_t ISR;
557  __IO uint32_t PRER;
558  __IO uint32_t WUTR;
559  __IO uint32_t CALIBR;
560  __IO uint32_t ALRMAR;
561  __IO uint32_t ALRMBR;
562  __IO uint32_t WPR;
563  __IO uint32_t SSR;
564  __IO uint32_t SHIFTR;
565  __IO uint32_t TSTR;
566  __IO uint32_t TSDR;
567  __IO uint32_t TSSSR;
568  __IO uint32_t CALR;
569  __IO uint32_t TAFCR;
570  __IO uint32_t ALRMASSR;
571  __IO uint32_t ALRMBSSR;
572  uint32_t RESERVED7;
573  __IO uint32_t BKP0R;
574  __IO uint32_t BKP1R;
575  __IO uint32_t BKP2R;
576  __IO uint32_t BKP3R;
577  __IO uint32_t BKP4R;
578  __IO uint32_t BKP5R;
579  __IO uint32_t BKP6R;
580  __IO uint32_t BKP7R;
581  __IO uint32_t BKP8R;
582  __IO uint32_t BKP9R;
583  __IO uint32_t BKP10R;
584  __IO uint32_t BKP11R;
585  __IO uint32_t BKP12R;
586  __IO uint32_t BKP13R;
587  __IO uint32_t BKP14R;
588  __IO uint32_t BKP15R;
589  __IO uint32_t BKP16R;
590  __IO uint32_t BKP17R;
591  __IO uint32_t BKP18R;
592  __IO uint32_t BKP19R;
593 } RTC_TypeDef;
594 
595 
600 typedef struct
601 {
602  __IO uint32_t POWER;
603  __IO uint32_t CLKCR;
604  __IO uint32_t ARG;
605  __IO uint32_t CMD;
606  __I uint32_t RESPCMD;
607  __I uint32_t RESP1;
608  __I uint32_t RESP2;
609  __I uint32_t RESP3;
610  __I uint32_t RESP4;
611  __IO uint32_t DTIMER;
612  __IO uint32_t DLEN;
613  __IO uint32_t DCTRL;
614  __I uint32_t DCOUNT;
615  __I uint32_t STA;
616  __IO uint32_t ICR;
617  __IO uint32_t MASK;
618  uint32_t RESERVED0[2];
619  __I uint32_t FIFOCNT;
620  uint32_t RESERVED1[13];
621  __IO uint32_t FIFO;
622 } SDIO_TypeDef;
623 
628 typedef struct
629 {
630  __IO uint32_t CR1;
631  __IO uint32_t CR2;
632  __IO uint32_t SR;
633  __IO uint32_t DR;
634  __IO uint32_t CRCPR;
635  __IO uint32_t RXCRCR;
636  __IO uint32_t TXCRCR;
637  __IO uint32_t I2SCFGR;
638  __IO uint32_t I2SPR;
639 } SPI_TypeDef;
640 
645 typedef struct
646 {
647  __IO uint32_t CR;
648  __IO uint32_t DCR;
649  __IO uint32_t SR;
650  __IO uint32_t FCR;
651  __IO uint32_t DLR;
652  __IO uint32_t CCR;
653  __IO uint32_t AR;
654  __IO uint32_t ABR;
655  __IO uint32_t DR;
656  __IO uint32_t PSMKR;
657  __IO uint32_t PSMAR;
658  __IO uint32_t PIR;
659  __IO uint32_t LPTR;
660 } QUADSPI_TypeDef;
661 
666 typedef struct
667 {
668  __IO uint32_t CR1;
669  __IO uint32_t CR2;
670  __IO uint32_t SMCR;
671  __IO uint32_t DIER;
672  __IO uint32_t SR;
673  __IO uint32_t EGR;
674  __IO uint32_t CCMR1;
675  __IO uint32_t CCMR2;
676  __IO uint32_t CCER;
677  __IO uint32_t CNT;
678  __IO uint32_t PSC;
679  __IO uint32_t ARR;
680  __IO uint32_t RCR;
681  __IO uint32_t CCR1;
682  __IO uint32_t CCR2;
683  __IO uint32_t CCR3;
684  __IO uint32_t CCR4;
685  __IO uint32_t BDTR;
686  __IO uint32_t DCR;
687  __IO uint32_t DMAR;
688  __IO uint32_t OR;
689 } TIM_TypeDef;
690 
695 typedef struct
696 {
697  __IO uint32_t SR;
698  __IO uint32_t DR;
699  __IO uint32_t BRR;
700  __IO uint32_t CR1;
701  __IO uint32_t CR2;
702  __IO uint32_t CR3;
703  __IO uint32_t GTPR;
704 } USART_TypeDef;
705 
710 typedef struct
711 {
712  __IO uint32_t CR;
713  __IO uint32_t CFR;
714  __IO uint32_t SR;
715 } WWDG_TypeDef;
716 
717 
722 typedef struct
723 {
724  __IO uint32_t CR;
725  __IO uint32_t SR;
726  __IO uint32_t DR;
727 } RNG_TypeDef;
728 
729 
733 typedef struct
734 {
735  __IO uint32_t GOTGCTL;
736  __IO uint32_t GOTGINT;
737  __IO uint32_t GAHBCFG;
738  __IO uint32_t GUSBCFG;
739  __IO uint32_t GRSTCTL;
740  __IO uint32_t GINTSTS;
741  __IO uint32_t GINTMSK;
742  __IO uint32_t GRXSTSR;
743  __IO uint32_t GRXSTSP;
744  __IO uint32_t GRXFSIZ;
745  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
746  __IO uint32_t HNPTXSTS;
747  uint32_t Reserved30[2];
748  __IO uint32_t GCCFG;
749  __IO uint32_t CID;
750  uint32_t Reserved5[3];
751  __IO uint32_t GHWCFG3;
752  uint32_t Reserved6;
753  __IO uint32_t GLPMCFG;
754  uint32_t Reserved;
755  __IO uint32_t GDFIFOCFG;
756  uint32_t Reserved43[40];
757  __IO uint32_t HPTXFSIZ;
758  __IO uint32_t DIEPTXF[0x0F];
759 } USB_OTG_GlobalTypeDef;
760 
761 
765 typedef struct
766 {
767  __IO uint32_t DCFG;
768  __IO uint32_t DCTL;
769  __IO uint32_t DSTS;
770  uint32_t Reserved0C;
771  __IO uint32_t DIEPMSK;
772  __IO uint32_t DOEPMSK;
773  __IO uint32_t DAINT;
774  __IO uint32_t DAINTMSK;
775  uint32_t Reserved20;
776  uint32_t Reserved9;
777  __IO uint32_t DVBUSDIS;
778  __IO uint32_t DVBUSPULSE;
779  __IO uint32_t DTHRCTL;
780  __IO uint32_t DIEPEMPMSK;
781  __IO uint32_t DEACHINT;
782  __IO uint32_t DEACHMSK;
783  uint32_t Reserved40;
784  __IO uint32_t DINEP1MSK;
785  uint32_t Reserved44[15];
786  __IO uint32_t DOUTEP1MSK;
787 } USB_OTG_DeviceTypeDef;
788 
789 
793 typedef struct
794 {
795  __IO uint32_t DIEPCTL;
796  uint32_t Reserved04;
797  __IO uint32_t DIEPINT;
798  uint32_t Reserved0C;
799  __IO uint32_t DIEPTSIZ;
800  __IO uint32_t DIEPDMA;
801  __IO uint32_t DTXFSTS;
802  uint32_t Reserved18;
803 } USB_OTG_INEndpointTypeDef;
804 
805 
809 typedef struct
810 {
811  __IO uint32_t DOEPCTL;
812  uint32_t Reserved04;
813  __IO uint32_t DOEPINT;
814  uint32_t Reserved0C;
815  __IO uint32_t DOEPTSIZ;
816  __IO uint32_t DOEPDMA;
817  uint32_t Reserved18[2];
818 } USB_OTG_OUTEndpointTypeDef;
819 
820 
824 typedef struct
825 {
826  __IO uint32_t HCFG;
827  __IO uint32_t HFIR;
828  __IO uint32_t HFNUM;
829  uint32_t Reserved40C;
830  __IO uint32_t HPTXSTS;
831  __IO uint32_t HAINT;
832  __IO uint32_t HAINTMSK;
833 } USB_OTG_HostTypeDef;
834 
835 
839 typedef struct
840 {
841  __IO uint32_t HCCHAR;
842  __IO uint32_t HCSPLT;
843  __IO uint32_t HCINT;
844  __IO uint32_t HCINTMSK;
845  __IO uint32_t HCTSIZ;
846  __IO uint32_t HCDMA;
847  uint32_t Reserved[2];
848 } USB_OTG_HostChannelTypeDef;
849 
850 
854 #define FLASH_BASE 0x08000000U
855 #define SRAM1_BASE 0x20000000U
856 #define PERIPH_BASE 0x40000000U
857 #define FSMC_R_BASE 0xA0000000U
858 #define QSPI_R_BASE 0xA0001000U
860 #define SRAM1_BB_BASE 0x22000000U
861 #define PERIPH_BB_BASE 0x42000000U
862 #define FLASH_END 0x080FFFFFU
864 /* Legacy defines */
865 #define SRAM_BASE SRAM1_BASE
866 #define SRAM_BB_BASE SRAM1_BB_BASE
867 
869 #define APB1PERIPH_BASE PERIPH_BASE
870 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
871 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
872 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
873 
875 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
876 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
877 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
878 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
879 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
880 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
881 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
882 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
883 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
884 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
885 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
886 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
887 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
888 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
889 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
890 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
891 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
892 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
893 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
894 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
895 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
896 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
897 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
898 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
899 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
900 
902 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
903 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
904 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
905 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
906 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
907 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
908 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
909 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
910 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
911 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
912 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
913 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
914 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
915 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
916 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
917 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
918 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
919 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
920 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
921 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
922 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
923 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
924 
926 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
927 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
928 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
929 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
930 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
931 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
932 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
933 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
934 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
935 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
936 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
937 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
938 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
939 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
940 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
941 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
942 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
943 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
944 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
945 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
946 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
947 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
948 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
949 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
950 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
951 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
952 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
953 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
954 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
955 
957 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
958 
960 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
961 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
962 
963 /* Debug MCU registers base address */
964 #define DBGMCU_BASE 0xE0042000U
965 
967 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
968 
969 #define USB_OTG_GLOBAL_BASE 0x000U
970 #define USB_OTG_DEVICE_BASE 0x800U
971 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
972 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
973 #define USB_OTG_EP_REG_SIZE 0x20U
974 #define USB_OTG_HOST_BASE 0x400U
975 #define USB_OTG_HOST_PORT_BASE 0x440U
976 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
977 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
978 #define USB_OTG_PCGCCTL_BASE 0xE00U
979 #define USB_OTG_FIFO_BASE 0x1000U
980 #define USB_OTG_FIFO_SIZE 0x1000U
981 
989 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
990 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
991 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
992 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
993 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
994 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
995 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
996 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
997 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
998 #define RTC ((RTC_TypeDef *) RTC_BASE)
999 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1000 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1001 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1002 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1003 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1004 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1005 #define USART2 ((USART_TypeDef *) USART2_BASE)
1006 #define USART3 ((USART_TypeDef *) USART3_BASE)
1007 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1008 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1009 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1010 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1011 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1012 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1013 #define PWR ((PWR_TypeDef *) PWR_BASE)
1014 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1015 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1016 #define USART1 ((USART_TypeDef *) USART1_BASE)
1017 #define USART6 ((USART_TypeDef *) USART6_BASE)
1018 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1019 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1020 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1021 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1022 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1023 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1024 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1025 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1026 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1027 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1028 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1029 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1030 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1031 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1032 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1033 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1034 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1035 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1036 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1037 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1038 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1039 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1040 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1041 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1042 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1043 #define CRC ((CRC_TypeDef *) CRC_BASE)
1044 #define RCC ((RCC_TypeDef *) RCC_BASE)
1045 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1046 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1047 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1048 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1049 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1050 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1051 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1052 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1053 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1054 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1055 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1056 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1057 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1058 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1059 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1060 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1061 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1062 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1063 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1064 #define RNG ((RNG_TypeDef *) RNG_BASE)
1065 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1066 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1067 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1068 
1069 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1070 
1071 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1072 
1085 /******************************************************************************/
1086 /* Peripheral Registers_Bits_Definition */
1087 /******************************************************************************/
1088 
1089 /******************************************************************************/
1090 /* */
1091 /* Analog to Digital Converter */
1092 /* */
1093 /******************************************************************************/
1094 /******************** Bit definition for ADC_SR register ********************/
1095 #define ADC_SR_AWD 0x00000001U
1096 #define ADC_SR_EOC 0x00000002U
1097 #define ADC_SR_JEOC 0x00000004U
1098 #define ADC_SR_JSTRT 0x00000008U
1099 #define ADC_SR_STRT 0x00000010U
1100 #define ADC_SR_OVR 0x00000020U
1102 /******************* Bit definition for ADC_CR1 register ********************/
1103 #define ADC_CR1_AWDCH 0x0000001FU
1104 #define ADC_CR1_AWDCH_0 0x00000001U
1105 #define ADC_CR1_AWDCH_1 0x00000002U
1106 #define ADC_CR1_AWDCH_2 0x00000004U
1107 #define ADC_CR1_AWDCH_3 0x00000008U
1108 #define ADC_CR1_AWDCH_4 0x00000010U
1109 #define ADC_CR1_EOCIE 0x00000020U
1110 #define ADC_CR1_AWDIE 0x00000040U
1111 #define ADC_CR1_JEOCIE 0x00000080U
1112 #define ADC_CR1_SCAN 0x00000100U
1113 #define ADC_CR1_AWDSGL 0x00000200U
1114 #define ADC_CR1_JAUTO 0x00000400U
1115 #define ADC_CR1_DISCEN 0x00000800U
1116 #define ADC_CR1_JDISCEN 0x00001000U
1117 #define ADC_CR1_DISCNUM 0x0000E000U
1118 #define ADC_CR1_DISCNUM_0 0x00002000U
1119 #define ADC_CR1_DISCNUM_1 0x00004000U
1120 #define ADC_CR1_DISCNUM_2 0x00008000U
1121 #define ADC_CR1_JAWDEN 0x00400000U
1122 #define ADC_CR1_AWDEN 0x00800000U
1123 #define ADC_CR1_RES 0x03000000U
1124 #define ADC_CR1_RES_0 0x01000000U
1125 #define ADC_CR1_RES_1 0x02000000U
1126 #define ADC_CR1_OVRIE 0x04000000U
1128 /******************* Bit definition for ADC_CR2 register ********************/
1129 #define ADC_CR2_ADON 0x00000001U
1130 #define ADC_CR2_CONT 0x00000002U
1131 #define ADC_CR2_DMA 0x00000100U
1132 #define ADC_CR2_DDS 0x00000200U
1133 #define ADC_CR2_EOCS 0x00000400U
1134 #define ADC_CR2_ALIGN 0x00000800U
1135 #define ADC_CR2_JEXTSEL 0x000F0000U
1136 #define ADC_CR2_JEXTSEL_0 0x00010000U
1137 #define ADC_CR2_JEXTSEL_1 0x00020000U
1138 #define ADC_CR2_JEXTSEL_2 0x00040000U
1139 #define ADC_CR2_JEXTSEL_3 0x00080000U
1140 #define ADC_CR2_JEXTEN 0x00300000U
1141 #define ADC_CR2_JEXTEN_0 0x00100000U
1142 #define ADC_CR2_JEXTEN_1 0x00200000U
1143 #define ADC_CR2_JSWSTART 0x00400000U
1144 #define ADC_CR2_EXTSEL 0x0F000000U
1145 #define ADC_CR2_EXTSEL_0 0x01000000U
1146 #define ADC_CR2_EXTSEL_1 0x02000000U
1147 #define ADC_CR2_EXTSEL_2 0x04000000U
1148 #define ADC_CR2_EXTSEL_3 0x08000000U
1149 #define ADC_CR2_EXTEN 0x30000000U
1150 #define ADC_CR2_EXTEN_0 0x10000000U
1151 #define ADC_CR2_EXTEN_1 0x20000000U
1152 #define ADC_CR2_SWSTART 0x40000000U
1154 /****************** Bit definition for ADC_SMPR1 register *******************/
1155 #define ADC_SMPR1_SMP10 0x00000007U
1156 #define ADC_SMPR1_SMP10_0 0x00000001U
1157 #define ADC_SMPR1_SMP10_1 0x00000002U
1158 #define ADC_SMPR1_SMP10_2 0x00000004U
1159 #define ADC_SMPR1_SMP11 0x00000038U
1160 #define ADC_SMPR1_SMP11_0 0x00000008U
1161 #define ADC_SMPR1_SMP11_1 0x00000010U
1162 #define ADC_SMPR1_SMP11_2 0x00000020U
1163 #define ADC_SMPR1_SMP12 0x000001C0U
1164 #define ADC_SMPR1_SMP12_0 0x00000040U
1165 #define ADC_SMPR1_SMP12_1 0x00000080U
1166 #define ADC_SMPR1_SMP12_2 0x00000100U
1167 #define ADC_SMPR1_SMP13 0x00000E00U
1168 #define ADC_SMPR1_SMP13_0 0x00000200U
1169 #define ADC_SMPR1_SMP13_1 0x00000400U
1170 #define ADC_SMPR1_SMP13_2 0x00000800U
1171 #define ADC_SMPR1_SMP14 0x00007000U
1172 #define ADC_SMPR1_SMP14_0 0x00001000U
1173 #define ADC_SMPR1_SMP14_1 0x00002000U
1174 #define ADC_SMPR1_SMP14_2 0x00004000U
1175 #define ADC_SMPR1_SMP15 0x00038000U
1176 #define ADC_SMPR1_SMP15_0 0x00008000U
1177 #define ADC_SMPR1_SMP15_1 0x00010000U
1178 #define ADC_SMPR1_SMP15_2 0x00020000U
1179 #define ADC_SMPR1_SMP16 0x001C0000U
1180 #define ADC_SMPR1_SMP16_0 0x00040000U
1181 #define ADC_SMPR1_SMP16_1 0x00080000U
1182 #define ADC_SMPR1_SMP16_2 0x00100000U
1183 #define ADC_SMPR1_SMP17 0x00E00000U
1184 #define ADC_SMPR1_SMP17_0 0x00200000U
1185 #define ADC_SMPR1_SMP17_1 0x00400000U
1186 #define ADC_SMPR1_SMP17_2 0x00800000U
1187 #define ADC_SMPR1_SMP18 0x07000000U
1188 #define ADC_SMPR1_SMP18_0 0x01000000U
1189 #define ADC_SMPR1_SMP18_1 0x02000000U
1190 #define ADC_SMPR1_SMP18_2 0x04000000U
1192 /****************** Bit definition for ADC_SMPR2 register *******************/
1193 #define ADC_SMPR2_SMP0 0x00000007U
1194 #define ADC_SMPR2_SMP0_0 0x00000001U
1195 #define ADC_SMPR2_SMP0_1 0x00000002U
1196 #define ADC_SMPR2_SMP0_2 0x00000004U
1197 #define ADC_SMPR2_SMP1 0x00000038U
1198 #define ADC_SMPR2_SMP1_0 0x00000008U
1199 #define ADC_SMPR2_SMP1_1 0x00000010U
1200 #define ADC_SMPR2_SMP1_2 0x00000020U
1201 #define ADC_SMPR2_SMP2 0x000001C0U
1202 #define ADC_SMPR2_SMP2_0 0x00000040U
1203 #define ADC_SMPR2_SMP2_1 0x00000080U
1204 #define ADC_SMPR2_SMP2_2 0x00000100U
1205 #define ADC_SMPR2_SMP3 0x00000E00U
1206 #define ADC_SMPR2_SMP3_0 0x00000200U
1207 #define ADC_SMPR2_SMP3_1 0x00000400U
1208 #define ADC_SMPR2_SMP3_2 0x00000800U
1209 #define ADC_SMPR2_SMP4 0x00007000U
1210 #define ADC_SMPR2_SMP4_0 0x00001000U
1211 #define ADC_SMPR2_SMP4_1 0x00002000U
1212 #define ADC_SMPR2_SMP4_2 0x00004000U
1213 #define ADC_SMPR2_SMP5 0x00038000U
1214 #define ADC_SMPR2_SMP5_0 0x00008000U
1215 #define ADC_SMPR2_SMP5_1 0x00010000U
1216 #define ADC_SMPR2_SMP5_2 0x00020000U
1217 #define ADC_SMPR2_SMP6 0x001C0000U
1218 #define ADC_SMPR2_SMP6_0 0x00040000U
1219 #define ADC_SMPR2_SMP6_1 0x00080000U
1220 #define ADC_SMPR2_SMP6_2 0x00100000U
1221 #define ADC_SMPR2_SMP7 0x00E00000U
1222 #define ADC_SMPR2_SMP7_0 0x00200000U
1223 #define ADC_SMPR2_SMP7_1 0x00400000U
1224 #define ADC_SMPR2_SMP7_2 0x00800000U
1225 #define ADC_SMPR2_SMP8 0x07000000U
1226 #define ADC_SMPR2_SMP8_0 0x01000000U
1227 #define ADC_SMPR2_SMP8_1 0x02000000U
1228 #define ADC_SMPR2_SMP8_2 0x04000000U
1229 #define ADC_SMPR2_SMP9 0x38000000U
1230 #define ADC_SMPR2_SMP9_0 0x08000000U
1231 #define ADC_SMPR2_SMP9_1 0x10000000U
1232 #define ADC_SMPR2_SMP9_2 0x20000000U
1234 /****************** Bit definition for ADC_JOFR1 register *******************/
1235 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1237 /****************** Bit definition for ADC_JOFR2 register *******************/
1238 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1240 /****************** Bit definition for ADC_JOFR3 register *******************/
1241 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1243 /****************** Bit definition for ADC_JOFR4 register *******************/
1244 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1246 /******************* Bit definition for ADC_HTR register ********************/
1247 #define ADC_HTR_HT 0x0FFFU
1249 /******************* Bit definition for ADC_LTR register ********************/
1250 #define ADC_LTR_LT 0x0FFFU
1252 /******************* Bit definition for ADC_SQR1 register *******************/
1253 #define ADC_SQR1_SQ13 0x0000001FU
1254 #define ADC_SQR1_SQ13_0 0x00000001U
1255 #define ADC_SQR1_SQ13_1 0x00000002U
1256 #define ADC_SQR1_SQ13_2 0x00000004U
1257 #define ADC_SQR1_SQ13_3 0x00000008U
1258 #define ADC_SQR1_SQ13_4 0x00000010U
1259 #define ADC_SQR1_SQ14 0x000003E0U
1260 #define ADC_SQR1_SQ14_0 0x00000020U
1261 #define ADC_SQR1_SQ14_1 0x00000040U
1262 #define ADC_SQR1_SQ14_2 0x00000080U
1263 #define ADC_SQR1_SQ14_3 0x00000100U
1264 #define ADC_SQR1_SQ14_4 0x00000200U
1265 #define ADC_SQR1_SQ15 0x00007C00U
1266 #define ADC_SQR1_SQ15_0 0x00000400U
1267 #define ADC_SQR1_SQ15_1 0x00000800U
1268 #define ADC_SQR1_SQ15_2 0x00001000U
1269 #define ADC_SQR1_SQ15_3 0x00002000U
1270 #define ADC_SQR1_SQ15_4 0x00004000U
1271 #define ADC_SQR1_SQ16 0x000F8000U
1272 #define ADC_SQR1_SQ16_0 0x00008000U
1273 #define ADC_SQR1_SQ16_1 0x00010000U
1274 #define ADC_SQR1_SQ16_2 0x00020000U
1275 #define ADC_SQR1_SQ16_3 0x00040000U
1276 #define ADC_SQR1_SQ16_4 0x00080000U
1277 #define ADC_SQR1_L 0x00F00000U
1278 #define ADC_SQR1_L_0 0x00100000U
1279 #define ADC_SQR1_L_1 0x00200000U
1280 #define ADC_SQR1_L_2 0x00400000U
1281 #define ADC_SQR1_L_3 0x00800000U
1283 /******************* Bit definition for ADC_SQR2 register *******************/
1284 #define ADC_SQR2_SQ7 0x0000001FU
1285 #define ADC_SQR2_SQ7_0 0x00000001U
1286 #define ADC_SQR2_SQ7_1 0x00000002U
1287 #define ADC_SQR2_SQ7_2 0x00000004U
1288 #define ADC_SQR2_SQ7_3 0x00000008U
1289 #define ADC_SQR2_SQ7_4 0x00000010U
1290 #define ADC_SQR2_SQ8 0x000003E0U
1291 #define ADC_SQR2_SQ8_0 0x00000020U
1292 #define ADC_SQR2_SQ8_1 0x00000040U
1293 #define ADC_SQR2_SQ8_2 0x00000080U
1294 #define ADC_SQR2_SQ8_3 0x00000100U
1295 #define ADC_SQR2_SQ8_4 0x00000200U
1296 #define ADC_SQR2_SQ9 0x00007C00U
1297 #define ADC_SQR2_SQ9_0 0x00000400U
1298 #define ADC_SQR2_SQ9_1 0x00000800U
1299 #define ADC_SQR2_SQ9_2 0x00001000U
1300 #define ADC_SQR2_SQ9_3 0x00002000U
1301 #define ADC_SQR2_SQ9_4 0x00004000U
1302 #define ADC_SQR2_SQ10 0x000F8000U
1303 #define ADC_SQR2_SQ10_0 0x00008000U
1304 #define ADC_SQR2_SQ10_1 0x00010000U
1305 #define ADC_SQR2_SQ10_2 0x00020000U
1306 #define ADC_SQR2_SQ10_3 0x00040000U
1307 #define ADC_SQR2_SQ10_4 0x00080000U
1308 #define ADC_SQR2_SQ11 0x01F00000U
1309 #define ADC_SQR2_SQ11_0 0x00100000U
1310 #define ADC_SQR2_SQ11_1 0x00200000U
1311 #define ADC_SQR2_SQ11_2 0x00400000U
1312 #define ADC_SQR2_SQ11_3 0x00800000U
1313 #define ADC_SQR2_SQ11_4 0x01000000U
1314 #define ADC_SQR2_SQ12 0x3E000000U
1315 #define ADC_SQR2_SQ12_0 0x02000000U
1316 #define ADC_SQR2_SQ12_1 0x04000000U
1317 #define ADC_SQR2_SQ12_2 0x08000000U
1318 #define ADC_SQR2_SQ12_3 0x10000000U
1319 #define ADC_SQR2_SQ12_4 0x20000000U
1321 /******************* Bit definition for ADC_SQR3 register *******************/
1322 #define ADC_SQR3_SQ1 0x0000001FU
1323 #define ADC_SQR3_SQ1_0 0x00000001U
1324 #define ADC_SQR3_SQ1_1 0x00000002U
1325 #define ADC_SQR3_SQ1_2 0x00000004U
1326 #define ADC_SQR3_SQ1_3 0x00000008U
1327 #define ADC_SQR3_SQ1_4 0x00000010U
1328 #define ADC_SQR3_SQ2 0x000003E0U
1329 #define ADC_SQR3_SQ2_0 0x00000020U
1330 #define ADC_SQR3_SQ2_1 0x00000040U
1331 #define ADC_SQR3_SQ2_2 0x00000080U
1332 #define ADC_SQR3_SQ2_3 0x00000100U
1333 #define ADC_SQR3_SQ2_4 0x00000200U
1334 #define ADC_SQR3_SQ3 0x00007C00U
1335 #define ADC_SQR3_SQ3_0 0x00000400U
1336 #define ADC_SQR3_SQ3_1 0x00000800U
1337 #define ADC_SQR3_SQ3_2 0x00001000U
1338 #define ADC_SQR3_SQ3_3 0x00002000U
1339 #define ADC_SQR3_SQ3_4 0x00004000U
1340 #define ADC_SQR3_SQ4 0x000F8000U
1341 #define ADC_SQR3_SQ4_0 0x00008000U
1342 #define ADC_SQR3_SQ4_1 0x00010000U
1343 #define ADC_SQR3_SQ4_2 0x00020000U
1344 #define ADC_SQR3_SQ4_3 0x00040000U
1345 #define ADC_SQR3_SQ4_4 0x00080000U
1346 #define ADC_SQR3_SQ5 0x01F00000U
1347 #define ADC_SQR3_SQ5_0 0x00100000U
1348 #define ADC_SQR3_SQ5_1 0x00200000U
1349 #define ADC_SQR3_SQ5_2 0x00400000U
1350 #define ADC_SQR3_SQ5_3 0x00800000U
1351 #define ADC_SQR3_SQ5_4 0x01000000U
1352 #define ADC_SQR3_SQ6 0x3E000000U
1353 #define ADC_SQR3_SQ6_0 0x02000000U
1354 #define ADC_SQR3_SQ6_1 0x04000000U
1355 #define ADC_SQR3_SQ6_2 0x08000000U
1356 #define ADC_SQR3_SQ6_3 0x10000000U
1357 #define ADC_SQR3_SQ6_4 0x20000000U
1359 /******************* Bit definition for ADC_JSQR register *******************/
1360 #define ADC_JSQR_JSQ1 0x0000001FU
1361 #define ADC_JSQR_JSQ1_0 0x00000001U
1362 #define ADC_JSQR_JSQ1_1 0x00000002U
1363 #define ADC_JSQR_JSQ1_2 0x00000004U
1364 #define ADC_JSQR_JSQ1_3 0x00000008U
1365 #define ADC_JSQR_JSQ1_4 0x00000010U
1366 #define ADC_JSQR_JSQ2 0x000003E0U
1367 #define ADC_JSQR_JSQ2_0 0x00000020U
1368 #define ADC_JSQR_JSQ2_1 0x00000040U
1369 #define ADC_JSQR_JSQ2_2 0x00000080U
1370 #define ADC_JSQR_JSQ2_3 0x00000100U
1371 #define ADC_JSQR_JSQ2_4 0x00000200U
1372 #define ADC_JSQR_JSQ3 0x00007C00U
1373 #define ADC_JSQR_JSQ3_0 0x00000400U
1374 #define ADC_JSQR_JSQ3_1 0x00000800U
1375 #define ADC_JSQR_JSQ3_2 0x00001000U
1376 #define ADC_JSQR_JSQ3_3 0x00002000U
1377 #define ADC_JSQR_JSQ3_4 0x00004000U
1378 #define ADC_JSQR_JSQ4 0x000F8000U
1379 #define ADC_JSQR_JSQ4_0 0x00008000U
1380 #define ADC_JSQR_JSQ4_1 0x00010000U
1381 #define ADC_JSQR_JSQ4_2 0x00020000U
1382 #define ADC_JSQR_JSQ4_3 0x00040000U
1383 #define ADC_JSQR_JSQ4_4 0x00080000U
1384 #define ADC_JSQR_JL 0x00300000U
1385 #define ADC_JSQR_JL_0 0x00100000U
1386 #define ADC_JSQR_JL_1 0x00200000U
1388 /******************* Bit definition for ADC_JDR1 register *******************/
1389 #define ADC_JDR1_JDATA 0xFFFFU
1391 /******************* Bit definition for ADC_JDR2 register *******************/
1392 #define ADC_JDR2_JDATA 0xFFFFU
1394 /******************* Bit definition for ADC_JDR3 register *******************/
1395 #define ADC_JDR3_JDATA 0xFFFFU
1397 /******************* Bit definition for ADC_JDR4 register *******************/
1398 #define ADC_JDR4_JDATA 0xFFFFU
1400 /******************** Bit definition for ADC_DR register ********************/
1401 #define ADC_DR_DATA 0x0000FFFFU
1402 #define ADC_DR_ADC2DATA 0xFFFF0000U
1404 /******************* Bit definition for ADC_CSR register ********************/
1405 #define ADC_CSR_AWD1 0x00000001U
1406 #define ADC_CSR_EOC1 0x00000002U
1407 #define ADC_CSR_JEOC1 0x00000004U
1408 #define ADC_CSR_JSTRT1 0x00000008U
1409 #define ADC_CSR_STRT1 0x00000010U
1410 #define ADC_CSR_DOVR1 0x00000020U
1411 #define ADC_CSR_AWD2 0x00000100U
1412 #define ADC_CSR_EOC2 0x00000200U
1413 #define ADC_CSR_JEOC2 0x00000400U
1414 #define ADC_CSR_JSTRT2 0x00000800U
1415 #define ADC_CSR_STRT2 0x00001000U
1416 #define ADC_CSR_DOVR2 0x00002000U
1418 /******************* Bit definition for ADC_CCR register ********************/
1419 #define ADC_CCR_MULTI 0x0000001FU
1420 #define ADC_CCR_MULTI_0 0x00000001U
1421 #define ADC_CCR_MULTI_1 0x00000002U
1422 #define ADC_CCR_MULTI_2 0x00000004U
1423 #define ADC_CCR_MULTI_3 0x00000008U
1424 #define ADC_CCR_MULTI_4 0x00000010U
1425 #define ADC_CCR_DELAY 0x00000F00U
1426 #define ADC_CCR_DELAY_0 0x00000100U
1427 #define ADC_CCR_DELAY_1 0x00000200U
1428 #define ADC_CCR_DELAY_2 0x00000400U
1429 #define ADC_CCR_DELAY_3 0x00000800U
1430 #define ADC_CCR_DDS 0x00002000U
1431 #define ADC_CCR_DMA 0x0000C000U
1432 #define ADC_CCR_DMA_0 0x00004000U
1433 #define ADC_CCR_DMA_1 0x00008000U
1434 #define ADC_CCR_ADCPRE 0x00030000U
1435 #define ADC_CCR_ADCPRE_0 0x00010000U
1436 #define ADC_CCR_ADCPRE_1 0x00020000U
1437 #define ADC_CCR_VBATE 0x00400000U
1438 #define ADC_CCR_TSVREFE 0x00800000U
1440 /******************* Bit definition for ADC_CDR register ********************/
1441 #define ADC_CDR_DATA1 0x0000FFFFU
1442 #define ADC_CDR_DATA2 0xFFFF0000U
1444 /******************************************************************************/
1445 /* */
1446 /* Controller Area Network */
1447 /* */
1448 /******************************************************************************/
1450 /******************* Bit definition for CAN_MCR register ********************/
1451 #define CAN_MCR_INRQ 0x00000001U
1452 #define CAN_MCR_SLEEP 0x00000002U
1453 #define CAN_MCR_TXFP 0x00000004U
1454 #define CAN_MCR_RFLM 0x00000008U
1455 #define CAN_MCR_NART 0x00000010U
1456 #define CAN_MCR_AWUM 0x00000020U
1457 #define CAN_MCR_ABOM 0x00000040U
1458 #define CAN_MCR_TTCM 0x00000080U
1459 #define CAN_MCR_RESET 0x00008000U
1460 #define CAN_MCR_DBF 0x00010000U
1461 /******************* Bit definition for CAN_MSR register ********************/
1462 #define CAN_MSR_INAK 0x0001U
1463 #define CAN_MSR_SLAK 0x0002U
1464 #define CAN_MSR_ERRI 0x0004U
1465 #define CAN_MSR_WKUI 0x0008U
1466 #define CAN_MSR_SLAKI 0x0010U
1467 #define CAN_MSR_TXM 0x0100U
1468 #define CAN_MSR_RXM 0x0200U
1469 #define CAN_MSR_SAMP 0x0400U
1470 #define CAN_MSR_RX 0x0800U
1472 /******************* Bit definition for CAN_TSR register ********************/
1473 #define CAN_TSR_RQCP0 0x00000001U
1474 #define CAN_TSR_TXOK0 0x00000002U
1475 #define CAN_TSR_ALST0 0x00000004U
1476 #define CAN_TSR_TERR0 0x00000008U
1477 #define CAN_TSR_ABRQ0 0x00000080U
1478 #define CAN_TSR_RQCP1 0x00000100U
1479 #define CAN_TSR_TXOK1 0x00000200U
1480 #define CAN_TSR_ALST1 0x00000400U
1481 #define CAN_TSR_TERR1 0x00000800U
1482 #define CAN_TSR_ABRQ1 0x00008000U
1483 #define CAN_TSR_RQCP2 0x00010000U
1484 #define CAN_TSR_TXOK2 0x00020000U
1485 #define CAN_TSR_ALST2 0x00040000U
1486 #define CAN_TSR_TERR2 0x00080000U
1487 #define CAN_TSR_ABRQ2 0x00800000U
1488 #define CAN_TSR_CODE 0x03000000U
1490 #define CAN_TSR_TME 0x1C000000U
1491 #define CAN_TSR_TME0 0x04000000U
1492 #define CAN_TSR_TME1 0x08000000U
1493 #define CAN_TSR_TME2 0x10000000U
1495 #define CAN_TSR_LOW 0xE0000000U
1496 #define CAN_TSR_LOW0 0x20000000U
1497 #define CAN_TSR_LOW1 0x40000000U
1498 #define CAN_TSR_LOW2 0x80000000U
1500 /******************* Bit definition for CAN_RF0R register *******************/
1501 #define CAN_RF0R_FMP0 0x03U
1502 #define CAN_RF0R_FULL0 0x08U
1503 #define CAN_RF0R_FOVR0 0x10U
1504 #define CAN_RF0R_RFOM0 0x20U
1506 /******************* Bit definition for CAN_RF1R register *******************/
1507 #define CAN_RF1R_FMP1 0x03U
1508 #define CAN_RF1R_FULL1 0x08U
1509 #define CAN_RF1R_FOVR1 0x10U
1510 #define CAN_RF1R_RFOM1 0x20U
1512 /******************** Bit definition for CAN_IER register *******************/
1513 #define CAN_IER_TMEIE 0x00000001U
1514 #define CAN_IER_FMPIE0 0x00000002U
1515 #define CAN_IER_FFIE0 0x00000004U
1516 #define CAN_IER_FOVIE0 0x00000008U
1517 #define CAN_IER_FMPIE1 0x00000010U
1518 #define CAN_IER_FFIE1 0x00000020U
1519 #define CAN_IER_FOVIE1 0x00000040U
1520 #define CAN_IER_EWGIE 0x00000100U
1521 #define CAN_IER_EPVIE 0x00000200U
1522 #define CAN_IER_BOFIE 0x00000400U
1523 #define CAN_IER_LECIE 0x00000800U
1524 #define CAN_IER_ERRIE 0x00008000U
1525 #define CAN_IER_WKUIE 0x00010000U
1526 #define CAN_IER_SLKIE 0x00020000U
1527 #define CAN_IER_EWGIE 0x00000100U
1528 #define CAN_IER_EPVIE 0x00000200U
1529 #define CAN_IER_BOFIE 0x00000400U
1530 #define CAN_IER_LECIE 0x00000800U
1531 #define CAN_IER_ERRIE 0x00008000U
1534 /******************** Bit definition for CAN_ESR register *******************/
1535 #define CAN_ESR_EWGF 0x00000001U
1536 #define CAN_ESR_EPVF 0x00000002U
1537 #define CAN_ESR_BOFF 0x00000004U
1539 #define CAN_ESR_LEC 0x00000070U
1540 #define CAN_ESR_LEC_0 0x00000010U
1541 #define CAN_ESR_LEC_1 0x00000020U
1542 #define CAN_ESR_LEC_2 0x00000040U
1544 #define CAN_ESR_TEC 0x00FF0000U
1545 #define CAN_ESR_REC 0xFF000000U
1547 /******************* Bit definition for CAN_BTR register ********************/
1548 #define CAN_BTR_BRP 0x000003FFU
1549 #define CAN_BTR_TS1 0x000F0000U
1550 #define CAN_BTR_TS1_0 0x00010000U
1551 #define CAN_BTR_TS1_1 0x00020000U
1552 #define CAN_BTR_TS1_2 0x00040000U
1553 #define CAN_BTR_TS1_3 0x00080000U
1554 #define CAN_BTR_TS2 0x00700000U
1555 #define CAN_BTR_TS2_0 0x00100000U
1556 #define CAN_BTR_TS2_1 0x00200000U
1557 #define CAN_BTR_TS2_2 0x00400000U
1558 #define CAN_BTR_SJW 0x03000000U
1559 #define CAN_BTR_SJW_0 0x01000000U
1560 #define CAN_BTR_SJW_1 0x02000000U
1561 #define CAN_BTR_LBKM 0x40000000U
1562 #define CAN_BTR_SILM 0x80000000U
1566 /****************** Bit definition for CAN_TI0R register ********************/
1567 #define CAN_TI0R_TXRQ 0x00000001U
1568 #define CAN_TI0R_RTR 0x00000002U
1569 #define CAN_TI0R_IDE 0x00000004U
1570 #define CAN_TI0R_EXID 0x001FFFF8U
1571 #define CAN_TI0R_STID 0xFFE00000U
1573 /****************** Bit definition for CAN_TDT0R register *******************/
1574 #define CAN_TDT0R_DLC 0x0000000FU
1575 #define CAN_TDT0R_TGT 0x00000100U
1576 #define CAN_TDT0R_TIME 0xFFFF0000U
1578 /****************** Bit definition for CAN_TDL0R register *******************/
1579 #define CAN_TDL0R_DATA0 0x000000FFU
1580 #define CAN_TDL0R_DATA1 0x0000FF00U
1581 #define CAN_TDL0R_DATA2 0x00FF0000U
1582 #define CAN_TDL0R_DATA3 0xFF000000U
1584 /****************** Bit definition for CAN_TDH0R register *******************/
1585 #define CAN_TDH0R_DATA4 0x000000FFU
1586 #define CAN_TDH0R_DATA5 0x0000FF00U
1587 #define CAN_TDH0R_DATA6 0x00FF0000U
1588 #define CAN_TDH0R_DATA7 0xFF000000U
1590 /******************* Bit definition for CAN_TI1R register *******************/
1591 #define CAN_TI1R_TXRQ 0x00000001U
1592 #define CAN_TI1R_RTR 0x00000002U
1593 #define CAN_TI1R_IDE 0x00000004U
1594 #define CAN_TI1R_EXID 0x001FFFF8U
1595 #define CAN_TI1R_STID 0xFFE00000U
1597 /******************* Bit definition for CAN_TDT1R register ******************/
1598 #define CAN_TDT1R_DLC 0x0000000FU
1599 #define CAN_TDT1R_TGT 0x00000100U
1600 #define CAN_TDT1R_TIME 0xFFFF0000U
1602 /******************* Bit definition for CAN_TDL1R register ******************/
1603 #define CAN_TDL1R_DATA0 0x000000FFU
1604 #define CAN_TDL1R_DATA1 0x0000FF00U
1605 #define CAN_TDL1R_DATA2 0x00FF0000U
1606 #define CAN_TDL1R_DATA3 0xFF000000U
1608 /******************* Bit definition for CAN_TDH1R register ******************/
1609 #define CAN_TDH1R_DATA4 0x000000FFU
1610 #define CAN_TDH1R_DATA5 0x0000FF00U
1611 #define CAN_TDH1R_DATA6 0x00FF0000U
1612 #define CAN_TDH1R_DATA7 0xFF000000U
1614 /******************* Bit definition for CAN_TI2R register *******************/
1615 #define CAN_TI2R_TXRQ 0x00000001U
1616 #define CAN_TI2R_RTR 0x00000002U
1617 #define CAN_TI2R_IDE 0x00000004U
1618 #define CAN_TI2R_EXID 0x001FFFF8U
1619 #define CAN_TI2R_STID 0xFFE00000U
1621 /******************* Bit definition for CAN_TDT2R register ******************/
1622 #define CAN_TDT2R_DLC 0x0000000FU
1623 #define CAN_TDT2R_TGT 0x00000100U
1624 #define CAN_TDT2R_TIME 0xFFFF0000U
1626 /******************* Bit definition for CAN_TDL2R register ******************/
1627 #define CAN_TDL2R_DATA0 0x000000FFU
1628 #define CAN_TDL2R_DATA1 0x0000FF00U
1629 #define CAN_TDL2R_DATA2 0x00FF0000U
1630 #define CAN_TDL2R_DATA3 0xFF000000U
1632 /******************* Bit definition for CAN_TDH2R register ******************/
1633 #define CAN_TDH2R_DATA4 0x000000FFU
1634 #define CAN_TDH2R_DATA5 0x0000FF00U
1635 #define CAN_TDH2R_DATA6 0x00FF0000U
1636 #define CAN_TDH2R_DATA7 0xFF000000U
1638 /******************* Bit definition for CAN_RI0R register *******************/
1639 #define CAN_RI0R_RTR 0x00000002U
1640 #define CAN_RI0R_IDE 0x00000004U
1641 #define CAN_RI0R_EXID 0x001FFFF8U
1642 #define CAN_RI0R_STID 0xFFE00000U
1644 /******************* Bit definition for CAN_RDT0R register ******************/
1645 #define CAN_RDT0R_DLC 0x0000000FU
1646 #define CAN_RDT0R_FMI 0x0000FF00U
1647 #define CAN_RDT0R_TIME 0xFFFF0000U
1649 /******************* Bit definition for CAN_RDL0R register ******************/
1650 #define CAN_RDL0R_DATA0 0x000000FFU
1651 #define CAN_RDL0R_DATA1 0x0000FF00U
1652 #define CAN_RDL0R_DATA2 0x00FF0000U
1653 #define CAN_RDL0R_DATA3 0xFF000000U
1655 /******************* Bit definition for CAN_RDH0R register ******************/
1656 #define CAN_RDH0R_DATA4 0x000000FFU
1657 #define CAN_RDH0R_DATA5 0x0000FF00U
1658 #define CAN_RDH0R_DATA6 0x00FF0000U
1659 #define CAN_RDH0R_DATA7 0xFF000000U
1661 /******************* Bit definition for CAN_RI1R register *******************/
1662 #define CAN_RI1R_RTR 0x00000002U
1663 #define CAN_RI1R_IDE 0x00000004U
1664 #define CAN_RI1R_EXID 0x001FFFF8U
1665 #define CAN_RI1R_STID 0xFFE00000U
1667 /******************* Bit definition for CAN_RDT1R register ******************/
1668 #define CAN_RDT1R_DLC 0x0000000FU
1669 #define CAN_RDT1R_FMI 0x0000FF00U
1670 #define CAN_RDT1R_TIME 0xFFFF0000U
1672 /******************* Bit definition for CAN_RDL1R register ******************/
1673 #define CAN_RDL1R_DATA0 0x000000FFU
1674 #define CAN_RDL1R_DATA1 0x0000FF00U
1675 #define CAN_RDL1R_DATA2 0x00FF0000U
1676 #define CAN_RDL1R_DATA3 0xFF000000U
1678 /******************* Bit definition for CAN_RDH1R register ******************/
1679 #define CAN_RDH1R_DATA4 0x000000FFU
1680 #define CAN_RDH1R_DATA5 0x0000FF00U
1681 #define CAN_RDH1R_DATA6 0x00FF0000U
1682 #define CAN_RDH1R_DATA7 0xFF000000U
1685 /******************* Bit definition for CAN_FMR register ********************/
1686 #define CAN_FMR_FINIT 0x01U
1687 #define CAN_FMR_CAN2SB 0x00003F00U
1689 /******************* Bit definition for CAN_FM1R register *******************/
1690 #define CAN_FM1R_FBM 0x0FFFFFFFU
1691 #define CAN_FM1R_FBM0 0x00000001U
1692 #define CAN_FM1R_FBM1 0x00000002U
1693 #define CAN_FM1R_FBM2 0x00000004U
1694 #define CAN_FM1R_FBM3 0x00000008U
1695 #define CAN_FM1R_FBM4 0x00000010U
1696 #define CAN_FM1R_FBM5 0x00000020U
1697 #define CAN_FM1R_FBM6 0x00000040U
1698 #define CAN_FM1R_FBM7 0x00000080U
1699 #define CAN_FM1R_FBM8 0x00000100U
1700 #define CAN_FM1R_FBM9 0x00000200U
1701 #define CAN_FM1R_FBM10 0x00000400U
1702 #define CAN_FM1R_FBM11 0x00000800U
1703 #define CAN_FM1R_FBM12 0x00001000U
1704 #define CAN_FM1R_FBM13 0x00002000U
1705 #define CAN_FM1R_FBM14 0x00004000U
1706 #define CAN_FM1R_FBM15 0x00008000U
1707 #define CAN_FM1R_FBM16 0x00010000U
1708 #define CAN_FM1R_FBM17 0x00020000U
1709 #define CAN_FM1R_FBM18 0x00040000U
1710 #define CAN_FM1R_FBM19 0x00080000U
1711 #define CAN_FM1R_FBM20 0x00100000U
1712 #define CAN_FM1R_FBM21 0x00200000U
1713 #define CAN_FM1R_FBM22 0x00400000U
1714 #define CAN_FM1R_FBM23 0x00800000U
1715 #define CAN_FM1R_FBM24 0x01000000U
1716 #define CAN_FM1R_FBM25 0x02000000U
1717 #define CAN_FM1R_FBM26 0x04000000U
1718 #define CAN_FM1R_FBM27 0x08000000U
1720 /******************* Bit definition for CAN_FS1R register *******************/
1721 #define CAN_FS1R_FSC 0x0FFFFFFFU
1722 #define CAN_FS1R_FSC0 0x00000001U
1723 #define CAN_FS1R_FSC1 0x00000002U
1724 #define CAN_FS1R_FSC2 0x00000004U
1725 #define CAN_FS1R_FSC3 0x00000008U
1726 #define CAN_FS1R_FSC4 0x00000010U
1727 #define CAN_FS1R_FSC5 0x00000020U
1728 #define CAN_FS1R_FSC6 0x00000040U
1729 #define CAN_FS1R_FSC7 0x00000080U
1730 #define CAN_FS1R_FSC8 0x00000100U
1731 #define CAN_FS1R_FSC9 0x00000200U
1732 #define CAN_FS1R_FSC10 0x00000400U
1733 #define CAN_FS1R_FSC11 0x00000800U
1734 #define CAN_FS1R_FSC12 0x00001000U
1735 #define CAN_FS1R_FSC13 0x00002000U
1736 #define CAN_FS1R_FSC14 0x00004000U
1737 #define CAN_FS1R_FSC15 0x00008000U
1738 #define CAN_FS1R_FSC16 0x00010000U
1739 #define CAN_FS1R_FSC17 0x00020000U
1740 #define CAN_FS1R_FSC18 0x00040000U
1741 #define CAN_FS1R_FSC19 0x00080000U
1742 #define CAN_FS1R_FSC20 0x00100000U
1743 #define CAN_FS1R_FSC21 0x00200000U
1744 #define CAN_FS1R_FSC22 0x00400000U
1745 #define CAN_FS1R_FSC23 0x00800000U
1746 #define CAN_FS1R_FSC24 0x01000000U
1747 #define CAN_FS1R_FSC25 0x02000000U
1748 #define CAN_FS1R_FSC26 0x04000000U
1749 #define CAN_FS1R_FSC27 0x08000000U
1751 /****************** Bit definition for CAN_FFA1R register *******************/
1752 #define CAN_FFA1R_FFA 0x0FFFFFFFU
1753 #define CAN_FFA1R_FFA0 0x00000001U
1754 #define CAN_FFA1R_FFA1 0x00000002U
1755 #define CAN_FFA1R_FFA2 0x00000004U
1756 #define CAN_FFA1R_FFA3 0x00000008U
1757 #define CAN_FFA1R_FFA4 0x00000010U
1758 #define CAN_FFA1R_FFA5 0x00000020U
1759 #define CAN_FFA1R_FFA6 0x00000040U
1760 #define CAN_FFA1R_FFA7 0x00000080U
1761 #define CAN_FFA1R_FFA8 0x00000100U
1762 #define CAN_FFA1R_FFA9 0x00000200U
1763 #define CAN_FFA1R_FFA10 0x00000400U
1764 #define CAN_FFA1R_FFA11 0x00000800U
1765 #define CAN_FFA1R_FFA12 0x00001000U
1766 #define CAN_FFA1R_FFA13 0x00002000U
1767 #define CAN_FFA1R_FFA14 0x00004000U
1768 #define CAN_FFA1R_FFA15 0x00008000U
1769 #define CAN_FFA1R_FFA16 0x00010000U
1770 #define CAN_FFA1R_FFA17 0x00020000U
1771 #define CAN_FFA1R_FFA18 0x00040000U
1772 #define CAN_FFA1R_FFA19 0x00080000U
1773 #define CAN_FFA1R_FFA20 0x00100000U
1774 #define CAN_FFA1R_FFA21 0x00200000U
1775 #define CAN_FFA1R_FFA22 0x00400000U
1776 #define CAN_FFA1R_FFA23 0x00800000U
1777 #define CAN_FFA1R_FFA24 0x01000000U
1778 #define CAN_FFA1R_FFA25 0x02000000U
1779 #define CAN_FFA1R_FFA26 0x04000000U
1780 #define CAN_FFA1R_FFA27 0x08000000U
1782 /******************* Bit definition for CAN_FA1R register *******************/
1783 #define CAN_FA1R_FACT 0x0FFFFFFFU
1784 #define CAN_FA1R_FACT0 0x00000001U
1785 #define CAN_FA1R_FACT1 0x00000002U
1786 #define CAN_FA1R_FACT2 0x00000004U
1787 #define CAN_FA1R_FACT3 0x00000008U
1788 #define CAN_FA1R_FACT4 0x00000010U
1789 #define CAN_FA1R_FACT5 0x00000020U
1790 #define CAN_FA1R_FACT6 0x00000040U
1791 #define CAN_FA1R_FACT7 0x00000080U
1792 #define CAN_FA1R_FACT8 0x00000100U
1793 #define CAN_FA1R_FACT9 0x00000200U
1794 #define CAN_FA1R_FACT10 0x00000400U
1795 #define CAN_FA1R_FACT11 0x00000800U
1796 #define CAN_FA1R_FACT12 0x00001000U
1797 #define CAN_FA1R_FACT13 0x00002000U
1798 #define CAN_FA1R_FACT14 0x00004000U
1799 #define CAN_FA1R_FACT15 0x00008000U
1800 #define CAN_FA1R_FACT16 0x00010000U
1801 #define CAN_FA1R_FACT17 0x00020000U
1802 #define CAN_FA1R_FACT18 0x00040000U
1803 #define CAN_FA1R_FACT19 0x00080000U
1804 #define CAN_FA1R_FACT20 0x00100000U
1805 #define CAN_FA1R_FACT21 0x00200000U
1806 #define CAN_FA1R_FACT22 0x00400000U
1807 #define CAN_FA1R_FACT23 0x00800000U
1808 #define CAN_FA1R_FACT24 0x01000000U
1809 #define CAN_FA1R_FACT25 0x02000000U
1810 #define CAN_FA1R_FACT26 0x04000000U
1811 #define CAN_FA1R_FACT27 0x08000000U
1813 /******************* Bit definition for CAN_F0R1 register *******************/
1814 #define CAN_F0R1_FB0 0x00000001U
1815 #define CAN_F0R1_FB1 0x00000002U
1816 #define CAN_F0R1_FB2 0x00000004U
1817 #define CAN_F0R1_FB3 0x00000008U
1818 #define CAN_F0R1_FB4 0x00000010U
1819 #define CAN_F0R1_FB5 0x00000020U
1820 #define CAN_F0R1_FB6 0x00000040U
1821 #define CAN_F0R1_FB7 0x00000080U
1822 #define CAN_F0R1_FB8 0x00000100U
1823 #define CAN_F0R1_FB9 0x00000200U
1824 #define CAN_F0R1_FB10 0x00000400U
1825 #define CAN_F0R1_FB11 0x00000800U
1826 #define CAN_F0R1_FB12 0x00001000U
1827 #define CAN_F0R1_FB13 0x00002000U
1828 #define CAN_F0R1_FB14 0x00004000U
1829 #define CAN_F0R1_FB15 0x00008000U
1830 #define CAN_F0R1_FB16 0x00010000U
1831 #define CAN_F0R1_FB17 0x00020000U
1832 #define CAN_F0R1_FB18 0x00040000U
1833 #define CAN_F0R1_FB19 0x00080000U
1834 #define CAN_F0R1_FB20 0x00100000U
1835 #define CAN_F0R1_FB21 0x00200000U
1836 #define CAN_F0R1_FB22 0x00400000U
1837 #define CAN_F0R1_FB23 0x00800000U
1838 #define CAN_F0R1_FB24 0x01000000U
1839 #define CAN_F0R1_FB25 0x02000000U
1840 #define CAN_F0R1_FB26 0x04000000U
1841 #define CAN_F0R1_FB27 0x08000000U
1842 #define CAN_F0R1_FB28 0x10000000U
1843 #define CAN_F0R1_FB29 0x20000000U
1844 #define CAN_F0R1_FB30 0x40000000U
1845 #define CAN_F0R1_FB31 0x80000000U
1847 /******************* Bit definition for CAN_F1R1 register *******************/
1848 #define CAN_F1R1_FB0 0x00000001U
1849 #define CAN_F1R1_FB1 0x00000002U
1850 #define CAN_F1R1_FB2 0x00000004U
1851 #define CAN_F1R1_FB3 0x00000008U
1852 #define CAN_F1R1_FB4 0x00000010U
1853 #define CAN_F1R1_FB5 0x00000020U
1854 #define CAN_F1R1_FB6 0x00000040U
1855 #define CAN_F1R1_FB7 0x00000080U
1856 #define CAN_F1R1_FB8 0x00000100U
1857 #define CAN_F1R1_FB9 0x00000200U
1858 #define CAN_F1R1_FB10 0x00000400U
1859 #define CAN_F1R1_FB11 0x00000800U
1860 #define CAN_F1R1_FB12 0x00001000U
1861 #define CAN_F1R1_FB13 0x00002000U
1862 #define CAN_F1R1_FB14 0x00004000U
1863 #define CAN_F1R1_FB15 0x00008000U
1864 #define CAN_F1R1_FB16 0x00010000U
1865 #define CAN_F1R1_FB17 0x00020000U
1866 #define CAN_F1R1_FB18 0x00040000U
1867 #define CAN_F1R1_FB19 0x00080000U
1868 #define CAN_F1R1_FB20 0x00100000U
1869 #define CAN_F1R1_FB21 0x00200000U
1870 #define CAN_F1R1_FB22 0x00400000U
1871 #define CAN_F1R1_FB23 0x00800000U
1872 #define CAN_F1R1_FB24 0x01000000U
1873 #define CAN_F1R1_FB25 0x02000000U
1874 #define CAN_F1R1_FB26 0x04000000U
1875 #define CAN_F1R1_FB27 0x08000000U
1876 #define CAN_F1R1_FB28 0x10000000U
1877 #define CAN_F1R1_FB29 0x20000000U
1878 #define CAN_F1R1_FB30 0x40000000U
1879 #define CAN_F1R1_FB31 0x80000000U
1881 /******************* Bit definition for CAN_F2R1 register *******************/
1882 #define CAN_F2R1_FB0 0x00000001U
1883 #define CAN_F2R1_FB1 0x00000002U
1884 #define CAN_F2R1_FB2 0x00000004U
1885 #define CAN_F2R1_FB3 0x00000008U
1886 #define CAN_F2R1_FB4 0x00000010U
1887 #define CAN_F2R1_FB5 0x00000020U
1888 #define CAN_F2R1_FB6 0x00000040U
1889 #define CAN_F2R1_FB7 0x00000080U
1890 #define CAN_F2R1_FB8 0x00000100U
1891 #define CAN_F2R1_FB9 0x00000200U
1892 #define CAN_F2R1_FB10 0x00000400U
1893 #define CAN_F2R1_FB11 0x00000800U
1894 #define CAN_F2R1_FB12 0x00001000U
1895 #define CAN_F2R1_FB13 0x00002000U
1896 #define CAN_F2R1_FB14 0x00004000U
1897 #define CAN_F2R1_FB15 0x00008000U
1898 #define CAN_F2R1_FB16 0x00010000U
1899 #define CAN_F2R1_FB17 0x00020000U
1900 #define CAN_F2R1_FB18 0x00040000U
1901 #define CAN_F2R1_FB19 0x00080000U
1902 #define CAN_F2R1_FB20 0x00100000U
1903 #define CAN_F2R1_FB21 0x00200000U
1904 #define CAN_F2R1_FB22 0x00400000U
1905 #define CAN_F2R1_FB23 0x00800000U
1906 #define CAN_F2R1_FB24 0x01000000U
1907 #define CAN_F2R1_FB25 0x02000000U
1908 #define CAN_F2R1_FB26 0x04000000U
1909 #define CAN_F2R1_FB27 0x08000000U
1910 #define CAN_F2R1_FB28 0x10000000U
1911 #define CAN_F2R1_FB29 0x20000000U
1912 #define CAN_F2R1_FB30 0x40000000U
1913 #define CAN_F2R1_FB31 0x80000000U
1915 /******************* Bit definition for CAN_F3R1 register *******************/
1916 #define CAN_F3R1_FB0 0x00000001U
1917 #define CAN_F3R1_FB1 0x00000002U
1918 #define CAN_F3R1_FB2 0x00000004U
1919 #define CAN_F3R1_FB3 0x00000008U
1920 #define CAN_F3R1_FB4 0x00000010U
1921 #define CAN_F3R1_FB5 0x00000020U
1922 #define CAN_F3R1_FB6 0x00000040U
1923 #define CAN_F3R1_FB7 0x00000080U
1924 #define CAN_F3R1_FB8 0x00000100U
1925 #define CAN_F3R1_FB9 0x00000200U
1926 #define CAN_F3R1_FB10 0x00000400U
1927 #define CAN_F3R1_FB11 0x00000800U
1928 #define CAN_F3R1_FB12 0x00001000U
1929 #define CAN_F3R1_FB13 0x00002000U
1930 #define CAN_F3R1_FB14 0x00004000U
1931 #define CAN_F3R1_FB15 0x00008000U
1932 #define CAN_F3R1_FB16 0x00010000U
1933 #define CAN_F3R1_FB17 0x00020000U
1934 #define CAN_F3R1_FB18 0x00040000U
1935 #define CAN_F3R1_FB19 0x00080000U
1936 #define CAN_F3R1_FB20 0x00100000U
1937 #define CAN_F3R1_FB21 0x00200000U
1938 #define CAN_F3R1_FB22 0x00400000U
1939 #define CAN_F3R1_FB23 0x00800000U
1940 #define CAN_F3R1_FB24 0x01000000U
1941 #define CAN_F3R1_FB25 0x02000000U
1942 #define CAN_F3R1_FB26 0x04000000U
1943 #define CAN_F3R1_FB27 0x08000000U
1944 #define CAN_F3R1_FB28 0x10000000U
1945 #define CAN_F3R1_FB29 0x20000000U
1946 #define CAN_F3R1_FB30 0x40000000U
1947 #define CAN_F3R1_FB31 0x80000000U
1949 /******************* Bit definition for CAN_F4R1 register *******************/
1950 #define CAN_F4R1_FB0 0x00000001U
1951 #define CAN_F4R1_FB1 0x00000002U
1952 #define CAN_F4R1_FB2 0x00000004U
1953 #define CAN_F4R1_FB3 0x00000008U
1954 #define CAN_F4R1_FB4 0x00000010U
1955 #define CAN_F4R1_FB5 0x00000020U
1956 #define CAN_F4R1_FB6 0x00000040U
1957 #define CAN_F4R1_FB7 0x00000080U
1958 #define CAN_F4R1_FB8 0x00000100U
1959 #define CAN_F4R1_FB9 0x00000200U
1960 #define CAN_F4R1_FB10 0x00000400U
1961 #define CAN_F4R1_FB11 0x00000800U
1962 #define CAN_F4R1_FB12 0x00001000U
1963 #define CAN_F4R1_FB13 0x00002000U
1964 #define CAN_F4R1_FB14 0x00004000U
1965 #define CAN_F4R1_FB15 0x00008000U
1966 #define CAN_F4R1_FB16 0x00010000U
1967 #define CAN_F4R1_FB17 0x00020000U
1968 #define CAN_F4R1_FB18 0x00040000U
1969 #define CAN_F4R1_FB19 0x00080000U
1970 #define CAN_F4R1_FB20 0x00100000U
1971 #define CAN_F4R1_FB21 0x00200000U
1972 #define CAN_F4R1_FB22 0x00400000U
1973 #define CAN_F4R1_FB23 0x00800000U
1974 #define CAN_F4R1_FB24 0x01000000U
1975 #define CAN_F4R1_FB25 0x02000000U
1976 #define CAN_F4R1_FB26 0x04000000U
1977 #define CAN_F4R1_FB27 0x08000000U
1978 #define CAN_F4R1_FB28 0x10000000U
1979 #define CAN_F4R1_FB29 0x20000000U
1980 #define CAN_F4R1_FB30 0x40000000U
1981 #define CAN_F4R1_FB31 0x80000000U
1983 /******************* Bit definition for CAN_F5R1 register *******************/
1984 #define CAN_F5R1_FB0 0x00000001U
1985 #define CAN_F5R1_FB1 0x00000002U
1986 #define CAN_F5R1_FB2 0x00000004U
1987 #define CAN_F5R1_FB3 0x00000008U
1988 #define CAN_F5R1_FB4 0x00000010U
1989 #define CAN_F5R1_FB5 0x00000020U
1990 #define CAN_F5R1_FB6 0x00000040U
1991 #define CAN_F5R1_FB7 0x00000080U
1992 #define CAN_F5R1_FB8 0x00000100U
1993 #define CAN_F5R1_FB9 0x00000200U
1994 #define CAN_F5R1_FB10 0x00000400U
1995 #define CAN_F5R1_FB11 0x00000800U
1996 #define CAN_F5R1_FB12 0x00001000U
1997 #define CAN_F5R1_FB13 0x00002000U
1998 #define CAN_F5R1_FB14 0x00004000U
1999 #define CAN_F5R1_FB15 0x00008000U
2000 #define CAN_F5R1_FB16 0x00010000U
2001 #define CAN_F5R1_FB17 0x00020000U
2002 #define CAN_F5R1_FB18 0x00040000U
2003 #define CAN_F5R1_FB19 0x00080000U
2004 #define CAN_F5R1_FB20 0x00100000U
2005 #define CAN_F5R1_FB21 0x00200000U
2006 #define CAN_F5R1_FB22 0x00400000U
2007 #define CAN_F5R1_FB23 0x00800000U
2008 #define CAN_F5R1_FB24 0x01000000U
2009 #define CAN_F5R1_FB25 0x02000000U
2010 #define CAN_F5R1_FB26 0x04000000U
2011 #define CAN_F5R1_FB27 0x08000000U
2012 #define CAN_F5R1_FB28 0x10000000U
2013 #define CAN_F5R1_FB29 0x20000000U
2014 #define CAN_F5R1_FB30 0x40000000U
2015 #define CAN_F5R1_FB31 0x80000000U
2017 /******************* Bit definition for CAN_F6R1 register *******************/
2018 #define CAN_F6R1_FB0 0x00000001U
2019 #define CAN_F6R1_FB1 0x00000002U
2020 #define CAN_F6R1_FB2 0x00000004U
2021 #define CAN_F6R1_FB3 0x00000008U
2022 #define CAN_F6R1_FB4 0x00000010U
2023 #define CAN_F6R1_FB5 0x00000020U
2024 #define CAN_F6R1_FB6 0x00000040U
2025 #define CAN_F6R1_FB7 0x00000080U
2026 #define CAN_F6R1_FB8 0x00000100U
2027 #define CAN_F6R1_FB9 0x00000200U
2028 #define CAN_F6R1_FB10 0x00000400U
2029 #define CAN_F6R1_FB11 0x00000800U
2030 #define CAN_F6R1_FB12 0x00001000U
2031 #define CAN_F6R1_FB13 0x00002000U
2032 #define CAN_F6R1_FB14 0x00004000U
2033 #define CAN_F6R1_FB15 0x00008000U
2034 #define CAN_F6R1_FB16 0x00010000U
2035 #define CAN_F6R1_FB17 0x00020000U
2036 #define CAN_F6R1_FB18 0x00040000U
2037 #define CAN_F6R1_FB19 0x00080000U
2038 #define CAN_F6R1_FB20 0x00100000U
2039 #define CAN_F6R1_FB21 0x00200000U
2040 #define CAN_F6R1_FB22 0x00400000U
2041 #define CAN_F6R1_FB23 0x00800000U
2042 #define CAN_F6R1_FB24 0x01000000U
2043 #define CAN_F6R1_FB25 0x02000000U
2044 #define CAN_F6R1_FB26 0x04000000U
2045 #define CAN_F6R1_FB27 0x08000000U
2046 #define CAN_F6R1_FB28 0x10000000U
2047 #define CAN_F6R1_FB29 0x20000000U
2048 #define CAN_F6R1_FB30 0x40000000U
2049 #define CAN_F6R1_FB31 0x80000000U
2051 /******************* Bit definition for CAN_F7R1 register *******************/
2052 #define CAN_F7R1_FB0 0x00000001U
2053 #define CAN_F7R1_FB1 0x00000002U
2054 #define CAN_F7R1_FB2 0x00000004U
2055 #define CAN_F7R1_FB3 0x00000008U
2056 #define CAN_F7R1_FB4 0x00000010U
2057 #define CAN_F7R1_FB5 0x00000020U
2058 #define CAN_F7R1_FB6 0x00000040U
2059 #define CAN_F7R1_FB7 0x00000080U
2060 #define CAN_F7R1_FB8 0x00000100U
2061 #define CAN_F7R1_FB9 0x00000200U
2062 #define CAN_F7R1_FB10 0x00000400U
2063 #define CAN_F7R1_FB11 0x00000800U
2064 #define CAN_F7R1_FB12 0x00001000U
2065 #define CAN_F7R1_FB13 0x00002000U
2066 #define CAN_F7R1_FB14 0x00004000U
2067 #define CAN_F7R1_FB15 0x00008000U
2068 #define CAN_F7R1_FB16 0x00010000U
2069 #define CAN_F7R1_FB17 0x00020000U
2070 #define CAN_F7R1_FB18 0x00040000U
2071 #define CAN_F7R1_FB19 0x00080000U
2072 #define CAN_F7R1_FB20 0x00100000U
2073 #define CAN_F7R1_FB21 0x00200000U
2074 #define CAN_F7R1_FB22 0x00400000U
2075 #define CAN_F7R1_FB23 0x00800000U
2076 #define CAN_F7R1_FB24 0x01000000U
2077 #define CAN_F7R1_FB25 0x02000000U
2078 #define CAN_F7R1_FB26 0x04000000U
2079 #define CAN_F7R1_FB27 0x08000000U
2080 #define CAN_F7R1_FB28 0x10000000U
2081 #define CAN_F7R1_FB29 0x20000000U
2082 #define CAN_F7R1_FB30 0x40000000U
2083 #define CAN_F7R1_FB31 0x80000000U
2085 /******************* Bit definition for CAN_F8R1 register *******************/
2086 #define CAN_F8R1_FB0 0x00000001U
2087 #define CAN_F8R1_FB1 0x00000002U
2088 #define CAN_F8R1_FB2 0x00000004U
2089 #define CAN_F8R1_FB3 0x00000008U
2090 #define CAN_F8R1_FB4 0x00000010U
2091 #define CAN_F8R1_FB5 0x00000020U
2092 #define CAN_F8R1_FB6 0x00000040U
2093 #define CAN_F8R1_FB7 0x00000080U
2094 #define CAN_F8R1_FB8 0x00000100U
2095 #define CAN_F8R1_FB9 0x00000200U
2096 #define CAN_F8R1_FB10 0x00000400U
2097 #define CAN_F8R1_FB11 0x00000800U
2098 #define CAN_F8R1_FB12 0x00001000U
2099 #define CAN_F8R1_FB13 0x00002000U
2100 #define CAN_F8R1_FB14 0x00004000U
2101 #define CAN_F8R1_FB15 0x00008000U
2102 #define CAN_F8R1_FB16 0x00010000U
2103 #define CAN_F8R1_FB17 0x00020000U
2104 #define CAN_F8R1_FB18 0x00040000U
2105 #define CAN_F8R1_FB19 0x00080000U
2106 #define CAN_F8R1_FB20 0x00100000U
2107 #define CAN_F8R1_FB21 0x00200000U
2108 #define CAN_F8R1_FB22 0x00400000U
2109 #define CAN_F8R1_FB23 0x00800000U
2110 #define CAN_F8R1_FB24 0x01000000U
2111 #define CAN_F8R1_FB25 0x02000000U
2112 #define CAN_F8R1_FB26 0x04000000U
2113 #define CAN_F8R1_FB27 0x08000000U
2114 #define CAN_F8R1_FB28 0x10000000U
2115 #define CAN_F8R1_FB29 0x20000000U
2116 #define CAN_F8R1_FB30 0x40000000U
2117 #define CAN_F8R1_FB31 0x80000000U
2119 /******************* Bit definition for CAN_F9R1 register *******************/
2120 #define CAN_F9R1_FB0 0x00000001U
2121 #define CAN_F9R1_FB1 0x00000002U
2122 #define CAN_F9R1_FB2 0x00000004U
2123 #define CAN_F9R1_FB3 0x00000008U
2124 #define CAN_F9R1_FB4 0x00000010U
2125 #define CAN_F9R1_FB5 0x00000020U
2126 #define CAN_F9R1_FB6 0x00000040U
2127 #define CAN_F9R1_FB7 0x00000080U
2128 #define CAN_F9R1_FB8 0x00000100U
2129 #define CAN_F9R1_FB9 0x00000200U
2130 #define CAN_F9R1_FB10 0x00000400U
2131 #define CAN_F9R1_FB11 0x00000800U
2132 #define CAN_F9R1_FB12 0x00001000U
2133 #define CAN_F9R1_FB13 0x00002000U
2134 #define CAN_F9R1_FB14 0x00004000U
2135 #define CAN_F9R1_FB15 0x00008000U
2136 #define CAN_F9R1_FB16 0x00010000U
2137 #define CAN_F9R1_FB17 0x00020000U
2138 #define CAN_F9R1_FB18 0x00040000U
2139 #define CAN_F9R1_FB19 0x00080000U
2140 #define CAN_F9R1_FB20 0x00100000U
2141 #define CAN_F9R1_FB21 0x00200000U
2142 #define CAN_F9R1_FB22 0x00400000U
2143 #define CAN_F9R1_FB23 0x00800000U
2144 #define CAN_F9R1_FB24 0x01000000U
2145 #define CAN_F9R1_FB25 0x02000000U
2146 #define CAN_F9R1_FB26 0x04000000U
2147 #define CAN_F9R1_FB27 0x08000000U
2148 #define CAN_F9R1_FB28 0x10000000U
2149 #define CAN_F9R1_FB29 0x20000000U
2150 #define CAN_F9R1_FB30 0x40000000U
2151 #define CAN_F9R1_FB31 0x80000000U
2153 /******************* Bit definition for CAN_F10R1 register ******************/
2154 #define CAN_F10R1_FB0 0x00000001U
2155 #define CAN_F10R1_FB1 0x00000002U
2156 #define CAN_F10R1_FB2 0x00000004U
2157 #define CAN_F10R1_FB3 0x00000008U
2158 #define CAN_F10R1_FB4 0x00000010U
2159 #define CAN_F10R1_FB5 0x00000020U
2160 #define CAN_F10R1_FB6 0x00000040U
2161 #define CAN_F10R1_FB7 0x00000080U
2162 #define CAN_F10R1_FB8 0x00000100U
2163 #define CAN_F10R1_FB9 0x00000200U
2164 #define CAN_F10R1_FB10 0x00000400U
2165 #define CAN_F10R1_FB11 0x00000800U
2166 #define CAN_F10R1_FB12 0x00001000U
2167 #define CAN_F10R1_FB13 0x00002000U
2168 #define CAN_F10R1_FB14 0x00004000U
2169 #define CAN_F10R1_FB15 0x00008000U
2170 #define CAN_F10R1_FB16 0x00010000U
2171 #define CAN_F10R1_FB17 0x00020000U
2172 #define CAN_F10R1_FB18 0x00040000U
2173 #define CAN_F10R1_FB19 0x00080000U
2174 #define CAN_F10R1_FB20 0x00100000U
2175 #define CAN_F10R1_FB21 0x00200000U
2176 #define CAN_F10R1_FB22 0x00400000U
2177 #define CAN_F10R1_FB23 0x00800000U
2178 #define CAN_F10R1_FB24 0x01000000U
2179 #define CAN_F10R1_FB25 0x02000000U
2180 #define CAN_F10R1_FB26 0x04000000U
2181 #define CAN_F10R1_FB27 0x08000000U
2182 #define CAN_F10R1_FB28 0x10000000U
2183 #define CAN_F10R1_FB29 0x20000000U
2184 #define CAN_F10R1_FB30 0x40000000U
2185 #define CAN_F10R1_FB31 0x80000000U
2187 /******************* Bit definition for CAN_F11R1 register ******************/
2188 #define CAN_F11R1_FB0 0x00000001U
2189 #define CAN_F11R1_FB1 0x00000002U
2190 #define CAN_F11R1_FB2 0x00000004U
2191 #define CAN_F11R1_FB3 0x00000008U
2192 #define CAN_F11R1_FB4 0x00000010U
2193 #define CAN_F11R1_FB5 0x00000020U
2194 #define CAN_F11R1_FB6 0x00000040U
2195 #define CAN_F11R1_FB7 0x00000080U
2196 #define CAN_F11R1_FB8 0x00000100U
2197 #define CAN_F11R1_FB9 0x00000200U
2198 #define CAN_F11R1_FB10 0x00000400U
2199 #define CAN_F11R1_FB11 0x00000800U
2200 #define CAN_F11R1_FB12 0x00001000U
2201 #define CAN_F11R1_FB13 0x00002000U
2202 #define CAN_F11R1_FB14 0x00004000U
2203 #define CAN_F11R1_FB15 0x00008000U
2204 #define CAN_F11R1_FB16 0x00010000U
2205 #define CAN_F11R1_FB17 0x00020000U
2206 #define CAN_F11R1_FB18 0x00040000U
2207 #define CAN_F11R1_FB19 0x00080000U
2208 #define CAN_F11R1_FB20 0x00100000U
2209 #define CAN_F11R1_FB21 0x00200000U
2210 #define CAN_F11R1_FB22 0x00400000U
2211 #define CAN_F11R1_FB23 0x00800000U
2212 #define CAN_F11R1_FB24 0x01000000U
2213 #define CAN_F11R1_FB25 0x02000000U
2214 #define CAN_F11R1_FB26 0x04000000U
2215 #define CAN_F11R1_FB27 0x08000000U
2216 #define CAN_F11R1_FB28 0x10000000U
2217 #define CAN_F11R1_FB29 0x20000000U
2218 #define CAN_F11R1_FB30 0x40000000U
2219 #define CAN_F11R1_FB31 0x80000000U
2221 /******************* Bit definition for CAN_F12R1 register ******************/
2222 #define CAN_F12R1_FB0 0x00000001U
2223 #define CAN_F12R1_FB1 0x00000002U
2224 #define CAN_F12R1_FB2 0x00000004U
2225 #define CAN_F12R1_FB3 0x00000008U
2226 #define CAN_F12R1_FB4 0x00000010U
2227 #define CAN_F12R1_FB5 0x00000020U
2228 #define CAN_F12R1_FB6 0x00000040U
2229 #define CAN_F12R1_FB7 0x00000080U
2230 #define CAN_F12R1_FB8 0x00000100U
2231 #define CAN_F12R1_FB9 0x00000200U
2232 #define CAN_F12R1_FB10 0x00000400U
2233 #define CAN_F12R1_FB11 0x00000800U
2234 #define CAN_F12R1_FB12 0x00001000U
2235 #define CAN_F12R1_FB13 0x00002000U
2236 #define CAN_F12R1_FB14 0x00004000U
2237 #define CAN_F12R1_FB15 0x00008000U
2238 #define CAN_F12R1_FB16 0x00010000U
2239 #define CAN_F12R1_FB17 0x00020000U
2240 #define CAN_F12R1_FB18 0x00040000U
2241 #define CAN_F12R1_FB19 0x00080000U
2242 #define CAN_F12R1_FB20 0x00100000U
2243 #define CAN_F12R1_FB21 0x00200000U
2244 #define CAN_F12R1_FB22 0x00400000U
2245 #define CAN_F12R1_FB23 0x00800000U
2246 #define CAN_F12R1_FB24 0x01000000U
2247 #define CAN_F12R1_FB25 0x02000000U
2248 #define CAN_F12R1_FB26 0x04000000U
2249 #define CAN_F12R1_FB27 0x08000000U
2250 #define CAN_F12R1_FB28 0x10000000U
2251 #define CAN_F12R1_FB29 0x20000000U
2252 #define CAN_F12R1_FB30 0x40000000U
2253 #define CAN_F12R1_FB31 0x80000000U
2255 /******************* Bit definition for CAN_F13R1 register ******************/
2256 #define CAN_F13R1_FB0 0x00000001U
2257 #define CAN_F13R1_FB1 0x00000002U
2258 #define CAN_F13R1_FB2 0x00000004U
2259 #define CAN_F13R1_FB3 0x00000008U
2260 #define CAN_F13R1_FB4 0x00000010U
2261 #define CAN_F13R1_FB5 0x00000020U
2262 #define CAN_F13R1_FB6 0x00000040U
2263 #define CAN_F13R1_FB7 0x00000080U
2264 #define CAN_F13R1_FB8 0x00000100U
2265 #define CAN_F13R1_FB9 0x00000200U
2266 #define CAN_F13R1_FB10 0x00000400U
2267 #define CAN_F13R1_FB11 0x00000800U
2268 #define CAN_F13R1_FB12 0x00001000U
2269 #define CAN_F13R1_FB13 0x00002000U
2270 #define CAN_F13R1_FB14 0x00004000U
2271 #define CAN_F13R1_FB15 0x00008000U
2272 #define CAN_F13R1_FB16 0x00010000U
2273 #define CAN_F13R1_FB17 0x00020000U
2274 #define CAN_F13R1_FB18 0x00040000U
2275 #define CAN_F13R1_FB19 0x00080000U
2276 #define CAN_F13R1_FB20 0x00100000U
2277 #define CAN_F13R1_FB21 0x00200000U
2278 #define CAN_F13R1_FB22 0x00400000U
2279 #define CAN_F13R1_FB23 0x00800000U
2280 #define CAN_F13R1_FB24 0x01000000U
2281 #define CAN_F13R1_FB25 0x02000000U
2282 #define CAN_F13R1_FB26 0x04000000U
2283 #define CAN_F13R1_FB27 0x08000000U
2284 #define CAN_F13R1_FB28 0x10000000U
2285 #define CAN_F13R1_FB29 0x20000000U
2286 #define CAN_F13R1_FB30 0x40000000U
2287 #define CAN_F13R1_FB31 0x80000000U
2289 /******************* Bit definition for CAN_F0R2 register *******************/
2290 #define CAN_F0R2_FB0 0x00000001U
2291 #define CAN_F0R2_FB1 0x00000002U
2292 #define CAN_F0R2_FB2 0x00000004U
2293 #define CAN_F0R2_FB3 0x00000008U
2294 #define CAN_F0R2_FB4 0x00000010U
2295 #define CAN_F0R2_FB5 0x00000020U
2296 #define CAN_F0R2_FB6 0x00000040U
2297 #define CAN_F0R2_FB7 0x00000080U
2298 #define CAN_F0R2_FB8 0x00000100U
2299 #define CAN_F0R2_FB9 0x00000200U
2300 #define CAN_F0R2_FB10 0x00000400U
2301 #define CAN_F0R2_FB11 0x00000800U
2302 #define CAN_F0R2_FB12 0x00001000U
2303 #define CAN_F0R2_FB13 0x00002000U
2304 #define CAN_F0R2_FB14 0x00004000U
2305 #define CAN_F0R2_FB15 0x00008000U
2306 #define CAN_F0R2_FB16 0x00010000U
2307 #define CAN_F0R2_FB17 0x00020000U
2308 #define CAN_F0R2_FB18 0x00040000U
2309 #define CAN_F0R2_FB19 0x00080000U
2310 #define CAN_F0R2_FB20 0x00100000U
2311 #define CAN_F0R2_FB21 0x00200000U
2312 #define CAN_F0R2_FB22 0x00400000U
2313 #define CAN_F0R2_FB23 0x00800000U
2314 #define CAN_F0R2_FB24 0x01000000U
2315 #define CAN_F0R2_FB25 0x02000000U
2316 #define CAN_F0R2_FB26 0x04000000U
2317 #define CAN_F0R2_FB27 0x08000000U
2318 #define CAN_F0R2_FB28 0x10000000U
2319 #define CAN_F0R2_FB29 0x20000000U
2320 #define CAN_F0R2_FB30 0x40000000U
2321 #define CAN_F0R2_FB31 0x80000000U
2323 /******************* Bit definition for CAN_F1R2 register *******************/
2324 #define CAN_F1R2_FB0 0x00000001U
2325 #define CAN_F1R2_FB1 0x00000002U
2326 #define CAN_F1R2_FB2 0x00000004U
2327 #define CAN_F1R2_FB3 0x00000008U
2328 #define CAN_F1R2_FB4 0x00000010U
2329 #define CAN_F1R2_FB5 0x00000020U
2330 #define CAN_F1R2_FB6 0x00000040U
2331 #define CAN_F1R2_FB7 0x00000080U
2332 #define CAN_F1R2_FB8 0x00000100U
2333 #define CAN_F1R2_FB9 0x00000200U
2334 #define CAN_F1R2_FB10 0x00000400U
2335 #define CAN_F1R2_FB11 0x00000800U
2336 #define CAN_F1R2_FB12 0x00001000U
2337 #define CAN_F1R2_FB13 0x00002000U
2338 #define CAN_F1R2_FB14 0x00004000U
2339 #define CAN_F1R2_FB15 0x00008000U
2340 #define CAN_F1R2_FB16 0x00010000U
2341 #define CAN_F1R2_FB17 0x00020000U
2342 #define CAN_F1R2_FB18 0x00040000U
2343 #define CAN_F1R2_FB19 0x00080000U
2344 #define CAN_F1R2_FB20 0x00100000U
2345 #define CAN_F1R2_FB21 0x00200000U
2346 #define CAN_F1R2_FB22 0x00400000U
2347 #define CAN_F1R2_FB23 0x00800000U
2348 #define CAN_F1R2_FB24 0x01000000U
2349 #define CAN_F1R2_FB25 0x02000000U
2350 #define CAN_F1R2_FB26 0x04000000U
2351 #define CAN_F1R2_FB27 0x08000000U
2352 #define CAN_F1R2_FB28 0x10000000U
2353 #define CAN_F1R2_FB29 0x20000000U
2354 #define CAN_F1R2_FB30 0x40000000U
2355 #define CAN_F1R2_FB31 0x80000000U
2357 /******************* Bit definition for CAN_F2R2 register *******************/
2358 #define CAN_F2R2_FB0 0x00000001U
2359 #define CAN_F2R2_FB1 0x00000002U
2360 #define CAN_F2R2_FB2 0x00000004U
2361 #define CAN_F2R2_FB3 0x00000008U
2362 #define CAN_F2R2_FB4 0x00000010U
2363 #define CAN_F2R2_FB5 0x00000020U
2364 #define CAN_F2R2_FB6 0x00000040U
2365 #define CAN_F2R2_FB7 0x00000080U
2366 #define CAN_F2R2_FB8 0x00000100U
2367 #define CAN_F2R2_FB9 0x00000200U
2368 #define CAN_F2R2_FB10 0x00000400U
2369 #define CAN_F2R2_FB11 0x00000800U
2370 #define CAN_F2R2_FB12 0x00001000U
2371 #define CAN_F2R2_FB13 0x00002000U
2372 #define CAN_F2R2_FB14 0x00004000U
2373 #define CAN_F2R2_FB15 0x00008000U
2374 #define CAN_F2R2_FB16 0x00010000U
2375 #define CAN_F2R2_FB17 0x00020000U
2376 #define CAN_F2R2_FB18 0x00040000U
2377 #define CAN_F2R2_FB19 0x00080000U
2378 #define CAN_F2R2_FB20 0x00100000U
2379 #define CAN_F2R2_FB21 0x00200000U
2380 #define CAN_F2R2_FB22 0x00400000U
2381 #define CAN_F2R2_FB23 0x00800000U
2382 #define CAN_F2R2_FB24 0x01000000U
2383 #define CAN_F2R2_FB25 0x02000000U
2384 #define CAN_F2R2_FB26 0x04000000U
2385 #define CAN_F2R2_FB27 0x08000000U
2386 #define CAN_F2R2_FB28 0x10000000U
2387 #define CAN_F2R2_FB29 0x20000000U
2388 #define CAN_F2R2_FB30 0x40000000U
2389 #define CAN_F2R2_FB31 0x80000000U
2391 /******************* Bit definition for CAN_F3R2 register *******************/
2392 #define CAN_F3R2_FB0 0x00000001U
2393 #define CAN_F3R2_FB1 0x00000002U
2394 #define CAN_F3R2_FB2 0x00000004U
2395 #define CAN_F3R2_FB3 0x00000008U
2396 #define CAN_F3R2_FB4 0x00000010U
2397 #define CAN_F3R2_FB5 0x00000020U
2398 #define CAN_F3R2_FB6 0x00000040U
2399 #define CAN_F3R2_FB7 0x00000080U
2400 #define CAN_F3R2_FB8 0x00000100U
2401 #define CAN_F3R2_FB9 0x00000200U
2402 #define CAN_F3R2_FB10 0x00000400U
2403 #define CAN_F3R2_FB11 0x00000800U
2404 #define CAN_F3R2_FB12 0x00001000U
2405 #define CAN_F3R2_FB13 0x00002000U
2406 #define CAN_F3R2_FB14 0x00004000U
2407 #define CAN_F3R2_FB15 0x00008000U
2408 #define CAN_F3R2_FB16 0x00010000U
2409 #define CAN_F3R2_FB17 0x00020000U
2410 #define CAN_F3R2_FB18 0x00040000U
2411 #define CAN_F3R2_FB19 0x00080000U
2412 #define CAN_F3R2_FB20 0x00100000U
2413 #define CAN_F3R2_FB21 0x00200000U
2414 #define CAN_F3R2_FB22 0x00400000U
2415 #define CAN_F3R2_FB23 0x00800000U
2416 #define CAN_F3R2_FB24 0x01000000U
2417 #define CAN_F3R2_FB25 0x02000000U
2418 #define CAN_F3R2_FB26 0x04000000U
2419 #define CAN_F3R2_FB27 0x08000000U
2420 #define CAN_F3R2_FB28 0x10000000U
2421 #define CAN_F3R2_FB29 0x20000000U
2422 #define CAN_F3R2_FB30 0x40000000U
2423 #define CAN_F3R2_FB31 0x80000000U
2425 /******************* Bit definition for CAN_F4R2 register *******************/
2426 #define CAN_F4R2_FB0 0x00000001U
2427 #define CAN_F4R2_FB1 0x00000002U
2428 #define CAN_F4R2_FB2 0x00000004U
2429 #define CAN_F4R2_FB3 0x00000008U
2430 #define CAN_F4R2_FB4 0x00000010U
2431 #define CAN_F4R2_FB5 0x00000020U
2432 #define CAN_F4R2_FB6 0x00000040U
2433 #define CAN_F4R2_FB7 0x00000080U
2434 #define CAN_F4R2_FB8 0x00000100U
2435 #define CAN_F4R2_FB9 0x00000200U
2436 #define CAN_F4R2_FB10 0x00000400U
2437 #define CAN_F4R2_FB11 0x00000800U
2438 #define CAN_F4R2_FB12 0x00001000U
2439 #define CAN_F4R2_FB13 0x00002000U
2440 #define CAN_F4R2_FB14 0x00004000U
2441 #define CAN_F4R2_FB15 0x00008000U
2442 #define CAN_F4R2_FB16 0x00010000U
2443 #define CAN_F4R2_FB17 0x00020000U
2444 #define CAN_F4R2_FB18 0x00040000U
2445 #define CAN_F4R2_FB19 0x00080000U
2446 #define CAN_F4R2_FB20 0x00100000U
2447 #define CAN_F4R2_FB21 0x00200000U
2448 #define CAN_F4R2_FB22 0x00400000U
2449 #define CAN_F4R2_FB23 0x00800000U
2450 #define CAN_F4R2_FB24 0x01000000U
2451 #define CAN_F4R2_FB25 0x02000000U
2452 #define CAN_F4R2_FB26 0x04000000U
2453 #define CAN_F4R2_FB27 0x08000000U
2454 #define CAN_F4R2_FB28 0x10000000U
2455 #define CAN_F4R2_FB29 0x20000000U
2456 #define CAN_F4R2_FB30 0x40000000U
2457 #define CAN_F4R2_FB31 0x80000000U
2459 /******************* Bit definition for CAN_F5R2 register *******************/
2460 #define CAN_F5R2_FB0 0x00000001U
2461 #define CAN_F5R2_FB1 0x00000002U
2462 #define CAN_F5R2_FB2 0x00000004U
2463 #define CAN_F5R2_FB3 0x00000008U
2464 #define CAN_F5R2_FB4 0x00000010U
2465 #define CAN_F5R2_FB5 0x00000020U
2466 #define CAN_F5R2_FB6 0x00000040U
2467 #define CAN_F5R2_FB7 0x00000080U
2468 #define CAN_F5R2_FB8 0x00000100U
2469 #define CAN_F5R2_FB9 0x00000200U
2470 #define CAN_F5R2_FB10 0x00000400U
2471 #define CAN_F5R2_FB11 0x00000800U
2472 #define CAN_F5R2_FB12 0x00001000U
2473 #define CAN_F5R2_FB13 0x00002000U
2474 #define CAN_F5R2_FB14 0x00004000U
2475 #define CAN_F5R2_FB15 0x00008000U
2476 #define CAN_F5R2_FB16 0x00010000U
2477 #define CAN_F5R2_FB17 0x00020000U
2478 #define CAN_F5R2_FB18 0x00040000U
2479 #define CAN_F5R2_FB19 0x00080000U
2480 #define CAN_F5R2_FB20 0x00100000U
2481 #define CAN_F5R2_FB21 0x00200000U
2482 #define CAN_F5R2_FB22 0x00400000U
2483 #define CAN_F5R2_FB23 0x00800000U
2484 #define CAN_F5R2_FB24 0x01000000U
2485 #define CAN_F5R2_FB25 0x02000000U
2486 #define CAN_F5R2_FB26 0x04000000U
2487 #define CAN_F5R2_FB27 0x08000000U
2488 #define CAN_F5R2_FB28 0x10000000U
2489 #define CAN_F5R2_FB29 0x20000000U
2490 #define CAN_F5R2_FB30 0x40000000U
2491 #define CAN_F5R2_FB31 0x80000000U
2493 /******************* Bit definition for CAN_F6R2 register *******************/
2494 #define CAN_F6R2_FB0 0x00000001U
2495 #define CAN_F6R2_FB1 0x00000002U
2496 #define CAN_F6R2_FB2 0x00000004U
2497 #define CAN_F6R2_FB3 0x00000008U
2498 #define CAN_F6R2_FB4 0x00000010U
2499 #define CAN_F6R2_FB5 0x00000020U
2500 #define CAN_F6R2_FB6 0x00000040U
2501 #define CAN_F6R2_FB7 0x00000080U
2502 #define CAN_F6R2_FB8 0x00000100U
2503 #define CAN_F6R2_FB9 0x00000200U
2504 #define CAN_F6R2_FB10 0x00000400U
2505 #define CAN_F6R2_FB11 0x00000800U
2506 #define CAN_F6R2_FB12 0x00001000U
2507 #define CAN_F6R2_FB13 0x00002000U
2508 #define CAN_F6R2_FB14 0x00004000U
2509 #define CAN_F6R2_FB15 0x00008000U
2510 #define CAN_F6R2_FB16 0x00010000U
2511 #define CAN_F6R2_FB17 0x00020000U
2512 #define CAN_F6R2_FB18 0x00040000U
2513 #define CAN_F6R2_FB19 0x00080000U
2514 #define CAN_F6R2_FB20 0x00100000U
2515 #define CAN_F6R2_FB21 0x00200000U
2516 #define CAN_F6R2_FB22 0x00400000U
2517 #define CAN_F6R2_FB23 0x00800000U
2518 #define CAN_F6R2_FB24 0x01000000U
2519 #define CAN_F6R2_FB25 0x02000000U
2520 #define CAN_F6R2_FB26 0x04000000U
2521 #define CAN_F6R2_FB27 0x08000000U
2522 #define CAN_F6R2_FB28 0x10000000U
2523 #define CAN_F6R2_FB29 0x20000000U
2524 #define CAN_F6R2_FB30 0x40000000U
2525 #define CAN_F6R2_FB31 0x80000000U
2527 /******************* Bit definition for CAN_F7R2 register *******************/
2528 #define CAN_F7R2_FB0 0x00000001U
2529 #define CAN_F7R2_FB1 0x00000002U
2530 #define CAN_F7R2_FB2 0x00000004U
2531 #define CAN_F7R2_FB3 0x00000008U
2532 #define CAN_F7R2_FB4 0x00000010U
2533 #define CAN_F7R2_FB5 0x00000020U
2534 #define CAN_F7R2_FB6 0x00000040U
2535 #define CAN_F7R2_FB7 0x00000080U
2536 #define CAN_F7R2_FB8 0x00000100U
2537 #define CAN_F7R2_FB9 0x00000200U
2538 #define CAN_F7R2_FB10 0x00000400U
2539 #define CAN_F7R2_FB11 0x00000800U
2540 #define CAN_F7R2_FB12 0x00001000U
2541 #define CAN_F7R2_FB13 0x00002000U
2542 #define CAN_F7R2_FB14 0x00004000U
2543 #define CAN_F7R2_FB15 0x00008000U
2544 #define CAN_F7R2_FB16 0x00010000U
2545 #define CAN_F7R2_FB17 0x00020000U
2546 #define CAN_F7R2_FB18 0x00040000U
2547 #define CAN_F7R2_FB19 0x00080000U
2548 #define CAN_F7R2_FB20 0x00100000U
2549 #define CAN_F7R2_FB21 0x00200000U
2550 #define CAN_F7R2_FB22 0x00400000U
2551 #define CAN_F7R2_FB23 0x00800000U
2552 #define CAN_F7R2_FB24 0x01000000U
2553 #define CAN_F7R2_FB25 0x02000000U
2554 #define CAN_F7R2_FB26 0x04000000U
2555 #define CAN_F7R2_FB27 0x08000000U
2556 #define CAN_F7R2_FB28 0x10000000U
2557 #define CAN_F7R2_FB29 0x20000000U
2558 #define CAN_F7R2_FB30 0x40000000U
2559 #define CAN_F7R2_FB31 0x80000000U
2561 /******************* Bit definition for CAN_F8R2 register *******************/
2562 #define CAN_F8R2_FB0 0x00000001U
2563 #define CAN_F8R2_FB1 0x00000002U
2564 #define CAN_F8R2_FB2 0x00000004U
2565 #define CAN_F8R2_FB3 0x00000008U
2566 #define CAN_F8R2_FB4 0x00000010U
2567 #define CAN_F8R2_FB5 0x00000020U
2568 #define CAN_F8R2_FB6 0x00000040U
2569 #define CAN_F8R2_FB7 0x00000080U
2570 #define CAN_F8R2_FB8 0x00000100U
2571 #define CAN_F8R2_FB9 0x00000200U
2572 #define CAN_F8R2_FB10 0x00000400U
2573 #define CAN_F8R2_FB11 0x00000800U
2574 #define CAN_F8R2_FB12 0x00001000U
2575 #define CAN_F8R2_FB13 0x00002000U
2576 #define CAN_F8R2_FB14 0x00004000U
2577 #define CAN_F8R2_FB15 0x00008000U
2578 #define CAN_F8R2_FB16 0x00010000U
2579 #define CAN_F8R2_FB17 0x00020000U
2580 #define CAN_F8R2_FB18 0x00040000U
2581 #define CAN_F8R2_FB19 0x00080000U
2582 #define CAN_F8R2_FB20 0x00100000U
2583 #define CAN_F8R2_FB21 0x00200000U
2584 #define CAN_F8R2_FB22 0x00400000U
2585 #define CAN_F8R2_FB23 0x00800000U
2586 #define CAN_F8R2_FB24 0x01000000U
2587 #define CAN_F8R2_FB25 0x02000000U
2588 #define CAN_F8R2_FB26 0x04000000U
2589 #define CAN_F8R2_FB27 0x08000000U
2590 #define CAN_F8R2_FB28 0x10000000U
2591 #define CAN_F8R2_FB29 0x20000000U
2592 #define CAN_F8R2_FB30 0x40000000U
2593 #define CAN_F8R2_FB31 0x80000000U
2595 /******************* Bit definition for CAN_F9R2 register *******************/
2596 #define CAN_F9R2_FB0 0x00000001U
2597 #define CAN_F9R2_FB1 0x00000002U
2598 #define CAN_F9R2_FB2 0x00000004U
2599 #define CAN_F9R2_FB3 0x00000008U
2600 #define CAN_F9R2_FB4 0x00000010U
2601 #define CAN_F9R2_FB5 0x00000020U
2602 #define CAN_F9R2_FB6 0x00000040U
2603 #define CAN_F9R2_FB7 0x00000080U
2604 #define CAN_F9R2_FB8 0x00000100U
2605 #define CAN_F9R2_FB9 0x00000200U
2606 #define CAN_F9R2_FB10 0x00000400U
2607 #define CAN_F9R2_FB11 0x00000800U
2608 #define CAN_F9R2_FB12 0x00001000U
2609 #define CAN_F9R2_FB13 0x00002000U
2610 #define CAN_F9R2_FB14 0x00004000U
2611 #define CAN_F9R2_FB15 0x00008000U
2612 #define CAN_F9R2_FB16 0x00010000U
2613 #define CAN_F9R2_FB17 0x00020000U
2614 #define CAN_F9R2_FB18 0x00040000U
2615 #define CAN_F9R2_FB19 0x00080000U
2616 #define CAN_F9R2_FB20 0x00100000U
2617 #define CAN_F9R2_FB21 0x00200000U
2618 #define CAN_F9R2_FB22 0x00400000U
2619 #define CAN_F9R2_FB23 0x00800000U
2620 #define CAN_F9R2_FB24 0x01000000U
2621 #define CAN_F9R2_FB25 0x02000000U
2622 #define CAN_F9R2_FB26 0x04000000U
2623 #define CAN_F9R2_FB27 0x08000000U
2624 #define CAN_F9R2_FB28 0x10000000U
2625 #define CAN_F9R2_FB29 0x20000000U
2626 #define CAN_F9R2_FB30 0x40000000U
2627 #define CAN_F9R2_FB31 0x80000000U
2629 /******************* Bit definition for CAN_F10R2 register ******************/
2630 #define CAN_F10R2_FB0 0x00000001U
2631 #define CAN_F10R2_FB1 0x00000002U
2632 #define CAN_F10R2_FB2 0x00000004U
2633 #define CAN_F10R2_FB3 0x00000008U
2634 #define CAN_F10R2_FB4 0x00000010U
2635 #define CAN_F10R2_FB5 0x00000020U
2636 #define CAN_F10R2_FB6 0x00000040U
2637 #define CAN_F10R2_FB7 0x00000080U
2638 #define CAN_F10R2_FB8 0x00000100U
2639 #define CAN_F10R2_FB9 0x00000200U
2640 #define CAN_F10R2_FB10 0x00000400U
2641 #define CAN_F10R2_FB11 0x00000800U
2642 #define CAN_F10R2_FB12 0x00001000U
2643 #define CAN_F10R2_FB13 0x00002000U
2644 #define CAN_F10R2_FB14 0x00004000U
2645 #define CAN_F10R2_FB15 0x00008000U
2646 #define CAN_F10R2_FB16 0x00010000U
2647 #define CAN_F10R2_FB17 0x00020000U
2648 #define CAN_F10R2_FB18 0x00040000U
2649 #define CAN_F10R2_FB19 0x00080000U
2650 #define CAN_F10R2_FB20 0x00100000U
2651 #define CAN_F10R2_FB21 0x00200000U
2652 #define CAN_F10R2_FB22 0x00400000U
2653 #define CAN_F10R2_FB23 0x00800000U
2654 #define CAN_F10R2_FB24 0x01000000U
2655 #define CAN_F10R2_FB25 0x02000000U
2656 #define CAN_F10R2_FB26 0x04000000U
2657 #define CAN_F10R2_FB27 0x08000000U
2658 #define CAN_F10R2_FB28 0x10000000U
2659 #define CAN_F10R2_FB29 0x20000000U
2660 #define CAN_F10R2_FB30 0x40000000U
2661 #define CAN_F10R2_FB31 0x80000000U
2663 /******************* Bit definition for CAN_F11R2 register ******************/
2664 #define CAN_F11R2_FB0 0x00000001U
2665 #define CAN_F11R2_FB1 0x00000002U
2666 #define CAN_F11R2_FB2 0x00000004U
2667 #define CAN_F11R2_FB3 0x00000008U
2668 #define CAN_F11R2_FB4 0x00000010U
2669 #define CAN_F11R2_FB5 0x00000020U
2670 #define CAN_F11R2_FB6 0x00000040U
2671 #define CAN_F11R2_FB7 0x00000080U
2672 #define CAN_F11R2_FB8 0x00000100U
2673 #define CAN_F11R2_FB9 0x00000200U
2674 #define CAN_F11R2_FB10 0x00000400U
2675 #define CAN_F11R2_FB11 0x00000800U
2676 #define CAN_F11R2_FB12 0x00001000U
2677 #define CAN_F11R2_FB13 0x00002000U
2678 #define CAN_F11R2_FB14 0x00004000U
2679 #define CAN_F11R2_FB15 0x00008000U
2680 #define CAN_F11R2_FB16 0x00010000U
2681 #define CAN_F11R2_FB17 0x00020000U
2682 #define CAN_F11R2_FB18 0x00040000U
2683 #define CAN_F11R2_FB19 0x00080000U
2684 #define CAN_F11R2_FB20 0x00100000U
2685 #define CAN_F11R2_FB21 0x00200000U
2686 #define CAN_F11R2_FB22 0x00400000U
2687 #define CAN_F11R2_FB23 0x00800000U
2688 #define CAN_F11R2_FB24 0x01000000U
2689 #define CAN_F11R2_FB25 0x02000000U
2690 #define CAN_F11R2_FB26 0x04000000U
2691 #define CAN_F11R2_FB27 0x08000000U
2692 #define CAN_F11R2_FB28 0x10000000U
2693 #define CAN_F11R2_FB29 0x20000000U
2694 #define CAN_F11R2_FB30 0x40000000U
2695 #define CAN_F11R2_FB31 0x80000000U
2697 /******************* Bit definition for CAN_F12R2 register ******************/
2698 #define CAN_F12R2_FB0 0x00000001U
2699 #define CAN_F12R2_FB1 0x00000002U
2700 #define CAN_F12R2_FB2 0x00000004U
2701 #define CAN_F12R2_FB3 0x00000008U
2702 #define CAN_F12R2_FB4 0x00000010U
2703 #define CAN_F12R2_FB5 0x00000020U
2704 #define CAN_F12R2_FB6 0x00000040U
2705 #define CAN_F12R2_FB7 0x00000080U
2706 #define CAN_F12R2_FB8 0x00000100U
2707 #define CAN_F12R2_FB9 0x00000200U
2708 #define CAN_F12R2_FB10 0x00000400U
2709 #define CAN_F12R2_FB11 0x00000800U
2710 #define CAN_F12R2_FB12 0x00001000U
2711 #define CAN_F12R2_FB13 0x00002000U
2712 #define CAN_F12R2_FB14 0x00004000U
2713 #define CAN_F12R2_FB15 0x00008000U
2714 #define CAN_F12R2_FB16 0x00010000U
2715 #define CAN_F12R2_FB17 0x00020000U
2716 #define CAN_F12R2_FB18 0x00040000U
2717 #define CAN_F12R2_FB19 0x00080000U
2718 #define CAN_F12R2_FB20 0x00100000U
2719 #define CAN_F12R2_FB21 0x00200000U
2720 #define CAN_F12R2_FB22 0x00400000U
2721 #define CAN_F12R2_FB23 0x00800000U
2722 #define CAN_F12R2_FB24 0x01000000U
2723 #define CAN_F12R2_FB25 0x02000000U
2724 #define CAN_F12R2_FB26 0x04000000U
2725 #define CAN_F12R2_FB27 0x08000000U
2726 #define CAN_F12R2_FB28 0x10000000U
2727 #define CAN_F12R2_FB29 0x20000000U
2728 #define CAN_F12R2_FB30 0x40000000U
2729 #define CAN_F12R2_FB31 0x80000000U
2731 /******************* Bit definition for CAN_F13R2 register ******************/
2732 #define CAN_F13R2_FB0 0x00000001U
2733 #define CAN_F13R2_FB1 0x00000002U
2734 #define CAN_F13R2_FB2 0x00000004U
2735 #define CAN_F13R2_FB3 0x00000008U
2736 #define CAN_F13R2_FB4 0x00000010U
2737 #define CAN_F13R2_FB5 0x00000020U
2738 #define CAN_F13R2_FB6 0x00000040U
2739 #define CAN_F13R2_FB7 0x00000080U
2740 #define CAN_F13R2_FB8 0x00000100U
2741 #define CAN_F13R2_FB9 0x00000200U
2742 #define CAN_F13R2_FB10 0x00000400U
2743 #define CAN_F13R2_FB11 0x00000800U
2744 #define CAN_F13R2_FB12 0x00001000U
2745 #define CAN_F13R2_FB13 0x00002000U
2746 #define CAN_F13R2_FB14 0x00004000U
2747 #define CAN_F13R2_FB15 0x00008000U
2748 #define CAN_F13R2_FB16 0x00010000U
2749 #define CAN_F13R2_FB17 0x00020000U
2750 #define CAN_F13R2_FB18 0x00040000U
2751 #define CAN_F13R2_FB19 0x00080000U
2752 #define CAN_F13R2_FB20 0x00100000U
2753 #define CAN_F13R2_FB21 0x00200000U
2754 #define CAN_F13R2_FB22 0x00400000U
2755 #define CAN_F13R2_FB23 0x00800000U
2756 #define CAN_F13R2_FB24 0x01000000U
2757 #define CAN_F13R2_FB25 0x02000000U
2758 #define CAN_F13R2_FB26 0x04000000U
2759 #define CAN_F13R2_FB27 0x08000000U
2760 #define CAN_F13R2_FB28 0x10000000U
2761 #define CAN_F13R2_FB29 0x20000000U
2762 #define CAN_F13R2_FB30 0x40000000U
2763 #define CAN_F13R2_FB31 0x80000000U
2765 /******************************************************************************/
2766 /* */
2767 /* CRC calculation unit */
2768 /* */
2769 /******************************************************************************/
2770 /******************* Bit definition for CRC_DR register *********************/
2771 #define CRC_DR_DR 0xFFFFFFFFU
2774 /******************* Bit definition for CRC_IDR register ********************/
2775 #define CRC_IDR_IDR 0xFFU
2778 /******************** Bit definition for CRC_CR register ********************/
2779 #define CRC_CR_RESET 0x01U
2781 /******************************************************************************/
2782 /* */
2783 /* Debug MCU */
2784 /* */
2785 /******************************************************************************/
2786 
2787 /******************************************************************************/
2788 /* */
2789 /* Digital Filter for Sigma Delta Modulators */
2790 /* */
2791 /******************************************************************************/
2792 
2793 /**************** DFSDM channel configuration registers ********************/
2794 
2795 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
2796 #define DFSDM_CHCFGR1_DFSDMEN 0x80000000U
2797 #define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U
2798 #define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U
2799 #define DFSDM_CHCFGR1_DATPACK 0x0000C000U
2800 #define DFSDM_CHCFGR1_DATPACK_1 0x00008000U
2801 #define DFSDM_CHCFGR1_DATPACK_0 0x00004000U
2802 #define DFSDM_CHCFGR1_DATMPX 0x00003000U
2803 #define DFSDM_CHCFGR1_DATMPX_1 0x00002000U
2804 #define DFSDM_CHCFGR1_DATMPX_0 0x00001000U
2805 #define DFSDM_CHCFGR1_CHINSEL 0x00000100U
2806 #define DFSDM_CHCFGR1_CHEN 0x00000080U
2807 #define DFSDM_CHCFGR1_CKABEN 0x00000040U
2808 #define DFSDM_CHCFGR1_SCDEN 0x00000020U
2809 #define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU
2810 #define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U
2811 #define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U
2812 #define DFSDM_CHCFGR1_SITP 0x00000003U
2813 #define DFSDM_CHCFGR1_SITP_1 0x00000002U
2814 #define DFSDM_CHCFGR1_SITP_0 0x00000001U
2816 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
2817 #define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U
2818 #define DFSDM_CHCFGR2_DTRBS 0x000000F8U
2820 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
2821 #define DFSDM_CHAWSCDR_AWFORD 0x00C00000U
2822 #define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U
2823 #define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U
2824 #define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U
2825 #define DFSDM_CHAWSCDR_BKSCD 0x0000F000U
2826 #define DFSDM_CHAWSCDR_SCDT 0x000000FFU
2828 /**************** Bit definition for DFSDM_CHWDATR register *******************/
2829 #define DFSDM_CHWDATR_WDATA 0x0000FFFFU
2831 /**************** Bit definition for DFSDM_CHDATINR register *****************/
2832 #define DFSDM_CHDATINR_INDAT0 0x0000FFFFU
2833 #define DFSDM_CHDATINR_INDAT1 0xFFFF0000U
2835 /************************ DFSDM module registers ****************************/
2836 
2837 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
2838 #define DFSDM_FLTCR1_AWFSEL 0x40000000U
2839 #define DFSDM_FLTCR1_FAST 0x20000000U
2840 #define DFSDM_FLTCR1_RCH 0x07000000U
2841 #define DFSDM_FLTCR1_RDMAEN 0x00200000U
2842 #define DFSDM_FLTCR1_RSYNC 0x00080000U
2843 #define DFSDM_FLTCR1_RCONT 0x00040000U
2844 #define DFSDM_FLTCR1_RSWSTART 0x00020000U
2845 #define DFSDM_FLTCR1_JEXTEN 0x00006000U
2846 #define DFSDM_FLTCR1_JEXTEN_1 0x00004000U
2847 #define DFSDM_FLTCR1_JEXTEN_0 0x00002000U
2848 #define DFSDM_FLTCR1_JEXTSEL 0x00000700U
2849 #define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U
2850 #define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U
2851 #define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U
2852 #define DFSDM_FLTCR1_JDMAEN 0x00000020U
2853 #define DFSDM_FLTCR1_JSCAN 0x00000010U
2854 #define DFSDM_FLTCR1_JSYNC 0x00000008U
2855 #define DFSDM_FLTCR1_JSWSTART 0x00000002U
2856 #define DFSDM_FLTCR1_DFEN 0x00000001U
2858 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
2859 #define DFSDM_FLTCR2_AWDCH 0x000F0000U
2860 #define DFSDM_FLTCR2_EXCH 0x00000F00U
2861 #define DFSDM_FLTCR2_CKABIE 0x00000040U
2862 #define DFSDM_FLTCR2_SCDIE 0x00000020U
2863 #define DFSDM_FLTCR2_AWDIE 0x00000010U
2864 #define DFSDM_FLTCR2_ROVRIE 0x00000008U
2865 #define DFSDM_FLTCR2_JOVRIE 0x00000004U
2866 #define DFSDM_FLTCR2_REOCIE 0x00000002U
2867 #define DFSDM_FLTCR2_JEOCIE 0x00000001U
2869 /***************** Bit definition for DFSDM_FLTISR register *******************/
2870 #define DFSDM_FLTISR_SCDF 0x0F000000U
2871 #define DFSDM_FLTISR_CKABF 0x000F0000U
2872 #define DFSDM_FLTISR_RCIP 0x00004000U
2873 #define DFSDM_FLTISR_JCIP 0x00002000U
2874 #define DFSDM_FLTISR_AWDF 0x00000010U
2875 #define DFSDM_FLTISR_ROVRF 0x00000008U
2876 #define DFSDM_FLTISR_JOVRF 0x00000004U
2877 #define DFSDM_FLTISR_REOCF 0x00000002U
2878 #define DFSDM_FLTISR_JEOCF 0x00000001U
2880 /***************** Bit definition for DFSDM_FLTICR register *******************/
2881 #define DFSDM_FLTICR_CLRSCSDF 0x0F000000U
2882 #define DFSDM_FLTICR_CLRCKABF 0x000F0000U
2883 #define DFSDM_FLTICR_CLRROVRF 0x00000008U
2884 #define DFSDM_FLTICR_CLRJOVRF 0x00000004U
2886 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
2887 #define DFSDM_FLTJCHGR_JCHG 0x0000000FU
2889 /***************** Bit definition for DFSDM_FLTFCR register *******************/
2890 #define DFSDM_FLTFCR_FORD 0xE0000000U
2891 #define DFSDM_FLTFCR_FORD_2 0x80000000U
2892 #define DFSDM_FLTFCR_FORD_1 0x40000000U
2893 #define DFSDM_FLTFCR_FORD_0 0x20000000U
2894 #define DFSDM_FLTFCR_FOSR 0x03FF0000U
2895 #define DFSDM_FLTFCR_IOSR 0x000000FFU
2897 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
2898 #define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U
2899 #define DFSDM_FLTJDATAR_JDATACH 0x00000007U
2901 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
2902 #define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U
2903 #define DFSDM_FLTRDATAR_RPEND 0x00000010U
2904 #define DFSDM_FLTRDATAR_RDATACH 0x00000007U
2906 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
2907 #define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U
2908 #define DFSDM_FLTAWHTR_BKAWH 0x0000000FU
2910 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
2911 #define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U
2912 #define DFSDM_FLTAWLTR_BKAWL 0x0000000FU
2914 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
2915 #define DFSDM_FLTAWSR_AWHTF 0x00000F00U
2916 #define DFSDM_FLTAWSR_AWLTF 0x0000000FU
2918 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
2919 #define DFSDM_FLTAWCFR_CLRAWHTF 0x00000F00U
2920 #define DFSDM_FLTAWCFR_CLRAWLTF 0x0000000FU
2922 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
2923 #define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U
2924 #define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U
2926 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
2927 #define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U
2928 #define DFSDM_FLTEXMIN_EXMINCH 0x00000007U
2930 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
2931 #define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U
2933 /******************************************************************************/
2934 /* */
2935 /* DMA Controller */
2936 /* */
2937 /******************************************************************************/
2938 /******************** Bits definition for DMA_SxCR register *****************/
2939 #define DMA_SxCR_CHSEL 0x0E000000U
2940 #define DMA_SxCR_CHSEL_0 0x02000000U
2941 #define DMA_SxCR_CHSEL_1 0x04000000U
2942 #define DMA_SxCR_CHSEL_2 0x08000000U
2943 #define DMA_SxCR_MBURST 0x01800000U
2944 #define DMA_SxCR_MBURST_0 0x00800000U
2945 #define DMA_SxCR_MBURST_1 0x01000000U
2946 #define DMA_SxCR_PBURST 0x00600000U
2947 #define DMA_SxCR_PBURST_0 0x00200000U
2948 #define DMA_SxCR_PBURST_1 0x00400000U
2949 #define DMA_SxCR_CT 0x00080000U
2950 #define DMA_SxCR_DBM 0x00040000U
2951 #define DMA_SxCR_PL 0x00030000U
2952 #define DMA_SxCR_PL_0 0x00010000U
2953 #define DMA_SxCR_PL_1 0x00020000U
2954 #define DMA_SxCR_PINCOS 0x00008000U
2955 #define DMA_SxCR_MSIZE 0x00006000U
2956 #define DMA_SxCR_MSIZE_0 0x00002000U
2957 #define DMA_SxCR_MSIZE_1 0x00004000U
2958 #define DMA_SxCR_PSIZE 0x00001800U
2959 #define DMA_SxCR_PSIZE_0 0x00000800U
2960 #define DMA_SxCR_PSIZE_1 0x00001000U
2961 #define DMA_SxCR_MINC 0x00000400U
2962 #define DMA_SxCR_PINC 0x00000200U
2963 #define DMA_SxCR_CIRC 0x00000100U
2964 #define DMA_SxCR_DIR 0x000000C0U
2965 #define DMA_SxCR_DIR_0 0x00000040U
2966 #define DMA_SxCR_DIR_1 0x00000080U
2967 #define DMA_SxCR_PFCTRL 0x00000020U
2968 #define DMA_SxCR_TCIE 0x00000010U
2969 #define DMA_SxCR_HTIE 0x00000008U
2970 #define DMA_SxCR_TEIE 0x00000004U
2971 #define DMA_SxCR_DMEIE 0x00000002U
2972 #define DMA_SxCR_EN 0x00000001U
2973 
2974 /* Legacy defines */
2975 #define DMA_SxCR_ACK 0x00100000U
2976 
2977 /******************** Bits definition for DMA_SxCNDTR register **************/
2978 #define DMA_SxNDT 0x0000FFFFU
2979 #define DMA_SxNDT_0 0x00000001U
2980 #define DMA_SxNDT_1 0x00000002U
2981 #define DMA_SxNDT_2 0x00000004U
2982 #define DMA_SxNDT_3 0x00000008U
2983 #define DMA_SxNDT_4 0x00000010U
2984 #define DMA_SxNDT_5 0x00000020U
2985 #define DMA_SxNDT_6 0x00000040U
2986 #define DMA_SxNDT_7 0x00000080U
2987 #define DMA_SxNDT_8 0x00000100U
2988 #define DMA_SxNDT_9 0x00000200U
2989 #define DMA_SxNDT_10 0x00000400U
2990 #define DMA_SxNDT_11 0x00000800U
2991 #define DMA_SxNDT_12 0x00001000U
2992 #define DMA_SxNDT_13 0x00002000U
2993 #define DMA_SxNDT_14 0x00004000U
2994 #define DMA_SxNDT_15 0x00008000U
2995 
2996 /******************** Bits definition for DMA_SxFCR register ****************/
2997 #define DMA_SxFCR_FEIE 0x00000080U
2998 #define DMA_SxFCR_FS 0x00000038U
2999 #define DMA_SxFCR_FS_0 0x00000008U
3000 #define DMA_SxFCR_FS_1 0x00000010U
3001 #define DMA_SxFCR_FS_2 0x00000020U
3002 #define DMA_SxFCR_DMDIS 0x00000004U
3003 #define DMA_SxFCR_FTH 0x00000003U
3004 #define DMA_SxFCR_FTH_0 0x00000001U
3005 #define DMA_SxFCR_FTH_1 0x00000002U
3006 
3007 /******************** Bits definition for DMA_LISR register *****************/
3008 #define DMA_LISR_TCIF3 0x08000000U
3009 #define DMA_LISR_HTIF3 0x04000000U
3010 #define DMA_LISR_TEIF3 0x02000000U
3011 #define DMA_LISR_DMEIF3 0x01000000U
3012 #define DMA_LISR_FEIF3 0x00400000U
3013 #define DMA_LISR_TCIF2 0x00200000U
3014 #define DMA_LISR_HTIF2 0x00100000U
3015 #define DMA_LISR_TEIF2 0x00080000U
3016 #define DMA_LISR_DMEIF2 0x00040000U
3017 #define DMA_LISR_FEIF2 0x00010000U
3018 #define DMA_LISR_TCIF1 0x00000800U
3019 #define DMA_LISR_HTIF1 0x00000400U
3020 #define DMA_LISR_TEIF1 0x00000200U
3021 #define DMA_LISR_DMEIF1 0x00000100U
3022 #define DMA_LISR_FEIF1 0x00000040U
3023 #define DMA_LISR_TCIF0 0x00000020U
3024 #define DMA_LISR_HTIF0 0x00000010U
3025 #define DMA_LISR_TEIF0 0x00000008U
3026 #define DMA_LISR_DMEIF0 0x00000004U
3027 #define DMA_LISR_FEIF0 0x00000001U
3028 
3029 /******************** Bits definition for DMA_HISR register *****************/
3030 #define DMA_HISR_TCIF7 0x08000000U
3031 #define DMA_HISR_HTIF7 0x04000000U
3032 #define DMA_HISR_TEIF7 0x02000000U
3033 #define DMA_HISR_DMEIF7 0x01000000U
3034 #define DMA_HISR_FEIF7 0x00400000U
3035 #define DMA_HISR_TCIF6 0x00200000U
3036 #define DMA_HISR_HTIF6 0x00100000U
3037 #define DMA_HISR_TEIF6 0x00080000U
3038 #define DMA_HISR_DMEIF6 0x00040000U
3039 #define DMA_HISR_FEIF6 0x00010000U
3040 #define DMA_HISR_TCIF5 0x00000800U
3041 #define DMA_HISR_HTIF5 0x00000400U
3042 #define DMA_HISR_TEIF5 0x00000200U
3043 #define DMA_HISR_DMEIF5 0x00000100U
3044 #define DMA_HISR_FEIF5 0x00000040U
3045 #define DMA_HISR_TCIF4 0x00000020U
3046 #define DMA_HISR_HTIF4 0x00000010U
3047 #define DMA_HISR_TEIF4 0x00000008U
3048 #define DMA_HISR_DMEIF4 0x00000004U
3049 #define DMA_HISR_FEIF4 0x00000001U
3050 
3051 /******************** Bits definition for DMA_LIFCR register ****************/
3052 #define DMA_LIFCR_CTCIF3 0x08000000U
3053 #define DMA_LIFCR_CHTIF3 0x04000000U
3054 #define DMA_LIFCR_CTEIF3 0x02000000U
3055 #define DMA_LIFCR_CDMEIF3 0x01000000U
3056 #define DMA_LIFCR_CFEIF3 0x00400000U
3057 #define DMA_LIFCR_CTCIF2 0x00200000U
3058 #define DMA_LIFCR_CHTIF2 0x00100000U
3059 #define DMA_LIFCR_CTEIF2 0x00080000U
3060 #define DMA_LIFCR_CDMEIF2 0x00040000U
3061 #define DMA_LIFCR_CFEIF2 0x00010000U
3062 #define DMA_LIFCR_CTCIF1 0x00000800U
3063 #define DMA_LIFCR_CHTIF1 0x00000400U
3064 #define DMA_LIFCR_CTEIF1 0x00000200U
3065 #define DMA_LIFCR_CDMEIF1 0x00000100U
3066 #define DMA_LIFCR_CFEIF1 0x00000040U
3067 #define DMA_LIFCR_CTCIF0 0x00000020U
3068 #define DMA_LIFCR_CHTIF0 0x00000010U
3069 #define DMA_LIFCR_CTEIF0 0x00000008U
3070 #define DMA_LIFCR_CDMEIF0 0x00000004U
3071 #define DMA_LIFCR_CFEIF0 0x00000001U
3072 
3073 /******************** Bits definition for DMA_HIFCR register ****************/
3074 #define DMA_HIFCR_CTCIF7 0x08000000U
3075 #define DMA_HIFCR_CHTIF7 0x04000000U
3076 #define DMA_HIFCR_CTEIF7 0x02000000U
3077 #define DMA_HIFCR_CDMEIF7 0x01000000U
3078 #define DMA_HIFCR_CFEIF7 0x00400000U
3079 #define DMA_HIFCR_CTCIF6 0x00200000U
3080 #define DMA_HIFCR_CHTIF6 0x00100000U
3081 #define DMA_HIFCR_CTEIF6 0x00080000U
3082 #define DMA_HIFCR_CDMEIF6 0x00040000U
3083 #define DMA_HIFCR_CFEIF6 0x00010000U
3084 #define DMA_HIFCR_CTCIF5 0x00000800U
3085 #define DMA_HIFCR_CHTIF5 0x00000400U
3086 #define DMA_HIFCR_CTEIF5 0x00000200U
3087 #define DMA_HIFCR_CDMEIF5 0x00000100U
3088 #define DMA_HIFCR_CFEIF5 0x00000040U
3089 #define DMA_HIFCR_CTCIF4 0x00000020U
3090 #define DMA_HIFCR_CHTIF4 0x00000010U
3091 #define DMA_HIFCR_CTEIF4 0x00000008U
3092 #define DMA_HIFCR_CDMEIF4 0x00000004U
3093 #define DMA_HIFCR_CFEIF4 0x00000001U
3094 
3095 
3096 /******************************************************************************/
3097 /* */
3098 /* External Interrupt/Event Controller */
3099 /* */
3100 /******************************************************************************/
3101 /******************* Bit definition for EXTI_IMR register *******************/
3102 #define EXTI_IMR_MR0 0x00000001U
3103 #define EXTI_IMR_MR1 0x00000002U
3104 #define EXTI_IMR_MR2 0x00000004U
3105 #define EXTI_IMR_MR3 0x00000008U
3106 #define EXTI_IMR_MR4 0x00000010U
3107 #define EXTI_IMR_MR5 0x00000020U
3108 #define EXTI_IMR_MR6 0x00000040U
3109 #define EXTI_IMR_MR7 0x00000080U
3110 #define EXTI_IMR_MR8 0x00000100U
3111 #define EXTI_IMR_MR9 0x00000200U
3112 #define EXTI_IMR_MR10 0x00000400U
3113 #define EXTI_IMR_MR11 0x00000800U
3114 #define EXTI_IMR_MR12 0x00001000U
3115 #define EXTI_IMR_MR13 0x00002000U
3116 #define EXTI_IMR_MR14 0x00004000U
3117 #define EXTI_IMR_MR15 0x00008000U
3118 #define EXTI_IMR_MR16 0x00010000U
3119 #define EXTI_IMR_MR17 0x00020000U
3120 #define EXTI_IMR_MR18 0x00040000U
3121 #define EXTI_IMR_MR19 0x00080000U
3122 #define EXTI_IMR_MR20 0x00100000U
3123 #define EXTI_IMR_MR21 0x00200000U
3124 #define EXTI_IMR_MR22 0x00400000U
3126 /******************* Bit definition for EXTI_EMR register *******************/
3127 #define EXTI_EMR_MR0 0x00000001U
3128 #define EXTI_EMR_MR1 0x00000002U
3129 #define EXTI_EMR_MR2 0x00000004U
3130 #define EXTI_EMR_MR3 0x00000008U
3131 #define EXTI_EMR_MR4 0x00000010U
3132 #define EXTI_EMR_MR5 0x00000020U
3133 #define EXTI_EMR_MR6 0x00000040U
3134 #define EXTI_EMR_MR7 0x00000080U
3135 #define EXTI_EMR_MR8 0x00000100U
3136 #define EXTI_EMR_MR9 0x00000200U
3137 #define EXTI_EMR_MR10 0x00000400U
3138 #define EXTI_EMR_MR11 0x00000800U
3139 #define EXTI_EMR_MR12 0x00001000U
3140 #define EXTI_EMR_MR13 0x00002000U
3141 #define EXTI_EMR_MR14 0x00004000U
3142 #define EXTI_EMR_MR15 0x00008000U
3143 #define EXTI_EMR_MR16 0x00010000U
3144 #define EXTI_EMR_MR17 0x00020000U
3145 #define EXTI_EMR_MR18 0x00040000U
3146 #define EXTI_EMR_MR19 0x00080000U
3147 #define EXTI_EMR_MR20 0x00100000U
3148 #define EXTI_EMR_MR21 0x00200000U
3149 #define EXTI_EMR_MR22 0x00400000U
3151 /****************** Bit definition for EXTI_RTSR register *******************/
3152 #define EXTI_RTSR_TR0 0x00000001U
3153 #define EXTI_RTSR_TR1 0x00000002U
3154 #define EXTI_RTSR_TR2 0x00000004U
3155 #define EXTI_RTSR_TR3 0x00000008U
3156 #define EXTI_RTSR_TR4 0x00000010U
3157 #define EXTI_RTSR_TR5 0x00000020U
3158 #define EXTI_RTSR_TR6 0x00000040U
3159 #define EXTI_RTSR_TR7 0x00000080U
3160 #define EXTI_RTSR_TR8 0x00000100U
3161 #define EXTI_RTSR_TR9 0x00000200U
3162 #define EXTI_RTSR_TR10 0x00000400U
3163 #define EXTI_RTSR_TR11 0x00000800U
3164 #define EXTI_RTSR_TR12 0x00001000U
3165 #define EXTI_RTSR_TR13 0x00002000U
3166 #define EXTI_RTSR_TR14 0x00004000U
3167 #define EXTI_RTSR_TR15 0x00008000U
3168 #define EXTI_RTSR_TR16 0x00010000U
3169 #define EXTI_RTSR_TR17 0x00020000U
3170 #define EXTI_RTSR_TR18 0x00040000U
3171 #define EXTI_RTSR_TR19 0x00080000U
3172 #define EXTI_RTSR_TR20 0x00100000U
3173 #define EXTI_RTSR_TR21 0x00200000U
3174 #define EXTI_RTSR_TR22 0x00400000U
3176 /****************** Bit definition for EXTI_FTSR register *******************/
3177 #define EXTI_FTSR_TR0 0x00000001U
3178 #define EXTI_FTSR_TR1 0x00000002U
3179 #define EXTI_FTSR_TR2 0x00000004U
3180 #define EXTI_FTSR_TR3 0x00000008U
3181 #define EXTI_FTSR_TR4 0x00000010U
3182 #define EXTI_FTSR_TR5 0x00000020U
3183 #define EXTI_FTSR_TR6 0x00000040U
3184 #define EXTI_FTSR_TR7 0x00000080U
3185 #define EXTI_FTSR_TR8 0x00000100U
3186 #define EXTI_FTSR_TR9 0x00000200U
3187 #define EXTI_FTSR_TR10 0x00000400U
3188 #define EXTI_FTSR_TR11 0x00000800U
3189 #define EXTI_FTSR_TR12 0x00001000U
3190 #define EXTI_FTSR_TR13 0x00002000U
3191 #define EXTI_FTSR_TR14 0x00004000U
3192 #define EXTI_FTSR_TR15 0x00008000U
3193 #define EXTI_FTSR_TR16 0x00010000U
3194 #define EXTI_FTSR_TR17 0x00020000U
3195 #define EXTI_FTSR_TR18 0x00040000U
3196 #define EXTI_FTSR_TR19 0x00080000U
3197 #define EXTI_FTSR_TR20 0x00100000U
3198 #define EXTI_FTSR_TR21 0x00200000U
3199 #define EXTI_FTSR_TR22 0x00400000U
3201 /****************** Bit definition for EXTI_SWIER register ******************/
3202 #define EXTI_SWIER_SWIER0 0x00000001U
3203 #define EXTI_SWIER_SWIER1 0x00000002U
3204 #define EXTI_SWIER_SWIER2 0x00000004U
3205 #define EXTI_SWIER_SWIER3 0x00000008U
3206 #define EXTI_SWIER_SWIER4 0x00000010U
3207 #define EXTI_SWIER_SWIER5 0x00000020U
3208 #define EXTI_SWIER_SWIER6 0x00000040U
3209 #define EXTI_SWIER_SWIER7 0x00000080U
3210 #define EXTI_SWIER_SWIER8 0x00000100U
3211 #define EXTI_SWIER_SWIER9 0x00000200U
3212 #define EXTI_SWIER_SWIER10 0x00000400U
3213 #define EXTI_SWIER_SWIER11 0x00000800U
3214 #define EXTI_SWIER_SWIER12 0x00001000U
3215 #define EXTI_SWIER_SWIER13 0x00002000U
3216 #define EXTI_SWIER_SWIER14 0x00004000U
3217 #define EXTI_SWIER_SWIER15 0x00008000U
3218 #define EXTI_SWIER_SWIER16 0x00010000U
3219 #define EXTI_SWIER_SWIER17 0x00020000U
3220 #define EXTI_SWIER_SWIER18 0x00040000U
3221 #define EXTI_SWIER_SWIER19 0x00080000U
3222 #define EXTI_SWIER_SWIER20 0x00100000U
3223 #define EXTI_SWIER_SWIER21 0x00200000U
3224 #define EXTI_SWIER_SWIER22 0x00400000U
3226 /******************* Bit definition for EXTI_PR register ********************/
3227 #define EXTI_PR_PR0 0x00000001U
3228 #define EXTI_PR_PR1 0x00000002U
3229 #define EXTI_PR_PR2 0x00000004U
3230 #define EXTI_PR_PR3 0x00000008U
3231 #define EXTI_PR_PR4 0x00000010U
3232 #define EXTI_PR_PR5 0x00000020U
3233 #define EXTI_PR_PR6 0x00000040U
3234 #define EXTI_PR_PR7 0x00000080U
3235 #define EXTI_PR_PR8 0x00000100U
3236 #define EXTI_PR_PR9 0x00000200U
3237 #define EXTI_PR_PR10 0x00000400U
3238 #define EXTI_PR_PR11 0x00000800U
3239 #define EXTI_PR_PR12 0x00001000U
3240 #define EXTI_PR_PR13 0x00002000U
3241 #define EXTI_PR_PR14 0x00004000U
3242 #define EXTI_PR_PR15 0x00008000U
3243 #define EXTI_PR_PR16 0x00010000U
3244 #define EXTI_PR_PR17 0x00020000U
3245 #define EXTI_PR_PR18 0x00040000U
3246 #define EXTI_PR_PR19 0x00080000U
3247 #define EXTI_PR_PR20 0x00100000U
3248 #define EXTI_PR_PR21 0x00200000U
3249 #define EXTI_PR_PR22 0x00400000U
3251 /******************************************************************************/
3252 /* */
3253 /* FLASH */
3254 /* */
3255 /******************************************************************************/
3256 /******************* Bits definition for FLASH_ACR register *****************/
3257 #define FLASH_ACR_LATENCY 0x0000000FU
3258 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3259 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3260 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3261 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3262 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3263 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3264 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3265 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3266 
3267 #define FLASH_ACR_PRFTEN 0x00000100U
3268 #define FLASH_ACR_ICEN 0x00000200U
3269 #define FLASH_ACR_DCEN 0x00000400U
3270 #define FLASH_ACR_ICRST 0x00000800U
3271 #define FLASH_ACR_DCRST 0x00001000U
3272 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3273 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3274 
3275 /******************* Bits definition for FLASH_SR register ******************/
3276 #define FLASH_SR_EOP 0x00000001U
3277 #define FLASH_SR_SOP 0x00000002U
3278 #define FLASH_SR_WRPERR 0x00000010U
3279 #define FLASH_SR_PGAERR 0x00000020U
3280 #define FLASH_SR_PGPERR 0x00000040U
3281 #define FLASH_SR_PGSERR 0x00000080U
3282 #define FLASH_SR_BSY 0x00010000U
3283 
3284 /******************* Bits definition for FLASH_CR register ******************/
3285 #define FLASH_CR_PG 0x00000001U
3286 #define FLASH_CR_SER 0x00000002U
3287 #define FLASH_CR_MER 0x00000004U
3288 #define FLASH_CR_SNB 0x000000F8U
3289 #define FLASH_CR_SNB_0 0x00000008U
3290 #define FLASH_CR_SNB_1 0x00000010U
3291 #define FLASH_CR_SNB_2 0x00000020U
3292 #define FLASH_CR_SNB_3 0x00000040U
3293 #define FLASH_CR_SNB_4 0x00000080U
3294 #define FLASH_CR_PSIZE 0x00000300U
3295 #define FLASH_CR_PSIZE_0 0x00000100U
3296 #define FLASH_CR_PSIZE_1 0x00000200U
3297 #define FLASH_CR_STRT 0x00010000U
3298 #define FLASH_CR_EOPIE 0x01000000U
3299 #define FLASH_CR_LOCK 0x80000000U
3300 
3301 /******************* Bits definition for FLASH_OPTCR register ***************/
3302 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3303 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3304 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3305 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3306 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3307 
3308 #define FLASH_OPTCR_WDG_SW 0x00000020U
3309 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3310 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3311 #define FLASH_OPTCR_RDP 0x0000FF00U
3312 #define FLASH_OPTCR_RDP_0 0x00000100U
3313 #define FLASH_OPTCR_RDP_1 0x00000200U
3314 #define FLASH_OPTCR_RDP_2 0x00000400U
3315 #define FLASH_OPTCR_RDP_3 0x00000800U
3316 #define FLASH_OPTCR_RDP_4 0x00001000U
3317 #define FLASH_OPTCR_RDP_5 0x00002000U
3318 #define FLASH_OPTCR_RDP_6 0x00004000U
3319 #define FLASH_OPTCR_RDP_7 0x00008000U
3320 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3321 #define FLASH_OPTCR_nWRP_0 0x00010000U
3322 #define FLASH_OPTCR_nWRP_1 0x00020000U
3323 #define FLASH_OPTCR_nWRP_2 0x00040000U
3324 #define FLASH_OPTCR_nWRP_3 0x00080000U
3325 #define FLASH_OPTCR_nWRP_4 0x00100000U
3326 #define FLASH_OPTCR_nWRP_5 0x00200000U
3327 #define FLASH_OPTCR_nWRP_6 0x00400000U
3328 #define FLASH_OPTCR_nWRP_7 0x00800000U
3329 #define FLASH_OPTCR_nWRP_8 0x01000000U
3330 #define FLASH_OPTCR_nWRP_9 0x02000000U
3331 #define FLASH_OPTCR_nWRP_10 0x04000000U
3332 #define FLASH_OPTCR_nWRP_11 0x08000000U
3333 
3334 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3335 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3336 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3337 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3338 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3339 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3340 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3341 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3342 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3343 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3344 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3345 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3346 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3347 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3348 
3349 /******************************************************************************/
3350 /* */
3351 /* Flexible Static Memory Controller */
3352 /* */
3353 /******************************************************************************/
3354 /****************** Bit definition for FSMC_BCR1 register *******************/
3355 #define FSMC_BCR1_MBKEN 0x00000001U
3356 #define FSMC_BCR1_MUXEN 0x00000002U
3358 #define FSMC_BCR1_MTYP 0x0000000CU
3359 #define FSMC_BCR1_MTYP_0 0x00000004U
3360 #define FSMC_BCR1_MTYP_1 0x00000008U
3362 #define FSMC_BCR1_MWID 0x00000030U
3363 #define FSMC_BCR1_MWID_0 0x00000010U
3364 #define FSMC_BCR1_MWID_1 0x00000020U
3366 #define FSMC_BCR1_FACCEN 0x00000040U
3367 #define FSMC_BCR1_BURSTEN 0x00000100U
3368 #define FSMC_BCR1_WAITPOL 0x00000200U
3369 #define FSMC_BCR1_WAITCFG 0x00000800U
3370 #define FSMC_BCR1_WREN 0x00001000U
3371 #define FSMC_BCR1_WAITEN 0x00002000U
3372 #define FSMC_BCR1_EXTMOD 0x00004000U
3373 #define FSMC_BCR1_ASYNCWAIT 0x00008000U
3374 #define FSMC_BCR1_CPSIZE 0x00070000U
3375 #define FSMC_BCR1_CPSIZE_0 0x00010000U
3376 #define FSMC_BCR1_CPSIZE_1 0x00020000U
3377 #define FSMC_BCR1_CPSIZE_2 0x00040000U
3378 #define FSMC_BCR1_CBURSTRW 0x00080000U
3379 #define FSMC_BCR1_CCLKEN 0x00100000U
3380 #define FSMC_BCR1_WFDIS 0x00200000U
3382 /****************** Bit definition for FSMC_BCR2 register *******************/
3383 #define FSMC_BCR2_MBKEN 0x00000001U
3384 #define FSMC_BCR2_MUXEN 0x00000002U
3386 #define FSMC_BCR2_MTYP 0x0000000CU
3387 #define FSMC_BCR2_MTYP_0 0x00000004U
3388 #define FSMC_BCR2_MTYP_1 0x00000008U
3390 #define FSMC_BCR2_MWID 0x00000030U
3391 #define FSMC_BCR2_MWID_0 0x00000010U
3392 #define FSMC_BCR2_MWID_1 0x00000020U
3394 #define FSMC_BCR2_FACCEN 0x00000040U
3395 #define FSMC_BCR2_BURSTEN 0x00000100U
3396 #define FSMC_BCR2_WAITPOL 0x00000200U
3397 #define FSMC_BCR2_WAITCFG 0x00000800U
3398 #define FSMC_BCR2_WREN 0x00001000U
3399 #define FSMC_BCR2_WAITEN 0x00002000U
3400 #define FSMC_BCR2_EXTMOD 0x00004000U
3401 #define FSMC_BCR2_CPSIZE 0x00070000U
3402 #define FSMC_BCR2_CPSIZE_0 0x00010000U
3403 #define FSMC_BCR2_CPSIZE_1 0x00020000U
3404 #define FSMC_BCR2_CPSIZE_2 0x00040000U
3405 #define FSMC_BCR2_ASYNCWAIT 0x00008000U
3406 #define FSMC_BCR2_CBURSTRW 0x00080000U
3408 /****************** Bit definition for FSMC_BCR3 register *******************/
3409 #define FSMC_BCR3_MBKEN 0x00000001U
3410 #define FSMC_BCR3_MUXEN 0x00000002U
3412 #define FSMC_BCR3_MTYP 0x0000000CU
3413 #define FSMC_BCR3_MTYP_0 0x00000004U
3414 #define FSMC_BCR3_MTYP_1 0x00000008U
3416 #define FSMC_BCR3_MWID 0x00000030U
3417 #define FSMC_BCR3_MWID_0 0x00000010U
3418 #define FSMC_BCR3_MWID_1 0x00000020U
3420 #define FSMC_BCR3_FACCEN 0x00000040U
3421 #define FSMC_BCR3_BURSTEN 0x00000100U
3422 #define FSMC_BCR3_WAITPOL 0x00000200U
3423 #define FSMC_BCR3_WAITCFG 0x00000800U
3424 #define FSMC_BCR3_WREN 0x00001000U
3425 #define FSMC_BCR3_WAITEN 0x00002000U
3426 #define FSMC_BCR3_EXTMOD 0x00004000U
3427 #define FSMC_BCR3_CPSIZE 0x00070000U
3428 #define FSMC_BCR3_CPSIZE_0 0x00010000U
3429 #define FSMC_BCR3_CPSIZE_1 0x00020000U
3430 #define FSMC_BCR3_CPSIZE_2 0x00040000U
3431 #define FSMC_BCR3_ASYNCWAIT 0x00008000U
3432 #define FSMC_BCR3_CBURSTRW 0x00080000U
3434 /****************** Bit definition for FSMC_BCR4 register *******************/
3435 #define FSMC_BCR4_MBKEN 0x00000001U
3436 #define FSMC_BCR4_MUXEN 0x00000002U
3438 #define FSMC_BCR4_MTYP 0x0000000CU
3439 #define FSMC_BCR4_MTYP_0 0x00000004U
3440 #define FSMC_BCR4_MTYP_1 0x00000008U
3442 #define FSMC_BCR4_MWID 0x00000030U
3443 #define FSMC_BCR4_MWID_0 0x00000010U
3444 #define FSMC_BCR4_MWID_1 0x00000020U
3446 #define FSMC_BCR4_FACCEN 0x00000040U
3447 #define FSMC_BCR4_BURSTEN 0x00000100U
3448 #define FSMC_BCR4_WAITPOL 0x00000200U
3449 #define FSMC_BCR4_WAITCFG 0x00000800U
3450 #define FSMC_BCR4_WREN 0x00001000U
3451 #define FSMC_BCR4_WAITEN 0x00002000U
3452 #define FSMC_BCR4_EXTMOD 0x00004000U
3453 #define FSMC_BCR4_CPSIZE 0x00070000U
3454 #define FSMC_BCR4_CPSIZE_0 0x00010000U
3455 #define FSMC_BCR4_CPSIZE_1 0x00020000U
3456 #define FSMC_BCR4_CPSIZE_2 0x00040000U
3457 #define FSMC_BCR4_ASYNCWAIT 0x00008000U
3458 #define FSMC_BCR4_CBURSTRW 0x00080000U
3460 /****************** Bit definition for FSMC_BTR1 register ******************/
3461 #define FSMC_BTR1_ADDSET 0x0000000FU
3462 #define FSMC_BTR1_ADDSET_0 0x00000001U
3463 #define FSMC_BTR1_ADDSET_1 0x00000002U
3464 #define FSMC_BTR1_ADDSET_2 0x00000004U
3465 #define FSMC_BTR1_ADDSET_3 0x00000008U
3467 #define FSMC_BTR1_ADDHLD 0x000000F0U
3468 #define FSMC_BTR1_ADDHLD_0 0x00000010U
3469 #define FSMC_BTR1_ADDHLD_1 0x00000020U
3470 #define FSMC_BTR1_ADDHLD_2 0x00000040U
3471 #define FSMC_BTR1_ADDHLD_3 0x00000080U
3473 #define FSMC_BTR1_DATAST 0x0000FF00U
3474 #define FSMC_BTR1_DATAST_0 0x00000100U
3475 #define FSMC_BTR1_DATAST_1 0x00000200U
3476 #define FSMC_BTR1_DATAST_2 0x00000400U
3477 #define FSMC_BTR1_DATAST_3 0x00000800U
3478 #define FSMC_BTR1_DATAST_4 0x00001000U
3479 #define FSMC_BTR1_DATAST_5 0x00002000U
3480 #define FSMC_BTR1_DATAST_6 0x00004000U
3481 #define FSMC_BTR1_DATAST_7 0x00008000U
3483 #define FSMC_BTR1_BUSTURN 0x000F0000U
3484 #define FSMC_BTR1_BUSTURN_0 0x00010000U
3485 #define FSMC_BTR1_BUSTURN_1 0x00020000U
3486 #define FSMC_BTR1_BUSTURN_2 0x00040000U
3487 #define FSMC_BTR1_BUSTURN_3 0x00080000U
3489 #define FSMC_BTR1_CLKDIV 0x00F00000U
3490 #define FSMC_BTR1_CLKDIV_0 0x00100000U
3491 #define FSMC_BTR1_CLKDIV_1 0x00200000U
3492 #define FSMC_BTR1_CLKDIV_2 0x00400000U
3493 #define FSMC_BTR1_CLKDIV_3 0x00800000U
3495 #define FSMC_BTR1_DATLAT 0x0F000000U
3496 #define FSMC_BTR1_DATLAT_0 0x01000000U
3497 #define FSMC_BTR1_DATLAT_1 0x02000000U
3498 #define FSMC_BTR1_DATLAT_2 0x04000000U
3499 #define FSMC_BTR1_DATLAT_3 0x08000000U
3501 #define FSMC_BTR1_ACCMOD 0x30000000U
3502 #define FSMC_BTR1_ACCMOD_0 0x10000000U
3503 #define FSMC_BTR1_ACCMOD_1 0x20000000U
3505 /****************** Bit definition for FSMC_BTR2 register *******************/
3506 #define FSMC_BTR2_ADDSET 0x0000000FU
3507 #define FSMC_BTR2_ADDSET_0 0x00000001U
3508 #define FSMC_BTR2_ADDSET_1 0x00000002U
3509 #define FSMC_BTR2_ADDSET_2 0x00000004U
3510 #define FSMC_BTR2_ADDSET_3 0x00000008U
3512 #define FSMC_BTR2_ADDHLD 0x000000F0U
3513 #define FSMC_BTR2_ADDHLD_0 0x00000010U
3514 #define FSMC_BTR2_ADDHLD_1 0x00000020U
3515 #define FSMC_BTR2_ADDHLD_2 0x00000040U
3516 #define FSMC_BTR2_ADDHLD_3 0x00000080U
3518 #define FSMC_BTR2_DATAST 0x0000FF00U
3519 #define FSMC_BTR2_DATAST_0 0x00000100U
3520 #define FSMC_BTR2_DATAST_1 0x00000200U
3521 #define FSMC_BTR2_DATAST_2 0x00000400U
3522 #define FSMC_BTR2_DATAST_3 0x00000800U
3523 #define FSMC_BTR2_DATAST_4 0x00001000U
3524 #define FSMC_BTR2_DATAST_5 0x00002000U
3525 #define FSMC_BTR2_DATAST_6 0x00004000U
3526 #define FSMC_BTR2_DATAST_7 0x00008000U
3528 #define FSMC_BTR2_BUSTURN 0x000F0000U
3529 #define FSMC_BTR2_BUSTURN_0 0x00010000U
3530 #define FSMC_BTR2_BUSTURN_1 0x00020000U
3531 #define FSMC_BTR2_BUSTURN_2 0x00040000U
3532 #define FSMC_BTR2_BUSTURN_3 0x00080000U
3534 #define FSMC_BTR2_CLKDIV 0x00F00000U
3535 #define FSMC_BTR2_CLKDIV_0 0x00100000U
3536 #define FSMC_BTR2_CLKDIV_1 0x00200000U
3537 #define FSMC_BTR2_CLKDIV_2 0x00400000U
3538 #define FSMC_BTR2_CLKDIV_3 0x00800000U
3540 #define FSMC_BTR2_DATLAT 0x0F000000U
3541 #define FSMC_BTR2_DATLAT_0 0x01000000U
3542 #define FSMC_BTR2_DATLAT_1 0x02000000U
3543 #define FSMC_BTR2_DATLAT_2 0x04000000U
3544 #define FSMC_BTR2_DATLAT_3 0x08000000U
3546 #define FSMC_BTR2_ACCMOD 0x30000000U
3547 #define FSMC_BTR2_ACCMOD_0 0x10000000U
3548 #define FSMC_BTR2_ACCMOD_1 0x20000000U
3550 /******************* Bit definition for FSMC_BTR3 register *******************/
3551 #define FSMC_BTR3_ADDSET 0x0000000FU
3552 #define FSMC_BTR3_ADDSET_0 0x00000001U
3553 #define FSMC_BTR3_ADDSET_1 0x00000002U
3554 #define FSMC_BTR3_ADDSET_2 0x00000004U
3555 #define FSMC_BTR3_ADDSET_3 0x00000008U
3557 #define FSMC_BTR3_ADDHLD 0x000000F0U
3558 #define FSMC_BTR3_ADDHLD_0 0x00000010U
3559 #define FSMC_BTR3_ADDHLD_1 0x00000020U
3560 #define FSMC_BTR3_ADDHLD_2 0x00000040U
3561 #define FSMC_BTR3_ADDHLD_3 0x00000080U
3563 #define FSMC_BTR3_DATAST 0x0000FF00U
3564 #define FSMC_BTR3_DATAST_0 0x00000100U
3565 #define FSMC_BTR3_DATAST_1 0x00000200U
3566 #define FSMC_BTR3_DATAST_2 0x00000400U
3567 #define FSMC_BTR3_DATAST_3 0x00000800U
3568 #define FSMC_BTR3_DATAST_4 0x00001000U
3569 #define FSMC_BTR3_DATAST_5 0x00002000U
3570 #define FSMC_BTR3_DATAST_6 0x00004000U
3571 #define FSMC_BTR3_DATAST_7 0x00008000U
3573 #define FSMC_BTR3_BUSTURN 0x000F0000U
3574 #define FSMC_BTR3_BUSTURN_0 0x00010000U
3575 #define FSMC_BTR3_BUSTURN_1 0x00020000U
3576 #define FSMC_BTR3_BUSTURN_2 0x00040000U
3577 #define FSMC_BTR3_BUSTURN_3 0x00080000U
3579 #define FSMC_BTR3_CLKDIV 0x00F00000U
3580 #define FSMC_BTR3_CLKDIV_0 0x00100000U
3581 #define FSMC_BTR3_CLKDIV_1 0x00200000U
3582 #define FSMC_BTR3_CLKDIV_2 0x00400000U
3583 #define FSMC_BTR3_CLKDIV_3 0x00800000U
3585 #define FSMC_BTR3_DATLAT 0x0F000000U
3586 #define FSMC_BTR3_DATLAT_0 0x01000000U
3587 #define FSMC_BTR3_DATLAT_1 0x02000000U
3588 #define FSMC_BTR3_DATLAT_2 0x04000000U
3589 #define FSMC_BTR3_DATLAT_3 0x08000000U
3591 #define FSMC_BTR3_ACCMOD 0x30000000U
3592 #define FSMC_BTR3_ACCMOD_0 0x10000000U
3593 #define FSMC_BTR3_ACCMOD_1 0x20000000U
3595 /****************** Bit definition for FSMC_BTR4 register *******************/
3596 #define FSMC_BTR4_ADDSET 0x0000000FU
3597 #define FSMC_BTR4_ADDSET_0 0x00000001U
3598 #define FSMC_BTR4_ADDSET_1 0x00000002U
3599 #define FSMC_BTR4_ADDSET_2 0x00000004U
3600 #define FSMC_BTR4_ADDSET_3 0x00000008U
3602 #define FSMC_BTR4_ADDHLD 0x000000F0U
3603 #define FSMC_BTR4_ADDHLD_0 0x00000010U
3604 #define FSMC_BTR4_ADDHLD_1 0x00000020U
3605 #define FSMC_BTR4_ADDHLD_2 0x00000040U
3606 #define FSMC_BTR4_ADDHLD_3 0x00000080U
3608 #define FSMC_BTR4_DATAST 0x0000FF00U
3609 #define FSMC_BTR4_DATAST_0 0x00000100U
3610 #define FSMC_BTR4_DATAST_1 0x00000200U
3611 #define FSMC_BTR4_DATAST_2 0x00000400U
3612 #define FSMC_BTR4_DATAST_3 0x00000800U
3613 #define FSMC_BTR4_DATAST_4 0x00001000U
3614 #define FSMC_BTR4_DATAST_5 0x00002000U
3615 #define FSMC_BTR4_DATAST_6 0x00004000U
3616 #define FSMC_BTR4_DATAST_7 0x00008000U
3618 #define FSMC_BTR4_BUSTURN 0x000F0000U
3619 #define FSMC_BTR4_BUSTURN_0 0x00010000U
3620 #define FSMC_BTR4_BUSTURN_1 0x00020000U
3621 #define FSMC_BTR4_BUSTURN_2 0x00040000U
3622 #define FSMC_BTR4_BUSTURN_3 0x00080000U
3624 #define FSMC_BTR4_CLKDIV 0x00F00000U
3625 #define FSMC_BTR4_CLKDIV_0 0x00100000U
3626 #define FSMC_BTR4_CLKDIV_1 0x00200000U
3627 #define FSMC_BTR4_CLKDIV_2 0x00400000U
3628 #define FSMC_BTR4_CLKDIV_3 0x00800000U
3630 #define FSMC_BTR4_DATLAT 0x0F000000U
3631 #define FSMC_BTR4_DATLAT_0 0x01000000U
3632 #define FSMC_BTR4_DATLAT_1 0x02000000U
3633 #define FSMC_BTR4_DATLAT_2 0x04000000U
3634 #define FSMC_BTR4_DATLAT_3 0x08000000U
3636 #define FSMC_BTR4_ACCMOD 0x30000000U
3637 #define FSMC_BTR4_ACCMOD_0 0x10000000U
3638 #define FSMC_BTR4_ACCMOD_1 0x20000000U
3640 /****************** Bit definition for FSMC_BWTR1 register ******************/
3641 #define FSMC_BWTR1_ADDSET 0x0000000FU
3642 #define FSMC_BWTR1_ADDSET_0 0x00000001U
3643 #define FSMC_BWTR1_ADDSET_1 0x00000002U
3644 #define FSMC_BWTR1_ADDSET_2 0x00000004U
3645 #define FSMC_BWTR1_ADDSET_3 0x00000008U
3647 #define FSMC_BWTR1_ADDHLD 0x000000F0U
3648 #define FSMC_BWTR1_ADDHLD_0 0x00000010U
3649 #define FSMC_BWTR1_ADDHLD_1 0x00000020U
3650 #define FSMC_BWTR1_ADDHLD_2 0x00000040U
3651 #define FSMC_BWTR1_ADDHLD_3 0x00000080U
3653 #define FSMC_BWTR1_DATAST 0x0000FF00U
3654 #define FSMC_BWTR1_DATAST_0 0x00000100U
3655 #define FSMC_BWTR1_DATAST_1 0x00000200U
3656 #define FSMC_BWTR1_DATAST_2 0x00000400U
3657 #define FSMC_BWTR1_DATAST_3 0x00000800U
3658 #define FSMC_BWTR1_DATAST_4 0x00001000U
3659 #define FSMC_BWTR1_DATAST_5 0x00002000U
3660 #define FSMC_BWTR1_DATAST_6 0x00004000U
3661 #define FSMC_BWTR1_DATAST_7 0x00008000U
3663 #define FSMC_BWTR1_BUSTURN 0x000F0000U
3664 #define FSMC_BWTR1_BUSTURN_0 0x00010000U
3665 #define FSMC_BWTR1_BUSTURN_1 0x00020000U
3666 #define FSMC_BWTR1_BUSTURN_2 0x00040000U
3667 #define FSMC_BWTR1_BUSTURN_3 0x00080000U
3669 #define FSMC_BWTR1_ACCMOD 0x30000000U
3670 #define FSMC_BWTR1_ACCMOD_0 0x10000000U
3671 #define FSMC_BWTR1_ACCMOD_1 0x20000000U
3673 /****************** Bit definition for FSMC_BWTR2 register ******************/
3674 #define FSMC_BWTR2_ADDSET 0x0000000FU
3675 #define FSMC_BWTR2_ADDSET_0 0x00000001U
3676 #define FSMC_BWTR2_ADDSET_1 0x00000002U
3677 #define FSMC_BWTR2_ADDSET_2 0x00000004U
3678 #define FSMC_BWTR2_ADDSET_3 0x00000008U
3680 #define FSMC_BWTR2_ADDHLD 0x000000F0U
3681 #define FSMC_BWTR2_ADDHLD_0 0x00000010U
3682 #define FSMC_BWTR2_ADDHLD_1 0x00000020U
3683 #define FSMC_BWTR2_ADDHLD_2 0x00000040U
3684 #define FSMC_BWTR2_ADDHLD_3 0x00000080U
3686 #define FSMC_BWTR2_DATAST 0x0000FF00U
3687 #define FSMC_BWTR2_DATAST_0 0x00000100U
3688 #define FSMC_BWTR2_DATAST_1 0x00000200U
3689 #define FSMC_BWTR2_DATAST_2 0x00000400U
3690 #define FSMC_BWTR2_DATAST_3 0x00000800U
3691 #define FSMC_BWTR2_DATAST_4 0x00001000U
3692 #define FSMC_BWTR2_DATAST_5 0x00002000U
3693 #define FSMC_BWTR2_DATAST_6 0x00004000U
3694 #define FSMC_BWTR2_DATAST_7 0x00008000U
3696 #define FSMC_BWTR2_BUSTURN 0x000F0000U
3697 #define FSMC_BWTR2_BUSTURN_0 0x00010000U
3698 #define FSMC_BWTR2_BUSTURN_1 0x00020000U
3699 #define FSMC_BWTR2_BUSTURN_2 0x00040000U
3700 #define FSMC_BWTR2_BUSTURN_3 0x00080000U
3702 #define FSMC_BWTR2_ACCMOD 0x30000000U
3703 #define FSMC_BWTR2_ACCMOD_0 0x10000000U
3704 #define FSMC_BWTR2_ACCMOD_1 0x20000000U
3706 /****************** Bit definition for FSMC_BWTR3 register ******************/
3707 #define FSMC_BWTR3_ADDSET 0x0000000FU
3708 #define FSMC_BWTR3_ADDSET_0 0x00000001U
3709 #define FSMC_BWTR3_ADDSET_1 0x00000002U
3710 #define FSMC_BWTR3_ADDSET_2 0x00000004U
3711 #define FSMC_BWTR3_ADDSET_3 0x00000008U
3713 #define FSMC_BWTR3_ADDHLD 0x000000F0U
3714 #define FSMC_BWTR3_ADDHLD_0 0x00000010U
3715 #define FSMC_BWTR3_ADDHLD_1 0x00000020U
3716 #define FSMC_BWTR3_ADDHLD_2 0x00000040U
3717 #define FSMC_BWTR3_ADDHLD_3 0x00000080U
3719 #define FSMC_BWTR3_DATAST 0x0000FF00U
3720 #define FSMC_BWTR3_DATAST_0 0x00000100U
3721 #define FSMC_BWTR3_DATAST_1 0x00000200U
3722 #define FSMC_BWTR3_DATAST_2 0x00000400U
3723 #define FSMC_BWTR3_DATAST_3 0x00000800U
3724 #define FSMC_BWTR3_DATAST_4 0x00001000U
3725 #define FSMC_BWTR3_DATAST_5 0x00002000U
3726 #define FSMC_BWTR3_DATAST_6 0x00004000U
3727 #define FSMC_BWTR3_DATAST_7 0x00008000U
3729 #define FSMC_BWTR3_BUSTURN 0x000F0000U
3730 #define FSMC_BWTR3_BUSTURN_0 0x00010000U
3731 #define FSMC_BWTR3_BUSTURN_1 0x00020000U
3732 #define FSMC_BWTR3_BUSTURN_2 0x00040000U
3733 #define FSMC_BWTR3_BUSTURN_3 0x00080000U
3735 #define FSMC_BWTR3_ACCMOD 0x30000000U
3736 #define FSMC_BWTR3_ACCMOD_0 0x10000000U
3737 #define FSMC_BWTR3_ACCMOD_1 0x20000000U
3739 /****************** Bit definition for FSMC_BWTR4 register ******************/
3740 #define FSMC_BWTR4_ADDSET 0x0000000FU
3741 #define FSMC_BWTR4_ADDSET_0 0x00000001U
3742 #define FSMC_BWTR4_ADDSET_1 0x00000002U
3743 #define FSMC_BWTR4_ADDSET_2 0x00000004U
3744 #define FSMC_BWTR4_ADDSET_3 0x00000008U
3746 #define FSMC_BWTR4_ADDHLD 0x000000F0U
3747 #define FSMC_BWTR4_ADDHLD_0 0x00000010U
3748 #define FSMC_BWTR4_ADDHLD_1 0x00000020U
3749 #define FSMC_BWTR4_ADDHLD_2 0x00000040U
3750 #define FSMC_BWTR4_ADDHLD_3 0x00000080U
3752 #define FSMC_BWTR4_DATAST 0x0000FF00U
3753 #define FSMC_BWTR4_DATAST_0 0x00000100U
3754 #define FSMC_BWTR4_DATAST_1 0x00000200U
3755 #define FSMC_BWTR4_DATAST_2 0x00000400U
3756 #define FSMC_BWTR4_DATAST_3 0x00000800U
3757 #define FSMC_BWTR4_DATAST_4 0x00001000U
3758 #define FSMC_BWTR4_DATAST_5 0x00002000U
3759 #define FSMC_BWTR4_DATAST_6 0x00004000U
3760 #define FSMC_BWTR4_DATAST_7 0x00008000U
3762 #define FSMC_BWTR4_BUSTURN 0x000F0000U
3763 #define FSMC_BWTR4_BUSTURN_0 0x00010000U
3764 #define FSMC_BWTR4_BUSTURN_1 0x00020000U
3765 #define FSMC_BWTR4_BUSTURN_2 0x00040000U
3766 #define FSMC_BWTR4_BUSTURN_3 0x00080000U
3768 #define FSMC_BWTR4_ACCMOD 0x30000000U
3769 #define FSMC_BWTR4_ACCMOD_0 0x10000000U
3770 #define FSMC_BWTR4_ACCMOD_1 0x20000000U
3772 /******************************************************************************/
3773 /* */
3774 /* General Purpose I/O */
3775 /* */
3776 /******************************************************************************/
3777 /****************** Bits definition for GPIO_MODER register *****************/
3778 #define GPIO_MODER_MODER0 0x00000003U
3779 #define GPIO_MODER_MODER0_0 0x00000001U
3780 #define GPIO_MODER_MODER0_1 0x00000002U
3781 
3782 #define GPIO_MODER_MODER1 0x0000000CU
3783 #define GPIO_MODER_MODER1_0 0x00000004U
3784 #define GPIO_MODER_MODER1_1 0x00000008U
3785 
3786 #define GPIO_MODER_MODER2 0x00000030U
3787 #define GPIO_MODER_MODER2_0 0x00000010U
3788 #define GPIO_MODER_MODER2_1 0x00000020U
3789 
3790 #define GPIO_MODER_MODER3 0x000000C0U
3791 #define GPIO_MODER_MODER3_0 0x00000040U
3792 #define GPIO_MODER_MODER3_1 0x00000080U
3793 
3794 #define GPIO_MODER_MODER4 0x00000300U
3795 #define GPIO_MODER_MODER4_0 0x00000100U
3796 #define GPIO_MODER_MODER4_1 0x00000200U
3797 
3798 #define GPIO_MODER_MODER5 0x00000C00U
3799 #define GPIO_MODER_MODER5_0 0x00000400U
3800 #define GPIO_MODER_MODER5_1 0x00000800U
3801 
3802 #define GPIO_MODER_MODER6 0x00003000U
3803 #define GPIO_MODER_MODER6_0 0x00001000U
3804 #define GPIO_MODER_MODER6_1 0x00002000U
3805 
3806 #define GPIO_MODER_MODER7 0x0000C000U
3807 #define GPIO_MODER_MODER7_0 0x00004000U
3808 #define GPIO_MODER_MODER7_1 0x00008000U
3809 
3810 #define GPIO_MODER_MODER8 0x00030000U
3811 #define GPIO_MODER_MODER8_0 0x00010000U
3812 #define GPIO_MODER_MODER8_1 0x00020000U
3813 
3814 #define GPIO_MODER_MODER9 0x000C0000U
3815 #define GPIO_MODER_MODER9_0 0x00040000U
3816 #define GPIO_MODER_MODER9_1 0x00080000U
3817 
3818 #define GPIO_MODER_MODER10 0x00300000U
3819 #define GPIO_MODER_MODER10_0 0x00100000U
3820 #define GPIO_MODER_MODER10_1 0x00200000U
3821 
3822 #define GPIO_MODER_MODER11 0x00C00000U
3823 #define GPIO_MODER_MODER11_0 0x00400000U
3824 #define GPIO_MODER_MODER11_1 0x00800000U
3825 
3826 #define GPIO_MODER_MODER12 0x03000000U
3827 #define GPIO_MODER_MODER12_0 0x01000000U
3828 #define GPIO_MODER_MODER12_1 0x02000000U
3829 
3830 #define GPIO_MODER_MODER13 0x0C000000U
3831 #define GPIO_MODER_MODER13_0 0x04000000U
3832 #define GPIO_MODER_MODER13_1 0x08000000U
3833 
3834 #define GPIO_MODER_MODER14 0x30000000U
3835 #define GPIO_MODER_MODER14_0 0x10000000U
3836 #define GPIO_MODER_MODER14_1 0x20000000U
3837 
3838 #define GPIO_MODER_MODER15 0xC0000000U
3839 #define GPIO_MODER_MODER15_0 0x40000000U
3840 #define GPIO_MODER_MODER15_1 0x80000000U
3841 
3842 /****************** Bits definition for GPIO_OTYPER register ****************/
3843 #define GPIO_OTYPER_OT_0 0x00000001U
3844 #define GPIO_OTYPER_OT_1 0x00000002U
3845 #define GPIO_OTYPER_OT_2 0x00000004U
3846 #define GPIO_OTYPER_OT_3 0x00000008U
3847 #define GPIO_OTYPER_OT_4 0x00000010U
3848 #define GPIO_OTYPER_OT_5 0x00000020U
3849 #define GPIO_OTYPER_OT_6 0x00000040U
3850 #define GPIO_OTYPER_OT_7 0x00000080U
3851 #define GPIO_OTYPER_OT_8 0x00000100U
3852 #define GPIO_OTYPER_OT_9 0x00000200U
3853 #define GPIO_OTYPER_OT_10 0x00000400U
3854 #define GPIO_OTYPER_OT_11 0x00000800U
3855 #define GPIO_OTYPER_OT_12 0x00001000U
3856 #define GPIO_OTYPER_OT_13 0x00002000U
3857 #define GPIO_OTYPER_OT_14 0x00004000U
3858 #define GPIO_OTYPER_OT_15 0x00008000U
3859 
3860 /****************** Bits definition for GPIO_OSPEEDR register ***************/
3861 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
3862 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
3863 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
3864 
3865 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
3866 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
3867 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
3868 
3869 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
3870 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
3871 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
3872 
3873 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
3874 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
3875 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
3876 
3877 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
3878 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
3879 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
3880 
3881 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
3882 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
3883 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
3884 
3885 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
3886 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
3887 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
3888 
3889 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
3890 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
3891 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
3892 
3893 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
3894 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
3895 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
3896 
3897 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
3898 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
3899 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
3900 
3901 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
3902 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
3903 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
3904 
3905 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
3906 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
3907 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
3908 
3909 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
3910 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
3911 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
3912 
3913 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
3914 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
3915 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
3916 
3917 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
3918 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
3919 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
3920 
3921 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
3922 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
3923 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
3924 
3925 /****************** Bits definition for GPIO_PUPDR register *****************/
3926 #define GPIO_PUPDR_PUPDR0 0x00000003U
3927 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
3928 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
3929 
3930 #define GPIO_PUPDR_PUPDR1 0x0000000CU
3931 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
3932 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
3933 
3934 #define GPIO_PUPDR_PUPDR2 0x00000030U
3935 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
3936 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
3937 
3938 #define GPIO_PUPDR_PUPDR3 0x000000C0U
3939 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
3940 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
3941 
3942 #define GPIO_PUPDR_PUPDR4 0x00000300U
3943 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
3944 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
3945 
3946 #define GPIO_PUPDR_PUPDR5 0x00000C00U
3947 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
3948 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
3949 
3950 #define GPIO_PUPDR_PUPDR6 0x00003000U
3951 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
3952 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
3953 
3954 #define GPIO_PUPDR_PUPDR7 0x0000C000U
3955 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
3956 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
3957 
3958 #define GPIO_PUPDR_PUPDR8 0x00030000U
3959 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
3960 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
3961 
3962 #define GPIO_PUPDR_PUPDR9 0x000C0000U
3963 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
3964 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
3965 
3966 #define GPIO_PUPDR_PUPDR10 0x00300000U
3967 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
3968 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
3969 
3970 #define GPIO_PUPDR_PUPDR11 0x00C00000U
3971 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
3972 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
3973 
3974 #define GPIO_PUPDR_PUPDR12 0x03000000U
3975 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
3976 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
3977 
3978 #define GPIO_PUPDR_PUPDR13 0x0C000000U
3979 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
3980 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
3981 
3982 #define GPIO_PUPDR_PUPDR14 0x30000000U
3983 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
3984 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
3985 
3986 #define GPIO_PUPDR_PUPDR15 0xC0000000U
3987 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
3988 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
3989 
3990 /****************** Bits definition for GPIO_IDR register *******************/
3991 #define GPIO_IDR_IDR_0 0x00000001U
3992 #define GPIO_IDR_IDR_1 0x00000002U
3993 #define GPIO_IDR_IDR_2 0x00000004U
3994 #define GPIO_IDR_IDR_3 0x00000008U
3995 #define GPIO_IDR_IDR_4 0x00000010U
3996 #define GPIO_IDR_IDR_5 0x00000020U
3997 #define GPIO_IDR_IDR_6 0x00000040U
3998 #define GPIO_IDR_IDR_7 0x00000080U
3999 #define GPIO_IDR_IDR_8 0x00000100U
4000 #define GPIO_IDR_IDR_9 0x00000200U
4001 #define GPIO_IDR_IDR_10 0x00000400U
4002 #define GPIO_IDR_IDR_11 0x00000800U
4003 #define GPIO_IDR_IDR_12 0x00001000U
4004 #define GPIO_IDR_IDR_13 0x00002000U
4005 #define GPIO_IDR_IDR_14 0x00004000U
4006 #define GPIO_IDR_IDR_15 0x00008000U
4007 
4008 /****************** Bits definition for GPIO_ODR register *******************/
4009 #define GPIO_ODR_ODR_0 0x00000001U
4010 #define GPIO_ODR_ODR_1 0x00000002U
4011 #define GPIO_ODR_ODR_2 0x00000004U
4012 #define GPIO_ODR_ODR_3 0x00000008U
4013 #define GPIO_ODR_ODR_4 0x00000010U
4014 #define GPIO_ODR_ODR_5 0x00000020U
4015 #define GPIO_ODR_ODR_6 0x00000040U
4016 #define GPIO_ODR_ODR_7 0x00000080U
4017 #define GPIO_ODR_ODR_8 0x00000100U
4018 #define GPIO_ODR_ODR_9 0x00000200U
4019 #define GPIO_ODR_ODR_10 0x00000400U
4020 #define GPIO_ODR_ODR_11 0x00000800U
4021 #define GPIO_ODR_ODR_12 0x00001000U
4022 #define GPIO_ODR_ODR_13 0x00002000U
4023 #define GPIO_ODR_ODR_14 0x00004000U
4024 #define GPIO_ODR_ODR_15 0x00008000U
4025 
4026 /****************** Bits definition for GPIO_BSRR register ******************/
4027 #define GPIO_BSRR_BS_0 0x00000001U
4028 #define GPIO_BSRR_BS_1 0x00000002U
4029 #define GPIO_BSRR_BS_2 0x00000004U
4030 #define GPIO_BSRR_BS_3 0x00000008U
4031 #define GPIO_BSRR_BS_4 0x00000010U
4032 #define GPIO_BSRR_BS_5 0x00000020U
4033 #define GPIO_BSRR_BS_6 0x00000040U
4034 #define GPIO_BSRR_BS_7 0x00000080U
4035 #define GPIO_BSRR_BS_8 0x00000100U
4036 #define GPIO_BSRR_BS_9 0x00000200U
4037 #define GPIO_BSRR_BS_10 0x00000400U
4038 #define GPIO_BSRR_BS_11 0x00000800U
4039 #define GPIO_BSRR_BS_12 0x00001000U
4040 #define GPIO_BSRR_BS_13 0x00002000U
4041 #define GPIO_BSRR_BS_14 0x00004000U
4042 #define GPIO_BSRR_BS_15 0x00008000U
4043 #define GPIO_BSRR_BR_0 0x00010000U
4044 #define GPIO_BSRR_BR_1 0x00020000U
4045 #define GPIO_BSRR_BR_2 0x00040000U
4046 #define GPIO_BSRR_BR_3 0x00080000U
4047 #define GPIO_BSRR_BR_4 0x00100000U
4048 #define GPIO_BSRR_BR_5 0x00200000U
4049 #define GPIO_BSRR_BR_6 0x00400000U
4050 #define GPIO_BSRR_BR_7 0x00800000U
4051 #define GPIO_BSRR_BR_8 0x01000000U
4052 #define GPIO_BSRR_BR_9 0x02000000U
4053 #define GPIO_BSRR_BR_10 0x04000000U
4054 #define GPIO_BSRR_BR_11 0x08000000U
4055 #define GPIO_BSRR_BR_12 0x10000000U
4056 #define GPIO_BSRR_BR_13 0x20000000U
4057 #define GPIO_BSRR_BR_14 0x40000000U
4058 #define GPIO_BSRR_BR_15 0x80000000U
4059 
4060 /****************** Bit definition for GPIO_LCKR register *********************/
4061 #define GPIO_LCKR_LCK0 0x00000001U
4062 #define GPIO_LCKR_LCK1 0x00000002U
4063 #define GPIO_LCKR_LCK2 0x00000004U
4064 #define GPIO_LCKR_LCK3 0x00000008U
4065 #define GPIO_LCKR_LCK4 0x00000010U
4066 #define GPIO_LCKR_LCK5 0x00000020U
4067 #define GPIO_LCKR_LCK6 0x00000040U
4068 #define GPIO_LCKR_LCK7 0x00000080U
4069 #define GPIO_LCKR_LCK8 0x00000100U
4070 #define GPIO_LCKR_LCK9 0x00000200U
4071 #define GPIO_LCKR_LCK10 0x00000400U
4072 #define GPIO_LCKR_LCK11 0x00000800U
4073 #define GPIO_LCKR_LCK12 0x00001000U
4074 #define GPIO_LCKR_LCK13 0x00002000U
4075 #define GPIO_LCKR_LCK14 0x00004000U
4076 #define GPIO_LCKR_LCK15 0x00008000U
4077 #define GPIO_LCKR_LCKK 0x00010000U
4078 
4079 /******************************************************************************/
4080 /* */
4081 /* Inter-integrated Circuit Interface */
4082 /* */
4083 /******************************************************************************/
4084 /******************* Bit definition for I2C_CR1 register ********************/
4085 #define I2C_CR1_PE 0x00000001U
4086 #define I2C_CR1_SMBUS 0x00000002U
4087 #define I2C_CR1_SMBTYPE 0x00000008U
4088 #define I2C_CR1_ENARP 0x00000010U
4089 #define I2C_CR1_ENPEC 0x00000020U
4090 #define I2C_CR1_ENGC 0x00000040U
4091 #define I2C_CR1_NOSTRETCH 0x00000080U
4092 #define I2C_CR1_START 0x00000100U
4093 #define I2C_CR1_STOP 0x00000200U
4094 #define I2C_CR1_ACK 0x00000400U
4095 #define I2C_CR1_POS 0x00000800U
4096 #define I2C_CR1_PEC 0x00001000U
4097 #define I2C_CR1_ALERT 0x00002000U
4098 #define I2C_CR1_SWRST 0x00008000U
4100 /******************* Bit definition for I2C_CR2 register ********************/
4101 #define I2C_CR2_FREQ 0x0000003FU
4102 #define I2C_CR2_FREQ_0 0x00000001U
4103 #define I2C_CR2_FREQ_1 0x00000002U
4104 #define I2C_CR2_FREQ_2 0x00000004U
4105 #define I2C_CR2_FREQ_3 0x00000008U
4106 #define I2C_CR2_FREQ_4 0x00000010U
4107 #define I2C_CR2_FREQ_5 0x00000020U
4109 #define I2C_CR2_ITERREN 0x00000100U
4110 #define I2C_CR2_ITEVTEN 0x00000200U
4111 #define I2C_CR2_ITBUFEN 0x00000400U
4112 #define I2C_CR2_DMAEN 0x00000800U
4113 #define I2C_CR2_LAST 0x00001000U
4115 /******************* Bit definition for I2C_OAR1 register *******************/
4116 #define I2C_OAR1_ADD1_7 0x000000FEU
4117 #define I2C_OAR1_ADD8_9 0x00000300U
4119 #define I2C_OAR1_ADD0 0x00000001U
4120 #define I2C_OAR1_ADD1 0x00000002U
4121 #define I2C_OAR1_ADD2 0x00000004U
4122 #define I2C_OAR1_ADD3 0x00000008U
4123 #define I2C_OAR1_ADD4 0x00000010U
4124 #define I2C_OAR1_ADD5 0x00000020U
4125 #define I2C_OAR1_ADD6 0x00000040U
4126 #define I2C_OAR1_ADD7 0x00000080U
4127 #define I2C_OAR1_ADD8 0x00000100U
4128 #define I2C_OAR1_ADD9 0x00000200U
4130 #define I2C_OAR1_ADDMODE 0x00008000U
4132 /******************* Bit definition for I2C_OAR2 register *******************/
4133 #define I2C_OAR2_ENDUAL 0x00000001U
4134 #define I2C_OAR2_ADD2 0x000000FEU
4136 /******************** Bit definition for I2C_DR register ********************/
4137 #define I2C_DR_DR 0x000000FFU
4139 /******************* Bit definition for I2C_SR1 register ********************/
4140 #define I2C_SR1_SB 0x00000001U
4141 #define I2C_SR1_ADDR 0x00000002U
4142 #define I2C_SR1_BTF 0x00000004U
4143 #define I2C_SR1_ADD10 0x00000008U
4144 #define I2C_SR1_STOPF 0x00000010U
4145 #define I2C_SR1_RXNE 0x00000040U
4146 #define I2C_SR1_TXE 0x00000080U
4147 #define I2C_SR1_BERR 0x00000100U
4148 #define I2C_SR1_ARLO 0x00000200U
4149 #define I2C_SR1_AF 0x00000400U
4150 #define I2C_SR1_OVR 0x00000800U
4151 #define I2C_SR1_PECERR 0x00001000U
4152 #define I2C_SR1_TIMEOUT 0x00004000U
4153 #define I2C_SR1_SMBALERT 0x00008000U
4155 /******************* Bit definition for I2C_SR2 register ********************/
4156 #define I2C_SR2_MSL 0x00000001U
4157 #define I2C_SR2_BUSY 0x00000002U
4158 #define I2C_SR2_TRA 0x00000004U
4159 #define I2C_SR2_GENCALL 0x00000010U
4160 #define I2C_SR2_SMBDEFAULT 0x00000020U
4161 #define I2C_SR2_SMBHOST 0x00000040U
4162 #define I2C_SR2_DUALF 0x00000080U
4163 #define I2C_SR2_PEC 0x0000FF00U
4165 /******************* Bit definition for I2C_CCR register ********************/
4166 #define I2C_CCR_CCR 0x00000FFFU
4167 #define I2C_CCR_DUTY 0x00004000U
4168 #define I2C_CCR_FS 0x00008000U
4170 /****************** Bit definition for I2C_TRISE register *******************/
4171 #define I2C_TRISE_TRISE 0x0000003FU
4173 /****************** Bit definition for I2C_FLTR register *******************/
4174 #define I2C_FLTR_DNF 0x0000000FU
4175 #define I2C_FLTR_ANOFF 0x00000010U
4177 /******************************************************************************/
4178 /* */
4179 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
4180 /* */
4181 /******************************************************************************/
4182 /******************* Bit definition for I2C_CR1 register *******************/
4183 #define FMPI2C_CR1_PE 0x00000001U
4184 #define FMPI2C_CR1_TXIE 0x00000002U
4185 #define FMPI2C_CR1_RXIE 0x00000004U
4186 #define FMPI2C_CR1_ADDRIE 0x00000008U
4187 #define FMPI2C_CR1_NACKIE 0x00000010U
4188 #define FMPI2C_CR1_STOPIE 0x00000020U
4189 #define FMPI2C_CR1_TCIE 0x00000040U
4190 #define FMPI2C_CR1_ERRIE 0x00000080U
4191 #define FMPI2C_CR1_DFN 0x00000F00U
4192 #define FMPI2C_CR1_ANFOFF 0x00001000U
4193 #define FMPI2C_CR1_TXDMAEN 0x00004000U
4194 #define FMPI2C_CR1_RXDMAEN 0x00008000U
4195 #define FMPI2C_CR1_SBC 0x00010000U
4196 #define FMPI2C_CR1_NOSTRETCH 0x00020000U
4197 #define FMPI2C_CR1_GCEN 0x00080000U
4198 #define FMPI2C_CR1_SMBHEN 0x00100000U
4199 #define FMPI2C_CR1_SMBDEN 0x00200000U
4200 #define FMPI2C_CR1_ALERTEN 0x00400000U
4201 #define FMPI2C_CR1_PECEN 0x00800000U
4203 /****************** Bit definition for I2C_CR2 register ********************/
4204 #define FMPI2C_CR2_SADD 0x000003FFU
4205 #define FMPI2C_CR2_RD_WRN 0x00000400U
4206 #define FMPI2C_CR2_ADD10 0x00000800U
4207 #define FMPI2C_CR2_HEAD10R 0x00001000U
4208 #define FMPI2C_CR2_START 0x00002000U
4209 #define FMPI2C_CR2_STOP 0x00004000U
4210 #define FMPI2C_CR2_NACK 0x00008000U
4211 #define FMPI2C_CR2_NBYTES 0x00FF0000U
4212 #define FMPI2C_CR2_RELOAD 0x01000000U
4213 #define FMPI2C_CR2_AUTOEND 0x02000000U
4214 #define FMPI2C_CR2_PECBYTE 0x04000000U
4216 /******************* Bit definition for I2C_OAR1 register ******************/
4217 #define FMPI2C_OAR1_OA1 0x000003FFU
4218 #define FMPI2C_OAR1_OA1MODE 0x00000400U
4219 #define FMPI2C_OAR1_OA1EN 0x00008000U
4221 /******************* Bit definition for I2C_OAR2 register ******************/
4222 #define FMPI2C_OAR2_OA2 0x000000FEU
4223 #define FMPI2C_OAR2_OA2MSK 0x00000700U
4224 #define FMPI2C_OAR2_OA2EN 0x00008000U
4226 /******************* Bit definition for I2C_TIMINGR register *******************/
4227 #define FMPI2C_TIMINGR_SCLL 0x000000FFU
4228 #define FMPI2C_TIMINGR_SCLH 0x0000FF00U
4229 #define FMPI2C_TIMINGR_SDADEL 0x000F0000U
4230 #define FMPI2C_TIMINGR_SCLDEL 0x00F00000U
4231 #define FMPI2C_TIMINGR_PRESC 0xF0000000U
4233 /******************* Bit definition for I2C_TIMEOUTR register *******************/
4234 #define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
4235 #define FMPI2C_TIMEOUTR_TIDLE 0x00001000U
4236 #define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U
4237 #define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
4238 #define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U
4240 /****************** Bit definition for I2C_ISR register *********************/
4241 #define FMPI2C_ISR_TXE 0x00000001U
4242 #define FMPI2C_ISR_TXIS 0x00000002U
4243 #define FMPI2C_ISR_RXNE 0x00000004U
4244 #define FMPI2C_ISR_ADDR 0x00000008U
4245 #define FMPI2C_ISR_NACKF 0x00000010U
4246 #define FMPI2C_ISR_STOPF 0x00000020U
4247 #define FMPI2C_ISR_TC 0x00000040U
4248 #define FMPI2C_ISR_TCR 0x00000080U
4249 #define FMPI2C_ISR_BERR 0x00000100U
4250 #define FMPI2C_ISR_ARLO 0x00000200U
4251 #define FMPI2C_ISR_OVR 0x00000400U
4252 #define FMPI2C_ISR_PECERR 0x00000800U
4253 #define FMPI2C_ISR_TIMEOUT 0x00001000U
4254 #define FMPI2C_ISR_ALERT 0x00002000U
4255 #define FMPI2C_ISR_BUSY 0x00008000U
4256 #define FMPI2C_ISR_DIR 0x00010000U
4257 #define FMPI2C_ISR_ADDCODE 0x00FE0000U
4259 /****************** Bit definition for I2C_ICR register *********************/
4260 #define FMPI2C_ICR_ADDRCF 0x00000008U
4261 #define FMPI2C_ICR_NACKCF 0x00000010U
4262 #define FMPI2C_ICR_STOPCF 0x00000020U
4263 #define FMPI2C_ICR_BERRCF 0x00000100U
4264 #define FMPI2C_ICR_ARLOCF 0x00000200U
4265 #define FMPI2C_ICR_OVRCF 0x00000400U
4266 #define FMPI2C_ICR_PECCF 0x00000800U
4267 #define FMPI2C_ICR_TIMOUTCF 0x00001000U
4268 #define FMPI2C_ICR_ALERTCF 0x00002000U
4270 /****************** Bit definition for I2C_PECR register *********************/
4271 #define FMPI2C_PECR_PEC 0x000000FFU
4273 /****************** Bit definition for I2C_RXDR register *********************/
4274 #define FMPI2C_RXDR_RXDATA 0x000000FFU
4276 /****************** Bit definition for I2C_TXDR register *********************/
4277 #define FMPI2C_TXDR_TXDATA 0x000000FFU
4279 /******************************************************************************/
4280 /* */
4281 /* Independent WATCHDOG */
4282 /* */
4283 /******************************************************************************/
4284 /******************* Bit definition for IWDG_KR register ********************/
4285 #define IWDG_KR_KEY 0xFFFFU
4287 /******************* Bit definition for IWDG_PR register ********************/
4288 #define IWDG_PR_PR 0x07U
4289 #define IWDG_PR_PR_0 0x01U
4290 #define IWDG_PR_PR_1 0x02U
4291 #define IWDG_PR_PR_2 0x04U
4293 /******************* Bit definition for IWDG_RLR register *******************/
4294 #define IWDG_RLR_RL 0x0FFFU
4296 /******************* Bit definition for IWDG_SR register ********************/
4297 #define IWDG_SR_PVU 0x01U
4298 #define IWDG_SR_RVU 0x02U
4301 /******************************************************************************/
4302 /* */
4303 /* Power Control */
4304 /* */
4305 /******************************************************************************/
4306 /******************** Bit definition for PWR_CR register ********************/
4307 #define PWR_CR_LPDS 0x00000001U
4308 #define PWR_CR_PDDS 0x00000002U
4309 #define PWR_CR_CWUF 0x00000004U
4310 #define PWR_CR_CSBF 0x00000008U
4311 #define PWR_CR_PVDE 0x00000010U
4313 #define PWR_CR_PLS 0x000000E0U
4314 #define PWR_CR_PLS_0 0x00000020U
4315 #define PWR_CR_PLS_1 0x00000040U
4316 #define PWR_CR_PLS_2 0x00000080U
4319 #define PWR_CR_PLS_LEV0 0x00000000U
4320 #define PWR_CR_PLS_LEV1 0x00000020U
4321 #define PWR_CR_PLS_LEV2 0x00000040U
4322 #define PWR_CR_PLS_LEV3 0x00000060U
4323 #define PWR_CR_PLS_LEV4 0x00000080U
4324 #define PWR_CR_PLS_LEV5 0x000000A0U
4325 #define PWR_CR_PLS_LEV6 0x000000C0U
4326 #define PWR_CR_PLS_LEV7 0x000000E0U
4328 #define PWR_CR_DBP 0x00000100U
4329 #define PWR_CR_FPDS 0x00000200U
4330 #define PWR_CR_LPLVDS 0x00000400U
4331 #define PWR_CR_MRLVDS 0x00000800U
4332 #define PWR_CR_ADCDC1 0x00002000U
4334 #define PWR_CR_VOS 0x0000C000U
4335 #define PWR_CR_VOS_0 0x00004000U
4336 #define PWR_CR_VOS_1 0x00008000U
4338 #define PWR_CR_FMSSR 0x00100000U
4339 #define PWR_CR_FISSR 0x00200000U
4341 /******************* Bit definition for PWR_CSR register ********************/
4342 #define PWR_CSR_WUF 0x00000001U
4343 #define PWR_CSR_SBF 0x00000002U
4344 #define PWR_CSR_PVDO 0x00000004U
4345 #define PWR_CSR_BRR 0x00000008U
4346 #define PWR_CSR_EWUP 0x00000100U
4347 #define PWR_CSR_BRE 0x00000200U
4348 #define PWR_CSR_VOSRDY 0x00004000U
4349 /******************************************************************************/
4350 /* */
4351 /* QUADSPI */
4352 /* */
4353 /******************************************************************************/
4354 /***************** Bit definition for QUADSPI_CR register *******************/
4355 #define QUADSPI_CR_EN 0x00000001U
4356 #define QUADSPI_CR_ABORT 0x00000002U
4357 #define QUADSPI_CR_DMAEN 0x00000004U
4358 #define QUADSPI_CR_TCEN 0x00000008U
4359 #define QUADSPI_CR_SSHIFT 0x00000010U
4360 #define QUADSPI_CR_DFM 0x00000040U
4361 #define QUADSPI_CR_FSEL 0x00000080U
4362 #define QUADSPI_CR_FTHRES 0x00001F00U
4363 #define QUADSPI_CR_FTHRES_0 0x00000100U
4364 #define QUADSPI_CR_FTHRES_1 0x00000200U
4365 #define QUADSPI_CR_FTHRES_2 0x00000400U
4366 #define QUADSPI_CR_FTHRES_3 0x00000800U
4367 #define QUADSPI_CR_FTHRES_4 0x00001000U
4368 #define QUADSPI_CR_TEIE 0x00010000U
4369 #define QUADSPI_CR_TCIE 0x00020000U
4370 #define QUADSPI_CR_FTIE 0x00040000U
4371 #define QUADSPI_CR_SMIE 0x00080000U
4372 #define QUADSPI_CR_TOIE 0x00100000U
4373 #define QUADSPI_CR_APMS 0x00400000U
4374 #define QUADSPI_CR_PMM 0x00800000U
4375 #define QUADSPI_CR_PRESCALER 0xFF000000U
4376 #define QUADSPI_CR_PRESCALER_0 0x01000000U
4377 #define QUADSPI_CR_PRESCALER_1 0x02000000U
4378 #define QUADSPI_CR_PRESCALER_2 0x04000000U
4379 #define QUADSPI_CR_PRESCALER_3 0x08000000U
4380 #define QUADSPI_CR_PRESCALER_4 0x10000000U
4381 #define QUADSPI_CR_PRESCALER_5 0x20000000U
4382 #define QUADSPI_CR_PRESCALER_6 0x40000000U
4383 #define QUADSPI_CR_PRESCALER_7 0x80000000U
4385 /***************** Bit definition for QUADSPI_DCR register ******************/
4386 #define QUADSPI_DCR_CKMODE 0x00000001U
4387 #define QUADSPI_DCR_CSHT 0x00000700U
4388 #define QUADSPI_DCR_CSHT_0 0x00000100U
4389 #define QUADSPI_DCR_CSHT_1 0x00000200U
4390 #define QUADSPI_DCR_CSHT_2 0x00000400U
4391 #define QUADSPI_DCR_FSIZE 0x001F0000U
4392 #define QUADSPI_DCR_FSIZE_0 0x00010000U
4393 #define QUADSPI_DCR_FSIZE_1 0x00020000U
4394 #define QUADSPI_DCR_FSIZE_2 0x00040000U
4395 #define QUADSPI_DCR_FSIZE_3 0x00080000U
4396 #define QUADSPI_DCR_FSIZE_4 0x00100000U
4398 /****************** Bit definition for QUADSPI_SR register *******************/
4399 #define QUADSPI_SR_TEF 0x00000001U
4400 #define QUADSPI_SR_TCF 0x00000002U
4401 #define QUADSPI_SR_FTF 0x00000004U
4402 #define QUADSPI_SR_SMF 0x00000008U
4403 #define QUADSPI_SR_TOF 0x00000010U
4404 #define QUADSPI_SR_BUSY 0x00000020U
4405 #define QUADSPI_SR_FLEVEL 0x00003F00U
4406 #define QUADSPI_SR_FLEVEL_0 0x00000100U
4407 #define QUADSPI_SR_FLEVEL_1 0x00000200U
4408 #define QUADSPI_SR_FLEVEL_2 0x00000400U
4409 #define QUADSPI_SR_FLEVEL_3 0x00000800U
4410 #define QUADSPI_SR_FLEVEL_4 0x00001000U
4411 #define QUADSPI_SR_FLEVEL_5 0x00002000U
4413 /****************** Bit definition for QUADSPI_FCR register ******************/
4414 #define QUADSPI_FCR_CTEF 0x00000001U
4415 #define QUADSPI_FCR_CTCF 0x00000002U
4416 #define QUADSPI_FCR_CSMF 0x00000008U
4417 #define QUADSPI_FCR_CTOF 0x00000010U
4419 /****************** Bit definition for QUADSPI_DLR register ******************/
4420 #define QUADSPI_DLR_DL 0xFFFFFFFFU
4422 /****************** Bit definition for QUADSPI_CCR register ******************/
4423 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
4424 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
4425 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
4426 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
4427 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
4428 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
4429 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
4430 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
4431 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
4432 #define QUADSPI_CCR_IMODE 0x00000300U
4433 #define QUADSPI_CCR_IMODE_0 0x00000100U
4434 #define QUADSPI_CCR_IMODE_1 0x00000200U
4435 #define QUADSPI_CCR_ADMODE 0x00000C00U
4436 #define QUADSPI_CCR_ADMODE_0 0x00000400U
4437 #define QUADSPI_CCR_ADMODE_1 0x00000800U
4438 #define QUADSPI_CCR_ADSIZE 0x00003000U
4439 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
4440 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
4441 #define QUADSPI_CCR_ABMODE 0x0000C000U
4442 #define QUADSPI_CCR_ABMODE_0 0x00004000U
4443 #define QUADSPI_CCR_ABMODE_1 0x00008000U
4444 #define QUADSPI_CCR_ABSIZE 0x00030000U
4445 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
4446 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
4447 #define QUADSPI_CCR_DCYC 0x007C0000U
4448 #define QUADSPI_CCR_DCYC_0 0x00040000U
4449 #define QUADSPI_CCR_DCYC_1 0x00080000U
4450 #define QUADSPI_CCR_DCYC_2 0x00100000U
4451 #define QUADSPI_CCR_DCYC_3 0x00200000U
4452 #define QUADSPI_CCR_DCYC_4 0x00400000U
4453 #define QUADSPI_CCR_DMODE 0x03000000U
4454 #define QUADSPI_CCR_DMODE_0 0x01000000U
4455 #define QUADSPI_CCR_DMODE_1 0x02000000U
4456 #define QUADSPI_CCR_FMODE 0x0C000000U
4457 #define QUADSPI_CCR_FMODE_0 0x04000000U
4458 #define QUADSPI_CCR_FMODE_1 0x08000000U
4459 #define QUADSPI_CCR_SIOO 0x10000000U
4460 #define QUADSPI_CCR_DHHC 0x40000000U
4461 #define QUADSPI_CCR_DDRM 0x80000000U
4462 /****************** Bit definition for QUADSPI_AR register *******************/
4463 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
4465 /****************** Bit definition for QUADSPI_ABR register ******************/
4466 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
4468 /****************** Bit definition for QUADSPI_DR register *******************/
4469 #define QUADSPI_DR_DATA 0xFFFFFFFFU
4471 /****************** Bit definition for QUADSPI_PSMKR register ****************/
4472 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
4474 /****************** Bit definition for QUADSPI_PSMAR register ****************/
4475 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
4477 /****************** Bit definition for QUADSPI_PIR register *****************/
4478 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
4480 /****************** Bit definition for QUADSPI_LPTR register *****************/
4481 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
4483 /******************************************************************************/
4484 /* */
4485 /* Reset and Clock Control */
4486 /* */
4487 /******************************************************************************/
4488 /******************** Bit definition for RCC_CR register ********************/
4489 #define RCC_CR_HSION 0x00000001U
4490 #define RCC_CR_HSIRDY 0x00000002U
4491 
4492 #define RCC_CR_HSITRIM 0x000000F8U
4493 #define RCC_CR_HSITRIM_0 0x00000008U
4494 #define RCC_CR_HSITRIM_1 0x00000010U
4495 #define RCC_CR_HSITRIM_2 0x00000020U
4496 #define RCC_CR_HSITRIM_3 0x00000040U
4497 #define RCC_CR_HSITRIM_4 0x00000080U
4499 #define RCC_CR_HSICAL 0x0000FF00U
4500 #define RCC_CR_HSICAL_0 0x00000100U
4501 #define RCC_CR_HSICAL_1 0x00000200U
4502 #define RCC_CR_HSICAL_2 0x00000400U
4503 #define RCC_CR_HSICAL_3 0x00000800U
4504 #define RCC_CR_HSICAL_4 0x00001000U
4505 #define RCC_CR_HSICAL_5 0x00002000U
4506 #define RCC_CR_HSICAL_6 0x00004000U
4507 #define RCC_CR_HSICAL_7 0x00008000U
4509 #define RCC_CR_HSEON 0x00010000U
4510 #define RCC_CR_HSERDY 0x00020000U
4511 #define RCC_CR_HSEBYP 0x00040000U
4512 #define RCC_CR_CSSON 0x00080000U
4513 #define RCC_CR_PLLON 0x01000000U
4514 #define RCC_CR_PLLRDY 0x02000000U
4515 #define RCC_CR_PLLI2SON 0x04000000U
4516 #define RCC_CR_PLLI2SRDY 0x08000000U
4517 
4518 /******************** Bit definition for RCC_PLLCFGR register ***************/
4519 #define RCC_PLLCFGR_PLLM 0x0000003FU
4520 #define RCC_PLLCFGR_PLLM_0 0x00000001U
4521 #define RCC_PLLCFGR_PLLM_1 0x00000002U
4522 #define RCC_PLLCFGR_PLLM_2 0x00000004U
4523 #define RCC_PLLCFGR_PLLM_3 0x00000008U
4524 #define RCC_PLLCFGR_PLLM_4 0x00000010U
4525 #define RCC_PLLCFGR_PLLM_5 0x00000020U
4526 
4527 #define RCC_PLLCFGR_PLLN 0x00007FC0U
4528 #define RCC_PLLCFGR_PLLN_0 0x00000040U
4529 #define RCC_PLLCFGR_PLLN_1 0x00000080U
4530 #define RCC_PLLCFGR_PLLN_2 0x00000100U
4531 #define RCC_PLLCFGR_PLLN_3 0x00000200U
4532 #define RCC_PLLCFGR_PLLN_4 0x00000400U
4533 #define RCC_PLLCFGR_PLLN_5 0x00000800U
4534 #define RCC_PLLCFGR_PLLN_6 0x00001000U
4535 #define RCC_PLLCFGR_PLLN_7 0x00002000U
4536 #define RCC_PLLCFGR_PLLN_8 0x00004000U
4537 
4538 #define RCC_PLLCFGR_PLLP 0x00030000U
4539 #define RCC_PLLCFGR_PLLP_0 0x00010000U
4540 #define RCC_PLLCFGR_PLLP_1 0x00020000U
4541 
4542 #define RCC_PLLCFGR_PLLSRC 0x00400000U
4543 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
4544 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
4545 
4546 #define RCC_PLLCFGR_PLLQ 0x0F000000U
4547 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
4548 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
4549 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
4550 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
4551 
4552 #define RCC_PLLCFGR_PLLR 0x70000000U
4553 #define RCC_PLLCFGR_PLLR_0 0x10000000U
4554 #define RCC_PLLCFGR_PLLR_1 0x20000000U
4555 #define RCC_PLLCFGR_PLLR_2 0x40000000U
4556 
4557 /******************** Bit definition for RCC_CFGR register ******************/
4559 #define RCC_CFGR_SW 0x00000003U
4560 #define RCC_CFGR_SW_0 0x00000001U
4561 #define RCC_CFGR_SW_1 0x00000002U
4563 #define RCC_CFGR_SW_HSI 0x00000000U
4564 #define RCC_CFGR_SW_HSE 0x00000001U
4565 #define RCC_CFGR_SW_PLL 0x00000002U
4566 #define RCC_CFGR_SW_PLLR 0x00000003U
4569 #define RCC_CFGR_SWS 0x0000000CU
4570 #define RCC_CFGR_SWS_0 0x00000004U
4571 #define RCC_CFGR_SWS_1 0x00000008U
4573 #define RCC_CFGR_SWS_HSI 0x00000000U
4574 #define RCC_CFGR_SWS_HSE 0x00000004U
4575 #define RCC_CFGR_SWS_PLL 0x00000008U
4576 #define RCC_CFGR_SWS_PLLR 0x0000000CU
4579 #define RCC_CFGR_HPRE 0x000000F0U
4580 #define RCC_CFGR_HPRE_0 0x00000010U
4581 #define RCC_CFGR_HPRE_1 0x00000020U
4582 #define RCC_CFGR_HPRE_2 0x00000040U
4583 #define RCC_CFGR_HPRE_3 0x00000080U
4585 #define RCC_CFGR_HPRE_DIV1 0x00000000U
4586 #define RCC_CFGR_HPRE_DIV2 0x00000080U
4587 #define RCC_CFGR_HPRE_DIV4 0x00000090U
4588 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
4589 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
4590 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
4591 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
4592 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
4593 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
4596 #define RCC_CFGR_PPRE1 0x00001C00U
4597 #define RCC_CFGR_PPRE1_0 0x00000400U
4598 #define RCC_CFGR_PPRE1_1 0x00000800U
4599 #define RCC_CFGR_PPRE1_2 0x00001000U
4601 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
4602 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
4603 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
4604 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
4605 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
4608 #define RCC_CFGR_PPRE2 0x0000E000U
4609 #define RCC_CFGR_PPRE2_0 0x00002000U
4610 #define RCC_CFGR_PPRE2_1 0x00004000U
4611 #define RCC_CFGR_PPRE2_2 0x00008000U
4613 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
4614 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
4615 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
4616 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
4617 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
4620 #define RCC_CFGR_RTCPRE 0x001F0000U
4621 #define RCC_CFGR_RTCPRE_0 0x00010000U
4622 #define RCC_CFGR_RTCPRE_1 0x00020000U
4623 #define RCC_CFGR_RTCPRE_2 0x00040000U
4624 #define RCC_CFGR_RTCPRE_3 0x00080000U
4625 #define RCC_CFGR_RTCPRE_4 0x00100000U
4626 
4628 #define RCC_CFGR_MCO1 0x00600000U
4629 #define RCC_CFGR_MCO1_0 0x00200000U
4630 #define RCC_CFGR_MCO1_1 0x00400000U
4631 
4632 #define RCC_CFGR_MCO1PRE 0x07000000U
4633 #define RCC_CFGR_MCO1PRE_0 0x01000000U
4634 #define RCC_CFGR_MCO1PRE_1 0x02000000U
4635 #define RCC_CFGR_MCO1PRE_2 0x04000000U
4636 
4637 #define RCC_CFGR_MCO2PRE 0x38000000U
4638 #define RCC_CFGR_MCO2PRE_0 0x08000000U
4639 #define RCC_CFGR_MCO2PRE_1 0x10000000U
4640 #define RCC_CFGR_MCO2PRE_2 0x20000000U
4641 
4642 #define RCC_CFGR_MCO2 0xC0000000U
4643 #define RCC_CFGR_MCO2_0 0x40000000U
4644 #define RCC_CFGR_MCO2_1 0x80000000U
4645 
4646 /******************** Bit definition for RCC_CIR register *******************/
4647 #define RCC_CIR_LSIRDYF 0x00000001U
4648 #define RCC_CIR_LSERDYF 0x00000002U
4649 #define RCC_CIR_HSIRDYF 0x00000004U
4650 #define RCC_CIR_HSERDYF 0x00000008U
4651 #define RCC_CIR_PLLRDYF 0x00000010U
4652 #define RCC_CIR_PLLI2SRDYF 0x00000020U
4653 
4654 #define RCC_CIR_CSSF 0x00000080U
4655 #define RCC_CIR_LSIRDYIE 0x00000100U
4656 #define RCC_CIR_LSERDYIE 0x00000200U
4657 #define RCC_CIR_HSIRDYIE 0x00000400U
4658 #define RCC_CIR_HSERDYIE 0x00000800U
4659 #define RCC_CIR_PLLRDYIE 0x00001000U
4660 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
4661 
4662 #define RCC_CIR_LSIRDYC 0x00010000U
4663 #define RCC_CIR_LSERDYC 0x00020000U
4664 #define RCC_CIR_HSIRDYC 0x00040000U
4665 #define RCC_CIR_HSERDYC 0x00080000U
4666 #define RCC_CIR_PLLRDYC 0x00100000U
4667 #define RCC_CIR_PLLI2SRDYC 0x00200000U
4668 
4669 #define RCC_CIR_CSSC 0x00800000U
4670 
4671 /******************** Bit definition for RCC_AHB1RSTR register **************/
4672 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
4673 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
4674 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
4675 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
4676 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
4677 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
4678 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
4679 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
4680 #define RCC_AHB1RSTR_CRCRST 0x00001000U
4681 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
4682 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
4683 
4684 /******************** Bit definition for RCC_AHB2RSTR register **************/
4685 #define RCC_AHB2RSTR_RNGRST 0x00000040U
4686 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
4687 
4688 /******************** Bit definition for RCC_AHB3RSTR register **************/
4689 #define RCC_AHB3RSTR_FSMCRST 0x00000001U
4690 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
4691 
4692 /******************** Bit definition for RCC_APB1RSTR register **************/
4693 #define RCC_APB1RSTR_TIM2RST 0x00000001U
4694 #define RCC_APB1RSTR_TIM3RST 0x00000002U
4695 #define RCC_APB1RSTR_TIM4RST 0x00000004U
4696 #define RCC_APB1RSTR_TIM5RST 0x00000008U
4697 #define RCC_APB1RSTR_TIM6RST 0x00000010U
4698 #define RCC_APB1RSTR_TIM7RST 0x00000020U
4699 #define RCC_APB1RSTR_TIM12RST 0x00000040U
4700 #define RCC_APB1RSTR_TIM13RST 0x00000080U
4701 #define RCC_APB1RSTR_TIM14RST 0x00000100U
4702 #define RCC_APB1RSTR_WWDGRST 0x00000800U
4703 #define RCC_APB1RSTR_SPI2RST 0x00004000U
4704 #define RCC_APB1RSTR_SPI3RST 0x00008000U
4705 #define RCC_APB1RSTR_USART2RST 0x00020000U
4706 #define RCC_APB1RSTR_USART3RST 0x00040000U
4707 #define RCC_APB1RSTR_I2C1RST 0x00200000U
4708 #define RCC_APB1RSTR_I2C2RST 0x00400000U
4709 #define RCC_APB1RSTR_I2C3RST 0x00800000U
4710 #define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
4711 #define RCC_APB1RSTR_CAN1RST 0x02000000U
4712 #define RCC_APB1RSTR_CAN2RST 0x04000000U
4713 #define RCC_APB1RSTR_PWRRST 0x10000000U
4714 
4715 /******************** Bit definition for RCC_APB2RSTR register **************/
4716 #define RCC_APB2RSTR_TIM1RST 0x00000001U
4717 #define RCC_APB2RSTR_TIM8RST 0x00000002U
4718 #define RCC_APB2RSTR_USART1RST 0x00000010U
4719 #define RCC_APB2RSTR_USART6RST 0x00000020U
4720 #define RCC_APB2RSTR_ADCRST 0x00000100U
4721 #define RCC_APB2RSTR_SDIORST 0x00000800U
4722 #define RCC_APB2RSTR_SPI1RST 0x00001000U
4723 #define RCC_APB2RSTR_SPI4RST 0x00002000U
4724 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
4725 #define RCC_APB2RSTR_TIM9RST 0x00010000U
4726 #define RCC_APB2RSTR_TIM10RST 0x00020000U
4727 #define RCC_APB2RSTR_TIM11RST 0x00040000U
4728 #define RCC_APB2RSTR_SPI5RST 0x00100000U
4729 #define RCC_APB2RSTR_DFSDM1RST 0x01000000U
4730 
4731 /******************** Bit definition for RCC_AHB1ENR register ***************/
4732 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
4733 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
4734 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
4735 #define RCC_AHB1ENR_GPIODEN 0x00000008U
4736 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
4737 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
4738 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
4739 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
4740 #define RCC_AHB1ENR_CRCEN 0x00001000U
4741 #define RCC_AHB1ENR_DMA1EN 0x00200000U
4742 #define RCC_AHB1ENR_DMA2EN 0x00400000U
4743 
4744 /******************** Bit definition for RCC_AHB2ENR register ***************/
4745 #define RCC_AHB2ENR_RNGEN 0x00000040U
4746 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
4747 
4748 /******************** Bit definition for RCC_AHB3ENR register ***************/
4749 #define RCC_AHB3ENR_FSMCEN 0x00000001U
4750 #define RCC_AHB3ENR_QSPIEN 0x00000002U
4751 
4752 /******************** Bit definition for RCC_APB1ENR register ***************/
4753 #define RCC_APB1ENR_TIM2EN 0x00000001U
4754 #define RCC_APB1ENR_TIM3EN 0x00000002U
4755 #define RCC_APB1ENR_TIM4EN 0x00000004U
4756 #define RCC_APB1ENR_TIM5EN 0x00000008U
4757 #define RCC_APB1ENR_TIM6EN 0x00000010U
4758 #define RCC_APB1ENR_TIM7EN 0x00000020U
4759 #define RCC_APB1ENR_TIM12EN 0x00000040U
4760 #define RCC_APB1ENR_TIM13EN 0x00000080U
4761 #define RCC_APB1ENR_TIM14EN 0x00000100U
4762 #define RCC_APB1ENR_RTCAPBEN 0x00000400U
4763 #define RCC_APB1ENR_WWDGEN 0x00000800U
4764 #define RCC_APB1ENR_SPI2EN 0x00004000U
4765 #define RCC_APB1ENR_SPI3EN 0x00008000U
4766 #define RCC_APB1ENR_USART2EN 0x00020000U
4767 #define RCC_APB1ENR_USART3EN 0x00040000U
4768 #define RCC_APB1ENR_I2C1EN 0x00200000U
4769 #define RCC_APB1ENR_I2C2EN 0x00400000U
4770 #define RCC_APB1ENR_I2C3EN 0x00800000U
4771 #define RCC_APB1ENR_FMPI2C1EN 0x01000000U
4772 #define RCC_APB1ENR_CAN1EN 0x02000000U
4773 #define RCC_APB1ENR_CAN2EN 0x04000000U
4774 #define RCC_APB1ENR_PWREN 0x10000000U
4775 
4776 /******************** Bit definition for RCC_APB2ENR register ***************/
4777 #define RCC_APB2ENR_TIM1EN 0x00000001U
4778 #define RCC_APB2ENR_TIM8EN 0x00000002U
4779 #define RCC_APB2ENR_USART1EN 0x00000010U
4780 #define RCC_APB2ENR_USART6EN 0x00000020U
4781 #define RCC_APB2ENR_ADC1EN 0x00000100U
4782 #define RCC_APB2ENR_SDIOEN 0x00000800U
4783 #define RCC_APB2ENR_SPI1EN 0x00001000U
4784 #define RCC_APB2ENR_SPI4EN 0x00002000U
4785 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
4786 #define RCC_APB2ENR_EXTITEN 0x00008000U
4787 #define RCC_APB2ENR_TIM9EN 0x00010000U
4788 #define RCC_APB2ENR_TIM10EN 0x00020000U
4789 #define RCC_APB2ENR_TIM11EN 0x00040000U
4790 #define RCC_APB2ENR_SPI5EN 0x00100000U
4791 #define RCC_APB2ENR_DFSDM1EN 0x01000000U
4792 /******************** Bit definition for RCC_AHB1LPENR register *************/
4793 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
4794 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
4795 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
4796 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
4797 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
4798 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
4799 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
4800 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
4801 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
4802 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
4803 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
4804 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
4805 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
4806 
4807 /******************** Bit definition for RCC_AHB2LPENR register *************/
4808 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
4809 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
4810 
4811 /******************** Bit definition for RCC_AHB3LPENR register *************/
4812 #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
4813 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
4814 
4815 /******************** Bit definition for RCC_APB1LPENR register *************/
4816 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
4817 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
4818 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
4819 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
4820 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
4821 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
4822 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
4823 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
4824 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
4825 #define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
4826 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
4827 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
4828 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
4829 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
4830 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
4831 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
4832 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
4833 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
4834 #define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
4835 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
4836 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
4837 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
4838 
4839 /******************** Bit definition for RCC_APB2LPENR register *************/
4840 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
4841 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
4842 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
4843 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
4844 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
4845 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
4846 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
4847 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
4848 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
4849 #define RCC_APB2LPENR_EXTITLPEN 0x00008000U
4850 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
4851 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
4852 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
4853 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
4854 #define RCC_APB2LPENR_DFSDM1LPEN 0x01000000U
4855 
4856 /******************** Bit definition for RCC_BDCR register ******************/
4857 #define RCC_BDCR_LSEON 0x00000001U
4858 #define RCC_BDCR_LSERDY 0x00000002U
4859 #define RCC_BDCR_LSEBYP 0x00000004U
4860 #define RCC_BDCR_LSEMOD 0x00000008U
4861 
4862 #define RCC_BDCR_RTCSEL 0x00000300U
4863 #define RCC_BDCR_RTCSEL_0 0x00000100U
4864 #define RCC_BDCR_RTCSEL_1 0x00000200U
4865 
4866 #define RCC_BDCR_RTCEN 0x00008000U
4867 #define RCC_BDCR_BDRST 0x00010000U
4868 
4869 /******************** Bit definition for RCC_CSR register *******************/
4870 #define RCC_CSR_LSION 0x00000001U
4871 #define RCC_CSR_LSIRDY 0x00000002U
4872 #define RCC_CSR_RMVF 0x01000000U
4873 #define RCC_CSR_PADRSTF 0x04000000U
4874 #define RCC_CSR_PORRSTF 0x08000000U
4875 #define RCC_CSR_SFTRSTF 0x10000000U
4876 #define RCC_CSR_WDGRSTF 0x20000000U
4877 #define RCC_CSR_WWDGRSTF 0x40000000U
4878 #define RCC_CSR_LPWRRSTF 0x80000000U
4879 
4880 /******************** Bit definition for RCC_SSCGR register *****************/
4881 #define RCC_SSCGR_MODPER 0x00001FFFU
4882 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
4883 #define RCC_SSCGR_SPREADSEL 0x40000000U
4884 #define RCC_SSCGR_SSCGEN 0x80000000U
4885 
4886 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
4887 #define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
4888 #define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
4889 #define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
4890 #define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
4891 #define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
4892 #define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
4893 #define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
4894 
4895 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
4896 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
4897 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
4898 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
4899 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
4900 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
4901 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
4902 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
4903 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
4904 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
4905 
4906 #define RCC_PLLI2SCFGR_PLLI2SSRC 0x00400000U
4907 
4908 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
4909 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
4910 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
4911 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
4912 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
4913 
4914 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
4915 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
4916 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
4917 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
4918 
4919 /******************** Bit definition for RCC_DCKCFGR register ****************/
4920 #define RCC_DCKCFGR_CKDFSDM1ASEL 0x00008000U
4921 #define RCC_DCKCFGR_TIMPRE 0x01000000U
4922 
4923 #define RCC_DCKCFGR_I2S1SRC 0x06000000U
4924 #define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
4925 #define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
4926 
4927 #define RCC_DCKCFGR_I2S2SRC 0x18000000U
4928 #define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
4929 #define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
4930 
4931 #define RCC_DCKCFGR_CKDFSDM1SEL 0x80000000U
4932 
4933 /******************** Bit definition for RCC_CKGATENR register ***************/
4934 #define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
4935 #define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
4936 #define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
4937 #define RCC_CKGATENR_SPARE_CKEN 0x00000008U
4938 #define RCC_CKGATENR_SRAM_CKEN 0x00000010U
4939 #define RCC_CKGATENR_FLITF_CKEN 0x00000020U
4940 #define RCC_CKGATENR_RCC_CKEN 0x00000040U
4941 #define RCC_CKGATENR_RCC_EVTCTL 0x00000080U
4942 
4943 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
4944 #define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
4945 #define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
4946 #define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
4947 
4948 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
4949 #define RCC_DCKCFGR2_SDIOSEL 0x10000000U
4950 
4951 /******************************************************************************/
4952 /* */
4953 /* RNG */
4954 /* */
4955 /******************************************************************************/
4956 /******************** Bits definition for RNG_CR register *******************/
4957 #define RNG_CR_RNGEN 0x00000004U
4958 #define RNG_CR_IE 0x00000008U
4959 
4960 /******************** Bits definition for RNG_SR register *******************/
4961 #define RNG_SR_DRDY 0x00000001U
4962 #define RNG_SR_CECS 0x00000002U
4963 #define RNG_SR_SECS 0x00000004U
4964 #define RNG_SR_CEIS 0x00000020U
4965 #define RNG_SR_SEIS 0x00000040U
4966 
4967 /******************************************************************************/
4968 /* */
4969 /* Real-Time Clock (RTC) */
4970 /* */
4971 /******************************************************************************/
4972 /******************** Bits definition for RTC_TR register *******************/
4973 #define RTC_TR_PM 0x00400000U
4974 #define RTC_TR_HT 0x00300000U
4975 #define RTC_TR_HT_0 0x00100000U
4976 #define RTC_TR_HT_1 0x00200000U
4977 #define RTC_TR_HU 0x000F0000U
4978 #define RTC_TR_HU_0 0x00010000U
4979 #define RTC_TR_HU_1 0x00020000U
4980 #define RTC_TR_HU_2 0x00040000U
4981 #define RTC_TR_HU_3 0x00080000U
4982 #define RTC_TR_MNT 0x00007000U
4983 #define RTC_TR_MNT_0 0x00001000U
4984 #define RTC_TR_MNT_1 0x00002000U
4985 #define RTC_TR_MNT_2 0x00004000U
4986 #define RTC_TR_MNU 0x00000F00U
4987 #define RTC_TR_MNU_0 0x00000100U
4988 #define RTC_TR_MNU_1 0x00000200U
4989 #define RTC_TR_MNU_2 0x00000400U
4990 #define RTC_TR_MNU_3 0x00000800U
4991 #define RTC_TR_ST 0x00000070U
4992 #define RTC_TR_ST_0 0x00000010U
4993 #define RTC_TR_ST_1 0x00000020U
4994 #define RTC_TR_ST_2 0x00000040U
4995 #define RTC_TR_SU 0x0000000FU
4996 #define RTC_TR_SU_0 0x00000001U
4997 #define RTC_TR_SU_1 0x00000002U
4998 #define RTC_TR_SU_2 0x00000004U
4999 #define RTC_TR_SU_3 0x00000008U
5000 
5001 /******************** Bits definition for RTC_DR register *******************/
5002 #define RTC_DR_YT 0x00F00000U
5003 #define RTC_DR_YT_0 0x00100000U
5004 #define RTC_DR_YT_1 0x00200000U
5005 #define RTC_DR_YT_2 0x00400000U
5006 #define RTC_DR_YT_3 0x00800000U
5007 #define RTC_DR_YU 0x000F0000U
5008 #define RTC_DR_YU_0 0x00010000U
5009 #define RTC_DR_YU_1 0x00020000U
5010 #define RTC_DR_YU_2 0x00040000U
5011 #define RTC_DR_YU_3 0x00080000U
5012 #define RTC_DR_WDU 0x0000E000U
5013 #define RTC_DR_WDU_0 0x00002000U
5014 #define RTC_DR_WDU_1 0x00004000U
5015 #define RTC_DR_WDU_2 0x00008000U
5016 #define RTC_DR_MT 0x00001000U
5017 #define RTC_DR_MU 0x00000F00U
5018 #define RTC_DR_MU_0 0x00000100U
5019 #define RTC_DR_MU_1 0x00000200U
5020 #define RTC_DR_MU_2 0x00000400U
5021 #define RTC_DR_MU_3 0x00000800U
5022 #define RTC_DR_DT 0x00000030U
5023 #define RTC_DR_DT_0 0x00000010U
5024 #define RTC_DR_DT_1 0x00000020U
5025 #define RTC_DR_DU 0x0000000FU
5026 #define RTC_DR_DU_0 0x00000001U
5027 #define RTC_DR_DU_1 0x00000002U
5028 #define RTC_DR_DU_2 0x00000004U
5029 #define RTC_DR_DU_3 0x00000008U
5030 
5031 /******************** Bits definition for RTC_CR register *******************/
5032 #define RTC_CR_COE 0x00800000U
5033 #define RTC_CR_OSEL 0x00600000U
5034 #define RTC_CR_OSEL_0 0x00200000U
5035 #define RTC_CR_OSEL_1 0x00400000U
5036 #define RTC_CR_POL 0x00100000U
5037 #define RTC_CR_COSEL 0x00080000U
5038 #define RTC_CR_BCK 0x00040000U
5039 #define RTC_CR_SUB1H 0x00020000U
5040 #define RTC_CR_ADD1H 0x00010000U
5041 #define RTC_CR_TSIE 0x00008000U
5042 #define RTC_CR_WUTIE 0x00004000U
5043 #define RTC_CR_ALRBIE 0x00002000U
5044 #define RTC_CR_ALRAIE 0x00001000U
5045 #define RTC_CR_TSE 0x00000800U
5046 #define RTC_CR_WUTE 0x00000400U
5047 #define RTC_CR_ALRBE 0x00000200U
5048 #define RTC_CR_ALRAE 0x00000100U
5049 #define RTC_CR_DCE 0x00000080U
5050 #define RTC_CR_FMT 0x00000040U
5051 #define RTC_CR_BYPSHAD 0x00000020U
5052 #define RTC_CR_REFCKON 0x00000010U
5053 #define RTC_CR_TSEDGE 0x00000008U
5054 #define RTC_CR_WUCKSEL 0x00000007U
5055 #define RTC_CR_WUCKSEL_0 0x00000001U
5056 #define RTC_CR_WUCKSEL_1 0x00000002U
5057 #define RTC_CR_WUCKSEL_2 0x00000004U
5058 
5059 /******************** Bits definition for RTC_ISR register ******************/
5060 #define RTC_ISR_RECALPF 0x00010000U
5061 #define RTC_ISR_TAMP1F 0x00002000U
5062 #define RTC_ISR_TAMP2F 0x00004000U
5063 #define RTC_ISR_TSOVF 0x00001000U
5064 #define RTC_ISR_TSF 0x00000800U
5065 #define RTC_ISR_WUTF 0x00000400U
5066 #define RTC_ISR_ALRBF 0x00000200U
5067 #define RTC_ISR_ALRAF 0x00000100U
5068 #define RTC_ISR_INIT 0x00000080U
5069 #define RTC_ISR_INITF 0x00000040U
5070 #define RTC_ISR_RSF 0x00000020U
5071 #define RTC_ISR_INITS 0x00000010U
5072 #define RTC_ISR_SHPF 0x00000008U
5073 #define RTC_ISR_WUTWF 0x00000004U
5074 #define RTC_ISR_ALRBWF 0x00000002U
5075 #define RTC_ISR_ALRAWF 0x00000001U
5076 
5077 /******************** Bits definition for RTC_PRER register *****************/
5078 #define RTC_PRER_PREDIV_A 0x007F0000U
5079 #define RTC_PRER_PREDIV_S 0x00007FFFU
5080 
5081 /******************** Bits definition for RTC_WUTR register *****************/
5082 #define RTC_WUTR_WUT 0x0000FFFFU
5083 
5084 /******************** Bits definition for RTC_CALIBR register ***************/
5085 #define RTC_CALIBR_DCS 0x00000080U
5086 #define RTC_CALIBR_DC 0x0000001FU
5087 
5088 /******************** Bits definition for RTC_ALRMAR register ***************/
5089 #define RTC_ALRMAR_MSK4 0x80000000U
5090 #define RTC_ALRMAR_WDSEL 0x40000000U
5091 #define RTC_ALRMAR_DT 0x30000000U
5092 #define RTC_ALRMAR_DT_0 0x10000000U
5093 #define RTC_ALRMAR_DT_1 0x20000000U
5094 #define RTC_ALRMAR_DU 0x0F000000U
5095 #define RTC_ALRMAR_DU_0 0x01000000U
5096 #define RTC_ALRMAR_DU_1 0x02000000U
5097 #define RTC_ALRMAR_DU_2 0x04000000U
5098 #define RTC_ALRMAR_DU_3 0x08000000U
5099 #define RTC_ALRMAR_MSK3 0x00800000U
5100 #define RTC_ALRMAR_PM 0x00400000U
5101 #define RTC_ALRMAR_HT 0x00300000U
5102 #define RTC_ALRMAR_HT_0 0x00100000U
5103 #define RTC_ALRMAR_HT_1 0x00200000U
5104 #define RTC_ALRMAR_HU 0x000F0000U
5105 #define RTC_ALRMAR_HU_0 0x00010000U
5106 #define RTC_ALRMAR_HU_1 0x00020000U
5107 #define RTC_ALRMAR_HU_2 0x00040000U
5108 #define RTC_ALRMAR_HU_3 0x00080000U
5109 #define RTC_ALRMAR_MSK2 0x00008000U
5110 #define RTC_ALRMAR_MNT 0x00007000U
5111 #define RTC_ALRMAR_MNT_0 0x00001000U
5112 #define RTC_ALRMAR_MNT_1 0x00002000U
5113 #define RTC_ALRMAR_MNT_2 0x00004000U
5114 #define RTC_ALRMAR_MNU 0x00000F00U
5115 #define RTC_ALRMAR_MNU_0 0x00000100U
5116 #define RTC_ALRMAR_MNU_1 0x00000200U
5117 #define RTC_ALRMAR_MNU_2 0x00000400U
5118 #define RTC_ALRMAR_MNU_3 0x00000800U
5119 #define RTC_ALRMAR_MSK1 0x00000080U
5120 #define RTC_ALRMAR_ST 0x00000070U
5121 #define RTC_ALRMAR_ST_0 0x00000010U
5122 #define RTC_ALRMAR_ST_1 0x00000020U
5123 #define RTC_ALRMAR_ST_2 0x00000040U
5124 #define RTC_ALRMAR_SU 0x0000000FU
5125 #define RTC_ALRMAR_SU_0 0x00000001U
5126 #define RTC_ALRMAR_SU_1 0x00000002U
5127 #define RTC_ALRMAR_SU_2 0x00000004U
5128 #define RTC_ALRMAR_SU_3 0x00000008U
5129 
5130 /******************** Bits definition for RTC_ALRMBR register ***************/
5131 #define RTC_ALRMBR_MSK4 0x80000000U
5132 #define RTC_ALRMBR_WDSEL 0x40000000U
5133 #define RTC_ALRMBR_DT 0x30000000U
5134 #define RTC_ALRMBR_DT_0 0x10000000U
5135 #define RTC_ALRMBR_DT_1 0x20000000U
5136 #define RTC_ALRMBR_DU 0x0F000000U
5137 #define RTC_ALRMBR_DU_0 0x01000000U
5138 #define RTC_ALRMBR_DU_1 0x02000000U
5139 #define RTC_ALRMBR_DU_2 0x04000000U
5140 #define RTC_ALRMBR_DU_3 0x08000000U
5141 #define RTC_ALRMBR_MSK3 0x00800000U
5142 #define RTC_ALRMBR_PM 0x00400000U
5143 #define RTC_ALRMBR_HT 0x00300000U
5144 #define RTC_ALRMBR_HT_0 0x00100000U
5145 #define RTC_ALRMBR_HT_1 0x00200000U
5146 #define RTC_ALRMBR_HU 0x000F0000U
5147 #define RTC_ALRMBR_HU_0 0x00010000U
5148 #define RTC_ALRMBR_HU_1 0x00020000U
5149 #define RTC_ALRMBR_HU_2 0x00040000U
5150 #define RTC_ALRMBR_HU_3 0x00080000U
5151 #define RTC_ALRMBR_MSK2 0x00008000U
5152 #define RTC_ALRMBR_MNT 0x00007000U
5153 #define RTC_ALRMBR_MNT_0 0x00001000U
5154 #define RTC_ALRMBR_MNT_1 0x00002000U
5155 #define RTC_ALRMBR_MNT_2 0x00004000U
5156 #define RTC_ALRMBR_MNU 0x00000F00U
5157 #define RTC_ALRMBR_MNU_0 0x00000100U
5158 #define RTC_ALRMBR_MNU_1 0x00000200U
5159 #define RTC_ALRMBR_MNU_2 0x00000400U
5160 #define RTC_ALRMBR_MNU_3 0x00000800U
5161 #define RTC_ALRMBR_MSK1 0x00000080U
5162 #define RTC_ALRMBR_ST 0x00000070U
5163 #define RTC_ALRMBR_ST_0 0x00000010U
5164 #define RTC_ALRMBR_ST_1 0x00000020U
5165 #define RTC_ALRMBR_ST_2 0x00000040U
5166 #define RTC_ALRMBR_SU 0x0000000FU
5167 #define RTC_ALRMBR_SU_0 0x00000001U
5168 #define RTC_ALRMBR_SU_1 0x00000002U
5169 #define RTC_ALRMBR_SU_2 0x00000004U
5170 #define RTC_ALRMBR_SU_3 0x00000008U
5171 
5172 /******************** Bits definition for RTC_WPR register ******************/
5173 #define RTC_WPR_KEY 0x000000FFU
5174 
5175 /******************** Bits definition for RTC_SSR register ******************/
5176 #define RTC_SSR_SS 0x0000FFFFU
5177 
5178 /******************** Bits definition for RTC_SHIFTR register ***************/
5179 #define RTC_SHIFTR_SUBFS 0x00007FFFU
5180 #define RTC_SHIFTR_ADD1S 0x80000000U
5181 
5182 /******************** Bits definition for RTC_TSTR register *****************/
5183 #define RTC_TSTR_PM 0x00400000U
5184 #define RTC_TSTR_HT 0x00300000U
5185 #define RTC_TSTR_HT_0 0x00100000U
5186 #define RTC_TSTR_HT_1 0x00200000U
5187 #define RTC_TSTR_HU 0x000F0000U
5188 #define RTC_TSTR_HU_0 0x00010000U
5189 #define RTC_TSTR_HU_1 0x00020000U
5190 #define RTC_TSTR_HU_2 0x00040000U
5191 #define RTC_TSTR_HU_3 0x00080000U
5192 #define RTC_TSTR_MNT 0x00007000U
5193 #define RTC_TSTR_MNT_0 0x00001000U
5194 #define RTC_TSTR_MNT_1 0x00002000U
5195 #define RTC_TSTR_MNT_2 0x00004000U
5196 #define RTC_TSTR_MNU 0x00000F00U
5197 #define RTC_TSTR_MNU_0 0x00000100U
5198 #define RTC_TSTR_MNU_1 0x00000200U
5199 #define RTC_TSTR_MNU_2 0x00000400U
5200 #define RTC_TSTR_MNU_3 0x00000800U
5201 #define RTC_TSTR_ST 0x00000070U
5202 #define RTC_TSTR_ST_0 0x00000010U
5203 #define RTC_TSTR_ST_1 0x00000020U
5204 #define RTC_TSTR_ST_2 0x00000040U
5205 #define RTC_TSTR_SU 0x0000000FU
5206 #define RTC_TSTR_SU_0 0x00000001U
5207 #define RTC_TSTR_SU_1 0x00000002U
5208 #define RTC_TSTR_SU_2 0x00000004U
5209 #define RTC_TSTR_SU_3 0x00000008U
5210 
5211 /******************** Bits definition for RTC_TSDR register *****************/
5212 #define RTC_TSDR_WDU 0x0000E000U
5213 #define RTC_TSDR_WDU_0 0x00002000U
5214 #define RTC_TSDR_WDU_1 0x00004000U
5215 #define RTC_TSDR_WDU_2 0x00008000U
5216 #define RTC_TSDR_MT 0x00001000U
5217 #define RTC_TSDR_MU 0x00000F00U
5218 #define RTC_TSDR_MU_0 0x00000100U
5219 #define RTC_TSDR_MU_1 0x00000200U
5220 #define RTC_TSDR_MU_2 0x00000400U
5221 #define RTC_TSDR_MU_3 0x00000800U
5222 #define RTC_TSDR_DT 0x00000030U
5223 #define RTC_TSDR_DT_0 0x00000010U
5224 #define RTC_TSDR_DT_1 0x00000020U
5225 #define RTC_TSDR_DU 0x0000000FU
5226 #define RTC_TSDR_DU_0 0x00000001U
5227 #define RTC_TSDR_DU_1 0x00000002U
5228 #define RTC_TSDR_DU_2 0x00000004U
5229 #define RTC_TSDR_DU_3 0x00000008U
5230 
5231 /******************** Bits definition for RTC_TSSSR register ****************/
5232 #define RTC_TSSSR_SS 0x0000FFFFU
5233 
5234 /******************** Bits definition for RTC_CAL register *****************/
5235 #define RTC_CALR_CALP 0x00008000U
5236 #define RTC_CALR_CALW8 0x00004000U
5237 #define RTC_CALR_CALW16 0x00002000U
5238 #define RTC_CALR_CALM 0x000001FFU
5239 #define RTC_CALR_CALM_0 0x00000001U
5240 #define RTC_CALR_CALM_1 0x00000002U
5241 #define RTC_CALR_CALM_2 0x00000004U
5242 #define RTC_CALR_CALM_3 0x00000008U
5243 #define RTC_CALR_CALM_4 0x00000010U
5244 #define RTC_CALR_CALM_5 0x00000020U
5245 #define RTC_CALR_CALM_6 0x00000040U
5246 #define RTC_CALR_CALM_7 0x00000080U
5247 #define RTC_CALR_CALM_8 0x00000100U
5248 
5249 /******************** Bits definition for RTC_TAFCR register ****************/
5250 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
5251 #define RTC_TAFCR_TSINSEL 0x00020000U
5252 #define RTC_TAFCR_TAMPINSEL 0x00010000U
5253 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
5254 #define RTC_TAFCR_TAMPPRCH 0x00006000U
5255 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
5256 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
5257 #define RTC_TAFCR_TAMPFLT 0x00001800U
5258 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
5259 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
5260 #define RTC_TAFCR_TAMPFREQ 0x00000700U
5261 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
5262 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
5263 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
5264 #define RTC_TAFCR_TAMPTS 0x00000080U
5265 #define RTC_TAFCR_TAMP2TRG 0x00000010U
5266 #define RTC_TAFCR_TAMP2E 0x00000008U
5267 #define RTC_TAFCR_TAMPIE 0x00000004U
5268 #define RTC_TAFCR_TAMP1TRG 0x00000002U
5269 #define RTC_TAFCR_TAMP1E 0x00000001U
5270 
5271 /******************** Bits definition for RTC_ALRMASSR register *************/
5272 #define RTC_ALRMASSR_MASKSS 0x0F000000U
5273 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
5274 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
5275 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
5276 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
5277 #define RTC_ALRMASSR_SS 0x00007FFFU
5278 
5279 /******************** Bits definition for RTC_ALRMBSSR register *************/
5280 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
5281 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
5282 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
5283 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
5284 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
5285 #define RTC_ALRMBSSR_SS 0x00007FFFU
5286 
5287 /******************** Bits definition for RTC_BKP0R register ****************/
5288 #define RTC_BKP0R 0xFFFFFFFFU
5289 
5290 /******************** Bits definition for RTC_BKP1R register ****************/
5291 #define RTC_BKP1R 0xFFFFFFFFU
5292 
5293 /******************** Bits definition for RTC_BKP2R register ****************/
5294 #define RTC_BKP2R 0xFFFFFFFFU
5295 
5296 /******************** Bits definition for RTC_BKP3R register ****************/
5297 #define RTC_BKP3R 0xFFFFFFFFU
5298 
5299 /******************** Bits definition for RTC_BKP4R register ****************/
5300 #define RTC_BKP4R 0xFFFFFFFFU
5301 
5302 /******************** Bits definition for RTC_BKP5R register ****************/
5303 #define RTC_BKP5R 0xFFFFFFFFU
5304 
5305 /******************** Bits definition for RTC_BKP6R register ****************/
5306 #define RTC_BKP6R 0xFFFFFFFFU
5307 
5308 /******************** Bits definition for RTC_BKP7R register ****************/
5309 #define RTC_BKP7R 0xFFFFFFFFU
5310 
5311 /******************** Bits definition for RTC_BKP8R register ****************/
5312 #define RTC_BKP8R 0xFFFFFFFFU
5313 
5314 /******************** Bits definition for RTC_BKP9R register ****************/
5315 #define RTC_BKP9R 0xFFFFFFFFU
5316 
5317 /******************** Bits definition for RTC_BKP10R register ***************/
5318 #define RTC_BKP10R 0xFFFFFFFFU
5319 
5320 /******************** Bits definition for RTC_BKP11R register ***************/
5321 #define RTC_BKP11R 0xFFFFFFFFU
5322 
5323 /******************** Bits definition for RTC_BKP12R register ***************/
5324 #define RTC_BKP12R 0xFFFFFFFFU
5325 
5326 /******************** Bits definition for RTC_BKP13R register ***************/
5327 #define RTC_BKP13R 0xFFFFFFFFU
5328 
5329 /******************** Bits definition for RTC_BKP14R register ***************/
5330 #define RTC_BKP14R 0xFFFFFFFFU
5331 
5332 /******************** Bits definition for RTC_BKP15R register ***************/
5333 #define RTC_BKP15R 0xFFFFFFFFU
5334 
5335 /******************** Bits definition for RTC_BKP16R register ***************/
5336 #define RTC_BKP16R 0xFFFFFFFFU
5337 
5338 /******************** Bits definition for RTC_BKP17R register ***************/
5339 #define RTC_BKP17R 0xFFFFFFFFU
5340 
5341 /******************** Bits definition for RTC_BKP18R register ***************/
5342 #define RTC_BKP18R 0xFFFFFFFFU
5343 
5344 /******************** Bits definition for RTC_BKP19R register ***************/
5345 #define RTC_BKP19R 0xFFFFFFFFU
5346 
5347 
5348 
5349 /******************************************************************************/
5350 /* */
5351 /* SD host Interface */
5352 /* */
5353 /******************************************************************************/
5354 /****************** Bit definition for SDIO_POWER register ******************/
5355 #define SDIO_POWER_PWRCTRL 0x03U
5356 #define SDIO_POWER_PWRCTRL_0 0x01U
5357 #define SDIO_POWER_PWRCTRL_1 0x02U
5359 /****************** Bit definition for SDIO_CLKCR register ******************/
5360 #define SDIO_CLKCR_CLKDIV 0x00FFU
5361 #define SDIO_CLKCR_CLKEN 0x0100U
5362 #define SDIO_CLKCR_PWRSAV 0x0200U
5363 #define SDIO_CLKCR_BYPASS 0x0400U
5365 #define SDIO_CLKCR_WIDBUS 0x1800U
5366 #define SDIO_CLKCR_WIDBUS_0 0x0800U
5367 #define SDIO_CLKCR_WIDBUS_1 0x1000U
5369 #define SDIO_CLKCR_NEGEDGE 0x2000U
5370 #define SDIO_CLKCR_HWFC_EN 0x4000U
5372 /******************* Bit definition for SDIO_ARG register *******************/
5373 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
5375 /******************* Bit definition for SDIO_CMD register *******************/
5376 #define SDIO_CMD_CMDINDEX 0x003FU
5378 #define SDIO_CMD_WAITRESP 0x00C0U
5379 #define SDIO_CMD_WAITRESP_0 0x0040U
5380 #define SDIO_CMD_WAITRESP_1 0x0080U
5382 #define SDIO_CMD_WAITINT 0x0100U
5383 #define SDIO_CMD_WAITPEND 0x0200U
5384 #define SDIO_CMD_CPSMEN 0x0400U
5385 #define SDIO_CMD_SDIOSUSPEND 0x0800U
5386 #define SDIO_CMD_ENCMDCOMPL 0x1000U
5387 #define SDIO_CMD_NIEN 0x2000U
5388 #define SDIO_CMD_CEATACMD 0x4000U
5390 /***************** Bit definition for SDIO_RESPCMD register *****************/
5391 #define SDIO_RESPCMD_RESPCMD 0x3FU
5393 /****************** Bit definition for SDIO_RESP0 register ******************/
5394 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
5396 /****************** Bit definition for SDIO_RESP1 register ******************/
5397 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
5399 /****************** Bit definition for SDIO_RESP2 register ******************/
5400 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
5402 /****************** Bit definition for SDIO_RESP3 register ******************/
5403 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
5405 /****************** Bit definition for SDIO_RESP4 register ******************/
5406 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
5408 /****************** Bit definition for SDIO_DTIMER register *****************/
5409 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
5411 /****************** Bit definition for SDIO_DLEN register *******************/
5412 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
5414 /****************** Bit definition for SDIO_DCTRL register ******************/
5415 #define SDIO_DCTRL_DTEN 0x0001U
5416 #define SDIO_DCTRL_DTDIR 0x0002U
5417 #define SDIO_DCTRL_DTMODE 0x0004U
5418 #define SDIO_DCTRL_DMAEN 0x0008U
5420 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
5421 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
5422 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
5423 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
5424 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
5426 #define SDIO_DCTRL_RWSTART 0x0100U
5427 #define SDIO_DCTRL_RWSTOP 0x0200U
5428 #define SDIO_DCTRL_RWMOD 0x0400U
5429 #define SDIO_DCTRL_SDIOEN 0x0800U
5431 /****************** Bit definition for SDIO_DCOUNT register *****************/
5432 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
5434 /****************** Bit definition for SDIO_STA register ********************/
5435 #define SDIO_STA_CCRCFAIL 0x00000001U
5436 #define SDIO_STA_DCRCFAIL 0x00000002U
5437 #define SDIO_STA_CTIMEOUT 0x00000004U
5438 #define SDIO_STA_DTIMEOUT 0x00000008U
5439 #define SDIO_STA_TXUNDERR 0x00000010U
5440 #define SDIO_STA_RXOVERR 0x00000020U
5441 #define SDIO_STA_CMDREND 0x00000040U
5442 #define SDIO_STA_CMDSENT 0x00000080U
5443 #define SDIO_STA_DATAEND 0x00000100U
5444 #define SDIO_STA_STBITERR 0x00000200U
5445 #define SDIO_STA_DBCKEND 0x00000400U
5446 #define SDIO_STA_CMDACT 0x00000800U
5447 #define SDIO_STA_TXACT 0x00001000U
5448 #define SDIO_STA_RXACT 0x00002000U
5449 #define SDIO_STA_TXFIFOHE 0x00004000U
5450 #define SDIO_STA_RXFIFOHF 0x00008000U
5451 #define SDIO_STA_TXFIFOF 0x00010000U
5452 #define SDIO_STA_RXFIFOF 0x00020000U
5453 #define SDIO_STA_TXFIFOE 0x00040000U
5454 #define SDIO_STA_RXFIFOE 0x00080000U
5455 #define SDIO_STA_TXDAVL 0x00100000U
5456 #define SDIO_STA_RXDAVL 0x00200000U
5457 #define SDIO_STA_SDIOIT 0x00400000U
5458 #define SDIO_STA_CEATAEND 0x00800000U
5460 /******************* Bit definition for SDIO_ICR register *******************/
5461 #define SDIO_ICR_CCRCFAILC 0x00000001U
5462 #define SDIO_ICR_DCRCFAILC 0x00000002U
5463 #define SDIO_ICR_CTIMEOUTC 0x00000004U
5464 #define SDIO_ICR_DTIMEOUTC 0x00000008U
5465 #define SDIO_ICR_TXUNDERRC 0x00000010U
5466 #define SDIO_ICR_RXOVERRC 0x00000020U
5467 #define SDIO_ICR_CMDRENDC 0x00000040U
5468 #define SDIO_ICR_CMDSENTC 0x00000080U
5469 #define SDIO_ICR_DATAENDC 0x00000100U
5470 #define SDIO_ICR_STBITERRC 0x00000200U
5471 #define SDIO_ICR_DBCKENDC 0x00000400U
5472 #define SDIO_ICR_SDIOITC 0x00400000U
5473 #define SDIO_ICR_CEATAENDC 0x00800000U
5475 /****************** Bit definition for SDIO_MASK register *******************/
5476 #define SDIO_MASK_CCRCFAILIE 0x00000001U
5477 #define SDIO_MASK_DCRCFAILIE 0x00000002U
5478 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
5479 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
5480 #define SDIO_MASK_TXUNDERRIE 0x00000010U
5481 #define SDIO_MASK_RXOVERRIE 0x00000020U
5482 #define SDIO_MASK_CMDRENDIE 0x00000040U
5483 #define SDIO_MASK_CMDSENTIE 0x00000080U
5484 #define SDIO_MASK_DATAENDIE 0x00000100U
5485 #define SDIO_MASK_STBITERRIE 0x00000200U
5486 #define SDIO_MASK_DBCKENDIE 0x00000400U
5487 #define SDIO_MASK_CMDACTIE 0x00000800U
5488 #define SDIO_MASK_TXACTIE 0x00001000U
5489 #define SDIO_MASK_RXACTIE 0x00002000U
5490 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
5491 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
5492 #define SDIO_MASK_TXFIFOFIE 0x00010000U
5493 #define SDIO_MASK_RXFIFOFIE 0x00020000U
5494 #define SDIO_MASK_TXFIFOEIE 0x00040000U
5495 #define SDIO_MASK_RXFIFOEIE 0x00080000U
5496 #define SDIO_MASK_TXDAVLIE 0x00100000U
5497 #define SDIO_MASK_RXDAVLIE 0x00200000U
5498 #define SDIO_MASK_SDIOITIE 0x00400000U
5499 #define SDIO_MASK_CEATAENDIE 0x00800000U
5501 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5502 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
5504 /****************** Bit definition for SDIO_FIFO register *******************/
5505 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
5507 /******************************************************************************/
5508 /* */
5509 /* Serial Peripheral Interface */
5510 /* */
5511 /******************************************************************************/
5512 /******************* Bit definition for SPI_CR1 register ********************/
5513 #define SPI_CR1_CPHA 0x00000001U
5514 #define SPI_CR1_CPOL 0x00000002U
5515 #define SPI_CR1_MSTR 0x00000004U
5517 #define SPI_CR1_BR 0x00000038U
5518 #define SPI_CR1_BR_0 0x00000008U
5519 #define SPI_CR1_BR_1 0x00000010U
5520 #define SPI_CR1_BR_2 0x00000020U
5522 #define SPI_CR1_SPE 0x00000040U
5523 #define SPI_CR1_LSBFIRST 0x00000080U
5524 #define SPI_CR1_SSI 0x00000100U
5525 #define SPI_CR1_SSM 0x00000200U
5526 #define SPI_CR1_RXONLY 0x00000400U
5527 #define SPI_CR1_DFF 0x00000800U
5528 #define SPI_CR1_CRCNEXT 0x00001000U
5529 #define SPI_CR1_CRCEN 0x00002000U
5530 #define SPI_CR1_BIDIOE 0x00004000U
5531 #define SPI_CR1_BIDIMODE 0x00008000U
5533 /******************* Bit definition for SPI_CR2 register ********************/
5534 #define SPI_CR2_RXDMAEN 0x00000001U
5535 #define SPI_CR2_TXDMAEN 0x00000002U
5536 #define SPI_CR2_SSOE 0x00000004U
5537 #define SPI_CR2_FRF 0x00000010U
5538 #define SPI_CR2_ERRIE 0x00000020U
5539 #define SPI_CR2_RXNEIE 0x00000040U
5540 #define SPI_CR2_TXEIE 0x00000080U
5542 /******************** Bit definition for SPI_SR register ********************/
5543 #define SPI_SR_RXNE 0x00000001U
5544 #define SPI_SR_TXE 0x00000002U
5545 #define SPI_SR_CHSIDE 0x00000004U
5546 #define SPI_SR_UDR 0x00000008U
5547 #define SPI_SR_CRCERR 0x00000010U
5548 #define SPI_SR_MODF 0x00000020U
5549 #define SPI_SR_OVR 0x00000040U
5550 #define SPI_SR_BSY 0x00000080U
5551 #define SPI_SR_FRE 0x00000100U
5553 /******************** Bit definition for SPI_DR register ********************/
5554 #define SPI_DR_DR 0x0000FFFFU
5556 /******************* Bit definition for SPI_CRCPR register ******************/
5557 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
5559 /****************** Bit definition for SPI_RXCRCR register ******************/
5560 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
5562 /****************** Bit definition for SPI_TXCRCR register ******************/
5563 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
5565 /****************** Bit definition for SPI_I2SCFGR register *****************/
5566 #define SPI_I2SCFGR_CHLEN 0x00000001U
5568 #define SPI_I2SCFGR_DATLEN 0x00000006U
5569 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
5570 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
5572 #define SPI_I2SCFGR_CKPOL 0x00000008U
5574 #define SPI_I2SCFGR_I2SSTD 0x00000030U
5575 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
5576 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
5578 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
5580 #define SPI_I2SCFGR_I2SCFG 0x00000300U
5581 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
5582 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
5584 #define SPI_I2SCFGR_I2SE 0x00000400U
5585 #define SPI_I2SCFGR_I2SMOD 0x00000800U
5587 /****************** Bit definition for SPI_I2SPR register *******************/
5588 #define SPI_I2SPR_I2SDIV 0x000000FFU
5589 #define SPI_I2SPR_ODD 0x00000100U
5590 #define SPI_I2SPR_MCKOE 0x00000200U
5592 /******************************************************************************/
5593 /* */
5594 /* SYSCFG */
5595 /* */
5596 /******************************************************************************/
5597 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
5598 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
5599 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
5600 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
5601 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
5602 
5603 #define SYSCFG_SWP_FSMC 0x00000C00U
5604 /****************** Bit definition for SYSCFG_PMC register ******************/
5605 #define SYSCFG_PMC_ADC1DC2 0x00010000U
5607 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5608 #define SYSCFG_EXTICR1_EXTI0 0x000FU
5609 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
5610 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
5611 #define SYSCFG_EXTICR1_EXTI3 0xF000U
5615 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
5616 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
5617 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
5618 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
5619 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
5620 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
5621 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
5622 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
5627 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
5628 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
5629 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
5630 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
5631 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
5632 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
5633 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
5634 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
5639 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
5640 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
5641 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
5642 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
5643 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
5644 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
5645 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
5646 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
5651 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
5652 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
5653 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
5654 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
5655 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
5656 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
5657 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
5658 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
5660 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5661 #define SYSCFG_EXTICR2_EXTI4 0x000FU
5662 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
5663 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
5664 #define SYSCFG_EXTICR2_EXTI7 0xF000U
5668 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
5669 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
5670 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
5671 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
5672 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
5673 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
5674 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
5675 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
5680 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
5681 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
5682 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
5683 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
5684 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
5685 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
5686 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
5687 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
5692 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
5693 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
5694 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
5695 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
5696 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
5697 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
5698 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
5699 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
5704 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
5705 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
5706 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
5707 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
5708 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
5709 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
5710 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
5711 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
5714 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5715 #define SYSCFG_EXTICR3_EXTI8 0x000FU
5716 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
5717 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
5718 #define SYSCFG_EXTICR3_EXTI11 0xF000U
5723 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
5724 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
5725 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
5726 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
5727 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
5728 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
5729 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
5730 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
5735 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
5736 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
5737 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
5738 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
5739 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
5740 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
5741 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
5742 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
5747 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
5748 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
5749 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
5750 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
5751 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
5752 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
5753 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
5754 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
5759 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
5760 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
5761 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
5762 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
5763 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
5764 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
5765 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
5766 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
5768 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5769 #define SYSCFG_EXTICR4_EXTI12 0x000FU
5770 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
5771 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
5772 #define SYSCFG_EXTICR4_EXTI15 0xF000U
5776 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
5777 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
5778 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
5779 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
5780 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
5781 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
5782 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
5783 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
5788 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
5789 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
5790 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
5791 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
5792 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
5793 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
5794 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
5795 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
5800 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
5801 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
5802 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
5803 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
5804 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
5805 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
5806 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
5807 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
5812 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
5813 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
5814 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
5815 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
5816 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
5817 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
5818 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
5819 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
5821 /****************** Bit definition for SYSCFG_CMPCR register ****************/
5822 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
5823 #define SYSCFG_CMPCR_READY 0x00000100U
5825 /****************** Bit definition for SYSCFG_CFGR register *****************/
5826 #define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U
5827 #define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U
5829 /******************************************************************************/
5830 /* */
5831 /* TIM */
5832 /* */
5833 /******************************************************************************/
5834 /******************* Bit definition for TIM_CR1 register ********************/
5835 #define TIM_CR1_CEN 0x0001U
5836 #define TIM_CR1_UDIS 0x0002U
5837 #define TIM_CR1_URS 0x0004U
5838 #define TIM_CR1_OPM 0x0008U
5839 #define TIM_CR1_DIR 0x0010U
5841 #define TIM_CR1_CMS 0x0060U
5842 #define TIM_CR1_CMS_0 0x0020U
5843 #define TIM_CR1_CMS_1 0x0040U
5845 #define TIM_CR1_ARPE 0x0080U
5847 #define TIM_CR1_CKD 0x0300U
5848 #define TIM_CR1_CKD_0 0x0100U
5849 #define TIM_CR1_CKD_1 0x0200U
5851 /******************* Bit definition for TIM_CR2 register ********************/
5852 #define TIM_CR2_CCPC 0x0001U
5853 #define TIM_CR2_CCUS 0x0004U
5854 #define TIM_CR2_CCDS 0x0008U
5856 #define TIM_CR2_MMS 0x0070U
5857 #define TIM_CR2_MMS_0 0x0010U
5858 #define TIM_CR2_MMS_1 0x0020U
5859 #define TIM_CR2_MMS_2 0x0040U
5861 #define TIM_CR2_TI1S 0x0080U
5862 #define TIM_CR2_OIS1 0x0100U
5863 #define TIM_CR2_OIS1N 0x0200U
5864 #define TIM_CR2_OIS2 0x0400U
5865 #define TIM_CR2_OIS2N 0x0800U
5866 #define TIM_CR2_OIS3 0x1000U
5867 #define TIM_CR2_OIS3N 0x2000U
5868 #define TIM_CR2_OIS4 0x4000U
5870 /******************* Bit definition for TIM_SMCR register *******************/
5871 #define TIM_SMCR_SMS 0x0007U
5872 #define TIM_SMCR_SMS_0 0x0001U
5873 #define TIM_SMCR_SMS_1 0x0002U
5874 #define TIM_SMCR_SMS_2 0x0004U
5876 #define TIM_SMCR_TS 0x0070U
5877 #define TIM_SMCR_TS_0 0x0010U
5878 #define TIM_SMCR_TS_1 0x0020U
5879 #define TIM_SMCR_TS_2 0x0040U
5881 #define TIM_SMCR_MSM 0x0080U
5883 #define TIM_SMCR_ETF 0x0F00U
5884 #define TIM_SMCR_ETF_0 0x0100U
5885 #define TIM_SMCR_ETF_1 0x0200U
5886 #define TIM_SMCR_ETF_2 0x0400U
5887 #define TIM_SMCR_ETF_3 0x0800U
5889 #define TIM_SMCR_ETPS 0x3000U
5890 #define TIM_SMCR_ETPS_0 0x1000U
5891 #define TIM_SMCR_ETPS_1 0x2000U
5893 #define TIM_SMCR_ECE 0x4000U
5894 #define TIM_SMCR_ETP 0x8000U
5896 /******************* Bit definition for TIM_DIER register *******************/
5897 #define TIM_DIER_UIE 0x0001U
5898 #define TIM_DIER_CC1IE 0x0002U
5899 #define TIM_DIER_CC2IE 0x0004U
5900 #define TIM_DIER_CC3IE 0x0008U
5901 #define TIM_DIER_CC4IE 0x0010U
5902 #define TIM_DIER_COMIE 0x0020U
5903 #define TIM_DIER_TIE 0x0040U
5904 #define TIM_DIER_BIE 0x0080U
5905 #define TIM_DIER_UDE 0x0100U
5906 #define TIM_DIER_CC1DE 0x0200U
5907 #define TIM_DIER_CC2DE 0x0400U
5908 #define TIM_DIER_CC3DE 0x0800U
5909 #define TIM_DIER_CC4DE 0x1000U
5910 #define TIM_DIER_COMDE 0x2000U
5911 #define TIM_DIER_TDE 0x4000U
5913 /******************** Bit definition for TIM_SR register ********************/
5914 #define TIM_SR_UIF 0x0001U
5915 #define TIM_SR_CC1IF 0x0002U
5916 #define TIM_SR_CC2IF 0x0004U
5917 #define TIM_SR_CC3IF 0x0008U
5918 #define TIM_SR_CC4IF 0x0010U
5919 #define TIM_SR_COMIF 0x0020U
5920 #define TIM_SR_TIF 0x0040U
5921 #define TIM_SR_BIF 0x0080U
5922 #define TIM_SR_CC1OF 0x0200U
5923 #define TIM_SR_CC2OF 0x0400U
5924 #define TIM_SR_CC3OF 0x0800U
5925 #define TIM_SR_CC4OF 0x1000U
5927 /******************* Bit definition for TIM_EGR register ********************/
5928 #define TIM_EGR_UG 0x01U
5929 #define TIM_EGR_CC1G 0x02U
5930 #define TIM_EGR_CC2G 0x04U
5931 #define TIM_EGR_CC3G 0x08U
5932 #define TIM_EGR_CC4G 0x10U
5933 #define TIM_EGR_COMG 0x20U
5934 #define TIM_EGR_TG 0x40U
5935 #define TIM_EGR_BG 0x80U
5937 /****************** Bit definition for TIM_CCMR1 register *******************/
5938 #define TIM_CCMR1_CC1S 0x0003U
5939 #define TIM_CCMR1_CC1S_0 0x0001U
5940 #define TIM_CCMR1_CC1S_1 0x0002U
5942 #define TIM_CCMR1_OC1FE 0x0004U
5943 #define TIM_CCMR1_OC1PE 0x0008U
5945 #define TIM_CCMR1_OC1M 0x0070U
5946 #define TIM_CCMR1_OC1M_0 0x0010U
5947 #define TIM_CCMR1_OC1M_1 0x0020U
5948 #define TIM_CCMR1_OC1M_2 0x0040U
5950 #define TIM_CCMR1_OC1CE 0x0080U
5952 #define TIM_CCMR1_CC2S 0x0300U
5953 #define TIM_CCMR1_CC2S_0 0x0100U
5954 #define TIM_CCMR1_CC2S_1 0x0200U
5956 #define TIM_CCMR1_OC2FE 0x0400U
5957 #define TIM_CCMR1_OC2PE 0x0800U
5959 #define TIM_CCMR1_OC2M 0x7000U
5960 #define TIM_CCMR1_OC2M_0 0x1000U
5961 #define TIM_CCMR1_OC2M_1 0x2000U
5962 #define TIM_CCMR1_OC2M_2 0x4000U
5964 #define TIM_CCMR1_OC2CE 0x8000U
5966 /*----------------------------------------------------------------------------*/
5967 
5968 #define TIM_CCMR1_IC1PSC 0x000CU
5969 #define TIM_CCMR1_IC1PSC_0 0x0004U
5970 #define TIM_CCMR1_IC1PSC_1 0x0008U
5972 #define TIM_CCMR1_IC1F 0x00F0U
5973 #define TIM_CCMR1_IC1F_0 0x0010U
5974 #define TIM_CCMR1_IC1F_1 0x0020U
5975 #define TIM_CCMR1_IC1F_2 0x0040U
5976 #define TIM_CCMR1_IC1F_3 0x0080U
5978 #define TIM_CCMR1_IC2PSC 0x0C00U
5979 #define TIM_CCMR1_IC2PSC_0 0x0400U
5980 #define TIM_CCMR1_IC2PSC_1 0x0800U
5982 #define TIM_CCMR1_IC2F 0xF000U
5983 #define TIM_CCMR1_IC2F_0 0x1000U
5984 #define TIM_CCMR1_IC2F_1 0x2000U
5985 #define TIM_CCMR1_IC2F_2 0x4000U
5986 #define TIM_CCMR1_IC2F_3 0x8000U
5988 /****************** Bit definition for TIM_CCMR2 register *******************/
5989 #define TIM_CCMR2_CC3S 0x0003U
5990 #define TIM_CCMR2_CC3S_0 0x0001U
5991 #define TIM_CCMR2_CC3S_1 0x0002U
5993 #define TIM_CCMR2_OC3FE 0x0004U
5994 #define TIM_CCMR2_OC3PE 0x0008U
5996 #define TIM_CCMR2_OC3M 0x0070U
5997 #define TIM_CCMR2_OC3M_0 0x0010U
5998 #define TIM_CCMR2_OC3M_1 0x0020U
5999 #define TIM_CCMR2_OC3M_2 0x0040U
6001 #define TIM_CCMR2_OC3CE 0x0080U
6003 #define TIM_CCMR2_CC4S 0x0300U
6004 #define TIM_CCMR2_CC4S_0 0x0100U
6005 #define TIM_CCMR2_CC4S_1 0x0200U
6007 #define TIM_CCMR2_OC4FE 0x0400U
6008 #define TIM_CCMR2_OC4PE 0x0800U
6010 #define TIM_CCMR2_OC4M 0x7000U
6011 #define TIM_CCMR2_OC4M_0 0x1000U
6012 #define TIM_CCMR2_OC4M_1 0x2000U
6013 #define TIM_CCMR2_OC4M_2 0x4000U
6015 #define TIM_CCMR2_OC4CE 0x8000U
6017 /*----------------------------------------------------------------------------*/
6018 
6019 #define TIM_CCMR2_IC3PSC 0x000CU
6020 #define TIM_CCMR2_IC3PSC_0 0x0004U
6021 #define TIM_CCMR2_IC3PSC_1 0x0008U
6023 #define TIM_CCMR2_IC3F 0x00F0U
6024 #define TIM_CCMR2_IC3F_0 0x0010U
6025 #define TIM_CCMR2_IC3F_1 0x0020U
6026 #define TIM_CCMR2_IC3F_2 0x0040U
6027 #define TIM_CCMR2_IC3F_3 0x0080U
6029 #define TIM_CCMR2_IC4PSC 0x0C00U
6030 #define TIM_CCMR2_IC4PSC_0 0x0400U
6031 #define TIM_CCMR2_IC4PSC_1 0x0800U
6033 #define TIM_CCMR2_IC4F 0xF000U
6034 #define TIM_CCMR2_IC4F_0 0x1000U
6035 #define TIM_CCMR2_IC4F_1 0x2000U
6036 #define TIM_CCMR2_IC4F_2 0x4000U
6037 #define TIM_CCMR2_IC4F_3 0x8000U
6039 /******************* Bit definition for TIM_CCER register *******************/
6040 #define TIM_CCER_CC1E 0x0001U
6041 #define TIM_CCER_CC1P 0x0002U
6042 #define TIM_CCER_CC1NE 0x0004U
6043 #define TIM_CCER_CC1NP 0x0008U
6044 #define TIM_CCER_CC2E 0x0010U
6045 #define TIM_CCER_CC2P 0x0020U
6046 #define TIM_CCER_CC2NE 0x0040U
6047 #define TIM_CCER_CC2NP 0x0080U
6048 #define TIM_CCER_CC3E 0x0100U
6049 #define TIM_CCER_CC3P 0x0200U
6050 #define TIM_CCER_CC3NE 0x0400U
6051 #define TIM_CCER_CC3NP 0x0800U
6052 #define TIM_CCER_CC4E 0x1000U
6053 #define TIM_CCER_CC4P 0x2000U
6054 #define TIM_CCER_CC4NP 0x8000U
6056 /******************* Bit definition for TIM_CNT register ********************/
6057 #define TIM_CNT_CNT 0xFFFFU
6059 /******************* Bit definition for TIM_PSC register ********************/
6060 #define TIM_PSC_PSC 0xFFFFU
6062 /******************* Bit definition for TIM_ARR register ********************/
6063 #define TIM_ARR_ARR 0xFFFFU
6065 /******************* Bit definition for TIM_RCR register ********************/
6066 #define TIM_RCR_REP 0xFFU
6068 /******************* Bit definition for TIM_CCR1 register *******************/
6069 #define TIM_CCR1_CCR1 0xFFFFU
6071 /******************* Bit definition for TIM_CCR2 register *******************/
6072 #define TIM_CCR2_CCR2 0xFFFFU
6074 /******************* Bit definition for TIM_CCR3 register *******************/
6075 #define TIM_CCR3_CCR3 0xFFFFU
6077 /******************* Bit definition for TIM_CCR4 register *******************/
6078 #define TIM_CCR4_CCR4 0xFFFFU
6080 /******************* Bit definition for TIM_BDTR register *******************/
6081 #define TIM_BDTR_DTG 0x00FFU
6082 #define TIM_BDTR_DTG_0 0x0001U
6083 #define TIM_BDTR_DTG_1 0x0002U
6084 #define TIM_BDTR_DTG_2 0x0004U
6085 #define TIM_BDTR_DTG_3 0x0008U
6086 #define TIM_BDTR_DTG_4 0x0010U
6087 #define TIM_BDTR_DTG_5 0x0020U
6088 #define TIM_BDTR_DTG_6 0x0040U
6089 #define TIM_BDTR_DTG_7 0x0080U
6091 #define TIM_BDTR_LOCK 0x0300U
6092 #define TIM_BDTR_LOCK_0 0x0100U
6093 #define TIM_BDTR_LOCK_1 0x0200U
6095 #define TIM_BDTR_OSSI 0x0400U
6096 #define TIM_BDTR_OSSR 0x0800U
6097 #define TIM_BDTR_BKE 0x1000U
6098 #define TIM_BDTR_BKP 0x2000U
6099 #define TIM_BDTR_AOE 0x4000U
6100 #define TIM_BDTR_MOE 0x8000U
6102 /******************* Bit definition for TIM_DCR register ********************/
6103 #define TIM_DCR_DBA 0x001FU
6104 #define TIM_DCR_DBA_0 0x0001U
6105 #define TIM_DCR_DBA_1 0x0002U
6106 #define TIM_DCR_DBA_2 0x0004U
6107 #define TIM_DCR_DBA_3 0x0008U
6108 #define TIM_DCR_DBA_4 0x0010U
6110 #define TIM_DCR_DBL 0x1F00U
6111 #define TIM_DCR_DBL_0 0x0100U
6112 #define TIM_DCR_DBL_1 0x0200U
6113 #define TIM_DCR_DBL_2 0x0400U
6114 #define TIM_DCR_DBL_3 0x0800U
6115 #define TIM_DCR_DBL_4 0x1000U
6117 /******************* Bit definition for TIM_DMAR register *******************/
6118 #define TIM_DMAR_DMAB 0xFFFFU
6120 /******************* Bit definition for TIM_OR register *********************/
6121 #define TIM_OR_TI4_RMP 0x00C0U
6122 #define TIM_OR_TI4_RMP_0 0x0040U
6123 #define TIM_OR_TI4_RMP_1 0x0080U
6124 #define TIM_OR_ITR1_RMP 0x0C00U
6125 #define TIM_OR_ITR1_RMP_0 0x0400U
6126 #define TIM_OR_ITR1_RMP_1 0x0800U
6129 /******************************************************************************/
6130 /* */
6131 /* Universal Synchronous Asynchronous Receiver Transmitter */
6132 /* */
6133 /******************************************************************************/
6134 /******************* Bit definition for USART_SR register *******************/
6135 #define USART_SR_PE 0x0001U
6136 #define USART_SR_FE 0x0002U
6137 #define USART_SR_NE 0x0004U
6138 #define USART_SR_ORE 0x0008U
6139 #define USART_SR_IDLE 0x0010U
6140 #define USART_SR_RXNE 0x0020U
6141 #define USART_SR_TC 0x0040U
6142 #define USART_SR_TXE 0x0080U
6143 #define USART_SR_LBD 0x0100U
6144 #define USART_SR_CTS 0x0200U
6146 /******************* Bit definition for USART_DR register *******************/
6147 #define USART_DR_DR 0x01FFU
6149 /****************** Bit definition for USART_BRR register *******************/
6150 #define USART_BRR_DIV_Fraction 0x000FU
6151 #define USART_BRR_DIV_Mantissa 0xFFF0U
6153 /****************** Bit definition for USART_CR1 register *******************/
6154 #define USART_CR1_SBK 0x0001U
6155 #define USART_CR1_RWU 0x0002U
6156 #define USART_CR1_RE 0x0004U
6157 #define USART_CR1_TE 0x0008U
6158 #define USART_CR1_IDLEIE 0x0010U
6159 #define USART_CR1_RXNEIE 0x0020U
6160 #define USART_CR1_TCIE 0x0040U
6161 #define USART_CR1_TXEIE 0x0080U
6162 #define USART_CR1_PEIE 0x0100U
6163 #define USART_CR1_PS 0x0200U
6164 #define USART_CR1_PCE 0x0400U
6165 #define USART_CR1_WAKE 0x0800U
6166 #define USART_CR1_M 0x1000U
6167 #define USART_CR1_UE 0x2000U
6168 #define USART_CR1_OVER8 0x8000U
6170 /****************** Bit definition for USART_CR2 register *******************/
6171 #define USART_CR2_ADD 0x000FU
6172 #define USART_CR2_LBDL 0x0020U
6173 #define USART_CR2_LBDIE 0x0040U
6174 #define USART_CR2_LBCL 0x0100U
6175 #define USART_CR2_CPHA 0x0200U
6176 #define USART_CR2_CPOL 0x0400U
6177 #define USART_CR2_CLKEN 0x0800U
6179 #define USART_CR2_STOP 0x3000U
6180 #define USART_CR2_STOP_0 0x1000U
6181 #define USART_CR2_STOP_1 0x2000U
6183 #define USART_CR2_LINEN 0x4000U
6185 /****************** Bit definition for USART_CR3 register *******************/
6186 #define USART_CR3_EIE 0x0001U
6187 #define USART_CR3_IREN 0x0002U
6188 #define USART_CR3_IRLP 0x0004U
6189 #define USART_CR3_HDSEL 0x0008U
6190 #define USART_CR3_NACK 0x0010U
6191 #define USART_CR3_SCEN 0x0020U
6192 #define USART_CR3_DMAR 0x0040U
6193 #define USART_CR3_DMAT 0x0080U
6194 #define USART_CR3_RTSE 0x0100U
6195 #define USART_CR3_CTSE 0x0200U
6196 #define USART_CR3_CTSIE 0x0400U
6197 #define USART_CR3_ONEBIT 0x0800U
6199 /****************** Bit definition for USART_GTPR register ******************/
6200 #define USART_GTPR_PSC 0x00FFU
6201 #define USART_GTPR_PSC_0 0x0001U
6202 #define USART_GTPR_PSC_1 0x0002U
6203 #define USART_GTPR_PSC_2 0x0004U
6204 #define USART_GTPR_PSC_3 0x0008U
6205 #define USART_GTPR_PSC_4 0x0010U
6206 #define USART_GTPR_PSC_5 0x0020U
6207 #define USART_GTPR_PSC_6 0x0040U
6208 #define USART_GTPR_PSC_7 0x0080U
6210 #define USART_GTPR_GT 0xFF00U
6212 /******************************************************************************/
6213 /* */
6214 /* Window WATCHDOG */
6215 /* */
6216 /******************************************************************************/
6217 /******************* Bit definition for WWDG_CR register ********************/
6218 #define WWDG_CR_T 0x7FU
6219 #define WWDG_CR_T_0 0x01U
6220 #define WWDG_CR_T_1 0x02U
6221 #define WWDG_CR_T_2 0x04U
6222 #define WWDG_CR_T_3 0x08U
6223 #define WWDG_CR_T_4 0x10U
6224 #define WWDG_CR_T_5 0x20U
6225 #define WWDG_CR_T_6 0x40U
6226 /* Legacy defines */
6227 #define WWDG_CR_T0 WWDG_CR_T_0
6228 #define WWDG_CR_T1 WWDG_CR_T_1
6229 #define WWDG_CR_T2 WWDG_CR_T_2
6230 #define WWDG_CR_T3 WWDG_CR_T_3
6231 #define WWDG_CR_T4 WWDG_CR_T_4
6232 #define WWDG_CR_T5 WWDG_CR_T_5
6233 #define WWDG_CR_T6 WWDG_CR_T_6
6234 
6235 #define WWDG_CR_WDGA 0x80U
6237 /******************* Bit definition for WWDG_CFR register *******************/
6238 #define WWDG_CFR_W 0x007FU
6239 #define WWDG_CFR_W_0 0x0001U
6240 #define WWDG_CFR_W_1 0x0002U
6241 #define WWDG_CFR_W_2 0x0004U
6242 #define WWDG_CFR_W_3 0x0008U
6243 #define WWDG_CFR_W_4 0x0010U
6244 #define WWDG_CFR_W_5 0x0020U
6245 #define WWDG_CFR_W_6 0x0040U
6246 /* Legacy defines */
6247 #define WWDG_CFR_W0 WWDG_CFR_W_0
6248 #define WWDG_CFR_W1 WWDG_CFR_W_1
6249 #define WWDG_CFR_W2 WWDG_CFR_W_2
6250 #define WWDG_CFR_W3 WWDG_CFR_W_3
6251 #define WWDG_CFR_W4 WWDG_CFR_W_4
6252 #define WWDG_CFR_W5 WWDG_CFR_W_5
6253 #define WWDG_CFR_W6 WWDG_CFR_W_6
6254 
6255 #define WWDG_CFR_WDGTB 0x0180U
6256 #define WWDG_CFR_WDGTB_0 0x0080U
6257 #define WWDG_CFR_WDGTB_1 0x0100U
6258 /* Legacy defines */
6259 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6260 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6261 
6262 #define WWDG_CFR_EWI 0x0200U
6264 /******************* Bit definition for WWDG_SR register ********************/
6265 #define WWDG_SR_EWIF 0x01U
6268 /******************************************************************************/
6269 /* */
6270 /* DBG */
6271 /* */
6272 /******************************************************************************/
6273 /******************** Bit definition for DBGMCU_IDCODE register *************/
6274 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
6275 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
6276 
6277 /******************** Bit definition for DBGMCU_CR register *****************/
6278 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
6279 #define DBGMCU_CR_DBG_STOP 0x00000002U
6280 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
6281 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
6282 
6283 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
6284 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
6285 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
6287 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6288 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
6289 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
6290 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
6291 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
6292 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
6293 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
6294 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
6295 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
6296 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
6297 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
6298 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
6299 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
6300 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
6301 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
6302 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
6303 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
6304 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
6305 
6306 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6307 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
6308 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
6309 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
6310 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
6311 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
6312 
6313 /******************************************************************************/
6314 /* */
6315 /* USB_OTG */
6316 /* */
6317 /******************************************************************************/
6318 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
6319 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
6320 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
6321 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
6322 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
6323 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
6324 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
6325 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
6326 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
6327 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
6328 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
6329 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
6330 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
6331 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
6332 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
6333 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
6334 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
6335 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
6336 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
6338 /******************** Bit definition for USB_OTG_HCFG register **************/
6339 
6340 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
6341 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
6342 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
6343 #define USB_OTG_HCFG_FSLSS 0x00000004U
6345 /******************** Bit definition for USB_OTG_DCFG register **************/
6346 
6347 #define USB_OTG_DCFG_DSPD 0x00000003U
6348 #define USB_OTG_DCFG_DSPD_0 0x00000001U
6349 #define USB_OTG_DCFG_DSPD_1 0x00000002U
6350 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
6352 #define USB_OTG_DCFG_DAD 0x000007F0U
6353 #define USB_OTG_DCFG_DAD_0 0x00000010U
6354 #define USB_OTG_DCFG_DAD_1 0x00000020U
6355 #define USB_OTG_DCFG_DAD_2 0x00000040U
6356 #define USB_OTG_DCFG_DAD_3 0x00000080U
6357 #define USB_OTG_DCFG_DAD_4 0x00000100U
6358 #define USB_OTG_DCFG_DAD_5 0x00000200U
6359 #define USB_OTG_DCFG_DAD_6 0x00000400U
6361 #define USB_OTG_DCFG_PFIVL 0x00001800U
6362 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
6363 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
6365 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
6366 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
6367 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
6369 /******************** Bit definition for USB_OTG_PCGCR register *************/
6370 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
6371 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
6372 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
6374 /******************** Bit definition for USB_OTG_GOTGINT register ***********/
6375 #define USB_OTG_GOTGINT_SEDET 0x00000004U
6376 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
6377 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
6378 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
6379 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
6380 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
6381 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
6383 /******************** Bit definition for USB_OTG_DCTL register **************/
6384 #define USB_OTG_DCTL_RWUSIG 0x00000001U
6385 #define USB_OTG_DCTL_SDIS 0x00000002U
6386 #define USB_OTG_DCTL_GINSTS 0x00000004U
6387 #define USB_OTG_DCTL_GONSTS 0x00000008U
6388 #define USB_OTG_DCTL_TCTL 0x00000070U
6389 #define USB_OTG_DCTL_TCTL_0 0x00000010U
6390 #define USB_OTG_DCTL_TCTL_1 0x00000020U
6391 #define USB_OTG_DCTL_TCTL_2 0x00000040U
6392 #define USB_OTG_DCTL_SGINAK 0x00000080U
6393 #define USB_OTG_DCTL_CGINAK 0x00000100U
6394 #define USB_OTG_DCTL_SGONAK 0x00000200U
6395 #define USB_OTG_DCTL_CGONAK 0x00000400U
6396 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
6398 /******************** Bit definition for USB_OTG_HFIR register **************/
6399 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
6401 /******************** Bit definition for USB_OTG_HFNUM register *************/
6402 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
6403 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
6405 /******************** Bit definition for USB_OTG_DSTS register **************/
6406 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
6408 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
6409 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
6410 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
6411 #define USB_OTG_DSTS_EERR 0x00000008U
6412 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
6414 /******************** Bit definition for USB_OTG_GAHBCFG register ***********/
6415 #define USB_OTG_GAHBCFG_GINT 0x00000001U
6416 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
6417 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
6418 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
6419 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
6420 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
6421 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
6422 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
6423 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
6425 /******************** Bit definition for USB_OTG_GUSBCFG register ***********/
6426 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
6427 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
6428 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
6429 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
6430 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
6431 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
6432 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
6434 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
6435 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
6436 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
6437 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
6438 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
6439 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
6440 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
6441 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
6442 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
6443 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
6444 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
6445 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
6446 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
6447 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
6448 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
6449 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
6450 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
6451 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
6453 /******************** Bit definition for USB_OTG_GRSTCTL register ***********/
6454 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
6455 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
6456 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
6457 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
6458 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
6460 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
6461 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
6462 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
6463 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
6464 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
6465 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
6466 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
6467 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
6469 /******************** Bit definition for USB_OTG_DIEPMSK register ***********/
6470 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
6471 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
6472 #define USB_OTG_DIEPMSK_TOM 0x00000008U
6473 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
6474 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
6475 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
6476 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
6477 #define USB_OTG_DIEPMSK_BIM 0x00000200U
6479 /******************** Bit definition for USB_OTG_HPTXSTS register ***********/
6480 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
6482 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
6483 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
6484 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
6485 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
6486 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
6487 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
6488 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
6489 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
6490 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
6492 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
6493 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
6494 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
6495 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
6496 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
6497 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
6498 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
6499 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
6500 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
6502 /******************** Bit definition for USB_OTG_HAINT register *************/
6503 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
6505 /******************** Bit definition for USB_OTG_DOEPMSK register ***********/
6506 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
6507 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
6508 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
6509 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
6510 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
6511 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
6512 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
6513 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
6515 /******************** Bit definition for USB_OTG_GINTSTS register ***********/
6516 #define USB_OTG_GINTSTS_CMOD 0x00000001U
6517 #define USB_OTG_GINTSTS_MMIS 0x00000002U
6518 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
6519 #define USB_OTG_GINTSTS_SOF 0x00000008U
6520 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
6521 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
6522 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
6523 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
6524 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
6525 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
6526 #define USB_OTG_GINTSTS_USBRST 0x00001000U
6527 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
6528 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
6529 #define USB_OTG_GINTSTS_EOPF 0x00008000U
6530 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
6531 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
6532 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
6533 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
6534 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
6535 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
6536 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
6537 #define USB_OTG_GINTSTS_HCINT 0x02000000U
6538 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
6539 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
6540 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
6541 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
6542 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
6543 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
6545 /******************** Bit definition for USB_OTG_GINTMSK register ***********/
6546 #define USB_OTG_GINTMSK_MMISM 0x00000002U
6547 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
6548 #define USB_OTG_GINTMSK_SOFM 0x00000008U
6549 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
6550 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
6551 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
6552 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
6553 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
6554 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
6555 #define USB_OTG_GINTMSK_USBRST 0x00001000U
6556 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
6557 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
6558 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
6559 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
6560 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
6561 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
6562 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
6563 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
6564 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
6565 #define USB_OTG_GINTMSK_RSTDETM 0x00800000U
6566 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
6567 #define USB_OTG_GINTMSK_HCIM 0x02000000U
6568 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
6569 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
6570 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
6571 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
6572 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
6573 #define USB_OTG_GINTMSK_WUIM 0x80000000U
6575 /******************** Bit definition for USB_OTG_DAINT register *************/
6576 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
6577 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
6579 /******************** Bit definition for USB_OTG_HAINTMSK register **********/
6580 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
6582 /******************** Bit definition for USB_OTG_GRXSTSP register ***********/
6583 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
6584 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
6585 #define USB_OTG_GRXSTSP_DPID 0x00018000U
6586 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
6588 /******************** Bit definition for USB_OTG_DAINTMSK register **********/
6589 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
6590 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
6592 /******************** Bit definition for OTG register ***********************/
6593 
6594 #define USB_OTG_CHNUM 0x0000000FU
6595 #define USB_OTG_CHNUM_0 0x00000001U
6596 #define USB_OTG_CHNUM_1 0x00000002U
6597 #define USB_OTG_CHNUM_2 0x00000004U
6598 #define USB_OTG_CHNUM_3 0x00000008U
6599 #define USB_OTG_BCNT 0x00007FF0U
6601 #define USB_OTG_DPID 0x00018000U
6602 #define USB_OTG_DPID_0 0x00008000U
6603 #define USB_OTG_DPID_1 0x00010000U
6605 #define USB_OTG_PKTSTS 0x001E0000U
6606 #define USB_OTG_PKTSTS_0 0x00020000U
6607 #define USB_OTG_PKTSTS_1 0x00040000U
6608 #define USB_OTG_PKTSTS_2 0x00080000U
6609 #define USB_OTG_PKTSTS_3 0x00100000U
6611 #define USB_OTG_EPNUM 0x0000000FU
6612 #define USB_OTG_EPNUM_0 0x00000001U
6613 #define USB_OTG_EPNUM_1 0x00000002U
6614 #define USB_OTG_EPNUM_2 0x00000004U
6615 #define USB_OTG_EPNUM_3 0x00000008U
6617 #define USB_OTG_FRMNUM 0x01E00000U
6618 #define USB_OTG_FRMNUM_0 0x00200000U
6619 #define USB_OTG_FRMNUM_1 0x00400000U
6620 #define USB_OTG_FRMNUM_2 0x00800000U
6621 #define USB_OTG_FRMNUM_3 0x01000000U
6623 /******************** Bit definition for OTG register ***********************/
6624 #define USB_OTG_CHNUM 0x0000000FU
6625 #define USB_OTG_CHNUM_0 0x00000001U
6626 #define USB_OTG_CHNUM_1 0x00000002U
6627 #define USB_OTG_CHNUM_2 0x00000004U
6628 #define USB_OTG_CHNUM_3 0x00000008U
6629 #define USB_OTG_BCNT 0x00007FF0U
6631 #define USB_OTG_DPID 0x00018000U
6632 #define USB_OTG_DPID_0 0x00008000U
6633 #define USB_OTG_DPID_1 0x00010000U
6635 #define USB_OTG_PKTSTS 0x001E0000U
6636 #define USB_OTG_PKTSTS_0 0x00020000U
6637 #define USB_OTG_PKTSTS_1 0x00040000U
6638 #define USB_OTG_PKTSTS_2 0x00080000U
6639 #define USB_OTG_PKTSTS_3 0x00100000U
6641 #define USB_OTG_EPNUM 0x0000000FU
6642 #define USB_OTG_EPNUM_0 0x00000001U
6643 #define USB_OTG_EPNUM_1 0x00000002U
6644 #define USB_OTG_EPNUM_2 0x00000004U
6645 #define USB_OTG_EPNUM_3 0x00000008U
6647 #define USB_OTG_FRMNUM 0x01E00000U
6648 #define USB_OTG_FRMNUM_0 0x00200000U
6649 #define USB_OTG_FRMNUM_1 0x00400000U
6650 #define USB_OTG_FRMNUM_2 0x00800000U
6651 #define USB_OTG_FRMNUM_3 0x01000000U
6653 /******************** Bit definition for USB_OTG_GRXFSIZ register ***********/
6654 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
6656 /******************** Bit definition for USB_OTG_DVBUSDIS register **********/
6657 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
6659 /******************** Bit definition for OTG register ***********************/
6660 #define USB_OTG_NPTXFSA 0x0000FFFFU
6661 #define USB_OTG_NPTXFD 0xFFFF0000U
6662 #define USB_OTG_TX0FSA 0x0000FFFFU
6663 #define USB_OTG_TX0FD 0xFFFF0000U
6665 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********/
6666 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
6668 /******************** Bit definition for USB_OTG_GNPTXSTS register **********/
6669 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
6671 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
6672 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
6673 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
6674 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
6675 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
6676 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
6677 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
6678 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
6679 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
6681 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
6682 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
6683 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
6684 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
6685 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
6686 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
6687 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
6688 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
6690 /******************** Bit definition for USB_OTG_DTHRCTL register ***********/
6691 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
6692 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
6694 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
6695 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
6696 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
6697 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
6698 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
6699 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
6700 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
6701 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
6702 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
6703 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
6704 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
6706 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
6707 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
6708 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
6709 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
6710 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
6711 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
6712 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
6713 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
6714 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
6715 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
6716 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
6718 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********/
6719 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
6721 /******************** Bit definition for USB_OTG_DEACHINT register **********/
6722 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
6723 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
6725 /******************** Bit definition for USB_OTG_GCCFG register *************/
6726 #define USB_OTG_GCCFG_DCDET 0x00000001U
6727 #define USB_OTG_GCCFG_PDET 0x00000002U
6728 #define USB_OTG_GCCFG_SDET 0x00000004U
6729 #define USB_OTG_GCCFG_PS2DET 0x00000008U
6730 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
6731 #define USB_OTG_GCCFG_BCDEN 0x00020000U
6732 #define USB_OTG_GCCFG_DCDEN 0x00040000U
6733 #define USB_OTG_GCCFG_PDEN 0x00080000U
6734 #define USB_OTG_GCCFG_SDEN 0x00100000U
6735 #define USB_OTG_GCCFG_VBDEN 0x00200000U
6737 /******************** Bit definition for USB_OTG_DEACHINTMSK register *******/
6738 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
6739 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
6741 /******************** Bit definition for USB_OTG_CID register ***************/
6742 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
6744 /******************** Bit definition for USB_OTG_GLPMCFG register ***********/
6745 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
6746 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
6747 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
6748 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
6749 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
6750 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
6751 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
6752 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
6753 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
6754 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
6755 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
6756 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
6757 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
6758 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
6759 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
6761 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******/
6762 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
6763 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
6764 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
6765 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
6766 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
6767 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
6768 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
6769 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
6770 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
6772 /******************** Bit definition for USB_OTG_HPRT register **************/
6773 #define USB_OTG_HPRT_PCSTS 0x00000001U
6774 #define USB_OTG_HPRT_PCDET 0x00000002U
6775 #define USB_OTG_HPRT_PENA 0x00000004U
6776 #define USB_OTG_HPRT_PENCHNG 0x00000008U
6777 #define USB_OTG_HPRT_POCA 0x00000010U
6778 #define USB_OTG_HPRT_POCCHNG 0x00000020U
6779 #define USB_OTG_HPRT_PRES 0x00000040U
6780 #define USB_OTG_HPRT_PSUSP 0x00000080U
6781 #define USB_OTG_HPRT_PRST 0x00000100U
6783 #define USB_OTG_HPRT_PLSTS 0x00000C00U
6784 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
6785 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
6786 #define USB_OTG_HPRT_PPWR 0x00001000U
6788 #define USB_OTG_HPRT_PTCTL 0x0001E000U
6789 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
6790 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
6791 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
6792 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
6794 #define USB_OTG_HPRT_PSPD 0x00060000U
6795 #define USB_OTG_HPRT_PSPD_0 0x00020000U
6796 #define USB_OTG_HPRT_PSPD_1 0x00040000U
6798 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******/
6799 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
6800 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
6801 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
6802 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
6803 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
6804 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
6805 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
6806 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
6807 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
6808 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
6809 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
6811 /******************** Bit definition for USB_OTG_HPTXFSIZ register **********/
6812 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
6813 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
6815 /******************** Bit definition for USB_OTG_DIEPCTL register ***********/
6816 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
6817 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
6818 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
6819 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
6821 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
6822 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
6823 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
6824 #define USB_OTG_DIEPCTL_STALL 0x00200000U
6826 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
6827 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
6828 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
6829 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
6830 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
6831 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
6832 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
6833 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
6834 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
6835 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
6836 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
6838 /******************** Bit definition for USB_OTG_HCCHAR register ************/
6839 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
6841 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
6842 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
6843 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
6844 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
6845 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
6846 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
6847 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
6849 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
6850 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
6851 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
6853 #define USB_OTG_HCCHAR_MC 0x00300000U
6854 #define USB_OTG_HCCHAR_MC_0 0x00100000U
6855 #define USB_OTG_HCCHAR_MC_1 0x00200000U
6857 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
6858 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
6859 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
6860 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
6861 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
6862 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
6863 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
6864 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
6865 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
6866 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
6867 #define USB_OTG_HCCHAR_CHENA 0x80000000U
6869 /******************** Bit definition for USB_OTG_HCSPLT register ************/
6870 
6871 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
6872 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
6873 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
6874 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
6875 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
6876 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
6877 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
6878 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
6880 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
6881 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
6882 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
6883 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
6884 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
6885 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
6886 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
6887 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
6889 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
6890 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
6891 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
6892 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
6893 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
6895 /******************** Bit definition for USB_OTG_HCINT register *************/
6896 #define USB_OTG_HCINT_XFRC 0x00000001U
6897 #define USB_OTG_HCINT_CHH 0x00000002U
6898 #define USB_OTG_HCINT_AHBERR 0x00000004U
6899 #define USB_OTG_HCINT_STALL 0x00000008U
6900 #define USB_OTG_HCINT_NAK 0x00000010U
6901 #define USB_OTG_HCINT_ACK 0x00000020U
6902 #define USB_OTG_HCINT_NYET 0x00000040U
6903 #define USB_OTG_HCINT_TXERR 0x00000080U
6904 #define USB_OTG_HCINT_BBERR 0x00000100U
6905 #define USB_OTG_HCINT_FRMOR 0x00000200U
6906 #define USB_OTG_HCINT_DTERR 0x00000400U
6908 /******************** Bit definition for USB_OTG_DIEPINT register ***********/
6909 #define USB_OTG_DIEPINT_XFRC 0x00000001U
6910 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
6911 #define USB_OTG_DIEPINT_TOC 0x00000008U
6912 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
6913 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
6914 #define USB_OTG_DIEPINT_TXFE 0x00000080U
6915 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
6916 #define USB_OTG_DIEPINT_BNA 0x00000200U
6917 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
6918 #define USB_OTG_DIEPINT_BERR 0x00001000U
6919 #define USB_OTG_DIEPINT_NAK 0x00002000U
6921 /******************** Bit definition for USB_OTG_HCINTMSK register **********/
6922 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
6923 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
6924 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
6925 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
6926 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
6927 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
6928 #define USB_OTG_HCINTMSK_NYET 0x00000040U
6929 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
6930 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
6931 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
6932 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
6934 /******************** Bit definition for USB_OTG_DIEPTSIZ register **********/
6935 
6936 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
6937 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
6938 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
6939 /******************** Bit definition for USB_OTG_HCTSIZ register ************/
6940 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
6941 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
6942 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
6943 #define USB_OTG_HCTSIZ_DPID 0x60000000U
6944 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
6945 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
6947 /******************** Bit definition for USB_OTG_DIEPDMA register ***********/
6948 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
6950 /******************** Bit definition for USB_OTG_HCDMA register *************/
6951 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
6953 /******************** Bit definition for USB_OTG_DTXFSTS register ***********/
6954 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
6956 /******************** Bit definition for USB_OTG_DIEPTXF register ***********/
6957 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
6958 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
6960 /******************** Bit definition for USB_OTG_DOEPCTL register ***********/
6961 
6962 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
6963 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
6964 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
6965 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
6966 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
6967 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
6968 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
6969 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
6970 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
6971 #define USB_OTG_DOEPCTL_STALL 0x00200000U
6972 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
6973 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
6974 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
6975 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
6977 /******************** Bit definition for USB_OTG_DOEPINT register ***********/
6978 #define USB_OTG_DOEPINT_XFRC 0x00000001U
6979 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
6980 #define USB_OTG_DOEPINT_STUP 0x00000008U
6981 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
6982 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
6983 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
6984 #define USB_OTG_DOEPINT_NYET 0x00004000U
6986 /******************** Bit definition for USB_OTG_DOEPTSIZ register **********/
6987 
6988 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
6989 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
6991 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
6992 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
6993 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
6995 /******************** Bit definition for PCGCCTL register *******************/
6996 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
6997 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
6998 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
7012 /******************************* ADC Instances ********************************/
7013 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
7014 
7015 /******************************* CAN Instances ********************************/
7016 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
7017  ((INSTANCE) == CAN2))
7018 /****************************** DFSDM Instances *******************************/
7019 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
7020  ((INSTANCE) == DFSDM1_Filter1))
7021 
7022 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
7023  ((INSTANCE) == DFSDM1_Channel1) || \
7024  ((INSTANCE) == DFSDM1_Channel2) || \
7025  ((INSTANCE) == DFSDM1_Channel3))
7026 
7027 /******************************* CRC Instances ********************************/
7028 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7029 
7030 /******************************** DMA Instances *******************************/
7031 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7032  ((INSTANCE) == DMA1_Stream1) || \
7033  ((INSTANCE) == DMA1_Stream2) || \
7034  ((INSTANCE) == DMA1_Stream3) || \
7035  ((INSTANCE) == DMA1_Stream4) || \
7036  ((INSTANCE) == DMA1_Stream5) || \
7037  ((INSTANCE) == DMA1_Stream6) || \
7038  ((INSTANCE) == DMA1_Stream7) || \
7039  ((INSTANCE) == DMA2_Stream0) || \
7040  ((INSTANCE) == DMA2_Stream1) || \
7041  ((INSTANCE) == DMA2_Stream2) || \
7042  ((INSTANCE) == DMA2_Stream3) || \
7043  ((INSTANCE) == DMA2_Stream4) || \
7044  ((INSTANCE) == DMA2_Stream5) || \
7045  ((INSTANCE) == DMA2_Stream6) || \
7046  ((INSTANCE) == DMA2_Stream7))
7047 
7048 /******************************* GPIO Instances *******************************/
7049 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7050  ((INSTANCE) == GPIOB) || \
7051  ((INSTANCE) == GPIOC) || \
7052  ((INSTANCE) == GPIOD) || \
7053  ((INSTANCE) == GPIOE) || \
7054  ((INSTANCE) == GPIOF) || \
7055  ((INSTANCE) == GPIOG) || \
7056  ((INSTANCE) == GPIOH))
7057 
7058 /******************************** I2C Instances *******************************/
7059 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7060  ((INSTANCE) == I2C2) || \
7061  ((INSTANCE) == I2C3))
7062 
7063 /******************************** I2S Instances *******************************/
7064 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7065  ((INSTANCE) == SPI2) || \
7066  ((INSTANCE) == SPI3) || \
7067  ((INSTANCE) == SPI4) || \
7068  ((INSTANCE) == SPI5))
7069 
7070 /*************************** I2S Extended Instances ***************************/
7071 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
7072  ((INSTANCE) == SPI3) || \
7073  ((INSTANCE) == I2S2ext) || \
7074  ((INSTANCE) == I2S3ext))
7075 
7076 /******************************* RNG Instances ********************************/
7077 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
7078 
7079 /****************************** RTC Instances *********************************/
7080 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7081 
7082 /******************************** SPI Instances *******************************/
7083 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7084  ((INSTANCE) == SPI2) || \
7085  ((INSTANCE) == SPI3) || \
7086  ((INSTANCE) == SPI4) || \
7087  ((INSTANCE) == SPI5))
7088 /*************************** SPI Extended Instances ***************************/
7089 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
7090  ((INSTANCE) == SPI2) || \
7091  ((INSTANCE) == SPI3) || \
7092  ((INSTANCE) == SPI4) || \
7093  ((INSTANCE) == SPI5) || \
7094  ((INSTANCE) == I2S2ext) || \
7095  ((INSTANCE) == I2S3ext))
7096 
7097 /****************** TIM Instances : All supported instances *******************/
7098 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7099  ((INSTANCE) == TIM2) || \
7100  ((INSTANCE) == TIM3) || \
7101  ((INSTANCE) == TIM4) || \
7102  ((INSTANCE) == TIM5) || \
7103  ((INSTANCE) == TIM6) || \
7104  ((INSTANCE) == TIM7) || \
7105  ((INSTANCE) == TIM8) || \
7106  ((INSTANCE) == TIM9) || \
7107  ((INSTANCE) == TIM10) || \
7108  ((INSTANCE) == TIM11) || \
7109  ((INSTANCE) == TIM12) || \
7110  ((INSTANCE) == TIM13) || \
7111  ((INSTANCE) == TIM14))
7112 
7113 /************* TIM Instances : at least 1 capture/compare channel *************/
7114 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7115  ((INSTANCE) == TIM2) || \
7116  ((INSTANCE) == TIM3) || \
7117  ((INSTANCE) == TIM4) || \
7118  ((INSTANCE) == TIM5) || \
7119  ((INSTANCE) == TIM8) || \
7120  ((INSTANCE) == TIM9) || \
7121  ((INSTANCE) == TIM10) || \
7122  ((INSTANCE) == TIM11) || \
7123  ((INSTANCE) == TIM12) || \
7124  ((INSTANCE) == TIM13) || \
7125  ((INSTANCE) == TIM14))
7126 
7127 /************ TIM Instances : at least 2 capture/compare channels *************/
7128 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7129  ((INSTANCE) == TIM2) || \
7130  ((INSTANCE) == TIM3) || \
7131  ((INSTANCE) == TIM4) || \
7132  ((INSTANCE) == TIM5) || \
7133  ((INSTANCE) == TIM8) || \
7134  ((INSTANCE) == TIM9) || \
7135  ((INSTANCE) == TIM12))
7136 
7137 /************ TIM Instances : at least 3 capture/compare channels *************/
7138 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7139  ((INSTANCE) == TIM2) || \
7140  ((INSTANCE) == TIM3) || \
7141  ((INSTANCE) == TIM4) || \
7142  ((INSTANCE) == TIM5) || \
7143  ((INSTANCE) == TIM8))
7144 
7145 /************ TIM Instances : at least 4 capture/compare channels *************/
7146 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7147  ((INSTANCE) == TIM2) || \
7148  ((INSTANCE) == TIM3) || \
7149  ((INSTANCE) == TIM4) || \
7150  ((INSTANCE) == TIM5) || \
7151  ((INSTANCE) == TIM8))
7152 
7153 /******************** TIM Instances : Advanced-control timers *****************/
7154 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7155  ((INSTANCE) == TIM8))
7156 
7157 /******************* TIM Instances : Timer input XOR function *****************/
7158 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7159  ((INSTANCE) == TIM2) || \
7160  ((INSTANCE) == TIM3) || \
7161  ((INSTANCE) == TIM4) || \
7162  ((INSTANCE) == TIM5) || \
7163  ((INSTANCE) == TIM8))
7164 
7165 /****************** TIM Instances : DMA requests generation (UDE) *************/
7166 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7167  ((INSTANCE) == TIM2) || \
7168  ((INSTANCE) == TIM3) || \
7169  ((INSTANCE) == TIM4) || \
7170  ((INSTANCE) == TIM5) || \
7171  ((INSTANCE) == TIM6) || \
7172  ((INSTANCE) == TIM7) || \
7173  ((INSTANCE) == TIM8))
7174 
7175 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
7176 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7177  ((INSTANCE) == TIM2) || \
7178  ((INSTANCE) == TIM3) || \
7179  ((INSTANCE) == TIM4) || \
7180  ((INSTANCE) == TIM5) || \
7181  ((INSTANCE) == TIM8))
7182 
7183 /************ TIM Instances : DMA requests generation (COMDE) *****************/
7184 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7185  ((INSTANCE) == TIM2) || \
7186  ((INSTANCE) == TIM3) || \
7187  ((INSTANCE) == TIM4) || \
7188  ((INSTANCE) == TIM5) || \
7189  ((INSTANCE) == TIM8))
7190 
7191 /******************** TIM Instances : DMA burst feature ***********************/
7192 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7193  ((INSTANCE) == TIM2) || \
7194  ((INSTANCE) == TIM3) || \
7195  ((INSTANCE) == TIM4) || \
7196  ((INSTANCE) == TIM5) || \
7197  ((INSTANCE) == TIM8))
7198 
7199 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
7200 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7201  ((INSTANCE) == TIM2) || \
7202  ((INSTANCE) == TIM3) || \
7203  ((INSTANCE) == TIM4) || \
7204  ((INSTANCE) == TIM5) || \
7205  ((INSTANCE) == TIM6) || \
7206  ((INSTANCE) == TIM7) || \
7207  ((INSTANCE) == TIM8) || \
7208  ((INSTANCE) == TIM9) || \
7209  ((INSTANCE) == TIM12))
7210 
7211 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7212 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7213  ((INSTANCE) == TIM2) || \
7214  ((INSTANCE) == TIM3) || \
7215  ((INSTANCE) == TIM4) || \
7216  ((INSTANCE) == TIM5) || \
7217  ((INSTANCE) == TIM8) || \
7218  ((INSTANCE) == TIM9) || \
7219  ((INSTANCE) == TIM12))
7220 
7221 /********************** TIM Instances : 32 bit Counter ************************/
7222 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
7223  ((INSTANCE) == TIM5))
7224 
7225 /***************** TIM Instances : external trigger input available ************/
7226 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7227  ((INSTANCE) == TIM2) || \
7228  ((INSTANCE) == TIM3) || \
7229  ((INSTANCE) == TIM4) || \
7230  ((INSTANCE) == TIM5) || \
7231  ((INSTANCE) == TIM8))
7232 
7233 /****************** TIM Instances : remapping capability **********************/
7234 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7235  ((INSTANCE) == TIM5) || \
7236  ((INSTANCE) == TIM11))
7237 
7238 /******************* TIM Instances : output(s) available **********************/
7239 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7240  ((((INSTANCE) == TIM1) && \
7241  (((CHANNEL) == TIM_CHANNEL_1) || \
7242  ((CHANNEL) == TIM_CHANNEL_2) || \
7243  ((CHANNEL) == TIM_CHANNEL_3) || \
7244  ((CHANNEL) == TIM_CHANNEL_4))) \
7245  || \
7246  (((INSTANCE) == TIM2) && \
7247  (((CHANNEL) == TIM_CHANNEL_1) || \
7248  ((CHANNEL) == TIM_CHANNEL_2) || \
7249  ((CHANNEL) == TIM_CHANNEL_3) || \
7250  ((CHANNEL) == TIM_CHANNEL_4))) \
7251  || \
7252  (((INSTANCE) == TIM3) && \
7253  (((CHANNEL) == TIM_CHANNEL_1) || \
7254  ((CHANNEL) == TIM_CHANNEL_2) || \
7255  ((CHANNEL) == TIM_CHANNEL_3) || \
7256  ((CHANNEL) == TIM_CHANNEL_4))) \
7257  || \
7258  (((INSTANCE) == TIM4) && \
7259  (((CHANNEL) == TIM_CHANNEL_1) || \
7260  ((CHANNEL) == TIM_CHANNEL_2) || \
7261  ((CHANNEL) == TIM_CHANNEL_3) || \
7262  ((CHANNEL) == TIM_CHANNEL_4))) \
7263  || \
7264  (((INSTANCE) == TIM5) && \
7265  (((CHANNEL) == TIM_CHANNEL_1) || \
7266  ((CHANNEL) == TIM_CHANNEL_2) || \
7267  ((CHANNEL) == TIM_CHANNEL_3) || \
7268  ((CHANNEL) == TIM_CHANNEL_4))) \
7269  || \
7270  (((INSTANCE) == TIM8) && \
7271  (((CHANNEL) == TIM_CHANNEL_1) || \
7272  ((CHANNEL) == TIM_CHANNEL_2) || \
7273  ((CHANNEL) == TIM_CHANNEL_3) || \
7274  ((CHANNEL) == TIM_CHANNEL_4))) \
7275  || \
7276  (((INSTANCE) == TIM9) && \
7277  (((CHANNEL) == TIM_CHANNEL_1) || \
7278  ((CHANNEL) == TIM_CHANNEL_2))) \
7279  || \
7280  (((INSTANCE) == TIM10) && \
7281  (((CHANNEL) == TIM_CHANNEL_1))) \
7282  || \
7283  (((INSTANCE) == TIM11) && \
7284  (((CHANNEL) == TIM_CHANNEL_1))) \
7285  || \
7286  (((INSTANCE) == TIM12) && \
7287  (((CHANNEL) == TIM_CHANNEL_1) || \
7288  ((CHANNEL) == TIM_CHANNEL_2))) \
7289  || \
7290  (((INSTANCE) == TIM13) && \
7291  (((CHANNEL) == TIM_CHANNEL_1))) \
7292  || \
7293  (((INSTANCE) == TIM14) && \
7294  (((CHANNEL) == TIM_CHANNEL_1))))
7295 
7296 /************ TIM Instances : complementary output(s) available ***************/
7297 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
7298  ((((INSTANCE) == TIM1) && \
7299  (((CHANNEL) == TIM_CHANNEL_1) || \
7300  ((CHANNEL) == TIM_CHANNEL_2) || \
7301  ((CHANNEL) == TIM_CHANNEL_3))) \
7302  || \
7303  (((INSTANCE) == TIM8) && \
7304  (((CHANNEL) == TIM_CHANNEL_1) || \
7305  ((CHANNEL) == TIM_CHANNEL_2) || \
7306  ((CHANNEL) == TIM_CHANNEL_3))))
7307 
7308 /******************** USART Instances : Synchronous mode **********************/
7309 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7310  ((INSTANCE) == USART2) || \
7311  ((INSTANCE) == USART3) || \
7312  ((INSTANCE) == USART6))
7313 
7314 /******************** UART Instances : Asynchronous mode **********************/
7315 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7316  ((INSTANCE) == USART2) || \
7317  ((INSTANCE) == USART3) || \
7318  ((INSTANCE) == USART6))
7319 
7320 /****************** UART Instances : Hardware Flow control ********************/
7321 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7322  ((INSTANCE) == USART2) || \
7323  ((INSTANCE) == USART3))
7324 
7325 /********************* UART Instances : Smart card mode ***********************/
7326 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7327  ((INSTANCE) == USART2) || \
7328  ((INSTANCE) == USART3) || \
7329  ((INSTANCE) == USART6))
7330 
7331 /*********************** UART Instances : IRDA mode ***************************/
7332 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7333  ((INSTANCE) == USART2) || \
7334  ((INSTANCE) == USART3) || \
7335  ((INSTANCE) == USART6))
7336 
7337 /*********************** PCD Instances ****************************************/
7338 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
7339 
7340 /*********************** HCD Instances ****************************************/
7341 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
7342 
7343 /****************************** IWDG Instances ********************************/
7344 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
7345 
7346 /****************************** WWDG Instances ********************************/
7347 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
7348 
7349 /****************************** QSPI Instances ********************************/
7350 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
7351 
7352 /***************************** FMPI2C Instances *******************************/
7353 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
7354 
7355 /****************************** SDIO Instances ********************************/
7356 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
7357 
7358 /****************************** USB Instances ********************************/
7359 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
7360 
7361 /****************************** USB Exported Constants ************************/
7362 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
7363 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
7364 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
7365 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
7366 
7367 
7380 #ifdef __cplusplus
7381 }
7382 #endif /* __cplusplus */
7383 
7384 #endif /* __STM32F412Rx_H */
7385 
7386 
7387 
7388 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32f412rx.h:659
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
TAMP_STAMP_IRQn
Definition: stm32f412rx.h:99
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f405xx.h:395
QUADSPI_IRQn
Definition: stm32f412rx.h:172
TIM2_IRQn
Definition: stm32f412rx.h:125
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f412rx.h:647
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f412rx.h:123
EXTI2_IRQn
Definition: stm32f412rx.h:105
EXTI4_IRQn
Definition: stm32f412rx.h:107
USART1_IRQn
Definition: stm32f412rx.h:134
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
DFSDM1_FLT1_IRQn
Definition: stm32f412rx.h:156
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f412rx.h:142
TIM4_IRQn
Definition: stm32f412rx.h:127
RTC_Alarm_IRQn
Definition: stm32f412rx.h:138
CAN2_SCE_IRQn
Definition: stm32f412rx.h:160
PendSV_IRQn
Definition: stm32f412rx.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f412rx.h:100
CAN1_RX1_IRQn
Definition: stm32f412rx.h:118
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32f412rx.h:657
CAN1_TX_IRQn
Definition: stm32f412rx.h:116
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f412rx.h:132
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
OTG_FS_WKUP_IRQn
Definition: stm32f412rx.h:139
DMA_TypeDef
Definition: stm32f401xc.h:243
DMA1_Stream2_IRQn
Definition: stm32f412rx.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f412rx.h:133
FMPI2C1_ER_IRQn
Definition: stm32f412rx.h:174
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32f412rx.h:654
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f412rx.h:648
__I
#define __I
Definition: core_cm0.h:210
RNG_IRQn
Definition: stm32f412rx.h:168
DMA2_Stream5_IRQn
Definition: stm32f412rx.h:162
ADC_IRQn
Definition: stm32f412rx.h:115
CAN1_RX0_IRQn
Definition: stm32f412rx.h:117
TIM6_IRQn
Definition: stm32f412rx.h:148
RCC_IRQn
Definition: stm32f412rx.h:102
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f412rx.h:93
DMA2_Stream3_IRQn
Definition: stm32f412rx.h:153
NonMaskableInt_IRQn
Definition: stm32f412rx.h:88
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f412rx.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f412rx.h:141
DMA1_Stream1_IRQn
Definition: stm32f412rx.h:109
DMA2_Stream7_IRQn
Definition: stm32f412rx.h:164
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f412rx.h:645
DMA2_Stream6_IRQn
Definition: stm32f412rx.h:163
BusFault_IRQn
Definition: stm32f412rx.h:90
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
I2C3_ER_IRQn
Definition: stm32f412rx.h:167
CAN2_RX0_IRQn
Definition: stm32f412rx.h:158
USART6_IRQn
Definition: stm32f412rx.h:165
PVD_IRQn
Definition: stm32f412rx.h:98
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f412rx.h:112
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32f412rx.h:651
DMA1_Stream0_IRQn
Definition: stm32f412rx.h:108
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f412rx.h:170
TIM8_CC_IRQn
Definition: stm32f412rx.h:143
DMA1_Stream3_IRQn
Definition: stm32f412rx.h:111
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f412rx.h:655
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32f412rx.h:658
FPU_IRQn
Definition: stm32f412rx.h:169
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
OTG_FS_IRQn
Definition: stm32f412rx.h:161
DMA2_Stream2_IRQn
Definition: stm32f412rx.h:152
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f412rx.h:652
SDIO_IRQn
Definition: stm32f412rx.h:145
FMPI2C1_EV_IRQn
Definition: stm32f412rx.h:173
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32f412cx.h:299
I2C3_EV_IRQn
Definition: stm32f412rx.h:166
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f412rx.h:649
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f412rx.h:135
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f412rx.h:149
I2C2_EV_IRQn
Definition: stm32f412rx.h:130
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f412rx.h:126
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f412rx.h:104
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32f412cx.h:321
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f412rx.h:650
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f412rx.h:92
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f412rx.h:124
DFSDM1_FLT0_IRQn
Definition: stm32f412rx.h:155
TIM8_BRK_TIM12_IRQn
Definition: stm32f412rx.h:140
FLASH_IRQn
Definition: stm32f412rx.h:101
DMA1_Stream5_IRQn
Definition: stm32f412rx.h:113
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f412rx.h:95
TIM1_UP_TIM10_IRQn
Definition: stm32f412rx.h:122
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f412rx.h:131
UsageFault_IRQn
Definition: stm32f412rx.h:91
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f405xx.h:404
SPI3_IRQn
Definition: stm32f412rx.h:147
DMA2_Stream1_IRQn
Definition: stm32f412rx.h:151
EXTI9_5_IRQn
Definition: stm32f412rx.h:120
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f412rx.h:128
DMA1_Stream6_IRQn
Definition: stm32f412rx.h:114
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32f412rx.h:656
I2C1_ER_IRQn
Definition: stm32f412rx.h:129
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
FMPI2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f410cx.h:354
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
CAN2_RX1_IRQn
Definition: stm32f412rx.h:159
DMA2_Stream4_IRQn
Definition: stm32f412rx.h:154
WWDG_IRQn
Definition: stm32f412rx.h:97
DMA1_Stream7_IRQn
Definition: stm32f412rx.h:144
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
SPI5_IRQn
Definition: stm32f412rx.h:171
EXTI15_10_IRQn
Definition: stm32f412rx.h:137
CAN1_SCE_IRQn
Definition: stm32f412rx.h:119
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f412rx.h:103
DMA2_Stream0_IRQn
Definition: stm32f412rx.h:150
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32f412rx.h:653
TIM1_BRK_TIM9_IRQn
Definition: stm32f412rx.h:121
CAN2_TX_IRQn
Definition: stm32f412rx.h:157
TIM5_IRQn
Definition: stm32f412rx.h:146
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f412rx.h:106
USART3_IRQn
Definition: stm32f412rx.h:136
MemoryManagement_IRQn
Definition: stm32f412rx.h:89