STM CMSIS
stm32f415xx.h
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1 
52 #ifndef __STM32F415xx_H
53 #define __STM32F415xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  CAN1_TX_IRQn = 19,
117  CAN1_RX0_IRQn = 20,
118  CAN1_RX1_IRQn = 21,
119  CAN1_SCE_IRQn = 22,
120  EXTI9_5_IRQn = 23,
121  TIM1_BRK_TIM9_IRQn = 24,
122  TIM1_UP_TIM10_IRQn = 25,
123  TIM1_TRG_COM_TIM11_IRQn = 26,
124  TIM1_CC_IRQn = 27,
125  TIM2_IRQn = 28,
126  TIM3_IRQn = 29,
127  TIM4_IRQn = 30,
128  I2C1_EV_IRQn = 31,
129  I2C1_ER_IRQn = 32,
130  I2C2_EV_IRQn = 33,
131  I2C2_ER_IRQn = 34,
132  SPI1_IRQn = 35,
133  SPI2_IRQn = 36,
134  USART1_IRQn = 37,
135  USART2_IRQn = 38,
136  USART3_IRQn = 39,
137  EXTI15_10_IRQn = 40,
138  RTC_Alarm_IRQn = 41,
139  OTG_FS_WKUP_IRQn = 42,
140  TIM8_BRK_TIM12_IRQn = 43,
141  TIM8_UP_TIM13_IRQn = 44,
142  TIM8_TRG_COM_TIM14_IRQn = 45,
143  TIM8_CC_IRQn = 46,
144  DMA1_Stream7_IRQn = 47,
145  FSMC_IRQn = 48,
146  SDIO_IRQn = 49,
147  TIM5_IRQn = 50,
148  SPI3_IRQn = 51,
149  UART4_IRQn = 52,
150  UART5_IRQn = 53,
151  TIM6_DAC_IRQn = 54,
152  TIM7_IRQn = 55,
153  DMA2_Stream0_IRQn = 56,
154  DMA2_Stream1_IRQn = 57,
155  DMA2_Stream2_IRQn = 58,
156  DMA2_Stream3_IRQn = 59,
157  DMA2_Stream4_IRQn = 60,
158  CAN2_TX_IRQn = 63,
159  CAN2_RX0_IRQn = 64,
160  CAN2_RX1_IRQn = 65,
161  CAN2_SCE_IRQn = 66,
162  OTG_FS_IRQn = 67,
163  DMA2_Stream5_IRQn = 68,
164  DMA2_Stream6_IRQn = 69,
165  DMA2_Stream7_IRQn = 70,
166  USART6_IRQn = 71,
167  I2C3_EV_IRQn = 72,
168  I2C3_ER_IRQn = 73,
169  OTG_HS_EP1_OUT_IRQn = 74,
170  OTG_HS_EP1_IN_IRQn = 75,
171  OTG_HS_WKUP_IRQn = 76,
172  OTG_HS_IRQn = 77,
173  CRYP_IRQn = 79,
174  HASH_RNG_IRQn = 80,
175  FPU_IRQn = 81
176 } IRQn_Type;
177 
182 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
183 #include "system_stm32f4xx.h"
184 #include <stdint.h>
185 
194 typedef struct
195 {
196  __IO uint32_t SR;
197  __IO uint32_t CR1;
198  __IO uint32_t CR2;
199  __IO uint32_t SMPR1;
200  __IO uint32_t SMPR2;
201  __IO uint32_t JOFR1;
202  __IO uint32_t JOFR2;
203  __IO uint32_t JOFR3;
204  __IO uint32_t JOFR4;
205  __IO uint32_t HTR;
206  __IO uint32_t LTR;
207  __IO uint32_t SQR1;
208  __IO uint32_t SQR2;
209  __IO uint32_t SQR3;
210  __IO uint32_t JSQR;
211  __IO uint32_t JDR1;
212  __IO uint32_t JDR2;
213  __IO uint32_t JDR3;
214  __IO uint32_t JDR4;
215  __IO uint32_t DR;
216 } ADC_TypeDef;
217 
218 typedef struct
219 {
220  __IO uint32_t CSR;
221  __IO uint32_t CCR;
222  __IO uint32_t CDR;
224 } ADC_Common_TypeDef;
225 
226 
231 typedef struct
232 {
233  __IO uint32_t TIR;
234  __IO uint32_t TDTR;
235  __IO uint32_t TDLR;
236  __IO uint32_t TDHR;
237 } CAN_TxMailBox_TypeDef;
238 
243 typedef struct
244 {
245  __IO uint32_t RIR;
246  __IO uint32_t RDTR;
247  __IO uint32_t RDLR;
248  __IO uint32_t RDHR;
249 } CAN_FIFOMailBox_TypeDef;
250 
255 typedef struct
256 {
257  __IO uint32_t FR1;
258  __IO uint32_t FR2;
259 } CAN_FilterRegister_TypeDef;
260 
265 typedef struct
266 {
267  __IO uint32_t MCR;
268  __IO uint32_t MSR;
269  __IO uint32_t TSR;
270  __IO uint32_t RF0R;
271  __IO uint32_t RF1R;
272  __IO uint32_t IER;
273  __IO uint32_t ESR;
274  __IO uint32_t BTR;
275  uint32_t RESERVED0[88];
276  CAN_TxMailBox_TypeDef sTxMailBox[3];
277  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
278  uint32_t RESERVED1[12];
279  __IO uint32_t FMR;
280  __IO uint32_t FM1R;
281  uint32_t RESERVED2;
282  __IO uint32_t FS1R;
283  uint32_t RESERVED3;
284  __IO uint32_t FFA1R;
285  uint32_t RESERVED4;
286  __IO uint32_t FA1R;
287  uint32_t RESERVED5[8];
288  CAN_FilterRegister_TypeDef sFilterRegister[28];
289 } CAN_TypeDef;
290 
295 typedef struct
296 {
297  __IO uint32_t DR;
298  __IO uint8_t IDR;
299  uint8_t RESERVED0;
300  uint16_t RESERVED1;
301  __IO uint32_t CR;
302 } CRC_TypeDef;
303 
308 typedef struct
309 {
310  __IO uint32_t CR;
311  __IO uint32_t SWTRIGR;
312  __IO uint32_t DHR12R1;
313  __IO uint32_t DHR12L1;
314  __IO uint32_t DHR8R1;
315  __IO uint32_t DHR12R2;
316  __IO uint32_t DHR12L2;
317  __IO uint32_t DHR8R2;
318  __IO uint32_t DHR12RD;
319  __IO uint32_t DHR12LD;
320  __IO uint32_t DHR8RD;
321  __IO uint32_t DOR1;
322  __IO uint32_t DOR2;
323  __IO uint32_t SR;
324 } DAC_TypeDef;
325 
330 typedef struct
331 {
332  __IO uint32_t IDCODE;
333  __IO uint32_t CR;
334  __IO uint32_t APB1FZ;
335  __IO uint32_t APB2FZ;
336 }DBGMCU_TypeDef;
337 
338 
343 typedef struct
344 {
345  __IO uint32_t CR;
346  __IO uint32_t NDTR;
347  __IO uint32_t PAR;
348  __IO uint32_t M0AR;
349  __IO uint32_t M1AR;
350  __IO uint32_t FCR;
351 } DMA_Stream_TypeDef;
352 
353 typedef struct
354 {
355  __IO uint32_t LISR;
356  __IO uint32_t HISR;
357  __IO uint32_t LIFCR;
358  __IO uint32_t HIFCR;
359 } DMA_TypeDef;
360 
361 
366 typedef struct
367 {
368  __IO uint32_t IMR;
369  __IO uint32_t EMR;
370  __IO uint32_t RTSR;
371  __IO uint32_t FTSR;
372  __IO uint32_t SWIER;
373  __IO uint32_t PR;
374 } EXTI_TypeDef;
375 
380 typedef struct
381 {
382  __IO uint32_t ACR;
383  __IO uint32_t KEYR;
384  __IO uint32_t OPTKEYR;
385  __IO uint32_t SR;
386  __IO uint32_t CR;
387  __IO uint32_t OPTCR;
388  __IO uint32_t OPTCR1;
389 } FLASH_TypeDef;
390 
391 
396 typedef struct
397 {
398  __IO uint32_t BTCR[8];
399 } FSMC_Bank1_TypeDef;
400 
405 typedef struct
406 {
407  __IO uint32_t BWTR[7];
408 } FSMC_Bank1E_TypeDef;
409 
414 typedef struct
415 {
416  __IO uint32_t PCR2;
417  __IO uint32_t SR2;
418  __IO uint32_t PMEM2;
419  __IO uint32_t PATT2;
420  uint32_t RESERVED0;
421  __IO uint32_t ECCR2;
422  uint32_t RESERVED1;
423  uint32_t RESERVED2;
424  __IO uint32_t PCR3;
425  __IO uint32_t SR3;
426  __IO uint32_t PMEM3;
427  __IO uint32_t PATT3;
428  uint32_t RESERVED3;
429  __IO uint32_t ECCR3;
430 } FSMC_Bank2_3_TypeDef;
431 
436 typedef struct
437 {
438  __IO uint32_t PCR4;
439  __IO uint32_t SR4;
440  __IO uint32_t PMEM4;
441  __IO uint32_t PATT4;
442  __IO uint32_t PIO4;
443 } FSMC_Bank4_TypeDef;
444 
445 
450 typedef struct
451 {
452  __IO uint32_t MODER;
453  __IO uint32_t OTYPER;
454  __IO uint32_t OSPEEDR;
455  __IO uint32_t PUPDR;
456  __IO uint32_t IDR;
457  __IO uint32_t ODR;
458  __IO uint32_t BSRR;
459  __IO uint32_t LCKR;
460  __IO uint32_t AFR[2];
461 } GPIO_TypeDef;
462 
467 typedef struct
468 {
469  __IO uint32_t MEMRMP;
470  __IO uint32_t PMC;
471  __IO uint32_t EXTICR[4];
472  uint32_t RESERVED[2];
473  __IO uint32_t CMPCR;
474 } SYSCFG_TypeDef;
475 
480 typedef struct
481 {
482  __IO uint32_t CR1;
483  __IO uint32_t CR2;
484  __IO uint32_t OAR1;
485  __IO uint32_t OAR2;
486  __IO uint32_t DR;
487  __IO uint32_t SR1;
488  __IO uint32_t SR2;
489  __IO uint32_t CCR;
490  __IO uint32_t TRISE;
491  __IO uint32_t FLTR;
492 } I2C_TypeDef;
493 
498 typedef struct
499 {
500  __IO uint32_t KR;
501  __IO uint32_t PR;
502  __IO uint32_t RLR;
503  __IO uint32_t SR;
504 } IWDG_TypeDef;
505 
510 typedef struct
511 {
512  __IO uint32_t CR;
513  __IO uint32_t CSR;
514 } PWR_TypeDef;
515 
520 typedef struct
521 {
522  __IO uint32_t CR;
523  __IO uint32_t PLLCFGR;
524  __IO uint32_t CFGR;
525  __IO uint32_t CIR;
526  __IO uint32_t AHB1RSTR;
527  __IO uint32_t AHB2RSTR;
528  __IO uint32_t AHB3RSTR;
529  uint32_t RESERVED0;
530  __IO uint32_t APB1RSTR;
531  __IO uint32_t APB2RSTR;
532  uint32_t RESERVED1[2];
533  __IO uint32_t AHB1ENR;
534  __IO uint32_t AHB2ENR;
535  __IO uint32_t AHB3ENR;
536  uint32_t RESERVED2;
537  __IO uint32_t APB1ENR;
538  __IO uint32_t APB2ENR;
539  uint32_t RESERVED3[2];
540  __IO uint32_t AHB1LPENR;
541  __IO uint32_t AHB2LPENR;
542  __IO uint32_t AHB3LPENR;
543  uint32_t RESERVED4;
544  __IO uint32_t APB1LPENR;
545  __IO uint32_t APB2LPENR;
546  uint32_t RESERVED5[2];
547  __IO uint32_t BDCR;
548  __IO uint32_t CSR;
549  uint32_t RESERVED6[2];
550  __IO uint32_t SSCGR;
551  __IO uint32_t PLLI2SCFGR;
553 } RCC_TypeDef;
554 
559 typedef struct
560 {
561  __IO uint32_t TR;
562  __IO uint32_t DR;
563  __IO uint32_t CR;
564  __IO uint32_t ISR;
565  __IO uint32_t PRER;
566  __IO uint32_t WUTR;
567  __IO uint32_t CALIBR;
568  __IO uint32_t ALRMAR;
569  __IO uint32_t ALRMBR;
570  __IO uint32_t WPR;
571  __IO uint32_t SSR;
572  __IO uint32_t SHIFTR;
573  __IO uint32_t TSTR;
574  __IO uint32_t TSDR;
575  __IO uint32_t TSSSR;
576  __IO uint32_t CALR;
577  __IO uint32_t TAFCR;
578  __IO uint32_t ALRMASSR;
579  __IO uint32_t ALRMBSSR;
580  uint32_t RESERVED7;
581  __IO uint32_t BKP0R;
582  __IO uint32_t BKP1R;
583  __IO uint32_t BKP2R;
584  __IO uint32_t BKP3R;
585  __IO uint32_t BKP4R;
586  __IO uint32_t BKP5R;
587  __IO uint32_t BKP6R;
588  __IO uint32_t BKP7R;
589  __IO uint32_t BKP8R;
590  __IO uint32_t BKP9R;
591  __IO uint32_t BKP10R;
592  __IO uint32_t BKP11R;
593  __IO uint32_t BKP12R;
594  __IO uint32_t BKP13R;
595  __IO uint32_t BKP14R;
596  __IO uint32_t BKP15R;
597  __IO uint32_t BKP16R;
598  __IO uint32_t BKP17R;
599  __IO uint32_t BKP18R;
600  __IO uint32_t BKP19R;
601 } RTC_TypeDef;
602 
603 
608 typedef struct
609 {
610  __IO uint32_t POWER;
611  __IO uint32_t CLKCR;
612  __IO uint32_t ARG;
613  __IO uint32_t CMD;
614  __I uint32_t RESPCMD;
615  __I uint32_t RESP1;
616  __I uint32_t RESP2;
617  __I uint32_t RESP3;
618  __I uint32_t RESP4;
619  __IO uint32_t DTIMER;
620  __IO uint32_t DLEN;
621  __IO uint32_t DCTRL;
622  __I uint32_t DCOUNT;
623  __I uint32_t STA;
624  __IO uint32_t ICR;
625  __IO uint32_t MASK;
626  uint32_t RESERVED0[2];
627  __I uint32_t FIFOCNT;
628  uint32_t RESERVED1[13];
629  __IO uint32_t FIFO;
630 } SDIO_TypeDef;
631 
636 typedef struct
637 {
638  __IO uint32_t CR1;
639  __IO uint32_t CR2;
640  __IO uint32_t SR;
641  __IO uint32_t DR;
642  __IO uint32_t CRCPR;
643  __IO uint32_t RXCRCR;
644  __IO uint32_t TXCRCR;
645  __IO uint32_t I2SCFGR;
646  __IO uint32_t I2SPR;
647 } SPI_TypeDef;
648 
653 typedef struct
654 {
655  __IO uint32_t CR1;
656  __IO uint32_t CR2;
657  __IO uint32_t SMCR;
658  __IO uint32_t DIER;
659  __IO uint32_t SR;
660  __IO uint32_t EGR;
661  __IO uint32_t CCMR1;
662  __IO uint32_t CCMR2;
663  __IO uint32_t CCER;
664  __IO uint32_t CNT;
665  __IO uint32_t PSC;
666  __IO uint32_t ARR;
667  __IO uint32_t RCR;
668  __IO uint32_t CCR1;
669  __IO uint32_t CCR2;
670  __IO uint32_t CCR3;
671  __IO uint32_t CCR4;
672  __IO uint32_t BDTR;
673  __IO uint32_t DCR;
674  __IO uint32_t DMAR;
675  __IO uint32_t OR;
676 } TIM_TypeDef;
677 
682 typedef struct
683 {
684  __IO uint32_t SR;
685  __IO uint32_t DR;
686  __IO uint32_t BRR;
687  __IO uint32_t CR1;
688  __IO uint32_t CR2;
689  __IO uint32_t CR3;
690  __IO uint32_t GTPR;
691 } USART_TypeDef;
692 
697 typedef struct
698 {
699  __IO uint32_t CR;
700  __IO uint32_t CFR;
701  __IO uint32_t SR;
702 } WWDG_TypeDef;
703 
708 typedef struct
709 {
710  __IO uint32_t CR;
711  __IO uint32_t SR;
712  __IO uint32_t DR;
713  __IO uint32_t DOUT;
714  __IO uint32_t DMACR;
715  __IO uint32_t IMSCR;
716  __IO uint32_t RISR;
717  __IO uint32_t MISR;
718  __IO uint32_t K0LR;
719  __IO uint32_t K0RR;
720  __IO uint32_t K1LR;
721  __IO uint32_t K1RR;
722  __IO uint32_t K2LR;
723  __IO uint32_t K2RR;
724  __IO uint32_t K3LR;
725  __IO uint32_t K3RR;
726  __IO uint32_t IV0LR;
727  __IO uint32_t IV0RR;
728  __IO uint32_t IV1LR;
729  __IO uint32_t IV1RR;
730  __IO uint32_t CSGCMCCM0R;
731  __IO uint32_t CSGCMCCM1R;
732  __IO uint32_t CSGCMCCM2R;
733  __IO uint32_t CSGCMCCM3R;
734  __IO uint32_t CSGCMCCM4R;
735  __IO uint32_t CSGCMCCM5R;
736  __IO uint32_t CSGCMCCM6R;
737  __IO uint32_t CSGCMCCM7R;
738  __IO uint32_t CSGCM0R;
739  __IO uint32_t CSGCM1R;
740  __IO uint32_t CSGCM2R;
741  __IO uint32_t CSGCM3R;
742  __IO uint32_t CSGCM4R;
743  __IO uint32_t CSGCM5R;
744  __IO uint32_t CSGCM6R;
745  __IO uint32_t CSGCM7R;
746 } CRYP_TypeDef;
747 
752 typedef struct
753 {
754  __IO uint32_t CR;
755  __IO uint32_t DIN;
756  __IO uint32_t STR;
757  __IO uint32_t HR[5];
758  __IO uint32_t IMR;
759  __IO uint32_t SR;
760  uint32_t RESERVED[52];
761  __IO uint32_t CSR[54];
762 } HASH_TypeDef;
763 
768 typedef struct
769 {
770  __IO uint32_t HR[8];
771 } HASH_DIGEST_TypeDef;
772 
777 typedef struct
778 {
779  __IO uint32_t CR;
780  __IO uint32_t SR;
781  __IO uint32_t DR;
782 } RNG_TypeDef;
783 
784 
785 
789 typedef struct
790 {
791  __IO uint32_t GOTGCTL;
792  __IO uint32_t GOTGINT;
793  __IO uint32_t GAHBCFG;
794  __IO uint32_t GUSBCFG;
795  __IO uint32_t GRSTCTL;
796  __IO uint32_t GINTSTS;
797  __IO uint32_t GINTMSK;
798  __IO uint32_t GRXSTSR;
799  __IO uint32_t GRXSTSP;
800  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
801  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
802  __IO uint32_t HNPTXSTS;
803  uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
804  __IO uint32_t GCCFG;
805  __IO uint32_t CID;
806  uint32_t Reserved40[48];
807  __IO uint32_t HPTXFSIZ;
808  __IO uint32_t DIEPTXF[0x0F];
809 }
810 USB_OTG_GlobalTypeDef;
811 
812 
813 
817 typedef struct
818 {
819  __IO uint32_t DCFG;
820  __IO uint32_t DCTL;
821  __IO uint32_t DSTS;
822  uint32_t Reserved0C;
823  __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
824  __IO uint32_t DOEPMSK;
825  __IO uint32_t DAINT;
826  __IO uint32_t DAINTMSK;
827  uint32_t Reserved20;
828  uint32_t Reserved9;
829  __IO uint32_t DVBUSDIS;
830  __IO uint32_t DVBUSPULSE;
831  __IO uint32_t DTHRCTL;
832  __IO uint32_t DIEPEMPMSK;
833  __IO uint32_t DEACHINT;
834  __IO uint32_t DEACHMSK;
835  uint32_t Reserved40;
836  __IO uint32_t DINEP1MSK;
837  uint32_t Reserved44[15];
838  __IO uint32_t DOUTEP1MSK;
839 }
840 USB_OTG_DeviceTypeDef;
841 
842 
846 typedef struct
847 {
848  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
849  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
850  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
851  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
852  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
853  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
854  __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
855  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
856 }
857 USB_OTG_INEndpointTypeDef;
858 
859 
863 typedef struct
864 {
865  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
866  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
867  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
868  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
869  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
870  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
871  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
872 }
873 USB_OTG_OUTEndpointTypeDef;
874 
875 
879 typedef struct
880 {
881  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
882  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
883  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
884  uint32_t Reserved40C; /* Reserved 40Ch*/
885  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
886  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
887  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
888 }
889 USB_OTG_HostTypeDef;
890 
891 
895 typedef struct
896 {
897  __IO uint32_t HCCHAR;
898  __IO uint32_t HCSPLT;
899  __IO uint32_t HCINT;
900  __IO uint32_t HCINTMSK;
901  __IO uint32_t HCTSIZ;
902  __IO uint32_t HCDMA;
903  uint32_t Reserved[2];
904 }
905 USB_OTG_HostChannelTypeDef;
906 
907 
911 #define FLASH_BASE 0x08000000U
912 #define CCMDATARAM_BASE 0x10000000U
913 #define SRAM1_BASE 0x20000000U
914 #define SRAM2_BASE 0x2001C000U
915 #define PERIPH_BASE 0x40000000U
916 #define BKPSRAM_BASE 0x40024000U
917 #define FSMC_R_BASE 0xA0000000U
918 #define SRAM1_BB_BASE 0x22000000U
919 #define SRAM2_BB_BASE 0x22380000U
920 #define PERIPH_BB_BASE 0x42000000U
921 #define BKPSRAM_BB_BASE 0x42480000U
922 #define FLASH_END 0x080FFFFFU
923 #define CCMDATARAM_END 0x1000FFFFU
925 /* Legacy defines */
926 #define SRAM_BASE SRAM1_BASE
927 #define SRAM_BB_BASE SRAM1_BB_BASE
928 
929 
931 #define APB1PERIPH_BASE PERIPH_BASE
932 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
933 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
934 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
935 
937 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
938 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
939 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
940 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
941 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
942 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
943 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
944 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
945 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
946 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
947 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
948 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
949 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
950 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
951 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
952 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
953 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
954 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
955 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
956 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
957 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
958 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
959 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
960 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
961 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
962 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
963 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
964 
966 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
967 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
968 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
969 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
970 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
971 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
972 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
973 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
974 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
975 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
976 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
977 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
978 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
979 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
980 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
981 
983 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
984 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
985 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
986 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
987 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
988 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
989 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
990 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
991 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
992 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
993 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
994 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
995 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
996 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
997 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
998 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
999 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1000 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1001 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1002 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1003 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1004 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1005 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1006 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1007 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1008 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1009 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1010 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1011 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1012 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1013 
1015 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1016 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1017 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1018 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1019 
1021 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
1022 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
1023 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
1024 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
1025 
1026 /* Debug MCU registers base address */
1027 #define DBGMCU_BASE 0xE0042000U
1028 
1030 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1031 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1032 
1033 #define USB_OTG_GLOBAL_BASE 0x000U
1034 #define USB_OTG_DEVICE_BASE 0x800U
1035 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1036 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1037 #define USB_OTG_EP_REG_SIZE 0x20U
1038 #define USB_OTG_HOST_BASE 0x400U
1039 #define USB_OTG_HOST_PORT_BASE 0x440U
1040 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1041 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1042 #define USB_OTG_PCGCCTL_BASE 0xE00U
1043 #define USB_OTG_FIFO_BASE 0x1000U
1044 #define USB_OTG_FIFO_SIZE 0x1000U
1045 
1053 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1054 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1055 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1056 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1057 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1058 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1059 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1060 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1061 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1062 #define RTC ((RTC_TypeDef *) RTC_BASE)
1063 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1064 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1065 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1066 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1067 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1068 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1069 #define USART2 ((USART_TypeDef *) USART2_BASE)
1070 #define USART3 ((USART_TypeDef *) USART3_BASE)
1071 #define UART4 ((USART_TypeDef *) UART4_BASE)
1072 #define UART5 ((USART_TypeDef *) UART5_BASE)
1073 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1074 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1075 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1076 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1077 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1078 #define PWR ((PWR_TypeDef *) PWR_BASE)
1079 #define DAC ((DAC_TypeDef *) DAC_BASE)
1080 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1081 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1082 #define USART1 ((USART_TypeDef *) USART1_BASE)
1083 #define USART6 ((USART_TypeDef *) USART6_BASE)
1084 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1085 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1086 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1087 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1088 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1089 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1090 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1091 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1092 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1093 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1094 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1095 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1096 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1097 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1098 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1099 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1100 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1101 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1102 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1103 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1104 #define CRC ((CRC_TypeDef *) CRC_BASE)
1105 #define RCC ((RCC_TypeDef *) RCC_BASE)
1106 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1107 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1108 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1109 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1110 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1111 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1112 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1113 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1114 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1115 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1116 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1117 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1118 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1119 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1120 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1121 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1122 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1123 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1124 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1125 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1126 #define HASH ((HASH_TypeDef *) HASH_BASE)
1127 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1128 #define RNG ((RNG_TypeDef *) RNG_BASE)
1129 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1130 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1131 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1132 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1133 
1134 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1135 
1136 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1137 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1138 
1151 /******************************************************************************/
1152 /* Peripheral Registers_Bits_Definition */
1153 /******************************************************************************/
1154 
1155 /******************************************************************************/
1156 /* */
1157 /* Analog to Digital Converter */
1158 /* */
1159 /******************************************************************************/
1160 /******************** Bit definition for ADC_SR register ********************/
1161 #define ADC_SR_AWD 0x00000001U
1162 #define ADC_SR_EOC 0x00000002U
1163 #define ADC_SR_JEOC 0x00000004U
1164 #define ADC_SR_JSTRT 0x00000008U
1165 #define ADC_SR_STRT 0x00000010U
1166 #define ADC_SR_OVR 0x00000020U
1168 /******************* Bit definition for ADC_CR1 register ********************/
1169 #define ADC_CR1_AWDCH 0x0000001FU
1170 #define ADC_CR1_AWDCH_0 0x00000001U
1171 #define ADC_CR1_AWDCH_1 0x00000002U
1172 #define ADC_CR1_AWDCH_2 0x00000004U
1173 #define ADC_CR1_AWDCH_3 0x00000008U
1174 #define ADC_CR1_AWDCH_4 0x00000010U
1175 #define ADC_CR1_EOCIE 0x00000020U
1176 #define ADC_CR1_AWDIE 0x00000040U
1177 #define ADC_CR1_JEOCIE 0x00000080U
1178 #define ADC_CR1_SCAN 0x00000100U
1179 #define ADC_CR1_AWDSGL 0x00000200U
1180 #define ADC_CR1_JAUTO 0x00000400U
1181 #define ADC_CR1_DISCEN 0x00000800U
1182 #define ADC_CR1_JDISCEN 0x00001000U
1183 #define ADC_CR1_DISCNUM 0x0000E000U
1184 #define ADC_CR1_DISCNUM_0 0x00002000U
1185 #define ADC_CR1_DISCNUM_1 0x00004000U
1186 #define ADC_CR1_DISCNUM_2 0x00008000U
1187 #define ADC_CR1_JAWDEN 0x00400000U
1188 #define ADC_CR1_AWDEN 0x00800000U
1189 #define ADC_CR1_RES 0x03000000U
1190 #define ADC_CR1_RES_0 0x01000000U
1191 #define ADC_CR1_RES_1 0x02000000U
1192 #define ADC_CR1_OVRIE 0x04000000U
1194 /******************* Bit definition for ADC_CR2 register ********************/
1195 #define ADC_CR2_ADON 0x00000001U
1196 #define ADC_CR2_CONT 0x00000002U
1197 #define ADC_CR2_DMA 0x00000100U
1198 #define ADC_CR2_DDS 0x00000200U
1199 #define ADC_CR2_EOCS 0x00000400U
1200 #define ADC_CR2_ALIGN 0x00000800U
1201 #define ADC_CR2_JEXTSEL 0x000F0000U
1202 #define ADC_CR2_JEXTSEL_0 0x00010000U
1203 #define ADC_CR2_JEXTSEL_1 0x00020000U
1204 #define ADC_CR2_JEXTSEL_2 0x00040000U
1205 #define ADC_CR2_JEXTSEL_3 0x00080000U
1206 #define ADC_CR2_JEXTEN 0x00300000U
1207 #define ADC_CR2_JEXTEN_0 0x00100000U
1208 #define ADC_CR2_JEXTEN_1 0x00200000U
1209 #define ADC_CR2_JSWSTART 0x00400000U
1210 #define ADC_CR2_EXTSEL 0x0F000000U
1211 #define ADC_CR2_EXTSEL_0 0x01000000U
1212 #define ADC_CR2_EXTSEL_1 0x02000000U
1213 #define ADC_CR2_EXTSEL_2 0x04000000U
1214 #define ADC_CR2_EXTSEL_3 0x08000000U
1215 #define ADC_CR2_EXTEN 0x30000000U
1216 #define ADC_CR2_EXTEN_0 0x10000000U
1217 #define ADC_CR2_EXTEN_1 0x20000000U
1218 #define ADC_CR2_SWSTART 0x40000000U
1220 /****************** Bit definition for ADC_SMPR1 register *******************/
1221 #define ADC_SMPR1_SMP10 0x00000007U
1222 #define ADC_SMPR1_SMP10_0 0x00000001U
1223 #define ADC_SMPR1_SMP10_1 0x00000002U
1224 #define ADC_SMPR1_SMP10_2 0x00000004U
1225 #define ADC_SMPR1_SMP11 0x00000038U
1226 #define ADC_SMPR1_SMP11_0 0x00000008U
1227 #define ADC_SMPR1_SMP11_1 0x00000010U
1228 #define ADC_SMPR1_SMP11_2 0x00000020U
1229 #define ADC_SMPR1_SMP12 0x000001C0U
1230 #define ADC_SMPR1_SMP12_0 0x00000040U
1231 #define ADC_SMPR1_SMP12_1 0x00000080U
1232 #define ADC_SMPR1_SMP12_2 0x00000100U
1233 #define ADC_SMPR1_SMP13 0x00000E00U
1234 #define ADC_SMPR1_SMP13_0 0x00000200U
1235 #define ADC_SMPR1_SMP13_1 0x00000400U
1236 #define ADC_SMPR1_SMP13_2 0x00000800U
1237 #define ADC_SMPR1_SMP14 0x00007000U
1238 #define ADC_SMPR1_SMP14_0 0x00001000U
1239 #define ADC_SMPR1_SMP14_1 0x00002000U
1240 #define ADC_SMPR1_SMP14_2 0x00004000U
1241 #define ADC_SMPR1_SMP15 0x00038000U
1242 #define ADC_SMPR1_SMP15_0 0x00008000U
1243 #define ADC_SMPR1_SMP15_1 0x00010000U
1244 #define ADC_SMPR1_SMP15_2 0x00020000U
1245 #define ADC_SMPR1_SMP16 0x001C0000U
1246 #define ADC_SMPR1_SMP16_0 0x00040000U
1247 #define ADC_SMPR1_SMP16_1 0x00080000U
1248 #define ADC_SMPR1_SMP16_2 0x00100000U
1249 #define ADC_SMPR1_SMP17 0x00E00000U
1250 #define ADC_SMPR1_SMP17_0 0x00200000U
1251 #define ADC_SMPR1_SMP17_1 0x00400000U
1252 #define ADC_SMPR1_SMP17_2 0x00800000U
1253 #define ADC_SMPR1_SMP18 0x07000000U
1254 #define ADC_SMPR1_SMP18_0 0x01000000U
1255 #define ADC_SMPR1_SMP18_1 0x02000000U
1256 #define ADC_SMPR1_SMP18_2 0x04000000U
1258 /****************** Bit definition for ADC_SMPR2 register *******************/
1259 #define ADC_SMPR2_SMP0 0x00000007U
1260 #define ADC_SMPR2_SMP0_0 0x00000001U
1261 #define ADC_SMPR2_SMP0_1 0x00000002U
1262 #define ADC_SMPR2_SMP0_2 0x00000004U
1263 #define ADC_SMPR2_SMP1 0x00000038U
1264 #define ADC_SMPR2_SMP1_0 0x00000008U
1265 #define ADC_SMPR2_SMP1_1 0x00000010U
1266 #define ADC_SMPR2_SMP1_2 0x00000020U
1267 #define ADC_SMPR2_SMP2 0x000001C0U
1268 #define ADC_SMPR2_SMP2_0 0x00000040U
1269 #define ADC_SMPR2_SMP2_1 0x00000080U
1270 #define ADC_SMPR2_SMP2_2 0x00000100U
1271 #define ADC_SMPR2_SMP3 0x00000E00U
1272 #define ADC_SMPR2_SMP3_0 0x00000200U
1273 #define ADC_SMPR2_SMP3_1 0x00000400U
1274 #define ADC_SMPR2_SMP3_2 0x00000800U
1275 #define ADC_SMPR2_SMP4 0x00007000U
1276 #define ADC_SMPR2_SMP4_0 0x00001000U
1277 #define ADC_SMPR2_SMP4_1 0x00002000U
1278 #define ADC_SMPR2_SMP4_2 0x00004000U
1279 #define ADC_SMPR2_SMP5 0x00038000U
1280 #define ADC_SMPR2_SMP5_0 0x00008000U
1281 #define ADC_SMPR2_SMP5_1 0x00010000U
1282 #define ADC_SMPR2_SMP5_2 0x00020000U
1283 #define ADC_SMPR2_SMP6 0x001C0000U
1284 #define ADC_SMPR2_SMP6_0 0x00040000U
1285 #define ADC_SMPR2_SMP6_1 0x00080000U
1286 #define ADC_SMPR2_SMP6_2 0x00100000U
1287 #define ADC_SMPR2_SMP7 0x00E00000U
1288 #define ADC_SMPR2_SMP7_0 0x00200000U
1289 #define ADC_SMPR2_SMP7_1 0x00400000U
1290 #define ADC_SMPR2_SMP7_2 0x00800000U
1291 #define ADC_SMPR2_SMP8 0x07000000U
1292 #define ADC_SMPR2_SMP8_0 0x01000000U
1293 #define ADC_SMPR2_SMP8_1 0x02000000U
1294 #define ADC_SMPR2_SMP8_2 0x04000000U
1295 #define ADC_SMPR2_SMP9 0x38000000U
1296 #define ADC_SMPR2_SMP9_0 0x08000000U
1297 #define ADC_SMPR2_SMP9_1 0x10000000U
1298 #define ADC_SMPR2_SMP9_2 0x20000000U
1300 /****************** Bit definition for ADC_JOFR1 register *******************/
1301 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1303 /****************** Bit definition for ADC_JOFR2 register *******************/
1304 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1306 /****************** Bit definition for ADC_JOFR3 register *******************/
1307 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1309 /****************** Bit definition for ADC_JOFR4 register *******************/
1310 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1312 /******************* Bit definition for ADC_HTR register ********************/
1313 #define ADC_HTR_HT 0x0FFFU
1315 /******************* Bit definition for ADC_LTR register ********************/
1316 #define ADC_LTR_LT 0x0FFFU
1318 /******************* Bit definition for ADC_SQR1 register *******************/
1319 #define ADC_SQR1_SQ13 0x0000001FU
1320 #define ADC_SQR1_SQ13_0 0x00000001U
1321 #define ADC_SQR1_SQ13_1 0x00000002U
1322 #define ADC_SQR1_SQ13_2 0x00000004U
1323 #define ADC_SQR1_SQ13_3 0x00000008U
1324 #define ADC_SQR1_SQ13_4 0x00000010U
1325 #define ADC_SQR1_SQ14 0x000003E0U
1326 #define ADC_SQR1_SQ14_0 0x00000020U
1327 #define ADC_SQR1_SQ14_1 0x00000040U
1328 #define ADC_SQR1_SQ14_2 0x00000080U
1329 #define ADC_SQR1_SQ14_3 0x00000100U
1330 #define ADC_SQR1_SQ14_4 0x00000200U
1331 #define ADC_SQR1_SQ15 0x00007C00U
1332 #define ADC_SQR1_SQ15_0 0x00000400U
1333 #define ADC_SQR1_SQ15_1 0x00000800U
1334 #define ADC_SQR1_SQ15_2 0x00001000U
1335 #define ADC_SQR1_SQ15_3 0x00002000U
1336 #define ADC_SQR1_SQ15_4 0x00004000U
1337 #define ADC_SQR1_SQ16 0x000F8000U
1338 #define ADC_SQR1_SQ16_0 0x00008000U
1339 #define ADC_SQR1_SQ16_1 0x00010000U
1340 #define ADC_SQR1_SQ16_2 0x00020000U
1341 #define ADC_SQR1_SQ16_3 0x00040000U
1342 #define ADC_SQR1_SQ16_4 0x00080000U
1343 #define ADC_SQR1_L 0x00F00000U
1344 #define ADC_SQR1_L_0 0x00100000U
1345 #define ADC_SQR1_L_1 0x00200000U
1346 #define ADC_SQR1_L_2 0x00400000U
1347 #define ADC_SQR1_L_3 0x00800000U
1349 /******************* Bit definition for ADC_SQR2 register *******************/
1350 #define ADC_SQR2_SQ7 0x0000001FU
1351 #define ADC_SQR2_SQ7_0 0x00000001U
1352 #define ADC_SQR2_SQ7_1 0x00000002U
1353 #define ADC_SQR2_SQ7_2 0x00000004U
1354 #define ADC_SQR2_SQ7_3 0x00000008U
1355 #define ADC_SQR2_SQ7_4 0x00000010U
1356 #define ADC_SQR2_SQ8 0x000003E0U
1357 #define ADC_SQR2_SQ8_0 0x00000020U
1358 #define ADC_SQR2_SQ8_1 0x00000040U
1359 #define ADC_SQR2_SQ8_2 0x00000080U
1360 #define ADC_SQR2_SQ8_3 0x00000100U
1361 #define ADC_SQR2_SQ8_4 0x00000200U
1362 #define ADC_SQR2_SQ9 0x00007C00U
1363 #define ADC_SQR2_SQ9_0 0x00000400U
1364 #define ADC_SQR2_SQ9_1 0x00000800U
1365 #define ADC_SQR2_SQ9_2 0x00001000U
1366 #define ADC_SQR2_SQ9_3 0x00002000U
1367 #define ADC_SQR2_SQ9_4 0x00004000U
1368 #define ADC_SQR2_SQ10 0x000F8000U
1369 #define ADC_SQR2_SQ10_0 0x00008000U
1370 #define ADC_SQR2_SQ10_1 0x00010000U
1371 #define ADC_SQR2_SQ10_2 0x00020000U
1372 #define ADC_SQR2_SQ10_3 0x00040000U
1373 #define ADC_SQR2_SQ10_4 0x00080000U
1374 #define ADC_SQR2_SQ11 0x01F00000U
1375 #define ADC_SQR2_SQ11_0 0x00100000U
1376 #define ADC_SQR2_SQ11_1 0x00200000U
1377 #define ADC_SQR2_SQ11_2 0x00400000U
1378 #define ADC_SQR2_SQ11_3 0x00800000U
1379 #define ADC_SQR2_SQ11_4 0x01000000U
1380 #define ADC_SQR2_SQ12 0x3E000000U
1381 #define ADC_SQR2_SQ12_0 0x02000000U
1382 #define ADC_SQR2_SQ12_1 0x04000000U
1383 #define ADC_SQR2_SQ12_2 0x08000000U
1384 #define ADC_SQR2_SQ12_3 0x10000000U
1385 #define ADC_SQR2_SQ12_4 0x20000000U
1387 /******************* Bit definition for ADC_SQR3 register *******************/
1388 #define ADC_SQR3_SQ1 0x0000001FU
1389 #define ADC_SQR3_SQ1_0 0x00000001U
1390 #define ADC_SQR3_SQ1_1 0x00000002U
1391 #define ADC_SQR3_SQ1_2 0x00000004U
1392 #define ADC_SQR3_SQ1_3 0x00000008U
1393 #define ADC_SQR3_SQ1_4 0x00000010U
1394 #define ADC_SQR3_SQ2 0x000003E0U
1395 #define ADC_SQR3_SQ2_0 0x00000020U
1396 #define ADC_SQR3_SQ2_1 0x00000040U
1397 #define ADC_SQR3_SQ2_2 0x00000080U
1398 #define ADC_SQR3_SQ2_3 0x00000100U
1399 #define ADC_SQR3_SQ2_4 0x00000200U
1400 #define ADC_SQR3_SQ3 0x00007C00U
1401 #define ADC_SQR3_SQ3_0 0x00000400U
1402 #define ADC_SQR3_SQ3_1 0x00000800U
1403 #define ADC_SQR3_SQ3_2 0x00001000U
1404 #define ADC_SQR3_SQ3_3 0x00002000U
1405 #define ADC_SQR3_SQ3_4 0x00004000U
1406 #define ADC_SQR3_SQ4 0x000F8000U
1407 #define ADC_SQR3_SQ4_0 0x00008000U
1408 #define ADC_SQR3_SQ4_1 0x00010000U
1409 #define ADC_SQR3_SQ4_2 0x00020000U
1410 #define ADC_SQR3_SQ4_3 0x00040000U
1411 #define ADC_SQR3_SQ4_4 0x00080000U
1412 #define ADC_SQR3_SQ5 0x01F00000U
1413 #define ADC_SQR3_SQ5_0 0x00100000U
1414 #define ADC_SQR3_SQ5_1 0x00200000U
1415 #define ADC_SQR3_SQ5_2 0x00400000U
1416 #define ADC_SQR3_SQ5_3 0x00800000U
1417 #define ADC_SQR3_SQ5_4 0x01000000U
1418 #define ADC_SQR3_SQ6 0x3E000000U
1419 #define ADC_SQR3_SQ6_0 0x02000000U
1420 #define ADC_SQR3_SQ6_1 0x04000000U
1421 #define ADC_SQR3_SQ6_2 0x08000000U
1422 #define ADC_SQR3_SQ6_3 0x10000000U
1423 #define ADC_SQR3_SQ6_4 0x20000000U
1425 /******************* Bit definition for ADC_JSQR register *******************/
1426 #define ADC_JSQR_JSQ1 0x0000001FU
1427 #define ADC_JSQR_JSQ1_0 0x00000001U
1428 #define ADC_JSQR_JSQ1_1 0x00000002U
1429 #define ADC_JSQR_JSQ1_2 0x00000004U
1430 #define ADC_JSQR_JSQ1_3 0x00000008U
1431 #define ADC_JSQR_JSQ1_4 0x00000010U
1432 #define ADC_JSQR_JSQ2 0x000003E0U
1433 #define ADC_JSQR_JSQ2_0 0x00000020U
1434 #define ADC_JSQR_JSQ2_1 0x00000040U
1435 #define ADC_JSQR_JSQ2_2 0x00000080U
1436 #define ADC_JSQR_JSQ2_3 0x00000100U
1437 #define ADC_JSQR_JSQ2_4 0x00000200U
1438 #define ADC_JSQR_JSQ3 0x00007C00U
1439 #define ADC_JSQR_JSQ3_0 0x00000400U
1440 #define ADC_JSQR_JSQ3_1 0x00000800U
1441 #define ADC_JSQR_JSQ3_2 0x00001000U
1442 #define ADC_JSQR_JSQ3_3 0x00002000U
1443 #define ADC_JSQR_JSQ3_4 0x00004000U
1444 #define ADC_JSQR_JSQ4 0x000F8000U
1445 #define ADC_JSQR_JSQ4_0 0x00008000U
1446 #define ADC_JSQR_JSQ4_1 0x00010000U
1447 #define ADC_JSQR_JSQ4_2 0x00020000U
1448 #define ADC_JSQR_JSQ4_3 0x00040000U
1449 #define ADC_JSQR_JSQ4_4 0x00080000U
1450 #define ADC_JSQR_JL 0x00300000U
1451 #define ADC_JSQR_JL_0 0x00100000U
1452 #define ADC_JSQR_JL_1 0x00200000U
1454 /******************* Bit definition for ADC_JDR1 register *******************/
1455 #define ADC_JDR1_JDATA 0xFFFFU
1457 /******************* Bit definition for ADC_JDR2 register *******************/
1458 #define ADC_JDR2_JDATA 0xFFFFU
1460 /******************* Bit definition for ADC_JDR3 register *******************/
1461 #define ADC_JDR3_JDATA 0xFFFFU
1463 /******************* Bit definition for ADC_JDR4 register *******************/
1464 #define ADC_JDR4_JDATA 0xFFFFU
1466 /******************** Bit definition for ADC_DR register ********************/
1467 #define ADC_DR_DATA 0x0000FFFFU
1468 #define ADC_DR_ADC2DATA 0xFFFF0000U
1470 /******************* Bit definition for ADC_CSR register ********************/
1471 #define ADC_CSR_AWD1 0x00000001U
1472 #define ADC_CSR_EOC1 0x00000002U
1473 #define ADC_CSR_JEOC1 0x00000004U
1474 #define ADC_CSR_JSTRT1 0x00000008U
1475 #define ADC_CSR_STRT1 0x00000010U
1476 #define ADC_CSR_OVR1 0x00000020U
1477 #define ADC_CSR_AWD2 0x00000100U
1478 #define ADC_CSR_EOC2 0x00000200U
1479 #define ADC_CSR_JEOC2 0x00000400U
1480 #define ADC_CSR_JSTRT2 0x00000800U
1481 #define ADC_CSR_STRT2 0x00001000U
1482 #define ADC_CSR_OVR2 0x00002000U
1483 #define ADC_CSR_AWD3 0x00010000U
1484 #define ADC_CSR_EOC3 0x00020000U
1485 #define ADC_CSR_JEOC3 0x00040000U
1486 #define ADC_CSR_JSTRT3 0x00080000U
1487 #define ADC_CSR_STRT3 0x00100000U
1488 #define ADC_CSR_OVR3 0x00200000U
1490 /* Legacy defines */
1491 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1492 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1493 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1494 
1495 /******************* Bit definition for ADC_CCR register ********************/
1496 #define ADC_CCR_MULTI 0x0000001FU
1497 #define ADC_CCR_MULTI_0 0x00000001U
1498 #define ADC_CCR_MULTI_1 0x00000002U
1499 #define ADC_CCR_MULTI_2 0x00000004U
1500 #define ADC_CCR_MULTI_3 0x00000008U
1501 #define ADC_CCR_MULTI_4 0x00000010U
1502 #define ADC_CCR_DELAY 0x00000F00U
1503 #define ADC_CCR_DELAY_0 0x00000100U
1504 #define ADC_CCR_DELAY_1 0x00000200U
1505 #define ADC_CCR_DELAY_2 0x00000400U
1506 #define ADC_CCR_DELAY_3 0x00000800U
1507 #define ADC_CCR_DDS 0x00002000U
1508 #define ADC_CCR_DMA 0x0000C000U
1509 #define ADC_CCR_DMA_0 0x00004000U
1510 #define ADC_CCR_DMA_1 0x00008000U
1511 #define ADC_CCR_ADCPRE 0x00030000U
1512 #define ADC_CCR_ADCPRE_0 0x00010000U
1513 #define ADC_CCR_ADCPRE_1 0x00020000U
1514 #define ADC_CCR_VBATE 0x00400000U
1515 #define ADC_CCR_TSVREFE 0x00800000U
1517 /******************* Bit definition for ADC_CDR register ********************/
1518 #define ADC_CDR_DATA1 0x0000FFFFU
1519 #define ADC_CDR_DATA2 0xFFFF0000U
1521 /******************************************************************************/
1522 /* */
1523 /* Controller Area Network */
1524 /* */
1525 /******************************************************************************/
1527 /******************* Bit definition for CAN_MCR register ********************/
1528 #define CAN_MCR_INRQ 0x00000001U
1529 #define CAN_MCR_SLEEP 0x00000002U
1530 #define CAN_MCR_TXFP 0x00000004U
1531 #define CAN_MCR_RFLM 0x00000008U
1532 #define CAN_MCR_NART 0x00000010U
1533 #define CAN_MCR_AWUM 0x00000020U
1534 #define CAN_MCR_ABOM 0x00000040U
1535 #define CAN_MCR_TTCM 0x00000080U
1536 #define CAN_MCR_RESET 0x00008000U
1537 #define CAN_MCR_DBF 0x00010000U
1538 /******************* Bit definition for CAN_MSR register ********************/
1539 #define CAN_MSR_INAK 0x0001U
1540 #define CAN_MSR_SLAK 0x0002U
1541 #define CAN_MSR_ERRI 0x0004U
1542 #define CAN_MSR_WKUI 0x0008U
1543 #define CAN_MSR_SLAKI 0x0010U
1544 #define CAN_MSR_TXM 0x0100U
1545 #define CAN_MSR_RXM 0x0200U
1546 #define CAN_MSR_SAMP 0x0400U
1547 #define CAN_MSR_RX 0x0800U
1549 /******************* Bit definition for CAN_TSR register ********************/
1550 #define CAN_TSR_RQCP0 0x00000001U
1551 #define CAN_TSR_TXOK0 0x00000002U
1552 #define CAN_TSR_ALST0 0x00000004U
1553 #define CAN_TSR_TERR0 0x00000008U
1554 #define CAN_TSR_ABRQ0 0x00000080U
1555 #define CAN_TSR_RQCP1 0x00000100U
1556 #define CAN_TSR_TXOK1 0x00000200U
1557 #define CAN_TSR_ALST1 0x00000400U
1558 #define CAN_TSR_TERR1 0x00000800U
1559 #define CAN_TSR_ABRQ1 0x00008000U
1560 #define CAN_TSR_RQCP2 0x00010000U
1561 #define CAN_TSR_TXOK2 0x00020000U
1562 #define CAN_TSR_ALST2 0x00040000U
1563 #define CAN_TSR_TERR2 0x00080000U
1564 #define CAN_TSR_ABRQ2 0x00800000U
1565 #define CAN_TSR_CODE 0x03000000U
1567 #define CAN_TSR_TME 0x1C000000U
1568 #define CAN_TSR_TME0 0x04000000U
1569 #define CAN_TSR_TME1 0x08000000U
1570 #define CAN_TSR_TME2 0x10000000U
1572 #define CAN_TSR_LOW 0xE0000000U
1573 #define CAN_TSR_LOW0 0x20000000U
1574 #define CAN_TSR_LOW1 0x40000000U
1575 #define CAN_TSR_LOW2 0x80000000U
1577 /******************* Bit definition for CAN_RF0R register *******************/
1578 #define CAN_RF0R_FMP0 0x03U
1579 #define CAN_RF0R_FULL0 0x08U
1580 #define CAN_RF0R_FOVR0 0x10U
1581 #define CAN_RF0R_RFOM0 0x20U
1583 /******************* Bit definition for CAN_RF1R register *******************/
1584 #define CAN_RF1R_FMP1 0x03U
1585 #define CAN_RF1R_FULL1 0x08U
1586 #define CAN_RF1R_FOVR1 0x10U
1587 #define CAN_RF1R_RFOM1 0x20U
1589 /******************** Bit definition for CAN_IER register *******************/
1590 #define CAN_IER_TMEIE 0x00000001U
1591 #define CAN_IER_FMPIE0 0x00000002U
1592 #define CAN_IER_FFIE0 0x00000004U
1593 #define CAN_IER_FOVIE0 0x00000008U
1594 #define CAN_IER_FMPIE1 0x00000010U
1595 #define CAN_IER_FFIE1 0x00000020U
1596 #define CAN_IER_FOVIE1 0x00000040U
1597 #define CAN_IER_EWGIE 0x00000100U
1598 #define CAN_IER_EPVIE 0x00000200U
1599 #define CAN_IER_BOFIE 0x00000400U
1600 #define CAN_IER_LECIE 0x00000800U
1601 #define CAN_IER_ERRIE 0x00008000U
1602 #define CAN_IER_WKUIE 0x00010000U
1603 #define CAN_IER_SLKIE 0x00020000U
1604 #define CAN_IER_EWGIE 0x00000100U
1605 #define CAN_IER_EPVIE 0x00000200U
1606 #define CAN_IER_BOFIE 0x00000400U
1607 #define CAN_IER_LECIE 0x00000800U
1608 #define CAN_IER_ERRIE 0x00008000U
1611 /******************** Bit definition for CAN_ESR register *******************/
1612 #define CAN_ESR_EWGF 0x00000001U
1613 #define CAN_ESR_EPVF 0x00000002U
1614 #define CAN_ESR_BOFF 0x00000004U
1616 #define CAN_ESR_LEC 0x00000070U
1617 #define CAN_ESR_LEC_0 0x00000010U
1618 #define CAN_ESR_LEC_1 0x00000020U
1619 #define CAN_ESR_LEC_2 0x00000040U
1621 #define CAN_ESR_TEC 0x00FF0000U
1622 #define CAN_ESR_REC 0xFF000000U
1624 /******************* Bit definition for CAN_BTR register ********************/
1625 #define CAN_BTR_BRP 0x000003FFU
1626 #define CAN_BTR_TS1 0x000F0000U
1627 #define CAN_BTR_TS1_0 0x00010000U
1628 #define CAN_BTR_TS1_1 0x00020000U
1629 #define CAN_BTR_TS1_2 0x00040000U
1630 #define CAN_BTR_TS1_3 0x00080000U
1631 #define CAN_BTR_TS2 0x00700000U
1632 #define CAN_BTR_TS2_0 0x00100000U
1633 #define CAN_BTR_TS2_1 0x00200000U
1634 #define CAN_BTR_TS2_2 0x00400000U
1635 #define CAN_BTR_SJW 0x03000000U
1636 #define CAN_BTR_SJW_0 0x01000000U
1637 #define CAN_BTR_SJW_1 0x02000000U
1638 #define CAN_BTR_LBKM 0x40000000U
1639 #define CAN_BTR_SILM 0x80000000U
1643 /****************** Bit definition for CAN_TI0R register ********************/
1644 #define CAN_TI0R_TXRQ 0x00000001U
1645 #define CAN_TI0R_RTR 0x00000002U
1646 #define CAN_TI0R_IDE 0x00000004U
1647 #define CAN_TI0R_EXID 0x001FFFF8U
1648 #define CAN_TI0R_STID 0xFFE00000U
1650 /****************** Bit definition for CAN_TDT0R register *******************/
1651 #define CAN_TDT0R_DLC 0x0000000FU
1652 #define CAN_TDT0R_TGT 0x00000100U
1653 #define CAN_TDT0R_TIME 0xFFFF0000U
1655 /****************** Bit definition for CAN_TDL0R register *******************/
1656 #define CAN_TDL0R_DATA0 0x000000FFU
1657 #define CAN_TDL0R_DATA1 0x0000FF00U
1658 #define CAN_TDL0R_DATA2 0x00FF0000U
1659 #define CAN_TDL0R_DATA3 0xFF000000U
1661 /****************** Bit definition for CAN_TDH0R register *******************/
1662 #define CAN_TDH0R_DATA4 0x000000FFU
1663 #define CAN_TDH0R_DATA5 0x0000FF00U
1664 #define CAN_TDH0R_DATA6 0x00FF0000U
1665 #define CAN_TDH0R_DATA7 0xFF000000U
1667 /******************* Bit definition for CAN_TI1R register *******************/
1668 #define CAN_TI1R_TXRQ 0x00000001U
1669 #define CAN_TI1R_RTR 0x00000002U
1670 #define CAN_TI1R_IDE 0x00000004U
1671 #define CAN_TI1R_EXID 0x001FFFF8U
1672 #define CAN_TI1R_STID 0xFFE00000U
1674 /******************* Bit definition for CAN_TDT1R register ******************/
1675 #define CAN_TDT1R_DLC 0x0000000FU
1676 #define CAN_TDT1R_TGT 0x00000100U
1677 #define CAN_TDT1R_TIME 0xFFFF0000U
1679 /******************* Bit definition for CAN_TDL1R register ******************/
1680 #define CAN_TDL1R_DATA0 0x000000FFU
1681 #define CAN_TDL1R_DATA1 0x0000FF00U
1682 #define CAN_TDL1R_DATA2 0x00FF0000U
1683 #define CAN_TDL1R_DATA3 0xFF000000U
1685 /******************* Bit definition for CAN_TDH1R register ******************/
1686 #define CAN_TDH1R_DATA4 0x000000FFU
1687 #define CAN_TDH1R_DATA5 0x0000FF00U
1688 #define CAN_TDH1R_DATA6 0x00FF0000U
1689 #define CAN_TDH1R_DATA7 0xFF000000U
1691 /******************* Bit definition for CAN_TI2R register *******************/
1692 #define CAN_TI2R_TXRQ 0x00000001U
1693 #define CAN_TI2R_RTR 0x00000002U
1694 #define CAN_TI2R_IDE 0x00000004U
1695 #define CAN_TI2R_EXID 0x001FFFF8U
1696 #define CAN_TI2R_STID 0xFFE00000U
1698 /******************* Bit definition for CAN_TDT2R register ******************/
1699 #define CAN_TDT2R_DLC 0x0000000FU
1700 #define CAN_TDT2R_TGT 0x00000100U
1701 #define CAN_TDT2R_TIME 0xFFFF0000U
1703 /******************* Bit definition for CAN_TDL2R register ******************/
1704 #define CAN_TDL2R_DATA0 0x000000FFU
1705 #define CAN_TDL2R_DATA1 0x0000FF00U
1706 #define CAN_TDL2R_DATA2 0x00FF0000U
1707 #define CAN_TDL2R_DATA3 0xFF000000U
1709 /******************* Bit definition for CAN_TDH2R register ******************/
1710 #define CAN_TDH2R_DATA4 0x000000FFU
1711 #define CAN_TDH2R_DATA5 0x0000FF00U
1712 #define CAN_TDH2R_DATA6 0x00FF0000U
1713 #define CAN_TDH2R_DATA7 0xFF000000U
1715 /******************* Bit definition for CAN_RI0R register *******************/
1716 #define CAN_RI0R_RTR 0x00000002U
1717 #define CAN_RI0R_IDE 0x00000004U
1718 #define CAN_RI0R_EXID 0x001FFFF8U
1719 #define CAN_RI0R_STID 0xFFE00000U
1721 /******************* Bit definition for CAN_RDT0R register ******************/
1722 #define CAN_RDT0R_DLC 0x0000000FU
1723 #define CAN_RDT0R_FMI 0x0000FF00U
1724 #define CAN_RDT0R_TIME 0xFFFF0000U
1726 /******************* Bit definition for CAN_RDL0R register ******************/
1727 #define CAN_RDL0R_DATA0 0x000000FFU
1728 #define CAN_RDL0R_DATA1 0x0000FF00U
1729 #define CAN_RDL0R_DATA2 0x00FF0000U
1730 #define CAN_RDL0R_DATA3 0xFF000000U
1732 /******************* Bit definition for CAN_RDH0R register ******************/
1733 #define CAN_RDH0R_DATA4 0x000000FFU
1734 #define CAN_RDH0R_DATA5 0x0000FF00U
1735 #define CAN_RDH0R_DATA6 0x00FF0000U
1736 #define CAN_RDH0R_DATA7 0xFF000000U
1738 /******************* Bit definition for CAN_RI1R register *******************/
1739 #define CAN_RI1R_RTR 0x00000002U
1740 #define CAN_RI1R_IDE 0x00000004U
1741 #define CAN_RI1R_EXID 0x001FFFF8U
1742 #define CAN_RI1R_STID 0xFFE00000U
1744 /******************* Bit definition for CAN_RDT1R register ******************/
1745 #define CAN_RDT1R_DLC 0x0000000FU
1746 #define CAN_RDT1R_FMI 0x0000FF00U
1747 #define CAN_RDT1R_TIME 0xFFFF0000U
1749 /******************* Bit definition for CAN_RDL1R register ******************/
1750 #define CAN_RDL1R_DATA0 0x000000FFU
1751 #define CAN_RDL1R_DATA1 0x0000FF00U
1752 #define CAN_RDL1R_DATA2 0x00FF0000U
1753 #define CAN_RDL1R_DATA3 0xFF000000U
1755 /******************* Bit definition for CAN_RDH1R register ******************/
1756 #define CAN_RDH1R_DATA4 0x000000FFU
1757 #define CAN_RDH1R_DATA5 0x0000FF00U
1758 #define CAN_RDH1R_DATA6 0x00FF0000U
1759 #define CAN_RDH1R_DATA7 0xFF000000U
1762 /******************* Bit definition for CAN_FMR register ********************/
1763 #define CAN_FMR_FINIT 0x01U
1764 #define CAN_FMR_CAN2SB 0x00003F00U
1766 /******************* Bit definition for CAN_FM1R register *******************/
1767 #define CAN_FM1R_FBM 0x0FFFFFFFU
1768 #define CAN_FM1R_FBM0 0x00000001U
1769 #define CAN_FM1R_FBM1 0x00000002U
1770 #define CAN_FM1R_FBM2 0x00000004U
1771 #define CAN_FM1R_FBM3 0x00000008U
1772 #define CAN_FM1R_FBM4 0x00000010U
1773 #define CAN_FM1R_FBM5 0x00000020U
1774 #define CAN_FM1R_FBM6 0x00000040U
1775 #define CAN_FM1R_FBM7 0x00000080U
1776 #define CAN_FM1R_FBM8 0x00000100U
1777 #define CAN_FM1R_FBM9 0x00000200U
1778 #define CAN_FM1R_FBM10 0x00000400U
1779 #define CAN_FM1R_FBM11 0x00000800U
1780 #define CAN_FM1R_FBM12 0x00001000U
1781 #define CAN_FM1R_FBM13 0x00002000U
1782 #define CAN_FM1R_FBM14 0x00004000U
1783 #define CAN_FM1R_FBM15 0x00008000U
1784 #define CAN_FM1R_FBM16 0x00010000U
1785 #define CAN_FM1R_FBM17 0x00020000U
1786 #define CAN_FM1R_FBM18 0x00040000U
1787 #define CAN_FM1R_FBM19 0x00080000U
1788 #define CAN_FM1R_FBM20 0x00100000U
1789 #define CAN_FM1R_FBM21 0x00200000U
1790 #define CAN_FM1R_FBM22 0x00400000U
1791 #define CAN_FM1R_FBM23 0x00800000U
1792 #define CAN_FM1R_FBM24 0x01000000U
1793 #define CAN_FM1R_FBM25 0x02000000U
1794 #define CAN_FM1R_FBM26 0x04000000U
1795 #define CAN_FM1R_FBM27 0x08000000U
1797 /******************* Bit definition for CAN_FS1R register *******************/
1798 #define CAN_FS1R_FSC 0x0FFFFFFFU
1799 #define CAN_FS1R_FSC0 0x00000001U
1800 #define CAN_FS1R_FSC1 0x00000002U
1801 #define CAN_FS1R_FSC2 0x00000004U
1802 #define CAN_FS1R_FSC3 0x00000008U
1803 #define CAN_FS1R_FSC4 0x00000010U
1804 #define CAN_FS1R_FSC5 0x00000020U
1805 #define CAN_FS1R_FSC6 0x00000040U
1806 #define CAN_FS1R_FSC7 0x00000080U
1807 #define CAN_FS1R_FSC8 0x00000100U
1808 #define CAN_FS1R_FSC9 0x00000200U
1809 #define CAN_FS1R_FSC10 0x00000400U
1810 #define CAN_FS1R_FSC11 0x00000800U
1811 #define CAN_FS1R_FSC12 0x00001000U
1812 #define CAN_FS1R_FSC13 0x00002000U
1813 #define CAN_FS1R_FSC14 0x00004000U
1814 #define CAN_FS1R_FSC15 0x00008000U
1815 #define CAN_FS1R_FSC16 0x00010000U
1816 #define CAN_FS1R_FSC17 0x00020000U
1817 #define CAN_FS1R_FSC18 0x00040000U
1818 #define CAN_FS1R_FSC19 0x00080000U
1819 #define CAN_FS1R_FSC20 0x00100000U
1820 #define CAN_FS1R_FSC21 0x00200000U
1821 #define CAN_FS1R_FSC22 0x00400000U
1822 #define CAN_FS1R_FSC23 0x00800000U
1823 #define CAN_FS1R_FSC24 0x01000000U
1824 #define CAN_FS1R_FSC25 0x02000000U
1825 #define CAN_FS1R_FSC26 0x04000000U
1826 #define CAN_FS1R_FSC27 0x08000000U
1828 /****************** Bit definition for CAN_FFA1R register *******************/
1829 #define CAN_FFA1R_FFA 0x0FFFFFFFU
1830 #define CAN_FFA1R_FFA0 0x00000001U
1831 #define CAN_FFA1R_FFA1 0x00000002U
1832 #define CAN_FFA1R_FFA2 0x00000004U
1833 #define CAN_FFA1R_FFA3 0x00000008U
1834 #define CAN_FFA1R_FFA4 0x00000010U
1835 #define CAN_FFA1R_FFA5 0x00000020U
1836 #define CAN_FFA1R_FFA6 0x00000040U
1837 #define CAN_FFA1R_FFA7 0x00000080U
1838 #define CAN_FFA1R_FFA8 0x00000100U
1839 #define CAN_FFA1R_FFA9 0x00000200U
1840 #define CAN_FFA1R_FFA10 0x00000400U
1841 #define CAN_FFA1R_FFA11 0x00000800U
1842 #define CAN_FFA1R_FFA12 0x00001000U
1843 #define CAN_FFA1R_FFA13 0x00002000U
1844 #define CAN_FFA1R_FFA14 0x00004000U
1845 #define CAN_FFA1R_FFA15 0x00008000U
1846 #define CAN_FFA1R_FFA16 0x00010000U
1847 #define CAN_FFA1R_FFA17 0x00020000U
1848 #define CAN_FFA1R_FFA18 0x00040000U
1849 #define CAN_FFA1R_FFA19 0x00080000U
1850 #define CAN_FFA1R_FFA20 0x00100000U
1851 #define CAN_FFA1R_FFA21 0x00200000U
1852 #define CAN_FFA1R_FFA22 0x00400000U
1853 #define CAN_FFA1R_FFA23 0x00800000U
1854 #define CAN_FFA1R_FFA24 0x01000000U
1855 #define CAN_FFA1R_FFA25 0x02000000U
1856 #define CAN_FFA1R_FFA26 0x04000000U
1857 #define CAN_FFA1R_FFA27 0x08000000U
1859 /******************* Bit definition for CAN_FA1R register *******************/
1860 #define CAN_FA1R_FACT 0x0FFFFFFFU
1861 #define CAN_FA1R_FACT0 0x00000001U
1862 #define CAN_FA1R_FACT1 0x00000002U
1863 #define CAN_FA1R_FACT2 0x00000004U
1864 #define CAN_FA1R_FACT3 0x00000008U
1865 #define CAN_FA1R_FACT4 0x00000010U
1866 #define CAN_FA1R_FACT5 0x00000020U
1867 #define CAN_FA1R_FACT6 0x00000040U
1868 #define CAN_FA1R_FACT7 0x00000080U
1869 #define CAN_FA1R_FACT8 0x00000100U
1870 #define CAN_FA1R_FACT9 0x00000200U
1871 #define CAN_FA1R_FACT10 0x00000400U
1872 #define CAN_FA1R_FACT11 0x00000800U
1873 #define CAN_FA1R_FACT12 0x00001000U
1874 #define CAN_FA1R_FACT13 0x00002000U
1875 #define CAN_FA1R_FACT14 0x00004000U
1876 #define CAN_FA1R_FACT15 0x00008000U
1877 #define CAN_FA1R_FACT16 0x00010000U
1878 #define CAN_FA1R_FACT17 0x00020000U
1879 #define CAN_FA1R_FACT18 0x00040000U
1880 #define CAN_FA1R_FACT19 0x00080000U
1881 #define CAN_FA1R_FACT20 0x00100000U
1882 #define CAN_FA1R_FACT21 0x00200000U
1883 #define CAN_FA1R_FACT22 0x00400000U
1884 #define CAN_FA1R_FACT23 0x00800000U
1885 #define CAN_FA1R_FACT24 0x01000000U
1886 #define CAN_FA1R_FACT25 0x02000000U
1887 #define CAN_FA1R_FACT26 0x04000000U
1888 #define CAN_FA1R_FACT27 0x08000000U
1890 /******************* Bit definition for CAN_F0R1 register *******************/
1891 #define CAN_F0R1_FB0 0x00000001U
1892 #define CAN_F0R1_FB1 0x00000002U
1893 #define CAN_F0R1_FB2 0x00000004U
1894 #define CAN_F0R1_FB3 0x00000008U
1895 #define CAN_F0R1_FB4 0x00000010U
1896 #define CAN_F0R1_FB5 0x00000020U
1897 #define CAN_F0R1_FB6 0x00000040U
1898 #define CAN_F0R1_FB7 0x00000080U
1899 #define CAN_F0R1_FB8 0x00000100U
1900 #define CAN_F0R1_FB9 0x00000200U
1901 #define CAN_F0R1_FB10 0x00000400U
1902 #define CAN_F0R1_FB11 0x00000800U
1903 #define CAN_F0R1_FB12 0x00001000U
1904 #define CAN_F0R1_FB13 0x00002000U
1905 #define CAN_F0R1_FB14 0x00004000U
1906 #define CAN_F0R1_FB15 0x00008000U
1907 #define CAN_F0R1_FB16 0x00010000U
1908 #define CAN_F0R1_FB17 0x00020000U
1909 #define CAN_F0R1_FB18 0x00040000U
1910 #define CAN_F0R1_FB19 0x00080000U
1911 #define CAN_F0R1_FB20 0x00100000U
1912 #define CAN_F0R1_FB21 0x00200000U
1913 #define CAN_F0R1_FB22 0x00400000U
1914 #define CAN_F0R1_FB23 0x00800000U
1915 #define CAN_F0R1_FB24 0x01000000U
1916 #define CAN_F0R1_FB25 0x02000000U
1917 #define CAN_F0R1_FB26 0x04000000U
1918 #define CAN_F0R1_FB27 0x08000000U
1919 #define CAN_F0R1_FB28 0x10000000U
1920 #define CAN_F0R1_FB29 0x20000000U
1921 #define CAN_F0R1_FB30 0x40000000U
1922 #define CAN_F0R1_FB31 0x80000000U
1924 /******************* Bit definition for CAN_F1R1 register *******************/
1925 #define CAN_F1R1_FB0 0x00000001U
1926 #define CAN_F1R1_FB1 0x00000002U
1927 #define CAN_F1R1_FB2 0x00000004U
1928 #define CAN_F1R1_FB3 0x00000008U
1929 #define CAN_F1R1_FB4 0x00000010U
1930 #define CAN_F1R1_FB5 0x00000020U
1931 #define CAN_F1R1_FB6 0x00000040U
1932 #define CAN_F1R1_FB7 0x00000080U
1933 #define CAN_F1R1_FB8 0x00000100U
1934 #define CAN_F1R1_FB9 0x00000200U
1935 #define CAN_F1R1_FB10 0x00000400U
1936 #define CAN_F1R1_FB11 0x00000800U
1937 #define CAN_F1R1_FB12 0x00001000U
1938 #define CAN_F1R1_FB13 0x00002000U
1939 #define CAN_F1R1_FB14 0x00004000U
1940 #define CAN_F1R1_FB15 0x00008000U
1941 #define CAN_F1R1_FB16 0x00010000U
1942 #define CAN_F1R1_FB17 0x00020000U
1943 #define CAN_F1R1_FB18 0x00040000U
1944 #define CAN_F1R1_FB19 0x00080000U
1945 #define CAN_F1R1_FB20 0x00100000U
1946 #define CAN_F1R1_FB21 0x00200000U
1947 #define CAN_F1R1_FB22 0x00400000U
1948 #define CAN_F1R1_FB23 0x00800000U
1949 #define CAN_F1R1_FB24 0x01000000U
1950 #define CAN_F1R1_FB25 0x02000000U
1951 #define CAN_F1R1_FB26 0x04000000U
1952 #define CAN_F1R1_FB27 0x08000000U
1953 #define CAN_F1R1_FB28 0x10000000U
1954 #define CAN_F1R1_FB29 0x20000000U
1955 #define CAN_F1R1_FB30 0x40000000U
1956 #define CAN_F1R1_FB31 0x80000000U
1958 /******************* Bit definition for CAN_F2R1 register *******************/
1959 #define CAN_F2R1_FB0 0x00000001U
1960 #define CAN_F2R1_FB1 0x00000002U
1961 #define CAN_F2R1_FB2 0x00000004U
1962 #define CAN_F2R1_FB3 0x00000008U
1963 #define CAN_F2R1_FB4 0x00000010U
1964 #define CAN_F2R1_FB5 0x00000020U
1965 #define CAN_F2R1_FB6 0x00000040U
1966 #define CAN_F2R1_FB7 0x00000080U
1967 #define CAN_F2R1_FB8 0x00000100U
1968 #define CAN_F2R1_FB9 0x00000200U
1969 #define CAN_F2R1_FB10 0x00000400U
1970 #define CAN_F2R1_FB11 0x00000800U
1971 #define CAN_F2R1_FB12 0x00001000U
1972 #define CAN_F2R1_FB13 0x00002000U
1973 #define CAN_F2R1_FB14 0x00004000U
1974 #define CAN_F2R1_FB15 0x00008000U
1975 #define CAN_F2R1_FB16 0x00010000U
1976 #define CAN_F2R1_FB17 0x00020000U
1977 #define CAN_F2R1_FB18 0x00040000U
1978 #define CAN_F2R1_FB19 0x00080000U
1979 #define CAN_F2R1_FB20 0x00100000U
1980 #define CAN_F2R1_FB21 0x00200000U
1981 #define CAN_F2R1_FB22 0x00400000U
1982 #define CAN_F2R1_FB23 0x00800000U
1983 #define CAN_F2R1_FB24 0x01000000U
1984 #define CAN_F2R1_FB25 0x02000000U
1985 #define CAN_F2R1_FB26 0x04000000U
1986 #define CAN_F2R1_FB27 0x08000000U
1987 #define CAN_F2R1_FB28 0x10000000U
1988 #define CAN_F2R1_FB29 0x20000000U
1989 #define CAN_F2R1_FB30 0x40000000U
1990 #define CAN_F2R1_FB31 0x80000000U
1992 /******************* Bit definition for CAN_F3R1 register *******************/
1993 #define CAN_F3R1_FB0 0x00000001U
1994 #define CAN_F3R1_FB1 0x00000002U
1995 #define CAN_F3R1_FB2 0x00000004U
1996 #define CAN_F3R1_FB3 0x00000008U
1997 #define CAN_F3R1_FB4 0x00000010U
1998 #define CAN_F3R1_FB5 0x00000020U
1999 #define CAN_F3R1_FB6 0x00000040U
2000 #define CAN_F3R1_FB7 0x00000080U
2001 #define CAN_F3R1_FB8 0x00000100U
2002 #define CAN_F3R1_FB9 0x00000200U
2003 #define CAN_F3R1_FB10 0x00000400U
2004 #define CAN_F3R1_FB11 0x00000800U
2005 #define CAN_F3R1_FB12 0x00001000U
2006 #define CAN_F3R1_FB13 0x00002000U
2007 #define CAN_F3R1_FB14 0x00004000U
2008 #define CAN_F3R1_FB15 0x00008000U
2009 #define CAN_F3R1_FB16 0x00010000U
2010 #define CAN_F3R1_FB17 0x00020000U
2011 #define CAN_F3R1_FB18 0x00040000U
2012 #define CAN_F3R1_FB19 0x00080000U
2013 #define CAN_F3R1_FB20 0x00100000U
2014 #define CAN_F3R1_FB21 0x00200000U
2015 #define CAN_F3R1_FB22 0x00400000U
2016 #define CAN_F3R1_FB23 0x00800000U
2017 #define CAN_F3R1_FB24 0x01000000U
2018 #define CAN_F3R1_FB25 0x02000000U
2019 #define CAN_F3R1_FB26 0x04000000U
2020 #define CAN_F3R1_FB27 0x08000000U
2021 #define CAN_F3R1_FB28 0x10000000U
2022 #define CAN_F3R1_FB29 0x20000000U
2023 #define CAN_F3R1_FB30 0x40000000U
2024 #define CAN_F3R1_FB31 0x80000000U
2026 /******************* Bit definition for CAN_F4R1 register *******************/
2027 #define CAN_F4R1_FB0 0x00000001U
2028 #define CAN_F4R1_FB1 0x00000002U
2029 #define CAN_F4R1_FB2 0x00000004U
2030 #define CAN_F4R1_FB3 0x00000008U
2031 #define CAN_F4R1_FB4 0x00000010U
2032 #define CAN_F4R1_FB5 0x00000020U
2033 #define CAN_F4R1_FB6 0x00000040U
2034 #define CAN_F4R1_FB7 0x00000080U
2035 #define CAN_F4R1_FB8 0x00000100U
2036 #define CAN_F4R1_FB9 0x00000200U
2037 #define CAN_F4R1_FB10 0x00000400U
2038 #define CAN_F4R1_FB11 0x00000800U
2039 #define CAN_F4R1_FB12 0x00001000U
2040 #define CAN_F4R1_FB13 0x00002000U
2041 #define CAN_F4R1_FB14 0x00004000U
2042 #define CAN_F4R1_FB15 0x00008000U
2043 #define CAN_F4R1_FB16 0x00010000U
2044 #define CAN_F4R1_FB17 0x00020000U
2045 #define CAN_F4R1_FB18 0x00040000U
2046 #define CAN_F4R1_FB19 0x00080000U
2047 #define CAN_F4R1_FB20 0x00100000U
2048 #define CAN_F4R1_FB21 0x00200000U
2049 #define CAN_F4R1_FB22 0x00400000U
2050 #define CAN_F4R1_FB23 0x00800000U
2051 #define CAN_F4R1_FB24 0x01000000U
2052 #define CAN_F4R1_FB25 0x02000000U
2053 #define CAN_F4R1_FB26 0x04000000U
2054 #define CAN_F4R1_FB27 0x08000000U
2055 #define CAN_F4R1_FB28 0x10000000U
2056 #define CAN_F4R1_FB29 0x20000000U
2057 #define CAN_F4R1_FB30 0x40000000U
2058 #define CAN_F4R1_FB31 0x80000000U
2060 /******************* Bit definition for CAN_F5R1 register *******************/
2061 #define CAN_F5R1_FB0 0x00000001U
2062 #define CAN_F5R1_FB1 0x00000002U
2063 #define CAN_F5R1_FB2 0x00000004U
2064 #define CAN_F5R1_FB3 0x00000008U
2065 #define CAN_F5R1_FB4 0x00000010U
2066 #define CAN_F5R1_FB5 0x00000020U
2067 #define CAN_F5R1_FB6 0x00000040U
2068 #define CAN_F5R1_FB7 0x00000080U
2069 #define CAN_F5R1_FB8 0x00000100U
2070 #define CAN_F5R1_FB9 0x00000200U
2071 #define CAN_F5R1_FB10 0x00000400U
2072 #define CAN_F5R1_FB11 0x00000800U
2073 #define CAN_F5R1_FB12 0x00001000U
2074 #define CAN_F5R1_FB13 0x00002000U
2075 #define CAN_F5R1_FB14 0x00004000U
2076 #define CAN_F5R1_FB15 0x00008000U
2077 #define CAN_F5R1_FB16 0x00010000U
2078 #define CAN_F5R1_FB17 0x00020000U
2079 #define CAN_F5R1_FB18 0x00040000U
2080 #define CAN_F5R1_FB19 0x00080000U
2081 #define CAN_F5R1_FB20 0x00100000U
2082 #define CAN_F5R1_FB21 0x00200000U
2083 #define CAN_F5R1_FB22 0x00400000U
2084 #define CAN_F5R1_FB23 0x00800000U
2085 #define CAN_F5R1_FB24 0x01000000U
2086 #define CAN_F5R1_FB25 0x02000000U
2087 #define CAN_F5R1_FB26 0x04000000U
2088 #define CAN_F5R1_FB27 0x08000000U
2089 #define CAN_F5R1_FB28 0x10000000U
2090 #define CAN_F5R1_FB29 0x20000000U
2091 #define CAN_F5R1_FB30 0x40000000U
2092 #define CAN_F5R1_FB31 0x80000000U
2094 /******************* Bit definition for CAN_F6R1 register *******************/
2095 #define CAN_F6R1_FB0 0x00000001U
2096 #define CAN_F6R1_FB1 0x00000002U
2097 #define CAN_F6R1_FB2 0x00000004U
2098 #define CAN_F6R1_FB3 0x00000008U
2099 #define CAN_F6R1_FB4 0x00000010U
2100 #define CAN_F6R1_FB5 0x00000020U
2101 #define CAN_F6R1_FB6 0x00000040U
2102 #define CAN_F6R1_FB7 0x00000080U
2103 #define CAN_F6R1_FB8 0x00000100U
2104 #define CAN_F6R1_FB9 0x00000200U
2105 #define CAN_F6R1_FB10 0x00000400U
2106 #define CAN_F6R1_FB11 0x00000800U
2107 #define CAN_F6R1_FB12 0x00001000U
2108 #define CAN_F6R1_FB13 0x00002000U
2109 #define CAN_F6R1_FB14 0x00004000U
2110 #define CAN_F6R1_FB15 0x00008000U
2111 #define CAN_F6R1_FB16 0x00010000U
2112 #define CAN_F6R1_FB17 0x00020000U
2113 #define CAN_F6R1_FB18 0x00040000U
2114 #define CAN_F6R1_FB19 0x00080000U
2115 #define CAN_F6R1_FB20 0x00100000U
2116 #define CAN_F6R1_FB21 0x00200000U
2117 #define CAN_F6R1_FB22 0x00400000U
2118 #define CAN_F6R1_FB23 0x00800000U
2119 #define CAN_F6R1_FB24 0x01000000U
2120 #define CAN_F6R1_FB25 0x02000000U
2121 #define CAN_F6R1_FB26 0x04000000U
2122 #define CAN_F6R1_FB27 0x08000000U
2123 #define CAN_F6R1_FB28 0x10000000U
2124 #define CAN_F6R1_FB29 0x20000000U
2125 #define CAN_F6R1_FB30 0x40000000U
2126 #define CAN_F6R1_FB31 0x80000000U
2128 /******************* Bit definition for CAN_F7R1 register *******************/
2129 #define CAN_F7R1_FB0 0x00000001U
2130 #define CAN_F7R1_FB1 0x00000002U
2131 #define CAN_F7R1_FB2 0x00000004U
2132 #define CAN_F7R1_FB3 0x00000008U
2133 #define CAN_F7R1_FB4 0x00000010U
2134 #define CAN_F7R1_FB5 0x00000020U
2135 #define CAN_F7R1_FB6 0x00000040U
2136 #define CAN_F7R1_FB7 0x00000080U
2137 #define CAN_F7R1_FB8 0x00000100U
2138 #define CAN_F7R1_FB9 0x00000200U
2139 #define CAN_F7R1_FB10 0x00000400U
2140 #define CAN_F7R1_FB11 0x00000800U
2141 #define CAN_F7R1_FB12 0x00001000U
2142 #define CAN_F7R1_FB13 0x00002000U
2143 #define CAN_F7R1_FB14 0x00004000U
2144 #define CAN_F7R1_FB15 0x00008000U
2145 #define CAN_F7R1_FB16 0x00010000U
2146 #define CAN_F7R1_FB17 0x00020000U
2147 #define CAN_F7R1_FB18 0x00040000U
2148 #define CAN_F7R1_FB19 0x00080000U
2149 #define CAN_F7R1_FB20 0x00100000U
2150 #define CAN_F7R1_FB21 0x00200000U
2151 #define CAN_F7R1_FB22 0x00400000U
2152 #define CAN_F7R1_FB23 0x00800000U
2153 #define CAN_F7R1_FB24 0x01000000U
2154 #define CAN_F7R1_FB25 0x02000000U
2155 #define CAN_F7R1_FB26 0x04000000U
2156 #define CAN_F7R1_FB27 0x08000000U
2157 #define CAN_F7R1_FB28 0x10000000U
2158 #define CAN_F7R1_FB29 0x20000000U
2159 #define CAN_F7R1_FB30 0x40000000U
2160 #define CAN_F7R1_FB31 0x80000000U
2162 /******************* Bit definition for CAN_F8R1 register *******************/
2163 #define CAN_F8R1_FB0 0x00000001U
2164 #define CAN_F8R1_FB1 0x00000002U
2165 #define CAN_F8R1_FB2 0x00000004U
2166 #define CAN_F8R1_FB3 0x00000008U
2167 #define CAN_F8R1_FB4 0x00000010U
2168 #define CAN_F8R1_FB5 0x00000020U
2169 #define CAN_F8R1_FB6 0x00000040U
2170 #define CAN_F8R1_FB7 0x00000080U
2171 #define CAN_F8R1_FB8 0x00000100U
2172 #define CAN_F8R1_FB9 0x00000200U
2173 #define CAN_F8R1_FB10 0x00000400U
2174 #define CAN_F8R1_FB11 0x00000800U
2175 #define CAN_F8R1_FB12 0x00001000U
2176 #define CAN_F8R1_FB13 0x00002000U
2177 #define CAN_F8R1_FB14 0x00004000U
2178 #define CAN_F8R1_FB15 0x00008000U
2179 #define CAN_F8R1_FB16 0x00010000U
2180 #define CAN_F8R1_FB17 0x00020000U
2181 #define CAN_F8R1_FB18 0x00040000U
2182 #define CAN_F8R1_FB19 0x00080000U
2183 #define CAN_F8R1_FB20 0x00100000U
2184 #define CAN_F8R1_FB21 0x00200000U
2185 #define CAN_F8R1_FB22 0x00400000U
2186 #define CAN_F8R1_FB23 0x00800000U
2187 #define CAN_F8R1_FB24 0x01000000U
2188 #define CAN_F8R1_FB25 0x02000000U
2189 #define CAN_F8R1_FB26 0x04000000U
2190 #define CAN_F8R1_FB27 0x08000000U
2191 #define CAN_F8R1_FB28 0x10000000U
2192 #define CAN_F8R1_FB29 0x20000000U
2193 #define CAN_F8R1_FB30 0x40000000U
2194 #define CAN_F8R1_FB31 0x80000000U
2196 /******************* Bit definition for CAN_F9R1 register *******************/
2197 #define CAN_F9R1_FB0 0x00000001U
2198 #define CAN_F9R1_FB1 0x00000002U
2199 #define CAN_F9R1_FB2 0x00000004U
2200 #define CAN_F9R1_FB3 0x00000008U
2201 #define CAN_F9R1_FB4 0x00000010U
2202 #define CAN_F9R1_FB5 0x00000020U
2203 #define CAN_F9R1_FB6 0x00000040U
2204 #define CAN_F9R1_FB7 0x00000080U
2205 #define CAN_F9R1_FB8 0x00000100U
2206 #define CAN_F9R1_FB9 0x00000200U
2207 #define CAN_F9R1_FB10 0x00000400U
2208 #define CAN_F9R1_FB11 0x00000800U
2209 #define CAN_F9R1_FB12 0x00001000U
2210 #define CAN_F9R1_FB13 0x00002000U
2211 #define CAN_F9R1_FB14 0x00004000U
2212 #define CAN_F9R1_FB15 0x00008000U
2213 #define CAN_F9R1_FB16 0x00010000U
2214 #define CAN_F9R1_FB17 0x00020000U
2215 #define CAN_F9R1_FB18 0x00040000U
2216 #define CAN_F9R1_FB19 0x00080000U
2217 #define CAN_F9R1_FB20 0x00100000U
2218 #define CAN_F9R1_FB21 0x00200000U
2219 #define CAN_F9R1_FB22 0x00400000U
2220 #define CAN_F9R1_FB23 0x00800000U
2221 #define CAN_F9R1_FB24 0x01000000U
2222 #define CAN_F9R1_FB25 0x02000000U
2223 #define CAN_F9R1_FB26 0x04000000U
2224 #define CAN_F9R1_FB27 0x08000000U
2225 #define CAN_F9R1_FB28 0x10000000U
2226 #define CAN_F9R1_FB29 0x20000000U
2227 #define CAN_F9R1_FB30 0x40000000U
2228 #define CAN_F9R1_FB31 0x80000000U
2230 /******************* Bit definition for CAN_F10R1 register ******************/
2231 #define CAN_F10R1_FB0 0x00000001U
2232 #define CAN_F10R1_FB1 0x00000002U
2233 #define CAN_F10R1_FB2 0x00000004U
2234 #define CAN_F10R1_FB3 0x00000008U
2235 #define CAN_F10R1_FB4 0x00000010U
2236 #define CAN_F10R1_FB5 0x00000020U
2237 #define CAN_F10R1_FB6 0x00000040U
2238 #define CAN_F10R1_FB7 0x00000080U
2239 #define CAN_F10R1_FB8 0x00000100U
2240 #define CAN_F10R1_FB9 0x00000200U
2241 #define CAN_F10R1_FB10 0x00000400U
2242 #define CAN_F10R1_FB11 0x00000800U
2243 #define CAN_F10R1_FB12 0x00001000U
2244 #define CAN_F10R1_FB13 0x00002000U
2245 #define CAN_F10R1_FB14 0x00004000U
2246 #define CAN_F10R1_FB15 0x00008000U
2247 #define CAN_F10R1_FB16 0x00010000U
2248 #define CAN_F10R1_FB17 0x00020000U
2249 #define CAN_F10R1_FB18 0x00040000U
2250 #define CAN_F10R1_FB19 0x00080000U
2251 #define CAN_F10R1_FB20 0x00100000U
2252 #define CAN_F10R1_FB21 0x00200000U
2253 #define CAN_F10R1_FB22 0x00400000U
2254 #define CAN_F10R1_FB23 0x00800000U
2255 #define CAN_F10R1_FB24 0x01000000U
2256 #define CAN_F10R1_FB25 0x02000000U
2257 #define CAN_F10R1_FB26 0x04000000U
2258 #define CAN_F10R1_FB27 0x08000000U
2259 #define CAN_F10R1_FB28 0x10000000U
2260 #define CAN_F10R1_FB29 0x20000000U
2261 #define CAN_F10R1_FB30 0x40000000U
2262 #define CAN_F10R1_FB31 0x80000000U
2264 /******************* Bit definition for CAN_F11R1 register ******************/
2265 #define CAN_F11R1_FB0 0x00000001U
2266 #define CAN_F11R1_FB1 0x00000002U
2267 #define CAN_F11R1_FB2 0x00000004U
2268 #define CAN_F11R1_FB3 0x00000008U
2269 #define CAN_F11R1_FB4 0x00000010U
2270 #define CAN_F11R1_FB5 0x00000020U
2271 #define CAN_F11R1_FB6 0x00000040U
2272 #define CAN_F11R1_FB7 0x00000080U
2273 #define CAN_F11R1_FB8 0x00000100U
2274 #define CAN_F11R1_FB9 0x00000200U
2275 #define CAN_F11R1_FB10 0x00000400U
2276 #define CAN_F11R1_FB11 0x00000800U
2277 #define CAN_F11R1_FB12 0x00001000U
2278 #define CAN_F11R1_FB13 0x00002000U
2279 #define CAN_F11R1_FB14 0x00004000U
2280 #define CAN_F11R1_FB15 0x00008000U
2281 #define CAN_F11R1_FB16 0x00010000U
2282 #define CAN_F11R1_FB17 0x00020000U
2283 #define CAN_F11R1_FB18 0x00040000U
2284 #define CAN_F11R1_FB19 0x00080000U
2285 #define CAN_F11R1_FB20 0x00100000U
2286 #define CAN_F11R1_FB21 0x00200000U
2287 #define CAN_F11R1_FB22 0x00400000U
2288 #define CAN_F11R1_FB23 0x00800000U
2289 #define CAN_F11R1_FB24 0x01000000U
2290 #define CAN_F11R1_FB25 0x02000000U
2291 #define CAN_F11R1_FB26 0x04000000U
2292 #define CAN_F11R1_FB27 0x08000000U
2293 #define CAN_F11R1_FB28 0x10000000U
2294 #define CAN_F11R1_FB29 0x20000000U
2295 #define CAN_F11R1_FB30 0x40000000U
2296 #define CAN_F11R1_FB31 0x80000000U
2298 /******************* Bit definition for CAN_F12R1 register ******************/
2299 #define CAN_F12R1_FB0 0x00000001U
2300 #define CAN_F12R1_FB1 0x00000002U
2301 #define CAN_F12R1_FB2 0x00000004U
2302 #define CAN_F12R1_FB3 0x00000008U
2303 #define CAN_F12R1_FB4 0x00000010U
2304 #define CAN_F12R1_FB5 0x00000020U
2305 #define CAN_F12R1_FB6 0x00000040U
2306 #define CAN_F12R1_FB7 0x00000080U
2307 #define CAN_F12R1_FB8 0x00000100U
2308 #define CAN_F12R1_FB9 0x00000200U
2309 #define CAN_F12R1_FB10 0x00000400U
2310 #define CAN_F12R1_FB11 0x00000800U
2311 #define CAN_F12R1_FB12 0x00001000U
2312 #define CAN_F12R1_FB13 0x00002000U
2313 #define CAN_F12R1_FB14 0x00004000U
2314 #define CAN_F12R1_FB15 0x00008000U
2315 #define CAN_F12R1_FB16 0x00010000U
2316 #define CAN_F12R1_FB17 0x00020000U
2317 #define CAN_F12R1_FB18 0x00040000U
2318 #define CAN_F12R1_FB19 0x00080000U
2319 #define CAN_F12R1_FB20 0x00100000U
2320 #define CAN_F12R1_FB21 0x00200000U
2321 #define CAN_F12R1_FB22 0x00400000U
2322 #define CAN_F12R1_FB23 0x00800000U
2323 #define CAN_F12R1_FB24 0x01000000U
2324 #define CAN_F12R1_FB25 0x02000000U
2325 #define CAN_F12R1_FB26 0x04000000U
2326 #define CAN_F12R1_FB27 0x08000000U
2327 #define CAN_F12R1_FB28 0x10000000U
2328 #define CAN_F12R1_FB29 0x20000000U
2329 #define CAN_F12R1_FB30 0x40000000U
2330 #define CAN_F12R1_FB31 0x80000000U
2332 /******************* Bit definition for CAN_F13R1 register ******************/
2333 #define CAN_F13R1_FB0 0x00000001U
2334 #define CAN_F13R1_FB1 0x00000002U
2335 #define CAN_F13R1_FB2 0x00000004U
2336 #define CAN_F13R1_FB3 0x00000008U
2337 #define CAN_F13R1_FB4 0x00000010U
2338 #define CAN_F13R1_FB5 0x00000020U
2339 #define CAN_F13R1_FB6 0x00000040U
2340 #define CAN_F13R1_FB7 0x00000080U
2341 #define CAN_F13R1_FB8 0x00000100U
2342 #define CAN_F13R1_FB9 0x00000200U
2343 #define CAN_F13R1_FB10 0x00000400U
2344 #define CAN_F13R1_FB11 0x00000800U
2345 #define CAN_F13R1_FB12 0x00001000U
2346 #define CAN_F13R1_FB13 0x00002000U
2347 #define CAN_F13R1_FB14 0x00004000U
2348 #define CAN_F13R1_FB15 0x00008000U
2349 #define CAN_F13R1_FB16 0x00010000U
2350 #define CAN_F13R1_FB17 0x00020000U
2351 #define CAN_F13R1_FB18 0x00040000U
2352 #define CAN_F13R1_FB19 0x00080000U
2353 #define CAN_F13R1_FB20 0x00100000U
2354 #define CAN_F13R1_FB21 0x00200000U
2355 #define CAN_F13R1_FB22 0x00400000U
2356 #define CAN_F13R1_FB23 0x00800000U
2357 #define CAN_F13R1_FB24 0x01000000U
2358 #define CAN_F13R1_FB25 0x02000000U
2359 #define CAN_F13R1_FB26 0x04000000U
2360 #define CAN_F13R1_FB27 0x08000000U
2361 #define CAN_F13R1_FB28 0x10000000U
2362 #define CAN_F13R1_FB29 0x20000000U
2363 #define CAN_F13R1_FB30 0x40000000U
2364 #define CAN_F13R1_FB31 0x80000000U
2366 /******************* Bit definition for CAN_F0R2 register *******************/
2367 #define CAN_F0R2_FB0 0x00000001U
2368 #define CAN_F0R2_FB1 0x00000002U
2369 #define CAN_F0R2_FB2 0x00000004U
2370 #define CAN_F0R2_FB3 0x00000008U
2371 #define CAN_F0R2_FB4 0x00000010U
2372 #define CAN_F0R2_FB5 0x00000020U
2373 #define CAN_F0R2_FB6 0x00000040U
2374 #define CAN_F0R2_FB7 0x00000080U
2375 #define CAN_F0R2_FB8 0x00000100U
2376 #define CAN_F0R2_FB9 0x00000200U
2377 #define CAN_F0R2_FB10 0x00000400U
2378 #define CAN_F0R2_FB11 0x00000800U
2379 #define CAN_F0R2_FB12 0x00001000U
2380 #define CAN_F0R2_FB13 0x00002000U
2381 #define CAN_F0R2_FB14 0x00004000U
2382 #define CAN_F0R2_FB15 0x00008000U
2383 #define CAN_F0R2_FB16 0x00010000U
2384 #define CAN_F0R2_FB17 0x00020000U
2385 #define CAN_F0R2_FB18 0x00040000U
2386 #define CAN_F0R2_FB19 0x00080000U
2387 #define CAN_F0R2_FB20 0x00100000U
2388 #define CAN_F0R2_FB21 0x00200000U
2389 #define CAN_F0R2_FB22 0x00400000U
2390 #define CAN_F0R2_FB23 0x00800000U
2391 #define CAN_F0R2_FB24 0x01000000U
2392 #define CAN_F0R2_FB25 0x02000000U
2393 #define CAN_F0R2_FB26 0x04000000U
2394 #define CAN_F0R2_FB27 0x08000000U
2395 #define CAN_F0R2_FB28 0x10000000U
2396 #define CAN_F0R2_FB29 0x20000000U
2397 #define CAN_F0R2_FB30 0x40000000U
2398 #define CAN_F0R2_FB31 0x80000000U
2400 /******************* Bit definition for CAN_F1R2 register *******************/
2401 #define CAN_F1R2_FB0 0x00000001U
2402 #define CAN_F1R2_FB1 0x00000002U
2403 #define CAN_F1R2_FB2 0x00000004U
2404 #define CAN_F1R2_FB3 0x00000008U
2405 #define CAN_F1R2_FB4 0x00000010U
2406 #define CAN_F1R2_FB5 0x00000020U
2407 #define CAN_F1R2_FB6 0x00000040U
2408 #define CAN_F1R2_FB7 0x00000080U
2409 #define CAN_F1R2_FB8 0x00000100U
2410 #define CAN_F1R2_FB9 0x00000200U
2411 #define CAN_F1R2_FB10 0x00000400U
2412 #define CAN_F1R2_FB11 0x00000800U
2413 #define CAN_F1R2_FB12 0x00001000U
2414 #define CAN_F1R2_FB13 0x00002000U
2415 #define CAN_F1R2_FB14 0x00004000U
2416 #define CAN_F1R2_FB15 0x00008000U
2417 #define CAN_F1R2_FB16 0x00010000U
2418 #define CAN_F1R2_FB17 0x00020000U
2419 #define CAN_F1R2_FB18 0x00040000U
2420 #define CAN_F1R2_FB19 0x00080000U
2421 #define CAN_F1R2_FB20 0x00100000U
2422 #define CAN_F1R2_FB21 0x00200000U
2423 #define CAN_F1R2_FB22 0x00400000U
2424 #define CAN_F1R2_FB23 0x00800000U
2425 #define CAN_F1R2_FB24 0x01000000U
2426 #define CAN_F1R2_FB25 0x02000000U
2427 #define CAN_F1R2_FB26 0x04000000U
2428 #define CAN_F1R2_FB27 0x08000000U
2429 #define CAN_F1R2_FB28 0x10000000U
2430 #define CAN_F1R2_FB29 0x20000000U
2431 #define CAN_F1R2_FB30 0x40000000U
2432 #define CAN_F1R2_FB31 0x80000000U
2434 /******************* Bit definition for CAN_F2R2 register *******************/
2435 #define CAN_F2R2_FB0 0x00000001U
2436 #define CAN_F2R2_FB1 0x00000002U
2437 #define CAN_F2R2_FB2 0x00000004U
2438 #define CAN_F2R2_FB3 0x00000008U
2439 #define CAN_F2R2_FB4 0x00000010U
2440 #define CAN_F2R2_FB5 0x00000020U
2441 #define CAN_F2R2_FB6 0x00000040U
2442 #define CAN_F2R2_FB7 0x00000080U
2443 #define CAN_F2R2_FB8 0x00000100U
2444 #define CAN_F2R2_FB9 0x00000200U
2445 #define CAN_F2R2_FB10 0x00000400U
2446 #define CAN_F2R2_FB11 0x00000800U
2447 #define CAN_F2R2_FB12 0x00001000U
2448 #define CAN_F2R2_FB13 0x00002000U
2449 #define CAN_F2R2_FB14 0x00004000U
2450 #define CAN_F2R2_FB15 0x00008000U
2451 #define CAN_F2R2_FB16 0x00010000U
2452 #define CAN_F2R2_FB17 0x00020000U
2453 #define CAN_F2R2_FB18 0x00040000U
2454 #define CAN_F2R2_FB19 0x00080000U
2455 #define CAN_F2R2_FB20 0x00100000U
2456 #define CAN_F2R2_FB21 0x00200000U
2457 #define CAN_F2R2_FB22 0x00400000U
2458 #define CAN_F2R2_FB23 0x00800000U
2459 #define CAN_F2R2_FB24 0x01000000U
2460 #define CAN_F2R2_FB25 0x02000000U
2461 #define CAN_F2R2_FB26 0x04000000U
2462 #define CAN_F2R2_FB27 0x08000000U
2463 #define CAN_F2R2_FB28 0x10000000U
2464 #define CAN_F2R2_FB29 0x20000000U
2465 #define CAN_F2R2_FB30 0x40000000U
2466 #define CAN_F2R2_FB31 0x80000000U
2468 /******************* Bit definition for CAN_F3R2 register *******************/
2469 #define CAN_F3R2_FB0 0x00000001U
2470 #define CAN_F3R2_FB1 0x00000002U
2471 #define CAN_F3R2_FB2 0x00000004U
2472 #define CAN_F3R2_FB3 0x00000008U
2473 #define CAN_F3R2_FB4 0x00000010U
2474 #define CAN_F3R2_FB5 0x00000020U
2475 #define CAN_F3R2_FB6 0x00000040U
2476 #define CAN_F3R2_FB7 0x00000080U
2477 #define CAN_F3R2_FB8 0x00000100U
2478 #define CAN_F3R2_FB9 0x00000200U
2479 #define CAN_F3R2_FB10 0x00000400U
2480 #define CAN_F3R2_FB11 0x00000800U
2481 #define CAN_F3R2_FB12 0x00001000U
2482 #define CAN_F3R2_FB13 0x00002000U
2483 #define CAN_F3R2_FB14 0x00004000U
2484 #define CAN_F3R2_FB15 0x00008000U
2485 #define CAN_F3R2_FB16 0x00010000U
2486 #define CAN_F3R2_FB17 0x00020000U
2487 #define CAN_F3R2_FB18 0x00040000U
2488 #define CAN_F3R2_FB19 0x00080000U
2489 #define CAN_F3R2_FB20 0x00100000U
2490 #define CAN_F3R2_FB21 0x00200000U
2491 #define CAN_F3R2_FB22 0x00400000U
2492 #define CAN_F3R2_FB23 0x00800000U
2493 #define CAN_F3R2_FB24 0x01000000U
2494 #define CAN_F3R2_FB25 0x02000000U
2495 #define CAN_F3R2_FB26 0x04000000U
2496 #define CAN_F3R2_FB27 0x08000000U
2497 #define CAN_F3R2_FB28 0x10000000U
2498 #define CAN_F3R2_FB29 0x20000000U
2499 #define CAN_F3R2_FB30 0x40000000U
2500 #define CAN_F3R2_FB31 0x80000000U
2502 /******************* Bit definition for CAN_F4R2 register *******************/
2503 #define CAN_F4R2_FB0 0x00000001U
2504 #define CAN_F4R2_FB1 0x00000002U
2505 #define CAN_F4R2_FB2 0x00000004U
2506 #define CAN_F4R2_FB3 0x00000008U
2507 #define CAN_F4R2_FB4 0x00000010U
2508 #define CAN_F4R2_FB5 0x00000020U
2509 #define CAN_F4R2_FB6 0x00000040U
2510 #define CAN_F4R2_FB7 0x00000080U
2511 #define CAN_F4R2_FB8 0x00000100U
2512 #define CAN_F4R2_FB9 0x00000200U
2513 #define CAN_F4R2_FB10 0x00000400U
2514 #define CAN_F4R2_FB11 0x00000800U
2515 #define CAN_F4R2_FB12 0x00001000U
2516 #define CAN_F4R2_FB13 0x00002000U
2517 #define CAN_F4R2_FB14 0x00004000U
2518 #define CAN_F4R2_FB15 0x00008000U
2519 #define CAN_F4R2_FB16 0x00010000U
2520 #define CAN_F4R2_FB17 0x00020000U
2521 #define CAN_F4R2_FB18 0x00040000U
2522 #define CAN_F4R2_FB19 0x00080000U
2523 #define CAN_F4R2_FB20 0x00100000U
2524 #define CAN_F4R2_FB21 0x00200000U
2525 #define CAN_F4R2_FB22 0x00400000U
2526 #define CAN_F4R2_FB23 0x00800000U
2527 #define CAN_F4R2_FB24 0x01000000U
2528 #define CAN_F4R2_FB25 0x02000000U
2529 #define CAN_F4R2_FB26 0x04000000U
2530 #define CAN_F4R2_FB27 0x08000000U
2531 #define CAN_F4R2_FB28 0x10000000U
2532 #define CAN_F4R2_FB29 0x20000000U
2533 #define CAN_F4R2_FB30 0x40000000U
2534 #define CAN_F4R2_FB31 0x80000000U
2536 /******************* Bit definition for CAN_F5R2 register *******************/
2537 #define CAN_F5R2_FB0 0x00000001U
2538 #define CAN_F5R2_FB1 0x00000002U
2539 #define CAN_F5R2_FB2 0x00000004U
2540 #define CAN_F5R2_FB3 0x00000008U
2541 #define CAN_F5R2_FB4 0x00000010U
2542 #define CAN_F5R2_FB5 0x00000020U
2543 #define CAN_F5R2_FB6 0x00000040U
2544 #define CAN_F5R2_FB7 0x00000080U
2545 #define CAN_F5R2_FB8 0x00000100U
2546 #define CAN_F5R2_FB9 0x00000200U
2547 #define CAN_F5R2_FB10 0x00000400U
2548 #define CAN_F5R2_FB11 0x00000800U
2549 #define CAN_F5R2_FB12 0x00001000U
2550 #define CAN_F5R2_FB13 0x00002000U
2551 #define CAN_F5R2_FB14 0x00004000U
2552 #define CAN_F5R2_FB15 0x00008000U
2553 #define CAN_F5R2_FB16 0x00010000U
2554 #define CAN_F5R2_FB17 0x00020000U
2555 #define CAN_F5R2_FB18 0x00040000U
2556 #define CAN_F5R2_FB19 0x00080000U
2557 #define CAN_F5R2_FB20 0x00100000U
2558 #define CAN_F5R2_FB21 0x00200000U
2559 #define CAN_F5R2_FB22 0x00400000U
2560 #define CAN_F5R2_FB23 0x00800000U
2561 #define CAN_F5R2_FB24 0x01000000U
2562 #define CAN_F5R2_FB25 0x02000000U
2563 #define CAN_F5R2_FB26 0x04000000U
2564 #define CAN_F5R2_FB27 0x08000000U
2565 #define CAN_F5R2_FB28 0x10000000U
2566 #define CAN_F5R2_FB29 0x20000000U
2567 #define CAN_F5R2_FB30 0x40000000U
2568 #define CAN_F5R2_FB31 0x80000000U
2570 /******************* Bit definition for CAN_F6R2 register *******************/
2571 #define CAN_F6R2_FB0 0x00000001U
2572 #define CAN_F6R2_FB1 0x00000002U
2573 #define CAN_F6R2_FB2 0x00000004U
2574 #define CAN_F6R2_FB3 0x00000008U
2575 #define CAN_F6R2_FB4 0x00000010U
2576 #define CAN_F6R2_FB5 0x00000020U
2577 #define CAN_F6R2_FB6 0x00000040U
2578 #define CAN_F6R2_FB7 0x00000080U
2579 #define CAN_F6R2_FB8 0x00000100U
2580 #define CAN_F6R2_FB9 0x00000200U
2581 #define CAN_F6R2_FB10 0x00000400U
2582 #define CAN_F6R2_FB11 0x00000800U
2583 #define CAN_F6R2_FB12 0x00001000U
2584 #define CAN_F6R2_FB13 0x00002000U
2585 #define CAN_F6R2_FB14 0x00004000U
2586 #define CAN_F6R2_FB15 0x00008000U
2587 #define CAN_F6R2_FB16 0x00010000U
2588 #define CAN_F6R2_FB17 0x00020000U
2589 #define CAN_F6R2_FB18 0x00040000U
2590 #define CAN_F6R2_FB19 0x00080000U
2591 #define CAN_F6R2_FB20 0x00100000U
2592 #define CAN_F6R2_FB21 0x00200000U
2593 #define CAN_F6R2_FB22 0x00400000U
2594 #define CAN_F6R2_FB23 0x00800000U
2595 #define CAN_F6R2_FB24 0x01000000U
2596 #define CAN_F6R2_FB25 0x02000000U
2597 #define CAN_F6R2_FB26 0x04000000U
2598 #define CAN_F6R2_FB27 0x08000000U
2599 #define CAN_F6R2_FB28 0x10000000U
2600 #define CAN_F6R2_FB29 0x20000000U
2601 #define CAN_F6R2_FB30 0x40000000U
2602 #define CAN_F6R2_FB31 0x80000000U
2604 /******************* Bit definition for CAN_F7R2 register *******************/
2605 #define CAN_F7R2_FB0 0x00000001U
2606 #define CAN_F7R2_FB1 0x00000002U
2607 #define CAN_F7R2_FB2 0x00000004U
2608 #define CAN_F7R2_FB3 0x00000008U
2609 #define CAN_F7R2_FB4 0x00000010U
2610 #define CAN_F7R2_FB5 0x00000020U
2611 #define CAN_F7R2_FB6 0x00000040U
2612 #define CAN_F7R2_FB7 0x00000080U
2613 #define CAN_F7R2_FB8 0x00000100U
2614 #define CAN_F7R2_FB9 0x00000200U
2615 #define CAN_F7R2_FB10 0x00000400U
2616 #define CAN_F7R2_FB11 0x00000800U
2617 #define CAN_F7R2_FB12 0x00001000U
2618 #define CAN_F7R2_FB13 0x00002000U
2619 #define CAN_F7R2_FB14 0x00004000U
2620 #define CAN_F7R2_FB15 0x00008000U
2621 #define CAN_F7R2_FB16 0x00010000U
2622 #define CAN_F7R2_FB17 0x00020000U
2623 #define CAN_F7R2_FB18 0x00040000U
2624 #define CAN_F7R2_FB19 0x00080000U
2625 #define CAN_F7R2_FB20 0x00100000U
2626 #define CAN_F7R2_FB21 0x00200000U
2627 #define CAN_F7R2_FB22 0x00400000U
2628 #define CAN_F7R2_FB23 0x00800000U
2629 #define CAN_F7R2_FB24 0x01000000U
2630 #define CAN_F7R2_FB25 0x02000000U
2631 #define CAN_F7R2_FB26 0x04000000U
2632 #define CAN_F7R2_FB27 0x08000000U
2633 #define CAN_F7R2_FB28 0x10000000U
2634 #define CAN_F7R2_FB29 0x20000000U
2635 #define CAN_F7R2_FB30 0x40000000U
2636 #define CAN_F7R2_FB31 0x80000000U
2638 /******************* Bit definition for CAN_F8R2 register *******************/
2639 #define CAN_F8R2_FB0 0x00000001U
2640 #define CAN_F8R2_FB1 0x00000002U
2641 #define CAN_F8R2_FB2 0x00000004U
2642 #define CAN_F8R2_FB3 0x00000008U
2643 #define CAN_F8R2_FB4 0x00000010U
2644 #define CAN_F8R2_FB5 0x00000020U
2645 #define CAN_F8R2_FB6 0x00000040U
2646 #define CAN_F8R2_FB7 0x00000080U
2647 #define CAN_F8R2_FB8 0x00000100U
2648 #define CAN_F8R2_FB9 0x00000200U
2649 #define CAN_F8R2_FB10 0x00000400U
2650 #define CAN_F8R2_FB11 0x00000800U
2651 #define CAN_F8R2_FB12 0x00001000U
2652 #define CAN_F8R2_FB13 0x00002000U
2653 #define CAN_F8R2_FB14 0x00004000U
2654 #define CAN_F8R2_FB15 0x00008000U
2655 #define CAN_F8R2_FB16 0x00010000U
2656 #define CAN_F8R2_FB17 0x00020000U
2657 #define CAN_F8R2_FB18 0x00040000U
2658 #define CAN_F8R2_FB19 0x00080000U
2659 #define CAN_F8R2_FB20 0x00100000U
2660 #define CAN_F8R2_FB21 0x00200000U
2661 #define CAN_F8R2_FB22 0x00400000U
2662 #define CAN_F8R2_FB23 0x00800000U
2663 #define CAN_F8R2_FB24 0x01000000U
2664 #define CAN_F8R2_FB25 0x02000000U
2665 #define CAN_F8R2_FB26 0x04000000U
2666 #define CAN_F8R2_FB27 0x08000000U
2667 #define CAN_F8R2_FB28 0x10000000U
2668 #define CAN_F8R2_FB29 0x20000000U
2669 #define CAN_F8R2_FB30 0x40000000U
2670 #define CAN_F8R2_FB31 0x80000000U
2672 /******************* Bit definition for CAN_F9R2 register *******************/
2673 #define CAN_F9R2_FB0 0x00000001U
2674 #define CAN_F9R2_FB1 0x00000002U
2675 #define CAN_F9R2_FB2 0x00000004U
2676 #define CAN_F9R2_FB3 0x00000008U
2677 #define CAN_F9R2_FB4 0x00000010U
2678 #define CAN_F9R2_FB5 0x00000020U
2679 #define CAN_F9R2_FB6 0x00000040U
2680 #define CAN_F9R2_FB7 0x00000080U
2681 #define CAN_F9R2_FB8 0x00000100U
2682 #define CAN_F9R2_FB9 0x00000200U
2683 #define CAN_F9R2_FB10 0x00000400U
2684 #define CAN_F9R2_FB11 0x00000800U
2685 #define CAN_F9R2_FB12 0x00001000U
2686 #define CAN_F9R2_FB13 0x00002000U
2687 #define CAN_F9R2_FB14 0x00004000U
2688 #define CAN_F9R2_FB15 0x00008000U
2689 #define CAN_F9R2_FB16 0x00010000U
2690 #define CAN_F9R2_FB17 0x00020000U
2691 #define CAN_F9R2_FB18 0x00040000U
2692 #define CAN_F9R2_FB19 0x00080000U
2693 #define CAN_F9R2_FB20 0x00100000U
2694 #define CAN_F9R2_FB21 0x00200000U
2695 #define CAN_F9R2_FB22 0x00400000U
2696 #define CAN_F9R2_FB23 0x00800000U
2697 #define CAN_F9R2_FB24 0x01000000U
2698 #define CAN_F9R2_FB25 0x02000000U
2699 #define CAN_F9R2_FB26 0x04000000U
2700 #define CAN_F9R2_FB27 0x08000000U
2701 #define CAN_F9R2_FB28 0x10000000U
2702 #define CAN_F9R2_FB29 0x20000000U
2703 #define CAN_F9R2_FB30 0x40000000U
2704 #define CAN_F9R2_FB31 0x80000000U
2706 /******************* Bit definition for CAN_F10R2 register ******************/
2707 #define CAN_F10R2_FB0 0x00000001U
2708 #define CAN_F10R2_FB1 0x00000002U
2709 #define CAN_F10R2_FB2 0x00000004U
2710 #define CAN_F10R2_FB3 0x00000008U
2711 #define CAN_F10R2_FB4 0x00000010U
2712 #define CAN_F10R2_FB5 0x00000020U
2713 #define CAN_F10R2_FB6 0x00000040U
2714 #define CAN_F10R2_FB7 0x00000080U
2715 #define CAN_F10R2_FB8 0x00000100U
2716 #define CAN_F10R2_FB9 0x00000200U
2717 #define CAN_F10R2_FB10 0x00000400U
2718 #define CAN_F10R2_FB11 0x00000800U
2719 #define CAN_F10R2_FB12 0x00001000U
2720 #define CAN_F10R2_FB13 0x00002000U
2721 #define CAN_F10R2_FB14 0x00004000U
2722 #define CAN_F10R2_FB15 0x00008000U
2723 #define CAN_F10R2_FB16 0x00010000U
2724 #define CAN_F10R2_FB17 0x00020000U
2725 #define CAN_F10R2_FB18 0x00040000U
2726 #define CAN_F10R2_FB19 0x00080000U
2727 #define CAN_F10R2_FB20 0x00100000U
2728 #define CAN_F10R2_FB21 0x00200000U
2729 #define CAN_F10R2_FB22 0x00400000U
2730 #define CAN_F10R2_FB23 0x00800000U
2731 #define CAN_F10R2_FB24 0x01000000U
2732 #define CAN_F10R2_FB25 0x02000000U
2733 #define CAN_F10R2_FB26 0x04000000U
2734 #define CAN_F10R2_FB27 0x08000000U
2735 #define CAN_F10R2_FB28 0x10000000U
2736 #define CAN_F10R2_FB29 0x20000000U
2737 #define CAN_F10R2_FB30 0x40000000U
2738 #define CAN_F10R2_FB31 0x80000000U
2740 /******************* Bit definition for CAN_F11R2 register ******************/
2741 #define CAN_F11R2_FB0 0x00000001U
2742 #define CAN_F11R2_FB1 0x00000002U
2743 #define CAN_F11R2_FB2 0x00000004U
2744 #define CAN_F11R2_FB3 0x00000008U
2745 #define CAN_F11R2_FB4 0x00000010U
2746 #define CAN_F11R2_FB5 0x00000020U
2747 #define CAN_F11R2_FB6 0x00000040U
2748 #define CAN_F11R2_FB7 0x00000080U
2749 #define CAN_F11R2_FB8 0x00000100U
2750 #define CAN_F11R2_FB9 0x00000200U
2751 #define CAN_F11R2_FB10 0x00000400U
2752 #define CAN_F11R2_FB11 0x00000800U
2753 #define CAN_F11R2_FB12 0x00001000U
2754 #define CAN_F11R2_FB13 0x00002000U
2755 #define CAN_F11R2_FB14 0x00004000U
2756 #define CAN_F11R2_FB15 0x00008000U
2757 #define CAN_F11R2_FB16 0x00010000U
2758 #define CAN_F11R2_FB17 0x00020000U
2759 #define CAN_F11R2_FB18 0x00040000U
2760 #define CAN_F11R2_FB19 0x00080000U
2761 #define CAN_F11R2_FB20 0x00100000U
2762 #define CAN_F11R2_FB21 0x00200000U
2763 #define CAN_F11R2_FB22 0x00400000U
2764 #define CAN_F11R2_FB23 0x00800000U
2765 #define CAN_F11R2_FB24 0x01000000U
2766 #define CAN_F11R2_FB25 0x02000000U
2767 #define CAN_F11R2_FB26 0x04000000U
2768 #define CAN_F11R2_FB27 0x08000000U
2769 #define CAN_F11R2_FB28 0x10000000U
2770 #define CAN_F11R2_FB29 0x20000000U
2771 #define CAN_F11R2_FB30 0x40000000U
2772 #define CAN_F11R2_FB31 0x80000000U
2774 /******************* Bit definition for CAN_F12R2 register ******************/
2775 #define CAN_F12R2_FB0 0x00000001U
2776 #define CAN_F12R2_FB1 0x00000002U
2777 #define CAN_F12R2_FB2 0x00000004U
2778 #define CAN_F12R2_FB3 0x00000008U
2779 #define CAN_F12R2_FB4 0x00000010U
2780 #define CAN_F12R2_FB5 0x00000020U
2781 #define CAN_F12R2_FB6 0x00000040U
2782 #define CAN_F12R2_FB7 0x00000080U
2783 #define CAN_F12R2_FB8 0x00000100U
2784 #define CAN_F12R2_FB9 0x00000200U
2785 #define CAN_F12R2_FB10 0x00000400U
2786 #define CAN_F12R2_FB11 0x00000800U
2787 #define CAN_F12R2_FB12 0x00001000U
2788 #define CAN_F12R2_FB13 0x00002000U
2789 #define CAN_F12R2_FB14 0x00004000U
2790 #define CAN_F12R2_FB15 0x00008000U
2791 #define CAN_F12R2_FB16 0x00010000U
2792 #define CAN_F12R2_FB17 0x00020000U
2793 #define CAN_F12R2_FB18 0x00040000U
2794 #define CAN_F12R2_FB19 0x00080000U
2795 #define CAN_F12R2_FB20 0x00100000U
2796 #define CAN_F12R2_FB21 0x00200000U
2797 #define CAN_F12R2_FB22 0x00400000U
2798 #define CAN_F12R2_FB23 0x00800000U
2799 #define CAN_F12R2_FB24 0x01000000U
2800 #define CAN_F12R2_FB25 0x02000000U
2801 #define CAN_F12R2_FB26 0x04000000U
2802 #define CAN_F12R2_FB27 0x08000000U
2803 #define CAN_F12R2_FB28 0x10000000U
2804 #define CAN_F12R2_FB29 0x20000000U
2805 #define CAN_F12R2_FB30 0x40000000U
2806 #define CAN_F12R2_FB31 0x80000000U
2808 /******************* Bit definition for CAN_F13R2 register ******************/
2809 #define CAN_F13R2_FB0 0x00000001U
2810 #define CAN_F13R2_FB1 0x00000002U
2811 #define CAN_F13R2_FB2 0x00000004U
2812 #define CAN_F13R2_FB3 0x00000008U
2813 #define CAN_F13R2_FB4 0x00000010U
2814 #define CAN_F13R2_FB5 0x00000020U
2815 #define CAN_F13R2_FB6 0x00000040U
2816 #define CAN_F13R2_FB7 0x00000080U
2817 #define CAN_F13R2_FB8 0x00000100U
2818 #define CAN_F13R2_FB9 0x00000200U
2819 #define CAN_F13R2_FB10 0x00000400U
2820 #define CAN_F13R2_FB11 0x00000800U
2821 #define CAN_F13R2_FB12 0x00001000U
2822 #define CAN_F13R2_FB13 0x00002000U
2823 #define CAN_F13R2_FB14 0x00004000U
2824 #define CAN_F13R2_FB15 0x00008000U
2825 #define CAN_F13R2_FB16 0x00010000U
2826 #define CAN_F13R2_FB17 0x00020000U
2827 #define CAN_F13R2_FB18 0x00040000U
2828 #define CAN_F13R2_FB19 0x00080000U
2829 #define CAN_F13R2_FB20 0x00100000U
2830 #define CAN_F13R2_FB21 0x00200000U
2831 #define CAN_F13R2_FB22 0x00400000U
2832 #define CAN_F13R2_FB23 0x00800000U
2833 #define CAN_F13R2_FB24 0x01000000U
2834 #define CAN_F13R2_FB25 0x02000000U
2835 #define CAN_F13R2_FB26 0x04000000U
2836 #define CAN_F13R2_FB27 0x08000000U
2837 #define CAN_F13R2_FB28 0x10000000U
2838 #define CAN_F13R2_FB29 0x20000000U
2839 #define CAN_F13R2_FB30 0x40000000U
2840 #define CAN_F13R2_FB31 0x80000000U
2842 /******************************************************************************/
2843 /* */
2844 /* CRC calculation unit */
2845 /* */
2846 /******************************************************************************/
2847 /******************* Bit definition for CRC_DR register *********************/
2848 #define CRC_DR_DR 0xFFFFFFFFU
2851 /******************* Bit definition for CRC_IDR register ********************/
2852 #define CRC_IDR_IDR 0xFFU
2855 /******************** Bit definition for CRC_CR register ********************/
2856 #define CRC_CR_RESET 0x01U
2858 /******************************************************************************/
2859 /* */
2860 /* Crypto Processor */
2861 /* */
2862 /******************************************************************************/
2863 /******************* Bits definition for CRYP_CR register ********************/
2864 #define CRYP_CR_ALGODIR 0x00000004U
2865 
2866 #define CRYP_CR_ALGOMODE 0x00080038U
2867 #define CRYP_CR_ALGOMODE_0 0x00000008U
2868 #define CRYP_CR_ALGOMODE_1 0x00000010U
2869 #define CRYP_CR_ALGOMODE_2 0x00000020U
2870 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
2871 #define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
2872 #define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
2873 #define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
2874 #define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
2875 #define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
2876 #define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
2877 #define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
2878 
2879 #define CRYP_CR_DATATYPE 0x000000C0U
2880 #define CRYP_CR_DATATYPE_0 0x00000040U
2881 #define CRYP_CR_DATATYPE_1 0x00000080U
2882 #define CRYP_CR_KEYSIZE 0x00000300U
2883 #define CRYP_CR_KEYSIZE_0 0x00000100U
2884 #define CRYP_CR_KEYSIZE_1 0x00000200U
2885 #define CRYP_CR_FFLUSH 0x00004000U
2886 #define CRYP_CR_CRYPEN 0x00008000U
2887 
2888 #define CRYP_CR_GCM_CCMPH 0x00030000U
2889 #define CRYP_CR_GCM_CCMPH_0 0x00010000U
2890 #define CRYP_CR_GCM_CCMPH_1 0x00020000U
2891 #define CRYP_CR_ALGOMODE_3 0x00080000U
2892 
2893 /****************** Bits definition for CRYP_SR register *********************/
2894 #define CRYP_SR_IFEM 0x00000001U
2895 #define CRYP_SR_IFNF 0x00000002U
2896 #define CRYP_SR_OFNE 0x00000004U
2897 #define CRYP_SR_OFFU 0x00000008U
2898 #define CRYP_SR_BUSY 0x00000010U
2899 /****************** Bits definition for CRYP_DMACR register ******************/
2900 #define CRYP_DMACR_DIEN 0x00000001U
2901 #define CRYP_DMACR_DOEN 0x00000002U
2902 /***************** Bits definition for CRYP_IMSCR register ******************/
2903 #define CRYP_IMSCR_INIM 0x00000001U
2904 #define CRYP_IMSCR_OUTIM 0x00000002U
2905 /****************** Bits definition for CRYP_RISR register *******************/
2906 #define CRYP_RISR_OUTRIS 0x00000001U
2907 #define CRYP_RISR_INRIS 0x00000002U
2908 /****************** Bits definition for CRYP_MISR register *******************/
2909 #define CRYP_MISR_INMIS 0x00000001U
2910 #define CRYP_MISR_OUTMIS 0x00000002U
2911 
2912 /******************************************************************************/
2913 /* */
2914 /* Digital to Analog Converter */
2915 /* */
2916 /******************************************************************************/
2917 /******************** Bit definition for DAC_CR register ********************/
2918 #define DAC_CR_EN1 0x00000001U
2919 #define DAC_CR_BOFF1 0x00000002U
2920 #define DAC_CR_TEN1 0x00000004U
2922 #define DAC_CR_TSEL1 0x00000038U
2923 #define DAC_CR_TSEL1_0 0x00000008U
2924 #define DAC_CR_TSEL1_1 0x00000010U
2925 #define DAC_CR_TSEL1_2 0x00000020U
2927 #define DAC_CR_WAVE1 0x000000C0U
2928 #define DAC_CR_WAVE1_0 0x00000040U
2929 #define DAC_CR_WAVE1_1 0x00000080U
2931 #define DAC_CR_MAMP1 0x00000F00U
2932 #define DAC_CR_MAMP1_0 0x00000100U
2933 #define DAC_CR_MAMP1_1 0x00000200U
2934 #define DAC_CR_MAMP1_2 0x00000400U
2935 #define DAC_CR_MAMP1_3 0x00000800U
2937 #define DAC_CR_DMAEN1 0x00001000U
2938 #define DAC_CR_DMAUDRIE1 0x00002000U
2939 #define DAC_CR_EN2 0x00010000U
2940 #define DAC_CR_BOFF2 0x00020000U
2941 #define DAC_CR_TEN2 0x00040000U
2943 #define DAC_CR_TSEL2 0x00380000U
2944 #define DAC_CR_TSEL2_0 0x00080000U
2945 #define DAC_CR_TSEL2_1 0x00100000U
2946 #define DAC_CR_TSEL2_2 0x00200000U
2948 #define DAC_CR_WAVE2 0x00C00000U
2949 #define DAC_CR_WAVE2_0 0x00400000U
2950 #define DAC_CR_WAVE2_1 0x00800000U
2952 #define DAC_CR_MAMP2 0x0F000000U
2953 #define DAC_CR_MAMP2_0 0x01000000U
2954 #define DAC_CR_MAMP2_1 0x02000000U
2955 #define DAC_CR_MAMP2_2 0x04000000U
2956 #define DAC_CR_MAMP2_3 0x08000000U
2958 #define DAC_CR_DMAEN2 0x10000000U
2959 #define DAC_CR_DMAUDRIE2 0x20000000U
2961 /***************** Bit definition for DAC_SWTRIGR register ******************/
2962 #define DAC_SWTRIGR_SWTRIG1 0x01U
2963 #define DAC_SWTRIGR_SWTRIG2 0x02U
2965 /***************** Bit definition for DAC_DHR12R1 register ******************/
2966 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
2968 /***************** Bit definition for DAC_DHR12L1 register ******************/
2969 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
2971 /****************** Bit definition for DAC_DHR8R1 register ******************/
2972 #define DAC_DHR8R1_DACC1DHR 0xFFU
2974 /***************** Bit definition for DAC_DHR12R2 register ******************/
2975 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
2977 /***************** Bit definition for DAC_DHR12L2 register ******************/
2978 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
2980 /****************** Bit definition for DAC_DHR8R2 register ******************/
2981 #define DAC_DHR8R2_DACC2DHR 0xFFU
2983 /***************** Bit definition for DAC_DHR12RD register ******************/
2984 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
2985 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
2987 /***************** Bit definition for DAC_DHR12LD register ******************/
2988 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
2989 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
2991 /****************** Bit definition for DAC_DHR8RD register ******************/
2992 #define DAC_DHR8RD_DACC1DHR 0x00FFU
2993 #define DAC_DHR8RD_DACC2DHR 0xFF00U
2995 /******************* Bit definition for DAC_DOR1 register *******************/
2996 #define DAC_DOR1_DACC1DOR 0x0FFFU
2998 /******************* Bit definition for DAC_DOR2 register *******************/
2999 #define DAC_DOR2_DACC2DOR 0x0FFFU
3001 /******************** Bit definition for DAC_SR register ********************/
3002 #define DAC_SR_DMAUDR1 0x00002000U
3003 #define DAC_SR_DMAUDR2 0x20000000U
3005 /******************************************************************************/
3006 /* */
3007 /* Debug MCU */
3008 /* */
3009 /******************************************************************************/
3010 
3011 /******************************************************************************/
3012 /* */
3013 /* DMA Controller */
3014 /* */
3015 /******************************************************************************/
3016 /******************** Bits definition for DMA_SxCR register *****************/
3017 #define DMA_SxCR_CHSEL 0x0E000000U
3018 #define DMA_SxCR_CHSEL_0 0x02000000U
3019 #define DMA_SxCR_CHSEL_1 0x04000000U
3020 #define DMA_SxCR_CHSEL_2 0x08000000U
3021 #define DMA_SxCR_MBURST 0x01800000U
3022 #define DMA_SxCR_MBURST_0 0x00800000U
3023 #define DMA_SxCR_MBURST_1 0x01000000U
3024 #define DMA_SxCR_PBURST 0x00600000U
3025 #define DMA_SxCR_PBURST_0 0x00200000U
3026 #define DMA_SxCR_PBURST_1 0x00400000U
3027 #define DMA_SxCR_CT 0x00080000U
3028 #define DMA_SxCR_DBM 0x00040000U
3029 #define DMA_SxCR_PL 0x00030000U
3030 #define DMA_SxCR_PL_0 0x00010000U
3031 #define DMA_SxCR_PL_1 0x00020000U
3032 #define DMA_SxCR_PINCOS 0x00008000U
3033 #define DMA_SxCR_MSIZE 0x00006000U
3034 #define DMA_SxCR_MSIZE_0 0x00002000U
3035 #define DMA_SxCR_MSIZE_1 0x00004000U
3036 #define DMA_SxCR_PSIZE 0x00001800U
3037 #define DMA_SxCR_PSIZE_0 0x00000800U
3038 #define DMA_SxCR_PSIZE_1 0x00001000U
3039 #define DMA_SxCR_MINC 0x00000400U
3040 #define DMA_SxCR_PINC 0x00000200U
3041 #define DMA_SxCR_CIRC 0x00000100U
3042 #define DMA_SxCR_DIR 0x000000C0U
3043 #define DMA_SxCR_DIR_0 0x00000040U
3044 #define DMA_SxCR_DIR_1 0x00000080U
3045 #define DMA_SxCR_PFCTRL 0x00000020U
3046 #define DMA_SxCR_TCIE 0x00000010U
3047 #define DMA_SxCR_HTIE 0x00000008U
3048 #define DMA_SxCR_TEIE 0x00000004U
3049 #define DMA_SxCR_DMEIE 0x00000002U
3050 #define DMA_SxCR_EN 0x00000001U
3051 
3052 /* Legacy defines */
3053 #define DMA_SxCR_ACK 0x00100000U
3054 
3055 /******************** Bits definition for DMA_SxCNDTR register **************/
3056 #define DMA_SxNDT 0x0000FFFFU
3057 #define DMA_SxNDT_0 0x00000001U
3058 #define DMA_SxNDT_1 0x00000002U
3059 #define DMA_SxNDT_2 0x00000004U
3060 #define DMA_SxNDT_3 0x00000008U
3061 #define DMA_SxNDT_4 0x00000010U
3062 #define DMA_SxNDT_5 0x00000020U
3063 #define DMA_SxNDT_6 0x00000040U
3064 #define DMA_SxNDT_7 0x00000080U
3065 #define DMA_SxNDT_8 0x00000100U
3066 #define DMA_SxNDT_9 0x00000200U
3067 #define DMA_SxNDT_10 0x00000400U
3068 #define DMA_SxNDT_11 0x00000800U
3069 #define DMA_SxNDT_12 0x00001000U
3070 #define DMA_SxNDT_13 0x00002000U
3071 #define DMA_SxNDT_14 0x00004000U
3072 #define DMA_SxNDT_15 0x00008000U
3073 
3074 /******************** Bits definition for DMA_SxFCR register ****************/
3075 #define DMA_SxFCR_FEIE 0x00000080U
3076 #define DMA_SxFCR_FS 0x00000038U
3077 #define DMA_SxFCR_FS_0 0x00000008U
3078 #define DMA_SxFCR_FS_1 0x00000010U
3079 #define DMA_SxFCR_FS_2 0x00000020U
3080 #define DMA_SxFCR_DMDIS 0x00000004U
3081 #define DMA_SxFCR_FTH 0x00000003U
3082 #define DMA_SxFCR_FTH_0 0x00000001U
3083 #define DMA_SxFCR_FTH_1 0x00000002U
3084 
3085 /******************** Bits definition for DMA_LISR register *****************/
3086 #define DMA_LISR_TCIF3 0x08000000U
3087 #define DMA_LISR_HTIF3 0x04000000U
3088 #define DMA_LISR_TEIF3 0x02000000U
3089 #define DMA_LISR_DMEIF3 0x01000000U
3090 #define DMA_LISR_FEIF3 0x00400000U
3091 #define DMA_LISR_TCIF2 0x00200000U
3092 #define DMA_LISR_HTIF2 0x00100000U
3093 #define DMA_LISR_TEIF2 0x00080000U
3094 #define DMA_LISR_DMEIF2 0x00040000U
3095 #define DMA_LISR_FEIF2 0x00010000U
3096 #define DMA_LISR_TCIF1 0x00000800U
3097 #define DMA_LISR_HTIF1 0x00000400U
3098 #define DMA_LISR_TEIF1 0x00000200U
3099 #define DMA_LISR_DMEIF1 0x00000100U
3100 #define DMA_LISR_FEIF1 0x00000040U
3101 #define DMA_LISR_TCIF0 0x00000020U
3102 #define DMA_LISR_HTIF0 0x00000010U
3103 #define DMA_LISR_TEIF0 0x00000008U
3104 #define DMA_LISR_DMEIF0 0x00000004U
3105 #define DMA_LISR_FEIF0 0x00000001U
3106 
3107 /******************** Bits definition for DMA_HISR register *****************/
3108 #define DMA_HISR_TCIF7 0x08000000U
3109 #define DMA_HISR_HTIF7 0x04000000U
3110 #define DMA_HISR_TEIF7 0x02000000U
3111 #define DMA_HISR_DMEIF7 0x01000000U
3112 #define DMA_HISR_FEIF7 0x00400000U
3113 #define DMA_HISR_TCIF6 0x00200000U
3114 #define DMA_HISR_HTIF6 0x00100000U
3115 #define DMA_HISR_TEIF6 0x00080000U
3116 #define DMA_HISR_DMEIF6 0x00040000U
3117 #define DMA_HISR_FEIF6 0x00010000U
3118 #define DMA_HISR_TCIF5 0x00000800U
3119 #define DMA_HISR_HTIF5 0x00000400U
3120 #define DMA_HISR_TEIF5 0x00000200U
3121 #define DMA_HISR_DMEIF5 0x00000100U
3122 #define DMA_HISR_FEIF5 0x00000040U
3123 #define DMA_HISR_TCIF4 0x00000020U
3124 #define DMA_HISR_HTIF4 0x00000010U
3125 #define DMA_HISR_TEIF4 0x00000008U
3126 #define DMA_HISR_DMEIF4 0x00000004U
3127 #define DMA_HISR_FEIF4 0x00000001U
3128 
3129 /******************** Bits definition for DMA_LIFCR register ****************/
3130 #define DMA_LIFCR_CTCIF3 0x08000000U
3131 #define DMA_LIFCR_CHTIF3 0x04000000U
3132 #define DMA_LIFCR_CTEIF3 0x02000000U
3133 #define DMA_LIFCR_CDMEIF3 0x01000000U
3134 #define DMA_LIFCR_CFEIF3 0x00400000U
3135 #define DMA_LIFCR_CTCIF2 0x00200000U
3136 #define DMA_LIFCR_CHTIF2 0x00100000U
3137 #define DMA_LIFCR_CTEIF2 0x00080000U
3138 #define DMA_LIFCR_CDMEIF2 0x00040000U
3139 #define DMA_LIFCR_CFEIF2 0x00010000U
3140 #define DMA_LIFCR_CTCIF1 0x00000800U
3141 #define DMA_LIFCR_CHTIF1 0x00000400U
3142 #define DMA_LIFCR_CTEIF1 0x00000200U
3143 #define DMA_LIFCR_CDMEIF1 0x00000100U
3144 #define DMA_LIFCR_CFEIF1 0x00000040U
3145 #define DMA_LIFCR_CTCIF0 0x00000020U
3146 #define DMA_LIFCR_CHTIF0 0x00000010U
3147 #define DMA_LIFCR_CTEIF0 0x00000008U
3148 #define DMA_LIFCR_CDMEIF0 0x00000004U
3149 #define DMA_LIFCR_CFEIF0 0x00000001U
3150 
3151 /******************** Bits definition for DMA_HIFCR register ****************/
3152 #define DMA_HIFCR_CTCIF7 0x08000000U
3153 #define DMA_HIFCR_CHTIF7 0x04000000U
3154 #define DMA_HIFCR_CTEIF7 0x02000000U
3155 #define DMA_HIFCR_CDMEIF7 0x01000000U
3156 #define DMA_HIFCR_CFEIF7 0x00400000U
3157 #define DMA_HIFCR_CTCIF6 0x00200000U
3158 #define DMA_HIFCR_CHTIF6 0x00100000U
3159 #define DMA_HIFCR_CTEIF6 0x00080000U
3160 #define DMA_HIFCR_CDMEIF6 0x00040000U
3161 #define DMA_HIFCR_CFEIF6 0x00010000U
3162 #define DMA_HIFCR_CTCIF5 0x00000800U
3163 #define DMA_HIFCR_CHTIF5 0x00000400U
3164 #define DMA_HIFCR_CTEIF5 0x00000200U
3165 #define DMA_HIFCR_CDMEIF5 0x00000100U
3166 #define DMA_HIFCR_CFEIF5 0x00000040U
3167 #define DMA_HIFCR_CTCIF4 0x00000020U
3168 #define DMA_HIFCR_CHTIF4 0x00000010U
3169 #define DMA_HIFCR_CTEIF4 0x00000008U
3170 #define DMA_HIFCR_CDMEIF4 0x00000004U
3171 #define DMA_HIFCR_CFEIF4 0x00000001U
3172 
3173 
3174 /******************************************************************************/
3175 /* */
3176 /* External Interrupt/Event Controller */
3177 /* */
3178 /******************************************************************************/
3179 /******************* Bit definition for EXTI_IMR register *******************/
3180 #define EXTI_IMR_MR0 0x00000001U
3181 #define EXTI_IMR_MR1 0x00000002U
3182 #define EXTI_IMR_MR2 0x00000004U
3183 #define EXTI_IMR_MR3 0x00000008U
3184 #define EXTI_IMR_MR4 0x00000010U
3185 #define EXTI_IMR_MR5 0x00000020U
3186 #define EXTI_IMR_MR6 0x00000040U
3187 #define EXTI_IMR_MR7 0x00000080U
3188 #define EXTI_IMR_MR8 0x00000100U
3189 #define EXTI_IMR_MR9 0x00000200U
3190 #define EXTI_IMR_MR10 0x00000400U
3191 #define EXTI_IMR_MR11 0x00000800U
3192 #define EXTI_IMR_MR12 0x00001000U
3193 #define EXTI_IMR_MR13 0x00002000U
3194 #define EXTI_IMR_MR14 0x00004000U
3195 #define EXTI_IMR_MR15 0x00008000U
3196 #define EXTI_IMR_MR16 0x00010000U
3197 #define EXTI_IMR_MR17 0x00020000U
3198 #define EXTI_IMR_MR18 0x00040000U
3199 #define EXTI_IMR_MR19 0x00080000U
3200 #define EXTI_IMR_MR20 0x00100000U
3201 #define EXTI_IMR_MR21 0x00200000U
3202 #define EXTI_IMR_MR22 0x00400000U
3204 /******************* Bit definition for EXTI_EMR register *******************/
3205 #define EXTI_EMR_MR0 0x00000001U
3206 #define EXTI_EMR_MR1 0x00000002U
3207 #define EXTI_EMR_MR2 0x00000004U
3208 #define EXTI_EMR_MR3 0x00000008U
3209 #define EXTI_EMR_MR4 0x00000010U
3210 #define EXTI_EMR_MR5 0x00000020U
3211 #define EXTI_EMR_MR6 0x00000040U
3212 #define EXTI_EMR_MR7 0x00000080U
3213 #define EXTI_EMR_MR8 0x00000100U
3214 #define EXTI_EMR_MR9 0x00000200U
3215 #define EXTI_EMR_MR10 0x00000400U
3216 #define EXTI_EMR_MR11 0x00000800U
3217 #define EXTI_EMR_MR12 0x00001000U
3218 #define EXTI_EMR_MR13 0x00002000U
3219 #define EXTI_EMR_MR14 0x00004000U
3220 #define EXTI_EMR_MR15 0x00008000U
3221 #define EXTI_EMR_MR16 0x00010000U
3222 #define EXTI_EMR_MR17 0x00020000U
3223 #define EXTI_EMR_MR18 0x00040000U
3224 #define EXTI_EMR_MR19 0x00080000U
3225 #define EXTI_EMR_MR20 0x00100000U
3226 #define EXTI_EMR_MR21 0x00200000U
3227 #define EXTI_EMR_MR22 0x00400000U
3229 /****************** Bit definition for EXTI_RTSR register *******************/
3230 #define EXTI_RTSR_TR0 0x00000001U
3231 #define EXTI_RTSR_TR1 0x00000002U
3232 #define EXTI_RTSR_TR2 0x00000004U
3233 #define EXTI_RTSR_TR3 0x00000008U
3234 #define EXTI_RTSR_TR4 0x00000010U
3235 #define EXTI_RTSR_TR5 0x00000020U
3236 #define EXTI_RTSR_TR6 0x00000040U
3237 #define EXTI_RTSR_TR7 0x00000080U
3238 #define EXTI_RTSR_TR8 0x00000100U
3239 #define EXTI_RTSR_TR9 0x00000200U
3240 #define EXTI_RTSR_TR10 0x00000400U
3241 #define EXTI_RTSR_TR11 0x00000800U
3242 #define EXTI_RTSR_TR12 0x00001000U
3243 #define EXTI_RTSR_TR13 0x00002000U
3244 #define EXTI_RTSR_TR14 0x00004000U
3245 #define EXTI_RTSR_TR15 0x00008000U
3246 #define EXTI_RTSR_TR16 0x00010000U
3247 #define EXTI_RTSR_TR17 0x00020000U
3248 #define EXTI_RTSR_TR18 0x00040000U
3249 #define EXTI_RTSR_TR19 0x00080000U
3250 #define EXTI_RTSR_TR20 0x00100000U
3251 #define EXTI_RTSR_TR21 0x00200000U
3252 #define EXTI_RTSR_TR22 0x00400000U
3254 /****************** Bit definition for EXTI_FTSR register *******************/
3255 #define EXTI_FTSR_TR0 0x00000001U
3256 #define EXTI_FTSR_TR1 0x00000002U
3257 #define EXTI_FTSR_TR2 0x00000004U
3258 #define EXTI_FTSR_TR3 0x00000008U
3259 #define EXTI_FTSR_TR4 0x00000010U
3260 #define EXTI_FTSR_TR5 0x00000020U
3261 #define EXTI_FTSR_TR6 0x00000040U
3262 #define EXTI_FTSR_TR7 0x00000080U
3263 #define EXTI_FTSR_TR8 0x00000100U
3264 #define EXTI_FTSR_TR9 0x00000200U
3265 #define EXTI_FTSR_TR10 0x00000400U
3266 #define EXTI_FTSR_TR11 0x00000800U
3267 #define EXTI_FTSR_TR12 0x00001000U
3268 #define EXTI_FTSR_TR13 0x00002000U
3269 #define EXTI_FTSR_TR14 0x00004000U
3270 #define EXTI_FTSR_TR15 0x00008000U
3271 #define EXTI_FTSR_TR16 0x00010000U
3272 #define EXTI_FTSR_TR17 0x00020000U
3273 #define EXTI_FTSR_TR18 0x00040000U
3274 #define EXTI_FTSR_TR19 0x00080000U
3275 #define EXTI_FTSR_TR20 0x00100000U
3276 #define EXTI_FTSR_TR21 0x00200000U
3277 #define EXTI_FTSR_TR22 0x00400000U
3279 /****************** Bit definition for EXTI_SWIER register ******************/
3280 #define EXTI_SWIER_SWIER0 0x00000001U
3281 #define EXTI_SWIER_SWIER1 0x00000002U
3282 #define EXTI_SWIER_SWIER2 0x00000004U
3283 #define EXTI_SWIER_SWIER3 0x00000008U
3284 #define EXTI_SWIER_SWIER4 0x00000010U
3285 #define EXTI_SWIER_SWIER5 0x00000020U
3286 #define EXTI_SWIER_SWIER6 0x00000040U
3287 #define EXTI_SWIER_SWIER7 0x00000080U
3288 #define EXTI_SWIER_SWIER8 0x00000100U
3289 #define EXTI_SWIER_SWIER9 0x00000200U
3290 #define EXTI_SWIER_SWIER10 0x00000400U
3291 #define EXTI_SWIER_SWIER11 0x00000800U
3292 #define EXTI_SWIER_SWIER12 0x00001000U
3293 #define EXTI_SWIER_SWIER13 0x00002000U
3294 #define EXTI_SWIER_SWIER14 0x00004000U
3295 #define EXTI_SWIER_SWIER15 0x00008000U
3296 #define EXTI_SWIER_SWIER16 0x00010000U
3297 #define EXTI_SWIER_SWIER17 0x00020000U
3298 #define EXTI_SWIER_SWIER18 0x00040000U
3299 #define EXTI_SWIER_SWIER19 0x00080000U
3300 #define EXTI_SWIER_SWIER20 0x00100000U
3301 #define EXTI_SWIER_SWIER21 0x00200000U
3302 #define EXTI_SWIER_SWIER22 0x00400000U
3304 /******************* Bit definition for EXTI_PR register ********************/
3305 #define EXTI_PR_PR0 0x00000001U
3306 #define EXTI_PR_PR1 0x00000002U
3307 #define EXTI_PR_PR2 0x00000004U
3308 #define EXTI_PR_PR3 0x00000008U
3309 #define EXTI_PR_PR4 0x00000010U
3310 #define EXTI_PR_PR5 0x00000020U
3311 #define EXTI_PR_PR6 0x00000040U
3312 #define EXTI_PR_PR7 0x00000080U
3313 #define EXTI_PR_PR8 0x00000100U
3314 #define EXTI_PR_PR9 0x00000200U
3315 #define EXTI_PR_PR10 0x00000400U
3316 #define EXTI_PR_PR11 0x00000800U
3317 #define EXTI_PR_PR12 0x00001000U
3318 #define EXTI_PR_PR13 0x00002000U
3319 #define EXTI_PR_PR14 0x00004000U
3320 #define EXTI_PR_PR15 0x00008000U
3321 #define EXTI_PR_PR16 0x00010000U
3322 #define EXTI_PR_PR17 0x00020000U
3323 #define EXTI_PR_PR18 0x00040000U
3324 #define EXTI_PR_PR19 0x00080000U
3325 #define EXTI_PR_PR20 0x00100000U
3326 #define EXTI_PR_PR21 0x00200000U
3327 #define EXTI_PR_PR22 0x00400000U
3329 /******************************************************************************/
3330 /* */
3331 /* FLASH */
3332 /* */
3333 /******************************************************************************/
3334 /******************* Bits definition for FLASH_ACR register *****************/
3335 #define FLASH_ACR_LATENCY 0x0000000FU
3336 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3337 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3338 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3339 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3340 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3341 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3342 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3343 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3344 
3345 #define FLASH_ACR_PRFTEN 0x00000100U
3346 #define FLASH_ACR_ICEN 0x00000200U
3347 #define FLASH_ACR_DCEN 0x00000400U
3348 #define FLASH_ACR_ICRST 0x00000800U
3349 #define FLASH_ACR_DCRST 0x00001000U
3350 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3351 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3352 
3353 /******************* Bits definition for FLASH_SR register ******************/
3354 #define FLASH_SR_EOP 0x00000001U
3355 #define FLASH_SR_SOP 0x00000002U
3356 #define FLASH_SR_WRPERR 0x00000010U
3357 #define FLASH_SR_PGAERR 0x00000020U
3358 #define FLASH_SR_PGPERR 0x00000040U
3359 #define FLASH_SR_PGSERR 0x00000080U
3360 #define FLASH_SR_BSY 0x00010000U
3361 
3362 /******************* Bits definition for FLASH_CR register ******************/
3363 #define FLASH_CR_PG 0x00000001U
3364 #define FLASH_CR_SER 0x00000002U
3365 #define FLASH_CR_MER 0x00000004U
3366 #define FLASH_CR_SNB 0x000000F8U
3367 #define FLASH_CR_SNB_0 0x00000008U
3368 #define FLASH_CR_SNB_1 0x00000010U
3369 #define FLASH_CR_SNB_2 0x00000020U
3370 #define FLASH_CR_SNB_3 0x00000040U
3371 #define FLASH_CR_SNB_4 0x00000080U
3372 #define FLASH_CR_PSIZE 0x00000300U
3373 #define FLASH_CR_PSIZE_0 0x00000100U
3374 #define FLASH_CR_PSIZE_1 0x00000200U
3375 #define FLASH_CR_STRT 0x00010000U
3376 #define FLASH_CR_EOPIE 0x01000000U
3377 #define FLASH_CR_LOCK 0x80000000U
3378 
3379 /******************* Bits definition for FLASH_OPTCR register ***************/
3380 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3381 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3382 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3383 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3384 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3385 
3386 #define FLASH_OPTCR_WDG_SW 0x00000020U
3387 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3388 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3389 #define FLASH_OPTCR_RDP 0x0000FF00U
3390 #define FLASH_OPTCR_RDP_0 0x00000100U
3391 #define FLASH_OPTCR_RDP_1 0x00000200U
3392 #define FLASH_OPTCR_RDP_2 0x00000400U
3393 #define FLASH_OPTCR_RDP_3 0x00000800U
3394 #define FLASH_OPTCR_RDP_4 0x00001000U
3395 #define FLASH_OPTCR_RDP_5 0x00002000U
3396 #define FLASH_OPTCR_RDP_6 0x00004000U
3397 #define FLASH_OPTCR_RDP_7 0x00008000U
3398 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3399 #define FLASH_OPTCR_nWRP_0 0x00010000U
3400 #define FLASH_OPTCR_nWRP_1 0x00020000U
3401 #define FLASH_OPTCR_nWRP_2 0x00040000U
3402 #define FLASH_OPTCR_nWRP_3 0x00080000U
3403 #define FLASH_OPTCR_nWRP_4 0x00100000U
3404 #define FLASH_OPTCR_nWRP_5 0x00200000U
3405 #define FLASH_OPTCR_nWRP_6 0x00400000U
3406 #define FLASH_OPTCR_nWRP_7 0x00800000U
3407 #define FLASH_OPTCR_nWRP_8 0x01000000U
3408 #define FLASH_OPTCR_nWRP_9 0x02000000U
3409 #define FLASH_OPTCR_nWRP_10 0x04000000U
3410 #define FLASH_OPTCR_nWRP_11 0x08000000U
3411 
3412 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3413 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3414 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3415 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3416 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3417 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3418 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3419 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3420 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3421 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3422 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3423 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3424 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3425 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3426 
3427 /******************************************************************************/
3428 /* */
3429 /* Flexible Static Memory Controller */
3430 /* */
3431 /******************************************************************************/
3432 /****************** Bit definition for FSMC_BCR1 register *******************/
3433 #define FSMC_BCR1_MBKEN 0x00000001U
3434 #define FSMC_BCR1_MUXEN 0x00000002U
3436 #define FSMC_BCR1_MTYP 0x0000000CU
3437 #define FSMC_BCR1_MTYP_0 0x00000004U
3438 #define FSMC_BCR1_MTYP_1 0x00000008U
3440 #define FSMC_BCR1_MWID 0x00000030U
3441 #define FSMC_BCR1_MWID_0 0x00000010U
3442 #define FSMC_BCR1_MWID_1 0x00000020U
3444 #define FSMC_BCR1_FACCEN 0x00000040U
3445 #define FSMC_BCR1_BURSTEN 0x00000100U
3446 #define FSMC_BCR1_WAITPOL 0x00000200U
3447 #define FSMC_BCR1_WRAPMOD 0x00000400U
3448 #define FSMC_BCR1_WAITCFG 0x00000800U
3449 #define FSMC_BCR1_WREN 0x00001000U
3450 #define FSMC_BCR1_WAITEN 0x00002000U
3451 #define FSMC_BCR1_EXTMOD 0x00004000U
3452 #define FSMC_BCR1_ASYNCWAIT 0x00008000U
3453 #define FSMC_BCR1_CPSIZE 0x00070000U
3454 #define FSMC_BCR1_CPSIZE_0 0x00010000U
3455 #define FSMC_BCR1_CPSIZE_1 0x00020000U
3456 #define FSMC_BCR1_CPSIZE_2 0x00040000U
3457 #define FSMC_BCR1_CBURSTRW 0x00080000U
3459 /****************** Bit definition for FSMC_BCR2 register *******************/
3460 #define FSMC_BCR2_MBKEN 0x00000001U
3461 #define FSMC_BCR2_MUXEN 0x00000002U
3463 #define FSMC_BCR2_MTYP 0x0000000CU
3464 #define FSMC_BCR2_MTYP_0 0x00000004U
3465 #define FSMC_BCR2_MTYP_1 0x00000008U
3467 #define FSMC_BCR2_MWID 0x00000030U
3468 #define FSMC_BCR2_MWID_0 0x00000010U
3469 #define FSMC_BCR2_MWID_1 0x00000020U
3471 #define FSMC_BCR2_FACCEN 0x00000040U
3472 #define FSMC_BCR2_BURSTEN 0x00000100U
3473 #define FSMC_BCR2_WAITPOL 0x00000200U
3474 #define FSMC_BCR2_WRAPMOD 0x00000400U
3475 #define FSMC_BCR2_WAITCFG 0x00000800U
3476 #define FSMC_BCR2_WREN 0x00001000U
3477 #define FSMC_BCR2_WAITEN 0x00002000U
3478 #define FSMC_BCR2_EXTMOD 0x00004000U
3479 #define FSMC_BCR2_ASYNCWAIT 0x00008000U
3480 #define FSMC_BCR2_CPSIZE 0x00070000U
3481 #define FSMC_BCR2_CPSIZE_0 0x00010000U
3482 #define FSMC_BCR2_CPSIZE_1 0x00020000U
3483 #define FSMC_BCR2_CPSIZE_2 0x00040000U
3484 #define FSMC_BCR2_CBURSTRW 0x00080000U
3486 /****************** Bit definition for FSMC_BCR3 register *******************/
3487 #define FSMC_BCR3_MBKEN 0x00000001U
3488 #define FSMC_BCR3_MUXEN 0x00000002U
3490 #define FSMC_BCR3_MTYP 0x0000000CU
3491 #define FSMC_BCR3_MTYP_0 0x00000004U
3492 #define FSMC_BCR3_MTYP_1 0x00000008U
3494 #define FSMC_BCR3_MWID 0x00000030U
3495 #define FSMC_BCR3_MWID_0 0x00000010U
3496 #define FSMC_BCR3_MWID_1 0x00000020U
3498 #define FSMC_BCR3_FACCEN 0x00000040U
3499 #define FSMC_BCR3_BURSTEN 0x00000100U
3500 #define FSMC_BCR3_WAITPOL 0x00000200U
3501 #define FSMC_BCR3_WRAPMOD 0x00000400U
3502 #define FSMC_BCR3_WAITCFG 0x00000800U
3503 #define FSMC_BCR3_WREN 0x00001000U
3504 #define FSMC_BCR3_WAITEN 0x00002000U
3505 #define FSMC_BCR3_EXTMOD 0x00004000U
3506 #define FSMC_BCR3_ASYNCWAIT 0x00008000U
3507 #define FSMC_BCR3_CPSIZE 0x00070000U
3508 #define FSMC_BCR3_CPSIZE_0 0x00010000U
3509 #define FSMC_BCR3_CPSIZE_1 0x00020000U
3510 #define FSMC_BCR3_CPSIZE_2 0x00040000U
3511 #define FSMC_BCR3_CBURSTRW 0x00080000U
3513 /****************** Bit definition for FSMC_BCR4 register *******************/
3514 #define FSMC_BCR4_MBKEN 0x00000001U
3515 #define FSMC_BCR4_MUXEN 0x00000002U
3517 #define FSMC_BCR4_MTYP 0x0000000CU
3518 #define FSMC_BCR4_MTYP_0 0x00000004U
3519 #define FSMC_BCR4_MTYP_1 0x00000008U
3521 #define FSMC_BCR4_MWID 0x00000030U
3522 #define FSMC_BCR4_MWID_0 0x00000010U
3523 #define FSMC_BCR4_MWID_1 0x00000020U
3525 #define FSMC_BCR4_FACCEN 0x00000040U
3526 #define FSMC_BCR4_BURSTEN 0x00000100U
3527 #define FSMC_BCR4_WAITPOL 0x00000200U
3528 #define FSMC_BCR4_WRAPMOD 0x00000400U
3529 #define FSMC_BCR4_WAITCFG 0x00000800U
3530 #define FSMC_BCR4_WREN 0x00001000U
3531 #define FSMC_BCR4_WAITEN 0x00002000U
3532 #define FSMC_BCR4_EXTMOD 0x00004000U
3533 #define FSMC_BCR4_ASYNCWAIT 0x00008000U
3534 #define FSMC_BCR4_CPSIZE 0x00070000U
3535 #define FSMC_BCR4_CPSIZE_0 0x00010000U
3536 #define FSMC_BCR4_CPSIZE_1 0x00020000U
3537 #define FSMC_BCR4_CPSIZE_2 0x00040000U
3538 #define FSMC_BCR4_CBURSTRW 0x00080000U
3540 /****************** Bit definition for FSMC_BTR1 register ******************/
3541 #define FSMC_BTR1_ADDSET 0x0000000FU
3542 #define FSMC_BTR1_ADDSET_0 0x00000001U
3543 #define FSMC_BTR1_ADDSET_1 0x00000002U
3544 #define FSMC_BTR1_ADDSET_2 0x00000004U
3545 #define FSMC_BTR1_ADDSET_3 0x00000008U
3547 #define FSMC_BTR1_ADDHLD 0x000000F0U
3548 #define FSMC_BTR1_ADDHLD_0 0x00000010U
3549 #define FSMC_BTR1_ADDHLD_1 0x00000020U
3550 #define FSMC_BTR1_ADDHLD_2 0x00000040U
3551 #define FSMC_BTR1_ADDHLD_3 0x00000080U
3553 #define FSMC_BTR1_DATAST 0x0000FF00U
3554 #define FSMC_BTR1_DATAST_0 0x00000100U
3555 #define FSMC_BTR1_DATAST_1 0x00000200U
3556 #define FSMC_BTR1_DATAST_2 0x00000400U
3557 #define FSMC_BTR1_DATAST_3 0x00000800U
3558 #define FSMC_BTR1_DATAST_4 0x00001000U
3559 #define FSMC_BTR1_DATAST_5 0x00002000U
3560 #define FSMC_BTR1_DATAST_6 0x00004000U
3561 #define FSMC_BTR1_DATAST_7 0x00008000U
3563 #define FSMC_BTR1_BUSTURN 0x000F0000U
3564 #define FSMC_BTR1_BUSTURN_0 0x00010000U
3565 #define FSMC_BTR1_BUSTURN_1 0x00020000U
3566 #define FSMC_BTR1_BUSTURN_2 0x00040000U
3567 #define FSMC_BTR1_BUSTURN_3 0x00080000U
3569 #define FSMC_BTR1_CLKDIV 0x00F00000U
3570 #define FSMC_BTR1_CLKDIV_0 0x00100000U
3571 #define FSMC_BTR1_CLKDIV_1 0x00200000U
3572 #define FSMC_BTR1_CLKDIV_2 0x00400000U
3573 #define FSMC_BTR1_CLKDIV_3 0x00800000U
3575 #define FSMC_BTR1_DATLAT 0x0F000000U
3576 #define FSMC_BTR1_DATLAT_0 0x01000000U
3577 #define FSMC_BTR1_DATLAT_1 0x02000000U
3578 #define FSMC_BTR1_DATLAT_2 0x04000000U
3579 #define FSMC_BTR1_DATLAT_3 0x08000000U
3581 #define FSMC_BTR1_ACCMOD 0x30000000U
3582 #define FSMC_BTR1_ACCMOD_0 0x10000000U
3583 #define FSMC_BTR1_ACCMOD_1 0x20000000U
3585 /****************** Bit definition for FSMC_BTR2 register *******************/
3586 #define FSMC_BTR2_ADDSET 0x0000000FU
3587 #define FSMC_BTR2_ADDSET_0 0x00000001U
3588 #define FSMC_BTR2_ADDSET_1 0x00000002U
3589 #define FSMC_BTR2_ADDSET_2 0x00000004U
3590 #define FSMC_BTR2_ADDSET_3 0x00000008U
3592 #define FSMC_BTR2_ADDHLD 0x000000F0U
3593 #define FSMC_BTR2_ADDHLD_0 0x00000010U
3594 #define FSMC_BTR2_ADDHLD_1 0x00000020U
3595 #define FSMC_BTR2_ADDHLD_2 0x00000040U
3596 #define FSMC_BTR2_ADDHLD_3 0x00000080U
3598 #define FSMC_BTR2_DATAST 0x0000FF00U
3599 #define FSMC_BTR2_DATAST_0 0x00000100U
3600 #define FSMC_BTR2_DATAST_1 0x00000200U
3601 #define FSMC_BTR2_DATAST_2 0x00000400U
3602 #define FSMC_BTR2_DATAST_3 0x00000800U
3603 #define FSMC_BTR2_DATAST_4 0x00001000U
3604 #define FSMC_BTR2_DATAST_5 0x00002000U
3605 #define FSMC_BTR2_DATAST_6 0x00004000U
3606 #define FSMC_BTR2_DATAST_7 0x00008000U
3608 #define FSMC_BTR2_BUSTURN 0x000F0000U
3609 #define FSMC_BTR2_BUSTURN_0 0x00010000U
3610 #define FSMC_BTR2_BUSTURN_1 0x00020000U
3611 #define FSMC_BTR2_BUSTURN_2 0x00040000U
3612 #define FSMC_BTR2_BUSTURN_3 0x00080000U
3614 #define FSMC_BTR2_CLKDIV 0x00F00000U
3615 #define FSMC_BTR2_CLKDIV_0 0x00100000U
3616 #define FSMC_BTR2_CLKDIV_1 0x00200000U
3617 #define FSMC_BTR2_CLKDIV_2 0x00400000U
3618 #define FSMC_BTR2_CLKDIV_3 0x00800000U
3620 #define FSMC_BTR2_DATLAT 0x0F000000U
3621 #define FSMC_BTR2_DATLAT_0 0x01000000U
3622 #define FSMC_BTR2_DATLAT_1 0x02000000U
3623 #define FSMC_BTR2_DATLAT_2 0x04000000U
3624 #define FSMC_BTR2_DATLAT_3 0x08000000U
3626 #define FSMC_BTR2_ACCMOD 0x30000000U
3627 #define FSMC_BTR2_ACCMOD_0 0x10000000U
3628 #define FSMC_BTR2_ACCMOD_1 0x20000000U
3630 /******************* Bit definition for FSMC_BTR3 register *******************/
3631 #define FSMC_BTR3_ADDSET 0x0000000FU
3632 #define FSMC_BTR3_ADDSET_0 0x00000001U
3633 #define FSMC_BTR3_ADDSET_1 0x00000002U
3634 #define FSMC_BTR3_ADDSET_2 0x00000004U
3635 #define FSMC_BTR3_ADDSET_3 0x00000008U
3637 #define FSMC_BTR3_ADDHLD 0x000000F0U
3638 #define FSMC_BTR3_ADDHLD_0 0x00000010U
3639 #define FSMC_BTR3_ADDHLD_1 0x00000020U
3640 #define FSMC_BTR3_ADDHLD_2 0x00000040U
3641 #define FSMC_BTR3_ADDHLD_3 0x00000080U
3643 #define FSMC_BTR3_DATAST 0x0000FF00U
3644 #define FSMC_BTR3_DATAST_0 0x00000100U
3645 #define FSMC_BTR3_DATAST_1 0x00000200U
3646 #define FSMC_BTR3_DATAST_2 0x00000400U
3647 #define FSMC_BTR3_DATAST_3 0x00000800U
3648 #define FSMC_BTR3_DATAST_4 0x00001000U
3649 #define FSMC_BTR3_DATAST_5 0x00002000U
3650 #define FSMC_BTR3_DATAST_6 0x00004000U
3651 #define FSMC_BTR3_DATAST_7 0x00008000U
3653 #define FSMC_BTR3_BUSTURN 0x000F0000U
3654 #define FSMC_BTR3_BUSTURN_0 0x00010000U
3655 #define FSMC_BTR3_BUSTURN_1 0x00020000U
3656 #define FSMC_BTR3_BUSTURN_2 0x00040000U
3657 #define FSMC_BTR3_BUSTURN_3 0x00080000U
3659 #define FSMC_BTR3_CLKDIV 0x00F00000U
3660 #define FSMC_BTR3_CLKDIV_0 0x00100000U
3661 #define FSMC_BTR3_CLKDIV_1 0x00200000U
3662 #define FSMC_BTR3_CLKDIV_2 0x00400000U
3663 #define FSMC_BTR3_CLKDIV_3 0x00800000U
3665 #define FSMC_BTR3_DATLAT 0x0F000000U
3666 #define FSMC_BTR3_DATLAT_0 0x01000000U
3667 #define FSMC_BTR3_DATLAT_1 0x02000000U
3668 #define FSMC_BTR3_DATLAT_2 0x04000000U
3669 #define FSMC_BTR3_DATLAT_3 0x08000000U
3671 #define FSMC_BTR3_ACCMOD 0x30000000U
3672 #define FSMC_BTR3_ACCMOD_0 0x10000000U
3673 #define FSMC_BTR3_ACCMOD_1 0x20000000U
3675 /****************** Bit definition for FSMC_BTR4 register *******************/
3676 #define FSMC_BTR4_ADDSET 0x0000000FU
3677 #define FSMC_BTR4_ADDSET_0 0x00000001U
3678 #define FSMC_BTR4_ADDSET_1 0x00000002U
3679 #define FSMC_BTR4_ADDSET_2 0x00000004U
3680 #define FSMC_BTR4_ADDSET_3 0x00000008U
3682 #define FSMC_BTR4_ADDHLD 0x000000F0U
3683 #define FSMC_BTR4_ADDHLD_0 0x00000010U
3684 #define FSMC_BTR4_ADDHLD_1 0x00000020U
3685 #define FSMC_BTR4_ADDHLD_2 0x00000040U
3686 #define FSMC_BTR4_ADDHLD_3 0x00000080U
3688 #define FSMC_BTR4_DATAST 0x0000FF00U
3689 #define FSMC_BTR4_DATAST_0 0x00000100U
3690 #define FSMC_BTR4_DATAST_1 0x00000200U
3691 #define FSMC_BTR4_DATAST_2 0x00000400U
3692 #define FSMC_BTR4_DATAST_3 0x00000800U
3693 #define FSMC_BTR4_DATAST_4 0x00001000U
3694 #define FSMC_BTR4_DATAST_5 0x00002000U
3695 #define FSMC_BTR4_DATAST_6 0x00004000U
3696 #define FSMC_BTR4_DATAST_7 0x00008000U
3698 #define FSMC_BTR4_BUSTURN 0x000F0000U
3699 #define FSMC_BTR4_BUSTURN_0 0x00010000U
3700 #define FSMC_BTR4_BUSTURN_1 0x00020000U
3701 #define FSMC_BTR4_BUSTURN_2 0x00040000U
3702 #define FSMC_BTR4_BUSTURN_3 0x00080000U
3704 #define FSMC_BTR4_CLKDIV 0x00F00000U
3705 #define FSMC_BTR4_CLKDIV_0 0x00100000U
3706 #define FSMC_BTR4_CLKDIV_1 0x00200000U
3707 #define FSMC_BTR4_CLKDIV_2 0x00400000U
3708 #define FSMC_BTR4_CLKDIV_3 0x00800000U
3710 #define FSMC_BTR4_DATLAT 0x0F000000U
3711 #define FSMC_BTR4_DATLAT_0 0x01000000U
3712 #define FSMC_BTR4_DATLAT_1 0x02000000U
3713 #define FSMC_BTR4_DATLAT_2 0x04000000U
3714 #define FSMC_BTR4_DATLAT_3 0x08000000U
3716 #define FSMC_BTR4_ACCMOD 0x30000000U
3717 #define FSMC_BTR4_ACCMOD_0 0x10000000U
3718 #define FSMC_BTR4_ACCMOD_1 0x20000000U
3720 /****************** Bit definition for FSMC_BWTR1 register ******************/
3721 #define FSMC_BWTR1_ADDSET 0x0000000FU
3722 #define FSMC_BWTR1_ADDSET_0 0x00000001U
3723 #define FSMC_BWTR1_ADDSET_1 0x00000002U
3724 #define FSMC_BWTR1_ADDSET_2 0x00000004U
3725 #define FSMC_BWTR1_ADDSET_3 0x00000008U
3727 #define FSMC_BWTR1_ADDHLD 0x000000F0U
3728 #define FSMC_BWTR1_ADDHLD_0 0x00000010U
3729 #define FSMC_BWTR1_ADDHLD_1 0x00000020U
3730 #define FSMC_BWTR1_ADDHLD_2 0x00000040U
3731 #define FSMC_BWTR1_ADDHLD_3 0x00000080U
3733 #define FSMC_BWTR1_DATAST 0x0000FF00U
3734 #define FSMC_BWTR1_DATAST_0 0x00000100U
3735 #define FSMC_BWTR1_DATAST_1 0x00000200U
3736 #define FSMC_BWTR1_DATAST_2 0x00000400U
3737 #define FSMC_BWTR1_DATAST_3 0x00000800U
3738 #define FSMC_BWTR1_DATAST_4 0x00001000U
3739 #define FSMC_BWTR1_DATAST_5 0x00002000U
3740 #define FSMC_BWTR1_DATAST_6 0x00004000U
3741 #define FSMC_BWTR1_DATAST_7 0x00008000U
3743 #define FSMC_BWTR1_BUSTURN 0x000F0000U
3744 #define FSMC_BWTR1_BUSTURN_0 0x00010000U
3745 #define FSMC_BWTR1_BUSTURN_1 0x00020000U
3746 #define FSMC_BWTR1_BUSTURN_2 0x00040000U
3747 #define FSMC_BWTR1_BUSTURN_3 0x00080000U
3749 #define FSMC_BWTR1_ACCMOD 0x30000000U
3750 #define FSMC_BWTR1_ACCMOD_0 0x10000000U
3751 #define FSMC_BWTR1_ACCMOD_1 0x20000000U
3753 /****************** Bit definition for FSMC_BWTR2 register ******************/
3754 #define FSMC_BWTR2_ADDSET 0x0000000FU
3755 #define FSMC_BWTR2_ADDSET_0 0x00000001U
3756 #define FSMC_BWTR2_ADDSET_1 0x00000002U
3757 #define FSMC_BWTR2_ADDSET_2 0x00000004U
3758 #define FSMC_BWTR2_ADDSET_3 0x00000008U
3760 #define FSMC_BWTR2_ADDHLD 0x000000F0U
3761 #define FSMC_BWTR2_ADDHLD_0 0x00000010U
3762 #define FSMC_BWTR2_ADDHLD_1 0x00000020U
3763 #define FSMC_BWTR2_ADDHLD_2 0x00000040U
3764 #define FSMC_BWTR2_ADDHLD_3 0x00000080U
3766 #define FSMC_BWTR2_DATAST 0x0000FF00U
3767 #define FSMC_BWTR2_DATAST_0 0x00000100U
3768 #define FSMC_BWTR2_DATAST_1 0x00000200U
3769 #define FSMC_BWTR2_DATAST_2 0x00000400U
3770 #define FSMC_BWTR2_DATAST_3 0x00000800U
3771 #define FSMC_BWTR2_DATAST_4 0x00001000U
3772 #define FSMC_BWTR2_DATAST_5 0x00002000U
3773 #define FSMC_BWTR2_DATAST_6 0x00004000U
3774 #define FSMC_BWTR2_DATAST_7 0x00008000U
3776 #define FSMC_BWTR2_BUSTURN 0x000F0000U
3777 #define FSMC_BWTR2_BUSTURN_0 0x00010000U
3778 #define FSMC_BWTR2_BUSTURN_1 0x00020000U
3779 #define FSMC_BWTR2_BUSTURN_2 0x00040000U
3780 #define FSMC_BWTR2_BUSTURN_3 0x00080000U
3782 #define FSMC_BWTR2_ACCMOD 0x30000000U
3783 #define FSMC_BWTR2_ACCMOD_0 0x10000000U
3784 #define FSMC_BWTR2_ACCMOD_1 0x20000000U
3786 /****************** Bit definition for FSMC_BWTR3 register ******************/
3787 #define FSMC_BWTR3_ADDSET 0x0000000FU
3788 #define FSMC_BWTR3_ADDSET_0 0x00000001U
3789 #define FSMC_BWTR3_ADDSET_1 0x00000002U
3790 #define FSMC_BWTR3_ADDSET_2 0x00000004U
3791 #define FSMC_BWTR3_ADDSET_3 0x00000008U
3793 #define FSMC_BWTR3_ADDHLD 0x000000F0U
3794 #define FSMC_BWTR3_ADDHLD_0 0x00000010U
3795 #define FSMC_BWTR3_ADDHLD_1 0x00000020U
3796 #define FSMC_BWTR3_ADDHLD_2 0x00000040U
3797 #define FSMC_BWTR3_ADDHLD_3 0x00000080U
3799 #define FSMC_BWTR3_DATAST 0x0000FF00U
3800 #define FSMC_BWTR3_DATAST_0 0x00000100U
3801 #define FSMC_BWTR3_DATAST_1 0x00000200U
3802 #define FSMC_BWTR3_DATAST_2 0x00000400U
3803 #define FSMC_BWTR3_DATAST_3 0x00000800U
3804 #define FSMC_BWTR3_DATAST_4 0x00001000U
3805 #define FSMC_BWTR3_DATAST_5 0x00002000U
3806 #define FSMC_BWTR3_DATAST_6 0x00004000U
3807 #define FSMC_BWTR3_DATAST_7 0x00008000U
3809 #define FSMC_BWTR3_BUSTURN 0x000F0000U
3810 #define FSMC_BWTR3_BUSTURN_0 0x00010000U
3811 #define FSMC_BWTR3_BUSTURN_1 0x00020000U
3812 #define FSMC_BWTR3_BUSTURN_2 0x00040000U
3813 #define FSMC_BWTR3_BUSTURN_3 0x00080000U
3815 #define FSMC_BWTR3_ACCMOD 0x30000000U
3816 #define FSMC_BWTR3_ACCMOD_0 0x10000000U
3817 #define FSMC_BWTR3_ACCMOD_1 0x20000000U
3819 /****************** Bit definition for FSMC_BWTR4 register ******************/
3820 #define FSMC_BWTR4_ADDSET 0x0000000FU
3821 #define FSMC_BWTR4_ADDSET_0 0x00000001U
3822 #define FSMC_BWTR4_ADDSET_1 0x00000002U
3823 #define FSMC_BWTR4_ADDSET_2 0x00000004U
3824 #define FSMC_BWTR4_ADDSET_3 0x00000008U
3826 #define FSMC_BWTR4_ADDHLD 0x000000F0U
3827 #define FSMC_BWTR4_ADDHLD_0 0x00000010U
3828 #define FSMC_BWTR4_ADDHLD_1 0x00000020U
3829 #define FSMC_BWTR4_ADDHLD_2 0x00000040U
3830 #define FSMC_BWTR4_ADDHLD_3 0x00000080U
3832 #define FSMC_BWTR4_DATAST 0x0000FF00U
3833 #define FSMC_BWTR4_DATAST_0 0x00000100U
3834 #define FSMC_BWTR4_DATAST_1 0x00000200U
3835 #define FSMC_BWTR4_DATAST_2 0x00000400U
3836 #define FSMC_BWTR4_DATAST_3 0x00000800U
3837 #define FSMC_BWTR4_DATAST_4 0x00001000U
3838 #define FSMC_BWTR4_DATAST_5 0x00002000U
3839 #define FSMC_BWTR4_DATAST_6 0x00004000U
3840 #define FSMC_BWTR4_DATAST_7 0x00008000U
3842 #define FSMC_BWTR4_BUSTURN 0x000F0000U
3843 #define FSMC_BWTR4_BUSTURN_0 0x00010000U
3844 #define FSMC_BWTR4_BUSTURN_1 0x00020000U
3845 #define FSMC_BWTR4_BUSTURN_2 0x00040000U
3846 #define FSMC_BWTR4_BUSTURN_3 0x00080000U
3848 #define FSMC_BWTR4_ACCMOD 0x30000000U
3849 #define FSMC_BWTR4_ACCMOD_0 0x10000000U
3850 #define FSMC_BWTR4_ACCMOD_1 0x20000000U
3852 /****************** Bit definition for FSMC_PCR2 register *******************/
3853 #define FSMC_PCR2_PWAITEN 0x00000002U
3854 #define FSMC_PCR2_PBKEN 0x00000004U
3855 #define FSMC_PCR2_PTYP 0x00000008U
3857 #define FSMC_PCR2_PWID 0x00000030U
3858 #define FSMC_PCR2_PWID_0 0x00000010U
3859 #define FSMC_PCR2_PWID_1 0x00000020U
3861 #define FSMC_PCR2_ECCEN 0x00000040U
3863 #define FSMC_PCR2_TCLR 0x00001E00U
3864 #define FSMC_PCR2_TCLR_0 0x00000200U
3865 #define FSMC_PCR2_TCLR_1 0x00000400U
3866 #define FSMC_PCR2_TCLR_2 0x00000800U
3867 #define FSMC_PCR2_TCLR_3 0x00001000U
3869 #define FSMC_PCR2_TAR 0x0001E000U
3870 #define FSMC_PCR2_TAR_0 0x00002000U
3871 #define FSMC_PCR2_TAR_1 0x00004000U
3872 #define FSMC_PCR2_TAR_2 0x00008000U
3873 #define FSMC_PCR2_TAR_3 0x00010000U
3875 #define FSMC_PCR2_ECCPS 0x000E0000U
3876 #define FSMC_PCR2_ECCPS_0 0x00020000U
3877 #define FSMC_PCR2_ECCPS_1 0x00040000U
3878 #define FSMC_PCR2_ECCPS_2 0x00080000U
3880 /****************** Bit definition for FSMC_PCR3 register *******************/
3881 #define FSMC_PCR3_PWAITEN 0x00000002U
3882 #define FSMC_PCR3_PBKEN 0x00000004U
3883 #define FSMC_PCR3_PTYP 0x00000008U
3885 #define FSMC_PCR3_PWID 0x00000030U
3886 #define FSMC_PCR3_PWID_0 0x00000010U
3887 #define FSMC_PCR3_PWID_1 0x00000020U
3889 #define FSMC_PCR3_ECCEN 0x00000040U
3891 #define FSMC_PCR3_TCLR 0x00001E00U
3892 #define FSMC_PCR3_TCLR_0 0x00000200U
3893 #define FSMC_PCR3_TCLR_1 0x00000400U
3894 #define FSMC_PCR3_TCLR_2 0x00000800U
3895 #define FSMC_PCR3_TCLR_3 0x00001000U
3897 #define FSMC_PCR3_TAR 0x0001E000U
3898 #define FSMC_PCR3_TAR_0 0x00002000U
3899 #define FSMC_PCR3_TAR_1 0x00004000U
3900 #define FSMC_PCR3_TAR_2 0x00008000U
3901 #define FSMC_PCR3_TAR_3 0x00010000U
3903 #define FSMC_PCR3_ECCPS 0x000E0000U
3904 #define FSMC_PCR3_ECCPS_0 0x00020000U
3905 #define FSMC_PCR3_ECCPS_1 0x00040000U
3906 #define FSMC_PCR3_ECCPS_2 0x00080000U
3908 /****************** Bit definition for FSMC_PCR4 register *******************/
3909 #define FSMC_PCR4_PWAITEN 0x00000002U
3910 #define FSMC_PCR4_PBKEN 0x00000004U
3911 #define FSMC_PCR4_PTYP 0x00000008U
3913 #define FSMC_PCR4_PWID 0x00000030U
3914 #define FSMC_PCR4_PWID_0 0x00000010U
3915 #define FSMC_PCR4_PWID_1 0x00000020U
3917 #define FSMC_PCR4_ECCEN 0x00000040U
3919 #define FSMC_PCR4_TCLR 0x00001E00U
3920 #define FSMC_PCR4_TCLR_0 0x00000200U
3921 #define FSMC_PCR4_TCLR_1 0x00000400U
3922 #define FSMC_PCR4_TCLR_2 0x00000800U
3923 #define FSMC_PCR4_TCLR_3 0x00001000U
3925 #define FSMC_PCR4_TAR 0x0001E000U
3926 #define FSMC_PCR4_TAR_0 0x00002000U
3927 #define FSMC_PCR4_TAR_1 0x00004000U
3928 #define FSMC_PCR4_TAR_2 0x00008000U
3929 #define FSMC_PCR4_TAR_3 0x00010000U
3931 #define FSMC_PCR4_ECCPS 0x000E0000U
3932 #define FSMC_PCR4_ECCPS_0 0x00020000U
3933 #define FSMC_PCR4_ECCPS_1 0x00040000U
3934 #define FSMC_PCR4_ECCPS_2 0x00080000U
3936 /******************* Bit definition for FSMC_SR2 register *******************/
3937 #define FSMC_SR2_IRS 0x01U
3938 #define FSMC_SR2_ILS 0x02U
3939 #define FSMC_SR2_IFS 0x04U
3940 #define FSMC_SR2_IREN 0x08U
3941 #define FSMC_SR2_ILEN 0x10U
3942 #define FSMC_SR2_IFEN 0x20U
3943 #define FSMC_SR2_FEMPT 0x40U
3945 /******************* Bit definition for FSMC_SR3 register *******************/
3946 #define FSMC_SR3_IRS 0x01U
3947 #define FSMC_SR3_ILS 0x02U
3948 #define FSMC_SR3_IFS 0x04U
3949 #define FSMC_SR3_IREN 0x08U
3950 #define FSMC_SR3_ILEN 0x10U
3951 #define FSMC_SR3_IFEN 0x20U
3952 #define FSMC_SR3_FEMPT 0x40U
3954 /******************* Bit definition for FSMC_SR4 register *******************/
3955 #define FSMC_SR4_IRS 0x01U
3956 #define FSMC_SR4_ILS 0x02U
3957 #define FSMC_SR4_IFS 0x04U
3958 #define FSMC_SR4_IREN 0x08U
3959 #define FSMC_SR4_ILEN 0x10U
3960 #define FSMC_SR4_IFEN 0x20U
3961 #define FSMC_SR4_FEMPT 0x40U
3963 /****************** Bit definition for FSMC_PMEM2 register ******************/
3964 #define FSMC_PMEM2_MEMSET2 0x000000FFU
3965 #define FSMC_PMEM2_MEMSET2_0 0x00000001U
3966 #define FSMC_PMEM2_MEMSET2_1 0x00000002U
3967 #define FSMC_PMEM2_MEMSET2_2 0x00000004U
3968 #define FSMC_PMEM2_MEMSET2_3 0x00000008U
3969 #define FSMC_PMEM2_MEMSET2_4 0x00000010U
3970 #define FSMC_PMEM2_MEMSET2_5 0x00000020U
3971 #define FSMC_PMEM2_MEMSET2_6 0x00000040U
3972 #define FSMC_PMEM2_MEMSET2_7 0x00000080U
3974 #define FSMC_PMEM2_MEMWAIT2 0x0000FF00U
3975 #define FSMC_PMEM2_MEMWAIT2_0 0x00000100U
3976 #define FSMC_PMEM2_MEMWAIT2_1 0x00000200U
3977 #define FSMC_PMEM2_MEMWAIT2_2 0x00000400U
3978 #define FSMC_PMEM2_MEMWAIT2_3 0x00000800U
3979 #define FSMC_PMEM2_MEMWAIT2_4 0x00001000U
3980 #define FSMC_PMEM2_MEMWAIT2_5 0x00002000U
3981 #define FSMC_PMEM2_MEMWAIT2_6 0x00004000U
3982 #define FSMC_PMEM2_MEMWAIT2_7 0x00008000U
3984 #define FSMC_PMEM2_MEMHOLD2 0x00FF0000U
3985 #define FSMC_PMEM2_MEMHOLD2_0 0x00010000U
3986 #define FSMC_PMEM2_MEMHOLD2_1 0x00020000U
3987 #define FSMC_PMEM2_MEMHOLD2_2 0x00040000U
3988 #define FSMC_PMEM2_MEMHOLD2_3 0x00080000U
3989 #define FSMC_PMEM2_MEMHOLD2_4 0x00100000U
3990 #define FSMC_PMEM2_MEMHOLD2_5 0x00200000U
3991 #define FSMC_PMEM2_MEMHOLD2_6 0x00400000U
3992 #define FSMC_PMEM2_MEMHOLD2_7 0x00800000U
3994 #define FSMC_PMEM2_MEMHIZ2 0xFF000000U
3995 #define FSMC_PMEM2_MEMHIZ2_0 0x01000000U
3996 #define FSMC_PMEM2_MEMHIZ2_1 0x02000000U
3997 #define FSMC_PMEM2_MEMHIZ2_2 0x04000000U
3998 #define FSMC_PMEM2_MEMHIZ2_3 0x08000000U
3999 #define FSMC_PMEM2_MEMHIZ2_4 0x10000000U
4000 #define FSMC_PMEM2_MEMHIZ2_5 0x20000000U
4001 #define FSMC_PMEM2_MEMHIZ2_6 0x40000000U
4002 #define FSMC_PMEM2_MEMHIZ2_7 0x80000000U
4004 /****************** Bit definition for FSMC_PMEM3 register ******************/
4005 #define FSMC_PMEM3_MEMSET3 0x000000FFU
4006 #define FSMC_PMEM3_MEMSET3_0 0x00000001U
4007 #define FSMC_PMEM3_MEMSET3_1 0x00000002U
4008 #define FSMC_PMEM3_MEMSET3_2 0x00000004U
4009 #define FSMC_PMEM3_MEMSET3_3 0x00000008U
4010 #define FSMC_PMEM3_MEMSET3_4 0x00000010U
4011 #define FSMC_PMEM3_MEMSET3_5 0x00000020U
4012 #define FSMC_PMEM3_MEMSET3_6 0x00000040U
4013 #define FSMC_PMEM3_MEMSET3_7 0x00000080U
4015 #define FSMC_PMEM3_MEMWAIT3 0x0000FF00U
4016 #define FSMC_PMEM3_MEMWAIT3_0 0x00000100U
4017 #define FSMC_PMEM3_MEMWAIT3_1 0x00000200U
4018 #define FSMC_PMEM3_MEMWAIT3_2 0x00000400U
4019 #define FSMC_PMEM3_MEMWAIT3_3 0x00000800U
4020 #define FSMC_PMEM3_MEMWAIT3_4 0x00001000U
4021 #define FSMC_PMEM3_MEMWAIT3_5 0x00002000U
4022 #define FSMC_PMEM3_MEMWAIT3_6 0x00004000U
4023 #define FSMC_PMEM3_MEMWAIT3_7 0x00008000U
4025 #define FSMC_PMEM3_MEMHOLD3 0x00FF0000U
4026 #define FSMC_PMEM3_MEMHOLD3_0 0x00010000U
4027 #define FSMC_PMEM3_MEMHOLD3_1 0x00020000U
4028 #define FSMC_PMEM3_MEMHOLD3_2 0x00040000U
4029 #define FSMC_PMEM3_MEMHOLD3_3 0x00080000U
4030 #define FSMC_PMEM3_MEMHOLD3_4 0x00100000U
4031 #define FSMC_PMEM3_MEMHOLD3_5 0x00200000U
4032 #define FSMC_PMEM3_MEMHOLD3_6 0x00400000U
4033 #define FSMC_PMEM3_MEMHOLD3_7 0x00800000U
4035 #define FSMC_PMEM3_MEMHIZ3 0xFF000000U
4036 #define FSMC_PMEM3_MEMHIZ3_0 0x01000000U
4037 #define FSMC_PMEM3_MEMHIZ3_1 0x02000000U
4038 #define FSMC_PMEM3_MEMHIZ3_2 0x04000000U
4039 #define FSMC_PMEM3_MEMHIZ3_3 0x08000000U
4040 #define FSMC_PMEM3_MEMHIZ3_4 0x10000000U
4041 #define FSMC_PMEM3_MEMHIZ3_5 0x20000000U
4042 #define FSMC_PMEM3_MEMHIZ3_6 0x40000000U
4043 #define FSMC_PMEM3_MEMHIZ3_7 0x80000000U
4045 /****************** Bit definition for FSMC_PMEM4 register ******************/
4046 #define FSMC_PMEM4_MEMSET4 0x000000FFU
4047 #define FSMC_PMEM4_MEMSET4_0 0x00000001U
4048 #define FSMC_PMEM4_MEMSET4_1 0x00000002U
4049 #define FSMC_PMEM4_MEMSET4_2 0x00000004U
4050 #define FSMC_PMEM4_MEMSET4_3 0x00000008U
4051 #define FSMC_PMEM4_MEMSET4_4 0x00000010U
4052 #define FSMC_PMEM4_MEMSET4_5 0x00000020U
4053 #define FSMC_PMEM4_MEMSET4_6 0x00000040U
4054 #define FSMC_PMEM4_MEMSET4_7 0x00000080U
4056 #define FSMC_PMEM4_MEMWAIT4 0x0000FF00U
4057 #define FSMC_PMEM4_MEMWAIT4_0 0x00000100U
4058 #define FSMC_PMEM4_MEMWAIT4_1 0x00000200U
4059 #define FSMC_PMEM4_MEMWAIT4_2 0x00000400U
4060 #define FSMC_PMEM4_MEMWAIT4_3 0x00000800U
4061 #define FSMC_PMEM4_MEMWAIT4_4 0x00001000U
4062 #define FSMC_PMEM4_MEMWAIT4_5 0x00002000U
4063 #define FSMC_PMEM4_MEMWAIT4_6 0x00004000U
4064 #define FSMC_PMEM4_MEMWAIT4_7 0x00008000U
4066 #define FSMC_PMEM4_MEMHOLD4 0x00FF0000U
4067 #define FSMC_PMEM4_MEMHOLD4_0 0x00010000U
4068 #define FSMC_PMEM4_MEMHOLD4_1 0x00020000U
4069 #define FSMC_PMEM4_MEMHOLD4_2 0x00040000U
4070 #define FSMC_PMEM4_MEMHOLD4_3 0x00080000U
4071 #define FSMC_PMEM4_MEMHOLD4_4 0x00100000U
4072 #define FSMC_PMEM4_MEMHOLD4_5 0x00200000U
4073 #define FSMC_PMEM4_MEMHOLD4_6 0x00400000U
4074 #define FSMC_PMEM4_MEMHOLD4_7 0x00800000U
4076 #define FSMC_PMEM4_MEMHIZ4 0xFF000000U
4077 #define FSMC_PMEM4_MEMHIZ4_0 0x01000000U
4078 #define FSMC_PMEM4_MEMHIZ4_1 0x02000000U
4079 #define FSMC_PMEM4_MEMHIZ4_2 0x04000000U
4080 #define FSMC_PMEM4_MEMHIZ4_3 0x08000000U
4081 #define FSMC_PMEM4_MEMHIZ4_4 0x10000000U
4082 #define FSMC_PMEM4_MEMHIZ4_5 0x20000000U
4083 #define FSMC_PMEM4_MEMHIZ4_6 0x40000000U
4084 #define FSMC_PMEM4_MEMHIZ4_7 0x80000000U
4086 /****************** Bit definition for FSMC_PATT2 register ******************/
4087 #define FSMC_PATT2_ATTSET2 0x000000FFU
4088 #define FSMC_PATT2_ATTSET2_0 0x00000001U
4089 #define FSMC_PATT2_ATTSET2_1 0x00000002U
4090 #define FSMC_PATT2_ATTSET2_2 0x00000004U
4091 #define FSMC_PATT2_ATTSET2_3 0x00000008U
4092 #define FSMC_PATT2_ATTSET2_4 0x00000010U
4093 #define FSMC_PATT2_ATTSET2_5 0x00000020U
4094 #define FSMC_PATT2_ATTSET2_6 0x00000040U
4095 #define FSMC_PATT2_ATTSET2_7 0x00000080U
4097 #define FSMC_PATT2_ATTWAIT2 0x0000FF00U
4098 #define FSMC_PATT2_ATTWAIT2_0 0x00000100U
4099 #define FSMC_PATT2_ATTWAIT2_1 0x00000200U
4100 #define FSMC_PATT2_ATTWAIT2_2 0x00000400U
4101 #define FSMC_PATT2_ATTWAIT2_3 0x00000800U
4102 #define FSMC_PATT2_ATTWAIT2_4 0x00001000U
4103 #define FSMC_PATT2_ATTWAIT2_5 0x00002000U
4104 #define FSMC_PATT2_ATTWAIT2_6 0x00004000U
4105 #define FSMC_PATT2_ATTWAIT2_7 0x00008000U
4107 #define FSMC_PATT2_ATTHOLD2 0x00FF0000U
4108 #define FSMC_PATT2_ATTHOLD2_0 0x00010000U
4109 #define FSMC_PATT2_ATTHOLD2_1 0x00020000U
4110 #define FSMC_PATT2_ATTHOLD2_2 0x00040000U
4111 #define FSMC_PATT2_ATTHOLD2_3 0x00080000U
4112 #define FSMC_PATT2_ATTHOLD2_4 0x00100000U
4113 #define FSMC_PATT2_ATTHOLD2_5 0x00200000U
4114 #define FSMC_PATT2_ATTHOLD2_6 0x00400000U
4115 #define FSMC_PATT2_ATTHOLD2_7 0x00800000U
4117 #define FSMC_PATT2_ATTHIZ2 0xFF000000U
4118 #define FSMC_PATT2_ATTHIZ2_0 0x01000000U
4119 #define FSMC_PATT2_ATTHIZ2_1 0x02000000U
4120 #define FSMC_PATT2_ATTHIZ2_2 0x04000000U
4121 #define FSMC_PATT2_ATTHIZ2_3 0x08000000U
4122 #define FSMC_PATT2_ATTHIZ2_4 0x10000000U
4123 #define FSMC_PATT2_ATTHIZ2_5 0x20000000U
4124 #define FSMC_PATT2_ATTHIZ2_6 0x40000000U
4125 #define FSMC_PATT2_ATTHIZ2_7 0x80000000U
4127 /****************** Bit definition for FSMC_PATT3 register ******************/
4128 #define FSMC_PATT3_ATTSET3 0x000000FFU
4129 #define FSMC_PATT3_ATTSET3_0 0x00000001U
4130 #define FSMC_PATT3_ATTSET3_1 0x00000002U
4131 #define FSMC_PATT3_ATTSET3_2 0x00000004U
4132 #define FSMC_PATT3_ATTSET3_3 0x00000008U
4133 #define FSMC_PATT3_ATTSET3_4 0x00000010U
4134 #define FSMC_PATT3_ATTSET3_5 0x00000020U
4135 #define FSMC_PATT3_ATTSET3_6 0x00000040U
4136 #define FSMC_PATT3_ATTSET3_7 0x00000080U
4138 #define FSMC_PATT3_ATTWAIT3 0x0000FF00U
4139 #define FSMC_PATT3_ATTWAIT3_0 0x00000100U
4140 #define FSMC_PATT3_ATTWAIT3_1 0x00000200U
4141 #define FSMC_PATT3_ATTWAIT3_2 0x00000400U
4142 #define FSMC_PATT3_ATTWAIT3_3 0x00000800U
4143 #define FSMC_PATT3_ATTWAIT3_4 0x00001000U
4144 #define FSMC_PATT3_ATTWAIT3_5 0x00002000U
4145 #define FSMC_PATT3_ATTWAIT3_6 0x00004000U
4146 #define FSMC_PATT3_ATTWAIT3_7 0x00008000U
4148 #define FSMC_PATT3_ATTHOLD3 0x00FF0000U
4149 #define FSMC_PATT3_ATTHOLD3_0 0x00010000U
4150 #define FSMC_PATT3_ATTHOLD3_1 0x00020000U
4151 #define FSMC_PATT3_ATTHOLD3_2 0x00040000U
4152 #define FSMC_PATT3_ATTHOLD3_3 0x00080000U
4153 #define FSMC_PATT3_ATTHOLD3_4 0x00100000U
4154 #define FSMC_PATT3_ATTHOLD3_5 0x00200000U
4155 #define FSMC_PATT3_ATTHOLD3_6 0x00400000U
4156 #define FSMC_PATT3_ATTHOLD3_7 0x00800000U
4158 #define FSMC_PATT3_ATTHIZ3 0xFF000000U
4159 #define FSMC_PATT3_ATTHIZ3_0 0x01000000U
4160 #define FSMC_PATT3_ATTHIZ3_1 0x02000000U
4161 #define FSMC_PATT3_ATTHIZ3_2 0x04000000U
4162 #define FSMC_PATT3_ATTHIZ3_3 0x08000000U
4163 #define FSMC_PATT3_ATTHIZ3_4 0x10000000U
4164 #define FSMC_PATT3_ATTHIZ3_5 0x20000000U
4165 #define FSMC_PATT3_ATTHIZ3_6 0x40000000U
4166 #define FSMC_PATT3_ATTHIZ3_7 0x80000000U
4168 /****************** Bit definition for FSMC_PATT4 register ******************/
4169 #define FSMC_PATT4_ATTSET4 0x000000FFU
4170 #define FSMC_PATT4_ATTSET4_0 0x00000001U
4171 #define FSMC_PATT4_ATTSET4_1 0x00000002U
4172 #define FSMC_PATT4_ATTSET4_2 0x00000004U
4173 #define FSMC_PATT4_ATTSET4_3 0x00000008U
4174 #define FSMC_PATT4_ATTSET4_4 0x00000010U
4175 #define FSMC_PATT4_ATTSET4_5 0x00000020U
4176 #define FSMC_PATT4_ATTSET4_6 0x00000040U
4177 #define FSMC_PATT4_ATTSET4_7 0x00000080U
4179 #define FSMC_PATT4_ATTWAIT4 0x0000FF00U
4180 #define FSMC_PATT4_ATTWAIT4_0 0x00000100U
4181 #define FSMC_PATT4_ATTWAIT4_1 0x00000200U
4182 #define FSMC_PATT4_ATTWAIT4_2 0x00000400U
4183 #define FSMC_PATT4_ATTWAIT4_3 0x00000800U
4184 #define FSMC_PATT4_ATTWAIT4_4 0x00001000U
4185 #define FSMC_PATT4_ATTWAIT4_5 0x00002000U
4186 #define FSMC_PATT4_ATTWAIT4_6 0x00004000U
4187 #define FSMC_PATT4_ATTWAIT4_7 0x00008000U
4189 #define FSMC_PATT4_ATTHOLD4 0x00FF0000U
4190 #define FSMC_PATT4_ATTHOLD4_0 0x00010000U
4191 #define FSMC_PATT4_ATTHOLD4_1 0x00020000U
4192 #define FSMC_PATT4_ATTHOLD4_2 0x00040000U
4193 #define FSMC_PATT4_ATTHOLD4_3 0x00080000U
4194 #define FSMC_PATT4_ATTHOLD4_4 0x00100000U
4195 #define FSMC_PATT4_ATTHOLD4_5 0x00200000U
4196 #define FSMC_PATT4_ATTHOLD4_6 0x00400000U
4197 #define FSMC_PATT4_ATTHOLD4_7 0x00800000U
4199 #define FSMC_PATT4_ATTHIZ4 0xFF000000U
4200 #define FSMC_PATT4_ATTHIZ4_0 0x01000000U
4201 #define FSMC_PATT4_ATTHIZ4_1 0x02000000U
4202 #define FSMC_PATT4_ATTHIZ4_2 0x04000000U
4203 #define FSMC_PATT4_ATTHIZ4_3 0x08000000U
4204 #define FSMC_PATT4_ATTHIZ4_4 0x10000000U
4205 #define FSMC_PATT4_ATTHIZ4_5 0x20000000U
4206 #define FSMC_PATT4_ATTHIZ4_6 0x40000000U
4207 #define FSMC_PATT4_ATTHIZ4_7 0x80000000U
4209 /****************** Bit definition for FSMC_PIO4 register *******************/
4210 #define FSMC_PIO4_IOSET4 0x000000FFU
4211 #define FSMC_PIO4_IOSET4_0 0x00000001U
4212 #define FSMC_PIO4_IOSET4_1 0x00000002U
4213 #define FSMC_PIO4_IOSET4_2 0x00000004U
4214 #define FSMC_PIO4_IOSET4_3 0x00000008U
4215 #define FSMC_PIO4_IOSET4_4 0x00000010U
4216 #define FSMC_PIO4_IOSET4_5 0x00000020U
4217 #define FSMC_PIO4_IOSET4_6 0x00000040U
4218 #define FSMC_PIO4_IOSET4_7 0x00000080U
4220 #define FSMC_PIO4_IOWAIT4 0x0000FF00U
4221 #define FSMC_PIO4_IOWAIT4_0 0x00000100U
4222 #define FSMC_PIO4_IOWAIT4_1 0x00000200U
4223 #define FSMC_PIO4_IOWAIT4_2 0x00000400U
4224 #define FSMC_PIO4_IOWAIT4_3 0x00000800U
4225 #define FSMC_PIO4_IOWAIT4_4 0x00001000U
4226 #define FSMC_PIO4_IOWAIT4_5 0x00002000U
4227 #define FSMC_PIO4_IOWAIT4_6 0x00004000U
4228 #define FSMC_PIO4_IOWAIT4_7 0x00008000U
4230 #define FSMC_PIO4_IOHOLD4 0x00FF0000U
4231 #define FSMC_PIO4_IOHOLD4_0 0x00010000U
4232 #define FSMC_PIO4_IOHOLD4_1 0x00020000U
4233 #define FSMC_PIO4_IOHOLD4_2 0x00040000U
4234 #define FSMC_PIO4_IOHOLD4_3 0x00080000U
4235 #define FSMC_PIO4_IOHOLD4_4 0x00100000U
4236 #define FSMC_PIO4_IOHOLD4_5 0x00200000U
4237 #define FSMC_PIO4_IOHOLD4_6 0x00400000U
4238 #define FSMC_PIO4_IOHOLD4_7 0x00800000U
4240 #define FSMC_PIO4_IOHIZ4 0xFF000000U
4241 #define FSMC_PIO4_IOHIZ4_0 0x01000000U
4242 #define FSMC_PIO4_IOHIZ4_1 0x02000000U
4243 #define FSMC_PIO4_IOHIZ4_2 0x04000000U
4244 #define FSMC_PIO4_IOHIZ4_3 0x08000000U
4245 #define FSMC_PIO4_IOHIZ4_4 0x10000000U
4246 #define FSMC_PIO4_IOHIZ4_5 0x20000000U
4247 #define FSMC_PIO4_IOHIZ4_6 0x40000000U
4248 #define FSMC_PIO4_IOHIZ4_7 0x80000000U
4250 /****************** Bit definition for FSMC_ECCR2 register ******************/
4251 #define FSMC_ECCR2_ECC2 0xFFFFFFFFU
4253 /****************** Bit definition for FSMC_ECCR3 register ******************/
4254 #define FSMC_ECCR3_ECC3 0xFFFFFFFFU
4256 /******************************************************************************/
4257 /* */
4258 /* General Purpose I/O */
4259 /* */
4260 /******************************************************************************/
4261 /****************** Bits definition for GPIO_MODER register *****************/
4262 #define GPIO_MODER_MODER0 0x00000003U
4263 #define GPIO_MODER_MODER0_0 0x00000001U
4264 #define GPIO_MODER_MODER0_1 0x00000002U
4265 
4266 #define GPIO_MODER_MODER1 0x0000000CU
4267 #define GPIO_MODER_MODER1_0 0x00000004U
4268 #define GPIO_MODER_MODER1_1 0x00000008U
4269 
4270 #define GPIO_MODER_MODER2 0x00000030U
4271 #define GPIO_MODER_MODER2_0 0x00000010U
4272 #define GPIO_MODER_MODER2_1 0x00000020U
4273 
4274 #define GPIO_MODER_MODER3 0x000000C0U
4275 #define GPIO_MODER_MODER3_0 0x00000040U
4276 #define GPIO_MODER_MODER3_1 0x00000080U
4277 
4278 #define GPIO_MODER_MODER4 0x00000300U
4279 #define GPIO_MODER_MODER4_0 0x00000100U
4280 #define GPIO_MODER_MODER4_1 0x00000200U
4281 
4282 #define GPIO_MODER_MODER5 0x00000C00U
4283 #define GPIO_MODER_MODER5_0 0x00000400U
4284 #define GPIO_MODER_MODER5_1 0x00000800U
4285 
4286 #define GPIO_MODER_MODER6 0x00003000U
4287 #define GPIO_MODER_MODER6_0 0x00001000U
4288 #define GPIO_MODER_MODER6_1 0x00002000U
4289 
4290 #define GPIO_MODER_MODER7 0x0000C000U
4291 #define GPIO_MODER_MODER7_0 0x00004000U
4292 #define GPIO_MODER_MODER7_1 0x00008000U
4293 
4294 #define GPIO_MODER_MODER8 0x00030000U
4295 #define GPIO_MODER_MODER8_0 0x00010000U
4296 #define GPIO_MODER_MODER8_1 0x00020000U
4297 
4298 #define GPIO_MODER_MODER9 0x000C0000U
4299 #define GPIO_MODER_MODER9_0 0x00040000U
4300 #define GPIO_MODER_MODER9_1 0x00080000U
4301 
4302 #define GPIO_MODER_MODER10 0x00300000U
4303 #define GPIO_MODER_MODER10_0 0x00100000U
4304 #define GPIO_MODER_MODER10_1 0x00200000U
4305 
4306 #define GPIO_MODER_MODER11 0x00C00000U
4307 #define GPIO_MODER_MODER11_0 0x00400000U
4308 #define GPIO_MODER_MODER11_1 0x00800000U
4309 
4310 #define GPIO_MODER_MODER12 0x03000000U
4311 #define GPIO_MODER_MODER12_0 0x01000000U
4312 #define GPIO_MODER_MODER12_1 0x02000000U
4313 
4314 #define GPIO_MODER_MODER13 0x0C000000U
4315 #define GPIO_MODER_MODER13_0 0x04000000U
4316 #define GPIO_MODER_MODER13_1 0x08000000U
4317 
4318 #define GPIO_MODER_MODER14 0x30000000U
4319 #define GPIO_MODER_MODER14_0 0x10000000U
4320 #define GPIO_MODER_MODER14_1 0x20000000U
4321 
4322 #define GPIO_MODER_MODER15 0xC0000000U
4323 #define GPIO_MODER_MODER15_0 0x40000000U
4324 #define GPIO_MODER_MODER15_1 0x80000000U
4325 
4326 /****************** Bits definition for GPIO_OTYPER register ****************/
4327 #define GPIO_OTYPER_OT_0 0x00000001U
4328 #define GPIO_OTYPER_OT_1 0x00000002U
4329 #define GPIO_OTYPER_OT_2 0x00000004U
4330 #define GPIO_OTYPER_OT_3 0x00000008U
4331 #define GPIO_OTYPER_OT_4 0x00000010U
4332 #define GPIO_OTYPER_OT_5 0x00000020U
4333 #define GPIO_OTYPER_OT_6 0x00000040U
4334 #define GPIO_OTYPER_OT_7 0x00000080U
4335 #define GPIO_OTYPER_OT_8 0x00000100U
4336 #define GPIO_OTYPER_OT_9 0x00000200U
4337 #define GPIO_OTYPER_OT_10 0x00000400U
4338 #define GPIO_OTYPER_OT_11 0x00000800U
4339 #define GPIO_OTYPER_OT_12 0x00001000U
4340 #define GPIO_OTYPER_OT_13 0x00002000U
4341 #define GPIO_OTYPER_OT_14 0x00004000U
4342 #define GPIO_OTYPER_OT_15 0x00008000U
4343 
4344 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4345 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4346 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4347 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4348 
4349 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4350 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4351 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4352 
4353 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4354 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4355 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4356 
4357 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4358 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4359 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4360 
4361 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4362 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4363 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4364 
4365 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4366 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4367 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4368 
4369 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4370 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4371 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4372 
4373 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4374 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4375 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4376 
4377 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4378 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4379 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4380 
4381 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4382 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4383 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4384 
4385 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4386 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4387 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4388 
4389 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4390 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4391 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4392 
4393 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4394 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4395 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4396 
4397 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4398 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4399 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4400 
4401 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4402 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4403 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4404 
4405 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4406 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4407 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4408 
4409 /****************** Bits definition for GPIO_PUPDR register *****************/
4410 #define GPIO_PUPDR_PUPDR0 0x00000003U
4411 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4412 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4413 
4414 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4415 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4416 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4417 
4418 #define GPIO_PUPDR_PUPDR2 0x00000030U
4419 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4420 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4421 
4422 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4423 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4424 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4425 
4426 #define GPIO_PUPDR_PUPDR4 0x00000300U
4427 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4428 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4429 
4430 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4431 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4432 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4433 
4434 #define GPIO_PUPDR_PUPDR6 0x00003000U
4435 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4436 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4437 
4438 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4439 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4440 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4441 
4442 #define GPIO_PUPDR_PUPDR8 0x00030000U
4443 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4444 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4445 
4446 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4447 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4448 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4449 
4450 #define GPIO_PUPDR_PUPDR10 0x00300000U
4451 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4452 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4453 
4454 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4455 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4456 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4457 
4458 #define GPIO_PUPDR_PUPDR12 0x03000000U
4459 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4460 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4461 
4462 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4463 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4464 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4465 
4466 #define GPIO_PUPDR_PUPDR14 0x30000000U
4467 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4468 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
4469 
4470 #define GPIO_PUPDR_PUPDR15 0xC0000000U
4471 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
4472 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
4473 
4474 /****************** Bits definition for GPIO_IDR register *******************/
4475 #define GPIO_IDR_IDR_0 0x00000001U
4476 #define GPIO_IDR_IDR_1 0x00000002U
4477 #define GPIO_IDR_IDR_2 0x00000004U
4478 #define GPIO_IDR_IDR_3 0x00000008U
4479 #define GPIO_IDR_IDR_4 0x00000010U
4480 #define GPIO_IDR_IDR_5 0x00000020U
4481 #define GPIO_IDR_IDR_6 0x00000040U
4482 #define GPIO_IDR_IDR_7 0x00000080U
4483 #define GPIO_IDR_IDR_8 0x00000100U
4484 #define GPIO_IDR_IDR_9 0x00000200U
4485 #define GPIO_IDR_IDR_10 0x00000400U
4486 #define GPIO_IDR_IDR_11 0x00000800U
4487 #define GPIO_IDR_IDR_12 0x00001000U
4488 #define GPIO_IDR_IDR_13 0x00002000U
4489 #define GPIO_IDR_IDR_14 0x00004000U
4490 #define GPIO_IDR_IDR_15 0x00008000U
4491 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4492 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4493 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4494 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4495 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4496 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4497 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4498 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4499 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4500 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4501 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4502 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4503 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4504 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4505 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4506 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4507 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4508 
4509 /****************** Bits definition for GPIO_ODR register *******************/
4510 #define GPIO_ODR_ODR_0 0x00000001U
4511 #define GPIO_ODR_ODR_1 0x00000002U
4512 #define GPIO_ODR_ODR_2 0x00000004U
4513 #define GPIO_ODR_ODR_3 0x00000008U
4514 #define GPIO_ODR_ODR_4 0x00000010U
4515 #define GPIO_ODR_ODR_5 0x00000020U
4516 #define GPIO_ODR_ODR_6 0x00000040U
4517 #define GPIO_ODR_ODR_7 0x00000080U
4518 #define GPIO_ODR_ODR_8 0x00000100U
4519 #define GPIO_ODR_ODR_9 0x00000200U
4520 #define GPIO_ODR_ODR_10 0x00000400U
4521 #define GPIO_ODR_ODR_11 0x00000800U
4522 #define GPIO_ODR_ODR_12 0x00001000U
4523 #define GPIO_ODR_ODR_13 0x00002000U
4524 #define GPIO_ODR_ODR_14 0x00004000U
4525 #define GPIO_ODR_ODR_15 0x00008000U
4526 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4527 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4528 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4529 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4530 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4531 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4532 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4533 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4534 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4535 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4536 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4537 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4538 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4539 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4540 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4541 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4542 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4543 
4544 /****************** Bits definition for GPIO_BSRR register ******************/
4545 #define GPIO_BSRR_BS_0 0x00000001U
4546 #define GPIO_BSRR_BS_1 0x00000002U
4547 #define GPIO_BSRR_BS_2 0x00000004U
4548 #define GPIO_BSRR_BS_3 0x00000008U
4549 #define GPIO_BSRR_BS_4 0x00000010U
4550 #define GPIO_BSRR_BS_5 0x00000020U
4551 #define GPIO_BSRR_BS_6 0x00000040U
4552 #define GPIO_BSRR_BS_7 0x00000080U
4553 #define GPIO_BSRR_BS_8 0x00000100U
4554 #define GPIO_BSRR_BS_9 0x00000200U
4555 #define GPIO_BSRR_BS_10 0x00000400U
4556 #define GPIO_BSRR_BS_11 0x00000800U
4557 #define GPIO_BSRR_BS_12 0x00001000U
4558 #define GPIO_BSRR_BS_13 0x00002000U
4559 #define GPIO_BSRR_BS_14 0x00004000U
4560 #define GPIO_BSRR_BS_15 0x00008000U
4561 #define GPIO_BSRR_BR_0 0x00010000U
4562 #define GPIO_BSRR_BR_1 0x00020000U
4563 #define GPIO_BSRR_BR_2 0x00040000U
4564 #define GPIO_BSRR_BR_3 0x00080000U
4565 #define GPIO_BSRR_BR_4 0x00100000U
4566 #define GPIO_BSRR_BR_5 0x00200000U
4567 #define GPIO_BSRR_BR_6 0x00400000U
4568 #define GPIO_BSRR_BR_7 0x00800000U
4569 #define GPIO_BSRR_BR_8 0x01000000U
4570 #define GPIO_BSRR_BR_9 0x02000000U
4571 #define GPIO_BSRR_BR_10 0x04000000U
4572 #define GPIO_BSRR_BR_11 0x08000000U
4573 #define GPIO_BSRR_BR_12 0x10000000U
4574 #define GPIO_BSRR_BR_13 0x20000000U
4575 #define GPIO_BSRR_BR_14 0x40000000U
4576 #define GPIO_BSRR_BR_15 0x80000000U
4577 
4578 /****************** Bit definition for GPIO_LCKR register *********************/
4579 #define GPIO_LCKR_LCK0 0x00000001U
4580 #define GPIO_LCKR_LCK1 0x00000002U
4581 #define GPIO_LCKR_LCK2 0x00000004U
4582 #define GPIO_LCKR_LCK3 0x00000008U
4583 #define GPIO_LCKR_LCK4 0x00000010U
4584 #define GPIO_LCKR_LCK5 0x00000020U
4585 #define GPIO_LCKR_LCK6 0x00000040U
4586 #define GPIO_LCKR_LCK7 0x00000080U
4587 #define GPIO_LCKR_LCK8 0x00000100U
4588 #define GPIO_LCKR_LCK9 0x00000200U
4589 #define GPIO_LCKR_LCK10 0x00000400U
4590 #define GPIO_LCKR_LCK11 0x00000800U
4591 #define GPIO_LCKR_LCK12 0x00001000U
4592 #define GPIO_LCKR_LCK13 0x00002000U
4593 #define GPIO_LCKR_LCK14 0x00004000U
4594 #define GPIO_LCKR_LCK15 0x00008000U
4595 #define GPIO_LCKR_LCKK 0x00010000U
4596 
4597 /******************************************************************************/
4598 /* */
4599 /* HASH */
4600 /* */
4601 /******************************************************************************/
4602 /****************** Bits definition for HASH_CR register ********************/
4603 #define HASH_CR_INIT 0x00000004U
4604 #define HASH_CR_DMAE 0x00000008U
4605 #define HASH_CR_DATATYPE 0x00000030U
4606 #define HASH_CR_DATATYPE_0 0x00000010U
4607 #define HASH_CR_DATATYPE_1 0x00000020U
4608 #define HASH_CR_MODE 0x00000040U
4609 #define HASH_CR_ALGO 0x00040080U
4610 #define HASH_CR_ALGO_0 0x00000080U
4611 #define HASH_CR_ALGO_1 0x00040000U
4612 #define HASH_CR_NBW 0x00000F00U
4613 #define HASH_CR_NBW_0 0x00000100U
4614 #define HASH_CR_NBW_1 0x00000200U
4615 #define HASH_CR_NBW_2 0x00000400U
4616 #define HASH_CR_NBW_3 0x00000800U
4617 #define HASH_CR_DINNE 0x00001000U
4618 #define HASH_CR_MDMAT 0x00002000U
4619 #define HASH_CR_LKEY 0x00010000U
4620 
4621 /****************** Bits definition for HASH_STR register *******************/
4622 #define HASH_STR_NBLW 0x0000001FU
4623 #define HASH_STR_NBLW_0 0x00000001U
4624 #define HASH_STR_NBLW_1 0x00000002U
4625 #define HASH_STR_NBLW_2 0x00000004U
4626 #define HASH_STR_NBLW_3 0x00000008U
4627 #define HASH_STR_NBLW_4 0x00000010U
4628 #define HASH_STR_DCAL 0x00000100U
4629 /* Aliases for HASH_STR register */
4630 #define HASH_STR_NBW HASH_STR_NBLW
4631 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
4632 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
4633 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
4634 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
4635 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
4636 
4637 /****************** Bits definition for HASH_IMR register *******************/
4638 #define HASH_IMR_DINIE 0x00000001U
4639 #define HASH_IMR_DCIE 0x00000002U
4640 /* Aliases for HASH_IMR register */
4641 #define HASH_IMR_DINIM HASH_IMR_DINIE
4642 #define HASH_IMR_DCIM HASH_IMR_DCIE
4643 
4644 /****************** Bits definition for HASH_SR register ********************/
4645 #define HASH_SR_DINIS 0x00000001U
4646 #define HASH_SR_DCIS 0x00000002U
4647 #define HASH_SR_DMAS 0x00000004U
4648 #define HASH_SR_BUSY 0x00000008U
4649 
4650 /******************************************************************************/
4651 /* */
4652 /* Inter-integrated Circuit Interface */
4653 /* */
4654 /******************************************************************************/
4655 /******************* Bit definition for I2C_CR1 register ********************/
4656 #define I2C_CR1_PE 0x00000001U
4657 #define I2C_CR1_SMBUS 0x00000002U
4658 #define I2C_CR1_SMBTYPE 0x00000008U
4659 #define I2C_CR1_ENARP 0x00000010U
4660 #define I2C_CR1_ENPEC 0x00000020U
4661 #define I2C_CR1_ENGC 0x00000040U
4662 #define I2C_CR1_NOSTRETCH 0x00000080U
4663 #define I2C_CR1_START 0x00000100U
4664 #define I2C_CR1_STOP 0x00000200U
4665 #define I2C_CR1_ACK 0x00000400U
4666 #define I2C_CR1_POS 0x00000800U
4667 #define I2C_CR1_PEC 0x00001000U
4668 #define I2C_CR1_ALERT 0x00002000U
4669 #define I2C_CR1_SWRST 0x00008000U
4671 /******************* Bit definition for I2C_CR2 register ********************/
4672 #define I2C_CR2_FREQ 0x0000003FU
4673 #define I2C_CR2_FREQ_0 0x00000001U
4674 #define I2C_CR2_FREQ_1 0x00000002U
4675 #define I2C_CR2_FREQ_2 0x00000004U
4676 #define I2C_CR2_FREQ_3 0x00000008U
4677 #define I2C_CR2_FREQ_4 0x00000010U
4678 #define I2C_CR2_FREQ_5 0x00000020U
4680 #define I2C_CR2_ITERREN 0x00000100U
4681 #define I2C_CR2_ITEVTEN 0x00000200U
4682 #define I2C_CR2_ITBUFEN 0x00000400U
4683 #define I2C_CR2_DMAEN 0x00000800U
4684 #define I2C_CR2_LAST 0x00001000U
4686 /******************* Bit definition for I2C_OAR1 register *******************/
4687 #define I2C_OAR1_ADD1_7 0x000000FEU
4688 #define I2C_OAR1_ADD8_9 0x00000300U
4690 #define I2C_OAR1_ADD0 0x00000001U
4691 #define I2C_OAR1_ADD1 0x00000002U
4692 #define I2C_OAR1_ADD2 0x00000004U
4693 #define I2C_OAR1_ADD3 0x00000008U
4694 #define I2C_OAR1_ADD4 0x00000010U
4695 #define I2C_OAR1_ADD5 0x00000020U
4696 #define I2C_OAR1_ADD6 0x00000040U
4697 #define I2C_OAR1_ADD7 0x00000080U
4698 #define I2C_OAR1_ADD8 0x00000100U
4699 #define I2C_OAR1_ADD9 0x00000200U
4701 #define I2C_OAR1_ADDMODE 0x00008000U
4703 /******************* Bit definition for I2C_OAR2 register *******************/
4704 #define I2C_OAR2_ENDUAL 0x00000001U
4705 #define I2C_OAR2_ADD2 0x000000FEU
4707 /******************** Bit definition for I2C_DR register ********************/
4708 #define I2C_DR_DR 0x000000FFU
4710 /******************* Bit definition for I2C_SR1 register ********************/
4711 #define I2C_SR1_SB 0x00000001U
4712 #define I2C_SR1_ADDR 0x00000002U
4713 #define I2C_SR1_BTF 0x00000004U
4714 #define I2C_SR1_ADD10 0x00000008U
4715 #define I2C_SR1_STOPF 0x00000010U
4716 #define I2C_SR1_RXNE 0x00000040U
4717 #define I2C_SR1_TXE 0x00000080U
4718 #define I2C_SR1_BERR 0x00000100U
4719 #define I2C_SR1_ARLO 0x00000200U
4720 #define I2C_SR1_AF 0x00000400U
4721 #define I2C_SR1_OVR 0x00000800U
4722 #define I2C_SR1_PECERR 0x00001000U
4723 #define I2C_SR1_TIMEOUT 0x00004000U
4724 #define I2C_SR1_SMBALERT 0x00008000U
4726 /******************* Bit definition for I2C_SR2 register ********************/
4727 #define I2C_SR2_MSL 0x00000001U
4728 #define I2C_SR2_BUSY 0x00000002U
4729 #define I2C_SR2_TRA 0x00000004U
4730 #define I2C_SR2_GENCALL 0x00000010U
4731 #define I2C_SR2_SMBDEFAULT 0x00000020U
4732 #define I2C_SR2_SMBHOST 0x00000040U
4733 #define I2C_SR2_DUALF 0x00000080U
4734 #define I2C_SR2_PEC 0x0000FF00U
4736 /******************* Bit definition for I2C_CCR register ********************/
4737 #define I2C_CCR_CCR 0x00000FFFU
4738 #define I2C_CCR_DUTY 0x00004000U
4739 #define I2C_CCR_FS 0x00008000U
4741 /****************** Bit definition for I2C_TRISE register *******************/
4742 #define I2C_TRISE_TRISE 0x0000003FU
4744 /****************** Bit definition for I2C_FLTR register *******************/
4745 #define I2C_FLTR_DNF 0x0000000FU
4746 #define I2C_FLTR_ANOFF 0x00000010U
4748 /******************************************************************************/
4749 /* */
4750 /* Independent WATCHDOG */
4751 /* */
4752 /******************************************************************************/
4753 /******************* Bit definition for IWDG_KR register ********************/
4754 #define IWDG_KR_KEY 0xFFFFU
4756 /******************* Bit definition for IWDG_PR register ********************/
4757 #define IWDG_PR_PR 0x07U
4758 #define IWDG_PR_PR_0 0x01U
4759 #define IWDG_PR_PR_1 0x02U
4760 #define IWDG_PR_PR_2 0x04U
4762 /******************* Bit definition for IWDG_RLR register *******************/
4763 #define IWDG_RLR_RL 0x0FFFU
4765 /******************* Bit definition for IWDG_SR register ********************/
4766 #define IWDG_SR_PVU 0x01U
4767 #define IWDG_SR_RVU 0x02U
4770 /******************************************************************************/
4771 /* */
4772 /* Power Control */
4773 /* */
4774 /******************************************************************************/
4775 /******************** Bit definition for PWR_CR register ********************/
4776 #define PWR_CR_LPDS 0x00000001U
4777 #define PWR_CR_PDDS 0x00000002U
4778 #define PWR_CR_CWUF 0x00000004U
4779 #define PWR_CR_CSBF 0x00000008U
4780 #define PWR_CR_PVDE 0x00000010U
4782 #define PWR_CR_PLS 0x000000E0U
4783 #define PWR_CR_PLS_0 0x00000020U
4784 #define PWR_CR_PLS_1 0x00000040U
4785 #define PWR_CR_PLS_2 0x00000080U
4788 #define PWR_CR_PLS_LEV0 0x00000000U
4789 #define PWR_CR_PLS_LEV1 0x00000020U
4790 #define PWR_CR_PLS_LEV2 0x00000040U
4791 #define PWR_CR_PLS_LEV3 0x00000060U
4792 #define PWR_CR_PLS_LEV4 0x00000080U
4793 #define PWR_CR_PLS_LEV5 0x000000A0U
4794 #define PWR_CR_PLS_LEV6 0x000000C0U
4795 #define PWR_CR_PLS_LEV7 0x000000E0U
4797 #define PWR_CR_DBP 0x00000100U
4798 #define PWR_CR_FPDS 0x00000200U
4799 #define PWR_CR_VOS 0x00004000U
4801 /* Legacy define */
4802 #define PWR_CR_PMODE PWR_CR_VOS
4803 
4804 /******************* Bit definition for PWR_CSR register ********************/
4805 #define PWR_CSR_WUF 0x00000001U
4806 #define PWR_CSR_SBF 0x00000002U
4807 #define PWR_CSR_PVDO 0x00000004U
4808 #define PWR_CSR_BRR 0x00000008U
4809 #define PWR_CSR_EWUP 0x00000100U
4810 #define PWR_CSR_BRE 0x00000200U
4811 #define PWR_CSR_VOSRDY 0x00004000U
4813 /* Legacy define */
4814 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
4815 
4816 /******************************************************************************/
4817 /* */
4818 /* Reset and Clock Control */
4819 /* */
4820 /******************************************************************************/
4821 /******************** Bit definition for RCC_CR register ********************/
4822 #define RCC_CR_HSION 0x00000001U
4823 #define RCC_CR_HSIRDY 0x00000002U
4824 
4825 #define RCC_CR_HSITRIM 0x000000F8U
4826 #define RCC_CR_HSITRIM_0 0x00000008U
4827 #define RCC_CR_HSITRIM_1 0x00000010U
4828 #define RCC_CR_HSITRIM_2 0x00000020U
4829 #define RCC_CR_HSITRIM_3 0x00000040U
4830 #define RCC_CR_HSITRIM_4 0x00000080U
4832 #define RCC_CR_HSICAL 0x0000FF00U
4833 #define RCC_CR_HSICAL_0 0x00000100U
4834 #define RCC_CR_HSICAL_1 0x00000200U
4835 #define RCC_CR_HSICAL_2 0x00000400U
4836 #define RCC_CR_HSICAL_3 0x00000800U
4837 #define RCC_CR_HSICAL_4 0x00001000U
4838 #define RCC_CR_HSICAL_5 0x00002000U
4839 #define RCC_CR_HSICAL_6 0x00004000U
4840 #define RCC_CR_HSICAL_7 0x00008000U
4842 #define RCC_CR_HSEON 0x00010000U
4843 #define RCC_CR_HSERDY 0x00020000U
4844 #define RCC_CR_HSEBYP 0x00040000U
4845 #define RCC_CR_CSSON 0x00080000U
4846 #define RCC_CR_PLLON 0x01000000U
4847 #define RCC_CR_PLLRDY 0x02000000U
4848 #define RCC_CR_PLLI2SON 0x04000000U
4849 #define RCC_CR_PLLI2SRDY 0x08000000U
4850 
4851 /******************** Bit definition for RCC_PLLCFGR register ***************/
4852 #define RCC_PLLCFGR_PLLM 0x0000003FU
4853 #define RCC_PLLCFGR_PLLM_0 0x00000001U
4854 #define RCC_PLLCFGR_PLLM_1 0x00000002U
4855 #define RCC_PLLCFGR_PLLM_2 0x00000004U
4856 #define RCC_PLLCFGR_PLLM_3 0x00000008U
4857 #define RCC_PLLCFGR_PLLM_4 0x00000010U
4858 #define RCC_PLLCFGR_PLLM_5 0x00000020U
4859 
4860 #define RCC_PLLCFGR_PLLN 0x00007FC0U
4861 #define RCC_PLLCFGR_PLLN_0 0x00000040U
4862 #define RCC_PLLCFGR_PLLN_1 0x00000080U
4863 #define RCC_PLLCFGR_PLLN_2 0x00000100U
4864 #define RCC_PLLCFGR_PLLN_3 0x00000200U
4865 #define RCC_PLLCFGR_PLLN_4 0x00000400U
4866 #define RCC_PLLCFGR_PLLN_5 0x00000800U
4867 #define RCC_PLLCFGR_PLLN_6 0x00001000U
4868 #define RCC_PLLCFGR_PLLN_7 0x00002000U
4869 #define RCC_PLLCFGR_PLLN_8 0x00004000U
4870 
4871 #define RCC_PLLCFGR_PLLP 0x00030000U
4872 #define RCC_PLLCFGR_PLLP_0 0x00010000U
4873 #define RCC_PLLCFGR_PLLP_1 0x00020000U
4874 
4875 #define RCC_PLLCFGR_PLLSRC 0x00400000U
4876 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
4877 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
4878 
4879 #define RCC_PLLCFGR_PLLQ 0x0F000000U
4880 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
4881 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
4882 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
4883 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
4884 
4885 /******************** Bit definition for RCC_CFGR register ******************/
4887 #define RCC_CFGR_SW 0x00000003U
4888 #define RCC_CFGR_SW_0 0x00000001U
4889 #define RCC_CFGR_SW_1 0x00000002U
4891 #define RCC_CFGR_SW_HSI 0x00000000U
4892 #define RCC_CFGR_SW_HSE 0x00000001U
4893 #define RCC_CFGR_SW_PLL 0x00000002U
4896 #define RCC_CFGR_SWS 0x0000000CU
4897 #define RCC_CFGR_SWS_0 0x00000004U
4898 #define RCC_CFGR_SWS_1 0x00000008U
4900 #define RCC_CFGR_SWS_HSI 0x00000000U
4901 #define RCC_CFGR_SWS_HSE 0x00000004U
4902 #define RCC_CFGR_SWS_PLL 0x00000008U
4905 #define RCC_CFGR_HPRE 0x000000F0U
4906 #define RCC_CFGR_HPRE_0 0x00000010U
4907 #define RCC_CFGR_HPRE_1 0x00000020U
4908 #define RCC_CFGR_HPRE_2 0x00000040U
4909 #define RCC_CFGR_HPRE_3 0x00000080U
4911 #define RCC_CFGR_HPRE_DIV1 0x00000000U
4912 #define RCC_CFGR_HPRE_DIV2 0x00000080U
4913 #define RCC_CFGR_HPRE_DIV4 0x00000090U
4914 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
4915 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
4916 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
4917 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
4918 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
4919 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
4922 #define RCC_CFGR_PPRE1 0x00001C00U
4923 #define RCC_CFGR_PPRE1_0 0x00000400U
4924 #define RCC_CFGR_PPRE1_1 0x00000800U
4925 #define RCC_CFGR_PPRE1_2 0x00001000U
4927 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
4928 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
4929 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
4930 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
4931 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
4934 #define RCC_CFGR_PPRE2 0x0000E000U
4935 #define RCC_CFGR_PPRE2_0 0x00002000U
4936 #define RCC_CFGR_PPRE2_1 0x00004000U
4937 #define RCC_CFGR_PPRE2_2 0x00008000U
4939 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
4940 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
4941 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
4942 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
4943 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
4946 #define RCC_CFGR_RTCPRE 0x001F0000U
4947 #define RCC_CFGR_RTCPRE_0 0x00010000U
4948 #define RCC_CFGR_RTCPRE_1 0x00020000U
4949 #define RCC_CFGR_RTCPRE_2 0x00040000U
4950 #define RCC_CFGR_RTCPRE_3 0x00080000U
4951 #define RCC_CFGR_RTCPRE_4 0x00100000U
4952 
4954 #define RCC_CFGR_MCO1 0x00600000U
4955 #define RCC_CFGR_MCO1_0 0x00200000U
4956 #define RCC_CFGR_MCO1_1 0x00400000U
4957 
4958 #define RCC_CFGR_I2SSRC 0x00800000U
4959 
4960 #define RCC_CFGR_MCO1PRE 0x07000000U
4961 #define RCC_CFGR_MCO1PRE_0 0x01000000U
4962 #define RCC_CFGR_MCO1PRE_1 0x02000000U
4963 #define RCC_CFGR_MCO1PRE_2 0x04000000U
4964 
4965 #define RCC_CFGR_MCO2PRE 0x38000000U
4966 #define RCC_CFGR_MCO2PRE_0 0x08000000U
4967 #define RCC_CFGR_MCO2PRE_1 0x10000000U
4968 #define RCC_CFGR_MCO2PRE_2 0x20000000U
4969 
4970 #define RCC_CFGR_MCO2 0xC0000000U
4971 #define RCC_CFGR_MCO2_0 0x40000000U
4972 #define RCC_CFGR_MCO2_1 0x80000000U
4973 
4974 /******************** Bit definition for RCC_CIR register *******************/
4975 #define RCC_CIR_LSIRDYF 0x00000001U
4976 #define RCC_CIR_LSERDYF 0x00000002U
4977 #define RCC_CIR_HSIRDYF 0x00000004U
4978 #define RCC_CIR_HSERDYF 0x00000008U
4979 #define RCC_CIR_PLLRDYF 0x00000010U
4980 #define RCC_CIR_PLLI2SRDYF 0x00000020U
4981 
4982 #define RCC_CIR_CSSF 0x00000080U
4983 #define RCC_CIR_LSIRDYIE 0x00000100U
4984 #define RCC_CIR_LSERDYIE 0x00000200U
4985 #define RCC_CIR_HSIRDYIE 0x00000400U
4986 #define RCC_CIR_HSERDYIE 0x00000800U
4987 #define RCC_CIR_PLLRDYIE 0x00001000U
4988 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
4989 
4990 #define RCC_CIR_LSIRDYC 0x00010000U
4991 #define RCC_CIR_LSERDYC 0x00020000U
4992 #define RCC_CIR_HSIRDYC 0x00040000U
4993 #define RCC_CIR_HSERDYC 0x00080000U
4994 #define RCC_CIR_PLLRDYC 0x00100000U
4995 #define RCC_CIR_PLLI2SRDYC 0x00200000U
4996 
4997 #define RCC_CIR_CSSC 0x00800000U
4998 
4999 /******************** Bit definition for RCC_AHB1RSTR register **************/
5000 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5001 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5002 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5003 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5004 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5005 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5006 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5007 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5008 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5009 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5010 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5011 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5012 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5013 
5014 /******************** Bit definition for RCC_AHB2RSTR register **************/
5015 #define RCC_AHB2RSTR_CRYPRST 0x00000010U
5016 #define RCC_AHB2RSTR_HASHRST 0x00000020U
5017  /* maintained for legacy purpose */
5018  #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
5019 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5020 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5021 
5022 /******************** Bit definition for RCC_AHB3RSTR register **************/
5023 
5024 #define RCC_AHB3RSTR_FSMCRST 0x00000001U
5025 
5026 /******************** Bit definition for RCC_APB1RSTR register **************/
5027 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5028 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5029 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5030 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5031 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5032 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5033 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5034 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5035 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5036 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5037 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5038 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5039 #define RCC_APB1RSTR_USART2RST 0x00020000U
5040 #define RCC_APB1RSTR_USART3RST 0x00040000U
5041 #define RCC_APB1RSTR_UART4RST 0x00080000U
5042 #define RCC_APB1RSTR_UART5RST 0x00100000U
5043 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5044 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5045 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5046 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5047 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5048 #define RCC_APB1RSTR_PWRRST 0x10000000U
5049 #define RCC_APB1RSTR_DACRST 0x20000000U
5050 
5051 /******************** Bit definition for RCC_APB2RSTR register **************/
5052 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5053 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5054 #define RCC_APB2RSTR_USART1RST 0x00000010U
5055 #define RCC_APB2RSTR_USART6RST 0x00000020U
5056 #define RCC_APB2RSTR_ADCRST 0x00000100U
5057 #define RCC_APB2RSTR_SDIORST 0x00000800U
5058 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5059 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5060 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5061 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5062 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5063 
5064 /* Old SPI1RST bit definition, maintained for legacy purpose */
5065 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5066 
5067 /******************** Bit definition for RCC_AHB1ENR register ***************/
5068 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5069 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5070 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5071 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5072 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5073 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5074 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5075 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5076 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5077 #define RCC_AHB1ENR_CRCEN 0x00001000U
5078 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5079 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
5080 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5081 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5082 
5083 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5084 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5085 
5086 /******************** Bit definition for RCC_AHB2ENR register ***************/
5087 #define RCC_AHB2ENR_CRYPEN 0x00000010U
5088 #define RCC_AHB2ENR_HASHEN 0x00000020U
5089 #define RCC_AHB2ENR_RNGEN 0x00000040U
5090 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5091 
5092 /******************** Bit definition for RCC_AHB3ENR register ***************/
5093 
5094 #define RCC_AHB3ENR_FSMCEN 0x00000001U
5095 
5096 /******************** Bit definition for RCC_APB1ENR register ***************/
5097 #define RCC_APB1ENR_TIM2EN 0x00000001U
5098 #define RCC_APB1ENR_TIM3EN 0x00000002U
5099 #define RCC_APB1ENR_TIM4EN 0x00000004U
5100 #define RCC_APB1ENR_TIM5EN 0x00000008U
5101 #define RCC_APB1ENR_TIM6EN 0x00000010U
5102 #define RCC_APB1ENR_TIM7EN 0x00000020U
5103 #define RCC_APB1ENR_TIM12EN 0x00000040U
5104 #define RCC_APB1ENR_TIM13EN 0x00000080U
5105 #define RCC_APB1ENR_TIM14EN 0x00000100U
5106 #define RCC_APB1ENR_WWDGEN 0x00000800U
5107 #define RCC_APB1ENR_SPI2EN 0x00004000U
5108 #define RCC_APB1ENR_SPI3EN 0x00008000U
5109 #define RCC_APB1ENR_USART2EN 0x00020000U
5110 #define RCC_APB1ENR_USART3EN 0x00040000U
5111 #define RCC_APB1ENR_UART4EN 0x00080000U
5112 #define RCC_APB1ENR_UART5EN 0x00100000U
5113 #define RCC_APB1ENR_I2C1EN 0x00200000U
5114 #define RCC_APB1ENR_I2C2EN 0x00400000U
5115 #define RCC_APB1ENR_I2C3EN 0x00800000U
5116 #define RCC_APB1ENR_CAN1EN 0x02000000U
5117 #define RCC_APB1ENR_CAN2EN 0x04000000U
5118 #define RCC_APB1ENR_PWREN 0x10000000U
5119 #define RCC_APB1ENR_DACEN 0x20000000U
5120 
5121 /******************** Bit definition for RCC_APB2ENR register ***************/
5122 #define RCC_APB2ENR_TIM1EN 0x00000001U
5123 #define RCC_APB2ENR_TIM8EN 0x00000002U
5124 #define RCC_APB2ENR_USART1EN 0x00000010U
5125 #define RCC_APB2ENR_USART6EN 0x00000020U
5126 #define RCC_APB2ENR_ADC1EN 0x00000100U
5127 #define RCC_APB2ENR_ADC2EN 0x00000200U
5128 #define RCC_APB2ENR_ADC3EN 0x00000400U
5129 #define RCC_APB2ENR_SDIOEN 0x00000800U
5130 #define RCC_APB2ENR_SPI1EN 0x00001000U
5131 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5132 #define RCC_APB2ENR_TIM9EN 0x00010000U
5133 #define RCC_APB2ENR_TIM10EN 0x00020000U
5134 #define RCC_APB2ENR_TIM11EN 0x00040000U
5135 #define RCC_APB2ENR_SPI5EN 0x00100000U
5136 #define RCC_APB2ENR_SPI6EN 0x00200000U
5137 
5138 /******************** Bit definition for RCC_AHB1LPENR register *************/
5139 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5140 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5141 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5142 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5143 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5144 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5145 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5146 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5147 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5148 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5149 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5150 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5151 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5152 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5153 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5154 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5155 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5156 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5157 
5158 /******************** Bit definition for RCC_AHB2LPENR register *************/
5159 #define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
5160 #define RCC_AHB2LPENR_HASHLPEN 0x00000020U
5161 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5162 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5163 
5164 /******************** Bit definition for RCC_AHB3LPENR register *************/
5165 
5166 #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
5167 
5168 /******************** Bit definition for RCC_APB1LPENR register *************/
5169 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5170 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5171 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5172 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5173 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5174 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5175 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5176 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5177 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5178 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5179 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5180 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5181 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5182 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5183 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5184 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5185 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5186 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5187 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5188 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5189 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5190 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5191 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5192 
5193 /******************** Bit definition for RCC_APB2LPENR register *************/
5194 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5195 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5196 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5197 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5198 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5199 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5200 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5201 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
5202 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5203 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5204 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5205 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5206 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5207 
5208 /******************** Bit definition for RCC_BDCR register ******************/
5209 #define RCC_BDCR_LSEON 0x00000001U
5210 #define RCC_BDCR_LSERDY 0x00000002U
5211 #define RCC_BDCR_LSEBYP 0x00000004U
5212 
5213 #define RCC_BDCR_RTCSEL 0x00000300U
5214 #define RCC_BDCR_RTCSEL_0 0x00000100U
5215 #define RCC_BDCR_RTCSEL_1 0x00000200U
5216 
5217 #define RCC_BDCR_RTCEN 0x00008000U
5218 #define RCC_BDCR_BDRST 0x00010000U
5219 
5220 /******************** Bit definition for RCC_CSR register *******************/
5221 #define RCC_CSR_LSION 0x00000001U
5222 #define RCC_CSR_LSIRDY 0x00000002U
5223 #define RCC_CSR_RMVF 0x01000000U
5224 #define RCC_CSR_BORRSTF 0x02000000U
5225 #define RCC_CSR_PADRSTF 0x04000000U
5226 #define RCC_CSR_PORRSTF 0x08000000U
5227 #define RCC_CSR_SFTRSTF 0x10000000U
5228 #define RCC_CSR_WDGRSTF 0x20000000U
5229 #define RCC_CSR_WWDGRSTF 0x40000000U
5230 #define RCC_CSR_LPWRRSTF 0x80000000U
5231 
5232 /******************** Bit definition for RCC_SSCGR register *****************/
5233 #define RCC_SSCGR_MODPER 0x00001FFFU
5234 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5235 #define RCC_SSCGR_SPREADSEL 0x40000000U
5236 #define RCC_SSCGR_SSCGEN 0x80000000U
5237 
5238 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5239 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5240 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5241 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5242 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5243 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5244 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5245 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5246 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5247 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5248 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5249 
5250 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5251 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5252 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5253 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5254 
5255 /******************************************************************************/
5256 /* */
5257 /* RNG */
5258 /* */
5259 /******************************************************************************/
5260 /******************** Bits definition for RNG_CR register *******************/
5261 #define RNG_CR_RNGEN 0x00000004U
5262 #define RNG_CR_IE 0x00000008U
5263 
5264 /******************** Bits definition for RNG_SR register *******************/
5265 #define RNG_SR_DRDY 0x00000001U
5266 #define RNG_SR_CECS 0x00000002U
5267 #define RNG_SR_SECS 0x00000004U
5268 #define RNG_SR_CEIS 0x00000020U
5269 #define RNG_SR_SEIS 0x00000040U
5270 
5271 /******************************************************************************/
5272 /* */
5273 /* Real-Time Clock (RTC) */
5274 /* */
5275 /******************************************************************************/
5276 /******************** Bits definition for RTC_TR register *******************/
5277 #define RTC_TR_PM 0x00400000U
5278 #define RTC_TR_HT 0x00300000U
5279 #define RTC_TR_HT_0 0x00100000U
5280 #define RTC_TR_HT_1 0x00200000U
5281 #define RTC_TR_HU 0x000F0000U
5282 #define RTC_TR_HU_0 0x00010000U
5283 #define RTC_TR_HU_1 0x00020000U
5284 #define RTC_TR_HU_2 0x00040000U
5285 #define RTC_TR_HU_3 0x00080000U
5286 #define RTC_TR_MNT 0x00007000U
5287 #define RTC_TR_MNT_0 0x00001000U
5288 #define RTC_TR_MNT_1 0x00002000U
5289 #define RTC_TR_MNT_2 0x00004000U
5290 #define RTC_TR_MNU 0x00000F00U
5291 #define RTC_TR_MNU_0 0x00000100U
5292 #define RTC_TR_MNU_1 0x00000200U
5293 #define RTC_TR_MNU_2 0x00000400U
5294 #define RTC_TR_MNU_3 0x00000800U
5295 #define RTC_TR_ST 0x00000070U
5296 #define RTC_TR_ST_0 0x00000010U
5297 #define RTC_TR_ST_1 0x00000020U
5298 #define RTC_TR_ST_2 0x00000040U
5299 #define RTC_TR_SU 0x0000000FU
5300 #define RTC_TR_SU_0 0x00000001U
5301 #define RTC_TR_SU_1 0x00000002U
5302 #define RTC_TR_SU_2 0x00000004U
5303 #define RTC_TR_SU_3 0x00000008U
5304 
5305 /******************** Bits definition for RTC_DR register *******************/
5306 #define RTC_DR_YT 0x00F00000U
5307 #define RTC_DR_YT_0 0x00100000U
5308 #define RTC_DR_YT_1 0x00200000U
5309 #define RTC_DR_YT_2 0x00400000U
5310 #define RTC_DR_YT_3 0x00800000U
5311 #define RTC_DR_YU 0x000F0000U
5312 #define RTC_DR_YU_0 0x00010000U
5313 #define RTC_DR_YU_1 0x00020000U
5314 #define RTC_DR_YU_2 0x00040000U
5315 #define RTC_DR_YU_3 0x00080000U
5316 #define RTC_DR_WDU 0x0000E000U
5317 #define RTC_DR_WDU_0 0x00002000U
5318 #define RTC_DR_WDU_1 0x00004000U
5319 #define RTC_DR_WDU_2 0x00008000U
5320 #define RTC_DR_MT 0x00001000U
5321 #define RTC_DR_MU 0x00000F00U
5322 #define RTC_DR_MU_0 0x00000100U
5323 #define RTC_DR_MU_1 0x00000200U
5324 #define RTC_DR_MU_2 0x00000400U
5325 #define RTC_DR_MU_3 0x00000800U
5326 #define RTC_DR_DT 0x00000030U
5327 #define RTC_DR_DT_0 0x00000010U
5328 #define RTC_DR_DT_1 0x00000020U
5329 #define RTC_DR_DU 0x0000000FU
5330 #define RTC_DR_DU_0 0x00000001U
5331 #define RTC_DR_DU_1 0x00000002U
5332 #define RTC_DR_DU_2 0x00000004U
5333 #define RTC_DR_DU_3 0x00000008U
5334 
5335 /******************** Bits definition for RTC_CR register *******************/
5336 #define RTC_CR_COE 0x00800000U
5337 #define RTC_CR_OSEL 0x00600000U
5338 #define RTC_CR_OSEL_0 0x00200000U
5339 #define RTC_CR_OSEL_1 0x00400000U
5340 #define RTC_CR_POL 0x00100000U
5341 #define RTC_CR_COSEL 0x00080000U
5342 #define RTC_CR_BCK 0x00040000U
5343 #define RTC_CR_SUB1H 0x00020000U
5344 #define RTC_CR_ADD1H 0x00010000U
5345 #define RTC_CR_TSIE 0x00008000U
5346 #define RTC_CR_WUTIE 0x00004000U
5347 #define RTC_CR_ALRBIE 0x00002000U
5348 #define RTC_CR_ALRAIE 0x00001000U
5349 #define RTC_CR_TSE 0x00000800U
5350 #define RTC_CR_WUTE 0x00000400U
5351 #define RTC_CR_ALRBE 0x00000200U
5352 #define RTC_CR_ALRAE 0x00000100U
5353 #define RTC_CR_DCE 0x00000080U
5354 #define RTC_CR_FMT 0x00000040U
5355 #define RTC_CR_BYPSHAD 0x00000020U
5356 #define RTC_CR_REFCKON 0x00000010U
5357 #define RTC_CR_TSEDGE 0x00000008U
5358 #define RTC_CR_WUCKSEL 0x00000007U
5359 #define RTC_CR_WUCKSEL_0 0x00000001U
5360 #define RTC_CR_WUCKSEL_1 0x00000002U
5361 #define RTC_CR_WUCKSEL_2 0x00000004U
5362 
5363 /******************** Bits definition for RTC_ISR register ******************/
5364 #define RTC_ISR_RECALPF 0x00010000U
5365 #define RTC_ISR_TAMP1F 0x00002000U
5366 #define RTC_ISR_TAMP2F 0x00004000U
5367 #define RTC_ISR_TSOVF 0x00001000U
5368 #define RTC_ISR_TSF 0x00000800U
5369 #define RTC_ISR_WUTF 0x00000400U
5370 #define RTC_ISR_ALRBF 0x00000200U
5371 #define RTC_ISR_ALRAF 0x00000100U
5372 #define RTC_ISR_INIT 0x00000080U
5373 #define RTC_ISR_INITF 0x00000040U
5374 #define RTC_ISR_RSF 0x00000020U
5375 #define RTC_ISR_INITS 0x00000010U
5376 #define RTC_ISR_SHPF 0x00000008U
5377 #define RTC_ISR_WUTWF 0x00000004U
5378 #define RTC_ISR_ALRBWF 0x00000002U
5379 #define RTC_ISR_ALRAWF 0x00000001U
5380 
5381 /******************** Bits definition for RTC_PRER register *****************/
5382 #define RTC_PRER_PREDIV_A 0x007F0000U
5383 #define RTC_PRER_PREDIV_S 0x00007FFFU
5384 
5385 /******************** Bits definition for RTC_WUTR register *****************/
5386 #define RTC_WUTR_WUT 0x0000FFFFU
5387 
5388 /******************** Bits definition for RTC_CALIBR register ***************/
5389 #define RTC_CALIBR_DCS 0x00000080U
5390 #define RTC_CALIBR_DC 0x0000001FU
5391 
5392 /******************** Bits definition for RTC_ALRMAR register ***************/
5393 #define RTC_ALRMAR_MSK4 0x80000000U
5394 #define RTC_ALRMAR_WDSEL 0x40000000U
5395 #define RTC_ALRMAR_DT 0x30000000U
5396 #define RTC_ALRMAR_DT_0 0x10000000U
5397 #define RTC_ALRMAR_DT_1 0x20000000U
5398 #define RTC_ALRMAR_DU 0x0F000000U
5399 #define RTC_ALRMAR_DU_0 0x01000000U
5400 #define RTC_ALRMAR_DU_1 0x02000000U
5401 #define RTC_ALRMAR_DU_2 0x04000000U
5402 #define RTC_ALRMAR_DU_3 0x08000000U
5403 #define RTC_ALRMAR_MSK3 0x00800000U
5404 #define RTC_ALRMAR_PM 0x00400000U
5405 #define RTC_ALRMAR_HT 0x00300000U
5406 #define RTC_ALRMAR_HT_0 0x00100000U
5407 #define RTC_ALRMAR_HT_1 0x00200000U
5408 #define RTC_ALRMAR_HU 0x000F0000U
5409 #define RTC_ALRMAR_HU_0 0x00010000U
5410 #define RTC_ALRMAR_HU_1 0x00020000U
5411 #define RTC_ALRMAR_HU_2 0x00040000U
5412 #define RTC_ALRMAR_HU_3 0x00080000U
5413 #define RTC_ALRMAR_MSK2 0x00008000U
5414 #define RTC_ALRMAR_MNT 0x00007000U
5415 #define RTC_ALRMAR_MNT_0 0x00001000U
5416 #define RTC_ALRMAR_MNT_1 0x00002000U
5417 #define RTC_ALRMAR_MNT_2 0x00004000U
5418 #define RTC_ALRMAR_MNU 0x00000F00U
5419 #define RTC_ALRMAR_MNU_0 0x00000100U
5420 #define RTC_ALRMAR_MNU_1 0x00000200U
5421 #define RTC_ALRMAR_MNU_2 0x00000400U
5422 #define RTC_ALRMAR_MNU_3 0x00000800U
5423 #define RTC_ALRMAR_MSK1 0x00000080U
5424 #define RTC_ALRMAR_ST 0x00000070U
5425 #define RTC_ALRMAR_ST_0 0x00000010U
5426 #define RTC_ALRMAR_ST_1 0x00000020U
5427 #define RTC_ALRMAR_ST_2 0x00000040U
5428 #define RTC_ALRMAR_SU 0x0000000FU
5429 #define RTC_ALRMAR_SU_0 0x00000001U
5430 #define RTC_ALRMAR_SU_1 0x00000002U
5431 #define RTC_ALRMAR_SU_2 0x00000004U
5432 #define RTC_ALRMAR_SU_3 0x00000008U
5433 
5434 /******************** Bits definition for RTC_ALRMBR register ***************/
5435 #define RTC_ALRMBR_MSK4 0x80000000U
5436 #define RTC_ALRMBR_WDSEL 0x40000000U
5437 #define RTC_ALRMBR_DT 0x30000000U
5438 #define RTC_ALRMBR_DT_0 0x10000000U
5439 #define RTC_ALRMBR_DT_1 0x20000000U
5440 #define RTC_ALRMBR_DU 0x0F000000U
5441 #define RTC_ALRMBR_DU_0 0x01000000U
5442 #define RTC_ALRMBR_DU_1 0x02000000U
5443 #define RTC_ALRMBR_DU_2 0x04000000U
5444 #define RTC_ALRMBR_DU_3 0x08000000U
5445 #define RTC_ALRMBR_MSK3 0x00800000U
5446 #define RTC_ALRMBR_PM 0x00400000U
5447 #define RTC_ALRMBR_HT 0x00300000U
5448 #define RTC_ALRMBR_HT_0 0x00100000U
5449 #define RTC_ALRMBR_HT_1 0x00200000U
5450 #define RTC_ALRMBR_HU 0x000F0000U
5451 #define RTC_ALRMBR_HU_0 0x00010000U
5452 #define RTC_ALRMBR_HU_1 0x00020000U
5453 #define RTC_ALRMBR_HU_2 0x00040000U
5454 #define RTC_ALRMBR_HU_3 0x00080000U
5455 #define RTC_ALRMBR_MSK2 0x00008000U
5456 #define RTC_ALRMBR_MNT 0x00007000U
5457 #define RTC_ALRMBR_MNT_0 0x00001000U
5458 #define RTC_ALRMBR_MNT_1 0x00002000U
5459 #define RTC_ALRMBR_MNT_2 0x00004000U
5460 #define RTC_ALRMBR_MNU 0x00000F00U
5461 #define RTC_ALRMBR_MNU_0 0x00000100U
5462 #define RTC_ALRMBR_MNU_1 0x00000200U
5463 #define RTC_ALRMBR_MNU_2 0x00000400U
5464 #define RTC_ALRMBR_MNU_3 0x00000800U
5465 #define RTC_ALRMBR_MSK1 0x00000080U
5466 #define RTC_ALRMBR_ST 0x00000070U
5467 #define RTC_ALRMBR_ST_0 0x00000010U
5468 #define RTC_ALRMBR_ST_1 0x00000020U
5469 #define RTC_ALRMBR_ST_2 0x00000040U
5470 #define RTC_ALRMBR_SU 0x0000000FU
5471 #define RTC_ALRMBR_SU_0 0x00000001U
5472 #define RTC_ALRMBR_SU_1 0x00000002U
5473 #define RTC_ALRMBR_SU_2 0x00000004U
5474 #define RTC_ALRMBR_SU_3 0x00000008U
5475 
5476 /******************** Bits definition for RTC_WPR register ******************/
5477 #define RTC_WPR_KEY 0x000000FFU
5478 
5479 /******************** Bits definition for RTC_SSR register ******************/
5480 #define RTC_SSR_SS 0x0000FFFFU
5481 
5482 /******************** Bits definition for RTC_SHIFTR register ***************/
5483 #define RTC_SHIFTR_SUBFS 0x00007FFFU
5484 #define RTC_SHIFTR_ADD1S 0x80000000U
5485 
5486 /******************** Bits definition for RTC_TSTR register *****************/
5487 #define RTC_TSTR_PM 0x00400000U
5488 #define RTC_TSTR_HT 0x00300000U
5489 #define RTC_TSTR_HT_0 0x00100000U
5490 #define RTC_TSTR_HT_1 0x00200000U
5491 #define RTC_TSTR_HU 0x000F0000U
5492 #define RTC_TSTR_HU_0 0x00010000U
5493 #define RTC_TSTR_HU_1 0x00020000U
5494 #define RTC_TSTR_HU_2 0x00040000U
5495 #define RTC_TSTR_HU_3 0x00080000U
5496 #define RTC_TSTR_MNT 0x00007000U
5497 #define RTC_TSTR_MNT_0 0x00001000U
5498 #define RTC_TSTR_MNT_1 0x00002000U
5499 #define RTC_TSTR_MNT_2 0x00004000U
5500 #define RTC_TSTR_MNU 0x00000F00U
5501 #define RTC_TSTR_MNU_0 0x00000100U
5502 #define RTC_TSTR_MNU_1 0x00000200U
5503 #define RTC_TSTR_MNU_2 0x00000400U
5504 #define RTC_TSTR_MNU_3 0x00000800U
5505 #define RTC_TSTR_ST 0x00000070U
5506 #define RTC_TSTR_ST_0 0x00000010U
5507 #define RTC_TSTR_ST_1 0x00000020U
5508 #define RTC_TSTR_ST_2 0x00000040U
5509 #define RTC_TSTR_SU 0x0000000FU
5510 #define RTC_TSTR_SU_0 0x00000001U
5511 #define RTC_TSTR_SU_1 0x00000002U
5512 #define RTC_TSTR_SU_2 0x00000004U
5513 #define RTC_TSTR_SU_3 0x00000008U
5514 
5515 /******************** Bits definition for RTC_TSDR register *****************/
5516 #define RTC_TSDR_WDU 0x0000E000U
5517 #define RTC_TSDR_WDU_0 0x00002000U
5518 #define RTC_TSDR_WDU_1 0x00004000U
5519 #define RTC_TSDR_WDU_2 0x00008000U
5520 #define RTC_TSDR_MT 0x00001000U
5521 #define RTC_TSDR_MU 0x00000F00U
5522 #define RTC_TSDR_MU_0 0x00000100U
5523 #define RTC_TSDR_MU_1 0x00000200U
5524 #define RTC_TSDR_MU_2 0x00000400U
5525 #define RTC_TSDR_MU_3 0x00000800U
5526 #define RTC_TSDR_DT 0x00000030U
5527 #define RTC_TSDR_DT_0 0x00000010U
5528 #define RTC_TSDR_DT_1 0x00000020U
5529 #define RTC_TSDR_DU 0x0000000FU
5530 #define RTC_TSDR_DU_0 0x00000001U
5531 #define RTC_TSDR_DU_1 0x00000002U
5532 #define RTC_TSDR_DU_2 0x00000004U
5533 #define RTC_TSDR_DU_3 0x00000008U
5534 
5535 /******************** Bits definition for RTC_TSSSR register ****************/
5536 #define RTC_TSSSR_SS 0x0000FFFFU
5537 
5538 /******************** Bits definition for RTC_CAL register *****************/
5539 #define RTC_CALR_CALP 0x00008000U
5540 #define RTC_CALR_CALW8 0x00004000U
5541 #define RTC_CALR_CALW16 0x00002000U
5542 #define RTC_CALR_CALM 0x000001FFU
5543 #define RTC_CALR_CALM_0 0x00000001U
5544 #define RTC_CALR_CALM_1 0x00000002U
5545 #define RTC_CALR_CALM_2 0x00000004U
5546 #define RTC_CALR_CALM_3 0x00000008U
5547 #define RTC_CALR_CALM_4 0x00000010U
5548 #define RTC_CALR_CALM_5 0x00000020U
5549 #define RTC_CALR_CALM_6 0x00000040U
5550 #define RTC_CALR_CALM_7 0x00000080U
5551 #define RTC_CALR_CALM_8 0x00000100U
5552 
5553 /******************** Bits definition for RTC_TAFCR register ****************/
5554 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
5555 #define RTC_TAFCR_TSINSEL 0x00020000U
5556 #define RTC_TAFCR_TAMPINSEL 0x00010000U
5557 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
5558 #define RTC_TAFCR_TAMPPRCH 0x00006000U
5559 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
5560 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
5561 #define RTC_TAFCR_TAMPFLT 0x00001800U
5562 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
5563 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
5564 #define RTC_TAFCR_TAMPFREQ 0x00000700U
5565 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
5566 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
5567 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
5568 #define RTC_TAFCR_TAMPTS 0x00000080U
5569 #define RTC_TAFCR_TAMP2TRG 0x00000010U
5570 #define RTC_TAFCR_TAMP2E 0x00000008U
5571 #define RTC_TAFCR_TAMPIE 0x00000004U
5572 #define RTC_TAFCR_TAMP1TRG 0x00000002U
5573 #define RTC_TAFCR_TAMP1E 0x00000001U
5574 
5575 /******************** Bits definition for RTC_ALRMASSR register *************/
5576 #define RTC_ALRMASSR_MASKSS 0x0F000000U
5577 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
5578 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
5579 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
5580 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
5581 #define RTC_ALRMASSR_SS 0x00007FFFU
5582 
5583 /******************** Bits definition for RTC_ALRMBSSR register *************/
5584 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
5585 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
5586 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
5587 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
5588 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
5589 #define RTC_ALRMBSSR_SS 0x00007FFFU
5590 
5591 /******************** Bits definition for RTC_BKP0R register ****************/
5592 #define RTC_BKP0R 0xFFFFFFFFU
5593 
5594 /******************** Bits definition for RTC_BKP1R register ****************/
5595 #define RTC_BKP1R 0xFFFFFFFFU
5596 
5597 /******************** Bits definition for RTC_BKP2R register ****************/
5598 #define RTC_BKP2R 0xFFFFFFFFU
5599 
5600 /******************** Bits definition for RTC_BKP3R register ****************/
5601 #define RTC_BKP3R 0xFFFFFFFFU
5602 
5603 /******************** Bits definition for RTC_BKP4R register ****************/
5604 #define RTC_BKP4R 0xFFFFFFFFU
5605 
5606 /******************** Bits definition for RTC_BKP5R register ****************/
5607 #define RTC_BKP5R 0xFFFFFFFFU
5608 
5609 /******************** Bits definition for RTC_BKP6R register ****************/
5610 #define RTC_BKP6R 0xFFFFFFFFU
5611 
5612 /******************** Bits definition for RTC_BKP7R register ****************/
5613 #define RTC_BKP7R 0xFFFFFFFFU
5614 
5615 /******************** Bits definition for RTC_BKP8R register ****************/
5616 #define RTC_BKP8R 0xFFFFFFFFU
5617 
5618 /******************** Bits definition for RTC_BKP9R register ****************/
5619 #define RTC_BKP9R 0xFFFFFFFFU
5620 
5621 /******************** Bits definition for RTC_BKP10R register ***************/
5622 #define RTC_BKP10R 0xFFFFFFFFU
5623 
5624 /******************** Bits definition for RTC_BKP11R register ***************/
5625 #define RTC_BKP11R 0xFFFFFFFFU
5626 
5627 /******************** Bits definition for RTC_BKP12R register ***************/
5628 #define RTC_BKP12R 0xFFFFFFFFU
5629 
5630 /******************** Bits definition for RTC_BKP13R register ***************/
5631 #define RTC_BKP13R 0xFFFFFFFFU
5632 
5633 /******************** Bits definition for RTC_BKP14R register ***************/
5634 #define RTC_BKP14R 0xFFFFFFFFU
5635 
5636 /******************** Bits definition for RTC_BKP15R register ***************/
5637 #define RTC_BKP15R 0xFFFFFFFFU
5638 
5639 /******************** Bits definition for RTC_BKP16R register ***************/
5640 #define RTC_BKP16R 0xFFFFFFFFU
5641 
5642 /******************** Bits definition for RTC_BKP17R register ***************/
5643 #define RTC_BKP17R 0xFFFFFFFFU
5644 
5645 /******************** Bits definition for RTC_BKP18R register ***************/
5646 #define RTC_BKP18R 0xFFFFFFFFU
5647 
5648 /******************** Bits definition for RTC_BKP19R register ***************/
5649 #define RTC_BKP19R 0xFFFFFFFFU
5650 
5651 
5652 
5653 /******************************************************************************/
5654 /* */
5655 /* SD host Interface */
5656 /* */
5657 /******************************************************************************/
5658 /****************** Bit definition for SDIO_POWER register ******************/
5659 #define SDIO_POWER_PWRCTRL 0x03U
5660 #define SDIO_POWER_PWRCTRL_0 0x01U
5661 #define SDIO_POWER_PWRCTRL_1 0x02U
5663 /****************** Bit definition for SDIO_CLKCR register ******************/
5664 #define SDIO_CLKCR_CLKDIV 0x00FFU
5665 #define SDIO_CLKCR_CLKEN 0x0100U
5666 #define SDIO_CLKCR_PWRSAV 0x0200U
5667 #define SDIO_CLKCR_BYPASS 0x0400U
5669 #define SDIO_CLKCR_WIDBUS 0x1800U
5670 #define SDIO_CLKCR_WIDBUS_0 0x0800U
5671 #define SDIO_CLKCR_WIDBUS_1 0x1000U
5673 #define SDIO_CLKCR_NEGEDGE 0x2000U
5674 #define SDIO_CLKCR_HWFC_EN 0x4000U
5676 /******************* Bit definition for SDIO_ARG register *******************/
5677 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
5679 /******************* Bit definition for SDIO_CMD register *******************/
5680 #define SDIO_CMD_CMDINDEX 0x003FU
5682 #define SDIO_CMD_WAITRESP 0x00C0U
5683 #define SDIO_CMD_WAITRESP_0 0x0040U
5684 #define SDIO_CMD_WAITRESP_1 0x0080U
5686 #define SDIO_CMD_WAITINT 0x0100U
5687 #define SDIO_CMD_WAITPEND 0x0200U
5688 #define SDIO_CMD_CPSMEN 0x0400U
5689 #define SDIO_CMD_SDIOSUSPEND 0x0800U
5690 #define SDIO_CMD_ENCMDCOMPL 0x1000U
5691 #define SDIO_CMD_NIEN 0x2000U
5692 #define SDIO_CMD_CEATACMD 0x4000U
5694 /***************** Bit definition for SDIO_RESPCMD register *****************/
5695 #define SDIO_RESPCMD_RESPCMD 0x3FU
5697 /****************** Bit definition for SDIO_RESP0 register ******************/
5698 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
5700 /****************** Bit definition for SDIO_RESP1 register ******************/
5701 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
5703 /****************** Bit definition for SDIO_RESP2 register ******************/
5704 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
5706 /****************** Bit definition for SDIO_RESP3 register ******************/
5707 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
5709 /****************** Bit definition for SDIO_RESP4 register ******************/
5710 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
5712 /****************** Bit definition for SDIO_DTIMER register *****************/
5713 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
5715 /****************** Bit definition for SDIO_DLEN register *******************/
5716 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
5718 /****************** Bit definition for SDIO_DCTRL register ******************/
5719 #define SDIO_DCTRL_DTEN 0x0001U
5720 #define SDIO_DCTRL_DTDIR 0x0002U
5721 #define SDIO_DCTRL_DTMODE 0x0004U
5722 #define SDIO_DCTRL_DMAEN 0x0008U
5724 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
5725 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
5726 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
5727 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
5728 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
5730 #define SDIO_DCTRL_RWSTART 0x0100U
5731 #define SDIO_DCTRL_RWSTOP 0x0200U
5732 #define SDIO_DCTRL_RWMOD 0x0400U
5733 #define SDIO_DCTRL_SDIOEN 0x0800U
5735 /****************** Bit definition for SDIO_DCOUNT register *****************/
5736 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
5738 /****************** Bit definition for SDIO_STA register ********************/
5739 #define SDIO_STA_CCRCFAIL 0x00000001U
5740 #define SDIO_STA_DCRCFAIL 0x00000002U
5741 #define SDIO_STA_CTIMEOUT 0x00000004U
5742 #define SDIO_STA_DTIMEOUT 0x00000008U
5743 #define SDIO_STA_TXUNDERR 0x00000010U
5744 #define SDIO_STA_RXOVERR 0x00000020U
5745 #define SDIO_STA_CMDREND 0x00000040U
5746 #define SDIO_STA_CMDSENT 0x00000080U
5747 #define SDIO_STA_DATAEND 0x00000100U
5748 #define SDIO_STA_STBITERR 0x00000200U
5749 #define SDIO_STA_DBCKEND 0x00000400U
5750 #define SDIO_STA_CMDACT 0x00000800U
5751 #define SDIO_STA_TXACT 0x00001000U
5752 #define SDIO_STA_RXACT 0x00002000U
5753 #define SDIO_STA_TXFIFOHE 0x00004000U
5754 #define SDIO_STA_RXFIFOHF 0x00008000U
5755 #define SDIO_STA_TXFIFOF 0x00010000U
5756 #define SDIO_STA_RXFIFOF 0x00020000U
5757 #define SDIO_STA_TXFIFOE 0x00040000U
5758 #define SDIO_STA_RXFIFOE 0x00080000U
5759 #define SDIO_STA_TXDAVL 0x00100000U
5760 #define SDIO_STA_RXDAVL 0x00200000U
5761 #define SDIO_STA_SDIOIT 0x00400000U
5762 #define SDIO_STA_CEATAEND 0x00800000U
5764 /******************* Bit definition for SDIO_ICR register *******************/
5765 #define SDIO_ICR_CCRCFAILC 0x00000001U
5766 #define SDIO_ICR_DCRCFAILC 0x00000002U
5767 #define SDIO_ICR_CTIMEOUTC 0x00000004U
5768 #define SDIO_ICR_DTIMEOUTC 0x00000008U
5769 #define SDIO_ICR_TXUNDERRC 0x00000010U
5770 #define SDIO_ICR_RXOVERRC 0x00000020U
5771 #define SDIO_ICR_CMDRENDC 0x00000040U
5772 #define SDIO_ICR_CMDSENTC 0x00000080U
5773 #define SDIO_ICR_DATAENDC 0x00000100U
5774 #define SDIO_ICR_STBITERRC 0x00000200U
5775 #define SDIO_ICR_DBCKENDC 0x00000400U
5776 #define SDIO_ICR_SDIOITC 0x00400000U
5777 #define SDIO_ICR_CEATAENDC 0x00800000U
5779 /****************** Bit definition for SDIO_MASK register *******************/
5780 #define SDIO_MASK_CCRCFAILIE 0x00000001U
5781 #define SDIO_MASK_DCRCFAILIE 0x00000002U
5782 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
5783 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
5784 #define SDIO_MASK_TXUNDERRIE 0x00000010U
5785 #define SDIO_MASK_RXOVERRIE 0x00000020U
5786 #define SDIO_MASK_CMDRENDIE 0x00000040U
5787 #define SDIO_MASK_CMDSENTIE 0x00000080U
5788 #define SDIO_MASK_DATAENDIE 0x00000100U
5789 #define SDIO_MASK_STBITERRIE 0x00000200U
5790 #define SDIO_MASK_DBCKENDIE 0x00000400U
5791 #define SDIO_MASK_CMDACTIE 0x00000800U
5792 #define SDIO_MASK_TXACTIE 0x00001000U
5793 #define SDIO_MASK_RXACTIE 0x00002000U
5794 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
5795 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
5796 #define SDIO_MASK_TXFIFOFIE 0x00010000U
5797 #define SDIO_MASK_RXFIFOFIE 0x00020000U
5798 #define SDIO_MASK_TXFIFOEIE 0x00040000U
5799 #define SDIO_MASK_RXFIFOEIE 0x00080000U
5800 #define SDIO_MASK_TXDAVLIE 0x00100000U
5801 #define SDIO_MASK_RXDAVLIE 0x00200000U
5802 #define SDIO_MASK_SDIOITIE 0x00400000U
5803 #define SDIO_MASK_CEATAENDIE 0x00800000U
5805 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5806 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
5808 /****************** Bit definition for SDIO_FIFO register *******************/
5809 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
5811 /******************************************************************************/
5812 /* */
5813 /* Serial Peripheral Interface */
5814 /* */
5815 /******************************************************************************/
5816 /******************* Bit definition for SPI_CR1 register ********************/
5817 #define SPI_CR1_CPHA 0x00000001U
5818 #define SPI_CR1_CPOL 0x00000002U
5819 #define SPI_CR1_MSTR 0x00000004U
5821 #define SPI_CR1_BR 0x00000038U
5822 #define SPI_CR1_BR_0 0x00000008U
5823 #define SPI_CR1_BR_1 0x00000010U
5824 #define SPI_CR1_BR_2 0x00000020U
5826 #define SPI_CR1_SPE 0x00000040U
5827 #define SPI_CR1_LSBFIRST 0x00000080U
5828 #define SPI_CR1_SSI 0x00000100U
5829 #define SPI_CR1_SSM 0x00000200U
5830 #define SPI_CR1_RXONLY 0x00000400U
5831 #define SPI_CR1_DFF 0x00000800U
5832 #define SPI_CR1_CRCNEXT 0x00001000U
5833 #define SPI_CR1_CRCEN 0x00002000U
5834 #define SPI_CR1_BIDIOE 0x00004000U
5835 #define SPI_CR1_BIDIMODE 0x00008000U
5837 /******************* Bit definition for SPI_CR2 register ********************/
5838 #define SPI_CR2_RXDMAEN 0x00000001U
5839 #define SPI_CR2_TXDMAEN 0x00000002U
5840 #define SPI_CR2_SSOE 0x00000004U
5841 #define SPI_CR2_FRF 0x00000010U
5842 #define SPI_CR2_ERRIE 0x00000020U
5843 #define SPI_CR2_RXNEIE 0x00000040U
5844 #define SPI_CR2_TXEIE 0x00000080U
5846 /******************** Bit definition for SPI_SR register ********************/
5847 #define SPI_SR_RXNE 0x00000001U
5848 #define SPI_SR_TXE 0x00000002U
5849 #define SPI_SR_CHSIDE 0x00000004U
5850 #define SPI_SR_UDR 0x00000008U
5851 #define SPI_SR_CRCERR 0x00000010U
5852 #define SPI_SR_MODF 0x00000020U
5853 #define SPI_SR_OVR 0x00000040U
5854 #define SPI_SR_BSY 0x00000080U
5855 #define SPI_SR_FRE 0x00000100U
5857 /******************** Bit definition for SPI_DR register ********************/
5858 #define SPI_DR_DR 0x0000FFFFU
5860 /******************* Bit definition for SPI_CRCPR register ******************/
5861 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
5863 /****************** Bit definition for SPI_RXCRCR register ******************/
5864 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
5866 /****************** Bit definition for SPI_TXCRCR register ******************/
5867 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
5869 /****************** Bit definition for SPI_I2SCFGR register *****************/
5870 #define SPI_I2SCFGR_CHLEN 0x00000001U
5872 #define SPI_I2SCFGR_DATLEN 0x00000006U
5873 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
5874 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
5876 #define SPI_I2SCFGR_CKPOL 0x00000008U
5878 #define SPI_I2SCFGR_I2SSTD 0x00000030U
5879 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
5880 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
5882 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
5884 #define SPI_I2SCFGR_I2SCFG 0x00000300U
5885 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
5886 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
5888 #define SPI_I2SCFGR_I2SE 0x00000400U
5889 #define SPI_I2SCFGR_I2SMOD 0x00000800U
5891 /****************** Bit definition for SPI_I2SPR register *******************/
5892 #define SPI_I2SPR_I2SDIV 0x000000FFU
5893 #define SPI_I2SPR_ODD 0x00000100U
5894 #define SPI_I2SPR_MCKOE 0x00000200U
5896 /******************************************************************************/
5897 /* */
5898 /* SYSCFG */
5899 /* */
5900 /******************************************************************************/
5901 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
5902 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
5903 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
5904 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
5905 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
5906 
5907 /****************** Bit definition for SYSCFG_PMC register ******************/
5908 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
5909 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
5910 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
5911 
5912 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5913 #define SYSCFG_EXTICR1_EXTI0 0x000FU
5914 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
5915 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
5916 #define SYSCFG_EXTICR1_EXTI3 0xF000U
5920 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
5921 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
5922 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
5923 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
5924 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
5925 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
5926 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
5927 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
5928 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
5933 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
5934 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
5935 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
5936 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
5937 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
5938 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
5939 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
5940 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
5941 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
5946 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
5947 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
5948 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
5949 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
5950 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
5951 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
5952 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
5953 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
5954 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
5959 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
5960 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
5961 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
5962 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
5963 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
5964 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
5965 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
5966 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
5967 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
5969 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5970 #define SYSCFG_EXTICR2_EXTI4 0x000FU
5971 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
5972 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
5973 #define SYSCFG_EXTICR2_EXTI7 0xF000U
5977 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
5978 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
5979 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
5980 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
5981 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
5982 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
5983 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
5984 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
5985 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
5990 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
5991 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
5992 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
5993 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
5994 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
5995 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
5996 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
5997 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
5998 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
6003 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
6004 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
6005 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
6006 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
6007 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
6008 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
6009 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
6010 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
6011 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
6016 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
6017 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
6018 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
6019 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
6020 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
6021 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
6022 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
6023 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
6024 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
6027 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6028 #define SYSCFG_EXTICR3_EXTI8 0x000FU
6029 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
6030 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
6031 #define SYSCFG_EXTICR3_EXTI11 0xF000U
6036 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
6037 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
6038 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
6039 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
6040 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
6041 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
6042 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
6043 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
6044 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
6049 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
6050 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
6051 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
6052 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
6053 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
6054 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
6055 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
6056 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
6057 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
6062 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
6063 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
6064 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
6065 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
6066 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
6067 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
6068 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
6069 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
6070 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
6075 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
6076 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
6077 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
6078 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
6079 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
6080 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
6081 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
6082 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
6083 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
6085 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6086 #define SYSCFG_EXTICR4_EXTI12 0x000FU
6087 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
6088 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
6089 #define SYSCFG_EXTICR4_EXTI15 0xF000U
6093 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
6094 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
6095 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
6096 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
6097 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
6098 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
6099 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
6100 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
6105 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
6106 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
6107 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
6108 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
6109 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
6110 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
6111 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
6112 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
6117 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
6118 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
6119 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
6120 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
6121 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
6122 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
6123 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
6124 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
6129 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
6130 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
6131 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
6132 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
6133 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
6134 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
6135 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
6136 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
6138 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6139 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
6140 #define SYSCFG_CMPCR_READY 0x00000100U
6142 /******************************************************************************/
6143 /* */
6144 /* TIM */
6145 /* */
6146 /******************************************************************************/
6147 /******************* Bit definition for TIM_CR1 register ********************/
6148 #define TIM_CR1_CEN 0x0001U
6149 #define TIM_CR1_UDIS 0x0002U
6150 #define TIM_CR1_URS 0x0004U
6151 #define TIM_CR1_OPM 0x0008U
6152 #define TIM_CR1_DIR 0x0010U
6154 #define TIM_CR1_CMS 0x0060U
6155 #define TIM_CR1_CMS_0 0x0020U
6156 #define TIM_CR1_CMS_1 0x0040U
6158 #define TIM_CR1_ARPE 0x0080U
6160 #define TIM_CR1_CKD 0x0300U
6161 #define TIM_CR1_CKD_0 0x0100U
6162 #define TIM_CR1_CKD_1 0x0200U
6164 /******************* Bit definition for TIM_CR2 register ********************/
6165 #define TIM_CR2_CCPC 0x0001U
6166 #define TIM_CR2_CCUS 0x0004U
6167 #define TIM_CR2_CCDS 0x0008U
6169 #define TIM_CR2_MMS 0x0070U
6170 #define TIM_CR2_MMS_0 0x0010U
6171 #define TIM_CR2_MMS_1 0x0020U
6172 #define TIM_CR2_MMS_2 0x0040U
6174 #define TIM_CR2_TI1S 0x0080U
6175 #define TIM_CR2_OIS1 0x0100U
6176 #define TIM_CR2_OIS1N 0x0200U
6177 #define TIM_CR2_OIS2 0x0400U
6178 #define TIM_CR2_OIS2N 0x0800U
6179 #define TIM_CR2_OIS3 0x1000U
6180 #define TIM_CR2_OIS3N 0x2000U
6181 #define TIM_CR2_OIS4 0x4000U
6183 /******************* Bit definition for TIM_SMCR register *******************/
6184 #define TIM_SMCR_SMS 0x0007U
6185 #define TIM_SMCR_SMS_0 0x0001U
6186 #define TIM_SMCR_SMS_1 0x0002U
6187 #define TIM_SMCR_SMS_2 0x0004U
6189 #define TIM_SMCR_TS 0x0070U
6190 #define TIM_SMCR_TS_0 0x0010U
6191 #define TIM_SMCR_TS_1 0x0020U
6192 #define TIM_SMCR_TS_2 0x0040U
6194 #define TIM_SMCR_MSM 0x0080U
6196 #define TIM_SMCR_ETF 0x0F00U
6197 #define TIM_SMCR_ETF_0 0x0100U
6198 #define TIM_SMCR_ETF_1 0x0200U
6199 #define TIM_SMCR_ETF_2 0x0400U
6200 #define TIM_SMCR_ETF_3 0x0800U
6202 #define TIM_SMCR_ETPS 0x3000U
6203 #define TIM_SMCR_ETPS_0 0x1000U
6204 #define TIM_SMCR_ETPS_1 0x2000U
6206 #define TIM_SMCR_ECE 0x4000U
6207 #define TIM_SMCR_ETP 0x8000U
6209 /******************* Bit definition for TIM_DIER register *******************/
6210 #define TIM_DIER_UIE 0x0001U
6211 #define TIM_DIER_CC1IE 0x0002U
6212 #define TIM_DIER_CC2IE 0x0004U
6213 #define TIM_DIER_CC3IE 0x0008U
6214 #define TIM_DIER_CC4IE 0x0010U
6215 #define TIM_DIER_COMIE 0x0020U
6216 #define TIM_DIER_TIE 0x0040U
6217 #define TIM_DIER_BIE 0x0080U
6218 #define TIM_DIER_UDE 0x0100U
6219 #define TIM_DIER_CC1DE 0x0200U
6220 #define TIM_DIER_CC2DE 0x0400U
6221 #define TIM_DIER_CC3DE 0x0800U
6222 #define TIM_DIER_CC4DE 0x1000U
6223 #define TIM_DIER_COMDE 0x2000U
6224 #define TIM_DIER_TDE 0x4000U
6226 /******************** Bit definition for TIM_SR register ********************/
6227 #define TIM_SR_UIF 0x0001U
6228 #define TIM_SR_CC1IF 0x0002U
6229 #define TIM_SR_CC2IF 0x0004U
6230 #define TIM_SR_CC3IF 0x0008U
6231 #define TIM_SR_CC4IF 0x0010U
6232 #define TIM_SR_COMIF 0x0020U
6233 #define TIM_SR_TIF 0x0040U
6234 #define TIM_SR_BIF 0x0080U
6235 #define TIM_SR_CC1OF 0x0200U
6236 #define TIM_SR_CC2OF 0x0400U
6237 #define TIM_SR_CC3OF 0x0800U
6238 #define TIM_SR_CC4OF 0x1000U
6240 /******************* Bit definition for TIM_EGR register ********************/
6241 #define TIM_EGR_UG 0x01U
6242 #define TIM_EGR_CC1G 0x02U
6243 #define TIM_EGR_CC2G 0x04U
6244 #define TIM_EGR_CC3G 0x08U
6245 #define TIM_EGR_CC4G 0x10U
6246 #define TIM_EGR_COMG 0x20U
6247 #define TIM_EGR_TG 0x40U
6248 #define TIM_EGR_BG 0x80U
6250 /****************** Bit definition for TIM_CCMR1 register *******************/
6251 #define TIM_CCMR1_CC1S 0x0003U
6252 #define TIM_CCMR1_CC1S_0 0x0001U
6253 #define TIM_CCMR1_CC1S_1 0x0002U
6255 #define TIM_CCMR1_OC1FE 0x0004U
6256 #define TIM_CCMR1_OC1PE 0x0008U
6258 #define TIM_CCMR1_OC1M 0x0070U
6259 #define TIM_CCMR1_OC1M_0 0x0010U
6260 #define TIM_CCMR1_OC1M_1 0x0020U
6261 #define TIM_CCMR1_OC1M_2 0x0040U
6263 #define TIM_CCMR1_OC1CE 0x0080U
6265 #define TIM_CCMR1_CC2S 0x0300U
6266 #define TIM_CCMR1_CC2S_0 0x0100U
6267 #define TIM_CCMR1_CC2S_1 0x0200U
6269 #define TIM_CCMR1_OC2FE 0x0400U
6270 #define TIM_CCMR1_OC2PE 0x0800U
6272 #define TIM_CCMR1_OC2M 0x7000U
6273 #define TIM_CCMR1_OC2M_0 0x1000U
6274 #define TIM_CCMR1_OC2M_1 0x2000U
6275 #define TIM_CCMR1_OC2M_2 0x4000U
6277 #define TIM_CCMR1_OC2CE 0x8000U
6279 /*----------------------------------------------------------------------------*/
6280 
6281 #define TIM_CCMR1_IC1PSC 0x000CU
6282 #define TIM_CCMR1_IC1PSC_0 0x0004U
6283 #define TIM_CCMR1_IC1PSC_1 0x0008U
6285 #define TIM_CCMR1_IC1F 0x00F0U
6286 #define TIM_CCMR1_IC1F_0 0x0010U
6287 #define TIM_CCMR1_IC1F_1 0x0020U
6288 #define TIM_CCMR1_IC1F_2 0x0040U
6289 #define TIM_CCMR1_IC1F_3 0x0080U
6291 #define TIM_CCMR1_IC2PSC 0x0C00U
6292 #define TIM_CCMR1_IC2PSC_0 0x0400U
6293 #define TIM_CCMR1_IC2PSC_1 0x0800U
6295 #define TIM_CCMR1_IC2F 0xF000U
6296 #define TIM_CCMR1_IC2F_0 0x1000U
6297 #define TIM_CCMR1_IC2F_1 0x2000U
6298 #define TIM_CCMR1_IC2F_2 0x4000U
6299 #define TIM_CCMR1_IC2F_3 0x8000U
6301 /****************** Bit definition for TIM_CCMR2 register *******************/
6302 #define TIM_CCMR2_CC3S 0x0003U
6303 #define TIM_CCMR2_CC3S_0 0x0001U
6304 #define TIM_CCMR2_CC3S_1 0x0002U
6306 #define TIM_CCMR2_OC3FE 0x0004U
6307 #define TIM_CCMR2_OC3PE 0x0008U
6309 #define TIM_CCMR2_OC3M 0x0070U
6310 #define TIM_CCMR2_OC3M_0 0x0010U
6311 #define TIM_CCMR2_OC3M_1 0x0020U
6312 #define TIM_CCMR2_OC3M_2 0x0040U
6314 #define TIM_CCMR2_OC3CE 0x0080U
6316 #define TIM_CCMR2_CC4S 0x0300U
6317 #define TIM_CCMR2_CC4S_0 0x0100U
6318 #define TIM_CCMR2_CC4S_1 0x0200U
6320 #define TIM_CCMR2_OC4FE 0x0400U
6321 #define TIM_CCMR2_OC4PE 0x0800U
6323 #define TIM_CCMR2_OC4M 0x7000U
6324 #define TIM_CCMR2_OC4M_0 0x1000U
6325 #define TIM_CCMR2_OC4M_1 0x2000U
6326 #define TIM_CCMR2_OC4M_2 0x4000U
6328 #define TIM_CCMR2_OC4CE 0x8000U
6330 /*----------------------------------------------------------------------------*/
6331 
6332 #define TIM_CCMR2_IC3PSC 0x000CU
6333 #define TIM_CCMR2_IC3PSC_0 0x0004U
6334 #define TIM_CCMR2_IC3PSC_1 0x0008U
6336 #define TIM_CCMR2_IC3F 0x00F0U
6337 #define TIM_CCMR2_IC3F_0 0x0010U
6338 #define TIM_CCMR2_IC3F_1 0x0020U
6339 #define TIM_CCMR2_IC3F_2 0x0040U
6340 #define TIM_CCMR2_IC3F_3 0x0080U
6342 #define TIM_CCMR2_IC4PSC 0x0C00U
6343 #define TIM_CCMR2_IC4PSC_0 0x0400U
6344 #define TIM_CCMR2_IC4PSC_1 0x0800U
6346 #define TIM_CCMR2_IC4F 0xF000U
6347 #define TIM_CCMR2_IC4F_0 0x1000U
6348 #define TIM_CCMR2_IC4F_1 0x2000U
6349 #define TIM_CCMR2_IC4F_2 0x4000U
6350 #define TIM_CCMR2_IC4F_3 0x8000U
6352 /******************* Bit definition for TIM_CCER register *******************/
6353 #define TIM_CCER_CC1E 0x0001U
6354 #define TIM_CCER_CC1P 0x0002U
6355 #define TIM_CCER_CC1NE 0x0004U
6356 #define TIM_CCER_CC1NP 0x0008U
6357 #define TIM_CCER_CC2E 0x0010U
6358 #define TIM_CCER_CC2P 0x0020U
6359 #define TIM_CCER_CC2NE 0x0040U
6360 #define TIM_CCER_CC2NP 0x0080U
6361 #define TIM_CCER_CC3E 0x0100U
6362 #define TIM_CCER_CC3P 0x0200U
6363 #define TIM_CCER_CC3NE 0x0400U
6364 #define TIM_CCER_CC3NP 0x0800U
6365 #define TIM_CCER_CC4E 0x1000U
6366 #define TIM_CCER_CC4P 0x2000U
6367 #define TIM_CCER_CC4NP 0x8000U
6369 /******************* Bit definition for TIM_CNT register ********************/
6370 #define TIM_CNT_CNT 0xFFFFU
6372 /******************* Bit definition for TIM_PSC register ********************/
6373 #define TIM_PSC_PSC 0xFFFFU
6375 /******************* Bit definition for TIM_ARR register ********************/
6376 #define TIM_ARR_ARR 0xFFFFU
6378 /******************* Bit definition for TIM_RCR register ********************/
6379 #define TIM_RCR_REP 0xFFU
6381 /******************* Bit definition for TIM_CCR1 register *******************/
6382 #define TIM_CCR1_CCR1 0xFFFFU
6384 /******************* Bit definition for TIM_CCR2 register *******************/
6385 #define TIM_CCR2_CCR2 0xFFFFU
6387 /******************* Bit definition for TIM_CCR3 register *******************/
6388 #define TIM_CCR3_CCR3 0xFFFFU
6390 /******************* Bit definition for TIM_CCR4 register *******************/
6391 #define TIM_CCR4_CCR4 0xFFFFU
6393 /******************* Bit definition for TIM_BDTR register *******************/
6394 #define TIM_BDTR_DTG 0x00FFU
6395 #define TIM_BDTR_DTG_0 0x0001U
6396 #define TIM_BDTR_DTG_1 0x0002U
6397 #define TIM_BDTR_DTG_2 0x0004U
6398 #define TIM_BDTR_DTG_3 0x0008U
6399 #define TIM_BDTR_DTG_4 0x0010U
6400 #define TIM_BDTR_DTG_5 0x0020U
6401 #define TIM_BDTR_DTG_6 0x0040U
6402 #define TIM_BDTR_DTG_7 0x0080U
6404 #define TIM_BDTR_LOCK 0x0300U
6405 #define TIM_BDTR_LOCK_0 0x0100U
6406 #define TIM_BDTR_LOCK_1 0x0200U
6408 #define TIM_BDTR_OSSI 0x0400U
6409 #define TIM_BDTR_OSSR 0x0800U
6410 #define TIM_BDTR_BKE 0x1000U
6411 #define TIM_BDTR_BKP 0x2000U
6412 #define TIM_BDTR_AOE 0x4000U
6413 #define TIM_BDTR_MOE 0x8000U
6415 /******************* Bit definition for TIM_DCR register ********************/
6416 #define TIM_DCR_DBA 0x001FU
6417 #define TIM_DCR_DBA_0 0x0001U
6418 #define TIM_DCR_DBA_1 0x0002U
6419 #define TIM_DCR_DBA_2 0x0004U
6420 #define TIM_DCR_DBA_3 0x0008U
6421 #define TIM_DCR_DBA_4 0x0010U
6423 #define TIM_DCR_DBL 0x1F00U
6424 #define TIM_DCR_DBL_0 0x0100U
6425 #define TIM_DCR_DBL_1 0x0200U
6426 #define TIM_DCR_DBL_2 0x0400U
6427 #define TIM_DCR_DBL_3 0x0800U
6428 #define TIM_DCR_DBL_4 0x1000U
6430 /******************* Bit definition for TIM_DMAR register *******************/
6431 #define TIM_DMAR_DMAB 0xFFFFU
6433 /******************* Bit definition for TIM_OR register *********************/
6434 #define TIM_OR_TI4_RMP 0x00C0U
6435 #define TIM_OR_TI4_RMP_0 0x0040U
6436 #define TIM_OR_TI4_RMP_1 0x0080U
6437 #define TIM_OR_ITR1_RMP 0x0C00U
6438 #define TIM_OR_ITR1_RMP_0 0x0400U
6439 #define TIM_OR_ITR1_RMP_1 0x0800U
6442 /******************************************************************************/
6443 /* */
6444 /* Universal Synchronous Asynchronous Receiver Transmitter */
6445 /* */
6446 /******************************************************************************/
6447 /******************* Bit definition for USART_SR register *******************/
6448 #define USART_SR_PE 0x0001U
6449 #define USART_SR_FE 0x0002U
6450 #define USART_SR_NE 0x0004U
6451 #define USART_SR_ORE 0x0008U
6452 #define USART_SR_IDLE 0x0010U
6453 #define USART_SR_RXNE 0x0020U
6454 #define USART_SR_TC 0x0040U
6455 #define USART_SR_TXE 0x0080U
6456 #define USART_SR_LBD 0x0100U
6457 #define USART_SR_CTS 0x0200U
6459 /******************* Bit definition for USART_DR register *******************/
6460 #define USART_DR_DR 0x01FFU
6462 /****************** Bit definition for USART_BRR register *******************/
6463 #define USART_BRR_DIV_Fraction 0x000FU
6464 #define USART_BRR_DIV_Mantissa 0xFFF0U
6466 /****************** Bit definition for USART_CR1 register *******************/
6467 #define USART_CR1_SBK 0x0001U
6468 #define USART_CR1_RWU 0x0002U
6469 #define USART_CR1_RE 0x0004U
6470 #define USART_CR1_TE 0x0008U
6471 #define USART_CR1_IDLEIE 0x0010U
6472 #define USART_CR1_RXNEIE 0x0020U
6473 #define USART_CR1_TCIE 0x0040U
6474 #define USART_CR1_TXEIE 0x0080U
6475 #define USART_CR1_PEIE 0x0100U
6476 #define USART_CR1_PS 0x0200U
6477 #define USART_CR1_PCE 0x0400U
6478 #define USART_CR1_WAKE 0x0800U
6479 #define USART_CR1_M 0x1000U
6480 #define USART_CR1_UE 0x2000U
6481 #define USART_CR1_OVER8 0x8000U
6483 /****************** Bit definition for USART_CR2 register *******************/
6484 #define USART_CR2_ADD 0x000FU
6485 #define USART_CR2_LBDL 0x0020U
6486 #define USART_CR2_LBDIE 0x0040U
6487 #define USART_CR2_LBCL 0x0100U
6488 #define USART_CR2_CPHA 0x0200U
6489 #define USART_CR2_CPOL 0x0400U
6490 #define USART_CR2_CLKEN 0x0800U
6492 #define USART_CR2_STOP 0x3000U
6493 #define USART_CR2_STOP_0 0x1000U
6494 #define USART_CR2_STOP_1 0x2000U
6496 #define USART_CR2_LINEN 0x4000U
6498 /****************** Bit definition for USART_CR3 register *******************/
6499 #define USART_CR3_EIE 0x0001U
6500 #define USART_CR3_IREN 0x0002U
6501 #define USART_CR3_IRLP 0x0004U
6502 #define USART_CR3_HDSEL 0x0008U
6503 #define USART_CR3_NACK 0x0010U
6504 #define USART_CR3_SCEN 0x0020U
6505 #define USART_CR3_DMAR 0x0040U
6506 #define USART_CR3_DMAT 0x0080U
6507 #define USART_CR3_RTSE 0x0100U
6508 #define USART_CR3_CTSE 0x0200U
6509 #define USART_CR3_CTSIE 0x0400U
6510 #define USART_CR3_ONEBIT 0x0800U
6512 /****************** Bit definition for USART_GTPR register ******************/
6513 #define USART_GTPR_PSC 0x00FFU
6514 #define USART_GTPR_PSC_0 0x0001U
6515 #define USART_GTPR_PSC_1 0x0002U
6516 #define USART_GTPR_PSC_2 0x0004U
6517 #define USART_GTPR_PSC_3 0x0008U
6518 #define USART_GTPR_PSC_4 0x0010U
6519 #define USART_GTPR_PSC_5 0x0020U
6520 #define USART_GTPR_PSC_6 0x0040U
6521 #define USART_GTPR_PSC_7 0x0080U
6523 #define USART_GTPR_GT 0xFF00U
6525 /******************************************************************************/
6526 /* */
6527 /* Window WATCHDOG */
6528 /* */
6529 /******************************************************************************/
6530 /******************* Bit definition for WWDG_CR register ********************/
6531 #define WWDG_CR_T 0x7FU
6532 #define WWDG_CR_T_0 0x01U
6533 #define WWDG_CR_T_1 0x02U
6534 #define WWDG_CR_T_2 0x04U
6535 #define WWDG_CR_T_3 0x08U
6536 #define WWDG_CR_T_4 0x10U
6537 #define WWDG_CR_T_5 0x20U
6538 #define WWDG_CR_T_6 0x40U
6539 /* Legacy defines */
6540 #define WWDG_CR_T0 WWDG_CR_T_0
6541 #define WWDG_CR_T1 WWDG_CR_T_1
6542 #define WWDG_CR_T2 WWDG_CR_T_2
6543 #define WWDG_CR_T3 WWDG_CR_T_3
6544 #define WWDG_CR_T4 WWDG_CR_T_4
6545 #define WWDG_CR_T5 WWDG_CR_T_5
6546 #define WWDG_CR_T6 WWDG_CR_T_6
6547 
6548 #define WWDG_CR_WDGA 0x80U
6550 /******************* Bit definition for WWDG_CFR register *******************/
6551 #define WWDG_CFR_W 0x007FU
6552 #define WWDG_CFR_W_0 0x0001U
6553 #define WWDG_CFR_W_1 0x0002U
6554 #define WWDG_CFR_W_2 0x0004U
6555 #define WWDG_CFR_W_3 0x0008U
6556 #define WWDG_CFR_W_4 0x0010U
6557 #define WWDG_CFR_W_5 0x0020U
6558 #define WWDG_CFR_W_6 0x0040U
6559 /* Legacy defines */
6560 #define WWDG_CFR_W0 WWDG_CFR_W_0
6561 #define WWDG_CFR_W1 WWDG_CFR_W_1
6562 #define WWDG_CFR_W2 WWDG_CFR_W_2
6563 #define WWDG_CFR_W3 WWDG_CFR_W_3
6564 #define WWDG_CFR_W4 WWDG_CFR_W_4
6565 #define WWDG_CFR_W5 WWDG_CFR_W_5
6566 #define WWDG_CFR_W6 WWDG_CFR_W_6
6567 
6568 #define WWDG_CFR_WDGTB 0x0180U
6569 #define WWDG_CFR_WDGTB_0 0x0080U
6570 #define WWDG_CFR_WDGTB_1 0x0100U
6571 /* Legacy defines */
6572 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6573 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6574 
6575 #define WWDG_CFR_EWI 0x0200U
6577 /******************* Bit definition for WWDG_SR register ********************/
6578 #define WWDG_SR_EWIF 0x01U
6581 /******************************************************************************/
6582 /* */
6583 /* DBG */
6584 /* */
6585 /******************************************************************************/
6586 /******************** Bit definition for DBGMCU_IDCODE register *************/
6587 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
6588 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
6589 
6590 /******************** Bit definition for DBGMCU_CR register *****************/
6591 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
6592 #define DBGMCU_CR_DBG_STOP 0x00000002U
6593 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
6594 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
6595 
6596 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
6597 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
6598 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
6600 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6601 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
6602 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
6603 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
6604 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
6605 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
6606 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
6607 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
6608 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
6609 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
6610 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
6611 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
6612 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
6613 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
6614 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
6615 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
6616 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
6617 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
6618 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
6619 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6620 
6621 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6622 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
6623 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
6624 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
6625 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
6626 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
6627 
6628 /******************************************************************************/
6629 /* */
6630 /* USB_OTG */
6631 /* */
6632 /******************************************************************************/
6633 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
6634 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
6635 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
6636 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
6637 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
6638 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
6639 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
6640 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
6641 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
6642 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
6643 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
6645 /******************** Bit definition forUSB_OTG_HCFG register ********************/
6646 
6647 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
6648 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
6649 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
6650 #define USB_OTG_HCFG_FSLSS 0x00000004U
6652 /******************** Bit definition forUSB_OTG_DCFG register ********************/
6653 
6654 #define USB_OTG_DCFG_DSPD 0x00000003U
6655 #define USB_OTG_DCFG_DSPD_0 0x00000001U
6656 #define USB_OTG_DCFG_DSPD_1 0x00000002U
6657 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
6659 #define USB_OTG_DCFG_DAD 0x000007F0U
6660 #define USB_OTG_DCFG_DAD_0 0x00000010U
6661 #define USB_OTG_DCFG_DAD_1 0x00000020U
6662 #define USB_OTG_DCFG_DAD_2 0x00000040U
6663 #define USB_OTG_DCFG_DAD_3 0x00000080U
6664 #define USB_OTG_DCFG_DAD_4 0x00000100U
6665 #define USB_OTG_DCFG_DAD_5 0x00000200U
6666 #define USB_OTG_DCFG_DAD_6 0x00000400U
6668 #define USB_OTG_DCFG_PFIVL 0x00001800U
6669 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
6670 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
6672 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
6673 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
6674 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
6676 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
6677 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
6678 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
6679 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
6681 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
6682 #define USB_OTG_GOTGINT_SEDET 0x00000004U
6683 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
6684 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
6685 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
6686 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
6687 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
6689 /******************** Bit definition forUSB_OTG_DCTL register ********************/
6690 #define USB_OTG_DCTL_RWUSIG 0x00000001U
6691 #define USB_OTG_DCTL_SDIS 0x00000002U
6692 #define USB_OTG_DCTL_GINSTS 0x00000004U
6693 #define USB_OTG_DCTL_GONSTS 0x00000008U
6695 #define USB_OTG_DCTL_TCTL 0x00000070U
6696 #define USB_OTG_DCTL_TCTL_0 0x00000010U
6697 #define USB_OTG_DCTL_TCTL_1 0x00000020U
6698 #define USB_OTG_DCTL_TCTL_2 0x00000040U
6699 #define USB_OTG_DCTL_SGINAK 0x00000080U
6700 #define USB_OTG_DCTL_CGINAK 0x00000100U
6701 #define USB_OTG_DCTL_SGONAK 0x00000200U
6702 #define USB_OTG_DCTL_CGONAK 0x00000400U
6703 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
6705 /******************** Bit definition forUSB_OTG_HFIR register ********************/
6706 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
6708 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
6709 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
6710 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
6712 /******************** Bit definition forUSB_OTG_DSTS register ********************/
6713 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
6715 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
6716 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
6717 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
6718 #define USB_OTG_DSTS_EERR 0x00000008U
6719 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
6721 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
6722 #define USB_OTG_GAHBCFG_GINT 0x00000001U
6724 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
6725 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
6726 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
6727 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
6728 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
6729 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
6730 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
6731 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
6733 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
6734 
6735 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
6736 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
6737 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
6738 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
6739 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
6740 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
6741 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
6743 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
6744 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
6745 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
6746 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
6747 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
6748 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
6749 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
6750 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
6751 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
6752 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
6753 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
6754 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
6755 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
6756 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
6757 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
6758 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
6759 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
6760 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
6762 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
6763 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
6764 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
6765 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
6766 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
6767 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
6769 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
6770 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
6771 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
6772 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
6773 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
6774 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
6775 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
6776 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
6778 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
6779 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
6780 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
6781 #define USB_OTG_DIEPMSK_TOM 0x00000008U
6782 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
6783 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
6784 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
6785 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
6786 #define USB_OTG_DIEPMSK_BIM 0x00000200U
6788 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
6789 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
6791 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
6792 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
6793 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
6794 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
6795 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
6796 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
6797 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
6798 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
6799 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
6801 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
6802 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
6803 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
6804 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
6805 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
6806 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
6807 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
6808 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
6809 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
6811 /******************** Bit definition forUSB_OTG_HAINT register ********************/
6812 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
6814 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
6815 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
6816 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
6817 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
6818 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
6819 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
6820 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
6821 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
6823 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
6824 #define USB_OTG_GINTSTS_CMOD 0x00000001U
6825 #define USB_OTG_GINTSTS_MMIS 0x00000002U
6826 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
6827 #define USB_OTG_GINTSTS_SOF 0x00000008U
6828 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
6829 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
6830 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
6831 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
6832 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
6833 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
6834 #define USB_OTG_GINTSTS_USBRST 0x00001000U
6835 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
6836 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
6837 #define USB_OTG_GINTSTS_EOPF 0x00008000U
6838 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
6839 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
6840 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
6841 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
6842 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
6843 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
6844 #define USB_OTG_GINTSTS_HCINT 0x02000000U
6845 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
6846 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
6847 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
6848 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
6849 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
6851 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
6852 #define USB_OTG_GINTMSK_MMISM 0x00000002U
6853 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
6854 #define USB_OTG_GINTMSK_SOFM 0x00000008U
6855 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
6856 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
6857 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
6858 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
6859 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
6860 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
6861 #define USB_OTG_GINTMSK_USBRST 0x00001000U
6862 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
6863 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
6864 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
6865 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
6866 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
6867 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
6868 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
6869 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
6870 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
6871 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
6872 #define USB_OTG_GINTMSK_HCIM 0x02000000U
6873 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
6874 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
6875 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
6876 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
6877 #define USB_OTG_GINTMSK_WUIM 0x80000000U
6879 /******************** Bit definition forUSB_OTG_DAINT register ********************/
6880 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
6881 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
6883 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
6884 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
6886 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
6887 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
6888 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
6889 #define USB_OTG_GRXSTSP_DPID 0x00018000U
6890 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
6892 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
6893 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
6894 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
6896 /******************** Bit definition for OTG register ********************/
6897 
6898 #define USB_OTG_CHNUM 0x0000000FU
6899 #define USB_OTG_CHNUM_0 0x00000001U
6900 #define USB_OTG_CHNUM_1 0x00000002U
6901 #define USB_OTG_CHNUM_2 0x00000004U
6902 #define USB_OTG_CHNUM_3 0x00000008U
6903 #define USB_OTG_BCNT 0x00007FF0U
6905 #define USB_OTG_DPID 0x00018000U
6906 #define USB_OTG_DPID_0 0x00008000U
6907 #define USB_OTG_DPID_1 0x00010000U
6909 #define USB_OTG_PKTSTS 0x001E0000U
6910 #define USB_OTG_PKTSTS_0 0x00020000U
6911 #define USB_OTG_PKTSTS_1 0x00040000U
6912 #define USB_OTG_PKTSTS_2 0x00080000U
6913 #define USB_OTG_PKTSTS_3 0x00100000U
6915 #define USB_OTG_EPNUM 0x0000000FU
6916 #define USB_OTG_EPNUM_0 0x00000001U
6917 #define USB_OTG_EPNUM_1 0x00000002U
6918 #define USB_OTG_EPNUM_2 0x00000004U
6919 #define USB_OTG_EPNUM_3 0x00000008U
6921 #define USB_OTG_FRMNUM 0x01E00000U
6922 #define USB_OTG_FRMNUM_0 0x00200000U
6923 #define USB_OTG_FRMNUM_1 0x00400000U
6924 #define USB_OTG_FRMNUM_2 0x00800000U
6925 #define USB_OTG_FRMNUM_3 0x01000000U
6927 /******************** Bit definition for OTG register ********************/
6928 
6929 #define USB_OTG_CHNUM 0x0000000FU
6930 #define USB_OTG_CHNUM_0 0x00000001U
6931 #define USB_OTG_CHNUM_1 0x00000002U
6932 #define USB_OTG_CHNUM_2 0x00000004U
6933 #define USB_OTG_CHNUM_3 0x00000008U
6934 #define USB_OTG_BCNT 0x00007FF0U
6936 #define USB_OTG_DPID 0x00018000U
6937 #define USB_OTG_DPID_0 0x00008000U
6938 #define USB_OTG_DPID_1 0x00010000U
6940 #define USB_OTG_PKTSTS 0x001E0000U
6941 #define USB_OTG_PKTSTS_0 0x00020000U
6942 #define USB_OTG_PKTSTS_1 0x00040000U
6943 #define USB_OTG_PKTSTS_2 0x00080000U
6944 #define USB_OTG_PKTSTS_3 0x00100000U
6946 #define USB_OTG_EPNUM 0x0000000FU
6947 #define USB_OTG_EPNUM_0 0x00000001U
6948 #define USB_OTG_EPNUM_1 0x00000002U
6949 #define USB_OTG_EPNUM_2 0x00000004U
6950 #define USB_OTG_EPNUM_3 0x00000008U
6952 #define USB_OTG_FRMNUM 0x01E00000U
6953 #define USB_OTG_FRMNUM_0 0x00200000U
6954 #define USB_OTG_FRMNUM_1 0x00400000U
6955 #define USB_OTG_FRMNUM_2 0x00800000U
6956 #define USB_OTG_FRMNUM_3 0x01000000U
6958 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
6959 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
6961 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
6962 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
6964 /******************** Bit definition for OTG register ********************/
6965 #define USB_OTG_NPTXFSA 0x0000FFFFU
6966 #define USB_OTG_NPTXFD 0xFFFF0000U
6967 #define USB_OTG_TX0FSA 0x0000FFFFU
6968 #define USB_OTG_TX0FD 0xFFFF0000U
6970 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
6971 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
6973 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
6974 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
6976 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
6977 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
6978 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
6979 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
6980 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
6981 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
6982 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
6983 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
6984 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
6986 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
6987 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
6988 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
6989 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
6990 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
6991 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
6992 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
6993 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
6995 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
6996 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
6997 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
6999 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
7000 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
7001 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
7002 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
7003 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
7004 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
7005 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
7006 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
7007 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
7008 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
7009 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
7011 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
7012 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
7013 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
7014 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
7015 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
7016 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
7017 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
7018 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
7019 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
7020 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
7021 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
7023 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
7024 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
7026 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
7027 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
7028 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
7030 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
7031 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
7032 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
7033 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
7034 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
7035 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
7036 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
7038 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
7039 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
7040 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
7042 /******************** Bit definition forUSB_OTG_CID register ********************/
7043 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
7045 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
7046 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
7047 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
7048 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
7049 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
7050 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
7051 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
7052 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
7053 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
7054 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
7056 /******************** Bit definition forUSB_OTG_HPRT register ********************/
7057 #define USB_OTG_HPRT_PCSTS 0x00000001U
7058 #define USB_OTG_HPRT_PCDET 0x00000002U
7059 #define USB_OTG_HPRT_PENA 0x00000004U
7060 #define USB_OTG_HPRT_PENCHNG 0x00000008U
7061 #define USB_OTG_HPRT_POCA 0x00000010U
7062 #define USB_OTG_HPRT_POCCHNG 0x00000020U
7063 #define USB_OTG_HPRT_PRES 0x00000040U
7064 #define USB_OTG_HPRT_PSUSP 0x00000080U
7065 #define USB_OTG_HPRT_PRST 0x00000100U
7067 #define USB_OTG_HPRT_PLSTS 0x00000C00U
7068 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
7069 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
7070 #define USB_OTG_HPRT_PPWR 0x00001000U
7072 #define USB_OTG_HPRT_PTCTL 0x0001E000U
7073 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
7074 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
7075 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
7076 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
7078 #define USB_OTG_HPRT_PSPD 0x00060000U
7079 #define USB_OTG_HPRT_PSPD_0 0x00020000U
7080 #define USB_OTG_HPRT_PSPD_1 0x00040000U
7082 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
7083 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
7084 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
7085 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
7086 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
7087 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
7088 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
7089 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
7090 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
7091 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
7092 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
7093 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
7095 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
7096 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
7097 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
7099 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
7100 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
7101 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
7102 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
7103 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
7105 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
7106 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
7107 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
7108 #define USB_OTG_DIEPCTL_STALL 0x00200000U
7110 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
7111 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
7112 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
7113 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
7114 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
7115 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
7116 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
7117 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
7118 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
7119 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
7120 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
7122 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
7123 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
7125 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
7126 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
7127 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
7128 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
7129 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
7130 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
7131 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
7133 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
7134 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
7135 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
7137 #define USB_OTG_HCCHAR_MC 0x00300000U
7138 #define USB_OTG_HCCHAR_MC_0 0x00100000U
7139 #define USB_OTG_HCCHAR_MC_1 0x00200000U
7141 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
7142 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
7143 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
7144 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
7145 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
7146 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
7147 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
7148 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
7149 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
7150 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
7151 #define USB_OTG_HCCHAR_CHENA 0x80000000U
7153 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
7154 
7155 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
7156 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
7157 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
7158 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
7159 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
7160 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
7161 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
7162 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
7164 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
7165 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
7166 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
7167 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
7168 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
7169 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
7170 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
7171 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
7173 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
7174 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
7175 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
7176 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
7177 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
7179 /******************** Bit definition forUSB_OTG_HCINT register ********************/
7180 #define USB_OTG_HCINT_XFRC 0x00000001U
7181 #define USB_OTG_HCINT_CHH 0x00000002U
7182 #define USB_OTG_HCINT_AHBERR 0x00000004U
7183 #define USB_OTG_HCINT_STALL 0x00000008U
7184 #define USB_OTG_HCINT_NAK 0x00000010U
7185 #define USB_OTG_HCINT_ACK 0x00000020U
7186 #define USB_OTG_HCINT_NYET 0x00000040U
7187 #define USB_OTG_HCINT_TXERR 0x00000080U
7188 #define USB_OTG_HCINT_BBERR 0x00000100U
7189 #define USB_OTG_HCINT_FRMOR 0x00000200U
7190 #define USB_OTG_HCINT_DTERR 0x00000400U
7192 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
7193 #define USB_OTG_DIEPINT_XFRC 0x00000001U
7194 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
7195 #define USB_OTG_DIEPINT_TOC 0x00000008U
7196 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
7197 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
7198 #define USB_OTG_DIEPINT_TXFE 0x00000080U
7199 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
7200 #define USB_OTG_DIEPINT_BNA 0x00000200U
7201 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
7202 #define USB_OTG_DIEPINT_BERR 0x00001000U
7203 #define USB_OTG_DIEPINT_NAK 0x00002000U
7205 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
7206 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
7207 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
7208 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
7209 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
7210 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
7211 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
7212 #define USB_OTG_HCINTMSK_NYET 0x00000040U
7213 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
7214 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
7215 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
7216 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
7218 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
7219 
7220 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
7221 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
7222 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
7223 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
7224 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
7225 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
7226 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
7227 #define USB_OTG_HCTSIZ_DPID 0x60000000U
7228 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
7229 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
7231 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
7232 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
7234 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
7235 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
7237 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
7238 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
7240 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
7241 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
7242 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
7244 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
7245 
7246 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
7247 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
7248 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
7249 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
7250 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
7251 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
7252 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
7253 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
7254 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
7255 #define USB_OTG_DOEPCTL_STALL 0x00200000U
7256 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
7257 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
7258 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
7259 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
7261 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
7262 #define USB_OTG_DOEPINT_XFRC 0x00000001U
7263 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
7264 #define USB_OTG_DOEPINT_STUP 0x00000008U
7265 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
7266 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
7267 #define USB_OTG_DOEPINT_NYET 0x00004000U
7269 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
7270 
7271 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
7272 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
7274 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
7275 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
7276 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
7278 /******************** Bit definition for PCGCCTL register ********************/
7279 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
7280 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
7281 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
7295 /******************************* ADC Instances ********************************/
7296 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
7297  ((INSTANCE) == ADC2) || \
7298  ((INSTANCE) == ADC3))
7299 
7300 /******************************* CAN Instances ********************************/
7301 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
7302  ((INSTANCE) == CAN2))
7303 
7304 /******************************* CRC Instances ********************************/
7305 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7306 
7307 /******************************* DAC Instances ********************************/
7308 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
7309 
7310 /******************************** DMA Instances *******************************/
7311 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7312  ((INSTANCE) == DMA1_Stream1) || \
7313  ((INSTANCE) == DMA1_Stream2) || \
7314  ((INSTANCE) == DMA1_Stream3) || \
7315  ((INSTANCE) == DMA1_Stream4) || \
7316  ((INSTANCE) == DMA1_Stream5) || \
7317  ((INSTANCE) == DMA1_Stream6) || \
7318  ((INSTANCE) == DMA1_Stream7) || \
7319  ((INSTANCE) == DMA2_Stream0) || \
7320  ((INSTANCE) == DMA2_Stream1) || \
7321  ((INSTANCE) == DMA2_Stream2) || \
7322  ((INSTANCE) == DMA2_Stream3) || \
7323  ((INSTANCE) == DMA2_Stream4) || \
7324  ((INSTANCE) == DMA2_Stream5) || \
7325  ((INSTANCE) == DMA2_Stream6) || \
7326  ((INSTANCE) == DMA2_Stream7))
7327 
7328 /******************************* GPIO Instances *******************************/
7329 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7330  ((INSTANCE) == GPIOB) || \
7331  ((INSTANCE) == GPIOC) || \
7332  ((INSTANCE) == GPIOD) || \
7333  ((INSTANCE) == GPIOE) || \
7334  ((INSTANCE) == GPIOF) || \
7335  ((INSTANCE) == GPIOG) || \
7336  ((INSTANCE) == GPIOH) || \
7337  ((INSTANCE) == GPIOI))
7338 
7339 /******************************** I2C Instances *******************************/
7340 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7341  ((INSTANCE) == I2C2) || \
7342  ((INSTANCE) == I2C3))
7343 
7344 /******************************** I2S Instances *******************************/
7345 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
7346  ((INSTANCE) == SPI3))
7347 
7348 /*************************** I2S Extended Instances ***************************/
7349 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
7350  ((INSTANCE) == SPI3) || \
7351  ((INSTANCE) == I2S2ext) || \
7352  ((INSTANCE) == I2S3ext))
7353 
7354 /******************************* RNG Instances ********************************/
7355 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
7356 
7357 /****************************** RTC Instances *********************************/
7358 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7359 
7360 /******************************** SPI Instances *******************************/
7361 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7362  ((INSTANCE) == SPI2) || \
7363  ((INSTANCE) == SPI3))
7364 
7365 /*************************** SPI Extended Instances ***************************/
7366 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
7367  ((INSTANCE) == SPI2) || \
7368  ((INSTANCE) == SPI3) || \
7369  ((INSTANCE) == I2S2ext) || \
7370  ((INSTANCE) == I2S3ext))
7371 
7372 /****************** TIM Instances : All supported instances *******************/
7373 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7374  ((INSTANCE) == TIM2) || \
7375  ((INSTANCE) == TIM3) || \
7376  ((INSTANCE) == TIM4) || \
7377  ((INSTANCE) == TIM5) || \
7378  ((INSTANCE) == TIM6) || \
7379  ((INSTANCE) == TIM7) || \
7380  ((INSTANCE) == TIM8) || \
7381  ((INSTANCE) == TIM9) || \
7382  ((INSTANCE) == TIM10) || \
7383  ((INSTANCE) == TIM11) || \
7384  ((INSTANCE) == TIM12) || \
7385  ((INSTANCE) == TIM13) || \
7386  ((INSTANCE) == TIM14))
7387 
7388 /************* TIM Instances : at least 1 capture/compare channel *************/
7389 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7390  ((INSTANCE) == TIM2) || \
7391  ((INSTANCE) == TIM3) || \
7392  ((INSTANCE) == TIM4) || \
7393  ((INSTANCE) == TIM5) || \
7394  ((INSTANCE) == TIM8) || \
7395  ((INSTANCE) == TIM9) || \
7396  ((INSTANCE) == TIM10) || \
7397  ((INSTANCE) == TIM11) || \
7398  ((INSTANCE) == TIM12) || \
7399  ((INSTANCE) == TIM13) || \
7400  ((INSTANCE) == TIM14))
7401 
7402 /************ TIM Instances : at least 2 capture/compare channels *************/
7403 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7404  ((INSTANCE) == TIM2) || \
7405  ((INSTANCE) == TIM3) || \
7406  ((INSTANCE) == TIM4) || \
7407  ((INSTANCE) == TIM5) || \
7408  ((INSTANCE) == TIM8) || \
7409  ((INSTANCE) == TIM9) || \
7410  ((INSTANCE) == TIM12))
7411 
7412 /************ TIM Instances : at least 3 capture/compare channels *************/
7413 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7414  ((INSTANCE) == TIM2) || \
7415  ((INSTANCE) == TIM3) || \
7416  ((INSTANCE) == TIM4) || \
7417  ((INSTANCE) == TIM5) || \
7418  ((INSTANCE) == TIM8))
7419 
7420 /************ TIM Instances : at least 4 capture/compare channels *************/
7421 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7422  ((INSTANCE) == TIM2) || \
7423  ((INSTANCE) == TIM3) || \
7424  ((INSTANCE) == TIM4) || \
7425  ((INSTANCE) == TIM5) || \
7426  ((INSTANCE) == TIM8))
7427 
7428 /******************** TIM Instances : Advanced-control timers *****************/
7429 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7430  ((INSTANCE) == TIM8))
7431 
7432 /******************* TIM Instances : Timer input XOR function *****************/
7433 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7434  ((INSTANCE) == TIM2) || \
7435  ((INSTANCE) == TIM3) || \
7436  ((INSTANCE) == TIM4) || \
7437  ((INSTANCE) == TIM5) || \
7438  ((INSTANCE) == TIM8))
7439 
7440 /****************** TIM Instances : DMA requests generation (UDE) *************/
7441 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7442  ((INSTANCE) == TIM2) || \
7443  ((INSTANCE) == TIM3) || \
7444  ((INSTANCE) == TIM4) || \
7445  ((INSTANCE) == TIM5) || \
7446  ((INSTANCE) == TIM6) || \
7447  ((INSTANCE) == TIM7) || \
7448  ((INSTANCE) == TIM8))
7449 
7450 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
7451 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7452  ((INSTANCE) == TIM2) || \
7453  ((INSTANCE) == TIM3) || \
7454  ((INSTANCE) == TIM4) || \
7455  ((INSTANCE) == TIM5) || \
7456  ((INSTANCE) == TIM8))
7457 
7458 /************ TIM Instances : DMA requests generation (COMDE) *****************/
7459 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7460  ((INSTANCE) == TIM2) || \
7461  ((INSTANCE) == TIM3) || \
7462  ((INSTANCE) == TIM4) || \
7463  ((INSTANCE) == TIM5) || \
7464  ((INSTANCE) == TIM8))
7465 
7466 /******************** TIM Instances : DMA burst feature ***********************/
7467 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7468  ((INSTANCE) == TIM2) || \
7469  ((INSTANCE) == TIM3) || \
7470  ((INSTANCE) == TIM4) || \
7471  ((INSTANCE) == TIM5) || \
7472  ((INSTANCE) == TIM8))
7473 
7474 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
7475 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7476  ((INSTANCE) == TIM2) || \
7477  ((INSTANCE) == TIM3) || \
7478  ((INSTANCE) == TIM4) || \
7479  ((INSTANCE) == TIM5) || \
7480  ((INSTANCE) == TIM6) || \
7481  ((INSTANCE) == TIM7) || \
7482  ((INSTANCE) == TIM8) || \
7483  ((INSTANCE) == TIM9) || \
7484  ((INSTANCE) == TIM12))
7485 
7486 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7487 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7488  ((INSTANCE) == TIM2) || \
7489  ((INSTANCE) == TIM3) || \
7490  ((INSTANCE) == TIM4) || \
7491  ((INSTANCE) == TIM5) || \
7492  ((INSTANCE) == TIM8) || \
7493  ((INSTANCE) == TIM9) || \
7494  ((INSTANCE) == TIM12))
7495 
7496 /********************** TIM Instances : 32 bit Counter ************************/
7497 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
7498  ((INSTANCE) == TIM5))
7499 
7500 /***************** TIM Instances : external trigger input availabe ************/
7501 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7502  ((INSTANCE) == TIM2) || \
7503  ((INSTANCE) == TIM3) || \
7504  ((INSTANCE) == TIM4) || \
7505  ((INSTANCE) == TIM5) || \
7506  ((INSTANCE) == TIM8))
7507 
7508 /****************** TIM Instances : remapping capability **********************/
7509 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7510  ((INSTANCE) == TIM5) || \
7511  ((INSTANCE) == TIM11))
7512 
7513 /******************* TIM Instances : output(s) available **********************/
7514 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7515  ((((INSTANCE) == TIM1) && \
7516  (((CHANNEL) == TIM_CHANNEL_1) || \
7517  ((CHANNEL) == TIM_CHANNEL_2) || \
7518  ((CHANNEL) == TIM_CHANNEL_3) || \
7519  ((CHANNEL) == TIM_CHANNEL_4))) \
7520  || \
7521  (((INSTANCE) == TIM2) && \
7522  (((CHANNEL) == TIM_CHANNEL_1) || \
7523  ((CHANNEL) == TIM_CHANNEL_2) || \
7524  ((CHANNEL) == TIM_CHANNEL_3) || \
7525  ((CHANNEL) == TIM_CHANNEL_4))) \
7526  || \
7527  (((INSTANCE) == TIM3) && \
7528  (((CHANNEL) == TIM_CHANNEL_1) || \
7529  ((CHANNEL) == TIM_CHANNEL_2) || \
7530  ((CHANNEL) == TIM_CHANNEL_3) || \
7531  ((CHANNEL) == TIM_CHANNEL_4))) \
7532  || \
7533  (((INSTANCE) == TIM4) && \
7534  (((CHANNEL) == TIM_CHANNEL_1) || \
7535  ((CHANNEL) == TIM_CHANNEL_2) || \
7536  ((CHANNEL) == TIM_CHANNEL_3) || \
7537  ((CHANNEL) == TIM_CHANNEL_4))) \
7538  || \
7539  (((INSTANCE) == TIM5) && \
7540  (((CHANNEL) == TIM_CHANNEL_1) || \
7541  ((CHANNEL) == TIM_CHANNEL_2) || \
7542  ((CHANNEL) == TIM_CHANNEL_3) || \
7543  ((CHANNEL) == TIM_CHANNEL_4))) \
7544  || \
7545  (((INSTANCE) == TIM8) && \
7546  (((CHANNEL) == TIM_CHANNEL_1) || \
7547  ((CHANNEL) == TIM_CHANNEL_2) || \
7548  ((CHANNEL) == TIM_CHANNEL_3) || \
7549  ((CHANNEL) == TIM_CHANNEL_4))) \
7550  || \
7551  (((INSTANCE) == TIM9) && \
7552  (((CHANNEL) == TIM_CHANNEL_1) || \
7553  ((CHANNEL) == TIM_CHANNEL_2))) \
7554  || \
7555  (((INSTANCE) == TIM10) && \
7556  (((CHANNEL) == TIM_CHANNEL_1))) \
7557  || \
7558  (((INSTANCE) == TIM11) && \
7559  (((CHANNEL) == TIM_CHANNEL_1))) \
7560  || \
7561  (((INSTANCE) == TIM12) && \
7562  (((CHANNEL) == TIM_CHANNEL_1) || \
7563  ((CHANNEL) == TIM_CHANNEL_2))) \
7564  || \
7565  (((INSTANCE) == TIM13) && \
7566  (((CHANNEL) == TIM_CHANNEL_1))) \
7567  || \
7568  (((INSTANCE) == TIM14) && \
7569  (((CHANNEL) == TIM_CHANNEL_1))))
7570 
7571 /************ TIM Instances : complementary output(s) available ***************/
7572 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
7573  ((((INSTANCE) == TIM1) && \
7574  (((CHANNEL) == TIM_CHANNEL_1) || \
7575  ((CHANNEL) == TIM_CHANNEL_2) || \
7576  ((CHANNEL) == TIM_CHANNEL_3))) \
7577  || \
7578  (((INSTANCE) == TIM8) && \
7579  (((CHANNEL) == TIM_CHANNEL_1) || \
7580  ((CHANNEL) == TIM_CHANNEL_2) || \
7581  ((CHANNEL) == TIM_CHANNEL_3))))
7582 
7583 /******************** USART Instances : Synchronous mode **********************/
7584 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7585  ((INSTANCE) == USART2) || \
7586  ((INSTANCE) == USART3) || \
7587  ((INSTANCE) == USART6))
7588 
7589 /******************** UART Instances : Asynchronous mode **********************/
7590 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7591  ((INSTANCE) == USART2) || \
7592  ((INSTANCE) == USART3) || \
7593  ((INSTANCE) == UART4) || \
7594  ((INSTANCE) == UART5) || \
7595  ((INSTANCE) == USART6))
7596 
7597 /****************** UART Instances : Hardware Flow control ********************/
7598 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7599  ((INSTANCE) == USART2) || \
7600  ((INSTANCE) == USART3) || \
7601  ((INSTANCE) == USART6))
7602 
7603 /********************* UART Instances : Smard card mode ***********************/
7604 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7605  ((INSTANCE) == USART2) || \
7606  ((INSTANCE) == USART3) || \
7607  ((INSTANCE) == USART6))
7608 
7609 /*********************** UART Instances : IRDA mode ***************************/
7610 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7611  ((INSTANCE) == USART2) || \
7612  ((INSTANCE) == USART3) || \
7613  ((INSTANCE) == UART4) || \
7614  ((INSTANCE) == UART5) || \
7615  ((INSTANCE) == USART6))
7616 
7617 /*********************** PCD Instances ****************************************/
7618 /*********************** PCD Instances ****************************************/
7619 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
7620  ((INSTANCE) == USB_OTG_HS))
7621 
7622 /*********************** HCD Instances ****************************************/
7623 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
7624  ((INSTANCE) == USB_OTG_HS))
7625 
7626 /*********************** HCD Instances ****************************************/
7627 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
7628  ((INSTANCE) == USB_OTG_HS))
7629 
7630 /****************************** IWDG Instances ********************************/
7631 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
7632 
7633 /****************************** WWDG Instances ********************************/
7634 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
7635 
7636 /****************************** SDIO Instances ********************************/
7637 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
7638 
7639 /****************************** USB Exported Constants ************************/
7640 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
7641 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
7642 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
7643 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
7644 
7645 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
7646 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
7647 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
7648 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
7649 
7650 /******************************************************************************/
7651 /* For a painless codes migration between the STM32F4xx device product */
7652 /* lines, the aliases defined below are put in place to overcome the */
7653 /* differences in the interrupt handlers and IRQn definitions. */
7654 /* No need to update developed interrupt code when moving across */
7655 /* product lines within the same STM32F4 Family */
7656 /******************************************************************************/
7657 
7658 /* Aliases for __IRQn */
7659 #define FMC_IRQn FSMC_IRQn
7660 
7661 /* Aliases for __IRQHandler */
7662 #define FMC_IRQHandler FSMC_IRQHandler
7663 
7676 #ifdef __cplusplus
7677 }
7678 #endif /* __cplusplus */
7679 
7680 #endif /* __STM32F415xx_H */
7681 
7682 
7683 
7684 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
CRYP_TypeDef::K0LR
__IO uint32_t K0LR
Definition: stm32f415xx.h:718
CRYP_TypeDef::IMSCR
__IO uint32_t IMSCR
Definition: stm32f415xx.h:715
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
HASH_TypeDef::STR
__IO uint32_t STR
Definition: stm32f415xx.h:756
TAMP_STAMP_IRQn
Definition: stm32f415xx.h:99
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f405xx.h:395
HASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f415xx.h:759
TIM2_IRQn
Definition: stm32f415xx.h:125
UART4_IRQn
Definition: stm32f415xx.h:149
UART5_IRQn
Definition: stm32f415xx.h:150
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f415xx.h:123
EXTI2_IRQn
Definition: stm32f415xx.h:105
EXTI4_IRQn
Definition: stm32f415xx.h:107
USART1_IRQn
Definition: stm32f415xx.h:134
CRYP_TypeDef::CSGCM5R
__IO uint32_t CSGCM5R
Definition: stm32f415xx.h:743
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
CRYP_TypeDef::IV1RR
__IO uint32_t IV1RR
Definition: stm32f415xx.h:729
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f415xx.h:142
TIM4_IRQn
Definition: stm32f415xx.h:127
RTC_Alarm_IRQn
Definition: stm32f415xx.h:138
CRYP_TypeDef::CSGCM0R
__IO uint32_t CSGCM0R
Definition: stm32f415xx.h:738
CAN2_SCE_IRQn
Definition: stm32f415xx.h:161
CRYP_IRQn
Definition: stm32f415xx.h:173
PendSV_IRQn
Definition: stm32f415xx.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f415xx.h:100
CAN1_RX1_IRQn
Definition: stm32f415xx.h:118
CRYP_TypeDef::CSGCM7R
__IO uint32_t CSGCM7R
Definition: stm32f415xx.h:745
TIM6_DAC_IRQn
Definition: stm32f415xx.h:151
CAN1_TX_IRQn
Definition: stm32f415xx.h:116
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f415xx.h:132
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
OTG_FS_WKUP_IRQn
Definition: stm32f415xx.h:139
DMA_TypeDef
Definition: stm32f401xc.h:243
DMA1_Stream2_IRQn
Definition: stm32f415xx.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f415xx.h:133
CRYP_TypeDef::DMACR
__IO uint32_t DMACR
Definition: stm32f415xx.h:714
CRYP_TypeDef::CSGCM2R
__IO uint32_t CSGCM2R
Definition: stm32f415xx.h:740
__I
#define __I
Definition: core_cm0.h:210
DMA2_Stream5_IRQn
Definition: stm32f415xx.h:163
ADC_IRQn
Definition: stm32f415xx.h:115
CAN1_RX0_IRQn
Definition: stm32f415xx.h:117
RCC_IRQn
Definition: stm32f415xx.h:102
CRYP_TypeDef::CSGCM1R
__IO uint32_t CSGCM1R
Definition: stm32f415xx.h:739
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32f415xx.h:768
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
CRYP_TypeDef::CR
__IO uint32_t CR
Definition: stm32f415xx.h:710
CRYP_TypeDef::DR
__IO uint32_t DR
Definition: stm32f415xx.h:712
DebugMonitor_IRQn
Definition: stm32f415xx.h:93
DMA2_Stream3_IRQn
Definition: stm32f415xx.h:156
CRYP_TypeDef::CSGCM3R
__IO uint32_t CSGCM3R
Definition: stm32f415xx.h:741
NonMaskableInt_IRQn
Definition: stm32f415xx.h:88
CRYP_TypeDef::CSGCMCCM2R
__IO uint32_t CSGCMCCM2R
Definition: stm32f415xx.h:732
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f415xx.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f415xx.h:141
DMA1_Stream1_IRQn
Definition: stm32f415xx.h:109
DMA2_Stream7_IRQn
Definition: stm32f415xx.h:165
DMA2_Stream6_IRQn
Definition: stm32f415xx.h:164
BusFault_IRQn
Definition: stm32f415xx.h:90
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
I2C3_ER_IRQn
Definition: stm32f415xx.h:168
CAN2_RX0_IRQn
Definition: stm32f415xx.h:159
USART6_IRQn
Definition: stm32f415xx.h:166
PVD_IRQn
Definition: stm32f415xx.h:98
__IO
#define __IO
Definition: core_cm0.h:213
CRYP_TypeDef::K0RR
__IO uint32_t K0RR
Definition: stm32f415xx.h:719
CRYP_TypeDef::K2LR
__IO uint32_t K2LR
Definition: stm32f415xx.h:722
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
CRYP_TypeDef::CSGCMCCM0R
__IO uint32_t CSGCMCCM0R
Definition: stm32f415xx.h:730
DMA1_Stream4_IRQn
Definition: stm32f415xx.h:112
CRYP_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32f415xx.h:717
DMA1_Stream0_IRQn
Definition: stm32f415xx.h:108
OTG_HS_IRQn
Definition: stm32f415xx.h:172
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
TIM8_CC_IRQn
Definition: stm32f415xx.h:143
DMA1_Stream3_IRQn
Definition: stm32f415xx.h:111
FPU_IRQn
Definition: stm32f415xx.h:175
CRYP_TypeDef::CSGCMCCM4R
__IO uint32_t CSGCMCCM4R
Definition: stm32f415xx.h:734
CRYP_TypeDef::SR
__IO uint32_t SR
Definition: stm32f415xx.h:711
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
OTG_FS_IRQn
Definition: stm32f415xx.h:162
DMA2_Stream2_IRQn
Definition: stm32f415xx.h:155
OTG_HS_EP1_OUT_IRQn
Definition: stm32f415xx.h:169
OTG_HS_EP1_IN_IRQn
Definition: stm32f415xx.h:170
CRYP_TypeDef::IV0RR
__IO uint32_t IV0RR
Definition: stm32f415xx.h:727
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f415xx.h:146
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f415xx.h:167
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f415xx.h:135
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f415xx.h:152
I2C2_EV_IRQn
Definition: stm32f415xx.h:130
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f415xx.h:126
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f415xx.h:104
CRYP_TypeDef::K1LR
__IO uint32_t K1LR
Definition: stm32f415xx.h:720
CRYP_TypeDef::CSGCM6R
__IO uint32_t CSGCM6R
Definition: stm32f415xx.h:744
CRYP_TypeDef::IV0LR
__IO uint32_t IV0LR
Definition: stm32f415xx.h:726
CRYP_TypeDef::CSGCMCCM5R
__IO uint32_t CSGCMCCM5R
Definition: stm32f415xx.h:735
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f415xx.h:92
CRYP_TypeDef::K2RR
__IO uint32_t K2RR
Definition: stm32f415xx.h:723
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f415xx.h:124
TIM8_BRK_TIM12_IRQn
Definition: stm32f415xx.h:140
CRYP_TypeDef::CSGCMCCM3R
__IO uint32_t CSGCMCCM3R
Definition: stm32f415xx.h:733
HASH_RNG_IRQn
Definition: stm32f415xx.h:174
FLASH_IRQn
Definition: stm32f415xx.h:101
DMA1_Stream5_IRQn
Definition: stm32f415xx.h:113
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
CRYP_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32f415xx.h:716
HASH_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f415xx.h:758
CRYP_TypeDef::CSGCMCCM6R
__IO uint32_t CSGCMCCM6R
Definition: stm32f415xx.h:736
SysTick_IRQn
Definition: stm32f415xx.h:95
TIM1_UP_TIM10_IRQn
Definition: stm32f415xx.h:122
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f415xx.h:131
HASH_TypeDef::DIN
__IO uint32_t DIN
Definition: stm32f415xx.h:755
UsageFault_IRQn
Definition: stm32f415xx.h:91
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f405xx.h:404
SPI3_IRQn
Definition: stm32f415xx.h:148
DMA2_Stream1_IRQn
Definition: stm32f415xx.h:154
EXTI9_5_IRQn
Definition: stm32f415xx.h:120
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
HASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f415xx.h:754
I2C1_EV_IRQn
Definition: stm32f415xx.h:128
DMA1_Stream6_IRQn
Definition: stm32f415xx.h:114
CRYP_TypeDef::K3LR
__IO uint32_t K3LR
Definition: stm32f415xx.h:724
OTG_HS_WKUP_IRQn
Definition: stm32f415xx.h:171
I2C1_ER_IRQn
Definition: stm32f415xx.h:129
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
FSMC_IRQn
Definition: stm32f415xx.h:145
HASH_TypeDef
HASH.
Definition: stm32f415xx.h:752
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
FSMC_Bank2_3_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f405xx.h:413
CRYP_TypeDef::DOUT
__IO uint32_t DOUT
Definition: stm32f415xx.h:713
CRYP_TypeDef::K3RR
__IO uint32_t K3RR
Definition: stm32f415xx.h:725
CAN2_RX1_IRQn
Definition: stm32f415xx.h:160
DMA2_Stream4_IRQn
Definition: stm32f415xx.h:157
WWDG_IRQn
Definition: stm32f415xx.h:97
CRYP_TypeDef::CSGCMCCM1R
__IO uint32_t CSGCMCCM1R
Definition: stm32f415xx.h:731
CRYP_TypeDef
Crypto Processor.
Definition: stm32f415xx.h:708
DMA1_Stream7_IRQn
Definition: stm32f415xx.h:144
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
CRYP_TypeDef::CSGCMCCM7R
__IO uint32_t CSGCMCCM7R
Definition: stm32f415xx.h:737
EXTI15_10_IRQn
Definition: stm32f415xx.h:137
CAN1_SCE_IRQn
Definition: stm32f415xx.h:119
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
CRYP_TypeDef::IV1LR
__IO uint32_t IV1LR
Definition: stm32f415xx.h:728
EXTI0_IRQn
Definition: stm32f415xx.h:103
DMA2_Stream0_IRQn
Definition: stm32f415xx.h:153
TIM1_BRK_TIM9_IRQn
Definition: stm32f415xx.h:121
CAN2_TX_IRQn
Definition: stm32f415xx.h:158
TIM5_IRQn
Definition: stm32f415xx.h:147
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f415xx.h:106
USART3_IRQn
Definition: stm32f415xx.h:136
CRYP_TypeDef::CSGCM4R
__IO uint32_t CSGCM4R
Definition: stm32f415xx.h:742
CRYP_TypeDef::K1RR
__IO uint32_t K1RR
Definition: stm32f415xx.h:721
MemoryManagement_IRQn
Definition: stm32f415xx.h:89
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f405xx.h:435