STM CMSIS
stm32f417xx.h
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1 
52 #ifndef __STM32F417xx_H
53 #define __STM32F417xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
59 
67 #define __CM4_REV 0x0001U
68 #define __MPU_PRESENT 1U
69 #define __NVIC_PRIO_BITS 4U
70 #define __Vendor_SysTickConfig 0U
71 #define __FPU_PRESENT 1U
85 typedef enum
86 {
87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
88  NonMaskableInt_IRQn = -14,
89  MemoryManagement_IRQn = -12,
90  BusFault_IRQn = -11,
91  UsageFault_IRQn = -10,
92  SVCall_IRQn = -5,
93  DebugMonitor_IRQn = -4,
94  PendSV_IRQn = -2,
95  SysTick_IRQn = -1,
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97  WWDG_IRQn = 0,
98  PVD_IRQn = 1,
99  TAMP_STAMP_IRQn = 2,
100  RTC_WKUP_IRQn = 3,
101  FLASH_IRQn = 4,
102  RCC_IRQn = 5,
103  EXTI0_IRQn = 6,
104  EXTI1_IRQn = 7,
105  EXTI2_IRQn = 8,
106  EXTI3_IRQn = 9,
107  EXTI4_IRQn = 10,
108  DMA1_Stream0_IRQn = 11,
109  DMA1_Stream1_IRQn = 12,
110  DMA1_Stream2_IRQn = 13,
111  DMA1_Stream3_IRQn = 14,
112  DMA1_Stream4_IRQn = 15,
113  DMA1_Stream5_IRQn = 16,
114  DMA1_Stream6_IRQn = 17,
115  ADC_IRQn = 18,
116  CAN1_TX_IRQn = 19,
117  CAN1_RX0_IRQn = 20,
118  CAN1_RX1_IRQn = 21,
119  CAN1_SCE_IRQn = 22,
120  EXTI9_5_IRQn = 23,
121  TIM1_BRK_TIM9_IRQn = 24,
122  TIM1_UP_TIM10_IRQn = 25,
123  TIM1_TRG_COM_TIM11_IRQn = 26,
124  TIM1_CC_IRQn = 27,
125  TIM2_IRQn = 28,
126  TIM3_IRQn = 29,
127  TIM4_IRQn = 30,
128  I2C1_EV_IRQn = 31,
129  I2C1_ER_IRQn = 32,
130  I2C2_EV_IRQn = 33,
131  I2C2_ER_IRQn = 34,
132  SPI1_IRQn = 35,
133  SPI2_IRQn = 36,
134  USART1_IRQn = 37,
135  USART2_IRQn = 38,
136  USART3_IRQn = 39,
137  EXTI15_10_IRQn = 40,
138  RTC_Alarm_IRQn = 41,
139  OTG_FS_WKUP_IRQn = 42,
140  TIM8_BRK_TIM12_IRQn = 43,
141  TIM8_UP_TIM13_IRQn = 44,
142  TIM8_TRG_COM_TIM14_IRQn = 45,
143  TIM8_CC_IRQn = 46,
144  DMA1_Stream7_IRQn = 47,
145  FSMC_IRQn = 48,
146  SDIO_IRQn = 49,
147  TIM5_IRQn = 50,
148  SPI3_IRQn = 51,
149  UART4_IRQn = 52,
150  UART5_IRQn = 53,
151  TIM6_DAC_IRQn = 54,
152  TIM7_IRQn = 55,
153  DMA2_Stream0_IRQn = 56,
154  DMA2_Stream1_IRQn = 57,
155  DMA2_Stream2_IRQn = 58,
156  DMA2_Stream3_IRQn = 59,
157  DMA2_Stream4_IRQn = 60,
158  ETH_IRQn = 61,
159  ETH_WKUP_IRQn = 62,
160  CAN2_TX_IRQn = 63,
161  CAN2_RX0_IRQn = 64,
162  CAN2_RX1_IRQn = 65,
163  CAN2_SCE_IRQn = 66,
164  OTG_FS_IRQn = 67,
165  DMA2_Stream5_IRQn = 68,
166  DMA2_Stream6_IRQn = 69,
167  DMA2_Stream7_IRQn = 70,
168  USART6_IRQn = 71,
169  I2C3_EV_IRQn = 72,
170  I2C3_ER_IRQn = 73,
171  OTG_HS_EP1_OUT_IRQn = 74,
172  OTG_HS_EP1_IN_IRQn = 75,
173  OTG_HS_WKUP_IRQn = 76,
174  OTG_HS_IRQn = 77,
175  DCMI_IRQn = 78,
176  CRYP_IRQn = 79,
177  HASH_RNG_IRQn = 80,
178  FPU_IRQn = 81
179 } IRQn_Type;
180 
185 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
186 #include "system_stm32f4xx.h"
187 #include <stdint.h>
188 
197 typedef struct
198 {
199  __IO uint32_t SR;
200  __IO uint32_t CR1;
201  __IO uint32_t CR2;
202  __IO uint32_t SMPR1;
203  __IO uint32_t SMPR2;
204  __IO uint32_t JOFR1;
205  __IO uint32_t JOFR2;
206  __IO uint32_t JOFR3;
207  __IO uint32_t JOFR4;
208  __IO uint32_t HTR;
209  __IO uint32_t LTR;
210  __IO uint32_t SQR1;
211  __IO uint32_t SQR2;
212  __IO uint32_t SQR3;
213  __IO uint32_t JSQR;
214  __IO uint32_t JDR1;
215  __IO uint32_t JDR2;
216  __IO uint32_t JDR3;
217  __IO uint32_t JDR4;
218  __IO uint32_t DR;
219 } ADC_TypeDef;
220 
221 typedef struct
222 {
223  __IO uint32_t CSR;
224  __IO uint32_t CCR;
225  __IO uint32_t CDR;
227 } ADC_Common_TypeDef;
228 
229 
234 typedef struct
235 {
236  __IO uint32_t TIR;
237  __IO uint32_t TDTR;
238  __IO uint32_t TDLR;
239  __IO uint32_t TDHR;
240 } CAN_TxMailBox_TypeDef;
241 
246 typedef struct
247 {
248  __IO uint32_t RIR;
249  __IO uint32_t RDTR;
250  __IO uint32_t RDLR;
251  __IO uint32_t RDHR;
252 } CAN_FIFOMailBox_TypeDef;
253 
258 typedef struct
259 {
260  __IO uint32_t FR1;
261  __IO uint32_t FR2;
262 } CAN_FilterRegister_TypeDef;
263 
268 typedef struct
269 {
270  __IO uint32_t MCR;
271  __IO uint32_t MSR;
272  __IO uint32_t TSR;
273  __IO uint32_t RF0R;
274  __IO uint32_t RF1R;
275  __IO uint32_t IER;
276  __IO uint32_t ESR;
277  __IO uint32_t BTR;
278  uint32_t RESERVED0[88];
279  CAN_TxMailBox_TypeDef sTxMailBox[3];
280  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
281  uint32_t RESERVED1[12];
282  __IO uint32_t FMR;
283  __IO uint32_t FM1R;
284  uint32_t RESERVED2;
285  __IO uint32_t FS1R;
286  uint32_t RESERVED3;
287  __IO uint32_t FFA1R;
288  uint32_t RESERVED4;
289  __IO uint32_t FA1R;
290  uint32_t RESERVED5[8];
291  CAN_FilterRegister_TypeDef sFilterRegister[28];
292 } CAN_TypeDef;
293 
298 typedef struct
299 {
300  __IO uint32_t DR;
301  __IO uint8_t IDR;
302  uint8_t RESERVED0;
303  uint16_t RESERVED1;
304  __IO uint32_t CR;
305 } CRC_TypeDef;
306 
311 typedef struct
312 {
313  __IO uint32_t CR;
314  __IO uint32_t SWTRIGR;
315  __IO uint32_t DHR12R1;
316  __IO uint32_t DHR12L1;
317  __IO uint32_t DHR8R1;
318  __IO uint32_t DHR12R2;
319  __IO uint32_t DHR12L2;
320  __IO uint32_t DHR8R2;
321  __IO uint32_t DHR12RD;
322  __IO uint32_t DHR12LD;
323  __IO uint32_t DHR8RD;
324  __IO uint32_t DOR1;
325  __IO uint32_t DOR2;
326  __IO uint32_t SR;
327 } DAC_TypeDef;
328 
333 typedef struct
334 {
335  __IO uint32_t IDCODE;
336  __IO uint32_t CR;
337  __IO uint32_t APB1FZ;
338  __IO uint32_t APB2FZ;
339 }DBGMCU_TypeDef;
340 
345 typedef struct
346 {
347  __IO uint32_t CR;
348  __IO uint32_t SR;
349  __IO uint32_t RISR;
350  __IO uint32_t IER;
351  __IO uint32_t MISR;
352  __IO uint32_t ICR;
353  __IO uint32_t ESCR;
354  __IO uint32_t ESUR;
355  __IO uint32_t CWSTRTR;
356  __IO uint32_t CWSIZER;
357  __IO uint32_t DR;
358 } DCMI_TypeDef;
359 
364 typedef struct
365 {
366  __IO uint32_t CR;
367  __IO uint32_t NDTR;
368  __IO uint32_t PAR;
369  __IO uint32_t M0AR;
370  __IO uint32_t M1AR;
371  __IO uint32_t FCR;
372 } DMA_Stream_TypeDef;
373 
374 typedef struct
375 {
376  __IO uint32_t LISR;
377  __IO uint32_t HISR;
378  __IO uint32_t LIFCR;
379  __IO uint32_t HIFCR;
380 } DMA_TypeDef;
381 
382 
387 typedef struct
388 {
389  __IO uint32_t MACCR;
390  __IO uint32_t MACFFR;
391  __IO uint32_t MACHTHR;
392  __IO uint32_t MACHTLR;
393  __IO uint32_t MACMIIAR;
394  __IO uint32_t MACMIIDR;
395  __IO uint32_t MACFCR;
396  __IO uint32_t MACVLANTR; /* 8 */
397  uint32_t RESERVED0[2];
398  __IO uint32_t MACRWUFFR; /* 11 */
399  __IO uint32_t MACPMTCSR;
400  uint32_t RESERVED1[2];
401  __IO uint32_t MACSR; /* 15 */
402  __IO uint32_t MACIMR;
403  __IO uint32_t MACA0HR;
404  __IO uint32_t MACA0LR;
405  __IO uint32_t MACA1HR;
406  __IO uint32_t MACA1LR;
407  __IO uint32_t MACA2HR;
408  __IO uint32_t MACA2LR;
409  __IO uint32_t MACA3HR;
410  __IO uint32_t MACA3LR; /* 24 */
411  uint32_t RESERVED2[40];
412  __IO uint32_t MMCCR; /* 65 */
413  __IO uint32_t MMCRIR;
414  __IO uint32_t MMCTIR;
415  __IO uint32_t MMCRIMR;
416  __IO uint32_t MMCTIMR; /* 69 */
417  uint32_t RESERVED3[14];
418  __IO uint32_t MMCTGFSCCR; /* 84 */
419  __IO uint32_t MMCTGFMSCCR;
420  uint32_t RESERVED4[5];
421  __IO uint32_t MMCTGFCR;
422  uint32_t RESERVED5[10];
423  __IO uint32_t MMCRFCECR;
424  __IO uint32_t MMCRFAECR;
425  uint32_t RESERVED6[10];
426  __IO uint32_t MMCRGUFCR;
427  uint32_t RESERVED7[334];
428  __IO uint32_t PTPTSCR;
429  __IO uint32_t PTPSSIR;
430  __IO uint32_t PTPTSHR;
431  __IO uint32_t PTPTSLR;
432  __IO uint32_t PTPTSHUR;
433  __IO uint32_t PTPTSLUR;
434  __IO uint32_t PTPTSAR;
435  __IO uint32_t PTPTTHR;
436  __IO uint32_t PTPTTLR;
437  __IO uint32_t RESERVED8;
438  __IO uint32_t PTPTSSR;
439  uint32_t RESERVED9[565];
440  __IO uint32_t DMABMR;
441  __IO uint32_t DMATPDR;
442  __IO uint32_t DMARPDR;
443  __IO uint32_t DMARDLAR;
444  __IO uint32_t DMATDLAR;
445  __IO uint32_t DMASR;
446  __IO uint32_t DMAOMR;
447  __IO uint32_t DMAIER;
448  __IO uint32_t DMAMFBOCR;
449  __IO uint32_t DMARSWTR;
450  uint32_t RESERVED10[8];
451  __IO uint32_t DMACHTDR;
452  __IO uint32_t DMACHRDR;
453  __IO uint32_t DMACHTBAR;
454  __IO uint32_t DMACHRBAR;
455 } ETH_TypeDef;
456 
461 typedef struct
462 {
463  __IO uint32_t IMR;
464  __IO uint32_t EMR;
465  __IO uint32_t RTSR;
466  __IO uint32_t FTSR;
467  __IO uint32_t SWIER;
468  __IO uint32_t PR;
469 } EXTI_TypeDef;
470 
475 typedef struct
476 {
477  __IO uint32_t ACR;
478  __IO uint32_t KEYR;
479  __IO uint32_t OPTKEYR;
480  __IO uint32_t SR;
481  __IO uint32_t CR;
482  __IO uint32_t OPTCR;
483  __IO uint32_t OPTCR1;
484 } FLASH_TypeDef;
485 
486 
491 typedef struct
492 {
493  __IO uint32_t BTCR[8];
494 } FSMC_Bank1_TypeDef;
495 
500 typedef struct
501 {
502  __IO uint32_t BWTR[7];
503 } FSMC_Bank1E_TypeDef;
504 
509 typedef struct
510 {
511  __IO uint32_t PCR2;
512  __IO uint32_t SR2;
513  __IO uint32_t PMEM2;
514  __IO uint32_t PATT2;
515  uint32_t RESERVED0;
516  __IO uint32_t ECCR2;
517  uint32_t RESERVED1;
518  uint32_t RESERVED2;
519  __IO uint32_t PCR3;
520  __IO uint32_t SR3;
521  __IO uint32_t PMEM3;
522  __IO uint32_t PATT3;
523  uint32_t RESERVED3;
524  __IO uint32_t ECCR3;
525 } FSMC_Bank2_3_TypeDef;
526 
531 typedef struct
532 {
533  __IO uint32_t PCR4;
534  __IO uint32_t SR4;
535  __IO uint32_t PMEM4;
536  __IO uint32_t PATT4;
537  __IO uint32_t PIO4;
538 } FSMC_Bank4_TypeDef;
539 
540 
545 typedef struct
546 {
547  __IO uint32_t MODER;
548  __IO uint32_t OTYPER;
549  __IO uint32_t OSPEEDR;
550  __IO uint32_t PUPDR;
551  __IO uint32_t IDR;
552  __IO uint32_t ODR;
553  __IO uint32_t BSRR;
554  __IO uint32_t LCKR;
555  __IO uint32_t AFR[2];
556 } GPIO_TypeDef;
557 
562 typedef struct
563 {
564  __IO uint32_t MEMRMP;
565  __IO uint32_t PMC;
566  __IO uint32_t EXTICR[4];
567  uint32_t RESERVED[2];
568  __IO uint32_t CMPCR;
569 } SYSCFG_TypeDef;
570 
575 typedef struct
576 {
577  __IO uint32_t CR1;
578  __IO uint32_t CR2;
579  __IO uint32_t OAR1;
580  __IO uint32_t OAR2;
581  __IO uint32_t DR;
582  __IO uint32_t SR1;
583  __IO uint32_t SR2;
584  __IO uint32_t CCR;
585  __IO uint32_t TRISE;
586  __IO uint32_t FLTR;
587 } I2C_TypeDef;
588 
593 typedef struct
594 {
595  __IO uint32_t KR;
596  __IO uint32_t PR;
597  __IO uint32_t RLR;
598  __IO uint32_t SR;
599 } IWDG_TypeDef;
600 
605 typedef struct
606 {
607  __IO uint32_t CR;
608  __IO uint32_t CSR;
609 } PWR_TypeDef;
610 
615 typedef struct
616 {
617  __IO uint32_t CR;
618  __IO uint32_t PLLCFGR;
619  __IO uint32_t CFGR;
620  __IO uint32_t CIR;
621  __IO uint32_t AHB1RSTR;
622  __IO uint32_t AHB2RSTR;
623  __IO uint32_t AHB3RSTR;
624  uint32_t RESERVED0;
625  __IO uint32_t APB1RSTR;
626  __IO uint32_t APB2RSTR;
627  uint32_t RESERVED1[2];
628  __IO uint32_t AHB1ENR;
629  __IO uint32_t AHB2ENR;
630  __IO uint32_t AHB3ENR;
631  uint32_t RESERVED2;
632  __IO uint32_t APB1ENR;
633  __IO uint32_t APB2ENR;
634  uint32_t RESERVED3[2];
635  __IO uint32_t AHB1LPENR;
636  __IO uint32_t AHB2LPENR;
637  __IO uint32_t AHB3LPENR;
638  uint32_t RESERVED4;
639  __IO uint32_t APB1LPENR;
640  __IO uint32_t APB2LPENR;
641  uint32_t RESERVED5[2];
642  __IO uint32_t BDCR;
643  __IO uint32_t CSR;
644  uint32_t RESERVED6[2];
645  __IO uint32_t SSCGR;
646  __IO uint32_t PLLI2SCFGR;
648 } RCC_TypeDef;
649 
654 typedef struct
655 {
656  __IO uint32_t TR;
657  __IO uint32_t DR;
658  __IO uint32_t CR;
659  __IO uint32_t ISR;
660  __IO uint32_t PRER;
661  __IO uint32_t WUTR;
662  __IO uint32_t CALIBR;
663  __IO uint32_t ALRMAR;
664  __IO uint32_t ALRMBR;
665  __IO uint32_t WPR;
666  __IO uint32_t SSR;
667  __IO uint32_t SHIFTR;
668  __IO uint32_t TSTR;
669  __IO uint32_t TSDR;
670  __IO uint32_t TSSSR;
671  __IO uint32_t CALR;
672  __IO uint32_t TAFCR;
673  __IO uint32_t ALRMASSR;
674  __IO uint32_t ALRMBSSR;
675  uint32_t RESERVED7;
676  __IO uint32_t BKP0R;
677  __IO uint32_t BKP1R;
678  __IO uint32_t BKP2R;
679  __IO uint32_t BKP3R;
680  __IO uint32_t BKP4R;
681  __IO uint32_t BKP5R;
682  __IO uint32_t BKP6R;
683  __IO uint32_t BKP7R;
684  __IO uint32_t BKP8R;
685  __IO uint32_t BKP9R;
686  __IO uint32_t BKP10R;
687  __IO uint32_t BKP11R;
688  __IO uint32_t BKP12R;
689  __IO uint32_t BKP13R;
690  __IO uint32_t BKP14R;
691  __IO uint32_t BKP15R;
692  __IO uint32_t BKP16R;
693  __IO uint32_t BKP17R;
694  __IO uint32_t BKP18R;
695  __IO uint32_t BKP19R;
696 } RTC_TypeDef;
697 
698 
703 typedef struct
704 {
705  __IO uint32_t POWER;
706  __IO uint32_t CLKCR;
707  __IO uint32_t ARG;
708  __IO uint32_t CMD;
709  __I uint32_t RESPCMD;
710  __I uint32_t RESP1;
711  __I uint32_t RESP2;
712  __I uint32_t RESP3;
713  __I uint32_t RESP4;
714  __IO uint32_t DTIMER;
715  __IO uint32_t DLEN;
716  __IO uint32_t DCTRL;
717  __I uint32_t DCOUNT;
718  __I uint32_t STA;
719  __IO uint32_t ICR;
720  __IO uint32_t MASK;
721  uint32_t RESERVED0[2];
722  __I uint32_t FIFOCNT;
723  uint32_t RESERVED1[13];
724  __IO uint32_t FIFO;
725 } SDIO_TypeDef;
726 
731 typedef struct
732 {
733  __IO uint32_t CR1;
734  __IO uint32_t CR2;
735  __IO uint32_t SR;
736  __IO uint32_t DR;
737  __IO uint32_t CRCPR;
738  __IO uint32_t RXCRCR;
739  __IO uint32_t TXCRCR;
740  __IO uint32_t I2SCFGR;
741  __IO uint32_t I2SPR;
742 } SPI_TypeDef;
743 
748 typedef struct
749 {
750  __IO uint32_t CR1;
751  __IO uint32_t CR2;
752  __IO uint32_t SMCR;
753  __IO uint32_t DIER;
754  __IO uint32_t SR;
755  __IO uint32_t EGR;
756  __IO uint32_t CCMR1;
757  __IO uint32_t CCMR2;
758  __IO uint32_t CCER;
759  __IO uint32_t CNT;
760  __IO uint32_t PSC;
761  __IO uint32_t ARR;
762  __IO uint32_t RCR;
763  __IO uint32_t CCR1;
764  __IO uint32_t CCR2;
765  __IO uint32_t CCR3;
766  __IO uint32_t CCR4;
767  __IO uint32_t BDTR;
768  __IO uint32_t DCR;
769  __IO uint32_t DMAR;
770  __IO uint32_t OR;
771 } TIM_TypeDef;
772 
777 typedef struct
778 {
779  __IO uint32_t SR;
780  __IO uint32_t DR;
781  __IO uint32_t BRR;
782  __IO uint32_t CR1;
783  __IO uint32_t CR2;
784  __IO uint32_t CR3;
785  __IO uint32_t GTPR;
786 } USART_TypeDef;
787 
792 typedef struct
793 {
794  __IO uint32_t CR;
795  __IO uint32_t CFR;
796  __IO uint32_t SR;
797 } WWDG_TypeDef;
798 
803 typedef struct
804 {
805  __IO uint32_t CR;
806  __IO uint32_t SR;
807  __IO uint32_t DR;
808  __IO uint32_t DOUT;
809  __IO uint32_t DMACR;
810  __IO uint32_t IMSCR;
811  __IO uint32_t RISR;
812  __IO uint32_t MISR;
813  __IO uint32_t K0LR;
814  __IO uint32_t K0RR;
815  __IO uint32_t K1LR;
816  __IO uint32_t K1RR;
817  __IO uint32_t K2LR;
818  __IO uint32_t K2RR;
819  __IO uint32_t K3LR;
820  __IO uint32_t K3RR;
821  __IO uint32_t IV0LR;
822  __IO uint32_t IV0RR;
823  __IO uint32_t IV1LR;
824  __IO uint32_t IV1RR;
825  __IO uint32_t CSGCMCCM0R;
826  __IO uint32_t CSGCMCCM1R;
827  __IO uint32_t CSGCMCCM2R;
828  __IO uint32_t CSGCMCCM3R;
829  __IO uint32_t CSGCMCCM4R;
830  __IO uint32_t CSGCMCCM5R;
831  __IO uint32_t CSGCMCCM6R;
832  __IO uint32_t CSGCMCCM7R;
833  __IO uint32_t CSGCM0R;
834  __IO uint32_t CSGCM1R;
835  __IO uint32_t CSGCM2R;
836  __IO uint32_t CSGCM3R;
837  __IO uint32_t CSGCM4R;
838  __IO uint32_t CSGCM5R;
839  __IO uint32_t CSGCM6R;
840  __IO uint32_t CSGCM7R;
841 } CRYP_TypeDef;
842 
847 typedef struct
848 {
849  __IO uint32_t CR;
850  __IO uint32_t DIN;
851  __IO uint32_t STR;
852  __IO uint32_t HR[5];
853  __IO uint32_t IMR;
854  __IO uint32_t SR;
855  uint32_t RESERVED[52];
856  __IO uint32_t CSR[54];
857 } HASH_TypeDef;
858 
863 typedef struct
864 {
865  __IO uint32_t HR[8];
866 } HASH_DIGEST_TypeDef;
867 
872 typedef struct
873 {
874  __IO uint32_t CR;
875  __IO uint32_t SR;
876  __IO uint32_t DR;
877 } RNG_TypeDef;
878 
879 
880 
884 typedef struct
885 {
886  __IO uint32_t GOTGCTL;
887  __IO uint32_t GOTGINT;
888  __IO uint32_t GAHBCFG;
889  __IO uint32_t GUSBCFG;
890  __IO uint32_t GRSTCTL;
891  __IO uint32_t GINTSTS;
892  __IO uint32_t GINTMSK;
893  __IO uint32_t GRXSTSR;
894  __IO uint32_t GRXSTSP;
895  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
896  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
897  __IO uint32_t HNPTXSTS;
898  uint32_t Reserved30[2]; /* Reserved 030h*/
899  __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
900  __IO uint32_t CID; /* User ID Register 03Ch*/
901  uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
902  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
903  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
904 }
905 USB_OTG_GlobalTypeDef;
906 
907 
908 
912 typedef struct
913 {
914  __IO uint32_t DCFG; /* dev Configuration Register 800h*/
915  __IO uint32_t DCTL; /* dev Control Register 804h*/
916  __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
917  uint32_t Reserved0C; /* Reserved 80Ch*/
918  __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
919  __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
920  __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
921  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
922  uint32_t Reserved20; /* Reserved 820h*/
923  uint32_t Reserved9; /* Reserved 824h*/
924  __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
925  __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
926  __IO uint32_t DTHRCTL; /* dev thr 830h*/
927  __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
928  __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
929  __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
930  uint32_t Reserved40; /* dedicated EP mask 840h*/
931  __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
932  uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
933  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
934 }
935 USB_OTG_DeviceTypeDef;
936 
937 
941 typedef struct
942 {
943  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
944  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
945  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
946  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
947  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
948  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
949  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
950  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
951 }
952 USB_OTG_INEndpointTypeDef;
953 
954 
958 typedef struct
959 {
960  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
961  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
962  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
963  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
964  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
965  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
966  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
967 }
968 USB_OTG_OUTEndpointTypeDef;
969 
970 
974 typedef struct
975 {
976  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
977  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
978  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
979  uint32_t Reserved40C; /* Reserved 40Ch*/
980  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
981  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
982  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
983 }
984 USB_OTG_HostTypeDef;
985 
986 
990 typedef struct
991 {
992  __IO uint32_t HCCHAR;
993  __IO uint32_t HCSPLT;
994  __IO uint32_t HCINT;
995  __IO uint32_t HCINTMSK;
996  __IO uint32_t HCTSIZ;
997  __IO uint32_t HCDMA;
998  uint32_t Reserved[2];
999 }
1000 USB_OTG_HostChannelTypeDef;
1001 
1002 
1006 #define FLASH_BASE 0x08000000U
1007 #define CCMDATARAM_BASE 0x10000000U
1008 #define SRAM1_BASE 0x20000000U
1009 #define SRAM2_BASE 0x2001C000U
1010 #define PERIPH_BASE 0x40000000U
1011 #define BKPSRAM_BASE 0x40024000U
1012 #define FSMC_R_BASE 0xA0000000U
1013 #define SRAM1_BB_BASE 0x22000000U
1014 #define SRAM2_BB_BASE 0x22380000U
1015 #define PERIPH_BB_BASE 0x42000000U
1016 #define BKPSRAM_BB_BASE 0x42480000U
1017 #define FLASH_END 0x080FFFFFU
1018 #define CCMDATARAM_END 0x1000FFFFU
1020 /* Legacy defines */
1021 #define SRAM_BASE SRAM1_BASE
1022 #define SRAM_BB_BASE SRAM1_BB_BASE
1023 
1024 
1026 #define APB1PERIPH_BASE PERIPH_BASE
1027 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1028 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1029 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1030 
1032 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1033 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1034 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1035 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1036 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1037 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1038 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1039 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1040 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1041 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1042 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1043 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1044 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1045 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1046 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1047 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1048 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1049 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1050 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1051 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1052 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1053 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1054 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1055 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1056 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1057 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1058 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1059 
1061 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1062 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1063 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1064 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1065 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1066 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1067 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1068 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1069 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1070 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1071 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1072 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1073 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1074 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1075 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1076 
1078 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1079 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1080 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1081 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1082 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1083 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1084 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1085 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1086 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1087 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1088 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1089 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1090 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1091 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1092 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1093 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1094 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1095 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1096 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1097 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1098 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1099 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1100 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1101 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1102 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1103 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1104 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1105 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1106 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1107 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1108 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1109 #define ETH_MAC_BASE (ETH_BASE)
1110 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1111 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1112 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1113 
1115 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1116 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1117 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1118 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1119 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1120 
1122 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
1123 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
1124 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
1125 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
1126 
1127 /* Debug MCU registers base address */
1128 #define DBGMCU_BASE 0xE0042000U
1129 
1131 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1132 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1133 
1134 #define USB_OTG_GLOBAL_BASE 0x000U
1135 #define USB_OTG_DEVICE_BASE 0x800U
1136 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1137 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1138 #define USB_OTG_EP_REG_SIZE 0x20U
1139 #define USB_OTG_HOST_BASE 0x400U
1140 #define USB_OTG_HOST_PORT_BASE 0x440U
1141 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1142 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1143 #define USB_OTG_PCGCCTL_BASE 0xE00U
1144 #define USB_OTG_FIFO_BASE 0x1000U
1145 #define USB_OTG_FIFO_SIZE 0x1000U
1146 
1154 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1155 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1156 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1157 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1158 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1159 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1160 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1161 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1162 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1163 #define RTC ((RTC_TypeDef *) RTC_BASE)
1164 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1165 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1166 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1167 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1168 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1169 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1170 #define USART2 ((USART_TypeDef *) USART2_BASE)
1171 #define USART3 ((USART_TypeDef *) USART3_BASE)
1172 #define UART4 ((USART_TypeDef *) UART4_BASE)
1173 #define UART5 ((USART_TypeDef *) UART5_BASE)
1174 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1175 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1176 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1177 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1178 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1179 #define PWR ((PWR_TypeDef *) PWR_BASE)
1180 #define DAC ((DAC_TypeDef *) DAC_BASE)
1181 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1182 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1183 #define USART1 ((USART_TypeDef *) USART1_BASE)
1184 #define USART6 ((USART_TypeDef *) USART6_BASE)
1185 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1186 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1187 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1188 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1189 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1190 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1191 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1192 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1193 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1194 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1195 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1196 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1197 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1198 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1199 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1200 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1201 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1202 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1203 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1204 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1205 #define CRC ((CRC_TypeDef *) CRC_BASE)
1206 #define RCC ((RCC_TypeDef *) RCC_BASE)
1207 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1208 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1209 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1210 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1211 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1212 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1213 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1214 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1215 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1216 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1217 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1218 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1219 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1220 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1221 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1222 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1223 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1224 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1225 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1226 #define ETH ((ETH_TypeDef *) ETH_BASE)
1227 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1228 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1229 #define HASH ((HASH_TypeDef *) HASH_BASE)
1230 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1231 #define RNG ((RNG_TypeDef *) RNG_BASE)
1232 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1233 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1234 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1235 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1236 
1237 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1238 
1239 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1240 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1241 
1254 /******************************************************************************/
1255 /* Peripheral Registers_Bits_Definition */
1256 /******************************************************************************/
1257 
1258 /******************************************************************************/
1259 /* */
1260 /* Analog to Digital Converter */
1261 /* */
1262 /******************************************************************************/
1263 /******************** Bit definition for ADC_SR register ********************/
1264 #define ADC_SR_AWD 0x00000001U
1265 #define ADC_SR_EOC 0x00000002U
1266 #define ADC_SR_JEOC 0x00000004U
1267 #define ADC_SR_JSTRT 0x00000008U
1268 #define ADC_SR_STRT 0x00000010U
1269 #define ADC_SR_OVR 0x00000020U
1271 /******************* Bit definition for ADC_CR1 register ********************/
1272 #define ADC_CR1_AWDCH 0x0000001FU
1273 #define ADC_CR1_AWDCH_0 0x00000001U
1274 #define ADC_CR1_AWDCH_1 0x00000002U
1275 #define ADC_CR1_AWDCH_2 0x00000004U
1276 #define ADC_CR1_AWDCH_3 0x00000008U
1277 #define ADC_CR1_AWDCH_4 0x00000010U
1278 #define ADC_CR1_EOCIE 0x00000020U
1279 #define ADC_CR1_AWDIE 0x00000040U
1280 #define ADC_CR1_JEOCIE 0x00000080U
1281 #define ADC_CR1_SCAN 0x00000100U
1282 #define ADC_CR1_AWDSGL 0x00000200U
1283 #define ADC_CR1_JAUTO 0x00000400U
1284 #define ADC_CR1_DISCEN 0x00000800U
1285 #define ADC_CR1_JDISCEN 0x00001000U
1286 #define ADC_CR1_DISCNUM 0x0000E000U
1287 #define ADC_CR1_DISCNUM_0 0x00002000U
1288 #define ADC_CR1_DISCNUM_1 0x00004000U
1289 #define ADC_CR1_DISCNUM_2 0x00008000U
1290 #define ADC_CR1_JAWDEN 0x00400000U
1291 #define ADC_CR1_AWDEN 0x00800000U
1292 #define ADC_CR1_RES 0x03000000U
1293 #define ADC_CR1_RES_0 0x01000000U
1294 #define ADC_CR1_RES_1 0x02000000U
1295 #define ADC_CR1_OVRIE 0x04000000U
1297 /******************* Bit definition for ADC_CR2 register ********************/
1298 #define ADC_CR2_ADON 0x00000001U
1299 #define ADC_CR2_CONT 0x00000002U
1300 #define ADC_CR2_DMA 0x00000100U
1301 #define ADC_CR2_DDS 0x00000200U
1302 #define ADC_CR2_EOCS 0x00000400U
1303 #define ADC_CR2_ALIGN 0x00000800U
1304 #define ADC_CR2_JEXTSEL 0x000F0000U
1305 #define ADC_CR2_JEXTSEL_0 0x00010000U
1306 #define ADC_CR2_JEXTSEL_1 0x00020000U
1307 #define ADC_CR2_JEXTSEL_2 0x00040000U
1308 #define ADC_CR2_JEXTSEL_3 0x00080000U
1309 #define ADC_CR2_JEXTEN 0x00300000U
1310 #define ADC_CR2_JEXTEN_0 0x00100000U
1311 #define ADC_CR2_JEXTEN_1 0x00200000U
1312 #define ADC_CR2_JSWSTART 0x00400000U
1313 #define ADC_CR2_EXTSEL 0x0F000000U
1314 #define ADC_CR2_EXTSEL_0 0x01000000U
1315 #define ADC_CR2_EXTSEL_1 0x02000000U
1316 #define ADC_CR2_EXTSEL_2 0x04000000U
1317 #define ADC_CR2_EXTSEL_3 0x08000000U
1318 #define ADC_CR2_EXTEN 0x30000000U
1319 #define ADC_CR2_EXTEN_0 0x10000000U
1320 #define ADC_CR2_EXTEN_1 0x20000000U
1321 #define ADC_CR2_SWSTART 0x40000000U
1323 /****************** Bit definition for ADC_SMPR1 register *******************/
1324 #define ADC_SMPR1_SMP10 0x00000007U
1325 #define ADC_SMPR1_SMP10_0 0x00000001U
1326 #define ADC_SMPR1_SMP10_1 0x00000002U
1327 #define ADC_SMPR1_SMP10_2 0x00000004U
1328 #define ADC_SMPR1_SMP11 0x00000038U
1329 #define ADC_SMPR1_SMP11_0 0x00000008U
1330 #define ADC_SMPR1_SMP11_1 0x00000010U
1331 #define ADC_SMPR1_SMP11_2 0x00000020U
1332 #define ADC_SMPR1_SMP12 0x000001C0U
1333 #define ADC_SMPR1_SMP12_0 0x00000040U
1334 #define ADC_SMPR1_SMP12_1 0x00000080U
1335 #define ADC_SMPR1_SMP12_2 0x00000100U
1336 #define ADC_SMPR1_SMP13 0x00000E00U
1337 #define ADC_SMPR1_SMP13_0 0x00000200U
1338 #define ADC_SMPR1_SMP13_1 0x00000400U
1339 #define ADC_SMPR1_SMP13_2 0x00000800U
1340 #define ADC_SMPR1_SMP14 0x00007000U
1341 #define ADC_SMPR1_SMP14_0 0x00001000U
1342 #define ADC_SMPR1_SMP14_1 0x00002000U
1343 #define ADC_SMPR1_SMP14_2 0x00004000U
1344 #define ADC_SMPR1_SMP15 0x00038000U
1345 #define ADC_SMPR1_SMP15_0 0x00008000U
1346 #define ADC_SMPR1_SMP15_1 0x00010000U
1347 #define ADC_SMPR1_SMP15_2 0x00020000U
1348 #define ADC_SMPR1_SMP16 0x001C0000U
1349 #define ADC_SMPR1_SMP16_0 0x00040000U
1350 #define ADC_SMPR1_SMP16_1 0x00080000U
1351 #define ADC_SMPR1_SMP16_2 0x00100000U
1352 #define ADC_SMPR1_SMP17 0x00E00000U
1353 #define ADC_SMPR1_SMP17_0 0x00200000U
1354 #define ADC_SMPR1_SMP17_1 0x00400000U
1355 #define ADC_SMPR1_SMP17_2 0x00800000U
1356 #define ADC_SMPR1_SMP18 0x07000000U
1357 #define ADC_SMPR1_SMP18_0 0x01000000U
1358 #define ADC_SMPR1_SMP18_1 0x02000000U
1359 #define ADC_SMPR1_SMP18_2 0x04000000U
1361 /****************** Bit definition for ADC_SMPR2 register *******************/
1362 #define ADC_SMPR2_SMP0 0x00000007U
1363 #define ADC_SMPR2_SMP0_0 0x00000001U
1364 #define ADC_SMPR2_SMP0_1 0x00000002U
1365 #define ADC_SMPR2_SMP0_2 0x00000004U
1366 #define ADC_SMPR2_SMP1 0x00000038U
1367 #define ADC_SMPR2_SMP1_0 0x00000008U
1368 #define ADC_SMPR2_SMP1_1 0x00000010U
1369 #define ADC_SMPR2_SMP1_2 0x00000020U
1370 #define ADC_SMPR2_SMP2 0x000001C0U
1371 #define ADC_SMPR2_SMP2_0 0x00000040U
1372 #define ADC_SMPR2_SMP2_1 0x00000080U
1373 #define ADC_SMPR2_SMP2_2 0x00000100U
1374 #define ADC_SMPR2_SMP3 0x00000E00U
1375 #define ADC_SMPR2_SMP3_0 0x00000200U
1376 #define ADC_SMPR2_SMP3_1 0x00000400U
1377 #define ADC_SMPR2_SMP3_2 0x00000800U
1378 #define ADC_SMPR2_SMP4 0x00007000U
1379 #define ADC_SMPR2_SMP4_0 0x00001000U
1380 #define ADC_SMPR2_SMP4_1 0x00002000U
1381 #define ADC_SMPR2_SMP4_2 0x00004000U
1382 #define ADC_SMPR2_SMP5 0x00038000U
1383 #define ADC_SMPR2_SMP5_0 0x00008000U
1384 #define ADC_SMPR2_SMP5_1 0x00010000U
1385 #define ADC_SMPR2_SMP5_2 0x00020000U
1386 #define ADC_SMPR2_SMP6 0x001C0000U
1387 #define ADC_SMPR2_SMP6_0 0x00040000U
1388 #define ADC_SMPR2_SMP6_1 0x00080000U
1389 #define ADC_SMPR2_SMP6_2 0x00100000U
1390 #define ADC_SMPR2_SMP7 0x00E00000U
1391 #define ADC_SMPR2_SMP7_0 0x00200000U
1392 #define ADC_SMPR2_SMP7_1 0x00400000U
1393 #define ADC_SMPR2_SMP7_2 0x00800000U
1394 #define ADC_SMPR2_SMP8 0x07000000U
1395 #define ADC_SMPR2_SMP8_0 0x01000000U
1396 #define ADC_SMPR2_SMP8_1 0x02000000U
1397 #define ADC_SMPR2_SMP8_2 0x04000000U
1398 #define ADC_SMPR2_SMP9 0x38000000U
1399 #define ADC_SMPR2_SMP9_0 0x08000000U
1400 #define ADC_SMPR2_SMP9_1 0x10000000U
1401 #define ADC_SMPR2_SMP9_2 0x20000000U
1403 /****************** Bit definition for ADC_JOFR1 register *******************/
1404 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1406 /****************** Bit definition for ADC_JOFR2 register *******************/
1407 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1409 /****************** Bit definition for ADC_JOFR3 register *******************/
1410 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1412 /****************** Bit definition for ADC_JOFR4 register *******************/
1413 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1415 /******************* Bit definition for ADC_HTR register ********************/
1416 #define ADC_HTR_HT 0x0FFFU
1418 /******************* Bit definition for ADC_LTR register ********************/
1419 #define ADC_LTR_LT 0x0FFFU
1421 /******************* Bit definition for ADC_SQR1 register *******************/
1422 #define ADC_SQR1_SQ13 0x0000001FU
1423 #define ADC_SQR1_SQ13_0 0x00000001U
1424 #define ADC_SQR1_SQ13_1 0x00000002U
1425 #define ADC_SQR1_SQ13_2 0x00000004U
1426 #define ADC_SQR1_SQ13_3 0x00000008U
1427 #define ADC_SQR1_SQ13_4 0x00000010U
1428 #define ADC_SQR1_SQ14 0x000003E0U
1429 #define ADC_SQR1_SQ14_0 0x00000020U
1430 #define ADC_SQR1_SQ14_1 0x00000040U
1431 #define ADC_SQR1_SQ14_2 0x00000080U
1432 #define ADC_SQR1_SQ14_3 0x00000100U
1433 #define ADC_SQR1_SQ14_4 0x00000200U
1434 #define ADC_SQR1_SQ15 0x00007C00U
1435 #define ADC_SQR1_SQ15_0 0x00000400U
1436 #define ADC_SQR1_SQ15_1 0x00000800U
1437 #define ADC_SQR1_SQ15_2 0x00001000U
1438 #define ADC_SQR1_SQ15_3 0x00002000U
1439 #define ADC_SQR1_SQ15_4 0x00004000U
1440 #define ADC_SQR1_SQ16 0x000F8000U
1441 #define ADC_SQR1_SQ16_0 0x00008000U
1442 #define ADC_SQR1_SQ16_1 0x00010000U
1443 #define ADC_SQR1_SQ16_2 0x00020000U
1444 #define ADC_SQR1_SQ16_3 0x00040000U
1445 #define ADC_SQR1_SQ16_4 0x00080000U
1446 #define ADC_SQR1_L 0x00F00000U
1447 #define ADC_SQR1_L_0 0x00100000U
1448 #define ADC_SQR1_L_1 0x00200000U
1449 #define ADC_SQR1_L_2 0x00400000U
1450 #define ADC_SQR1_L_3 0x00800000U
1452 /******************* Bit definition for ADC_SQR2 register *******************/
1453 #define ADC_SQR2_SQ7 0x0000001FU
1454 #define ADC_SQR2_SQ7_0 0x00000001U
1455 #define ADC_SQR2_SQ7_1 0x00000002U
1456 #define ADC_SQR2_SQ7_2 0x00000004U
1457 #define ADC_SQR2_SQ7_3 0x00000008U
1458 #define ADC_SQR2_SQ7_4 0x00000010U
1459 #define ADC_SQR2_SQ8 0x000003E0U
1460 #define ADC_SQR2_SQ8_0 0x00000020U
1461 #define ADC_SQR2_SQ8_1 0x00000040U
1462 #define ADC_SQR2_SQ8_2 0x00000080U
1463 #define ADC_SQR2_SQ8_3 0x00000100U
1464 #define ADC_SQR2_SQ8_4 0x00000200U
1465 #define ADC_SQR2_SQ9 0x00007C00U
1466 #define ADC_SQR2_SQ9_0 0x00000400U
1467 #define ADC_SQR2_SQ9_1 0x00000800U
1468 #define ADC_SQR2_SQ9_2 0x00001000U
1469 #define ADC_SQR2_SQ9_3 0x00002000U
1470 #define ADC_SQR2_SQ9_4 0x00004000U
1471 #define ADC_SQR2_SQ10 0x000F8000U
1472 #define ADC_SQR2_SQ10_0 0x00008000U
1473 #define ADC_SQR2_SQ10_1 0x00010000U
1474 #define ADC_SQR2_SQ10_2 0x00020000U
1475 #define ADC_SQR2_SQ10_3 0x00040000U
1476 #define ADC_SQR2_SQ10_4 0x00080000U
1477 #define ADC_SQR2_SQ11 0x01F00000U
1478 #define ADC_SQR2_SQ11_0 0x00100000U
1479 #define ADC_SQR2_SQ11_1 0x00200000U
1480 #define ADC_SQR2_SQ11_2 0x00400000U
1481 #define ADC_SQR2_SQ11_3 0x00800000U
1482 #define ADC_SQR2_SQ11_4 0x01000000U
1483 #define ADC_SQR2_SQ12 0x3E000000U
1484 #define ADC_SQR2_SQ12_0 0x02000000U
1485 #define ADC_SQR2_SQ12_1 0x04000000U
1486 #define ADC_SQR2_SQ12_2 0x08000000U
1487 #define ADC_SQR2_SQ12_3 0x10000000U
1488 #define ADC_SQR2_SQ12_4 0x20000000U
1490 /******************* Bit definition for ADC_SQR3 register *******************/
1491 #define ADC_SQR3_SQ1 0x0000001FU
1492 #define ADC_SQR3_SQ1_0 0x00000001U
1493 #define ADC_SQR3_SQ1_1 0x00000002U
1494 #define ADC_SQR3_SQ1_2 0x00000004U
1495 #define ADC_SQR3_SQ1_3 0x00000008U
1496 #define ADC_SQR3_SQ1_4 0x00000010U
1497 #define ADC_SQR3_SQ2 0x000003E0U
1498 #define ADC_SQR3_SQ2_0 0x00000020U
1499 #define ADC_SQR3_SQ2_1 0x00000040U
1500 #define ADC_SQR3_SQ2_2 0x00000080U
1501 #define ADC_SQR3_SQ2_3 0x00000100U
1502 #define ADC_SQR3_SQ2_4 0x00000200U
1503 #define ADC_SQR3_SQ3 0x00007C00U
1504 #define ADC_SQR3_SQ3_0 0x00000400U
1505 #define ADC_SQR3_SQ3_1 0x00000800U
1506 #define ADC_SQR3_SQ3_2 0x00001000U
1507 #define ADC_SQR3_SQ3_3 0x00002000U
1508 #define ADC_SQR3_SQ3_4 0x00004000U
1509 #define ADC_SQR3_SQ4 0x000F8000U
1510 #define ADC_SQR3_SQ4_0 0x00008000U
1511 #define ADC_SQR3_SQ4_1 0x00010000U
1512 #define ADC_SQR3_SQ4_2 0x00020000U
1513 #define ADC_SQR3_SQ4_3 0x00040000U
1514 #define ADC_SQR3_SQ4_4 0x00080000U
1515 #define ADC_SQR3_SQ5 0x01F00000U
1516 #define ADC_SQR3_SQ5_0 0x00100000U
1517 #define ADC_SQR3_SQ5_1 0x00200000U
1518 #define ADC_SQR3_SQ5_2 0x00400000U
1519 #define ADC_SQR3_SQ5_3 0x00800000U
1520 #define ADC_SQR3_SQ5_4 0x01000000U
1521 #define ADC_SQR3_SQ6 0x3E000000U
1522 #define ADC_SQR3_SQ6_0 0x02000000U
1523 #define ADC_SQR3_SQ6_1 0x04000000U
1524 #define ADC_SQR3_SQ6_2 0x08000000U
1525 #define ADC_SQR3_SQ6_3 0x10000000U
1526 #define ADC_SQR3_SQ6_4 0x20000000U
1528 /******************* Bit definition for ADC_JSQR register *******************/
1529 #define ADC_JSQR_JSQ1 0x0000001FU
1530 #define ADC_JSQR_JSQ1_0 0x00000001U
1531 #define ADC_JSQR_JSQ1_1 0x00000002U
1532 #define ADC_JSQR_JSQ1_2 0x00000004U
1533 #define ADC_JSQR_JSQ1_3 0x00000008U
1534 #define ADC_JSQR_JSQ1_4 0x00000010U
1535 #define ADC_JSQR_JSQ2 0x000003E0U
1536 #define ADC_JSQR_JSQ2_0 0x00000020U
1537 #define ADC_JSQR_JSQ2_1 0x00000040U
1538 #define ADC_JSQR_JSQ2_2 0x00000080U
1539 #define ADC_JSQR_JSQ2_3 0x00000100U
1540 #define ADC_JSQR_JSQ2_4 0x00000200U
1541 #define ADC_JSQR_JSQ3 0x00007C00U
1542 #define ADC_JSQR_JSQ3_0 0x00000400U
1543 #define ADC_JSQR_JSQ3_1 0x00000800U
1544 #define ADC_JSQR_JSQ3_2 0x00001000U
1545 #define ADC_JSQR_JSQ3_3 0x00002000U
1546 #define ADC_JSQR_JSQ3_4 0x00004000U
1547 #define ADC_JSQR_JSQ4 0x000F8000U
1548 #define ADC_JSQR_JSQ4_0 0x00008000U
1549 #define ADC_JSQR_JSQ4_1 0x00010000U
1550 #define ADC_JSQR_JSQ4_2 0x00020000U
1551 #define ADC_JSQR_JSQ4_3 0x00040000U
1552 #define ADC_JSQR_JSQ4_4 0x00080000U
1553 #define ADC_JSQR_JL 0x00300000U
1554 #define ADC_JSQR_JL_0 0x00100000U
1555 #define ADC_JSQR_JL_1 0x00200000U
1557 /******************* Bit definition for ADC_JDR1 register *******************/
1558 #define ADC_JDR1_JDATA 0xFFFFU
1560 /******************* Bit definition for ADC_JDR2 register *******************/
1561 #define ADC_JDR2_JDATA 0xFFFFU
1563 /******************* Bit definition for ADC_JDR3 register *******************/
1564 #define ADC_JDR3_JDATA 0xFFFFU
1566 /******************* Bit definition for ADC_JDR4 register *******************/
1567 #define ADC_JDR4_JDATA 0xFFFFU
1569 /******************** Bit definition for ADC_DR register ********************/
1570 #define ADC_DR_DATA 0x0000FFFFU
1571 #define ADC_DR_ADC2DATA 0xFFFF0000U
1573 /******************* Bit definition for ADC_CSR register ********************/
1574 #define ADC_CSR_AWD1 0x00000001U
1575 #define ADC_CSR_EOC1 0x00000002U
1576 #define ADC_CSR_JEOC1 0x00000004U
1577 #define ADC_CSR_JSTRT1 0x00000008U
1578 #define ADC_CSR_STRT1 0x00000010U
1579 #define ADC_CSR_OVR1 0x00000020U
1580 #define ADC_CSR_AWD2 0x00000100U
1581 #define ADC_CSR_EOC2 0x00000200U
1582 #define ADC_CSR_JEOC2 0x00000400U
1583 #define ADC_CSR_JSTRT2 0x00000800U
1584 #define ADC_CSR_STRT2 0x00001000U
1585 #define ADC_CSR_OVR2 0x00002000U
1586 #define ADC_CSR_AWD3 0x00010000U
1587 #define ADC_CSR_EOC3 0x00020000U
1588 #define ADC_CSR_JEOC3 0x00040000U
1589 #define ADC_CSR_JSTRT3 0x00080000U
1590 #define ADC_CSR_STRT3 0x00100000U
1591 #define ADC_CSR_OVR3 0x00200000U
1593 /* Legacy defines */
1594 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1595 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1596 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1597 
1598 /******************* Bit definition for ADC_CCR register ********************/
1599 #define ADC_CCR_MULTI 0x0000001FU
1600 #define ADC_CCR_MULTI_0 0x00000001U
1601 #define ADC_CCR_MULTI_1 0x00000002U
1602 #define ADC_CCR_MULTI_2 0x00000004U
1603 #define ADC_CCR_MULTI_3 0x00000008U
1604 #define ADC_CCR_MULTI_4 0x00000010U
1605 #define ADC_CCR_DELAY 0x00000F00U
1606 #define ADC_CCR_DELAY_0 0x00000100U
1607 #define ADC_CCR_DELAY_1 0x00000200U
1608 #define ADC_CCR_DELAY_2 0x00000400U
1609 #define ADC_CCR_DELAY_3 0x00000800U
1610 #define ADC_CCR_DDS 0x00002000U
1611 #define ADC_CCR_DMA 0x0000C000U
1612 #define ADC_CCR_DMA_0 0x00004000U
1613 #define ADC_CCR_DMA_1 0x00008000U
1614 #define ADC_CCR_ADCPRE 0x00030000U
1615 #define ADC_CCR_ADCPRE_0 0x00010000U
1616 #define ADC_CCR_ADCPRE_1 0x00020000U
1617 #define ADC_CCR_VBATE 0x00400000U
1618 #define ADC_CCR_TSVREFE 0x00800000U
1620 /******************* Bit definition for ADC_CDR register ********************/
1621 #define ADC_CDR_DATA1 0x0000FFFFU
1622 #define ADC_CDR_DATA2 0xFFFF0000U
1624 /******************************************************************************/
1625 /* */
1626 /* Controller Area Network */
1627 /* */
1628 /******************************************************************************/
1630 /******************* Bit definition for CAN_MCR register ********************/
1631 #define CAN_MCR_INRQ 0x00000001U
1632 #define CAN_MCR_SLEEP 0x00000002U
1633 #define CAN_MCR_TXFP 0x00000004U
1634 #define CAN_MCR_RFLM 0x00000008U
1635 #define CAN_MCR_NART 0x00000010U
1636 #define CAN_MCR_AWUM 0x00000020U
1637 #define CAN_MCR_ABOM 0x00000040U
1638 #define CAN_MCR_TTCM 0x00000080U
1639 #define CAN_MCR_RESET 0x00008000U
1640 #define CAN_MCR_DBF 0x00010000U
1641 /******************* Bit definition for CAN_MSR register ********************/
1642 #define CAN_MSR_INAK 0x0001U
1643 #define CAN_MSR_SLAK 0x0002U
1644 #define CAN_MSR_ERRI 0x0004U
1645 #define CAN_MSR_WKUI 0x0008U
1646 #define CAN_MSR_SLAKI 0x0010U
1647 #define CAN_MSR_TXM 0x0100U
1648 #define CAN_MSR_RXM 0x0200U
1649 #define CAN_MSR_SAMP 0x0400U
1650 #define CAN_MSR_RX 0x0800U
1652 /******************* Bit definition for CAN_TSR register ********************/
1653 #define CAN_TSR_RQCP0 0x00000001U
1654 #define CAN_TSR_TXOK0 0x00000002U
1655 #define CAN_TSR_ALST0 0x00000004U
1656 #define CAN_TSR_TERR0 0x00000008U
1657 #define CAN_TSR_ABRQ0 0x00000080U
1658 #define CAN_TSR_RQCP1 0x00000100U
1659 #define CAN_TSR_TXOK1 0x00000200U
1660 #define CAN_TSR_ALST1 0x00000400U
1661 #define CAN_TSR_TERR1 0x00000800U
1662 #define CAN_TSR_ABRQ1 0x00008000U
1663 #define CAN_TSR_RQCP2 0x00010000U
1664 #define CAN_TSR_TXOK2 0x00020000U
1665 #define CAN_TSR_ALST2 0x00040000U
1666 #define CAN_TSR_TERR2 0x00080000U
1667 #define CAN_TSR_ABRQ2 0x00800000U
1668 #define CAN_TSR_CODE 0x03000000U
1670 #define CAN_TSR_TME 0x1C000000U
1671 #define CAN_TSR_TME0 0x04000000U
1672 #define CAN_TSR_TME1 0x08000000U
1673 #define CAN_TSR_TME2 0x10000000U
1675 #define CAN_TSR_LOW 0xE0000000U
1676 #define CAN_TSR_LOW0 0x20000000U
1677 #define CAN_TSR_LOW1 0x40000000U
1678 #define CAN_TSR_LOW2 0x80000000U
1680 /******************* Bit definition for CAN_RF0R register *******************/
1681 #define CAN_RF0R_FMP0 0x03U
1682 #define CAN_RF0R_FULL0 0x08U
1683 #define CAN_RF0R_FOVR0 0x10U
1684 #define CAN_RF0R_RFOM0 0x20U
1686 /******************* Bit definition for CAN_RF1R register *******************/
1687 #define CAN_RF1R_FMP1 0x03U
1688 #define CAN_RF1R_FULL1 0x08U
1689 #define CAN_RF1R_FOVR1 0x10U
1690 #define CAN_RF1R_RFOM1 0x20U
1692 /******************** Bit definition for CAN_IER register *******************/
1693 #define CAN_IER_TMEIE 0x00000001U
1694 #define CAN_IER_FMPIE0 0x00000002U
1695 #define CAN_IER_FFIE0 0x00000004U
1696 #define CAN_IER_FOVIE0 0x00000008U
1697 #define CAN_IER_FMPIE1 0x00000010U
1698 #define CAN_IER_FFIE1 0x00000020U
1699 #define CAN_IER_FOVIE1 0x00000040U
1700 #define CAN_IER_EWGIE 0x00000100U
1701 #define CAN_IER_EPVIE 0x00000200U
1702 #define CAN_IER_BOFIE 0x00000400U
1703 #define CAN_IER_LECIE 0x00000800U
1704 #define CAN_IER_ERRIE 0x00008000U
1705 #define CAN_IER_WKUIE 0x00010000U
1706 #define CAN_IER_SLKIE 0x00020000U
1707 #define CAN_IER_EWGIE 0x00000100U
1708 #define CAN_IER_EPVIE 0x00000200U
1709 #define CAN_IER_BOFIE 0x00000400U
1710 #define CAN_IER_LECIE 0x00000800U
1711 #define CAN_IER_ERRIE 0x00008000U
1714 /******************** Bit definition for CAN_ESR register *******************/
1715 #define CAN_ESR_EWGF 0x00000001U
1716 #define CAN_ESR_EPVF 0x00000002U
1717 #define CAN_ESR_BOFF 0x00000004U
1719 #define CAN_ESR_LEC 0x00000070U
1720 #define CAN_ESR_LEC_0 0x00000010U
1721 #define CAN_ESR_LEC_1 0x00000020U
1722 #define CAN_ESR_LEC_2 0x00000040U
1724 #define CAN_ESR_TEC 0x00FF0000U
1725 #define CAN_ESR_REC 0xFF000000U
1727 /******************* Bit definition for CAN_BTR register ********************/
1728 #define CAN_BTR_BRP 0x000003FFU
1729 #define CAN_BTR_TS1 0x000F0000U
1730 #define CAN_BTR_TS1_0 0x00010000U
1731 #define CAN_BTR_TS1_1 0x00020000U
1732 #define CAN_BTR_TS1_2 0x00040000U
1733 #define CAN_BTR_TS1_3 0x00080000U
1734 #define CAN_BTR_TS2 0x00700000U
1735 #define CAN_BTR_TS2_0 0x00100000U
1736 #define CAN_BTR_TS2_1 0x00200000U
1737 #define CAN_BTR_TS2_2 0x00400000U
1738 #define CAN_BTR_SJW 0x03000000U
1739 #define CAN_BTR_SJW_0 0x01000000U
1740 #define CAN_BTR_SJW_1 0x02000000U
1741 #define CAN_BTR_LBKM 0x40000000U
1742 #define CAN_BTR_SILM 0x80000000U
1746 /****************** Bit definition for CAN_TI0R register ********************/
1747 #define CAN_TI0R_TXRQ 0x00000001U
1748 #define CAN_TI0R_RTR 0x00000002U
1749 #define CAN_TI0R_IDE 0x00000004U
1750 #define CAN_TI0R_EXID 0x001FFFF8U
1751 #define CAN_TI0R_STID 0xFFE00000U
1753 /****************** Bit definition for CAN_TDT0R register *******************/
1754 #define CAN_TDT0R_DLC 0x0000000FU
1755 #define CAN_TDT0R_TGT 0x00000100U
1756 #define CAN_TDT0R_TIME 0xFFFF0000U
1758 /****************** Bit definition for CAN_TDL0R register *******************/
1759 #define CAN_TDL0R_DATA0 0x000000FFU
1760 #define CAN_TDL0R_DATA1 0x0000FF00U
1761 #define CAN_TDL0R_DATA2 0x00FF0000U
1762 #define CAN_TDL0R_DATA3 0xFF000000U
1764 /****************** Bit definition for CAN_TDH0R register *******************/
1765 #define CAN_TDH0R_DATA4 0x000000FFU
1766 #define CAN_TDH0R_DATA5 0x0000FF00U
1767 #define CAN_TDH0R_DATA6 0x00FF0000U
1768 #define CAN_TDH0R_DATA7 0xFF000000U
1770 /******************* Bit definition for CAN_TI1R register *******************/
1771 #define CAN_TI1R_TXRQ 0x00000001U
1772 #define CAN_TI1R_RTR 0x00000002U
1773 #define CAN_TI1R_IDE 0x00000004U
1774 #define CAN_TI1R_EXID 0x001FFFF8U
1775 #define CAN_TI1R_STID 0xFFE00000U
1777 /******************* Bit definition for CAN_TDT1R register ******************/
1778 #define CAN_TDT1R_DLC 0x0000000FU
1779 #define CAN_TDT1R_TGT 0x00000100U
1780 #define CAN_TDT1R_TIME 0xFFFF0000U
1782 /******************* Bit definition for CAN_TDL1R register ******************/
1783 #define CAN_TDL1R_DATA0 0x000000FFU
1784 #define CAN_TDL1R_DATA1 0x0000FF00U
1785 #define CAN_TDL1R_DATA2 0x00FF0000U
1786 #define CAN_TDL1R_DATA3 0xFF000000U
1788 /******************* Bit definition for CAN_TDH1R register ******************/
1789 #define CAN_TDH1R_DATA4 0x000000FFU
1790 #define CAN_TDH1R_DATA5 0x0000FF00U
1791 #define CAN_TDH1R_DATA6 0x00FF0000U
1792 #define CAN_TDH1R_DATA7 0xFF000000U
1794 /******************* Bit definition for CAN_TI2R register *******************/
1795 #define CAN_TI2R_TXRQ 0x00000001U
1796 #define CAN_TI2R_RTR 0x00000002U
1797 #define CAN_TI2R_IDE 0x00000004U
1798 #define CAN_TI2R_EXID 0x001FFFF8U
1799 #define CAN_TI2R_STID 0xFFE00000U
1801 /******************* Bit definition for CAN_TDT2R register ******************/
1802 #define CAN_TDT2R_DLC 0x0000000FU
1803 #define CAN_TDT2R_TGT 0x00000100U
1804 #define CAN_TDT2R_TIME 0xFFFF0000U
1806 /******************* Bit definition for CAN_TDL2R register ******************/
1807 #define CAN_TDL2R_DATA0 0x000000FFU
1808 #define CAN_TDL2R_DATA1 0x0000FF00U
1809 #define CAN_TDL2R_DATA2 0x00FF0000U
1810 #define CAN_TDL2R_DATA3 0xFF000000U
1812 /******************* Bit definition for CAN_TDH2R register ******************/
1813 #define CAN_TDH2R_DATA4 0x000000FFU
1814 #define CAN_TDH2R_DATA5 0x0000FF00U
1815 #define CAN_TDH2R_DATA6 0x00FF0000U
1816 #define CAN_TDH2R_DATA7 0xFF000000U
1818 /******************* Bit definition for CAN_RI0R register *******************/
1819 #define CAN_RI0R_RTR 0x00000002U
1820 #define CAN_RI0R_IDE 0x00000004U
1821 #define CAN_RI0R_EXID 0x001FFFF8U
1822 #define CAN_RI0R_STID 0xFFE00000U
1824 /******************* Bit definition for CAN_RDT0R register ******************/
1825 #define CAN_RDT0R_DLC 0x0000000FU
1826 #define CAN_RDT0R_FMI 0x0000FF00U
1827 #define CAN_RDT0R_TIME 0xFFFF0000U
1829 /******************* Bit definition for CAN_RDL0R register ******************/
1830 #define CAN_RDL0R_DATA0 0x000000FFU
1831 #define CAN_RDL0R_DATA1 0x0000FF00U
1832 #define CAN_RDL0R_DATA2 0x00FF0000U
1833 #define CAN_RDL0R_DATA3 0xFF000000U
1835 /******************* Bit definition for CAN_RDH0R register ******************/
1836 #define CAN_RDH0R_DATA4 0x000000FFU
1837 #define CAN_RDH0R_DATA5 0x0000FF00U
1838 #define CAN_RDH0R_DATA6 0x00FF0000U
1839 #define CAN_RDH0R_DATA7 0xFF000000U
1841 /******************* Bit definition for CAN_RI1R register *******************/
1842 #define CAN_RI1R_RTR 0x00000002U
1843 #define CAN_RI1R_IDE 0x00000004U
1844 #define CAN_RI1R_EXID 0x001FFFF8U
1845 #define CAN_RI1R_STID 0xFFE00000U
1847 /******************* Bit definition for CAN_RDT1R register ******************/
1848 #define CAN_RDT1R_DLC 0x0000000FU
1849 #define CAN_RDT1R_FMI 0x0000FF00U
1850 #define CAN_RDT1R_TIME 0xFFFF0000U
1852 /******************* Bit definition for CAN_RDL1R register ******************/
1853 #define CAN_RDL1R_DATA0 0x000000FFU
1854 #define CAN_RDL1R_DATA1 0x0000FF00U
1855 #define CAN_RDL1R_DATA2 0x00FF0000U
1856 #define CAN_RDL1R_DATA3 0xFF000000U
1858 /******************* Bit definition for CAN_RDH1R register ******************/
1859 #define CAN_RDH1R_DATA4 0x000000FFU
1860 #define CAN_RDH1R_DATA5 0x0000FF00U
1861 #define CAN_RDH1R_DATA6 0x00FF0000U
1862 #define CAN_RDH1R_DATA7 0xFF000000U
1865 /******************* Bit definition for CAN_FMR register ********************/
1866 #define CAN_FMR_FINIT 0x01U
1867 #define CAN_FMR_CAN2SB 0x00003F00U
1869 /******************* Bit definition for CAN_FM1R register *******************/
1870 #define CAN_FM1R_FBM 0x0FFFFFFFU
1871 #define CAN_FM1R_FBM0 0x00000001U
1872 #define CAN_FM1R_FBM1 0x00000002U
1873 #define CAN_FM1R_FBM2 0x00000004U
1874 #define CAN_FM1R_FBM3 0x00000008U
1875 #define CAN_FM1R_FBM4 0x00000010U
1876 #define CAN_FM1R_FBM5 0x00000020U
1877 #define CAN_FM1R_FBM6 0x00000040U
1878 #define CAN_FM1R_FBM7 0x00000080U
1879 #define CAN_FM1R_FBM8 0x00000100U
1880 #define CAN_FM1R_FBM9 0x00000200U
1881 #define CAN_FM1R_FBM10 0x00000400U
1882 #define CAN_FM1R_FBM11 0x00000800U
1883 #define CAN_FM1R_FBM12 0x00001000U
1884 #define CAN_FM1R_FBM13 0x00002000U
1885 #define CAN_FM1R_FBM14 0x00004000U
1886 #define CAN_FM1R_FBM15 0x00008000U
1887 #define CAN_FM1R_FBM16 0x00010000U
1888 #define CAN_FM1R_FBM17 0x00020000U
1889 #define CAN_FM1R_FBM18 0x00040000U
1890 #define CAN_FM1R_FBM19 0x00080000U
1891 #define CAN_FM1R_FBM20 0x00100000U
1892 #define CAN_FM1R_FBM21 0x00200000U
1893 #define CAN_FM1R_FBM22 0x00400000U
1894 #define CAN_FM1R_FBM23 0x00800000U
1895 #define CAN_FM1R_FBM24 0x01000000U
1896 #define CAN_FM1R_FBM25 0x02000000U
1897 #define CAN_FM1R_FBM26 0x04000000U
1898 #define CAN_FM1R_FBM27 0x08000000U
1900 /******************* Bit definition for CAN_FS1R register *******************/
1901 #define CAN_FS1R_FSC 0x0FFFFFFFU
1902 #define CAN_FS1R_FSC0 0x00000001U
1903 #define CAN_FS1R_FSC1 0x00000002U
1904 #define CAN_FS1R_FSC2 0x00000004U
1905 #define CAN_FS1R_FSC3 0x00000008U
1906 #define CAN_FS1R_FSC4 0x00000010U
1907 #define CAN_FS1R_FSC5 0x00000020U
1908 #define CAN_FS1R_FSC6 0x00000040U
1909 #define CAN_FS1R_FSC7 0x00000080U
1910 #define CAN_FS1R_FSC8 0x00000100U
1911 #define CAN_FS1R_FSC9 0x00000200U
1912 #define CAN_FS1R_FSC10 0x00000400U
1913 #define CAN_FS1R_FSC11 0x00000800U
1914 #define CAN_FS1R_FSC12 0x00001000U
1915 #define CAN_FS1R_FSC13 0x00002000U
1916 #define CAN_FS1R_FSC14 0x00004000U
1917 #define CAN_FS1R_FSC15 0x00008000U
1918 #define CAN_FS1R_FSC16 0x00010000U
1919 #define CAN_FS1R_FSC17 0x00020000U
1920 #define CAN_FS1R_FSC18 0x00040000U
1921 #define CAN_FS1R_FSC19 0x00080000U
1922 #define CAN_FS1R_FSC20 0x00100000U
1923 #define CAN_FS1R_FSC21 0x00200000U
1924 #define CAN_FS1R_FSC22 0x00400000U
1925 #define CAN_FS1R_FSC23 0x00800000U
1926 #define CAN_FS1R_FSC24 0x01000000U
1927 #define CAN_FS1R_FSC25 0x02000000U
1928 #define CAN_FS1R_FSC26 0x04000000U
1929 #define CAN_FS1R_FSC27 0x08000000U
1931 /****************** Bit definition for CAN_FFA1R register *******************/
1932 #define CAN_FFA1R_FFA 0x0FFFFFFFU
1933 #define CAN_FFA1R_FFA0 0x00000001U
1934 #define CAN_FFA1R_FFA1 0x00000002U
1935 #define CAN_FFA1R_FFA2 0x00000004U
1936 #define CAN_FFA1R_FFA3 0x00000008U
1937 #define CAN_FFA1R_FFA4 0x00000010U
1938 #define CAN_FFA1R_FFA5 0x00000020U
1939 #define CAN_FFA1R_FFA6 0x00000040U
1940 #define CAN_FFA1R_FFA7 0x00000080U
1941 #define CAN_FFA1R_FFA8 0x00000100U
1942 #define CAN_FFA1R_FFA9 0x00000200U
1943 #define CAN_FFA1R_FFA10 0x00000400U
1944 #define CAN_FFA1R_FFA11 0x00000800U
1945 #define CAN_FFA1R_FFA12 0x00001000U
1946 #define CAN_FFA1R_FFA13 0x00002000U
1947 #define CAN_FFA1R_FFA14 0x00004000U
1948 #define CAN_FFA1R_FFA15 0x00008000U
1949 #define CAN_FFA1R_FFA16 0x00010000U
1950 #define CAN_FFA1R_FFA17 0x00020000U
1951 #define CAN_FFA1R_FFA18 0x00040000U
1952 #define CAN_FFA1R_FFA19 0x00080000U
1953 #define CAN_FFA1R_FFA20 0x00100000U
1954 #define CAN_FFA1R_FFA21 0x00200000U
1955 #define CAN_FFA1R_FFA22 0x00400000U
1956 #define CAN_FFA1R_FFA23 0x00800000U
1957 #define CAN_FFA1R_FFA24 0x01000000U
1958 #define CAN_FFA1R_FFA25 0x02000000U
1959 #define CAN_FFA1R_FFA26 0x04000000U
1960 #define CAN_FFA1R_FFA27 0x08000000U
1962 /******************* Bit definition for CAN_FA1R register *******************/
1963 #define CAN_FA1R_FACT 0x0FFFFFFFU
1964 #define CAN_FA1R_FACT0 0x00000001U
1965 #define CAN_FA1R_FACT1 0x00000002U
1966 #define CAN_FA1R_FACT2 0x00000004U
1967 #define CAN_FA1R_FACT3 0x00000008U
1968 #define CAN_FA1R_FACT4 0x00000010U
1969 #define CAN_FA1R_FACT5 0x00000020U
1970 #define CAN_FA1R_FACT6 0x00000040U
1971 #define CAN_FA1R_FACT7 0x00000080U
1972 #define CAN_FA1R_FACT8 0x00000100U
1973 #define CAN_FA1R_FACT9 0x00000200U
1974 #define CAN_FA1R_FACT10 0x00000400U
1975 #define CAN_FA1R_FACT11 0x00000800U
1976 #define CAN_FA1R_FACT12 0x00001000U
1977 #define CAN_FA1R_FACT13 0x00002000U
1978 #define CAN_FA1R_FACT14 0x00004000U
1979 #define CAN_FA1R_FACT15 0x00008000U
1980 #define CAN_FA1R_FACT16 0x00010000U
1981 #define CAN_FA1R_FACT17 0x00020000U
1982 #define CAN_FA1R_FACT18 0x00040000U
1983 #define CAN_FA1R_FACT19 0x00080000U
1984 #define CAN_FA1R_FACT20 0x00100000U
1985 #define CAN_FA1R_FACT21 0x00200000U
1986 #define CAN_FA1R_FACT22 0x00400000U
1987 #define CAN_FA1R_FACT23 0x00800000U
1988 #define CAN_FA1R_FACT24 0x01000000U
1989 #define CAN_FA1R_FACT25 0x02000000U
1990 #define CAN_FA1R_FACT26 0x04000000U
1991 #define CAN_FA1R_FACT27 0x08000000U
1993 /******************* Bit definition for CAN_F0R1 register *******************/
1994 #define CAN_F0R1_FB0 0x00000001U
1995 #define CAN_F0R1_FB1 0x00000002U
1996 #define CAN_F0R1_FB2 0x00000004U
1997 #define CAN_F0R1_FB3 0x00000008U
1998 #define CAN_F0R1_FB4 0x00000010U
1999 #define CAN_F0R1_FB5 0x00000020U
2000 #define CAN_F0R1_FB6 0x00000040U
2001 #define CAN_F0R1_FB7 0x00000080U
2002 #define CAN_F0R1_FB8 0x00000100U
2003 #define CAN_F0R1_FB9 0x00000200U
2004 #define CAN_F0R1_FB10 0x00000400U
2005 #define CAN_F0R1_FB11 0x00000800U
2006 #define CAN_F0R1_FB12 0x00001000U
2007 #define CAN_F0R1_FB13 0x00002000U
2008 #define CAN_F0R1_FB14 0x00004000U
2009 #define CAN_F0R1_FB15 0x00008000U
2010 #define CAN_F0R1_FB16 0x00010000U
2011 #define CAN_F0R1_FB17 0x00020000U
2012 #define CAN_F0R1_FB18 0x00040000U
2013 #define CAN_F0R1_FB19 0x00080000U
2014 #define CAN_F0R1_FB20 0x00100000U
2015 #define CAN_F0R1_FB21 0x00200000U
2016 #define CAN_F0R1_FB22 0x00400000U
2017 #define CAN_F0R1_FB23 0x00800000U
2018 #define CAN_F0R1_FB24 0x01000000U
2019 #define CAN_F0R1_FB25 0x02000000U
2020 #define CAN_F0R1_FB26 0x04000000U
2021 #define CAN_F0R1_FB27 0x08000000U
2022 #define CAN_F0R1_FB28 0x10000000U
2023 #define CAN_F0R1_FB29 0x20000000U
2024 #define CAN_F0R1_FB30 0x40000000U
2025 #define CAN_F0R1_FB31 0x80000000U
2027 /******************* Bit definition for CAN_F1R1 register *******************/
2028 #define CAN_F1R1_FB0 0x00000001U
2029 #define CAN_F1R1_FB1 0x00000002U
2030 #define CAN_F1R1_FB2 0x00000004U
2031 #define CAN_F1R1_FB3 0x00000008U
2032 #define CAN_F1R1_FB4 0x00000010U
2033 #define CAN_F1R1_FB5 0x00000020U
2034 #define CAN_F1R1_FB6 0x00000040U
2035 #define CAN_F1R1_FB7 0x00000080U
2036 #define CAN_F1R1_FB8 0x00000100U
2037 #define CAN_F1R1_FB9 0x00000200U
2038 #define CAN_F1R1_FB10 0x00000400U
2039 #define CAN_F1R1_FB11 0x00000800U
2040 #define CAN_F1R1_FB12 0x00001000U
2041 #define CAN_F1R1_FB13 0x00002000U
2042 #define CAN_F1R1_FB14 0x00004000U
2043 #define CAN_F1R1_FB15 0x00008000U
2044 #define CAN_F1R1_FB16 0x00010000U
2045 #define CAN_F1R1_FB17 0x00020000U
2046 #define CAN_F1R1_FB18 0x00040000U
2047 #define CAN_F1R1_FB19 0x00080000U
2048 #define CAN_F1R1_FB20 0x00100000U
2049 #define CAN_F1R1_FB21 0x00200000U
2050 #define CAN_F1R1_FB22 0x00400000U
2051 #define CAN_F1R1_FB23 0x00800000U
2052 #define CAN_F1R1_FB24 0x01000000U
2053 #define CAN_F1R1_FB25 0x02000000U
2054 #define CAN_F1R1_FB26 0x04000000U
2055 #define CAN_F1R1_FB27 0x08000000U
2056 #define CAN_F1R1_FB28 0x10000000U
2057 #define CAN_F1R1_FB29 0x20000000U
2058 #define CAN_F1R1_FB30 0x40000000U
2059 #define CAN_F1R1_FB31 0x80000000U
2061 /******************* Bit definition for CAN_F2R1 register *******************/
2062 #define CAN_F2R1_FB0 0x00000001U
2063 #define CAN_F2R1_FB1 0x00000002U
2064 #define CAN_F2R1_FB2 0x00000004U
2065 #define CAN_F2R1_FB3 0x00000008U
2066 #define CAN_F2R1_FB4 0x00000010U
2067 #define CAN_F2R1_FB5 0x00000020U
2068 #define CAN_F2R1_FB6 0x00000040U
2069 #define CAN_F2R1_FB7 0x00000080U
2070 #define CAN_F2R1_FB8 0x00000100U
2071 #define CAN_F2R1_FB9 0x00000200U
2072 #define CAN_F2R1_FB10 0x00000400U
2073 #define CAN_F2R1_FB11 0x00000800U
2074 #define CAN_F2R1_FB12 0x00001000U
2075 #define CAN_F2R1_FB13 0x00002000U
2076 #define CAN_F2R1_FB14 0x00004000U
2077 #define CAN_F2R1_FB15 0x00008000U
2078 #define CAN_F2R1_FB16 0x00010000U
2079 #define CAN_F2R1_FB17 0x00020000U
2080 #define CAN_F2R1_FB18 0x00040000U
2081 #define CAN_F2R1_FB19 0x00080000U
2082 #define CAN_F2R1_FB20 0x00100000U
2083 #define CAN_F2R1_FB21 0x00200000U
2084 #define CAN_F2R1_FB22 0x00400000U
2085 #define CAN_F2R1_FB23 0x00800000U
2086 #define CAN_F2R1_FB24 0x01000000U
2087 #define CAN_F2R1_FB25 0x02000000U
2088 #define CAN_F2R1_FB26 0x04000000U
2089 #define CAN_F2R1_FB27 0x08000000U
2090 #define CAN_F2R1_FB28 0x10000000U
2091 #define CAN_F2R1_FB29 0x20000000U
2092 #define CAN_F2R1_FB30 0x40000000U
2093 #define CAN_F2R1_FB31 0x80000000U
2095 /******************* Bit definition for CAN_F3R1 register *******************/
2096 #define CAN_F3R1_FB0 0x00000001U
2097 #define CAN_F3R1_FB1 0x00000002U
2098 #define CAN_F3R1_FB2 0x00000004U
2099 #define CAN_F3R1_FB3 0x00000008U
2100 #define CAN_F3R1_FB4 0x00000010U
2101 #define CAN_F3R1_FB5 0x00000020U
2102 #define CAN_F3R1_FB6 0x00000040U
2103 #define CAN_F3R1_FB7 0x00000080U
2104 #define CAN_F3R1_FB8 0x00000100U
2105 #define CAN_F3R1_FB9 0x00000200U
2106 #define CAN_F3R1_FB10 0x00000400U
2107 #define CAN_F3R1_FB11 0x00000800U
2108 #define CAN_F3R1_FB12 0x00001000U
2109 #define CAN_F3R1_FB13 0x00002000U
2110 #define CAN_F3R1_FB14 0x00004000U
2111 #define CAN_F3R1_FB15 0x00008000U
2112 #define CAN_F3R1_FB16 0x00010000U
2113 #define CAN_F3R1_FB17 0x00020000U
2114 #define CAN_F3R1_FB18 0x00040000U
2115 #define CAN_F3R1_FB19 0x00080000U
2116 #define CAN_F3R1_FB20 0x00100000U
2117 #define CAN_F3R1_FB21 0x00200000U
2118 #define CAN_F3R1_FB22 0x00400000U
2119 #define CAN_F3R1_FB23 0x00800000U
2120 #define CAN_F3R1_FB24 0x01000000U
2121 #define CAN_F3R1_FB25 0x02000000U
2122 #define CAN_F3R1_FB26 0x04000000U
2123 #define CAN_F3R1_FB27 0x08000000U
2124 #define CAN_F3R1_FB28 0x10000000U
2125 #define CAN_F3R1_FB29 0x20000000U
2126 #define CAN_F3R1_FB30 0x40000000U
2127 #define CAN_F3R1_FB31 0x80000000U
2129 /******************* Bit definition for CAN_F4R1 register *******************/
2130 #define CAN_F4R1_FB0 0x00000001U
2131 #define CAN_F4R1_FB1 0x00000002U
2132 #define CAN_F4R1_FB2 0x00000004U
2133 #define CAN_F4R1_FB3 0x00000008U
2134 #define CAN_F4R1_FB4 0x00000010U
2135 #define CAN_F4R1_FB5 0x00000020U
2136 #define CAN_F4R1_FB6 0x00000040U
2137 #define CAN_F4R1_FB7 0x00000080U
2138 #define CAN_F4R1_FB8 0x00000100U
2139 #define CAN_F4R1_FB9 0x00000200U
2140 #define CAN_F4R1_FB10 0x00000400U
2141 #define CAN_F4R1_FB11 0x00000800U
2142 #define CAN_F4R1_FB12 0x00001000U
2143 #define CAN_F4R1_FB13 0x00002000U
2144 #define CAN_F4R1_FB14 0x00004000U
2145 #define CAN_F4R1_FB15 0x00008000U
2146 #define CAN_F4R1_FB16 0x00010000U
2147 #define CAN_F4R1_FB17 0x00020000U
2148 #define CAN_F4R1_FB18 0x00040000U
2149 #define CAN_F4R1_FB19 0x00080000U
2150 #define CAN_F4R1_FB20 0x00100000U
2151 #define CAN_F4R1_FB21 0x00200000U
2152 #define CAN_F4R1_FB22 0x00400000U
2153 #define CAN_F4R1_FB23 0x00800000U
2154 #define CAN_F4R1_FB24 0x01000000U
2155 #define CAN_F4R1_FB25 0x02000000U
2156 #define CAN_F4R1_FB26 0x04000000U
2157 #define CAN_F4R1_FB27 0x08000000U
2158 #define CAN_F4R1_FB28 0x10000000U
2159 #define CAN_F4R1_FB29 0x20000000U
2160 #define CAN_F4R1_FB30 0x40000000U
2161 #define CAN_F4R1_FB31 0x80000000U
2163 /******************* Bit definition for CAN_F5R1 register *******************/
2164 #define CAN_F5R1_FB0 0x00000001U
2165 #define CAN_F5R1_FB1 0x00000002U
2166 #define CAN_F5R1_FB2 0x00000004U
2167 #define CAN_F5R1_FB3 0x00000008U
2168 #define CAN_F5R1_FB4 0x00000010U
2169 #define CAN_F5R1_FB5 0x00000020U
2170 #define CAN_F5R1_FB6 0x00000040U
2171 #define CAN_F5R1_FB7 0x00000080U
2172 #define CAN_F5R1_FB8 0x00000100U
2173 #define CAN_F5R1_FB9 0x00000200U
2174 #define CAN_F5R1_FB10 0x00000400U
2175 #define CAN_F5R1_FB11 0x00000800U
2176 #define CAN_F5R1_FB12 0x00001000U
2177 #define CAN_F5R1_FB13 0x00002000U
2178 #define CAN_F5R1_FB14 0x00004000U
2179 #define CAN_F5R1_FB15 0x00008000U
2180 #define CAN_F5R1_FB16 0x00010000U
2181 #define CAN_F5R1_FB17 0x00020000U
2182 #define CAN_F5R1_FB18 0x00040000U
2183 #define CAN_F5R1_FB19 0x00080000U
2184 #define CAN_F5R1_FB20 0x00100000U
2185 #define CAN_F5R1_FB21 0x00200000U
2186 #define CAN_F5R1_FB22 0x00400000U
2187 #define CAN_F5R1_FB23 0x00800000U
2188 #define CAN_F5R1_FB24 0x01000000U
2189 #define CAN_F5R1_FB25 0x02000000U
2190 #define CAN_F5R1_FB26 0x04000000U
2191 #define CAN_F5R1_FB27 0x08000000U
2192 #define CAN_F5R1_FB28 0x10000000U
2193 #define CAN_F5R1_FB29 0x20000000U
2194 #define CAN_F5R1_FB30 0x40000000U
2195 #define CAN_F5R1_FB31 0x80000000U
2197 /******************* Bit definition for CAN_F6R1 register *******************/
2198 #define CAN_F6R1_FB0 0x00000001U
2199 #define CAN_F6R1_FB1 0x00000002U
2200 #define CAN_F6R1_FB2 0x00000004U
2201 #define CAN_F6R1_FB3 0x00000008U
2202 #define CAN_F6R1_FB4 0x00000010U
2203 #define CAN_F6R1_FB5 0x00000020U
2204 #define CAN_F6R1_FB6 0x00000040U
2205 #define CAN_F6R1_FB7 0x00000080U
2206 #define CAN_F6R1_FB8 0x00000100U
2207 #define CAN_F6R1_FB9 0x00000200U
2208 #define CAN_F6R1_FB10 0x00000400U
2209 #define CAN_F6R1_FB11 0x00000800U
2210 #define CAN_F6R1_FB12 0x00001000U
2211 #define CAN_F6R1_FB13 0x00002000U
2212 #define CAN_F6R1_FB14 0x00004000U
2213 #define CAN_F6R1_FB15 0x00008000U
2214 #define CAN_F6R1_FB16 0x00010000U
2215 #define CAN_F6R1_FB17 0x00020000U
2216 #define CAN_F6R1_FB18 0x00040000U
2217 #define CAN_F6R1_FB19 0x00080000U
2218 #define CAN_F6R1_FB20 0x00100000U
2219 #define CAN_F6R1_FB21 0x00200000U
2220 #define CAN_F6R1_FB22 0x00400000U
2221 #define CAN_F6R1_FB23 0x00800000U
2222 #define CAN_F6R1_FB24 0x01000000U
2223 #define CAN_F6R1_FB25 0x02000000U
2224 #define CAN_F6R1_FB26 0x04000000U
2225 #define CAN_F6R1_FB27 0x08000000U
2226 #define CAN_F6R1_FB28 0x10000000U
2227 #define CAN_F6R1_FB29 0x20000000U
2228 #define CAN_F6R1_FB30 0x40000000U
2229 #define CAN_F6R1_FB31 0x80000000U
2231 /******************* Bit definition for CAN_F7R1 register *******************/
2232 #define CAN_F7R1_FB0 0x00000001U
2233 #define CAN_F7R1_FB1 0x00000002U
2234 #define CAN_F7R1_FB2 0x00000004U
2235 #define CAN_F7R1_FB3 0x00000008U
2236 #define CAN_F7R1_FB4 0x00000010U
2237 #define CAN_F7R1_FB5 0x00000020U
2238 #define CAN_F7R1_FB6 0x00000040U
2239 #define CAN_F7R1_FB7 0x00000080U
2240 #define CAN_F7R1_FB8 0x00000100U
2241 #define CAN_F7R1_FB9 0x00000200U
2242 #define CAN_F7R1_FB10 0x00000400U
2243 #define CAN_F7R1_FB11 0x00000800U
2244 #define CAN_F7R1_FB12 0x00001000U
2245 #define CAN_F7R1_FB13 0x00002000U
2246 #define CAN_F7R1_FB14 0x00004000U
2247 #define CAN_F7R1_FB15 0x00008000U
2248 #define CAN_F7R1_FB16 0x00010000U
2249 #define CAN_F7R1_FB17 0x00020000U
2250 #define CAN_F7R1_FB18 0x00040000U
2251 #define CAN_F7R1_FB19 0x00080000U
2252 #define CAN_F7R1_FB20 0x00100000U
2253 #define CAN_F7R1_FB21 0x00200000U
2254 #define CAN_F7R1_FB22 0x00400000U
2255 #define CAN_F7R1_FB23 0x00800000U
2256 #define CAN_F7R1_FB24 0x01000000U
2257 #define CAN_F7R1_FB25 0x02000000U
2258 #define CAN_F7R1_FB26 0x04000000U
2259 #define CAN_F7R1_FB27 0x08000000U
2260 #define CAN_F7R1_FB28 0x10000000U
2261 #define CAN_F7R1_FB29 0x20000000U
2262 #define CAN_F7R1_FB30 0x40000000U
2263 #define CAN_F7R1_FB31 0x80000000U
2265 /******************* Bit definition for CAN_F8R1 register *******************/
2266 #define CAN_F8R1_FB0 0x00000001U
2267 #define CAN_F8R1_FB1 0x00000002U
2268 #define CAN_F8R1_FB2 0x00000004U
2269 #define CAN_F8R1_FB3 0x00000008U
2270 #define CAN_F8R1_FB4 0x00000010U
2271 #define CAN_F8R1_FB5 0x00000020U
2272 #define CAN_F8R1_FB6 0x00000040U
2273 #define CAN_F8R1_FB7 0x00000080U
2274 #define CAN_F8R1_FB8 0x00000100U
2275 #define CAN_F8R1_FB9 0x00000200U
2276 #define CAN_F8R1_FB10 0x00000400U
2277 #define CAN_F8R1_FB11 0x00000800U
2278 #define CAN_F8R1_FB12 0x00001000U
2279 #define CAN_F8R1_FB13 0x00002000U
2280 #define CAN_F8R1_FB14 0x00004000U
2281 #define CAN_F8R1_FB15 0x00008000U
2282 #define CAN_F8R1_FB16 0x00010000U
2283 #define CAN_F8R1_FB17 0x00020000U
2284 #define CAN_F8R1_FB18 0x00040000U
2285 #define CAN_F8R1_FB19 0x00080000U
2286 #define CAN_F8R1_FB20 0x00100000U
2287 #define CAN_F8R1_FB21 0x00200000U
2288 #define CAN_F8R1_FB22 0x00400000U
2289 #define CAN_F8R1_FB23 0x00800000U
2290 #define CAN_F8R1_FB24 0x01000000U
2291 #define CAN_F8R1_FB25 0x02000000U
2292 #define CAN_F8R1_FB26 0x04000000U
2293 #define CAN_F8R1_FB27 0x08000000U
2294 #define CAN_F8R1_FB28 0x10000000U
2295 #define CAN_F8R1_FB29 0x20000000U
2296 #define CAN_F8R1_FB30 0x40000000U
2297 #define CAN_F8R1_FB31 0x80000000U
2299 /******************* Bit definition for CAN_F9R1 register *******************/
2300 #define CAN_F9R1_FB0 0x00000001U
2301 #define CAN_F9R1_FB1 0x00000002U
2302 #define CAN_F9R1_FB2 0x00000004U
2303 #define CAN_F9R1_FB3 0x00000008U
2304 #define CAN_F9R1_FB4 0x00000010U
2305 #define CAN_F9R1_FB5 0x00000020U
2306 #define CAN_F9R1_FB6 0x00000040U
2307 #define CAN_F9R1_FB7 0x00000080U
2308 #define CAN_F9R1_FB8 0x00000100U
2309 #define CAN_F9R1_FB9 0x00000200U
2310 #define CAN_F9R1_FB10 0x00000400U
2311 #define CAN_F9R1_FB11 0x00000800U
2312 #define CAN_F9R1_FB12 0x00001000U
2313 #define CAN_F9R1_FB13 0x00002000U
2314 #define CAN_F9R1_FB14 0x00004000U
2315 #define CAN_F9R1_FB15 0x00008000U
2316 #define CAN_F9R1_FB16 0x00010000U
2317 #define CAN_F9R1_FB17 0x00020000U
2318 #define CAN_F9R1_FB18 0x00040000U
2319 #define CAN_F9R1_FB19 0x00080000U
2320 #define CAN_F9R1_FB20 0x00100000U
2321 #define CAN_F9R1_FB21 0x00200000U
2322 #define CAN_F9R1_FB22 0x00400000U
2323 #define CAN_F9R1_FB23 0x00800000U
2324 #define CAN_F9R1_FB24 0x01000000U
2325 #define CAN_F9R1_FB25 0x02000000U
2326 #define CAN_F9R1_FB26 0x04000000U
2327 #define CAN_F9R1_FB27 0x08000000U
2328 #define CAN_F9R1_FB28 0x10000000U
2329 #define CAN_F9R1_FB29 0x20000000U
2330 #define CAN_F9R1_FB30 0x40000000U
2331 #define CAN_F9R1_FB31 0x80000000U
2333 /******************* Bit definition for CAN_F10R1 register ******************/
2334 #define CAN_F10R1_FB0 0x00000001U
2335 #define CAN_F10R1_FB1 0x00000002U
2336 #define CAN_F10R1_FB2 0x00000004U
2337 #define CAN_F10R1_FB3 0x00000008U
2338 #define CAN_F10R1_FB4 0x00000010U
2339 #define CAN_F10R1_FB5 0x00000020U
2340 #define CAN_F10R1_FB6 0x00000040U
2341 #define CAN_F10R1_FB7 0x00000080U
2342 #define CAN_F10R1_FB8 0x00000100U
2343 #define CAN_F10R1_FB9 0x00000200U
2344 #define CAN_F10R1_FB10 0x00000400U
2345 #define CAN_F10R1_FB11 0x00000800U
2346 #define CAN_F10R1_FB12 0x00001000U
2347 #define CAN_F10R1_FB13 0x00002000U
2348 #define CAN_F10R1_FB14 0x00004000U
2349 #define CAN_F10R1_FB15 0x00008000U
2350 #define CAN_F10R1_FB16 0x00010000U
2351 #define CAN_F10R1_FB17 0x00020000U
2352 #define CAN_F10R1_FB18 0x00040000U
2353 #define CAN_F10R1_FB19 0x00080000U
2354 #define CAN_F10R1_FB20 0x00100000U
2355 #define CAN_F10R1_FB21 0x00200000U
2356 #define CAN_F10R1_FB22 0x00400000U
2357 #define CAN_F10R1_FB23 0x00800000U
2358 #define CAN_F10R1_FB24 0x01000000U
2359 #define CAN_F10R1_FB25 0x02000000U
2360 #define CAN_F10R1_FB26 0x04000000U
2361 #define CAN_F10R1_FB27 0x08000000U
2362 #define CAN_F10R1_FB28 0x10000000U
2363 #define CAN_F10R1_FB29 0x20000000U
2364 #define CAN_F10R1_FB30 0x40000000U
2365 #define CAN_F10R1_FB31 0x80000000U
2367 /******************* Bit definition for CAN_F11R1 register ******************/
2368 #define CAN_F11R1_FB0 0x00000001U
2369 #define CAN_F11R1_FB1 0x00000002U
2370 #define CAN_F11R1_FB2 0x00000004U
2371 #define CAN_F11R1_FB3 0x00000008U
2372 #define CAN_F11R1_FB4 0x00000010U
2373 #define CAN_F11R1_FB5 0x00000020U
2374 #define CAN_F11R1_FB6 0x00000040U
2375 #define CAN_F11R1_FB7 0x00000080U
2376 #define CAN_F11R1_FB8 0x00000100U
2377 #define CAN_F11R1_FB9 0x00000200U
2378 #define CAN_F11R1_FB10 0x00000400U
2379 #define CAN_F11R1_FB11 0x00000800U
2380 #define CAN_F11R1_FB12 0x00001000U
2381 #define CAN_F11R1_FB13 0x00002000U
2382 #define CAN_F11R1_FB14 0x00004000U
2383 #define CAN_F11R1_FB15 0x00008000U
2384 #define CAN_F11R1_FB16 0x00010000U
2385 #define CAN_F11R1_FB17 0x00020000U
2386 #define CAN_F11R1_FB18 0x00040000U
2387 #define CAN_F11R1_FB19 0x00080000U
2388 #define CAN_F11R1_FB20 0x00100000U
2389 #define CAN_F11R1_FB21 0x00200000U
2390 #define CAN_F11R1_FB22 0x00400000U
2391 #define CAN_F11R1_FB23 0x00800000U
2392 #define CAN_F11R1_FB24 0x01000000U
2393 #define CAN_F11R1_FB25 0x02000000U
2394 #define CAN_F11R1_FB26 0x04000000U
2395 #define CAN_F11R1_FB27 0x08000000U
2396 #define CAN_F11R1_FB28 0x10000000U
2397 #define CAN_F11R1_FB29 0x20000000U
2398 #define CAN_F11R1_FB30 0x40000000U
2399 #define CAN_F11R1_FB31 0x80000000U
2401 /******************* Bit definition for CAN_F12R1 register ******************/
2402 #define CAN_F12R1_FB0 0x00000001U
2403 #define CAN_F12R1_FB1 0x00000002U
2404 #define CAN_F12R1_FB2 0x00000004U
2405 #define CAN_F12R1_FB3 0x00000008U
2406 #define CAN_F12R1_FB4 0x00000010U
2407 #define CAN_F12R1_FB5 0x00000020U
2408 #define CAN_F12R1_FB6 0x00000040U
2409 #define CAN_F12R1_FB7 0x00000080U
2410 #define CAN_F12R1_FB8 0x00000100U
2411 #define CAN_F12R1_FB9 0x00000200U
2412 #define CAN_F12R1_FB10 0x00000400U
2413 #define CAN_F12R1_FB11 0x00000800U
2414 #define CAN_F12R1_FB12 0x00001000U
2415 #define CAN_F12R1_FB13 0x00002000U
2416 #define CAN_F12R1_FB14 0x00004000U
2417 #define CAN_F12R1_FB15 0x00008000U
2418 #define CAN_F12R1_FB16 0x00010000U
2419 #define CAN_F12R1_FB17 0x00020000U
2420 #define CAN_F12R1_FB18 0x00040000U
2421 #define CAN_F12R1_FB19 0x00080000U
2422 #define CAN_F12R1_FB20 0x00100000U
2423 #define CAN_F12R1_FB21 0x00200000U
2424 #define CAN_F12R1_FB22 0x00400000U
2425 #define CAN_F12R1_FB23 0x00800000U
2426 #define CAN_F12R1_FB24 0x01000000U
2427 #define CAN_F12R1_FB25 0x02000000U
2428 #define CAN_F12R1_FB26 0x04000000U
2429 #define CAN_F12R1_FB27 0x08000000U
2430 #define CAN_F12R1_FB28 0x10000000U
2431 #define CAN_F12R1_FB29 0x20000000U
2432 #define CAN_F12R1_FB30 0x40000000U
2433 #define CAN_F12R1_FB31 0x80000000U
2435 /******************* Bit definition for CAN_F13R1 register ******************/
2436 #define CAN_F13R1_FB0 0x00000001U
2437 #define CAN_F13R1_FB1 0x00000002U
2438 #define CAN_F13R1_FB2 0x00000004U
2439 #define CAN_F13R1_FB3 0x00000008U
2440 #define CAN_F13R1_FB4 0x00000010U
2441 #define CAN_F13R1_FB5 0x00000020U
2442 #define CAN_F13R1_FB6 0x00000040U
2443 #define CAN_F13R1_FB7 0x00000080U
2444 #define CAN_F13R1_FB8 0x00000100U
2445 #define CAN_F13R1_FB9 0x00000200U
2446 #define CAN_F13R1_FB10 0x00000400U
2447 #define CAN_F13R1_FB11 0x00000800U
2448 #define CAN_F13R1_FB12 0x00001000U
2449 #define CAN_F13R1_FB13 0x00002000U
2450 #define CAN_F13R1_FB14 0x00004000U
2451 #define CAN_F13R1_FB15 0x00008000U
2452 #define CAN_F13R1_FB16 0x00010000U
2453 #define CAN_F13R1_FB17 0x00020000U
2454 #define CAN_F13R1_FB18 0x00040000U
2455 #define CAN_F13R1_FB19 0x00080000U
2456 #define CAN_F13R1_FB20 0x00100000U
2457 #define CAN_F13R1_FB21 0x00200000U
2458 #define CAN_F13R1_FB22 0x00400000U
2459 #define CAN_F13R1_FB23 0x00800000U
2460 #define CAN_F13R1_FB24 0x01000000U
2461 #define CAN_F13R1_FB25 0x02000000U
2462 #define CAN_F13R1_FB26 0x04000000U
2463 #define CAN_F13R1_FB27 0x08000000U
2464 #define CAN_F13R1_FB28 0x10000000U
2465 #define CAN_F13R1_FB29 0x20000000U
2466 #define CAN_F13R1_FB30 0x40000000U
2467 #define CAN_F13R1_FB31 0x80000000U
2469 /******************* Bit definition for CAN_F0R2 register *******************/
2470 #define CAN_F0R2_FB0 0x00000001U
2471 #define CAN_F0R2_FB1 0x00000002U
2472 #define CAN_F0R2_FB2 0x00000004U
2473 #define CAN_F0R2_FB3 0x00000008U
2474 #define CAN_F0R2_FB4 0x00000010U
2475 #define CAN_F0R2_FB5 0x00000020U
2476 #define CAN_F0R2_FB6 0x00000040U
2477 #define CAN_F0R2_FB7 0x00000080U
2478 #define CAN_F0R2_FB8 0x00000100U
2479 #define CAN_F0R2_FB9 0x00000200U
2480 #define CAN_F0R2_FB10 0x00000400U
2481 #define CAN_F0R2_FB11 0x00000800U
2482 #define CAN_F0R2_FB12 0x00001000U
2483 #define CAN_F0R2_FB13 0x00002000U
2484 #define CAN_F0R2_FB14 0x00004000U
2485 #define CAN_F0R2_FB15 0x00008000U
2486 #define CAN_F0R2_FB16 0x00010000U
2487 #define CAN_F0R2_FB17 0x00020000U
2488 #define CAN_F0R2_FB18 0x00040000U
2489 #define CAN_F0R2_FB19 0x00080000U
2490 #define CAN_F0R2_FB20 0x00100000U
2491 #define CAN_F0R2_FB21 0x00200000U
2492 #define CAN_F0R2_FB22 0x00400000U
2493 #define CAN_F0R2_FB23 0x00800000U
2494 #define CAN_F0R2_FB24 0x01000000U
2495 #define CAN_F0R2_FB25 0x02000000U
2496 #define CAN_F0R2_FB26 0x04000000U
2497 #define CAN_F0R2_FB27 0x08000000U
2498 #define CAN_F0R2_FB28 0x10000000U
2499 #define CAN_F0R2_FB29 0x20000000U
2500 #define CAN_F0R2_FB30 0x40000000U
2501 #define CAN_F0R2_FB31 0x80000000U
2503 /******************* Bit definition for CAN_F1R2 register *******************/
2504 #define CAN_F1R2_FB0 0x00000001U
2505 #define CAN_F1R2_FB1 0x00000002U
2506 #define CAN_F1R2_FB2 0x00000004U
2507 #define CAN_F1R2_FB3 0x00000008U
2508 #define CAN_F1R2_FB4 0x00000010U
2509 #define CAN_F1R2_FB5 0x00000020U
2510 #define CAN_F1R2_FB6 0x00000040U
2511 #define CAN_F1R2_FB7 0x00000080U
2512 #define CAN_F1R2_FB8 0x00000100U
2513 #define CAN_F1R2_FB9 0x00000200U
2514 #define CAN_F1R2_FB10 0x00000400U
2515 #define CAN_F1R2_FB11 0x00000800U
2516 #define CAN_F1R2_FB12 0x00001000U
2517 #define CAN_F1R2_FB13 0x00002000U
2518 #define CAN_F1R2_FB14 0x00004000U
2519 #define CAN_F1R2_FB15 0x00008000U
2520 #define CAN_F1R2_FB16 0x00010000U
2521 #define CAN_F1R2_FB17 0x00020000U
2522 #define CAN_F1R2_FB18 0x00040000U
2523 #define CAN_F1R2_FB19 0x00080000U
2524 #define CAN_F1R2_FB20 0x00100000U
2525 #define CAN_F1R2_FB21 0x00200000U
2526 #define CAN_F1R2_FB22 0x00400000U
2527 #define CAN_F1R2_FB23 0x00800000U
2528 #define CAN_F1R2_FB24 0x01000000U
2529 #define CAN_F1R2_FB25 0x02000000U
2530 #define CAN_F1R2_FB26 0x04000000U
2531 #define CAN_F1R2_FB27 0x08000000U
2532 #define CAN_F1R2_FB28 0x10000000U
2533 #define CAN_F1R2_FB29 0x20000000U
2534 #define CAN_F1R2_FB30 0x40000000U
2535 #define CAN_F1R2_FB31 0x80000000U
2537 /******************* Bit definition for CAN_F2R2 register *******************/
2538 #define CAN_F2R2_FB0 0x00000001U
2539 #define CAN_F2R2_FB1 0x00000002U
2540 #define CAN_F2R2_FB2 0x00000004U
2541 #define CAN_F2R2_FB3 0x00000008U
2542 #define CAN_F2R2_FB4 0x00000010U
2543 #define CAN_F2R2_FB5 0x00000020U
2544 #define CAN_F2R2_FB6 0x00000040U
2545 #define CAN_F2R2_FB7 0x00000080U
2546 #define CAN_F2R2_FB8 0x00000100U
2547 #define CAN_F2R2_FB9 0x00000200U
2548 #define CAN_F2R2_FB10 0x00000400U
2549 #define CAN_F2R2_FB11 0x00000800U
2550 #define CAN_F2R2_FB12 0x00001000U
2551 #define CAN_F2R2_FB13 0x00002000U
2552 #define CAN_F2R2_FB14 0x00004000U
2553 #define CAN_F2R2_FB15 0x00008000U
2554 #define CAN_F2R2_FB16 0x00010000U
2555 #define CAN_F2R2_FB17 0x00020000U
2556 #define CAN_F2R2_FB18 0x00040000U
2557 #define CAN_F2R2_FB19 0x00080000U
2558 #define CAN_F2R2_FB20 0x00100000U
2559 #define CAN_F2R2_FB21 0x00200000U
2560 #define CAN_F2R2_FB22 0x00400000U
2561 #define CAN_F2R2_FB23 0x00800000U
2562 #define CAN_F2R2_FB24 0x01000000U
2563 #define CAN_F2R2_FB25 0x02000000U
2564 #define CAN_F2R2_FB26 0x04000000U
2565 #define CAN_F2R2_FB27 0x08000000U
2566 #define CAN_F2R2_FB28 0x10000000U
2567 #define CAN_F2R2_FB29 0x20000000U
2568 #define CAN_F2R2_FB30 0x40000000U
2569 #define CAN_F2R2_FB31 0x80000000U
2571 /******************* Bit definition for CAN_F3R2 register *******************/
2572 #define CAN_F3R2_FB0 0x00000001U
2573 #define CAN_F3R2_FB1 0x00000002U
2574 #define CAN_F3R2_FB2 0x00000004U
2575 #define CAN_F3R2_FB3 0x00000008U
2576 #define CAN_F3R2_FB4 0x00000010U
2577 #define CAN_F3R2_FB5 0x00000020U
2578 #define CAN_F3R2_FB6 0x00000040U
2579 #define CAN_F3R2_FB7 0x00000080U
2580 #define CAN_F3R2_FB8 0x00000100U
2581 #define CAN_F3R2_FB9 0x00000200U
2582 #define CAN_F3R2_FB10 0x00000400U
2583 #define CAN_F3R2_FB11 0x00000800U
2584 #define CAN_F3R2_FB12 0x00001000U
2585 #define CAN_F3R2_FB13 0x00002000U
2586 #define CAN_F3R2_FB14 0x00004000U
2587 #define CAN_F3R2_FB15 0x00008000U
2588 #define CAN_F3R2_FB16 0x00010000U
2589 #define CAN_F3R2_FB17 0x00020000U
2590 #define CAN_F3R2_FB18 0x00040000U
2591 #define CAN_F3R2_FB19 0x00080000U
2592 #define CAN_F3R2_FB20 0x00100000U
2593 #define CAN_F3R2_FB21 0x00200000U
2594 #define CAN_F3R2_FB22 0x00400000U
2595 #define CAN_F3R2_FB23 0x00800000U
2596 #define CAN_F3R2_FB24 0x01000000U
2597 #define CAN_F3R2_FB25 0x02000000U
2598 #define CAN_F3R2_FB26 0x04000000U
2599 #define CAN_F3R2_FB27 0x08000000U
2600 #define CAN_F3R2_FB28 0x10000000U
2601 #define CAN_F3R2_FB29 0x20000000U
2602 #define CAN_F3R2_FB30 0x40000000U
2603 #define CAN_F3R2_FB31 0x80000000U
2605 /******************* Bit definition for CAN_F4R2 register *******************/
2606 #define CAN_F4R2_FB0 0x00000001U
2607 #define CAN_F4R2_FB1 0x00000002U
2608 #define CAN_F4R2_FB2 0x00000004U
2609 #define CAN_F4R2_FB3 0x00000008U
2610 #define CAN_F4R2_FB4 0x00000010U
2611 #define CAN_F4R2_FB5 0x00000020U
2612 #define CAN_F4R2_FB6 0x00000040U
2613 #define CAN_F4R2_FB7 0x00000080U
2614 #define CAN_F4R2_FB8 0x00000100U
2615 #define CAN_F4R2_FB9 0x00000200U
2616 #define CAN_F4R2_FB10 0x00000400U
2617 #define CAN_F4R2_FB11 0x00000800U
2618 #define CAN_F4R2_FB12 0x00001000U
2619 #define CAN_F4R2_FB13 0x00002000U
2620 #define CAN_F4R2_FB14 0x00004000U
2621 #define CAN_F4R2_FB15 0x00008000U
2622 #define CAN_F4R2_FB16 0x00010000U
2623 #define CAN_F4R2_FB17 0x00020000U
2624 #define CAN_F4R2_FB18 0x00040000U
2625 #define CAN_F4R2_FB19 0x00080000U
2626 #define CAN_F4R2_FB20 0x00100000U
2627 #define CAN_F4R2_FB21 0x00200000U
2628 #define CAN_F4R2_FB22 0x00400000U
2629 #define CAN_F4R2_FB23 0x00800000U
2630 #define CAN_F4R2_FB24 0x01000000U
2631 #define CAN_F4R2_FB25 0x02000000U
2632 #define CAN_F4R2_FB26 0x04000000U
2633 #define CAN_F4R2_FB27 0x08000000U
2634 #define CAN_F4R2_FB28 0x10000000U
2635 #define CAN_F4R2_FB29 0x20000000U
2636 #define CAN_F4R2_FB30 0x40000000U
2637 #define CAN_F4R2_FB31 0x80000000U
2639 /******************* Bit definition for CAN_F5R2 register *******************/
2640 #define CAN_F5R2_FB0 0x00000001U
2641 #define CAN_F5R2_FB1 0x00000002U
2642 #define CAN_F5R2_FB2 0x00000004U
2643 #define CAN_F5R2_FB3 0x00000008U
2644 #define CAN_F5R2_FB4 0x00000010U
2645 #define CAN_F5R2_FB5 0x00000020U
2646 #define CAN_F5R2_FB6 0x00000040U
2647 #define CAN_F5R2_FB7 0x00000080U
2648 #define CAN_F5R2_FB8 0x00000100U
2649 #define CAN_F5R2_FB9 0x00000200U
2650 #define CAN_F5R2_FB10 0x00000400U
2651 #define CAN_F5R2_FB11 0x00000800U
2652 #define CAN_F5R2_FB12 0x00001000U
2653 #define CAN_F5R2_FB13 0x00002000U
2654 #define CAN_F5R2_FB14 0x00004000U
2655 #define CAN_F5R2_FB15 0x00008000U
2656 #define CAN_F5R2_FB16 0x00010000U
2657 #define CAN_F5R2_FB17 0x00020000U
2658 #define CAN_F5R2_FB18 0x00040000U
2659 #define CAN_F5R2_FB19 0x00080000U
2660 #define CAN_F5R2_FB20 0x00100000U
2661 #define CAN_F5R2_FB21 0x00200000U
2662 #define CAN_F5R2_FB22 0x00400000U
2663 #define CAN_F5R2_FB23 0x00800000U
2664 #define CAN_F5R2_FB24 0x01000000U
2665 #define CAN_F5R2_FB25 0x02000000U
2666 #define CAN_F5R2_FB26 0x04000000U
2667 #define CAN_F5R2_FB27 0x08000000U
2668 #define CAN_F5R2_FB28 0x10000000U
2669 #define CAN_F5R2_FB29 0x20000000U
2670 #define CAN_F5R2_FB30 0x40000000U
2671 #define CAN_F5R2_FB31 0x80000000U
2673 /******************* Bit definition for CAN_F6R2 register *******************/
2674 #define CAN_F6R2_FB0 0x00000001U
2675 #define CAN_F6R2_FB1 0x00000002U
2676 #define CAN_F6R2_FB2 0x00000004U
2677 #define CAN_F6R2_FB3 0x00000008U
2678 #define CAN_F6R2_FB4 0x00000010U
2679 #define CAN_F6R2_FB5 0x00000020U
2680 #define CAN_F6R2_FB6 0x00000040U
2681 #define CAN_F6R2_FB7 0x00000080U
2682 #define CAN_F6R2_FB8 0x00000100U
2683 #define CAN_F6R2_FB9 0x00000200U
2684 #define CAN_F6R2_FB10 0x00000400U
2685 #define CAN_F6R2_FB11 0x00000800U
2686 #define CAN_F6R2_FB12 0x00001000U
2687 #define CAN_F6R2_FB13 0x00002000U
2688 #define CAN_F6R2_FB14 0x00004000U
2689 #define CAN_F6R2_FB15 0x00008000U
2690 #define CAN_F6R2_FB16 0x00010000U
2691 #define CAN_F6R2_FB17 0x00020000U
2692 #define CAN_F6R2_FB18 0x00040000U
2693 #define CAN_F6R2_FB19 0x00080000U
2694 #define CAN_F6R2_FB20 0x00100000U
2695 #define CAN_F6R2_FB21 0x00200000U
2696 #define CAN_F6R2_FB22 0x00400000U
2697 #define CAN_F6R2_FB23 0x00800000U
2698 #define CAN_F6R2_FB24 0x01000000U
2699 #define CAN_F6R2_FB25 0x02000000U
2700 #define CAN_F6R2_FB26 0x04000000U
2701 #define CAN_F6R2_FB27 0x08000000U
2702 #define CAN_F6R2_FB28 0x10000000U
2703 #define CAN_F6R2_FB29 0x20000000U
2704 #define CAN_F6R2_FB30 0x40000000U
2705 #define CAN_F6R2_FB31 0x80000000U
2707 /******************* Bit definition for CAN_F7R2 register *******************/
2708 #define CAN_F7R2_FB0 0x00000001U
2709 #define CAN_F7R2_FB1 0x00000002U
2710 #define CAN_F7R2_FB2 0x00000004U
2711 #define CAN_F7R2_FB3 0x00000008U
2712 #define CAN_F7R2_FB4 0x00000010U
2713 #define CAN_F7R2_FB5 0x00000020U
2714 #define CAN_F7R2_FB6 0x00000040U
2715 #define CAN_F7R2_FB7 0x00000080U
2716 #define CAN_F7R2_FB8 0x00000100U
2717 #define CAN_F7R2_FB9 0x00000200U
2718 #define CAN_F7R2_FB10 0x00000400U
2719 #define CAN_F7R2_FB11 0x00000800U
2720 #define CAN_F7R2_FB12 0x00001000U
2721 #define CAN_F7R2_FB13 0x00002000U
2722 #define CAN_F7R2_FB14 0x00004000U
2723 #define CAN_F7R2_FB15 0x00008000U
2724 #define CAN_F7R2_FB16 0x00010000U
2725 #define CAN_F7R2_FB17 0x00020000U
2726 #define CAN_F7R2_FB18 0x00040000U
2727 #define CAN_F7R2_FB19 0x00080000U
2728 #define CAN_F7R2_FB20 0x00100000U
2729 #define CAN_F7R2_FB21 0x00200000U
2730 #define CAN_F7R2_FB22 0x00400000U
2731 #define CAN_F7R2_FB23 0x00800000U
2732 #define CAN_F7R2_FB24 0x01000000U
2733 #define CAN_F7R2_FB25 0x02000000U
2734 #define CAN_F7R2_FB26 0x04000000U
2735 #define CAN_F7R2_FB27 0x08000000U
2736 #define CAN_F7R2_FB28 0x10000000U
2737 #define CAN_F7R2_FB29 0x20000000U
2738 #define CAN_F7R2_FB30 0x40000000U
2739 #define CAN_F7R2_FB31 0x80000000U
2741 /******************* Bit definition for CAN_F8R2 register *******************/
2742 #define CAN_F8R2_FB0 0x00000001U
2743 #define CAN_F8R2_FB1 0x00000002U
2744 #define CAN_F8R2_FB2 0x00000004U
2745 #define CAN_F8R2_FB3 0x00000008U
2746 #define CAN_F8R2_FB4 0x00000010U
2747 #define CAN_F8R2_FB5 0x00000020U
2748 #define CAN_F8R2_FB6 0x00000040U
2749 #define CAN_F8R2_FB7 0x00000080U
2750 #define CAN_F8R2_FB8 0x00000100U
2751 #define CAN_F8R2_FB9 0x00000200U
2752 #define CAN_F8R2_FB10 0x00000400U
2753 #define CAN_F8R2_FB11 0x00000800U
2754 #define CAN_F8R2_FB12 0x00001000U
2755 #define CAN_F8R2_FB13 0x00002000U
2756 #define CAN_F8R2_FB14 0x00004000U
2757 #define CAN_F8R2_FB15 0x00008000U
2758 #define CAN_F8R2_FB16 0x00010000U
2759 #define CAN_F8R2_FB17 0x00020000U
2760 #define CAN_F8R2_FB18 0x00040000U
2761 #define CAN_F8R2_FB19 0x00080000U
2762 #define CAN_F8R2_FB20 0x00100000U
2763 #define CAN_F8R2_FB21 0x00200000U
2764 #define CAN_F8R2_FB22 0x00400000U
2765 #define CAN_F8R2_FB23 0x00800000U
2766 #define CAN_F8R2_FB24 0x01000000U
2767 #define CAN_F8R2_FB25 0x02000000U
2768 #define CAN_F8R2_FB26 0x04000000U
2769 #define CAN_F8R2_FB27 0x08000000U
2770 #define CAN_F8R2_FB28 0x10000000U
2771 #define CAN_F8R2_FB29 0x20000000U
2772 #define CAN_F8R2_FB30 0x40000000U
2773 #define CAN_F8R2_FB31 0x80000000U
2775 /******************* Bit definition for CAN_F9R2 register *******************/
2776 #define CAN_F9R2_FB0 0x00000001U
2777 #define CAN_F9R2_FB1 0x00000002U
2778 #define CAN_F9R2_FB2 0x00000004U
2779 #define CAN_F9R2_FB3 0x00000008U
2780 #define CAN_F9R2_FB4 0x00000010U
2781 #define CAN_F9R2_FB5 0x00000020U
2782 #define CAN_F9R2_FB6 0x00000040U
2783 #define CAN_F9R2_FB7 0x00000080U
2784 #define CAN_F9R2_FB8 0x00000100U
2785 #define CAN_F9R2_FB9 0x00000200U
2786 #define CAN_F9R2_FB10 0x00000400U
2787 #define CAN_F9R2_FB11 0x00000800U
2788 #define CAN_F9R2_FB12 0x00001000U
2789 #define CAN_F9R2_FB13 0x00002000U
2790 #define CAN_F9R2_FB14 0x00004000U
2791 #define CAN_F9R2_FB15 0x00008000U
2792 #define CAN_F9R2_FB16 0x00010000U
2793 #define CAN_F9R2_FB17 0x00020000U
2794 #define CAN_F9R2_FB18 0x00040000U
2795 #define CAN_F9R2_FB19 0x00080000U
2796 #define CAN_F9R2_FB20 0x00100000U
2797 #define CAN_F9R2_FB21 0x00200000U
2798 #define CAN_F9R2_FB22 0x00400000U
2799 #define CAN_F9R2_FB23 0x00800000U
2800 #define CAN_F9R2_FB24 0x01000000U
2801 #define CAN_F9R2_FB25 0x02000000U
2802 #define CAN_F9R2_FB26 0x04000000U
2803 #define CAN_F9R2_FB27 0x08000000U
2804 #define CAN_F9R2_FB28 0x10000000U
2805 #define CAN_F9R2_FB29 0x20000000U
2806 #define CAN_F9R2_FB30 0x40000000U
2807 #define CAN_F9R2_FB31 0x80000000U
2809 /******************* Bit definition for CAN_F10R2 register ******************/
2810 #define CAN_F10R2_FB0 0x00000001U
2811 #define CAN_F10R2_FB1 0x00000002U
2812 #define CAN_F10R2_FB2 0x00000004U
2813 #define CAN_F10R2_FB3 0x00000008U
2814 #define CAN_F10R2_FB4 0x00000010U
2815 #define CAN_F10R2_FB5 0x00000020U
2816 #define CAN_F10R2_FB6 0x00000040U
2817 #define CAN_F10R2_FB7 0x00000080U
2818 #define CAN_F10R2_FB8 0x00000100U
2819 #define CAN_F10R2_FB9 0x00000200U
2820 #define CAN_F10R2_FB10 0x00000400U
2821 #define CAN_F10R2_FB11 0x00000800U
2822 #define CAN_F10R2_FB12 0x00001000U
2823 #define CAN_F10R2_FB13 0x00002000U
2824 #define CAN_F10R2_FB14 0x00004000U
2825 #define CAN_F10R2_FB15 0x00008000U
2826 #define CAN_F10R2_FB16 0x00010000U
2827 #define CAN_F10R2_FB17 0x00020000U
2828 #define CAN_F10R2_FB18 0x00040000U
2829 #define CAN_F10R2_FB19 0x00080000U
2830 #define CAN_F10R2_FB20 0x00100000U
2831 #define CAN_F10R2_FB21 0x00200000U
2832 #define CAN_F10R2_FB22 0x00400000U
2833 #define CAN_F10R2_FB23 0x00800000U
2834 #define CAN_F10R2_FB24 0x01000000U
2835 #define CAN_F10R2_FB25 0x02000000U
2836 #define CAN_F10R2_FB26 0x04000000U
2837 #define CAN_F10R2_FB27 0x08000000U
2838 #define CAN_F10R2_FB28 0x10000000U
2839 #define CAN_F10R2_FB29 0x20000000U
2840 #define CAN_F10R2_FB30 0x40000000U
2841 #define CAN_F10R2_FB31 0x80000000U
2843 /******************* Bit definition for CAN_F11R2 register ******************/
2844 #define CAN_F11R2_FB0 0x00000001U
2845 #define CAN_F11R2_FB1 0x00000002U
2846 #define CAN_F11R2_FB2 0x00000004U
2847 #define CAN_F11R2_FB3 0x00000008U
2848 #define CAN_F11R2_FB4 0x00000010U
2849 #define CAN_F11R2_FB5 0x00000020U
2850 #define CAN_F11R2_FB6 0x00000040U
2851 #define CAN_F11R2_FB7 0x00000080U
2852 #define CAN_F11R2_FB8 0x00000100U
2853 #define CAN_F11R2_FB9 0x00000200U
2854 #define CAN_F11R2_FB10 0x00000400U
2855 #define CAN_F11R2_FB11 0x00000800U
2856 #define CAN_F11R2_FB12 0x00001000U
2857 #define CAN_F11R2_FB13 0x00002000U
2858 #define CAN_F11R2_FB14 0x00004000U
2859 #define CAN_F11R2_FB15 0x00008000U
2860 #define CAN_F11R2_FB16 0x00010000U
2861 #define CAN_F11R2_FB17 0x00020000U
2862 #define CAN_F11R2_FB18 0x00040000U
2863 #define CAN_F11R2_FB19 0x00080000U
2864 #define CAN_F11R2_FB20 0x00100000U
2865 #define CAN_F11R2_FB21 0x00200000U
2866 #define CAN_F11R2_FB22 0x00400000U
2867 #define CAN_F11R2_FB23 0x00800000U
2868 #define CAN_F11R2_FB24 0x01000000U
2869 #define CAN_F11R2_FB25 0x02000000U
2870 #define CAN_F11R2_FB26 0x04000000U
2871 #define CAN_F11R2_FB27 0x08000000U
2872 #define CAN_F11R2_FB28 0x10000000U
2873 #define CAN_F11R2_FB29 0x20000000U
2874 #define CAN_F11R2_FB30 0x40000000U
2875 #define CAN_F11R2_FB31 0x80000000U
2877 /******************* Bit definition for CAN_F12R2 register ******************/
2878 #define CAN_F12R2_FB0 0x00000001U
2879 #define CAN_F12R2_FB1 0x00000002U
2880 #define CAN_F12R2_FB2 0x00000004U
2881 #define CAN_F12R2_FB3 0x00000008U
2882 #define CAN_F12R2_FB4 0x00000010U
2883 #define CAN_F12R2_FB5 0x00000020U
2884 #define CAN_F12R2_FB6 0x00000040U
2885 #define CAN_F12R2_FB7 0x00000080U
2886 #define CAN_F12R2_FB8 0x00000100U
2887 #define CAN_F12R2_FB9 0x00000200U
2888 #define CAN_F12R2_FB10 0x00000400U
2889 #define CAN_F12R2_FB11 0x00000800U
2890 #define CAN_F12R2_FB12 0x00001000U
2891 #define CAN_F12R2_FB13 0x00002000U
2892 #define CAN_F12R2_FB14 0x00004000U
2893 #define CAN_F12R2_FB15 0x00008000U
2894 #define CAN_F12R2_FB16 0x00010000U
2895 #define CAN_F12R2_FB17 0x00020000U
2896 #define CAN_F12R2_FB18 0x00040000U
2897 #define CAN_F12R2_FB19 0x00080000U
2898 #define CAN_F12R2_FB20 0x00100000U
2899 #define CAN_F12R2_FB21 0x00200000U
2900 #define CAN_F12R2_FB22 0x00400000U
2901 #define CAN_F12R2_FB23 0x00800000U
2902 #define CAN_F12R2_FB24 0x01000000U
2903 #define CAN_F12R2_FB25 0x02000000U
2904 #define CAN_F12R2_FB26 0x04000000U
2905 #define CAN_F12R2_FB27 0x08000000U
2906 #define CAN_F12R2_FB28 0x10000000U
2907 #define CAN_F12R2_FB29 0x20000000U
2908 #define CAN_F12R2_FB30 0x40000000U
2909 #define CAN_F12R2_FB31 0x80000000U
2911 /******************* Bit definition for CAN_F13R2 register ******************/
2912 #define CAN_F13R2_FB0 0x00000001U
2913 #define CAN_F13R2_FB1 0x00000002U
2914 #define CAN_F13R2_FB2 0x00000004U
2915 #define CAN_F13R2_FB3 0x00000008U
2916 #define CAN_F13R2_FB4 0x00000010U
2917 #define CAN_F13R2_FB5 0x00000020U
2918 #define CAN_F13R2_FB6 0x00000040U
2919 #define CAN_F13R2_FB7 0x00000080U
2920 #define CAN_F13R2_FB8 0x00000100U
2921 #define CAN_F13R2_FB9 0x00000200U
2922 #define CAN_F13R2_FB10 0x00000400U
2923 #define CAN_F13R2_FB11 0x00000800U
2924 #define CAN_F13R2_FB12 0x00001000U
2925 #define CAN_F13R2_FB13 0x00002000U
2926 #define CAN_F13R2_FB14 0x00004000U
2927 #define CAN_F13R2_FB15 0x00008000U
2928 #define CAN_F13R2_FB16 0x00010000U
2929 #define CAN_F13R2_FB17 0x00020000U
2930 #define CAN_F13R2_FB18 0x00040000U
2931 #define CAN_F13R2_FB19 0x00080000U
2932 #define CAN_F13R2_FB20 0x00100000U
2933 #define CAN_F13R2_FB21 0x00200000U
2934 #define CAN_F13R2_FB22 0x00400000U
2935 #define CAN_F13R2_FB23 0x00800000U
2936 #define CAN_F13R2_FB24 0x01000000U
2937 #define CAN_F13R2_FB25 0x02000000U
2938 #define CAN_F13R2_FB26 0x04000000U
2939 #define CAN_F13R2_FB27 0x08000000U
2940 #define CAN_F13R2_FB28 0x10000000U
2941 #define CAN_F13R2_FB29 0x20000000U
2942 #define CAN_F13R2_FB30 0x40000000U
2943 #define CAN_F13R2_FB31 0x80000000U
2945 /******************************************************************************/
2946 /* */
2947 /* CRC calculation unit */
2948 /* */
2949 /******************************************************************************/
2950 /******************* Bit definition for CRC_DR register *********************/
2951 #define CRC_DR_DR 0xFFFFFFFFU
2954 /******************* Bit definition for CRC_IDR register ********************/
2955 #define CRC_IDR_IDR 0xFFU
2958 /******************** Bit definition for CRC_CR register ********************/
2959 #define CRC_CR_RESET 0x01U
2961 /******************************************************************************/
2962 /* */
2963 /* Crypto Processor */
2964 /* */
2965 /******************************************************************************/
2966 /******************* Bits definition for CRYP_CR register ********************/
2967 #define CRYP_CR_ALGODIR 0x00000004U
2968 
2969 #define CRYP_CR_ALGOMODE 0x00080038U
2970 #define CRYP_CR_ALGOMODE_0 0x00000008U
2971 #define CRYP_CR_ALGOMODE_1 0x00000010U
2972 #define CRYP_CR_ALGOMODE_2 0x00000020U
2973 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
2974 #define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
2975 #define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
2976 #define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
2977 #define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
2978 #define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
2979 #define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
2980 #define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
2981 
2982 #define CRYP_CR_DATATYPE 0x000000C0U
2983 #define CRYP_CR_DATATYPE_0 0x00000040U
2984 #define CRYP_CR_DATATYPE_1 0x00000080U
2985 #define CRYP_CR_KEYSIZE 0x00000300U
2986 #define CRYP_CR_KEYSIZE_0 0x00000100U
2987 #define CRYP_CR_KEYSIZE_1 0x00000200U
2988 #define CRYP_CR_FFLUSH 0x00004000U
2989 #define CRYP_CR_CRYPEN 0x00008000U
2990 
2991 #define CRYP_CR_GCM_CCMPH 0x00030000U
2992 #define CRYP_CR_GCM_CCMPH_0 0x00010000U
2993 #define CRYP_CR_GCM_CCMPH_1 0x00020000U
2994 #define CRYP_CR_ALGOMODE_3 0x00080000U
2995 
2996 /****************** Bits definition for CRYP_SR register *********************/
2997 #define CRYP_SR_IFEM 0x00000001U
2998 #define CRYP_SR_IFNF 0x00000002U
2999 #define CRYP_SR_OFNE 0x00000004U
3000 #define CRYP_SR_OFFU 0x00000008U
3001 #define CRYP_SR_BUSY 0x00000010U
3002 /****************** Bits definition for CRYP_DMACR register ******************/
3003 #define CRYP_DMACR_DIEN 0x00000001U
3004 #define CRYP_DMACR_DOEN 0x00000002U
3005 /***************** Bits definition for CRYP_IMSCR register ******************/
3006 #define CRYP_IMSCR_INIM 0x00000001U
3007 #define CRYP_IMSCR_OUTIM 0x00000002U
3008 /****************** Bits definition for CRYP_RISR register *******************/
3009 #define CRYP_RISR_OUTRIS 0x00000001U
3010 #define CRYP_RISR_INRIS 0x00000002U
3011 /****************** Bits definition for CRYP_MISR register *******************/
3012 #define CRYP_MISR_INMIS 0x00000001U
3013 #define CRYP_MISR_OUTMIS 0x00000002U
3014 
3015 /******************************************************************************/
3016 /* */
3017 /* Digital to Analog Converter */
3018 /* */
3019 /******************************************************************************/
3020 /******************** Bit definition for DAC_CR register ********************/
3021 #define DAC_CR_EN1 0x00000001U
3022 #define DAC_CR_BOFF1 0x00000002U
3023 #define DAC_CR_TEN1 0x00000004U
3025 #define DAC_CR_TSEL1 0x00000038U
3026 #define DAC_CR_TSEL1_0 0x00000008U
3027 #define DAC_CR_TSEL1_1 0x00000010U
3028 #define DAC_CR_TSEL1_2 0x00000020U
3030 #define DAC_CR_WAVE1 0x000000C0U
3031 #define DAC_CR_WAVE1_0 0x00000040U
3032 #define DAC_CR_WAVE1_1 0x00000080U
3034 #define DAC_CR_MAMP1 0x00000F00U
3035 #define DAC_CR_MAMP1_0 0x00000100U
3036 #define DAC_CR_MAMP1_1 0x00000200U
3037 #define DAC_CR_MAMP1_2 0x00000400U
3038 #define DAC_CR_MAMP1_3 0x00000800U
3040 #define DAC_CR_DMAEN1 0x00001000U
3041 #define DAC_CR_DMAUDRIE1 0x00002000U
3042 #define DAC_CR_EN2 0x00010000U
3043 #define DAC_CR_BOFF2 0x00020000U
3044 #define DAC_CR_TEN2 0x00040000U
3046 #define DAC_CR_TSEL2 0x00380000U
3047 #define DAC_CR_TSEL2_0 0x00080000U
3048 #define DAC_CR_TSEL2_1 0x00100000U
3049 #define DAC_CR_TSEL2_2 0x00200000U
3051 #define DAC_CR_WAVE2 0x00C00000U
3052 #define DAC_CR_WAVE2_0 0x00400000U
3053 #define DAC_CR_WAVE2_1 0x00800000U
3055 #define DAC_CR_MAMP2 0x0F000000U
3056 #define DAC_CR_MAMP2_0 0x01000000U
3057 #define DAC_CR_MAMP2_1 0x02000000U
3058 #define DAC_CR_MAMP2_2 0x04000000U
3059 #define DAC_CR_MAMP2_3 0x08000000U
3061 #define DAC_CR_DMAEN2 0x10000000U
3062 #define DAC_CR_DMAUDRIE2 0x20000000U
3064 /***************** Bit definition for DAC_SWTRIGR register ******************/
3065 #define DAC_SWTRIGR_SWTRIG1 0x01U
3066 #define DAC_SWTRIGR_SWTRIG2 0x02U
3068 /***************** Bit definition for DAC_DHR12R1 register ******************/
3069 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3071 /***************** Bit definition for DAC_DHR12L1 register ******************/
3072 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3074 /****************** Bit definition for DAC_DHR8R1 register ******************/
3075 #define DAC_DHR8R1_DACC1DHR 0xFFU
3077 /***************** Bit definition for DAC_DHR12R2 register ******************/
3078 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3080 /***************** Bit definition for DAC_DHR12L2 register ******************/
3081 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3083 /****************** Bit definition for DAC_DHR8R2 register ******************/
3084 #define DAC_DHR8R2_DACC2DHR 0xFFU
3086 /***************** Bit definition for DAC_DHR12RD register ******************/
3087 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3088 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3090 /***************** Bit definition for DAC_DHR12LD register ******************/
3091 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3092 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3094 /****************** Bit definition for DAC_DHR8RD register ******************/
3095 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3096 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3098 /******************* Bit definition for DAC_DOR1 register *******************/
3099 #define DAC_DOR1_DACC1DOR 0x0FFFU
3101 /******************* Bit definition for DAC_DOR2 register *******************/
3102 #define DAC_DOR2_DACC2DOR 0x0FFFU
3104 /******************** Bit definition for DAC_SR register ********************/
3105 #define DAC_SR_DMAUDR1 0x00002000U
3106 #define DAC_SR_DMAUDR2 0x20000000U
3108 /******************************************************************************/
3109 /* */
3110 /* Debug MCU */
3111 /* */
3112 /******************************************************************************/
3113 
3114 /******************************************************************************/
3115 /* */
3116 /* DCMI */
3117 /* */
3118 /******************************************************************************/
3119 /******************** Bits definition for DCMI_CR register ******************/
3120 #define DCMI_CR_CAPTURE 0x00000001U
3121 #define DCMI_CR_CM 0x00000002U
3122 #define DCMI_CR_CROP 0x00000004U
3123 #define DCMI_CR_JPEG 0x00000008U
3124 #define DCMI_CR_ESS 0x00000010U
3125 #define DCMI_CR_PCKPOL 0x00000020U
3126 #define DCMI_CR_HSPOL 0x00000040U
3127 #define DCMI_CR_VSPOL 0x00000080U
3128 #define DCMI_CR_FCRC_0 0x00000100U
3129 #define DCMI_CR_FCRC_1 0x00000200U
3130 #define DCMI_CR_EDM_0 0x00000400U
3131 #define DCMI_CR_EDM_1 0x00000800U
3132 #define DCMI_CR_CRE 0x00001000U
3133 #define DCMI_CR_ENABLE 0x00004000U
3134 
3135 /******************** Bits definition for DCMI_SR register ******************/
3136 #define DCMI_SR_HSYNC 0x00000001U
3137 #define DCMI_SR_VSYNC 0x00000002U
3138 #define DCMI_SR_FNE 0x00000004U
3139 
3140 /******************** Bits definition for DCMI_RIS register *****************/
3141 #define DCMI_RIS_FRAME_RIS 0x00000001U
3142 #define DCMI_RIS_OVR_RIS 0x00000002U
3143 #define DCMI_RIS_ERR_RIS 0x00000004U
3144 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3145 #define DCMI_RIS_LINE_RIS 0x00000010U
3146 /* Legacy defines */
3147 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3148 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
3149 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3150 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3151 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3152 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3153 
3154 /******************** Bits definition for DCMI_IER register *****************/
3155 #define DCMI_IER_FRAME_IE 0x00000001U
3156 #define DCMI_IER_OVR_IE 0x00000002U
3157 #define DCMI_IER_ERR_IE 0x00000004U
3158 #define DCMI_IER_VSYNC_IE 0x00000008U
3159 #define DCMI_IER_LINE_IE 0x00000010U
3160 /* Legacy defines */
3161 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3162 
3163 /******************** Bits definition for DCMI_MIS register *****************/
3164 #define DCMI_MIS_FRAME_MIS 0x00000001U
3165 #define DCMI_MIS_OVR_MIS 0x00000002U
3166 #define DCMI_MIS_ERR_MIS 0x00000004U
3167 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3168 #define DCMI_MIS_LINE_MIS 0x00000010U
3169 
3170 /* Legacy defines */
3171 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3172 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3173 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3174 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3175 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3176 
3177 /******************** Bits definition for DCMI_ICR register *****************/
3178 #define DCMI_ICR_FRAME_ISC 0x00000001U
3179 #define DCMI_ICR_OVR_ISC 0x00000002U
3180 #define DCMI_ICR_ERR_ISC 0x00000004U
3181 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3182 #define DCMI_ICR_LINE_ISC 0x00000010U
3183 
3184 /* Legacy defines */
3185 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3186 
3187 /******************** Bits definition for DCMI_ESCR register ******************/
3188 #define DCMI_ESCR_FSC 0x000000FFU
3189 #define DCMI_ESCR_LSC 0x0000FF00U
3190 #define DCMI_ESCR_LEC 0x00FF0000U
3191 #define DCMI_ESCR_FEC 0xFF000000U
3192 
3193 /******************** Bits definition for DCMI_ESUR register ******************/
3194 #define DCMI_ESUR_FSU 0x000000FFU
3195 #define DCMI_ESUR_LSU 0x0000FF00U
3196 #define DCMI_ESUR_LEU 0x00FF0000U
3197 #define DCMI_ESUR_FEU 0xFF000000U
3198 
3199 /******************** Bits definition for DCMI_CWSTRT register ******************/
3200 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3201 #define DCMI_CWSTRT_VST 0x1FFF0000U
3202 
3203 /******************** Bits definition for DCMI_CWSIZE register ******************/
3204 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3205 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3206 
3207 /******************** Bits definition for DCMI_DR register ******************/
3208 #define DCMI_DR_BYTE0 0x000000FFU
3209 #define DCMI_DR_BYTE1 0x0000FF00U
3210 #define DCMI_DR_BYTE2 0x00FF0000U
3211 #define DCMI_DR_BYTE3 0xFF000000U
3212 
3213 /******************************************************************************/
3214 /* */
3215 /* DMA Controller */
3216 /* */
3217 /******************************************************************************/
3218 /******************** Bits definition for DMA_SxCR register *****************/
3219 #define DMA_SxCR_CHSEL 0x0E000000U
3220 #define DMA_SxCR_CHSEL_0 0x02000000U
3221 #define DMA_SxCR_CHSEL_1 0x04000000U
3222 #define DMA_SxCR_CHSEL_2 0x08000000U
3223 #define DMA_SxCR_MBURST 0x01800000U
3224 #define DMA_SxCR_MBURST_0 0x00800000U
3225 #define DMA_SxCR_MBURST_1 0x01000000U
3226 #define DMA_SxCR_PBURST 0x00600000U
3227 #define DMA_SxCR_PBURST_0 0x00200000U
3228 #define DMA_SxCR_PBURST_1 0x00400000U
3229 #define DMA_SxCR_CT 0x00080000U
3230 #define DMA_SxCR_DBM 0x00040000U
3231 #define DMA_SxCR_PL 0x00030000U
3232 #define DMA_SxCR_PL_0 0x00010000U
3233 #define DMA_SxCR_PL_1 0x00020000U
3234 #define DMA_SxCR_PINCOS 0x00008000U
3235 #define DMA_SxCR_MSIZE 0x00006000U
3236 #define DMA_SxCR_MSIZE_0 0x00002000U
3237 #define DMA_SxCR_MSIZE_1 0x00004000U
3238 #define DMA_SxCR_PSIZE 0x00001800U
3239 #define DMA_SxCR_PSIZE_0 0x00000800U
3240 #define DMA_SxCR_PSIZE_1 0x00001000U
3241 #define DMA_SxCR_MINC 0x00000400U
3242 #define DMA_SxCR_PINC 0x00000200U
3243 #define DMA_SxCR_CIRC 0x00000100U
3244 #define DMA_SxCR_DIR 0x000000C0U
3245 #define DMA_SxCR_DIR_0 0x00000040U
3246 #define DMA_SxCR_DIR_1 0x00000080U
3247 #define DMA_SxCR_PFCTRL 0x00000020U
3248 #define DMA_SxCR_TCIE 0x00000010U
3249 #define DMA_SxCR_HTIE 0x00000008U
3250 #define DMA_SxCR_TEIE 0x00000004U
3251 #define DMA_SxCR_DMEIE 0x00000002U
3252 #define DMA_SxCR_EN 0x00000001U
3253 
3254 /* Legacy defines */
3255 #define DMA_SxCR_ACK 0x00100000U
3256 
3257 /******************** Bits definition for DMA_SxCNDTR register **************/
3258 #define DMA_SxNDT 0x0000FFFFU
3259 #define DMA_SxNDT_0 0x00000001U
3260 #define DMA_SxNDT_1 0x00000002U
3261 #define DMA_SxNDT_2 0x00000004U
3262 #define DMA_SxNDT_3 0x00000008U
3263 #define DMA_SxNDT_4 0x00000010U
3264 #define DMA_SxNDT_5 0x00000020U
3265 #define DMA_SxNDT_6 0x00000040U
3266 #define DMA_SxNDT_7 0x00000080U
3267 #define DMA_SxNDT_8 0x00000100U
3268 #define DMA_SxNDT_9 0x00000200U
3269 #define DMA_SxNDT_10 0x00000400U
3270 #define DMA_SxNDT_11 0x00000800U
3271 #define DMA_SxNDT_12 0x00001000U
3272 #define DMA_SxNDT_13 0x00002000U
3273 #define DMA_SxNDT_14 0x00004000U
3274 #define DMA_SxNDT_15 0x00008000U
3275 
3276 /******************** Bits definition for DMA_SxFCR register ****************/
3277 #define DMA_SxFCR_FEIE 0x00000080U
3278 #define DMA_SxFCR_FS 0x00000038U
3279 #define DMA_SxFCR_FS_0 0x00000008U
3280 #define DMA_SxFCR_FS_1 0x00000010U
3281 #define DMA_SxFCR_FS_2 0x00000020U
3282 #define DMA_SxFCR_DMDIS 0x00000004U
3283 #define DMA_SxFCR_FTH 0x00000003U
3284 #define DMA_SxFCR_FTH_0 0x00000001U
3285 #define DMA_SxFCR_FTH_1 0x00000002U
3286 
3287 /******************** Bits definition for DMA_LISR register *****************/
3288 #define DMA_LISR_TCIF3 0x08000000U
3289 #define DMA_LISR_HTIF3 0x04000000U
3290 #define DMA_LISR_TEIF3 0x02000000U
3291 #define DMA_LISR_DMEIF3 0x01000000U
3292 #define DMA_LISR_FEIF3 0x00400000U
3293 #define DMA_LISR_TCIF2 0x00200000U
3294 #define DMA_LISR_HTIF2 0x00100000U
3295 #define DMA_LISR_TEIF2 0x00080000U
3296 #define DMA_LISR_DMEIF2 0x00040000U
3297 #define DMA_LISR_FEIF2 0x00010000U
3298 #define DMA_LISR_TCIF1 0x00000800U
3299 #define DMA_LISR_HTIF1 0x00000400U
3300 #define DMA_LISR_TEIF1 0x00000200U
3301 #define DMA_LISR_DMEIF1 0x00000100U
3302 #define DMA_LISR_FEIF1 0x00000040U
3303 #define DMA_LISR_TCIF0 0x00000020U
3304 #define DMA_LISR_HTIF0 0x00000010U
3305 #define DMA_LISR_TEIF0 0x00000008U
3306 #define DMA_LISR_DMEIF0 0x00000004U
3307 #define DMA_LISR_FEIF0 0x00000001U
3308 
3309 /******************** Bits definition for DMA_HISR register *****************/
3310 #define DMA_HISR_TCIF7 0x08000000U
3311 #define DMA_HISR_HTIF7 0x04000000U
3312 #define DMA_HISR_TEIF7 0x02000000U
3313 #define DMA_HISR_DMEIF7 0x01000000U
3314 #define DMA_HISR_FEIF7 0x00400000U
3315 #define DMA_HISR_TCIF6 0x00200000U
3316 #define DMA_HISR_HTIF6 0x00100000U
3317 #define DMA_HISR_TEIF6 0x00080000U
3318 #define DMA_HISR_DMEIF6 0x00040000U
3319 #define DMA_HISR_FEIF6 0x00010000U
3320 #define DMA_HISR_TCIF5 0x00000800U
3321 #define DMA_HISR_HTIF5 0x00000400U
3322 #define DMA_HISR_TEIF5 0x00000200U
3323 #define DMA_HISR_DMEIF5 0x00000100U
3324 #define DMA_HISR_FEIF5 0x00000040U
3325 #define DMA_HISR_TCIF4 0x00000020U
3326 #define DMA_HISR_HTIF4 0x00000010U
3327 #define DMA_HISR_TEIF4 0x00000008U
3328 #define DMA_HISR_DMEIF4 0x00000004U
3329 #define DMA_HISR_FEIF4 0x00000001U
3330 
3331 /******************** Bits definition for DMA_LIFCR register ****************/
3332 #define DMA_LIFCR_CTCIF3 0x08000000U
3333 #define DMA_LIFCR_CHTIF3 0x04000000U
3334 #define DMA_LIFCR_CTEIF3 0x02000000U
3335 #define DMA_LIFCR_CDMEIF3 0x01000000U
3336 #define DMA_LIFCR_CFEIF3 0x00400000U
3337 #define DMA_LIFCR_CTCIF2 0x00200000U
3338 #define DMA_LIFCR_CHTIF2 0x00100000U
3339 #define DMA_LIFCR_CTEIF2 0x00080000U
3340 #define DMA_LIFCR_CDMEIF2 0x00040000U
3341 #define DMA_LIFCR_CFEIF2 0x00010000U
3342 #define DMA_LIFCR_CTCIF1 0x00000800U
3343 #define DMA_LIFCR_CHTIF1 0x00000400U
3344 #define DMA_LIFCR_CTEIF1 0x00000200U
3345 #define DMA_LIFCR_CDMEIF1 0x00000100U
3346 #define DMA_LIFCR_CFEIF1 0x00000040U
3347 #define DMA_LIFCR_CTCIF0 0x00000020U
3348 #define DMA_LIFCR_CHTIF0 0x00000010U
3349 #define DMA_LIFCR_CTEIF0 0x00000008U
3350 #define DMA_LIFCR_CDMEIF0 0x00000004U
3351 #define DMA_LIFCR_CFEIF0 0x00000001U
3352 
3353 /******************** Bits definition for DMA_HIFCR register ****************/
3354 #define DMA_HIFCR_CTCIF7 0x08000000U
3355 #define DMA_HIFCR_CHTIF7 0x04000000U
3356 #define DMA_HIFCR_CTEIF7 0x02000000U
3357 #define DMA_HIFCR_CDMEIF7 0x01000000U
3358 #define DMA_HIFCR_CFEIF7 0x00400000U
3359 #define DMA_HIFCR_CTCIF6 0x00200000U
3360 #define DMA_HIFCR_CHTIF6 0x00100000U
3361 #define DMA_HIFCR_CTEIF6 0x00080000U
3362 #define DMA_HIFCR_CDMEIF6 0x00040000U
3363 #define DMA_HIFCR_CFEIF6 0x00010000U
3364 #define DMA_HIFCR_CTCIF5 0x00000800U
3365 #define DMA_HIFCR_CHTIF5 0x00000400U
3366 #define DMA_HIFCR_CTEIF5 0x00000200U
3367 #define DMA_HIFCR_CDMEIF5 0x00000100U
3368 #define DMA_HIFCR_CFEIF5 0x00000040U
3369 #define DMA_HIFCR_CTCIF4 0x00000020U
3370 #define DMA_HIFCR_CHTIF4 0x00000010U
3371 #define DMA_HIFCR_CTEIF4 0x00000008U
3372 #define DMA_HIFCR_CDMEIF4 0x00000004U
3373 #define DMA_HIFCR_CFEIF4 0x00000001U
3374 
3375 
3376 /******************************************************************************/
3377 /* */
3378 /* External Interrupt/Event Controller */
3379 /* */
3380 /******************************************************************************/
3381 /******************* Bit definition for EXTI_IMR register *******************/
3382 #define EXTI_IMR_MR0 0x00000001U
3383 #define EXTI_IMR_MR1 0x00000002U
3384 #define EXTI_IMR_MR2 0x00000004U
3385 #define EXTI_IMR_MR3 0x00000008U
3386 #define EXTI_IMR_MR4 0x00000010U
3387 #define EXTI_IMR_MR5 0x00000020U
3388 #define EXTI_IMR_MR6 0x00000040U
3389 #define EXTI_IMR_MR7 0x00000080U
3390 #define EXTI_IMR_MR8 0x00000100U
3391 #define EXTI_IMR_MR9 0x00000200U
3392 #define EXTI_IMR_MR10 0x00000400U
3393 #define EXTI_IMR_MR11 0x00000800U
3394 #define EXTI_IMR_MR12 0x00001000U
3395 #define EXTI_IMR_MR13 0x00002000U
3396 #define EXTI_IMR_MR14 0x00004000U
3397 #define EXTI_IMR_MR15 0x00008000U
3398 #define EXTI_IMR_MR16 0x00010000U
3399 #define EXTI_IMR_MR17 0x00020000U
3400 #define EXTI_IMR_MR18 0x00040000U
3401 #define EXTI_IMR_MR19 0x00080000U
3402 #define EXTI_IMR_MR20 0x00100000U
3403 #define EXTI_IMR_MR21 0x00200000U
3404 #define EXTI_IMR_MR22 0x00400000U
3406 /******************* Bit definition for EXTI_EMR register *******************/
3407 #define EXTI_EMR_MR0 0x00000001U
3408 #define EXTI_EMR_MR1 0x00000002U
3409 #define EXTI_EMR_MR2 0x00000004U
3410 #define EXTI_EMR_MR3 0x00000008U
3411 #define EXTI_EMR_MR4 0x00000010U
3412 #define EXTI_EMR_MR5 0x00000020U
3413 #define EXTI_EMR_MR6 0x00000040U
3414 #define EXTI_EMR_MR7 0x00000080U
3415 #define EXTI_EMR_MR8 0x00000100U
3416 #define EXTI_EMR_MR9 0x00000200U
3417 #define EXTI_EMR_MR10 0x00000400U
3418 #define EXTI_EMR_MR11 0x00000800U
3419 #define EXTI_EMR_MR12 0x00001000U
3420 #define EXTI_EMR_MR13 0x00002000U
3421 #define EXTI_EMR_MR14 0x00004000U
3422 #define EXTI_EMR_MR15 0x00008000U
3423 #define EXTI_EMR_MR16 0x00010000U
3424 #define EXTI_EMR_MR17 0x00020000U
3425 #define EXTI_EMR_MR18 0x00040000U
3426 #define EXTI_EMR_MR19 0x00080000U
3427 #define EXTI_EMR_MR20 0x00100000U
3428 #define EXTI_EMR_MR21 0x00200000U
3429 #define EXTI_EMR_MR22 0x00400000U
3431 /****************** Bit definition for EXTI_RTSR register *******************/
3432 #define EXTI_RTSR_TR0 0x00000001U
3433 #define EXTI_RTSR_TR1 0x00000002U
3434 #define EXTI_RTSR_TR2 0x00000004U
3435 #define EXTI_RTSR_TR3 0x00000008U
3436 #define EXTI_RTSR_TR4 0x00000010U
3437 #define EXTI_RTSR_TR5 0x00000020U
3438 #define EXTI_RTSR_TR6 0x00000040U
3439 #define EXTI_RTSR_TR7 0x00000080U
3440 #define EXTI_RTSR_TR8 0x00000100U
3441 #define EXTI_RTSR_TR9 0x00000200U
3442 #define EXTI_RTSR_TR10 0x00000400U
3443 #define EXTI_RTSR_TR11 0x00000800U
3444 #define EXTI_RTSR_TR12 0x00001000U
3445 #define EXTI_RTSR_TR13 0x00002000U
3446 #define EXTI_RTSR_TR14 0x00004000U
3447 #define EXTI_RTSR_TR15 0x00008000U
3448 #define EXTI_RTSR_TR16 0x00010000U
3449 #define EXTI_RTSR_TR17 0x00020000U
3450 #define EXTI_RTSR_TR18 0x00040000U
3451 #define EXTI_RTSR_TR19 0x00080000U
3452 #define EXTI_RTSR_TR20 0x00100000U
3453 #define EXTI_RTSR_TR21 0x00200000U
3454 #define EXTI_RTSR_TR22 0x00400000U
3456 /****************** Bit definition for EXTI_FTSR register *******************/
3457 #define EXTI_FTSR_TR0 0x00000001U
3458 #define EXTI_FTSR_TR1 0x00000002U
3459 #define EXTI_FTSR_TR2 0x00000004U
3460 #define EXTI_FTSR_TR3 0x00000008U
3461 #define EXTI_FTSR_TR4 0x00000010U
3462 #define EXTI_FTSR_TR5 0x00000020U
3463 #define EXTI_FTSR_TR6 0x00000040U
3464 #define EXTI_FTSR_TR7 0x00000080U
3465 #define EXTI_FTSR_TR8 0x00000100U
3466 #define EXTI_FTSR_TR9 0x00000200U
3467 #define EXTI_FTSR_TR10 0x00000400U
3468 #define EXTI_FTSR_TR11 0x00000800U
3469 #define EXTI_FTSR_TR12 0x00001000U
3470 #define EXTI_FTSR_TR13 0x00002000U
3471 #define EXTI_FTSR_TR14 0x00004000U
3472 #define EXTI_FTSR_TR15 0x00008000U
3473 #define EXTI_FTSR_TR16 0x00010000U
3474 #define EXTI_FTSR_TR17 0x00020000U
3475 #define EXTI_FTSR_TR18 0x00040000U
3476 #define EXTI_FTSR_TR19 0x00080000U
3477 #define EXTI_FTSR_TR20 0x00100000U
3478 #define EXTI_FTSR_TR21 0x00200000U
3479 #define EXTI_FTSR_TR22 0x00400000U
3481 /****************** Bit definition for EXTI_SWIER register ******************/
3482 #define EXTI_SWIER_SWIER0 0x00000001U
3483 #define EXTI_SWIER_SWIER1 0x00000002U
3484 #define EXTI_SWIER_SWIER2 0x00000004U
3485 #define EXTI_SWIER_SWIER3 0x00000008U
3486 #define EXTI_SWIER_SWIER4 0x00000010U
3487 #define EXTI_SWIER_SWIER5 0x00000020U
3488 #define EXTI_SWIER_SWIER6 0x00000040U
3489 #define EXTI_SWIER_SWIER7 0x00000080U
3490 #define EXTI_SWIER_SWIER8 0x00000100U
3491 #define EXTI_SWIER_SWIER9 0x00000200U
3492 #define EXTI_SWIER_SWIER10 0x00000400U
3493 #define EXTI_SWIER_SWIER11 0x00000800U
3494 #define EXTI_SWIER_SWIER12 0x00001000U
3495 #define EXTI_SWIER_SWIER13 0x00002000U
3496 #define EXTI_SWIER_SWIER14 0x00004000U
3497 #define EXTI_SWIER_SWIER15 0x00008000U
3498 #define EXTI_SWIER_SWIER16 0x00010000U
3499 #define EXTI_SWIER_SWIER17 0x00020000U
3500 #define EXTI_SWIER_SWIER18 0x00040000U
3501 #define EXTI_SWIER_SWIER19 0x00080000U
3502 #define EXTI_SWIER_SWIER20 0x00100000U
3503 #define EXTI_SWIER_SWIER21 0x00200000U
3504 #define EXTI_SWIER_SWIER22 0x00400000U
3506 /******************* Bit definition for EXTI_PR register ********************/
3507 #define EXTI_PR_PR0 0x00000001U
3508 #define EXTI_PR_PR1 0x00000002U
3509 #define EXTI_PR_PR2 0x00000004U
3510 #define EXTI_PR_PR3 0x00000008U
3511 #define EXTI_PR_PR4 0x00000010U
3512 #define EXTI_PR_PR5 0x00000020U
3513 #define EXTI_PR_PR6 0x00000040U
3514 #define EXTI_PR_PR7 0x00000080U
3515 #define EXTI_PR_PR8 0x00000100U
3516 #define EXTI_PR_PR9 0x00000200U
3517 #define EXTI_PR_PR10 0x00000400U
3518 #define EXTI_PR_PR11 0x00000800U
3519 #define EXTI_PR_PR12 0x00001000U
3520 #define EXTI_PR_PR13 0x00002000U
3521 #define EXTI_PR_PR14 0x00004000U
3522 #define EXTI_PR_PR15 0x00008000U
3523 #define EXTI_PR_PR16 0x00010000U
3524 #define EXTI_PR_PR17 0x00020000U
3525 #define EXTI_PR_PR18 0x00040000U
3526 #define EXTI_PR_PR19 0x00080000U
3527 #define EXTI_PR_PR20 0x00100000U
3528 #define EXTI_PR_PR21 0x00200000U
3529 #define EXTI_PR_PR22 0x00400000U
3531 /******************************************************************************/
3532 /* */
3533 /* FLASH */
3534 /* */
3535 /******************************************************************************/
3536 /******************* Bits definition for FLASH_ACR register *****************/
3537 #define FLASH_ACR_LATENCY 0x0000000FU
3538 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3539 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3540 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3541 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3542 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3543 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3544 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3545 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3546 
3547 #define FLASH_ACR_PRFTEN 0x00000100U
3548 #define FLASH_ACR_ICEN 0x00000200U
3549 #define FLASH_ACR_DCEN 0x00000400U
3550 #define FLASH_ACR_ICRST 0x00000800U
3551 #define FLASH_ACR_DCRST 0x00001000U
3552 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3553 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3554 
3555 /******************* Bits definition for FLASH_SR register ******************/
3556 #define FLASH_SR_EOP 0x00000001U
3557 #define FLASH_SR_SOP 0x00000002U
3558 #define FLASH_SR_WRPERR 0x00000010U
3559 #define FLASH_SR_PGAERR 0x00000020U
3560 #define FLASH_SR_PGPERR 0x00000040U
3561 #define FLASH_SR_PGSERR 0x00000080U
3562 #define FLASH_SR_BSY 0x00010000U
3563 
3564 /******************* Bits definition for FLASH_CR register ******************/
3565 #define FLASH_CR_PG 0x00000001U
3566 #define FLASH_CR_SER 0x00000002U
3567 #define FLASH_CR_MER 0x00000004U
3568 #define FLASH_CR_SNB 0x000000F8U
3569 #define FLASH_CR_SNB_0 0x00000008U
3570 #define FLASH_CR_SNB_1 0x00000010U
3571 #define FLASH_CR_SNB_2 0x00000020U
3572 #define FLASH_CR_SNB_3 0x00000040U
3573 #define FLASH_CR_SNB_4 0x00000080U
3574 #define FLASH_CR_PSIZE 0x00000300U
3575 #define FLASH_CR_PSIZE_0 0x00000100U
3576 #define FLASH_CR_PSIZE_1 0x00000200U
3577 #define FLASH_CR_STRT 0x00010000U
3578 #define FLASH_CR_EOPIE 0x01000000U
3579 #define FLASH_CR_LOCK 0x80000000U
3580 
3581 /******************* Bits definition for FLASH_OPTCR register ***************/
3582 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3583 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3584 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3585 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3586 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3587 
3588 #define FLASH_OPTCR_WDG_SW 0x00000020U
3589 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3590 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3591 #define FLASH_OPTCR_RDP 0x0000FF00U
3592 #define FLASH_OPTCR_RDP_0 0x00000100U
3593 #define FLASH_OPTCR_RDP_1 0x00000200U
3594 #define FLASH_OPTCR_RDP_2 0x00000400U
3595 #define FLASH_OPTCR_RDP_3 0x00000800U
3596 #define FLASH_OPTCR_RDP_4 0x00001000U
3597 #define FLASH_OPTCR_RDP_5 0x00002000U
3598 #define FLASH_OPTCR_RDP_6 0x00004000U
3599 #define FLASH_OPTCR_RDP_7 0x00008000U
3600 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3601 #define FLASH_OPTCR_nWRP_0 0x00010000U
3602 #define FLASH_OPTCR_nWRP_1 0x00020000U
3603 #define FLASH_OPTCR_nWRP_2 0x00040000U
3604 #define FLASH_OPTCR_nWRP_3 0x00080000U
3605 #define FLASH_OPTCR_nWRP_4 0x00100000U
3606 #define FLASH_OPTCR_nWRP_5 0x00200000U
3607 #define FLASH_OPTCR_nWRP_6 0x00400000U
3608 #define FLASH_OPTCR_nWRP_7 0x00800000U
3609 #define FLASH_OPTCR_nWRP_8 0x01000000U
3610 #define FLASH_OPTCR_nWRP_9 0x02000000U
3611 #define FLASH_OPTCR_nWRP_10 0x04000000U
3612 #define FLASH_OPTCR_nWRP_11 0x08000000U
3613 
3614 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3615 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3616 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3617 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3618 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3619 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3620 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3621 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3622 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3623 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3624 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3625 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3626 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3627 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3628 
3629 /******************************************************************************/
3630 /* */
3631 /* Flexible Static Memory Controller */
3632 /* */
3633 /******************************************************************************/
3634 /****************** Bit definition for FSMC_BCR1 register *******************/
3635 #define FSMC_BCR1_MBKEN 0x00000001U
3636 #define FSMC_BCR1_MUXEN 0x00000002U
3638 #define FSMC_BCR1_MTYP 0x0000000CU
3639 #define FSMC_BCR1_MTYP_0 0x00000004U
3640 #define FSMC_BCR1_MTYP_1 0x00000008U
3642 #define FSMC_BCR1_MWID 0x00000030U
3643 #define FSMC_BCR1_MWID_0 0x00000010U
3644 #define FSMC_BCR1_MWID_1 0x00000020U
3646 #define FSMC_BCR1_FACCEN 0x00000040U
3647 #define FSMC_BCR1_BURSTEN 0x00000100U
3648 #define FSMC_BCR1_WAITPOL 0x00000200U
3649 #define FSMC_BCR1_WRAPMOD 0x00000400U
3650 #define FSMC_BCR1_WAITCFG 0x00000800U
3651 #define FSMC_BCR1_WREN 0x00001000U
3652 #define FSMC_BCR1_WAITEN 0x00002000U
3653 #define FSMC_BCR1_EXTMOD 0x00004000U
3654 #define FSMC_BCR1_ASYNCWAIT 0x00008000U
3655 #define FSMC_BCR1_CPSIZE 0x00070000U
3656 #define FSMC_BCR1_CPSIZE_0 0x00010000U
3657 #define FSMC_BCR1_CPSIZE_1 0x00020000U
3658 #define FSMC_BCR1_CPSIZE_2 0x00040000U
3659 #define FSMC_BCR1_CBURSTRW 0x00080000U
3661 /****************** Bit definition for FSMC_BCR2 register *******************/
3662 #define FSMC_BCR2_MBKEN 0x00000001U
3663 #define FSMC_BCR2_MUXEN 0x00000002U
3665 #define FSMC_BCR2_MTYP 0x0000000CU
3666 #define FSMC_BCR2_MTYP_0 0x00000004U
3667 #define FSMC_BCR2_MTYP_1 0x00000008U
3669 #define FSMC_BCR2_MWID 0x00000030U
3670 #define FSMC_BCR2_MWID_0 0x00000010U
3671 #define FSMC_BCR2_MWID_1 0x00000020U
3673 #define FSMC_BCR2_FACCEN 0x00000040U
3674 #define FSMC_BCR2_BURSTEN 0x00000100U
3675 #define FSMC_BCR2_WAITPOL 0x00000200U
3676 #define FSMC_BCR2_WRAPMOD 0x00000400U
3677 #define FSMC_BCR2_WAITCFG 0x00000800U
3678 #define FSMC_BCR2_WREN 0x00001000U
3679 #define FSMC_BCR2_WAITEN 0x00002000U
3680 #define FSMC_BCR2_EXTMOD 0x00004000U
3681 #define FSMC_BCR2_ASYNCWAIT 0x00008000U
3682 #define FSMC_BCR2_CPSIZE 0x00070000U
3683 #define FSMC_BCR2_CPSIZE_0 0x00010000U
3684 #define FSMC_BCR2_CPSIZE_1 0x00020000U
3685 #define FSMC_BCR2_CPSIZE_2 0x00040000U
3686 #define FSMC_BCR2_CBURSTRW 0x00080000U
3688 /****************** Bit definition for FSMC_BCR3 register *******************/
3689 #define FSMC_BCR3_MBKEN 0x00000001U
3690 #define FSMC_BCR3_MUXEN 0x00000002U
3692 #define FSMC_BCR3_MTYP 0x0000000CU
3693 #define FSMC_BCR3_MTYP_0 0x00000004U
3694 #define FSMC_BCR3_MTYP_1 0x00000008U
3696 #define FSMC_BCR3_MWID 0x00000030U
3697 #define FSMC_BCR3_MWID_0 0x00000010U
3698 #define FSMC_BCR3_MWID_1 0x00000020U
3700 #define FSMC_BCR3_FACCEN 0x00000040U
3701 #define FSMC_BCR3_BURSTEN 0x00000100U
3702 #define FSMC_BCR3_WAITPOL 0x00000200U
3703 #define FSMC_BCR3_WRAPMOD 0x00000400U
3704 #define FSMC_BCR3_WAITCFG 0x00000800U
3705 #define FSMC_BCR3_WREN 0x00001000U
3706 #define FSMC_BCR3_WAITEN 0x00002000U
3707 #define FSMC_BCR3_EXTMOD 0x00004000U
3708 #define FSMC_BCR3_ASYNCWAIT 0x00008000U
3709 #define FSMC_BCR3_CPSIZE 0x00070000U
3710 #define FSMC_BCR3_CPSIZE_0 0x00010000U
3711 #define FSMC_BCR3_CPSIZE_1 0x00020000U
3712 #define FSMC_BCR3_CPSIZE_2 0x00040000U
3713 #define FSMC_BCR3_CBURSTRW 0x00080000U
3715 /****************** Bit definition for FSMC_BCR4 register *******************/
3716 #define FSMC_BCR4_MBKEN 0x00000001U
3717 #define FSMC_BCR4_MUXEN 0x00000002U
3719 #define FSMC_BCR4_MTYP 0x0000000CU
3720 #define FSMC_BCR4_MTYP_0 0x00000004U
3721 #define FSMC_BCR4_MTYP_1 0x00000008U
3723 #define FSMC_BCR4_MWID 0x00000030U
3724 #define FSMC_BCR4_MWID_0 0x00000010U
3725 #define FSMC_BCR4_MWID_1 0x00000020U
3727 #define FSMC_BCR4_FACCEN 0x00000040U
3728 #define FSMC_BCR4_BURSTEN 0x00000100U
3729 #define FSMC_BCR4_WAITPOL 0x00000200U
3730 #define FSMC_BCR4_WRAPMOD 0x00000400U
3731 #define FSMC_BCR4_WAITCFG 0x00000800U
3732 #define FSMC_BCR4_WREN 0x00001000U
3733 #define FSMC_BCR4_WAITEN 0x00002000U
3734 #define FSMC_BCR4_EXTMOD 0x00004000U
3735 #define FSMC_BCR4_ASYNCWAIT 0x00008000U
3736 #define FSMC_BCR4_CPSIZE 0x00070000U
3737 #define FSMC_BCR4_CPSIZE_0 0x00010000U
3738 #define FSMC_BCR4_CPSIZE_1 0x00020000U
3739 #define FSMC_BCR4_CPSIZE_2 0x00040000U
3740 #define FSMC_BCR4_CBURSTRW 0x00080000U
3742 /****************** Bit definition for FSMC_BTR1 register ******************/
3743 #define FSMC_BTR1_ADDSET 0x0000000FU
3744 #define FSMC_BTR1_ADDSET_0 0x00000001U
3745 #define FSMC_BTR1_ADDSET_1 0x00000002U
3746 #define FSMC_BTR1_ADDSET_2 0x00000004U
3747 #define FSMC_BTR1_ADDSET_3 0x00000008U
3749 #define FSMC_BTR1_ADDHLD 0x000000F0U
3750 #define FSMC_BTR1_ADDHLD_0 0x00000010U
3751 #define FSMC_BTR1_ADDHLD_1 0x00000020U
3752 #define FSMC_BTR1_ADDHLD_2 0x00000040U
3753 #define FSMC_BTR1_ADDHLD_3 0x00000080U
3755 #define FSMC_BTR1_DATAST 0x0000FF00U
3756 #define FSMC_BTR1_DATAST_0 0x00000100U
3757 #define FSMC_BTR1_DATAST_1 0x00000200U
3758 #define FSMC_BTR1_DATAST_2 0x00000400U
3759 #define FSMC_BTR1_DATAST_3 0x00000800U
3760 #define FSMC_BTR1_DATAST_4 0x00001000U
3761 #define FSMC_BTR1_DATAST_5 0x00002000U
3762 #define FSMC_BTR1_DATAST_6 0x00004000U
3763 #define FSMC_BTR1_DATAST_7 0x00008000U
3765 #define FSMC_BTR1_BUSTURN 0x000F0000U
3766 #define FSMC_BTR1_BUSTURN_0 0x00010000U
3767 #define FSMC_BTR1_BUSTURN_1 0x00020000U
3768 #define FSMC_BTR1_BUSTURN_2 0x00040000U
3769 #define FSMC_BTR1_BUSTURN_3 0x00080000U
3771 #define FSMC_BTR1_CLKDIV 0x00F00000U
3772 #define FSMC_BTR1_CLKDIV_0 0x00100000U
3773 #define FSMC_BTR1_CLKDIV_1 0x00200000U
3774 #define FSMC_BTR1_CLKDIV_2 0x00400000U
3775 #define FSMC_BTR1_CLKDIV_3 0x00800000U
3777 #define FSMC_BTR1_DATLAT 0x0F000000U
3778 #define FSMC_BTR1_DATLAT_0 0x01000000U
3779 #define FSMC_BTR1_DATLAT_1 0x02000000U
3780 #define FSMC_BTR1_DATLAT_2 0x04000000U
3781 #define FSMC_BTR1_DATLAT_3 0x08000000U
3783 #define FSMC_BTR1_ACCMOD 0x30000000U
3784 #define FSMC_BTR1_ACCMOD_0 0x10000000U
3785 #define FSMC_BTR1_ACCMOD_1 0x20000000U
3787 /****************** Bit definition for FSMC_BTR2 register *******************/
3788 #define FSMC_BTR2_ADDSET 0x0000000FU
3789 #define FSMC_BTR2_ADDSET_0 0x00000001U
3790 #define FSMC_BTR2_ADDSET_1 0x00000002U
3791 #define FSMC_BTR2_ADDSET_2 0x00000004U
3792 #define FSMC_BTR2_ADDSET_3 0x00000008U
3794 #define FSMC_BTR2_ADDHLD 0x000000F0U
3795 #define FSMC_BTR2_ADDHLD_0 0x00000010U
3796 #define FSMC_BTR2_ADDHLD_1 0x00000020U
3797 #define FSMC_BTR2_ADDHLD_2 0x00000040U
3798 #define FSMC_BTR2_ADDHLD_3 0x00000080U
3800 #define FSMC_BTR2_DATAST 0x0000FF00U
3801 #define FSMC_BTR2_DATAST_0 0x00000100U
3802 #define FSMC_BTR2_DATAST_1 0x00000200U
3803 #define FSMC_BTR2_DATAST_2 0x00000400U
3804 #define FSMC_BTR2_DATAST_3 0x00000800U
3805 #define FSMC_BTR2_DATAST_4 0x00001000U
3806 #define FSMC_BTR2_DATAST_5 0x00002000U
3807 #define FSMC_BTR2_DATAST_6 0x00004000U
3808 #define FSMC_BTR2_DATAST_7 0x00008000U
3810 #define FSMC_BTR2_BUSTURN 0x000F0000U
3811 #define FSMC_BTR2_BUSTURN_0 0x00010000U
3812 #define FSMC_BTR2_BUSTURN_1 0x00020000U
3813 #define FSMC_BTR2_BUSTURN_2 0x00040000U
3814 #define FSMC_BTR2_BUSTURN_3 0x00080000U
3816 #define FSMC_BTR2_CLKDIV 0x00F00000U
3817 #define FSMC_BTR2_CLKDIV_0 0x00100000U
3818 #define FSMC_BTR2_CLKDIV_1 0x00200000U
3819 #define FSMC_BTR2_CLKDIV_2 0x00400000U
3820 #define FSMC_BTR2_CLKDIV_3 0x00800000U
3822 #define FSMC_BTR2_DATLAT 0x0F000000U
3823 #define FSMC_BTR2_DATLAT_0 0x01000000U
3824 #define FSMC_BTR2_DATLAT_1 0x02000000U
3825 #define FSMC_BTR2_DATLAT_2 0x04000000U
3826 #define FSMC_BTR2_DATLAT_3 0x08000000U
3828 #define FSMC_BTR2_ACCMOD 0x30000000U
3829 #define FSMC_BTR2_ACCMOD_0 0x10000000U
3830 #define FSMC_BTR2_ACCMOD_1 0x20000000U
3832 /******************* Bit definition for FSMC_BTR3 register *******************/
3833 #define FSMC_BTR3_ADDSET 0x0000000FU
3834 #define FSMC_BTR3_ADDSET_0 0x00000001U
3835 #define FSMC_BTR3_ADDSET_1 0x00000002U
3836 #define FSMC_BTR3_ADDSET_2 0x00000004U
3837 #define FSMC_BTR3_ADDSET_3 0x00000008U
3839 #define FSMC_BTR3_ADDHLD 0x000000F0U
3840 #define FSMC_BTR3_ADDHLD_0 0x00000010U
3841 #define FSMC_BTR3_ADDHLD_1 0x00000020U
3842 #define FSMC_BTR3_ADDHLD_2 0x00000040U
3843 #define FSMC_BTR3_ADDHLD_3 0x00000080U
3845 #define FSMC_BTR3_DATAST 0x0000FF00U
3846 #define FSMC_BTR3_DATAST_0 0x00000100U
3847 #define FSMC_BTR3_DATAST_1 0x00000200U
3848 #define FSMC_BTR3_DATAST_2 0x00000400U
3849 #define FSMC_BTR3_DATAST_3 0x00000800U
3850 #define FSMC_BTR3_DATAST_4 0x00001000U
3851 #define FSMC_BTR3_DATAST_5 0x00002000U
3852 #define FSMC_BTR3_DATAST_6 0x00004000U
3853 #define FSMC_BTR3_DATAST_7 0x00008000U
3855 #define FSMC_BTR3_BUSTURN 0x000F0000U
3856 #define FSMC_BTR3_BUSTURN_0 0x00010000U
3857 #define FSMC_BTR3_BUSTURN_1 0x00020000U
3858 #define FSMC_BTR3_BUSTURN_2 0x00040000U
3859 #define FSMC_BTR3_BUSTURN_3 0x00080000U
3861 #define FSMC_BTR3_CLKDIV 0x00F00000U
3862 #define FSMC_BTR3_CLKDIV_0 0x00100000U
3863 #define FSMC_BTR3_CLKDIV_1 0x00200000U
3864 #define FSMC_BTR3_CLKDIV_2 0x00400000U
3865 #define FSMC_BTR3_CLKDIV_3 0x00800000U
3867 #define FSMC_BTR3_DATLAT 0x0F000000U
3868 #define FSMC_BTR3_DATLAT_0 0x01000000U
3869 #define FSMC_BTR3_DATLAT_1 0x02000000U
3870 #define FSMC_BTR3_DATLAT_2 0x04000000U
3871 #define FSMC_BTR3_DATLAT_3 0x08000000U
3873 #define FSMC_BTR3_ACCMOD 0x30000000U
3874 #define FSMC_BTR3_ACCMOD_0 0x10000000U
3875 #define FSMC_BTR3_ACCMOD_1 0x20000000U
3877 /****************** Bit definition for FSMC_BTR4 register *******************/
3878 #define FSMC_BTR4_ADDSET 0x0000000FU
3879 #define FSMC_BTR4_ADDSET_0 0x00000001U
3880 #define FSMC_BTR4_ADDSET_1 0x00000002U
3881 #define FSMC_BTR4_ADDSET_2 0x00000004U
3882 #define FSMC_BTR4_ADDSET_3 0x00000008U
3884 #define FSMC_BTR4_ADDHLD 0x000000F0U
3885 #define FSMC_BTR4_ADDHLD_0 0x00000010U
3886 #define FSMC_BTR4_ADDHLD_1 0x00000020U
3887 #define FSMC_BTR4_ADDHLD_2 0x00000040U
3888 #define FSMC_BTR4_ADDHLD_3 0x00000080U
3890 #define FSMC_BTR4_DATAST 0x0000FF00U
3891 #define FSMC_BTR4_DATAST_0 0x00000100U
3892 #define FSMC_BTR4_DATAST_1 0x00000200U
3893 #define FSMC_BTR4_DATAST_2 0x00000400U
3894 #define FSMC_BTR4_DATAST_3 0x00000800U
3895 #define FSMC_BTR4_DATAST_4 0x00001000U
3896 #define FSMC_BTR4_DATAST_5 0x00002000U
3897 #define FSMC_BTR4_DATAST_6 0x00004000U
3898 #define FSMC_BTR4_DATAST_7 0x00008000U
3900 #define FSMC_BTR4_BUSTURN 0x000F0000U
3901 #define FSMC_BTR4_BUSTURN_0 0x00010000U
3902 #define FSMC_BTR4_BUSTURN_1 0x00020000U
3903 #define FSMC_BTR4_BUSTURN_2 0x00040000U
3904 #define FSMC_BTR4_BUSTURN_3 0x00080000U
3906 #define FSMC_BTR4_CLKDIV 0x00F00000U
3907 #define FSMC_BTR4_CLKDIV_0 0x00100000U
3908 #define FSMC_BTR4_CLKDIV_1 0x00200000U
3909 #define FSMC_BTR4_CLKDIV_2 0x00400000U
3910 #define FSMC_BTR4_CLKDIV_3 0x00800000U
3912 #define FSMC_BTR4_DATLAT 0x0F000000U
3913 #define FSMC_BTR4_DATLAT_0 0x01000000U
3914 #define FSMC_BTR4_DATLAT_1 0x02000000U
3915 #define FSMC_BTR4_DATLAT_2 0x04000000U
3916 #define FSMC_BTR4_DATLAT_3 0x08000000U
3918 #define FSMC_BTR4_ACCMOD 0x30000000U
3919 #define FSMC_BTR4_ACCMOD_0 0x10000000U
3920 #define FSMC_BTR4_ACCMOD_1 0x20000000U
3922 /****************** Bit definition for FSMC_BWTR1 register ******************/
3923 #define FSMC_BWTR1_ADDSET 0x0000000FU
3924 #define FSMC_BWTR1_ADDSET_0 0x00000001U
3925 #define FSMC_BWTR1_ADDSET_1 0x00000002U
3926 #define FSMC_BWTR1_ADDSET_2 0x00000004U
3927 #define FSMC_BWTR1_ADDSET_3 0x00000008U
3929 #define FSMC_BWTR1_ADDHLD 0x000000F0U
3930 #define FSMC_BWTR1_ADDHLD_0 0x00000010U
3931 #define FSMC_BWTR1_ADDHLD_1 0x00000020U
3932 #define FSMC_BWTR1_ADDHLD_2 0x00000040U
3933 #define FSMC_BWTR1_ADDHLD_3 0x00000080U
3935 #define FSMC_BWTR1_DATAST 0x0000FF00U
3936 #define FSMC_BWTR1_DATAST_0 0x00000100U
3937 #define FSMC_BWTR1_DATAST_1 0x00000200U
3938 #define FSMC_BWTR1_DATAST_2 0x00000400U
3939 #define FSMC_BWTR1_DATAST_3 0x00000800U
3940 #define FSMC_BWTR1_DATAST_4 0x00001000U
3941 #define FSMC_BWTR1_DATAST_5 0x00002000U
3942 #define FSMC_BWTR1_DATAST_6 0x00004000U
3943 #define FSMC_BWTR1_DATAST_7 0x00008000U
3945 #define FSMC_BWTR1_BUSTURN 0x000F0000U
3946 #define FSMC_BWTR1_BUSTURN_0 0x00010000U
3947 #define FSMC_BWTR1_BUSTURN_1 0x00020000U
3948 #define FSMC_BWTR1_BUSTURN_2 0x00040000U
3949 #define FSMC_BWTR1_BUSTURN_3 0x00080000U
3951 #define FSMC_BWTR1_ACCMOD 0x30000000U
3952 #define FSMC_BWTR1_ACCMOD_0 0x10000000U
3953 #define FSMC_BWTR1_ACCMOD_1 0x20000000U
3955 /****************** Bit definition for FSMC_BWTR2 register ******************/
3956 #define FSMC_BWTR2_ADDSET 0x0000000FU
3957 #define FSMC_BWTR2_ADDSET_0 0x00000001U
3958 #define FSMC_BWTR2_ADDSET_1 0x00000002U
3959 #define FSMC_BWTR2_ADDSET_2 0x00000004U
3960 #define FSMC_BWTR2_ADDSET_3 0x00000008U
3962 #define FSMC_BWTR2_ADDHLD 0x000000F0U
3963 #define FSMC_BWTR2_ADDHLD_0 0x00000010U
3964 #define FSMC_BWTR2_ADDHLD_1 0x00000020U
3965 #define FSMC_BWTR2_ADDHLD_2 0x00000040U
3966 #define FSMC_BWTR2_ADDHLD_3 0x00000080U
3968 #define FSMC_BWTR2_DATAST 0x0000FF00U
3969 #define FSMC_BWTR2_DATAST_0 0x00000100U
3970 #define FSMC_BWTR2_DATAST_1 0x00000200U
3971 #define FSMC_BWTR2_DATAST_2 0x00000400U
3972 #define FSMC_BWTR2_DATAST_3 0x00000800U
3973 #define FSMC_BWTR2_DATAST_4 0x00001000U
3974 #define FSMC_BWTR2_DATAST_5 0x00002000U
3975 #define FSMC_BWTR2_DATAST_6 0x00004000U
3976 #define FSMC_BWTR2_DATAST_7 0x00008000U
3978 #define FSMC_BWTR2_BUSTURN 0x000F0000U
3979 #define FSMC_BWTR2_BUSTURN_0 0x00010000U
3980 #define FSMC_BWTR2_BUSTURN_1 0x00020000U
3981 #define FSMC_BWTR2_BUSTURN_2 0x00040000U
3982 #define FSMC_BWTR2_BUSTURN_3 0x00080000U
3984 #define FSMC_BWTR2_ACCMOD 0x30000000U
3985 #define FSMC_BWTR2_ACCMOD_0 0x10000000U
3986 #define FSMC_BWTR2_ACCMOD_1 0x20000000U
3988 /****************** Bit definition for FSMC_BWTR3 register ******************/
3989 #define FSMC_BWTR3_ADDSET 0x0000000FU
3990 #define FSMC_BWTR3_ADDSET_0 0x00000001U
3991 #define FSMC_BWTR3_ADDSET_1 0x00000002U
3992 #define FSMC_BWTR3_ADDSET_2 0x00000004U
3993 #define FSMC_BWTR3_ADDSET_3 0x00000008U
3995 #define FSMC_BWTR3_ADDHLD 0x000000F0U
3996 #define FSMC_BWTR3_ADDHLD_0 0x00000010U
3997 #define FSMC_BWTR3_ADDHLD_1 0x00000020U
3998 #define FSMC_BWTR3_ADDHLD_2 0x00000040U
3999 #define FSMC_BWTR3_ADDHLD_3 0x00000080U
4001 #define FSMC_BWTR3_DATAST 0x0000FF00U
4002 #define FSMC_BWTR3_DATAST_0 0x00000100U
4003 #define FSMC_BWTR3_DATAST_1 0x00000200U
4004 #define FSMC_BWTR3_DATAST_2 0x00000400U
4005 #define FSMC_BWTR3_DATAST_3 0x00000800U
4006 #define FSMC_BWTR3_DATAST_4 0x00001000U
4007 #define FSMC_BWTR3_DATAST_5 0x00002000U
4008 #define FSMC_BWTR3_DATAST_6 0x00004000U
4009 #define FSMC_BWTR3_DATAST_7 0x00008000U
4011 #define FSMC_BWTR3_BUSTURN 0x000F0000U
4012 #define FSMC_BWTR3_BUSTURN_0 0x00010000U
4013 #define FSMC_BWTR3_BUSTURN_1 0x00020000U
4014 #define FSMC_BWTR3_BUSTURN_2 0x00040000U
4015 #define FSMC_BWTR3_BUSTURN_3 0x00080000U
4017 #define FSMC_BWTR3_ACCMOD 0x30000000U
4018 #define FSMC_BWTR3_ACCMOD_0 0x10000000U
4019 #define FSMC_BWTR3_ACCMOD_1 0x20000000U
4021 /****************** Bit definition for FSMC_BWTR4 register ******************/
4022 #define FSMC_BWTR4_ADDSET 0x0000000FU
4023 #define FSMC_BWTR4_ADDSET_0 0x00000001U
4024 #define FSMC_BWTR4_ADDSET_1 0x00000002U
4025 #define FSMC_BWTR4_ADDSET_2 0x00000004U
4026 #define FSMC_BWTR4_ADDSET_3 0x00000008U
4028 #define FSMC_BWTR4_ADDHLD 0x000000F0U
4029 #define FSMC_BWTR4_ADDHLD_0 0x00000010U
4030 #define FSMC_BWTR4_ADDHLD_1 0x00000020U
4031 #define FSMC_BWTR4_ADDHLD_2 0x00000040U
4032 #define FSMC_BWTR4_ADDHLD_3 0x00000080U
4034 #define FSMC_BWTR4_DATAST 0x0000FF00U
4035 #define FSMC_BWTR4_DATAST_0 0x00000100U
4036 #define FSMC_BWTR4_DATAST_1 0x00000200U
4037 #define FSMC_BWTR4_DATAST_2 0x00000400U
4038 #define FSMC_BWTR4_DATAST_3 0x00000800U
4039 #define FSMC_BWTR4_DATAST_4 0x00001000U
4040 #define FSMC_BWTR4_DATAST_5 0x00002000U
4041 #define FSMC_BWTR4_DATAST_6 0x00004000U
4042 #define FSMC_BWTR4_DATAST_7 0x00008000U
4044 #define FSMC_BWTR4_BUSTURN 0x000F0000U
4045 #define FSMC_BWTR4_BUSTURN_0 0x00010000U
4046 #define FSMC_BWTR4_BUSTURN_1 0x00020000U
4047 #define FSMC_BWTR4_BUSTURN_2 0x00040000U
4048 #define FSMC_BWTR4_BUSTURN_3 0x00080000U
4050 #define FSMC_BWTR4_ACCMOD 0x30000000U
4051 #define FSMC_BWTR4_ACCMOD_0 0x10000000U
4052 #define FSMC_BWTR4_ACCMOD_1 0x20000000U
4054 /****************** Bit definition for FSMC_PCR2 register *******************/
4055 #define FSMC_PCR2_PWAITEN 0x00000002U
4056 #define FSMC_PCR2_PBKEN 0x00000004U
4057 #define FSMC_PCR2_PTYP 0x00000008U
4059 #define FSMC_PCR2_PWID 0x00000030U
4060 #define FSMC_PCR2_PWID_0 0x00000010U
4061 #define FSMC_PCR2_PWID_1 0x00000020U
4063 #define FSMC_PCR2_ECCEN 0x00000040U
4065 #define FSMC_PCR2_TCLR 0x00001E00U
4066 #define FSMC_PCR2_TCLR_0 0x00000200U
4067 #define FSMC_PCR2_TCLR_1 0x00000400U
4068 #define FSMC_PCR2_TCLR_2 0x00000800U
4069 #define FSMC_PCR2_TCLR_3 0x00001000U
4071 #define FSMC_PCR2_TAR 0x0001E000U
4072 #define FSMC_PCR2_TAR_0 0x00002000U
4073 #define FSMC_PCR2_TAR_1 0x00004000U
4074 #define FSMC_PCR2_TAR_2 0x00008000U
4075 #define FSMC_PCR2_TAR_3 0x00010000U
4077 #define FSMC_PCR2_ECCPS 0x000E0000U
4078 #define FSMC_PCR2_ECCPS_0 0x00020000U
4079 #define FSMC_PCR2_ECCPS_1 0x00040000U
4080 #define FSMC_PCR2_ECCPS_2 0x00080000U
4082 /****************** Bit definition for FSMC_PCR3 register *******************/
4083 #define FSMC_PCR3_PWAITEN 0x00000002U
4084 #define FSMC_PCR3_PBKEN 0x00000004U
4085 #define FSMC_PCR3_PTYP 0x00000008U
4087 #define FSMC_PCR3_PWID 0x00000030U
4088 #define FSMC_PCR3_PWID_0 0x00000010U
4089 #define FSMC_PCR3_PWID_1 0x00000020U
4091 #define FSMC_PCR3_ECCEN 0x00000040U
4093 #define FSMC_PCR3_TCLR 0x00001E00U
4094 #define FSMC_PCR3_TCLR_0 0x00000200U
4095 #define FSMC_PCR3_TCLR_1 0x00000400U
4096 #define FSMC_PCR3_TCLR_2 0x00000800U
4097 #define FSMC_PCR3_TCLR_3 0x00001000U
4099 #define FSMC_PCR3_TAR 0x0001E000U
4100 #define FSMC_PCR3_TAR_0 0x00002000U
4101 #define FSMC_PCR3_TAR_1 0x00004000U
4102 #define FSMC_PCR3_TAR_2 0x00008000U
4103 #define FSMC_PCR3_TAR_3 0x00010000U
4105 #define FSMC_PCR3_ECCPS 0x000E0000U
4106 #define FSMC_PCR3_ECCPS_0 0x00020000U
4107 #define FSMC_PCR3_ECCPS_1 0x00040000U
4108 #define FSMC_PCR3_ECCPS_2 0x00080000U
4110 /****************** Bit definition for FSMC_PCR4 register *******************/
4111 #define FSMC_PCR4_PWAITEN 0x00000002U
4112 #define FSMC_PCR4_PBKEN 0x00000004U
4113 #define FSMC_PCR4_PTYP 0x00000008U
4115 #define FSMC_PCR4_PWID 0x00000030U
4116 #define FSMC_PCR4_PWID_0 0x00000010U
4117 #define FSMC_PCR4_PWID_1 0x00000020U
4119 #define FSMC_PCR4_ECCEN 0x00000040U
4121 #define FSMC_PCR4_TCLR 0x00001E00U
4122 #define FSMC_PCR4_TCLR_0 0x00000200U
4123 #define FSMC_PCR4_TCLR_1 0x00000400U
4124 #define FSMC_PCR4_TCLR_2 0x00000800U
4125 #define FSMC_PCR4_TCLR_3 0x00001000U
4127 #define FSMC_PCR4_TAR 0x0001E000U
4128 #define FSMC_PCR4_TAR_0 0x00002000U
4129 #define FSMC_PCR4_TAR_1 0x00004000U
4130 #define FSMC_PCR4_TAR_2 0x00008000U
4131 #define FSMC_PCR4_TAR_3 0x00010000U
4133 #define FSMC_PCR4_ECCPS 0x000E0000U
4134 #define FSMC_PCR4_ECCPS_0 0x00020000U
4135 #define FSMC_PCR4_ECCPS_1 0x00040000U
4136 #define FSMC_PCR4_ECCPS_2 0x00080000U
4138 /******************* Bit definition for FSMC_SR2 register *******************/
4139 #define FSMC_SR2_IRS 0x01U
4140 #define FSMC_SR2_ILS 0x02U
4141 #define FSMC_SR2_IFS 0x04U
4142 #define FSMC_SR2_IREN 0x08U
4143 #define FSMC_SR2_ILEN 0x10U
4144 #define FSMC_SR2_IFEN 0x20U
4145 #define FSMC_SR2_FEMPT 0x40U
4147 /******************* Bit definition for FSMC_SR3 register *******************/
4148 #define FSMC_SR3_IRS 0x01U
4149 #define FSMC_SR3_ILS 0x02U
4150 #define FSMC_SR3_IFS 0x04U
4151 #define FSMC_SR3_IREN 0x08U
4152 #define FSMC_SR3_ILEN 0x10U
4153 #define FSMC_SR3_IFEN 0x20U
4154 #define FSMC_SR3_FEMPT 0x40U
4156 /******************* Bit definition for FSMC_SR4 register *******************/
4157 #define FSMC_SR4_IRS 0x01U
4158 #define FSMC_SR4_ILS 0x02U
4159 #define FSMC_SR4_IFS 0x04U
4160 #define FSMC_SR4_IREN 0x08U
4161 #define FSMC_SR4_ILEN 0x10U
4162 #define FSMC_SR4_IFEN 0x20U
4163 #define FSMC_SR4_FEMPT 0x40U
4165 /****************** Bit definition for FSMC_PMEM2 register ******************/
4166 #define FSMC_PMEM2_MEMSET2 0x000000FFU
4167 #define FSMC_PMEM2_MEMSET2_0 0x00000001U
4168 #define FSMC_PMEM2_MEMSET2_1 0x00000002U
4169 #define FSMC_PMEM2_MEMSET2_2 0x00000004U
4170 #define FSMC_PMEM2_MEMSET2_3 0x00000008U
4171 #define FSMC_PMEM2_MEMSET2_4 0x00000010U
4172 #define FSMC_PMEM2_MEMSET2_5 0x00000020U
4173 #define FSMC_PMEM2_MEMSET2_6 0x00000040U
4174 #define FSMC_PMEM2_MEMSET2_7 0x00000080U
4176 #define FSMC_PMEM2_MEMWAIT2 0x0000FF00U
4177 #define FSMC_PMEM2_MEMWAIT2_0 0x00000100U
4178 #define FSMC_PMEM2_MEMWAIT2_1 0x00000200U
4179 #define FSMC_PMEM2_MEMWAIT2_2 0x00000400U
4180 #define FSMC_PMEM2_MEMWAIT2_3 0x00000800U
4181 #define FSMC_PMEM2_MEMWAIT2_4 0x00001000U
4182 #define FSMC_PMEM2_MEMWAIT2_5 0x00002000U
4183 #define FSMC_PMEM2_MEMWAIT2_6 0x00004000U
4184 #define FSMC_PMEM2_MEMWAIT2_7 0x00008000U
4186 #define FSMC_PMEM2_MEMHOLD2 0x00FF0000U
4187 #define FSMC_PMEM2_MEMHOLD2_0 0x00010000U
4188 #define FSMC_PMEM2_MEMHOLD2_1 0x00020000U
4189 #define FSMC_PMEM2_MEMHOLD2_2 0x00040000U
4190 #define FSMC_PMEM2_MEMHOLD2_3 0x00080000U
4191 #define FSMC_PMEM2_MEMHOLD2_4 0x00100000U
4192 #define FSMC_PMEM2_MEMHOLD2_5 0x00200000U
4193 #define FSMC_PMEM2_MEMHOLD2_6 0x00400000U
4194 #define FSMC_PMEM2_MEMHOLD2_7 0x00800000U
4196 #define FSMC_PMEM2_MEMHIZ2 0xFF000000U
4197 #define FSMC_PMEM2_MEMHIZ2_0 0x01000000U
4198 #define FSMC_PMEM2_MEMHIZ2_1 0x02000000U
4199 #define FSMC_PMEM2_MEMHIZ2_2 0x04000000U
4200 #define FSMC_PMEM2_MEMHIZ2_3 0x08000000U
4201 #define FSMC_PMEM2_MEMHIZ2_4 0x10000000U
4202 #define FSMC_PMEM2_MEMHIZ2_5 0x20000000U
4203 #define FSMC_PMEM2_MEMHIZ2_6 0x40000000U
4204 #define FSMC_PMEM2_MEMHIZ2_7 0x80000000U
4206 /****************** Bit definition for FSMC_PMEM3 register ******************/
4207 #define FSMC_PMEM3_MEMSET3 0x000000FFU
4208 #define FSMC_PMEM3_MEMSET3_0 0x00000001U
4209 #define FSMC_PMEM3_MEMSET3_1 0x00000002U
4210 #define FSMC_PMEM3_MEMSET3_2 0x00000004U
4211 #define FSMC_PMEM3_MEMSET3_3 0x00000008U
4212 #define FSMC_PMEM3_MEMSET3_4 0x00000010U
4213 #define FSMC_PMEM3_MEMSET3_5 0x00000020U
4214 #define FSMC_PMEM3_MEMSET3_6 0x00000040U
4215 #define FSMC_PMEM3_MEMSET3_7 0x00000080U
4217 #define FSMC_PMEM3_MEMWAIT3 0x0000FF00U
4218 #define FSMC_PMEM3_MEMWAIT3_0 0x00000100U
4219 #define FSMC_PMEM3_MEMWAIT3_1 0x00000200U
4220 #define FSMC_PMEM3_MEMWAIT3_2 0x00000400U
4221 #define FSMC_PMEM3_MEMWAIT3_3 0x00000800U
4222 #define FSMC_PMEM3_MEMWAIT3_4 0x00001000U
4223 #define FSMC_PMEM3_MEMWAIT3_5 0x00002000U
4224 #define FSMC_PMEM3_MEMWAIT3_6 0x00004000U
4225 #define FSMC_PMEM3_MEMWAIT3_7 0x00008000U
4227 #define FSMC_PMEM3_MEMHOLD3 0x00FF0000U
4228 #define FSMC_PMEM3_MEMHOLD3_0 0x00010000U
4229 #define FSMC_PMEM3_MEMHOLD3_1 0x00020000U
4230 #define FSMC_PMEM3_MEMHOLD3_2 0x00040000U
4231 #define FSMC_PMEM3_MEMHOLD3_3 0x00080000U
4232 #define FSMC_PMEM3_MEMHOLD3_4 0x00100000U
4233 #define FSMC_PMEM3_MEMHOLD3_5 0x00200000U
4234 #define FSMC_PMEM3_MEMHOLD3_6 0x00400000U
4235 #define FSMC_PMEM3_MEMHOLD3_7 0x00800000U
4237 #define FSMC_PMEM3_MEMHIZ3 0xFF000000U
4238 #define FSMC_PMEM3_MEMHIZ3_0 0x01000000U
4239 #define FSMC_PMEM3_MEMHIZ3_1 0x02000000U
4240 #define FSMC_PMEM3_MEMHIZ3_2 0x04000000U
4241 #define FSMC_PMEM3_MEMHIZ3_3 0x08000000U
4242 #define FSMC_PMEM3_MEMHIZ3_4 0x10000000U
4243 #define FSMC_PMEM3_MEMHIZ3_5 0x20000000U
4244 #define FSMC_PMEM3_MEMHIZ3_6 0x40000000U
4245 #define FSMC_PMEM3_MEMHIZ3_7 0x80000000U
4247 /****************** Bit definition for FSMC_PMEM4 register ******************/
4248 #define FSMC_PMEM4_MEMSET4 0x000000FFU
4249 #define FSMC_PMEM4_MEMSET4_0 0x00000001U
4250 #define FSMC_PMEM4_MEMSET4_1 0x00000002U
4251 #define FSMC_PMEM4_MEMSET4_2 0x00000004U
4252 #define FSMC_PMEM4_MEMSET4_3 0x00000008U
4253 #define FSMC_PMEM4_MEMSET4_4 0x00000010U
4254 #define FSMC_PMEM4_MEMSET4_5 0x00000020U
4255 #define FSMC_PMEM4_MEMSET4_6 0x00000040U
4256 #define FSMC_PMEM4_MEMSET4_7 0x00000080U
4258 #define FSMC_PMEM4_MEMWAIT4 0x0000FF00U
4259 #define FSMC_PMEM4_MEMWAIT4_0 0x00000100U
4260 #define FSMC_PMEM4_MEMWAIT4_1 0x00000200U
4261 #define FSMC_PMEM4_MEMWAIT4_2 0x00000400U
4262 #define FSMC_PMEM4_MEMWAIT4_3 0x00000800U
4263 #define FSMC_PMEM4_MEMWAIT4_4 0x00001000U
4264 #define FSMC_PMEM4_MEMWAIT4_5 0x00002000U
4265 #define FSMC_PMEM4_MEMWAIT4_6 0x00004000U
4266 #define FSMC_PMEM4_MEMWAIT4_7 0x00008000U
4268 #define FSMC_PMEM4_MEMHOLD4 0x00FF0000U
4269 #define FSMC_PMEM4_MEMHOLD4_0 0x00010000U
4270 #define FSMC_PMEM4_MEMHOLD4_1 0x00020000U
4271 #define FSMC_PMEM4_MEMHOLD4_2 0x00040000U
4272 #define FSMC_PMEM4_MEMHOLD4_3 0x00080000U
4273 #define FSMC_PMEM4_MEMHOLD4_4 0x00100000U
4274 #define FSMC_PMEM4_MEMHOLD4_5 0x00200000U
4275 #define FSMC_PMEM4_MEMHOLD4_6 0x00400000U
4276 #define FSMC_PMEM4_MEMHOLD4_7 0x00800000U
4278 #define FSMC_PMEM4_MEMHIZ4 0xFF000000U
4279 #define FSMC_PMEM4_MEMHIZ4_0 0x01000000U
4280 #define FSMC_PMEM4_MEMHIZ4_1 0x02000000U
4281 #define FSMC_PMEM4_MEMHIZ4_2 0x04000000U
4282 #define FSMC_PMEM4_MEMHIZ4_3 0x08000000U
4283 #define FSMC_PMEM4_MEMHIZ4_4 0x10000000U
4284 #define FSMC_PMEM4_MEMHIZ4_5 0x20000000U
4285 #define FSMC_PMEM4_MEMHIZ4_6 0x40000000U
4286 #define FSMC_PMEM4_MEMHIZ4_7 0x80000000U
4288 /****************** Bit definition for FSMC_PATT2 register ******************/
4289 #define FSMC_PATT2_ATTSET2 0x000000FFU
4290 #define FSMC_PATT2_ATTSET2_0 0x00000001U
4291 #define FSMC_PATT2_ATTSET2_1 0x00000002U
4292 #define FSMC_PATT2_ATTSET2_2 0x00000004U
4293 #define FSMC_PATT2_ATTSET2_3 0x00000008U
4294 #define FSMC_PATT2_ATTSET2_4 0x00000010U
4295 #define FSMC_PATT2_ATTSET2_5 0x00000020U
4296 #define FSMC_PATT2_ATTSET2_6 0x00000040U
4297 #define FSMC_PATT2_ATTSET2_7 0x00000080U
4299 #define FSMC_PATT2_ATTWAIT2 0x0000FF00U
4300 #define FSMC_PATT2_ATTWAIT2_0 0x00000100U
4301 #define FSMC_PATT2_ATTWAIT2_1 0x00000200U
4302 #define FSMC_PATT2_ATTWAIT2_2 0x00000400U
4303 #define FSMC_PATT2_ATTWAIT2_3 0x00000800U
4304 #define FSMC_PATT2_ATTWAIT2_4 0x00001000U
4305 #define FSMC_PATT2_ATTWAIT2_5 0x00002000U
4306 #define FSMC_PATT2_ATTWAIT2_6 0x00004000U
4307 #define FSMC_PATT2_ATTWAIT2_7 0x00008000U
4309 #define FSMC_PATT2_ATTHOLD2 0x00FF0000U
4310 #define FSMC_PATT2_ATTHOLD2_0 0x00010000U
4311 #define FSMC_PATT2_ATTHOLD2_1 0x00020000U
4312 #define FSMC_PATT2_ATTHOLD2_2 0x00040000U
4313 #define FSMC_PATT2_ATTHOLD2_3 0x00080000U
4314 #define FSMC_PATT2_ATTHOLD2_4 0x00100000U
4315 #define FSMC_PATT2_ATTHOLD2_5 0x00200000U
4316 #define FSMC_PATT2_ATTHOLD2_6 0x00400000U
4317 #define FSMC_PATT2_ATTHOLD2_7 0x00800000U
4319 #define FSMC_PATT2_ATTHIZ2 0xFF000000U
4320 #define FSMC_PATT2_ATTHIZ2_0 0x01000000U
4321 #define FSMC_PATT2_ATTHIZ2_1 0x02000000U
4322 #define FSMC_PATT2_ATTHIZ2_2 0x04000000U
4323 #define FSMC_PATT2_ATTHIZ2_3 0x08000000U
4324 #define FSMC_PATT2_ATTHIZ2_4 0x10000000U
4325 #define FSMC_PATT2_ATTHIZ2_5 0x20000000U
4326 #define FSMC_PATT2_ATTHIZ2_6 0x40000000U
4327 #define FSMC_PATT2_ATTHIZ2_7 0x80000000U
4329 /****************** Bit definition for FSMC_PATT3 register ******************/
4330 #define FSMC_PATT3_ATTSET3 0x000000FFU
4331 #define FSMC_PATT3_ATTSET3_0 0x00000001U
4332 #define FSMC_PATT3_ATTSET3_1 0x00000002U
4333 #define FSMC_PATT3_ATTSET3_2 0x00000004U
4334 #define FSMC_PATT3_ATTSET3_3 0x00000008U
4335 #define FSMC_PATT3_ATTSET3_4 0x00000010U
4336 #define FSMC_PATT3_ATTSET3_5 0x00000020U
4337 #define FSMC_PATT3_ATTSET3_6 0x00000040U
4338 #define FSMC_PATT3_ATTSET3_7 0x00000080U
4340 #define FSMC_PATT3_ATTWAIT3 0x0000FF00U
4341 #define FSMC_PATT3_ATTWAIT3_0 0x00000100U
4342 #define FSMC_PATT3_ATTWAIT3_1 0x00000200U
4343 #define FSMC_PATT3_ATTWAIT3_2 0x00000400U
4344 #define FSMC_PATT3_ATTWAIT3_3 0x00000800U
4345 #define FSMC_PATT3_ATTWAIT3_4 0x00001000U
4346 #define FSMC_PATT3_ATTWAIT3_5 0x00002000U
4347 #define FSMC_PATT3_ATTWAIT3_6 0x00004000U
4348 #define FSMC_PATT3_ATTWAIT3_7 0x00008000U
4350 #define FSMC_PATT3_ATTHOLD3 0x00FF0000U
4351 #define FSMC_PATT3_ATTHOLD3_0 0x00010000U
4352 #define FSMC_PATT3_ATTHOLD3_1 0x00020000U
4353 #define FSMC_PATT3_ATTHOLD3_2 0x00040000U
4354 #define FSMC_PATT3_ATTHOLD3_3 0x00080000U
4355 #define FSMC_PATT3_ATTHOLD3_4 0x00100000U
4356 #define FSMC_PATT3_ATTHOLD3_5 0x00200000U
4357 #define FSMC_PATT3_ATTHOLD3_6 0x00400000U
4358 #define FSMC_PATT3_ATTHOLD3_7 0x00800000U
4360 #define FSMC_PATT3_ATTHIZ3 0xFF000000U
4361 #define FSMC_PATT3_ATTHIZ3_0 0x01000000U
4362 #define FSMC_PATT3_ATTHIZ3_1 0x02000000U
4363 #define FSMC_PATT3_ATTHIZ3_2 0x04000000U
4364 #define FSMC_PATT3_ATTHIZ3_3 0x08000000U
4365 #define FSMC_PATT3_ATTHIZ3_4 0x10000000U
4366 #define FSMC_PATT3_ATTHIZ3_5 0x20000000U
4367 #define FSMC_PATT3_ATTHIZ3_6 0x40000000U
4368 #define FSMC_PATT3_ATTHIZ3_7 0x80000000U
4370 /****************** Bit definition for FSMC_PATT4 register ******************/
4371 #define FSMC_PATT4_ATTSET4 0x000000FFU
4372 #define FSMC_PATT4_ATTSET4_0 0x00000001U
4373 #define FSMC_PATT4_ATTSET4_1 0x00000002U
4374 #define FSMC_PATT4_ATTSET4_2 0x00000004U
4375 #define FSMC_PATT4_ATTSET4_3 0x00000008U
4376 #define FSMC_PATT4_ATTSET4_4 0x00000010U
4377 #define FSMC_PATT4_ATTSET4_5 0x00000020U
4378 #define FSMC_PATT4_ATTSET4_6 0x00000040U
4379 #define FSMC_PATT4_ATTSET4_7 0x00000080U
4381 #define FSMC_PATT4_ATTWAIT4 0x0000FF00U
4382 #define FSMC_PATT4_ATTWAIT4_0 0x00000100U
4383 #define FSMC_PATT4_ATTWAIT4_1 0x00000200U
4384 #define FSMC_PATT4_ATTWAIT4_2 0x00000400U
4385 #define FSMC_PATT4_ATTWAIT4_3 0x00000800U
4386 #define FSMC_PATT4_ATTWAIT4_4 0x00001000U
4387 #define FSMC_PATT4_ATTWAIT4_5 0x00002000U
4388 #define FSMC_PATT4_ATTWAIT4_6 0x00004000U
4389 #define FSMC_PATT4_ATTWAIT4_7 0x00008000U
4391 #define FSMC_PATT4_ATTHOLD4 0x00FF0000U
4392 #define FSMC_PATT4_ATTHOLD4_0 0x00010000U
4393 #define FSMC_PATT4_ATTHOLD4_1 0x00020000U
4394 #define FSMC_PATT4_ATTHOLD4_2 0x00040000U
4395 #define FSMC_PATT4_ATTHOLD4_3 0x00080000U
4396 #define FSMC_PATT4_ATTHOLD4_4 0x00100000U
4397 #define FSMC_PATT4_ATTHOLD4_5 0x00200000U
4398 #define FSMC_PATT4_ATTHOLD4_6 0x00400000U
4399 #define FSMC_PATT4_ATTHOLD4_7 0x00800000U
4401 #define FSMC_PATT4_ATTHIZ4 0xFF000000U
4402 #define FSMC_PATT4_ATTHIZ4_0 0x01000000U
4403 #define FSMC_PATT4_ATTHIZ4_1 0x02000000U
4404 #define FSMC_PATT4_ATTHIZ4_2 0x04000000U
4405 #define FSMC_PATT4_ATTHIZ4_3 0x08000000U
4406 #define FSMC_PATT4_ATTHIZ4_4 0x10000000U
4407 #define FSMC_PATT4_ATTHIZ4_5 0x20000000U
4408 #define FSMC_PATT4_ATTHIZ4_6 0x40000000U
4409 #define FSMC_PATT4_ATTHIZ4_7 0x80000000U
4411 /****************** Bit definition for FSMC_PIO4 register *******************/
4412 #define FSMC_PIO4_IOSET4 0x000000FFU
4413 #define FSMC_PIO4_IOSET4_0 0x00000001U
4414 #define FSMC_PIO4_IOSET4_1 0x00000002U
4415 #define FSMC_PIO4_IOSET4_2 0x00000004U
4416 #define FSMC_PIO4_IOSET4_3 0x00000008U
4417 #define FSMC_PIO4_IOSET4_4 0x00000010U
4418 #define FSMC_PIO4_IOSET4_5 0x00000020U
4419 #define FSMC_PIO4_IOSET4_6 0x00000040U
4420 #define FSMC_PIO4_IOSET4_7 0x00000080U
4422 #define FSMC_PIO4_IOWAIT4 0x0000FF00U
4423 #define FSMC_PIO4_IOWAIT4_0 0x00000100U
4424 #define FSMC_PIO4_IOWAIT4_1 0x00000200U
4425 #define FSMC_PIO4_IOWAIT4_2 0x00000400U
4426 #define FSMC_PIO4_IOWAIT4_3 0x00000800U
4427 #define FSMC_PIO4_IOWAIT4_4 0x00001000U
4428 #define FSMC_PIO4_IOWAIT4_5 0x00002000U
4429 #define FSMC_PIO4_IOWAIT4_6 0x00004000U
4430 #define FSMC_PIO4_IOWAIT4_7 0x00008000U
4432 #define FSMC_PIO4_IOHOLD4 0x00FF0000U
4433 #define FSMC_PIO4_IOHOLD4_0 0x00010000U
4434 #define FSMC_PIO4_IOHOLD4_1 0x00020000U
4435 #define FSMC_PIO4_IOHOLD4_2 0x00040000U
4436 #define FSMC_PIO4_IOHOLD4_3 0x00080000U
4437 #define FSMC_PIO4_IOHOLD4_4 0x00100000U
4438 #define FSMC_PIO4_IOHOLD4_5 0x00200000U
4439 #define FSMC_PIO4_IOHOLD4_6 0x00400000U
4440 #define FSMC_PIO4_IOHOLD4_7 0x00800000U
4442 #define FSMC_PIO4_IOHIZ4 0xFF000000U
4443 #define FSMC_PIO4_IOHIZ4_0 0x01000000U
4444 #define FSMC_PIO4_IOHIZ4_1 0x02000000U
4445 #define FSMC_PIO4_IOHIZ4_2 0x04000000U
4446 #define FSMC_PIO4_IOHIZ4_3 0x08000000U
4447 #define FSMC_PIO4_IOHIZ4_4 0x10000000U
4448 #define FSMC_PIO4_IOHIZ4_5 0x20000000U
4449 #define FSMC_PIO4_IOHIZ4_6 0x40000000U
4450 #define FSMC_PIO4_IOHIZ4_7 0x80000000U
4452 /****************** Bit definition for FSMC_ECCR2 register ******************/
4453 #define FSMC_ECCR2_ECC2 0xFFFFFFFFU
4455 /****************** Bit definition for FSMC_ECCR3 register ******************/
4456 #define FSMC_ECCR3_ECC3 0xFFFFFFFFU
4458 /******************************************************************************/
4459 /* */
4460 /* General Purpose I/O */
4461 /* */
4462 /******************************************************************************/
4463 /****************** Bits definition for GPIO_MODER register *****************/
4464 #define GPIO_MODER_MODER0 0x00000003U
4465 #define GPIO_MODER_MODER0_0 0x00000001U
4466 #define GPIO_MODER_MODER0_1 0x00000002U
4467 
4468 #define GPIO_MODER_MODER1 0x0000000CU
4469 #define GPIO_MODER_MODER1_0 0x00000004U
4470 #define GPIO_MODER_MODER1_1 0x00000008U
4471 
4472 #define GPIO_MODER_MODER2 0x00000030U
4473 #define GPIO_MODER_MODER2_0 0x00000010U
4474 #define GPIO_MODER_MODER2_1 0x00000020U
4475 
4476 #define GPIO_MODER_MODER3 0x000000C0U
4477 #define GPIO_MODER_MODER3_0 0x00000040U
4478 #define GPIO_MODER_MODER3_1 0x00000080U
4479 
4480 #define GPIO_MODER_MODER4 0x00000300U
4481 #define GPIO_MODER_MODER4_0 0x00000100U
4482 #define GPIO_MODER_MODER4_1 0x00000200U
4483 
4484 #define GPIO_MODER_MODER5 0x00000C00U
4485 #define GPIO_MODER_MODER5_0 0x00000400U
4486 #define GPIO_MODER_MODER5_1 0x00000800U
4487 
4488 #define GPIO_MODER_MODER6 0x00003000U
4489 #define GPIO_MODER_MODER6_0 0x00001000U
4490 #define GPIO_MODER_MODER6_1 0x00002000U
4491 
4492 #define GPIO_MODER_MODER7 0x0000C000U
4493 #define GPIO_MODER_MODER7_0 0x00004000U
4494 #define GPIO_MODER_MODER7_1 0x00008000U
4495 
4496 #define GPIO_MODER_MODER8 0x00030000U
4497 #define GPIO_MODER_MODER8_0 0x00010000U
4498 #define GPIO_MODER_MODER8_1 0x00020000U
4499 
4500 #define GPIO_MODER_MODER9 0x000C0000U
4501 #define GPIO_MODER_MODER9_0 0x00040000U
4502 #define GPIO_MODER_MODER9_1 0x00080000U
4503 
4504 #define GPIO_MODER_MODER10 0x00300000U
4505 #define GPIO_MODER_MODER10_0 0x00100000U
4506 #define GPIO_MODER_MODER10_1 0x00200000U
4507 
4508 #define GPIO_MODER_MODER11 0x00C00000U
4509 #define GPIO_MODER_MODER11_0 0x00400000U
4510 #define GPIO_MODER_MODER11_1 0x00800000U
4511 
4512 #define GPIO_MODER_MODER12 0x03000000U
4513 #define GPIO_MODER_MODER12_0 0x01000000U
4514 #define GPIO_MODER_MODER12_1 0x02000000U
4515 
4516 #define GPIO_MODER_MODER13 0x0C000000U
4517 #define GPIO_MODER_MODER13_0 0x04000000U
4518 #define GPIO_MODER_MODER13_1 0x08000000U
4519 
4520 #define GPIO_MODER_MODER14 0x30000000U
4521 #define GPIO_MODER_MODER14_0 0x10000000U
4522 #define GPIO_MODER_MODER14_1 0x20000000U
4523 
4524 #define GPIO_MODER_MODER15 0xC0000000U
4525 #define GPIO_MODER_MODER15_0 0x40000000U
4526 #define GPIO_MODER_MODER15_1 0x80000000U
4527 
4528 /****************** Bits definition for GPIO_OTYPER register ****************/
4529 #define GPIO_OTYPER_OT_0 0x00000001U
4530 #define GPIO_OTYPER_OT_1 0x00000002U
4531 #define GPIO_OTYPER_OT_2 0x00000004U
4532 #define GPIO_OTYPER_OT_3 0x00000008U
4533 #define GPIO_OTYPER_OT_4 0x00000010U
4534 #define GPIO_OTYPER_OT_5 0x00000020U
4535 #define GPIO_OTYPER_OT_6 0x00000040U
4536 #define GPIO_OTYPER_OT_7 0x00000080U
4537 #define GPIO_OTYPER_OT_8 0x00000100U
4538 #define GPIO_OTYPER_OT_9 0x00000200U
4539 #define GPIO_OTYPER_OT_10 0x00000400U
4540 #define GPIO_OTYPER_OT_11 0x00000800U
4541 #define GPIO_OTYPER_OT_12 0x00001000U
4542 #define GPIO_OTYPER_OT_13 0x00002000U
4543 #define GPIO_OTYPER_OT_14 0x00004000U
4544 #define GPIO_OTYPER_OT_15 0x00008000U
4545 
4546 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4547 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4548 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4549 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4550 
4551 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4552 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4553 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4554 
4555 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4556 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4557 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4558 
4559 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4560 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4561 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4562 
4563 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4564 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4565 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4566 
4567 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4568 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4569 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4570 
4571 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4572 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4573 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4574 
4575 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4576 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4577 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4578 
4579 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4580 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4581 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4582 
4583 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4584 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4585 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4586 
4587 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4588 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4589 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4590 
4591 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4592 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4593 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4594 
4595 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4596 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4597 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4598 
4599 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4600 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4601 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4602 
4603 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4604 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4605 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4606 
4607 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4608 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4609 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4610 
4611 /****************** Bits definition for GPIO_PUPDR register *****************/
4612 #define GPIO_PUPDR_PUPDR0 0x00000003U
4613 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4614 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4615 
4616 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4617 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4618 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4619 
4620 #define GPIO_PUPDR_PUPDR2 0x00000030U
4621 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4622 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4623 
4624 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4625 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4626 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4627 
4628 #define GPIO_PUPDR_PUPDR4 0x00000300U
4629 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4630 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4631 
4632 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4633 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4634 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4635 
4636 #define GPIO_PUPDR_PUPDR6 0x00003000U
4637 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4638 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4639 
4640 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4641 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4642 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4643 
4644 #define GPIO_PUPDR_PUPDR8 0x00030000U
4645 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4646 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4647 
4648 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4649 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4650 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4651 
4652 #define GPIO_PUPDR_PUPDR10 0x00300000U
4653 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4654 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4655 
4656 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4657 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4658 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4659 
4660 #define GPIO_PUPDR_PUPDR12 0x03000000U
4661 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4662 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4663 
4664 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4665 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4666 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4667 
4668 #define GPIO_PUPDR_PUPDR14 0x30000000U
4669 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4670 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
4671 
4672 #define GPIO_PUPDR_PUPDR15 0xC0000000U
4673 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
4674 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
4675 
4676 /****************** Bits definition for GPIO_IDR register *******************/
4677 #define GPIO_IDR_IDR_0 0x00000001U
4678 #define GPIO_IDR_IDR_1 0x00000002U
4679 #define GPIO_IDR_IDR_2 0x00000004U
4680 #define GPIO_IDR_IDR_3 0x00000008U
4681 #define GPIO_IDR_IDR_4 0x00000010U
4682 #define GPIO_IDR_IDR_5 0x00000020U
4683 #define GPIO_IDR_IDR_6 0x00000040U
4684 #define GPIO_IDR_IDR_7 0x00000080U
4685 #define GPIO_IDR_IDR_8 0x00000100U
4686 #define GPIO_IDR_IDR_9 0x00000200U
4687 #define GPIO_IDR_IDR_10 0x00000400U
4688 #define GPIO_IDR_IDR_11 0x00000800U
4689 #define GPIO_IDR_IDR_12 0x00001000U
4690 #define GPIO_IDR_IDR_13 0x00002000U
4691 #define GPIO_IDR_IDR_14 0x00004000U
4692 #define GPIO_IDR_IDR_15 0x00008000U
4693 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4694 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4695 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4696 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4697 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4698 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4699 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4700 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4701 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4702 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4703 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4704 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4705 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4706 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4707 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4708 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4709 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4710 
4711 /****************** Bits definition for GPIO_ODR register *******************/
4712 #define GPIO_ODR_ODR_0 0x00000001U
4713 #define GPIO_ODR_ODR_1 0x00000002U
4714 #define GPIO_ODR_ODR_2 0x00000004U
4715 #define GPIO_ODR_ODR_3 0x00000008U
4716 #define GPIO_ODR_ODR_4 0x00000010U
4717 #define GPIO_ODR_ODR_5 0x00000020U
4718 #define GPIO_ODR_ODR_6 0x00000040U
4719 #define GPIO_ODR_ODR_7 0x00000080U
4720 #define GPIO_ODR_ODR_8 0x00000100U
4721 #define GPIO_ODR_ODR_9 0x00000200U
4722 #define GPIO_ODR_ODR_10 0x00000400U
4723 #define GPIO_ODR_ODR_11 0x00000800U
4724 #define GPIO_ODR_ODR_12 0x00001000U
4725 #define GPIO_ODR_ODR_13 0x00002000U
4726 #define GPIO_ODR_ODR_14 0x00004000U
4727 #define GPIO_ODR_ODR_15 0x00008000U
4728 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4729 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4730 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4731 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4732 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4733 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4734 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4735 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4736 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4737 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4738 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4739 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4740 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4741 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4742 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4743 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4744 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4745 
4746 /****************** Bits definition for GPIO_BSRR register ******************/
4747 #define GPIO_BSRR_BS_0 0x00000001U
4748 #define GPIO_BSRR_BS_1 0x00000002U
4749 #define GPIO_BSRR_BS_2 0x00000004U
4750 #define GPIO_BSRR_BS_3 0x00000008U
4751 #define GPIO_BSRR_BS_4 0x00000010U
4752 #define GPIO_BSRR_BS_5 0x00000020U
4753 #define GPIO_BSRR_BS_6 0x00000040U
4754 #define GPIO_BSRR_BS_7 0x00000080U
4755 #define GPIO_BSRR_BS_8 0x00000100U
4756 #define GPIO_BSRR_BS_9 0x00000200U
4757 #define GPIO_BSRR_BS_10 0x00000400U
4758 #define GPIO_BSRR_BS_11 0x00000800U
4759 #define GPIO_BSRR_BS_12 0x00001000U
4760 #define GPIO_BSRR_BS_13 0x00002000U
4761 #define GPIO_BSRR_BS_14 0x00004000U
4762 #define GPIO_BSRR_BS_15 0x00008000U
4763 #define GPIO_BSRR_BR_0 0x00010000U
4764 #define GPIO_BSRR_BR_1 0x00020000U
4765 #define GPIO_BSRR_BR_2 0x00040000U
4766 #define GPIO_BSRR_BR_3 0x00080000U
4767 #define GPIO_BSRR_BR_4 0x00100000U
4768 #define GPIO_BSRR_BR_5 0x00200000U
4769 #define GPIO_BSRR_BR_6 0x00400000U
4770 #define GPIO_BSRR_BR_7 0x00800000U
4771 #define GPIO_BSRR_BR_8 0x01000000U
4772 #define GPIO_BSRR_BR_9 0x02000000U
4773 #define GPIO_BSRR_BR_10 0x04000000U
4774 #define GPIO_BSRR_BR_11 0x08000000U
4775 #define GPIO_BSRR_BR_12 0x10000000U
4776 #define GPIO_BSRR_BR_13 0x20000000U
4777 #define GPIO_BSRR_BR_14 0x40000000U
4778 #define GPIO_BSRR_BR_15 0x80000000U
4779 
4780 /****************** Bit definition for GPIO_LCKR register *********************/
4781 #define GPIO_LCKR_LCK0 0x00000001U
4782 #define GPIO_LCKR_LCK1 0x00000002U
4783 #define GPIO_LCKR_LCK2 0x00000004U
4784 #define GPIO_LCKR_LCK3 0x00000008U
4785 #define GPIO_LCKR_LCK4 0x00000010U
4786 #define GPIO_LCKR_LCK5 0x00000020U
4787 #define GPIO_LCKR_LCK6 0x00000040U
4788 #define GPIO_LCKR_LCK7 0x00000080U
4789 #define GPIO_LCKR_LCK8 0x00000100U
4790 #define GPIO_LCKR_LCK9 0x00000200U
4791 #define GPIO_LCKR_LCK10 0x00000400U
4792 #define GPIO_LCKR_LCK11 0x00000800U
4793 #define GPIO_LCKR_LCK12 0x00001000U
4794 #define GPIO_LCKR_LCK13 0x00002000U
4795 #define GPIO_LCKR_LCK14 0x00004000U
4796 #define GPIO_LCKR_LCK15 0x00008000U
4797 #define GPIO_LCKR_LCKK 0x00010000U
4798 
4799 /******************************************************************************/
4800 /* */
4801 /* HASH */
4802 /* */
4803 /******************************************************************************/
4804 /****************** Bits definition for HASH_CR register ********************/
4805 #define HASH_CR_INIT 0x00000004U
4806 #define HASH_CR_DMAE 0x00000008U
4807 #define HASH_CR_DATATYPE 0x00000030U
4808 #define HASH_CR_DATATYPE_0 0x00000010U
4809 #define HASH_CR_DATATYPE_1 0x00000020U
4810 #define HASH_CR_MODE 0x00000040U
4811 #define HASH_CR_ALGO 0x00040080U
4812 #define HASH_CR_ALGO_0 0x00000080U
4813 #define HASH_CR_ALGO_1 0x00040000U
4814 #define HASH_CR_NBW 0x00000F00U
4815 #define HASH_CR_NBW_0 0x00000100U
4816 #define HASH_CR_NBW_1 0x00000200U
4817 #define HASH_CR_NBW_2 0x00000400U
4818 #define HASH_CR_NBW_3 0x00000800U
4819 #define HASH_CR_DINNE 0x00001000U
4820 #define HASH_CR_MDMAT 0x00002000U
4821 #define HASH_CR_LKEY 0x00010000U
4822 
4823 /****************** Bits definition for HASH_STR register *******************/
4824 #define HASH_STR_NBLW 0x0000001FU
4825 #define HASH_STR_NBLW_0 0x00000001U
4826 #define HASH_STR_NBLW_1 0x00000002U
4827 #define HASH_STR_NBLW_2 0x00000004U
4828 #define HASH_STR_NBLW_3 0x00000008U
4829 #define HASH_STR_NBLW_4 0x00000010U
4830 #define HASH_STR_DCAL 0x00000100U
4831 /* Aliases for HASH_STR register */
4832 #define HASH_STR_NBW HASH_STR_NBLW
4833 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
4834 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
4835 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
4836 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
4837 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
4838 
4839 /****************** Bits definition for HASH_IMR register *******************/
4840 #define HASH_IMR_DINIE 0x00000001U
4841 #define HASH_IMR_DCIE 0x00000002U
4842 /* Aliases for HASH_IMR register */
4843 #define HASH_IMR_DINIM HASH_IMR_DINIE
4844 #define HASH_IMR_DCIM HASH_IMR_DCIE
4845 
4846 /****************** Bits definition for HASH_SR register ********************/
4847 #define HASH_SR_DINIS 0x00000001U
4848 #define HASH_SR_DCIS 0x00000002U
4849 #define HASH_SR_DMAS 0x00000004U
4850 #define HASH_SR_BUSY 0x00000008U
4851 
4852 /******************************************************************************/
4853 /* */
4854 /* Inter-integrated Circuit Interface */
4855 /* */
4856 /******************************************************************************/
4857 /******************* Bit definition for I2C_CR1 register ********************/
4858 #define I2C_CR1_PE 0x00000001U
4859 #define I2C_CR1_SMBUS 0x00000002U
4860 #define I2C_CR1_SMBTYPE 0x00000008U
4861 #define I2C_CR1_ENARP 0x00000010U
4862 #define I2C_CR1_ENPEC 0x00000020U
4863 #define I2C_CR1_ENGC 0x00000040U
4864 #define I2C_CR1_NOSTRETCH 0x00000080U
4865 #define I2C_CR1_START 0x00000100U
4866 #define I2C_CR1_STOP 0x00000200U
4867 #define I2C_CR1_ACK 0x00000400U
4868 #define I2C_CR1_POS 0x00000800U
4869 #define I2C_CR1_PEC 0x00001000U
4870 #define I2C_CR1_ALERT 0x00002000U
4871 #define I2C_CR1_SWRST 0x00008000U
4873 /******************* Bit definition for I2C_CR2 register ********************/
4874 #define I2C_CR2_FREQ 0x0000003FU
4875 #define I2C_CR2_FREQ_0 0x00000001U
4876 #define I2C_CR2_FREQ_1 0x00000002U
4877 #define I2C_CR2_FREQ_2 0x00000004U
4878 #define I2C_CR2_FREQ_3 0x00000008U
4879 #define I2C_CR2_FREQ_4 0x00000010U
4880 #define I2C_CR2_FREQ_5 0x00000020U
4882 #define I2C_CR2_ITERREN 0x00000100U
4883 #define I2C_CR2_ITEVTEN 0x00000200U
4884 #define I2C_CR2_ITBUFEN 0x00000400U
4885 #define I2C_CR2_DMAEN 0x00000800U
4886 #define I2C_CR2_LAST 0x00001000U
4888 /******************* Bit definition for I2C_OAR1 register *******************/
4889 #define I2C_OAR1_ADD1_7 0x000000FEU
4890 #define I2C_OAR1_ADD8_9 0x00000300U
4892 #define I2C_OAR1_ADD0 0x00000001U
4893 #define I2C_OAR1_ADD1 0x00000002U
4894 #define I2C_OAR1_ADD2 0x00000004U
4895 #define I2C_OAR1_ADD3 0x00000008U
4896 #define I2C_OAR1_ADD4 0x00000010U
4897 #define I2C_OAR1_ADD5 0x00000020U
4898 #define I2C_OAR1_ADD6 0x00000040U
4899 #define I2C_OAR1_ADD7 0x00000080U
4900 #define I2C_OAR1_ADD8 0x00000100U
4901 #define I2C_OAR1_ADD9 0x00000200U
4903 #define I2C_OAR1_ADDMODE 0x00008000U
4905 /******************* Bit definition for I2C_OAR2 register *******************/
4906 #define I2C_OAR2_ENDUAL 0x00000001U
4907 #define I2C_OAR2_ADD2 0x000000FEU
4909 /******************** Bit definition for I2C_DR register ********************/
4910 #define I2C_DR_DR 0x000000FFU
4912 /******************* Bit definition for I2C_SR1 register ********************/
4913 #define I2C_SR1_SB 0x00000001U
4914 #define I2C_SR1_ADDR 0x00000002U
4915 #define I2C_SR1_BTF 0x00000004U
4916 #define I2C_SR1_ADD10 0x00000008U
4917 #define I2C_SR1_STOPF 0x00000010U
4918 #define I2C_SR1_RXNE 0x00000040U
4919 #define I2C_SR1_TXE 0x00000080U
4920 #define I2C_SR1_BERR 0x00000100U
4921 #define I2C_SR1_ARLO 0x00000200U
4922 #define I2C_SR1_AF 0x00000400U
4923 #define I2C_SR1_OVR 0x00000800U
4924 #define I2C_SR1_PECERR 0x00001000U
4925 #define I2C_SR1_TIMEOUT 0x00004000U
4926 #define I2C_SR1_SMBALERT 0x00008000U
4928 /******************* Bit definition for I2C_SR2 register ********************/
4929 #define I2C_SR2_MSL 0x00000001U
4930 #define I2C_SR2_BUSY 0x00000002U
4931 #define I2C_SR2_TRA 0x00000004U
4932 #define I2C_SR2_GENCALL 0x00000010U
4933 #define I2C_SR2_SMBDEFAULT 0x00000020U
4934 #define I2C_SR2_SMBHOST 0x00000040U
4935 #define I2C_SR2_DUALF 0x00000080U
4936 #define I2C_SR2_PEC 0x0000FF00U
4938 /******************* Bit definition for I2C_CCR register ********************/
4939 #define I2C_CCR_CCR 0x00000FFFU
4940 #define I2C_CCR_DUTY 0x00004000U
4941 #define I2C_CCR_FS 0x00008000U
4943 /****************** Bit definition for I2C_TRISE register *******************/
4944 #define I2C_TRISE_TRISE 0x0000003FU
4946 /****************** Bit definition for I2C_FLTR register *******************/
4947 #define I2C_FLTR_DNF 0x0000000FU
4948 #define I2C_FLTR_ANOFF 0x00000010U
4950 /******************************************************************************/
4951 /* */
4952 /* Independent WATCHDOG */
4953 /* */
4954 /******************************************************************************/
4955 /******************* Bit definition for IWDG_KR register ********************/
4956 #define IWDG_KR_KEY 0xFFFFU
4958 /******************* Bit definition for IWDG_PR register ********************/
4959 #define IWDG_PR_PR 0x07U
4960 #define IWDG_PR_PR_0 0x01U
4961 #define IWDG_PR_PR_1 0x02U
4962 #define IWDG_PR_PR_2 0x04U
4964 /******************* Bit definition for IWDG_RLR register *******************/
4965 #define IWDG_RLR_RL 0x0FFFU
4967 /******************* Bit definition for IWDG_SR register ********************/
4968 #define IWDG_SR_PVU 0x01U
4969 #define IWDG_SR_RVU 0x02U
4972 /******************************************************************************/
4973 /* */
4974 /* Power Control */
4975 /* */
4976 /******************************************************************************/
4977 /******************** Bit definition for PWR_CR register ********************/
4978 #define PWR_CR_LPDS 0x00000001U
4979 #define PWR_CR_PDDS 0x00000002U
4980 #define PWR_CR_CWUF 0x00000004U
4981 #define PWR_CR_CSBF 0x00000008U
4982 #define PWR_CR_PVDE 0x00000010U
4984 #define PWR_CR_PLS 0x000000E0U
4985 #define PWR_CR_PLS_0 0x00000020U
4986 #define PWR_CR_PLS_1 0x00000040U
4987 #define PWR_CR_PLS_2 0x00000080U
4990 #define PWR_CR_PLS_LEV0 0x00000000U
4991 #define PWR_CR_PLS_LEV1 0x00000020U
4992 #define PWR_CR_PLS_LEV2 0x00000040U
4993 #define PWR_CR_PLS_LEV3 0x00000060U
4994 #define PWR_CR_PLS_LEV4 0x00000080U
4995 #define PWR_CR_PLS_LEV5 0x000000A0U
4996 #define PWR_CR_PLS_LEV6 0x000000C0U
4997 #define PWR_CR_PLS_LEV7 0x000000E0U
4999 #define PWR_CR_DBP 0x00000100U
5000 #define PWR_CR_FPDS 0x00000200U
5001 #define PWR_CR_VOS 0x00004000U
5003 /* Legacy define */
5004 #define PWR_CR_PMODE PWR_CR_VOS
5005 
5006 /******************* Bit definition for PWR_CSR register ********************/
5007 #define PWR_CSR_WUF 0x00000001U
5008 #define PWR_CSR_SBF 0x00000002U
5009 #define PWR_CSR_PVDO 0x00000004U
5010 #define PWR_CSR_BRR 0x00000008U
5011 #define PWR_CSR_EWUP 0x00000100U
5012 #define PWR_CSR_BRE 0x00000200U
5013 #define PWR_CSR_VOSRDY 0x00004000U
5015 /* Legacy define */
5016 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
5017 
5018 /******************************************************************************/
5019 /* */
5020 /* Reset and Clock Control */
5021 /* */
5022 /******************************************************************************/
5023 /******************** Bit definition for RCC_CR register ********************/
5024 #define RCC_CR_HSION 0x00000001U
5025 #define RCC_CR_HSIRDY 0x00000002U
5026 
5027 #define RCC_CR_HSITRIM 0x000000F8U
5028 #define RCC_CR_HSITRIM_0 0x00000008U
5029 #define RCC_CR_HSITRIM_1 0x00000010U
5030 #define RCC_CR_HSITRIM_2 0x00000020U
5031 #define RCC_CR_HSITRIM_3 0x00000040U
5032 #define RCC_CR_HSITRIM_4 0x00000080U
5034 #define RCC_CR_HSICAL 0x0000FF00U
5035 #define RCC_CR_HSICAL_0 0x00000100U
5036 #define RCC_CR_HSICAL_1 0x00000200U
5037 #define RCC_CR_HSICAL_2 0x00000400U
5038 #define RCC_CR_HSICAL_3 0x00000800U
5039 #define RCC_CR_HSICAL_4 0x00001000U
5040 #define RCC_CR_HSICAL_5 0x00002000U
5041 #define RCC_CR_HSICAL_6 0x00004000U
5042 #define RCC_CR_HSICAL_7 0x00008000U
5044 #define RCC_CR_HSEON 0x00010000U
5045 #define RCC_CR_HSERDY 0x00020000U
5046 #define RCC_CR_HSEBYP 0x00040000U
5047 #define RCC_CR_CSSON 0x00080000U
5048 #define RCC_CR_PLLON 0x01000000U
5049 #define RCC_CR_PLLRDY 0x02000000U
5050 #define RCC_CR_PLLI2SON 0x04000000U
5051 #define RCC_CR_PLLI2SRDY 0x08000000U
5052 
5053 /******************** Bit definition for RCC_PLLCFGR register ***************/
5054 #define RCC_PLLCFGR_PLLM 0x0000003FU
5055 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5056 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5057 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5058 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5059 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5060 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5061 
5062 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5063 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5064 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5065 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5066 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5067 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5068 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5069 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5070 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5071 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5072 
5073 #define RCC_PLLCFGR_PLLP 0x00030000U
5074 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5075 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5076 
5077 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5078 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5079 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5080 
5081 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5082 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5083 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5084 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5085 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5086 
5087 /******************** Bit definition for RCC_CFGR register ******************/
5089 #define RCC_CFGR_SW 0x00000003U
5090 #define RCC_CFGR_SW_0 0x00000001U
5091 #define RCC_CFGR_SW_1 0x00000002U
5093 #define RCC_CFGR_SW_HSI 0x00000000U
5094 #define RCC_CFGR_SW_HSE 0x00000001U
5095 #define RCC_CFGR_SW_PLL 0x00000002U
5098 #define RCC_CFGR_SWS 0x0000000CU
5099 #define RCC_CFGR_SWS_0 0x00000004U
5100 #define RCC_CFGR_SWS_1 0x00000008U
5102 #define RCC_CFGR_SWS_HSI 0x00000000U
5103 #define RCC_CFGR_SWS_HSE 0x00000004U
5104 #define RCC_CFGR_SWS_PLL 0x00000008U
5107 #define RCC_CFGR_HPRE 0x000000F0U
5108 #define RCC_CFGR_HPRE_0 0x00000010U
5109 #define RCC_CFGR_HPRE_1 0x00000020U
5110 #define RCC_CFGR_HPRE_2 0x00000040U
5111 #define RCC_CFGR_HPRE_3 0x00000080U
5113 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5114 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5115 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5116 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5117 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5118 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5119 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5120 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5121 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5124 #define RCC_CFGR_PPRE1 0x00001C00U
5125 #define RCC_CFGR_PPRE1_0 0x00000400U
5126 #define RCC_CFGR_PPRE1_1 0x00000800U
5127 #define RCC_CFGR_PPRE1_2 0x00001000U
5129 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5130 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5131 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5132 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5133 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5136 #define RCC_CFGR_PPRE2 0x0000E000U
5137 #define RCC_CFGR_PPRE2_0 0x00002000U
5138 #define RCC_CFGR_PPRE2_1 0x00004000U
5139 #define RCC_CFGR_PPRE2_2 0x00008000U
5141 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5142 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5143 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5144 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5145 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5148 #define RCC_CFGR_RTCPRE 0x001F0000U
5149 #define RCC_CFGR_RTCPRE_0 0x00010000U
5150 #define RCC_CFGR_RTCPRE_1 0x00020000U
5151 #define RCC_CFGR_RTCPRE_2 0x00040000U
5152 #define RCC_CFGR_RTCPRE_3 0x00080000U
5153 #define RCC_CFGR_RTCPRE_4 0x00100000U
5154 
5156 #define RCC_CFGR_MCO1 0x00600000U
5157 #define RCC_CFGR_MCO1_0 0x00200000U
5158 #define RCC_CFGR_MCO1_1 0x00400000U
5159 
5160 #define RCC_CFGR_I2SSRC 0x00800000U
5161 
5162 #define RCC_CFGR_MCO1PRE 0x07000000U
5163 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5164 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5165 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5166 
5167 #define RCC_CFGR_MCO2PRE 0x38000000U
5168 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5169 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5170 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5171 
5172 #define RCC_CFGR_MCO2 0xC0000000U
5173 #define RCC_CFGR_MCO2_0 0x40000000U
5174 #define RCC_CFGR_MCO2_1 0x80000000U
5175 
5176 /******************** Bit definition for RCC_CIR register *******************/
5177 #define RCC_CIR_LSIRDYF 0x00000001U
5178 #define RCC_CIR_LSERDYF 0x00000002U
5179 #define RCC_CIR_HSIRDYF 0x00000004U
5180 #define RCC_CIR_HSERDYF 0x00000008U
5181 #define RCC_CIR_PLLRDYF 0x00000010U
5182 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5183 
5184 #define RCC_CIR_CSSF 0x00000080U
5185 #define RCC_CIR_LSIRDYIE 0x00000100U
5186 #define RCC_CIR_LSERDYIE 0x00000200U
5187 #define RCC_CIR_HSIRDYIE 0x00000400U
5188 #define RCC_CIR_HSERDYIE 0x00000800U
5189 #define RCC_CIR_PLLRDYIE 0x00001000U
5190 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5191 
5192 #define RCC_CIR_LSIRDYC 0x00010000U
5193 #define RCC_CIR_LSERDYC 0x00020000U
5194 #define RCC_CIR_HSIRDYC 0x00040000U
5195 #define RCC_CIR_HSERDYC 0x00080000U
5196 #define RCC_CIR_PLLRDYC 0x00100000U
5197 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5198 
5199 #define RCC_CIR_CSSC 0x00800000U
5200 
5201 /******************** Bit definition for RCC_AHB1RSTR register **************/
5202 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5203 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5204 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5205 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5206 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5207 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5208 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5209 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5210 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5211 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5212 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5213 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5214 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5215 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5216 
5217 /******************** Bit definition for RCC_AHB2RSTR register **************/
5218 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5219 #define RCC_AHB2RSTR_CRYPRST 0x00000010U
5220 #define RCC_AHB2RSTR_HASHRST 0x00000020U
5221  /* maintained for legacy purpose */
5222  #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
5223 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5224 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5225 
5226 /******************** Bit definition for RCC_AHB3RSTR register **************/
5227 
5228 #define RCC_AHB3RSTR_FSMCRST 0x00000001U
5229 
5230 /******************** Bit definition for RCC_APB1RSTR register **************/
5231 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5232 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5233 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5234 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5235 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5236 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5237 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5238 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5239 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5240 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5241 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5242 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5243 #define RCC_APB1RSTR_USART2RST 0x00020000U
5244 #define RCC_APB1RSTR_USART3RST 0x00040000U
5245 #define RCC_APB1RSTR_UART4RST 0x00080000U
5246 #define RCC_APB1RSTR_UART5RST 0x00100000U
5247 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5248 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5249 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5250 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5251 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5252 #define RCC_APB1RSTR_PWRRST 0x10000000U
5253 #define RCC_APB1RSTR_DACRST 0x20000000U
5254 
5255 /******************** Bit definition for RCC_APB2RSTR register **************/
5256 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5257 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5258 #define RCC_APB2RSTR_USART1RST 0x00000010U
5259 #define RCC_APB2RSTR_USART6RST 0x00000020U
5260 #define RCC_APB2RSTR_ADCRST 0x00000100U
5261 #define RCC_APB2RSTR_SDIORST 0x00000800U
5262 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5263 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5264 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5265 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5266 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5267 
5268 /* Old SPI1RST bit definition, maintained for legacy purpose */
5269 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5270 
5271 /******************** Bit definition for RCC_AHB1ENR register ***************/
5272 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5273 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5274 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5275 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5276 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5277 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5278 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5279 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5280 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5281 #define RCC_AHB1ENR_CRCEN 0x00001000U
5282 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5283 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
5284 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5285 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5286 
5287 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5288 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5289 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5290 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5291 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5292 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5293 
5294 /******************** Bit definition for RCC_AHB2ENR register ***************/
5295 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5296 #define RCC_AHB2ENR_CRYPEN 0x00000010U
5297 #define RCC_AHB2ENR_HASHEN 0x00000020U
5298 #define RCC_AHB2ENR_RNGEN 0x00000040U
5299 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5300 
5301 /******************** Bit definition for RCC_AHB3ENR register ***************/
5302 
5303 #define RCC_AHB3ENR_FSMCEN 0x00000001U
5304 
5305 /******************** Bit definition for RCC_APB1ENR register ***************/
5306 #define RCC_APB1ENR_TIM2EN 0x00000001U
5307 #define RCC_APB1ENR_TIM3EN 0x00000002U
5308 #define RCC_APB1ENR_TIM4EN 0x00000004U
5309 #define RCC_APB1ENR_TIM5EN 0x00000008U
5310 #define RCC_APB1ENR_TIM6EN 0x00000010U
5311 #define RCC_APB1ENR_TIM7EN 0x00000020U
5312 #define RCC_APB1ENR_TIM12EN 0x00000040U
5313 #define RCC_APB1ENR_TIM13EN 0x00000080U
5314 #define RCC_APB1ENR_TIM14EN 0x00000100U
5315 #define RCC_APB1ENR_WWDGEN 0x00000800U
5316 #define RCC_APB1ENR_SPI2EN 0x00004000U
5317 #define RCC_APB1ENR_SPI3EN 0x00008000U
5318 #define RCC_APB1ENR_USART2EN 0x00020000U
5319 #define RCC_APB1ENR_USART3EN 0x00040000U
5320 #define RCC_APB1ENR_UART4EN 0x00080000U
5321 #define RCC_APB1ENR_UART5EN 0x00100000U
5322 #define RCC_APB1ENR_I2C1EN 0x00200000U
5323 #define RCC_APB1ENR_I2C2EN 0x00400000U
5324 #define RCC_APB1ENR_I2C3EN 0x00800000U
5325 #define RCC_APB1ENR_CAN1EN 0x02000000U
5326 #define RCC_APB1ENR_CAN2EN 0x04000000U
5327 #define RCC_APB1ENR_PWREN 0x10000000U
5328 #define RCC_APB1ENR_DACEN 0x20000000U
5329 
5330 /******************** Bit definition for RCC_APB2ENR register ***************/
5331 #define RCC_APB2ENR_TIM1EN 0x00000001U
5332 #define RCC_APB2ENR_TIM8EN 0x00000002U
5333 #define RCC_APB2ENR_USART1EN 0x00000010U
5334 #define RCC_APB2ENR_USART6EN 0x00000020U
5335 #define RCC_APB2ENR_ADC1EN 0x00000100U
5336 #define RCC_APB2ENR_ADC2EN 0x00000200U
5337 #define RCC_APB2ENR_ADC3EN 0x00000400U
5338 #define RCC_APB2ENR_SDIOEN 0x00000800U
5339 #define RCC_APB2ENR_SPI1EN 0x00001000U
5340 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5341 #define RCC_APB2ENR_TIM9EN 0x00010000U
5342 #define RCC_APB2ENR_TIM10EN 0x00020000U
5343 #define RCC_APB2ENR_TIM11EN 0x00040000U
5344 #define RCC_APB2ENR_SPI5EN 0x00100000U
5345 #define RCC_APB2ENR_SPI6EN 0x00200000U
5346 
5347 /******************** Bit definition for RCC_AHB1LPENR register *************/
5348 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5349 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5350 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5351 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5352 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5353 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5354 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5355 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5356 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5357 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5358 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5359 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5360 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5361 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5362 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5363 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5364 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5365 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5366 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5367 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5368 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5369 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5370 
5371 /******************** Bit definition for RCC_AHB2LPENR register *************/
5372 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5373 #define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
5374 #define RCC_AHB2LPENR_HASHLPEN 0x00000020U
5375 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5376 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5377 
5378 /******************** Bit definition for RCC_AHB3LPENR register *************/
5379 
5380 #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
5381 
5382 /******************** Bit definition for RCC_APB1LPENR register *************/
5383 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5384 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5385 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5386 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5387 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5388 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5389 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5390 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5391 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5392 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5393 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5394 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5395 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5396 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5397 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5398 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5399 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5400 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5401 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5402 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5403 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5404 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5405 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5406 
5407 /******************** Bit definition for RCC_APB2LPENR register *************/
5408 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5409 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5410 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5411 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5412 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5413 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5414 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5415 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
5416 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5417 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5418 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5419 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5420 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5421 
5422 /******************** Bit definition for RCC_BDCR register ******************/
5423 #define RCC_BDCR_LSEON 0x00000001U
5424 #define RCC_BDCR_LSERDY 0x00000002U
5425 #define RCC_BDCR_LSEBYP 0x00000004U
5426 
5427 #define RCC_BDCR_RTCSEL 0x00000300U
5428 #define RCC_BDCR_RTCSEL_0 0x00000100U
5429 #define RCC_BDCR_RTCSEL_1 0x00000200U
5430 
5431 #define RCC_BDCR_RTCEN 0x00008000U
5432 #define RCC_BDCR_BDRST 0x00010000U
5433 
5434 /******************** Bit definition for RCC_CSR register *******************/
5435 #define RCC_CSR_LSION 0x00000001U
5436 #define RCC_CSR_LSIRDY 0x00000002U
5437 #define RCC_CSR_RMVF 0x01000000U
5438 #define RCC_CSR_BORRSTF 0x02000000U
5439 #define RCC_CSR_PADRSTF 0x04000000U
5440 #define RCC_CSR_PORRSTF 0x08000000U
5441 #define RCC_CSR_SFTRSTF 0x10000000U
5442 #define RCC_CSR_WDGRSTF 0x20000000U
5443 #define RCC_CSR_WWDGRSTF 0x40000000U
5444 #define RCC_CSR_LPWRRSTF 0x80000000U
5445 
5446 /******************** Bit definition for RCC_SSCGR register *****************/
5447 #define RCC_SSCGR_MODPER 0x00001FFFU
5448 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5449 #define RCC_SSCGR_SPREADSEL 0x40000000U
5450 #define RCC_SSCGR_SSCGEN 0x80000000U
5451 
5452 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5453 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5454 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5455 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5456 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5457 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5458 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5459 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5460 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5461 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5462 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5463 
5464 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5465 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5466 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5467 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5468 
5469 /******************************************************************************/
5470 /* */
5471 /* RNG */
5472 /* */
5473 /******************************************************************************/
5474 /******************** Bits definition for RNG_CR register *******************/
5475 #define RNG_CR_RNGEN 0x00000004U
5476 #define RNG_CR_IE 0x00000008U
5477 
5478 /******************** Bits definition for RNG_SR register *******************/
5479 #define RNG_SR_DRDY 0x00000001U
5480 #define RNG_SR_CECS 0x00000002U
5481 #define RNG_SR_SECS 0x00000004U
5482 #define RNG_SR_CEIS 0x00000020U
5483 #define RNG_SR_SEIS 0x00000040U
5484 
5485 /******************************************************************************/
5486 /* */
5487 /* Real-Time Clock (RTC) */
5488 /* */
5489 /******************************************************************************/
5490 /******************** Bits definition for RTC_TR register *******************/
5491 #define RTC_TR_PM 0x00400000U
5492 #define RTC_TR_HT 0x00300000U
5493 #define RTC_TR_HT_0 0x00100000U
5494 #define RTC_TR_HT_1 0x00200000U
5495 #define RTC_TR_HU 0x000F0000U
5496 #define RTC_TR_HU_0 0x00010000U
5497 #define RTC_TR_HU_1 0x00020000U
5498 #define RTC_TR_HU_2 0x00040000U
5499 #define RTC_TR_HU_3 0x00080000U
5500 #define RTC_TR_MNT 0x00007000U
5501 #define RTC_TR_MNT_0 0x00001000U
5502 #define RTC_TR_MNT_1 0x00002000U
5503 #define RTC_TR_MNT_2 0x00004000U
5504 #define RTC_TR_MNU 0x00000F00U
5505 #define RTC_TR_MNU_0 0x00000100U
5506 #define RTC_TR_MNU_1 0x00000200U
5507 #define RTC_TR_MNU_2 0x00000400U
5508 #define RTC_TR_MNU_3 0x00000800U
5509 #define RTC_TR_ST 0x00000070U
5510 #define RTC_TR_ST_0 0x00000010U
5511 #define RTC_TR_ST_1 0x00000020U
5512 #define RTC_TR_ST_2 0x00000040U
5513 #define RTC_TR_SU 0x0000000FU
5514 #define RTC_TR_SU_0 0x00000001U
5515 #define RTC_TR_SU_1 0x00000002U
5516 #define RTC_TR_SU_2 0x00000004U
5517 #define RTC_TR_SU_3 0x00000008U
5518 
5519 /******************** Bits definition for RTC_DR register *******************/
5520 #define RTC_DR_YT 0x00F00000U
5521 #define RTC_DR_YT_0 0x00100000U
5522 #define RTC_DR_YT_1 0x00200000U
5523 #define RTC_DR_YT_2 0x00400000U
5524 #define RTC_DR_YT_3 0x00800000U
5525 #define RTC_DR_YU 0x000F0000U
5526 #define RTC_DR_YU_0 0x00010000U
5527 #define RTC_DR_YU_1 0x00020000U
5528 #define RTC_DR_YU_2 0x00040000U
5529 #define RTC_DR_YU_3 0x00080000U
5530 #define RTC_DR_WDU 0x0000E000U
5531 #define RTC_DR_WDU_0 0x00002000U
5532 #define RTC_DR_WDU_1 0x00004000U
5533 #define RTC_DR_WDU_2 0x00008000U
5534 #define RTC_DR_MT 0x00001000U
5535 #define RTC_DR_MU 0x00000F00U
5536 #define RTC_DR_MU_0 0x00000100U
5537 #define RTC_DR_MU_1 0x00000200U
5538 #define RTC_DR_MU_2 0x00000400U
5539 #define RTC_DR_MU_3 0x00000800U
5540 #define RTC_DR_DT 0x00000030U
5541 #define RTC_DR_DT_0 0x00000010U
5542 #define RTC_DR_DT_1 0x00000020U
5543 #define RTC_DR_DU 0x0000000FU
5544 #define RTC_DR_DU_0 0x00000001U
5545 #define RTC_DR_DU_1 0x00000002U
5546 #define RTC_DR_DU_2 0x00000004U
5547 #define RTC_DR_DU_3 0x00000008U
5548 
5549 /******************** Bits definition for RTC_CR register *******************/
5550 #define RTC_CR_COE 0x00800000U
5551 #define RTC_CR_OSEL 0x00600000U
5552 #define RTC_CR_OSEL_0 0x00200000U
5553 #define RTC_CR_OSEL_1 0x00400000U
5554 #define RTC_CR_POL 0x00100000U
5555 #define RTC_CR_COSEL 0x00080000U
5556 #define RTC_CR_BCK 0x00040000U
5557 #define RTC_CR_SUB1H 0x00020000U
5558 #define RTC_CR_ADD1H 0x00010000U
5559 #define RTC_CR_TSIE 0x00008000U
5560 #define RTC_CR_WUTIE 0x00004000U
5561 #define RTC_CR_ALRBIE 0x00002000U
5562 #define RTC_CR_ALRAIE 0x00001000U
5563 #define RTC_CR_TSE 0x00000800U
5564 #define RTC_CR_WUTE 0x00000400U
5565 #define RTC_CR_ALRBE 0x00000200U
5566 #define RTC_CR_ALRAE 0x00000100U
5567 #define RTC_CR_DCE 0x00000080U
5568 #define RTC_CR_FMT 0x00000040U
5569 #define RTC_CR_BYPSHAD 0x00000020U
5570 #define RTC_CR_REFCKON 0x00000010U
5571 #define RTC_CR_TSEDGE 0x00000008U
5572 #define RTC_CR_WUCKSEL 0x00000007U
5573 #define RTC_CR_WUCKSEL_0 0x00000001U
5574 #define RTC_CR_WUCKSEL_1 0x00000002U
5575 #define RTC_CR_WUCKSEL_2 0x00000004U
5576 
5577 /******************** Bits definition for RTC_ISR register ******************/
5578 #define RTC_ISR_RECALPF 0x00010000U
5579 #define RTC_ISR_TAMP1F 0x00002000U
5580 #define RTC_ISR_TAMP2F 0x00004000U
5581 #define RTC_ISR_TSOVF 0x00001000U
5582 #define RTC_ISR_TSF 0x00000800U
5583 #define RTC_ISR_WUTF 0x00000400U
5584 #define RTC_ISR_ALRBF 0x00000200U
5585 #define RTC_ISR_ALRAF 0x00000100U
5586 #define RTC_ISR_INIT 0x00000080U
5587 #define RTC_ISR_INITF 0x00000040U
5588 #define RTC_ISR_RSF 0x00000020U
5589 #define RTC_ISR_INITS 0x00000010U
5590 #define RTC_ISR_SHPF 0x00000008U
5591 #define RTC_ISR_WUTWF 0x00000004U
5592 #define RTC_ISR_ALRBWF 0x00000002U
5593 #define RTC_ISR_ALRAWF 0x00000001U
5594 
5595 /******************** Bits definition for RTC_PRER register *****************/
5596 #define RTC_PRER_PREDIV_A 0x007F0000U
5597 #define RTC_PRER_PREDIV_S 0x00007FFFU
5598 
5599 /******************** Bits definition for RTC_WUTR register *****************/
5600 #define RTC_WUTR_WUT 0x0000FFFFU
5601 
5602 /******************** Bits definition for RTC_CALIBR register ***************/
5603 #define RTC_CALIBR_DCS 0x00000080U
5604 #define RTC_CALIBR_DC 0x0000001FU
5605 
5606 /******************** Bits definition for RTC_ALRMAR register ***************/
5607 #define RTC_ALRMAR_MSK4 0x80000000U
5608 #define RTC_ALRMAR_WDSEL 0x40000000U
5609 #define RTC_ALRMAR_DT 0x30000000U
5610 #define RTC_ALRMAR_DT_0 0x10000000U
5611 #define RTC_ALRMAR_DT_1 0x20000000U
5612 #define RTC_ALRMAR_DU 0x0F000000U
5613 #define RTC_ALRMAR_DU_0 0x01000000U
5614 #define RTC_ALRMAR_DU_1 0x02000000U
5615 #define RTC_ALRMAR_DU_2 0x04000000U
5616 #define RTC_ALRMAR_DU_3 0x08000000U
5617 #define RTC_ALRMAR_MSK3 0x00800000U
5618 #define RTC_ALRMAR_PM 0x00400000U
5619 #define RTC_ALRMAR_HT 0x00300000U
5620 #define RTC_ALRMAR_HT_0 0x00100000U
5621 #define RTC_ALRMAR_HT_1 0x00200000U
5622 #define RTC_ALRMAR_HU 0x000F0000U
5623 #define RTC_ALRMAR_HU_0 0x00010000U
5624 #define RTC_ALRMAR_HU_1 0x00020000U
5625 #define RTC_ALRMAR_HU_2 0x00040000U
5626 #define RTC_ALRMAR_HU_3 0x00080000U
5627 #define RTC_ALRMAR_MSK2 0x00008000U
5628 #define RTC_ALRMAR_MNT 0x00007000U
5629 #define RTC_ALRMAR_MNT_0 0x00001000U
5630 #define RTC_ALRMAR_MNT_1 0x00002000U
5631 #define RTC_ALRMAR_MNT_2 0x00004000U
5632 #define RTC_ALRMAR_MNU 0x00000F00U
5633 #define RTC_ALRMAR_MNU_0 0x00000100U
5634 #define RTC_ALRMAR_MNU_1 0x00000200U
5635 #define RTC_ALRMAR_MNU_2 0x00000400U
5636 #define RTC_ALRMAR_MNU_3 0x00000800U
5637 #define RTC_ALRMAR_MSK1 0x00000080U
5638 #define RTC_ALRMAR_ST 0x00000070U
5639 #define RTC_ALRMAR_ST_0 0x00000010U
5640 #define RTC_ALRMAR_ST_1 0x00000020U
5641 #define RTC_ALRMAR_ST_2 0x00000040U
5642 #define RTC_ALRMAR_SU 0x0000000FU
5643 #define RTC_ALRMAR_SU_0 0x00000001U
5644 #define RTC_ALRMAR_SU_1 0x00000002U
5645 #define RTC_ALRMAR_SU_2 0x00000004U
5646 #define RTC_ALRMAR_SU_3 0x00000008U
5647 
5648 /******************** Bits definition for RTC_ALRMBR register ***************/
5649 #define RTC_ALRMBR_MSK4 0x80000000U
5650 #define RTC_ALRMBR_WDSEL 0x40000000U
5651 #define RTC_ALRMBR_DT 0x30000000U
5652 #define RTC_ALRMBR_DT_0 0x10000000U
5653 #define RTC_ALRMBR_DT_1 0x20000000U
5654 #define RTC_ALRMBR_DU 0x0F000000U
5655 #define RTC_ALRMBR_DU_0 0x01000000U
5656 #define RTC_ALRMBR_DU_1 0x02000000U
5657 #define RTC_ALRMBR_DU_2 0x04000000U
5658 #define RTC_ALRMBR_DU_3 0x08000000U
5659 #define RTC_ALRMBR_MSK3 0x00800000U
5660 #define RTC_ALRMBR_PM 0x00400000U
5661 #define RTC_ALRMBR_HT 0x00300000U
5662 #define RTC_ALRMBR_HT_0 0x00100000U
5663 #define RTC_ALRMBR_HT_1 0x00200000U
5664 #define RTC_ALRMBR_HU 0x000F0000U
5665 #define RTC_ALRMBR_HU_0 0x00010000U
5666 #define RTC_ALRMBR_HU_1 0x00020000U
5667 #define RTC_ALRMBR_HU_2 0x00040000U
5668 #define RTC_ALRMBR_HU_3 0x00080000U
5669 #define RTC_ALRMBR_MSK2 0x00008000U
5670 #define RTC_ALRMBR_MNT 0x00007000U
5671 #define RTC_ALRMBR_MNT_0 0x00001000U
5672 #define RTC_ALRMBR_MNT_1 0x00002000U
5673 #define RTC_ALRMBR_MNT_2 0x00004000U
5674 #define RTC_ALRMBR_MNU 0x00000F00U
5675 #define RTC_ALRMBR_MNU_0 0x00000100U
5676 #define RTC_ALRMBR_MNU_1 0x00000200U
5677 #define RTC_ALRMBR_MNU_2 0x00000400U
5678 #define RTC_ALRMBR_MNU_3 0x00000800U
5679 #define RTC_ALRMBR_MSK1 0x00000080U
5680 #define RTC_ALRMBR_ST 0x00000070U
5681 #define RTC_ALRMBR_ST_0 0x00000010U
5682 #define RTC_ALRMBR_ST_1 0x00000020U
5683 #define RTC_ALRMBR_ST_2 0x00000040U
5684 #define RTC_ALRMBR_SU 0x0000000FU
5685 #define RTC_ALRMBR_SU_0 0x00000001U
5686 #define RTC_ALRMBR_SU_1 0x00000002U
5687 #define RTC_ALRMBR_SU_2 0x00000004U
5688 #define RTC_ALRMBR_SU_3 0x00000008U
5689 
5690 /******************** Bits definition for RTC_WPR register ******************/
5691 #define RTC_WPR_KEY 0x000000FFU
5692 
5693 /******************** Bits definition for RTC_SSR register ******************/
5694 #define RTC_SSR_SS 0x0000FFFFU
5695 
5696 /******************** Bits definition for RTC_SHIFTR register ***************/
5697 #define RTC_SHIFTR_SUBFS 0x00007FFFU
5698 #define RTC_SHIFTR_ADD1S 0x80000000U
5699 
5700 /******************** Bits definition for RTC_TSTR register *****************/
5701 #define RTC_TSTR_PM 0x00400000U
5702 #define RTC_TSTR_HT 0x00300000U
5703 #define RTC_TSTR_HT_0 0x00100000U
5704 #define RTC_TSTR_HT_1 0x00200000U
5705 #define RTC_TSTR_HU 0x000F0000U
5706 #define RTC_TSTR_HU_0 0x00010000U
5707 #define RTC_TSTR_HU_1 0x00020000U
5708 #define RTC_TSTR_HU_2 0x00040000U
5709 #define RTC_TSTR_HU_3 0x00080000U
5710 #define RTC_TSTR_MNT 0x00007000U
5711 #define RTC_TSTR_MNT_0 0x00001000U
5712 #define RTC_TSTR_MNT_1 0x00002000U
5713 #define RTC_TSTR_MNT_2 0x00004000U
5714 #define RTC_TSTR_MNU 0x00000F00U
5715 #define RTC_TSTR_MNU_0 0x00000100U
5716 #define RTC_TSTR_MNU_1 0x00000200U
5717 #define RTC_TSTR_MNU_2 0x00000400U
5718 #define RTC_TSTR_MNU_3 0x00000800U
5719 #define RTC_TSTR_ST 0x00000070U
5720 #define RTC_TSTR_ST_0 0x00000010U
5721 #define RTC_TSTR_ST_1 0x00000020U
5722 #define RTC_TSTR_ST_2 0x00000040U
5723 #define RTC_TSTR_SU 0x0000000FU
5724 #define RTC_TSTR_SU_0 0x00000001U
5725 #define RTC_TSTR_SU_1 0x00000002U
5726 #define RTC_TSTR_SU_2 0x00000004U
5727 #define RTC_TSTR_SU_3 0x00000008U
5728 
5729 /******************** Bits definition for RTC_TSDR register *****************/
5730 #define RTC_TSDR_WDU 0x0000E000U
5731 #define RTC_TSDR_WDU_0 0x00002000U
5732 #define RTC_TSDR_WDU_1 0x00004000U
5733 #define RTC_TSDR_WDU_2 0x00008000U
5734 #define RTC_TSDR_MT 0x00001000U
5735 #define RTC_TSDR_MU 0x00000F00U
5736 #define RTC_TSDR_MU_0 0x00000100U
5737 #define RTC_TSDR_MU_1 0x00000200U
5738 #define RTC_TSDR_MU_2 0x00000400U
5739 #define RTC_TSDR_MU_3 0x00000800U
5740 #define RTC_TSDR_DT 0x00000030U
5741 #define RTC_TSDR_DT_0 0x00000010U
5742 #define RTC_TSDR_DT_1 0x00000020U
5743 #define RTC_TSDR_DU 0x0000000FU
5744 #define RTC_TSDR_DU_0 0x00000001U
5745 #define RTC_TSDR_DU_1 0x00000002U
5746 #define RTC_TSDR_DU_2 0x00000004U
5747 #define RTC_TSDR_DU_3 0x00000008U
5748 
5749 /******************** Bits definition for RTC_TSSSR register ****************/
5750 #define RTC_TSSSR_SS 0x0000FFFFU
5751 
5752 /******************** Bits definition for RTC_CAL register *****************/
5753 #define RTC_CALR_CALP 0x00008000U
5754 #define RTC_CALR_CALW8 0x00004000U
5755 #define RTC_CALR_CALW16 0x00002000U
5756 #define RTC_CALR_CALM 0x000001FFU
5757 #define RTC_CALR_CALM_0 0x00000001U
5758 #define RTC_CALR_CALM_1 0x00000002U
5759 #define RTC_CALR_CALM_2 0x00000004U
5760 #define RTC_CALR_CALM_3 0x00000008U
5761 #define RTC_CALR_CALM_4 0x00000010U
5762 #define RTC_CALR_CALM_5 0x00000020U
5763 #define RTC_CALR_CALM_6 0x00000040U
5764 #define RTC_CALR_CALM_7 0x00000080U
5765 #define RTC_CALR_CALM_8 0x00000100U
5766 
5767 /******************** Bits definition for RTC_TAFCR register ****************/
5768 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
5769 #define RTC_TAFCR_TSINSEL 0x00020000U
5770 #define RTC_TAFCR_TAMPINSEL 0x00010000U
5771 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
5772 #define RTC_TAFCR_TAMPPRCH 0x00006000U
5773 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
5774 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
5775 #define RTC_TAFCR_TAMPFLT 0x00001800U
5776 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
5777 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
5778 #define RTC_TAFCR_TAMPFREQ 0x00000700U
5779 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
5780 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
5781 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
5782 #define RTC_TAFCR_TAMPTS 0x00000080U
5783 #define RTC_TAFCR_TAMP2TRG 0x00000010U
5784 #define RTC_TAFCR_TAMP2E 0x00000008U
5785 #define RTC_TAFCR_TAMPIE 0x00000004U
5786 #define RTC_TAFCR_TAMP1TRG 0x00000002U
5787 #define RTC_TAFCR_TAMP1E 0x00000001U
5788 
5789 /******************** Bits definition for RTC_ALRMASSR register *************/
5790 #define RTC_ALRMASSR_MASKSS 0x0F000000U
5791 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
5792 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
5793 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
5794 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
5795 #define RTC_ALRMASSR_SS 0x00007FFFU
5796 
5797 /******************** Bits definition for RTC_ALRMBSSR register *************/
5798 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
5799 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
5800 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
5801 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
5802 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
5803 #define RTC_ALRMBSSR_SS 0x00007FFFU
5804 
5805 /******************** Bits definition for RTC_BKP0R register ****************/
5806 #define RTC_BKP0R 0xFFFFFFFFU
5807 
5808 /******************** Bits definition for RTC_BKP1R register ****************/
5809 #define RTC_BKP1R 0xFFFFFFFFU
5810 
5811 /******************** Bits definition for RTC_BKP2R register ****************/
5812 #define RTC_BKP2R 0xFFFFFFFFU
5813 
5814 /******************** Bits definition for RTC_BKP3R register ****************/
5815 #define RTC_BKP3R 0xFFFFFFFFU
5816 
5817 /******************** Bits definition for RTC_BKP4R register ****************/
5818 #define RTC_BKP4R 0xFFFFFFFFU
5819 
5820 /******************** Bits definition for RTC_BKP5R register ****************/
5821 #define RTC_BKP5R 0xFFFFFFFFU
5822 
5823 /******************** Bits definition for RTC_BKP6R register ****************/
5824 #define RTC_BKP6R 0xFFFFFFFFU
5825 
5826 /******************** Bits definition for RTC_BKP7R register ****************/
5827 #define RTC_BKP7R 0xFFFFFFFFU
5828 
5829 /******************** Bits definition for RTC_BKP8R register ****************/
5830 #define RTC_BKP8R 0xFFFFFFFFU
5831 
5832 /******************** Bits definition for RTC_BKP9R register ****************/
5833 #define RTC_BKP9R 0xFFFFFFFFU
5834 
5835 /******************** Bits definition for RTC_BKP10R register ***************/
5836 #define RTC_BKP10R 0xFFFFFFFFU
5837 
5838 /******************** Bits definition for RTC_BKP11R register ***************/
5839 #define RTC_BKP11R 0xFFFFFFFFU
5840 
5841 /******************** Bits definition for RTC_BKP12R register ***************/
5842 #define RTC_BKP12R 0xFFFFFFFFU
5843 
5844 /******************** Bits definition for RTC_BKP13R register ***************/
5845 #define RTC_BKP13R 0xFFFFFFFFU
5846 
5847 /******************** Bits definition for RTC_BKP14R register ***************/
5848 #define RTC_BKP14R 0xFFFFFFFFU
5849 
5850 /******************** Bits definition for RTC_BKP15R register ***************/
5851 #define RTC_BKP15R 0xFFFFFFFFU
5852 
5853 /******************** Bits definition for RTC_BKP16R register ***************/
5854 #define RTC_BKP16R 0xFFFFFFFFU
5855 
5856 /******************** Bits definition for RTC_BKP17R register ***************/
5857 #define RTC_BKP17R 0xFFFFFFFFU
5858 
5859 /******************** Bits definition for RTC_BKP18R register ***************/
5860 #define RTC_BKP18R 0xFFFFFFFFU
5861 
5862 /******************** Bits definition for RTC_BKP19R register ***************/
5863 #define RTC_BKP19R 0xFFFFFFFFU
5864 
5865 
5866 
5867 /******************************************************************************/
5868 /* */
5869 /* SD host Interface */
5870 /* */
5871 /******************************************************************************/
5872 /****************** Bit definition for SDIO_POWER register ******************/
5873 #define SDIO_POWER_PWRCTRL 0x03U
5874 #define SDIO_POWER_PWRCTRL_0 0x01U
5875 #define SDIO_POWER_PWRCTRL_1 0x02U
5877 /****************** Bit definition for SDIO_CLKCR register ******************/
5878 #define SDIO_CLKCR_CLKDIV 0x00FFU
5879 #define SDIO_CLKCR_CLKEN 0x0100U
5880 #define SDIO_CLKCR_PWRSAV 0x0200U
5881 #define SDIO_CLKCR_BYPASS 0x0400U
5883 #define SDIO_CLKCR_WIDBUS 0x1800U
5884 #define SDIO_CLKCR_WIDBUS_0 0x0800U
5885 #define SDIO_CLKCR_WIDBUS_1 0x1000U
5887 #define SDIO_CLKCR_NEGEDGE 0x2000U
5888 #define SDIO_CLKCR_HWFC_EN 0x4000U
5890 /******************* Bit definition for SDIO_ARG register *******************/
5891 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
5893 /******************* Bit definition for SDIO_CMD register *******************/
5894 #define SDIO_CMD_CMDINDEX 0x003FU
5896 #define SDIO_CMD_WAITRESP 0x00C0U
5897 #define SDIO_CMD_WAITRESP_0 0x0040U
5898 #define SDIO_CMD_WAITRESP_1 0x0080U
5900 #define SDIO_CMD_WAITINT 0x0100U
5901 #define SDIO_CMD_WAITPEND 0x0200U
5902 #define SDIO_CMD_CPSMEN 0x0400U
5903 #define SDIO_CMD_SDIOSUSPEND 0x0800U
5904 #define SDIO_CMD_ENCMDCOMPL 0x1000U
5905 #define SDIO_CMD_NIEN 0x2000U
5906 #define SDIO_CMD_CEATACMD 0x4000U
5908 /***************** Bit definition for SDIO_RESPCMD register *****************/
5909 #define SDIO_RESPCMD_RESPCMD 0x3FU
5911 /****************** Bit definition for SDIO_RESP0 register ******************/
5912 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
5914 /****************** Bit definition for SDIO_RESP1 register ******************/
5915 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
5917 /****************** Bit definition for SDIO_RESP2 register ******************/
5918 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
5920 /****************** Bit definition for SDIO_RESP3 register ******************/
5921 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
5923 /****************** Bit definition for SDIO_RESP4 register ******************/
5924 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
5926 /****************** Bit definition for SDIO_DTIMER register *****************/
5927 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
5929 /****************** Bit definition for SDIO_DLEN register *******************/
5930 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
5932 /****************** Bit definition for SDIO_DCTRL register ******************/
5933 #define SDIO_DCTRL_DTEN 0x0001U
5934 #define SDIO_DCTRL_DTDIR 0x0002U
5935 #define SDIO_DCTRL_DTMODE 0x0004U
5936 #define SDIO_DCTRL_DMAEN 0x0008U
5938 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
5939 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
5940 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
5941 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
5942 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
5944 #define SDIO_DCTRL_RWSTART 0x0100U
5945 #define SDIO_DCTRL_RWSTOP 0x0200U
5946 #define SDIO_DCTRL_RWMOD 0x0400U
5947 #define SDIO_DCTRL_SDIOEN 0x0800U
5949 /****************** Bit definition for SDIO_DCOUNT register *****************/
5950 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
5952 /****************** Bit definition for SDIO_STA register ********************/
5953 #define SDIO_STA_CCRCFAIL 0x00000001U
5954 #define SDIO_STA_DCRCFAIL 0x00000002U
5955 #define SDIO_STA_CTIMEOUT 0x00000004U
5956 #define SDIO_STA_DTIMEOUT 0x00000008U
5957 #define SDIO_STA_TXUNDERR 0x00000010U
5958 #define SDIO_STA_RXOVERR 0x00000020U
5959 #define SDIO_STA_CMDREND 0x00000040U
5960 #define SDIO_STA_CMDSENT 0x00000080U
5961 #define SDIO_STA_DATAEND 0x00000100U
5962 #define SDIO_STA_STBITERR 0x00000200U
5963 #define SDIO_STA_DBCKEND 0x00000400U
5964 #define SDIO_STA_CMDACT 0x00000800U
5965 #define SDIO_STA_TXACT 0x00001000U
5966 #define SDIO_STA_RXACT 0x00002000U
5967 #define SDIO_STA_TXFIFOHE 0x00004000U
5968 #define SDIO_STA_RXFIFOHF 0x00008000U
5969 #define SDIO_STA_TXFIFOF 0x00010000U
5970 #define SDIO_STA_RXFIFOF 0x00020000U
5971 #define SDIO_STA_TXFIFOE 0x00040000U
5972 #define SDIO_STA_RXFIFOE 0x00080000U
5973 #define SDIO_STA_TXDAVL 0x00100000U
5974 #define SDIO_STA_RXDAVL 0x00200000U
5975 #define SDIO_STA_SDIOIT 0x00400000U
5976 #define SDIO_STA_CEATAEND 0x00800000U
5978 /******************* Bit definition for SDIO_ICR register *******************/
5979 #define SDIO_ICR_CCRCFAILC 0x00000001U
5980 #define SDIO_ICR_DCRCFAILC 0x00000002U
5981 #define SDIO_ICR_CTIMEOUTC 0x00000004U
5982 #define SDIO_ICR_DTIMEOUTC 0x00000008U
5983 #define SDIO_ICR_TXUNDERRC 0x00000010U
5984 #define SDIO_ICR_RXOVERRC 0x00000020U
5985 #define SDIO_ICR_CMDRENDC 0x00000040U
5986 #define SDIO_ICR_CMDSENTC 0x00000080U
5987 #define SDIO_ICR_DATAENDC 0x00000100U
5988 #define SDIO_ICR_STBITERRC 0x00000200U
5989 #define SDIO_ICR_DBCKENDC 0x00000400U
5990 #define SDIO_ICR_SDIOITC 0x00400000U
5991 #define SDIO_ICR_CEATAENDC 0x00800000U
5993 /****************** Bit definition for SDIO_MASK register *******************/
5994 #define SDIO_MASK_CCRCFAILIE 0x00000001U
5995 #define SDIO_MASK_DCRCFAILIE 0x00000002U
5996 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
5997 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
5998 #define SDIO_MASK_TXUNDERRIE 0x00000010U
5999 #define SDIO_MASK_RXOVERRIE 0x00000020U
6000 #define SDIO_MASK_CMDRENDIE 0x00000040U
6001 #define SDIO_MASK_CMDSENTIE 0x00000080U
6002 #define SDIO_MASK_DATAENDIE 0x00000100U
6003 #define SDIO_MASK_STBITERRIE 0x00000200U
6004 #define SDIO_MASK_DBCKENDIE 0x00000400U
6005 #define SDIO_MASK_CMDACTIE 0x00000800U
6006 #define SDIO_MASK_TXACTIE 0x00001000U
6007 #define SDIO_MASK_RXACTIE 0x00002000U
6008 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
6009 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
6010 #define SDIO_MASK_TXFIFOFIE 0x00010000U
6011 #define SDIO_MASK_RXFIFOFIE 0x00020000U
6012 #define SDIO_MASK_TXFIFOEIE 0x00040000U
6013 #define SDIO_MASK_RXFIFOEIE 0x00080000U
6014 #define SDIO_MASK_TXDAVLIE 0x00100000U
6015 #define SDIO_MASK_RXDAVLIE 0x00200000U
6016 #define SDIO_MASK_SDIOITIE 0x00400000U
6017 #define SDIO_MASK_CEATAENDIE 0x00800000U
6019 /***************** Bit definition for SDIO_FIFOCNT register *****************/
6020 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6022 /****************** Bit definition for SDIO_FIFO register *******************/
6023 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
6025 /******************************************************************************/
6026 /* */
6027 /* Serial Peripheral Interface */
6028 /* */
6029 /******************************************************************************/
6030 /******************* Bit definition for SPI_CR1 register ********************/
6031 #define SPI_CR1_CPHA 0x00000001U
6032 #define SPI_CR1_CPOL 0x00000002U
6033 #define SPI_CR1_MSTR 0x00000004U
6035 #define SPI_CR1_BR 0x00000038U
6036 #define SPI_CR1_BR_0 0x00000008U
6037 #define SPI_CR1_BR_1 0x00000010U
6038 #define SPI_CR1_BR_2 0x00000020U
6040 #define SPI_CR1_SPE 0x00000040U
6041 #define SPI_CR1_LSBFIRST 0x00000080U
6042 #define SPI_CR1_SSI 0x00000100U
6043 #define SPI_CR1_SSM 0x00000200U
6044 #define SPI_CR1_RXONLY 0x00000400U
6045 #define SPI_CR1_DFF 0x00000800U
6046 #define SPI_CR1_CRCNEXT 0x00001000U
6047 #define SPI_CR1_CRCEN 0x00002000U
6048 #define SPI_CR1_BIDIOE 0x00004000U
6049 #define SPI_CR1_BIDIMODE 0x00008000U
6051 /******************* Bit definition for SPI_CR2 register ********************/
6052 #define SPI_CR2_RXDMAEN 0x00000001U
6053 #define SPI_CR2_TXDMAEN 0x00000002U
6054 #define SPI_CR2_SSOE 0x00000004U
6055 #define SPI_CR2_FRF 0x00000010U
6056 #define SPI_CR2_ERRIE 0x00000020U
6057 #define SPI_CR2_RXNEIE 0x00000040U
6058 #define SPI_CR2_TXEIE 0x00000080U
6060 /******************** Bit definition for SPI_SR register ********************/
6061 #define SPI_SR_RXNE 0x00000001U
6062 #define SPI_SR_TXE 0x00000002U
6063 #define SPI_SR_CHSIDE 0x00000004U
6064 #define SPI_SR_UDR 0x00000008U
6065 #define SPI_SR_CRCERR 0x00000010U
6066 #define SPI_SR_MODF 0x00000020U
6067 #define SPI_SR_OVR 0x00000040U
6068 #define SPI_SR_BSY 0x00000080U
6069 #define SPI_SR_FRE 0x00000100U
6071 /******************** Bit definition for SPI_DR register ********************/
6072 #define SPI_DR_DR 0x0000FFFFU
6074 /******************* Bit definition for SPI_CRCPR register ******************/
6075 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
6077 /****************** Bit definition for SPI_RXCRCR register ******************/
6078 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
6080 /****************** Bit definition for SPI_TXCRCR register ******************/
6081 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
6083 /****************** Bit definition for SPI_I2SCFGR register *****************/
6084 #define SPI_I2SCFGR_CHLEN 0x00000001U
6086 #define SPI_I2SCFGR_DATLEN 0x00000006U
6087 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
6088 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
6090 #define SPI_I2SCFGR_CKPOL 0x00000008U
6092 #define SPI_I2SCFGR_I2SSTD 0x00000030U
6093 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
6094 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
6096 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
6098 #define SPI_I2SCFGR_I2SCFG 0x00000300U
6099 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
6100 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
6102 #define SPI_I2SCFGR_I2SE 0x00000400U
6103 #define SPI_I2SCFGR_I2SMOD 0x00000800U
6105 /****************** Bit definition for SPI_I2SPR register *******************/
6106 #define SPI_I2SPR_I2SDIV 0x000000FFU
6107 #define SPI_I2SPR_ODD 0x00000100U
6108 #define SPI_I2SPR_MCKOE 0x00000200U
6110 /******************************************************************************/
6111 /* */
6112 /* SYSCFG */
6113 /* */
6114 /******************************************************************************/
6115 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6116 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
6117 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
6118 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
6119 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
6120 
6121 /****************** Bit definition for SYSCFG_PMC register ******************/
6122 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
6124 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6125 #define SYSCFG_EXTICR1_EXTI0 0x000FU
6126 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
6127 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
6128 #define SYSCFG_EXTICR1_EXTI3 0xF000U
6132 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
6133 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
6134 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
6135 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
6136 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
6137 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
6138 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
6139 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
6140 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
6145 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
6146 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
6147 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
6148 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
6149 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
6150 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
6151 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
6152 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
6153 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
6158 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
6159 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
6160 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
6161 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
6162 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
6163 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
6164 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
6165 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
6166 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
6171 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
6172 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
6173 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
6174 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
6175 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
6176 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
6177 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
6178 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
6179 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
6181 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6182 #define SYSCFG_EXTICR2_EXTI4 0x000FU
6183 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
6184 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
6185 #define SYSCFG_EXTICR2_EXTI7 0xF000U
6189 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
6190 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
6191 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
6192 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
6193 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
6194 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
6195 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
6196 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
6197 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
6202 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
6203 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
6204 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
6205 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
6206 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
6207 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
6208 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
6209 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
6210 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
6215 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
6216 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
6217 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
6218 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
6219 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
6220 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
6221 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
6222 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
6223 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
6228 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
6229 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
6230 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
6231 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
6232 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
6233 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
6234 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
6235 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
6236 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
6239 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6240 #define SYSCFG_EXTICR3_EXTI8 0x000FU
6241 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
6242 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
6243 #define SYSCFG_EXTICR3_EXTI11 0xF000U
6248 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
6249 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
6250 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
6251 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
6252 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
6253 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
6254 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
6255 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
6256 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
6261 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
6262 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
6263 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
6264 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
6265 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
6266 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
6267 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
6268 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
6269 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
6274 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
6275 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
6276 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
6277 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
6278 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
6279 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
6280 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
6281 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
6282 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
6287 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
6288 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
6289 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
6290 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
6291 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
6292 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
6293 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
6294 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
6295 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
6297 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6298 #define SYSCFG_EXTICR4_EXTI12 0x000FU
6299 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
6300 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
6301 #define SYSCFG_EXTICR4_EXTI15 0xF000U
6305 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
6306 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
6307 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
6308 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
6309 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
6310 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
6311 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
6312 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
6317 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
6318 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
6319 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
6320 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
6321 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
6322 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
6323 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
6324 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
6329 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
6330 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
6331 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
6332 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
6333 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
6334 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
6335 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
6336 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
6341 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
6342 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
6343 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
6344 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
6345 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
6346 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
6347 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
6348 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
6350 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6351 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
6352 #define SYSCFG_CMPCR_READY 0x00000100U
6354 /******************************************************************************/
6355 /* */
6356 /* TIM */
6357 /* */
6358 /******************************************************************************/
6359 /******************* Bit definition for TIM_CR1 register ********************/
6360 #define TIM_CR1_CEN 0x0001U
6361 #define TIM_CR1_UDIS 0x0002U
6362 #define TIM_CR1_URS 0x0004U
6363 #define TIM_CR1_OPM 0x0008U
6364 #define TIM_CR1_DIR 0x0010U
6366 #define TIM_CR1_CMS 0x0060U
6367 #define TIM_CR1_CMS_0 0x0020U
6368 #define TIM_CR1_CMS_1 0x0040U
6370 #define TIM_CR1_ARPE 0x0080U
6372 #define TIM_CR1_CKD 0x0300U
6373 #define TIM_CR1_CKD_0 0x0100U
6374 #define TIM_CR1_CKD_1 0x0200U
6376 /******************* Bit definition for TIM_CR2 register ********************/
6377 #define TIM_CR2_CCPC 0x0001U
6378 #define TIM_CR2_CCUS 0x0004U
6379 #define TIM_CR2_CCDS 0x0008U
6381 #define TIM_CR2_MMS 0x0070U
6382 #define TIM_CR2_MMS_0 0x0010U
6383 #define TIM_CR2_MMS_1 0x0020U
6384 #define TIM_CR2_MMS_2 0x0040U
6386 #define TIM_CR2_TI1S 0x0080U
6387 #define TIM_CR2_OIS1 0x0100U
6388 #define TIM_CR2_OIS1N 0x0200U
6389 #define TIM_CR2_OIS2 0x0400U
6390 #define TIM_CR2_OIS2N 0x0800U
6391 #define TIM_CR2_OIS3 0x1000U
6392 #define TIM_CR2_OIS3N 0x2000U
6393 #define TIM_CR2_OIS4 0x4000U
6395 /******************* Bit definition for TIM_SMCR register *******************/
6396 #define TIM_SMCR_SMS 0x0007U
6397 #define TIM_SMCR_SMS_0 0x0001U
6398 #define TIM_SMCR_SMS_1 0x0002U
6399 #define TIM_SMCR_SMS_2 0x0004U
6401 #define TIM_SMCR_TS 0x0070U
6402 #define TIM_SMCR_TS_0 0x0010U
6403 #define TIM_SMCR_TS_1 0x0020U
6404 #define TIM_SMCR_TS_2 0x0040U
6406 #define TIM_SMCR_MSM 0x0080U
6408 #define TIM_SMCR_ETF 0x0F00U
6409 #define TIM_SMCR_ETF_0 0x0100U
6410 #define TIM_SMCR_ETF_1 0x0200U
6411 #define TIM_SMCR_ETF_2 0x0400U
6412 #define TIM_SMCR_ETF_3 0x0800U
6414 #define TIM_SMCR_ETPS 0x3000U
6415 #define TIM_SMCR_ETPS_0 0x1000U
6416 #define TIM_SMCR_ETPS_1 0x2000U
6418 #define TIM_SMCR_ECE 0x4000U
6419 #define TIM_SMCR_ETP 0x8000U
6421 /******************* Bit definition for TIM_DIER register *******************/
6422 #define TIM_DIER_UIE 0x0001U
6423 #define TIM_DIER_CC1IE 0x0002U
6424 #define TIM_DIER_CC2IE 0x0004U
6425 #define TIM_DIER_CC3IE 0x0008U
6426 #define TIM_DIER_CC4IE 0x0010U
6427 #define TIM_DIER_COMIE 0x0020U
6428 #define TIM_DIER_TIE 0x0040U
6429 #define TIM_DIER_BIE 0x0080U
6430 #define TIM_DIER_UDE 0x0100U
6431 #define TIM_DIER_CC1DE 0x0200U
6432 #define TIM_DIER_CC2DE 0x0400U
6433 #define TIM_DIER_CC3DE 0x0800U
6434 #define TIM_DIER_CC4DE 0x1000U
6435 #define TIM_DIER_COMDE 0x2000U
6436 #define TIM_DIER_TDE 0x4000U
6438 /******************** Bit definition for TIM_SR register ********************/
6439 #define TIM_SR_UIF 0x0001U
6440 #define TIM_SR_CC1IF 0x0002U
6441 #define TIM_SR_CC2IF 0x0004U
6442 #define TIM_SR_CC3IF 0x0008U
6443 #define TIM_SR_CC4IF 0x0010U
6444 #define TIM_SR_COMIF 0x0020U
6445 #define TIM_SR_TIF 0x0040U
6446 #define TIM_SR_BIF 0x0080U
6447 #define TIM_SR_CC1OF 0x0200U
6448 #define TIM_SR_CC2OF 0x0400U
6449 #define TIM_SR_CC3OF 0x0800U
6450 #define TIM_SR_CC4OF 0x1000U
6452 /******************* Bit definition for TIM_EGR register ********************/
6453 #define TIM_EGR_UG 0x01U
6454 #define TIM_EGR_CC1G 0x02U
6455 #define TIM_EGR_CC2G 0x04U
6456 #define TIM_EGR_CC3G 0x08U
6457 #define TIM_EGR_CC4G 0x10U
6458 #define TIM_EGR_COMG 0x20U
6459 #define TIM_EGR_TG 0x40U
6460 #define TIM_EGR_BG 0x80U
6462 /****************** Bit definition for TIM_CCMR1 register *******************/
6463 #define TIM_CCMR1_CC1S 0x0003U
6464 #define TIM_CCMR1_CC1S_0 0x0001U
6465 #define TIM_CCMR1_CC1S_1 0x0002U
6467 #define TIM_CCMR1_OC1FE 0x0004U
6468 #define TIM_CCMR1_OC1PE 0x0008U
6470 #define TIM_CCMR1_OC1M 0x0070U
6471 #define TIM_CCMR1_OC1M_0 0x0010U
6472 #define TIM_CCMR1_OC1M_1 0x0020U
6473 #define TIM_CCMR1_OC1M_2 0x0040U
6475 #define TIM_CCMR1_OC1CE 0x0080U
6477 #define TIM_CCMR1_CC2S 0x0300U
6478 #define TIM_CCMR1_CC2S_0 0x0100U
6479 #define TIM_CCMR1_CC2S_1 0x0200U
6481 #define TIM_CCMR1_OC2FE 0x0400U
6482 #define TIM_CCMR1_OC2PE 0x0800U
6484 #define TIM_CCMR1_OC2M 0x7000U
6485 #define TIM_CCMR1_OC2M_0 0x1000U
6486 #define TIM_CCMR1_OC2M_1 0x2000U
6487 #define TIM_CCMR1_OC2M_2 0x4000U
6489 #define TIM_CCMR1_OC2CE 0x8000U
6491 /*----------------------------------------------------------------------------*/
6492 
6493 #define TIM_CCMR1_IC1PSC 0x000CU
6494 #define TIM_CCMR1_IC1PSC_0 0x0004U
6495 #define TIM_CCMR1_IC1PSC_1 0x0008U
6497 #define TIM_CCMR1_IC1F 0x00F0U
6498 #define TIM_CCMR1_IC1F_0 0x0010U
6499 #define TIM_CCMR1_IC1F_1 0x0020U
6500 #define TIM_CCMR1_IC1F_2 0x0040U
6501 #define TIM_CCMR1_IC1F_3 0x0080U
6503 #define TIM_CCMR1_IC2PSC 0x0C00U
6504 #define TIM_CCMR1_IC2PSC_0 0x0400U
6505 #define TIM_CCMR1_IC2PSC_1 0x0800U
6507 #define TIM_CCMR1_IC2F 0xF000U
6508 #define TIM_CCMR1_IC2F_0 0x1000U
6509 #define TIM_CCMR1_IC2F_1 0x2000U
6510 #define TIM_CCMR1_IC2F_2 0x4000U
6511 #define TIM_CCMR1_IC2F_3 0x8000U
6513 /****************** Bit definition for TIM_CCMR2 register *******************/
6514 #define TIM_CCMR2_CC3S 0x0003U
6515 #define TIM_CCMR2_CC3S_0 0x0001U
6516 #define TIM_CCMR2_CC3S_1 0x0002U
6518 #define TIM_CCMR2_OC3FE 0x0004U
6519 #define TIM_CCMR2_OC3PE 0x0008U
6521 #define TIM_CCMR2_OC3M 0x0070U
6522 #define TIM_CCMR2_OC3M_0 0x0010U
6523 #define TIM_CCMR2_OC3M_1 0x0020U
6524 #define TIM_CCMR2_OC3M_2 0x0040U
6526 #define TIM_CCMR2_OC3CE 0x0080U
6528 #define TIM_CCMR2_CC4S 0x0300U
6529 #define TIM_CCMR2_CC4S_0 0x0100U
6530 #define TIM_CCMR2_CC4S_1 0x0200U
6532 #define TIM_CCMR2_OC4FE 0x0400U
6533 #define TIM_CCMR2_OC4PE 0x0800U
6535 #define TIM_CCMR2_OC4M 0x7000U
6536 #define TIM_CCMR2_OC4M_0 0x1000U
6537 #define TIM_CCMR2_OC4M_1 0x2000U
6538 #define TIM_CCMR2_OC4M_2 0x4000U
6540 #define TIM_CCMR2_OC4CE 0x8000U
6542 /*----------------------------------------------------------------------------*/
6543 
6544 #define TIM_CCMR2_IC3PSC 0x000CU
6545 #define TIM_CCMR2_IC3PSC_0 0x0004U
6546 #define TIM_CCMR2_IC3PSC_1 0x0008U
6548 #define TIM_CCMR2_IC3F 0x00F0U
6549 #define TIM_CCMR2_IC3F_0 0x0010U
6550 #define TIM_CCMR2_IC3F_1 0x0020U
6551 #define TIM_CCMR2_IC3F_2 0x0040U
6552 #define TIM_CCMR2_IC3F_3 0x0080U
6554 #define TIM_CCMR2_IC4PSC 0x0C00U
6555 #define TIM_CCMR2_IC4PSC_0 0x0400U
6556 #define TIM_CCMR2_IC4PSC_1 0x0800U
6558 #define TIM_CCMR2_IC4F 0xF000U
6559 #define TIM_CCMR2_IC4F_0 0x1000U
6560 #define TIM_CCMR2_IC4F_1 0x2000U
6561 #define TIM_CCMR2_IC4F_2 0x4000U
6562 #define TIM_CCMR2_IC4F_3 0x8000U
6564 /******************* Bit definition for TIM_CCER register *******************/
6565 #define TIM_CCER_CC1E 0x0001U
6566 #define TIM_CCER_CC1P 0x0002U
6567 #define TIM_CCER_CC1NE 0x0004U
6568 #define TIM_CCER_CC1NP 0x0008U
6569 #define TIM_CCER_CC2E 0x0010U
6570 #define TIM_CCER_CC2P 0x0020U
6571 #define TIM_CCER_CC2NE 0x0040U
6572 #define TIM_CCER_CC2NP 0x0080U
6573 #define TIM_CCER_CC3E 0x0100U
6574 #define TIM_CCER_CC3P 0x0200U
6575 #define TIM_CCER_CC3NE 0x0400U
6576 #define TIM_CCER_CC3NP 0x0800U
6577 #define TIM_CCER_CC4E 0x1000U
6578 #define TIM_CCER_CC4P 0x2000U
6579 #define TIM_CCER_CC4NP 0x8000U
6581 /******************* Bit definition for TIM_CNT register ********************/
6582 #define TIM_CNT_CNT 0xFFFFU
6584 /******************* Bit definition for TIM_PSC register ********************/
6585 #define TIM_PSC_PSC 0xFFFFU
6587 /******************* Bit definition for TIM_ARR register ********************/
6588 #define TIM_ARR_ARR 0xFFFFU
6590 /******************* Bit definition for TIM_RCR register ********************/
6591 #define TIM_RCR_REP 0xFFU
6593 /******************* Bit definition for TIM_CCR1 register *******************/
6594 #define TIM_CCR1_CCR1 0xFFFFU
6596 /******************* Bit definition for TIM_CCR2 register *******************/
6597 #define TIM_CCR2_CCR2 0xFFFFU
6599 /******************* Bit definition for TIM_CCR3 register *******************/
6600 #define TIM_CCR3_CCR3 0xFFFFU
6602 /******************* Bit definition for TIM_CCR4 register *******************/
6603 #define TIM_CCR4_CCR4 0xFFFFU
6605 /******************* Bit definition for TIM_BDTR register *******************/
6606 #define TIM_BDTR_DTG 0x00FFU
6607 #define TIM_BDTR_DTG_0 0x0001U
6608 #define TIM_BDTR_DTG_1 0x0002U
6609 #define TIM_BDTR_DTG_2 0x0004U
6610 #define TIM_BDTR_DTG_3 0x0008U
6611 #define TIM_BDTR_DTG_4 0x0010U
6612 #define TIM_BDTR_DTG_5 0x0020U
6613 #define TIM_BDTR_DTG_6 0x0040U
6614 #define TIM_BDTR_DTG_7 0x0080U
6616 #define TIM_BDTR_LOCK 0x0300U
6617 #define TIM_BDTR_LOCK_0 0x0100U
6618 #define TIM_BDTR_LOCK_1 0x0200U
6620 #define TIM_BDTR_OSSI 0x0400U
6621 #define TIM_BDTR_OSSR 0x0800U
6622 #define TIM_BDTR_BKE 0x1000U
6623 #define TIM_BDTR_BKP 0x2000U
6624 #define TIM_BDTR_AOE 0x4000U
6625 #define TIM_BDTR_MOE 0x8000U
6627 /******************* Bit definition for TIM_DCR register ********************/
6628 #define TIM_DCR_DBA 0x001FU
6629 #define TIM_DCR_DBA_0 0x0001U
6630 #define TIM_DCR_DBA_1 0x0002U
6631 #define TIM_DCR_DBA_2 0x0004U
6632 #define TIM_DCR_DBA_3 0x0008U
6633 #define TIM_DCR_DBA_4 0x0010U
6635 #define TIM_DCR_DBL 0x1F00U
6636 #define TIM_DCR_DBL_0 0x0100U
6637 #define TIM_DCR_DBL_1 0x0200U
6638 #define TIM_DCR_DBL_2 0x0400U
6639 #define TIM_DCR_DBL_3 0x0800U
6640 #define TIM_DCR_DBL_4 0x1000U
6642 /******************* Bit definition for TIM_DMAR register *******************/
6643 #define TIM_DMAR_DMAB 0xFFFFU
6645 /******************* Bit definition for TIM_OR register *********************/
6646 #define TIM_OR_TI4_RMP 0x00C0U
6647 #define TIM_OR_TI4_RMP_0 0x0040U
6648 #define TIM_OR_TI4_RMP_1 0x0080U
6649 #define TIM_OR_ITR1_RMP 0x0C00U
6650 #define TIM_OR_ITR1_RMP_0 0x0400U
6651 #define TIM_OR_ITR1_RMP_1 0x0800U
6654 /******************************************************************************/
6655 /* */
6656 /* Universal Synchronous Asynchronous Receiver Transmitter */
6657 /* */
6658 /******************************************************************************/
6659 /******************* Bit definition for USART_SR register *******************/
6660 #define USART_SR_PE 0x0001U
6661 #define USART_SR_FE 0x0002U
6662 #define USART_SR_NE 0x0004U
6663 #define USART_SR_ORE 0x0008U
6664 #define USART_SR_IDLE 0x0010U
6665 #define USART_SR_RXNE 0x0020U
6666 #define USART_SR_TC 0x0040U
6667 #define USART_SR_TXE 0x0080U
6668 #define USART_SR_LBD 0x0100U
6669 #define USART_SR_CTS 0x0200U
6671 /******************* Bit definition for USART_DR register *******************/
6672 #define USART_DR_DR 0x01FFU
6674 /****************** Bit definition for USART_BRR register *******************/
6675 #define USART_BRR_DIV_Fraction 0x000FU
6676 #define USART_BRR_DIV_Mantissa 0xFFF0U
6678 /****************** Bit definition for USART_CR1 register *******************/
6679 #define USART_CR1_SBK 0x0001U
6680 #define USART_CR1_RWU 0x0002U
6681 #define USART_CR1_RE 0x0004U
6682 #define USART_CR1_TE 0x0008U
6683 #define USART_CR1_IDLEIE 0x0010U
6684 #define USART_CR1_RXNEIE 0x0020U
6685 #define USART_CR1_TCIE 0x0040U
6686 #define USART_CR1_TXEIE 0x0080U
6687 #define USART_CR1_PEIE 0x0100U
6688 #define USART_CR1_PS 0x0200U
6689 #define USART_CR1_PCE 0x0400U
6690 #define USART_CR1_WAKE 0x0800U
6691 #define USART_CR1_M 0x1000U
6692 #define USART_CR1_UE 0x2000U
6693 #define USART_CR1_OVER8 0x8000U
6695 /****************** Bit definition for USART_CR2 register *******************/
6696 #define USART_CR2_ADD 0x000FU
6697 #define USART_CR2_LBDL 0x0020U
6698 #define USART_CR2_LBDIE 0x0040U
6699 #define USART_CR2_LBCL 0x0100U
6700 #define USART_CR2_CPHA 0x0200U
6701 #define USART_CR2_CPOL 0x0400U
6702 #define USART_CR2_CLKEN 0x0800U
6704 #define USART_CR2_STOP 0x3000U
6705 #define USART_CR2_STOP_0 0x1000U
6706 #define USART_CR2_STOP_1 0x2000U
6708 #define USART_CR2_LINEN 0x4000U
6710 /****************** Bit definition for USART_CR3 register *******************/
6711 #define USART_CR3_EIE 0x0001U
6712 #define USART_CR3_IREN 0x0002U
6713 #define USART_CR3_IRLP 0x0004U
6714 #define USART_CR3_HDSEL 0x0008U
6715 #define USART_CR3_NACK 0x0010U
6716 #define USART_CR3_SCEN 0x0020U
6717 #define USART_CR3_DMAR 0x0040U
6718 #define USART_CR3_DMAT 0x0080U
6719 #define USART_CR3_RTSE 0x0100U
6720 #define USART_CR3_CTSE 0x0200U
6721 #define USART_CR3_CTSIE 0x0400U
6722 #define USART_CR3_ONEBIT 0x0800U
6724 /****************** Bit definition for USART_GTPR register ******************/
6725 #define USART_GTPR_PSC 0x00FFU
6726 #define USART_GTPR_PSC_0 0x0001U
6727 #define USART_GTPR_PSC_1 0x0002U
6728 #define USART_GTPR_PSC_2 0x0004U
6729 #define USART_GTPR_PSC_3 0x0008U
6730 #define USART_GTPR_PSC_4 0x0010U
6731 #define USART_GTPR_PSC_5 0x0020U
6732 #define USART_GTPR_PSC_6 0x0040U
6733 #define USART_GTPR_PSC_7 0x0080U
6735 #define USART_GTPR_GT 0xFF00U
6737 /******************************************************************************/
6738 /* */
6739 /* Window WATCHDOG */
6740 /* */
6741 /******************************************************************************/
6742 /******************* Bit definition for WWDG_CR register ********************/
6743 #define WWDG_CR_T 0x7FU
6744 #define WWDG_CR_T_0 0x01U
6745 #define WWDG_CR_T_1 0x02U
6746 #define WWDG_CR_T_2 0x04U
6747 #define WWDG_CR_T_3 0x08U
6748 #define WWDG_CR_T_4 0x10U
6749 #define WWDG_CR_T_5 0x20U
6750 #define WWDG_CR_T_6 0x40U
6751 /* Legacy defines */
6752 #define WWDG_CR_T0 WWDG_CR_T_0
6753 #define WWDG_CR_T1 WWDG_CR_T_1
6754 #define WWDG_CR_T2 WWDG_CR_T_2
6755 #define WWDG_CR_T3 WWDG_CR_T_3
6756 #define WWDG_CR_T4 WWDG_CR_T_4
6757 #define WWDG_CR_T5 WWDG_CR_T_5
6758 #define WWDG_CR_T6 WWDG_CR_T_6
6759 
6760 #define WWDG_CR_WDGA 0x80U
6762 /******************* Bit definition for WWDG_CFR register *******************/
6763 #define WWDG_CFR_W 0x007FU
6764 #define WWDG_CFR_W_0 0x0001U
6765 #define WWDG_CFR_W_1 0x0002U
6766 #define WWDG_CFR_W_2 0x0004U
6767 #define WWDG_CFR_W_3 0x0008U
6768 #define WWDG_CFR_W_4 0x0010U
6769 #define WWDG_CFR_W_5 0x0020U
6770 #define WWDG_CFR_W_6 0x0040U
6771 /* Legacy defines */
6772 #define WWDG_CFR_W0 WWDG_CFR_W_0
6773 #define WWDG_CFR_W1 WWDG_CFR_W_1
6774 #define WWDG_CFR_W2 WWDG_CFR_W_2
6775 #define WWDG_CFR_W3 WWDG_CFR_W_3
6776 #define WWDG_CFR_W4 WWDG_CFR_W_4
6777 #define WWDG_CFR_W5 WWDG_CFR_W_5
6778 #define WWDG_CFR_W6 WWDG_CFR_W_6
6779 
6780 #define WWDG_CFR_WDGTB 0x0180U
6781 #define WWDG_CFR_WDGTB_0 0x0080U
6782 #define WWDG_CFR_WDGTB_1 0x0100U
6783 /* Legacy defines */
6784 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6785 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6786 
6787 #define WWDG_CFR_EWI 0x0200U
6789 /******************* Bit definition for WWDG_SR register ********************/
6790 #define WWDG_SR_EWIF 0x01U
6793 /******************************************************************************/
6794 /* */
6795 /* DBG */
6796 /* */
6797 /******************************************************************************/
6798 /******************** Bit definition for DBGMCU_IDCODE register *************/
6799 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
6800 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
6801 
6802 /******************** Bit definition for DBGMCU_CR register *****************/
6803 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
6804 #define DBGMCU_CR_DBG_STOP 0x00000002U
6805 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
6806 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
6807 
6808 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
6809 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
6810 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
6812 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6813 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
6814 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
6815 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
6816 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
6817 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
6818 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
6819 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
6820 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
6821 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
6822 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
6823 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
6824 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
6825 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
6826 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
6827 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
6828 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
6829 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
6830 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
6831 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6832 
6833 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6834 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
6835 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
6836 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
6837 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
6838 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
6839 
6840 /******************************************************************************/
6841 /* */
6842 /* Ethernet MAC Registers bits definitions */
6843 /* */
6844 /******************************************************************************/
6845 /* Bit definition for Ethernet MAC Control Register register */
6846 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
6847 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
6848 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
6849 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
6850  #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
6851  #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
6852  #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
6853  #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
6854  #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
6855  #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
6856  #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
6857 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
6858 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
6859 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
6860 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
6861 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
6862 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
6863 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
6864 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
6865 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
6866  a transmission attempt during retries after a collision: 0 =< r <2^k */
6867  #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
6868  #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
6869  #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
6870  #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
6871 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
6872 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
6873 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
6874 
6875 /* Bit definition for Ethernet MAC Frame Filter Register */
6876 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
6877 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
6878 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
6879 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
6880 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
6881  #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
6882  #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
6883  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
6884 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
6885 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
6886 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
6887 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
6888 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
6889 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
6890 
6891 /* Bit definition for Ethernet MAC Hash Table High Register */
6892 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
6893 
6894 /* Bit definition for Ethernet MAC Hash Table Low Register */
6895 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
6896 
6897 /* Bit definition for Ethernet MAC MII Address Register */
6898 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
6899 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
6900 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
6901  #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
6902  #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
6903  #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
6904  #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
6905  #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
6906 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
6907 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
6908 
6909 /* Bit definition for Ethernet MAC MII Data Register */
6910 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
6911 
6912 /* Bit definition for Ethernet MAC Flow Control Register */
6913 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
6914 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
6915 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
6916  #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
6917  #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
6918  #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
6919  #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
6920 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
6921 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
6922 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
6923 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
6924 
6925 /* Bit definition for Ethernet MAC VLAN Tag Register */
6926 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
6927 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
6928 
6929 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
6930 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
6931 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
6932  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
6933 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
6934  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
6935  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
6936  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
6937  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
6938  RSVD - Filter1 Command - RSVD - Filter0 Command
6939  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
6940  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
6941  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
6942 
6943 /* Bit definition for Ethernet MAC PMT Control and Status Register */
6944 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
6945 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
6946 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
6947 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
6948 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
6949 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
6950 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
6951 
6952 /* Bit definition for Ethernet MAC Status Register */
6953 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
6954 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
6955 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
6956 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
6957 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
6958 
6959 /* Bit definition for Ethernet MAC Interrupt Mask Register */
6960 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
6961 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
6962 
6963 /* Bit definition for Ethernet MAC Address0 High Register */
6964 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
6965 
6966 /* Bit definition for Ethernet MAC Address0 Low Register */
6967 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
6968 
6969 /* Bit definition for Ethernet MAC Address1 High Register */
6970 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
6971 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
6972 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
6973  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
6974  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
6975  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
6976  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
6977  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
6978  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
6979 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
6980 
6981 /* Bit definition for Ethernet MAC Address1 Low Register */
6982 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
6983 
6984 /* Bit definition for Ethernet MAC Address2 High Register */
6985 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
6986 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
6987 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
6988  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
6989  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
6990  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
6991  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
6992  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
6993  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
6994 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
6995 
6996 /* Bit definition for Ethernet MAC Address2 Low Register */
6997 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
6998 
6999 /* Bit definition for Ethernet MAC Address3 High Register */
7000 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
7001 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
7002 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
7003  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7004  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7005  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7006  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7007  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7008  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7009 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
7010 
7011 /* Bit definition for Ethernet MAC Address3 Low Register */
7012 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
7013 
7014 /******************************************************************************/
7015 /* Ethernet MMC Registers bits definition */
7016 /******************************************************************************/
7017 
7018 /* Bit definition for Ethernet MMC Contol Register */
7019 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
7020 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
7021 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
7022 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
7023 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
7024 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
7025 
7026 /* Bit definition for Ethernet MMC Receive Interrupt Register */
7027 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
7028 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
7029 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
7030 
7031 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
7032 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
7033 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
7034 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
7035 
7036 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
7037 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
7038 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
7039 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
7040 
7041 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
7042 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
7043 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
7044 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
7045 
7046 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
7047 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
7048 
7049 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
7050 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
7051 
7052 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
7053 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
7054 
7055 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
7056 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
7057 
7058 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
7059 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
7060 
7061 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
7062 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
7063 
7064 /******************************************************************************/
7065 /* Ethernet PTP Registers bits definition */
7066 /******************************************************************************/
7067 
7068 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
7069 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
7070 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
7071 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
7072 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
7073 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
7074 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
7075 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
7076 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
7077 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
7078 
7079 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
7080 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
7081 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
7082 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
7083 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
7084 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
7085 
7086 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
7087 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
7088 
7089 /* Bit definition for Ethernet PTP Time Stamp High Register */
7090 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
7091 
7092 /* Bit definition for Ethernet PTP Time Stamp Low Register */
7093 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
7094 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
7095 
7096 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
7097 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
7098 
7099 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7100 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
7101 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
7102 
7103 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
7104 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
7105 
7106 /* Bit definition for Ethernet PTP Target Time High Register */
7107 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
7108 
7109 /* Bit definition for Ethernet PTP Target Time Low Register */
7110 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
7111 
7112 /* Bit definition for Ethernet PTP Time Stamp Status Register */
7113 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
7114 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
7115 
7116 /******************************************************************************/
7117 /* Ethernet DMA Registers bits definition */
7118 /******************************************************************************/
7119 
7120 /* Bit definition for Ethernet DMA Bus Mode Register */
7121 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
7122 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
7123 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
7124 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
7125  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7126  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7127  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7128  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7129  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7130  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7131  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7132  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7133  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7134  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7135  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7136  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7137 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
7138 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
7139  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
7140  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
7141  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
7142  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
7143 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
7144  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7145  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7146  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7147  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7148  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7149  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7150  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7151  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7152  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7153  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7154  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7155  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7156 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
7157 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
7158 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
7159 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
7160 
7161 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7162 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
7163 
7164 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
7165 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
7166 
7167 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7168 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
7169 
7170 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7171 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
7172 
7173 /* Bit definition for Ethernet DMA Status Register */
7174 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
7175 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
7176 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
7177 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
7178  /* combination with EBS[2:0] for GetFlagStatus function */
7179  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
7180  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
7181  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
7182 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
7183  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
7184  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
7185  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
7186  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
7187  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
7188  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
7189 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
7190  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
7191  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
7192  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
7193  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
7194  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
7195  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
7196 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
7197 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
7198 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
7199 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
7200 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
7201 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
7202 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
7203 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
7204 #define ETH_DMASR_RS 0x00000040U /* Receive status */
7205 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
7206 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
7207 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
7208 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
7209 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
7210 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
7211 
7212 /* Bit definition for Ethernet DMA Operation Mode Register */
7213 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
7214 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
7215 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
7216 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
7217 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
7218 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
7219  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7220  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7221  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7222  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7223  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7224  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7225  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7226  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7227 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
7228 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
7229 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
7230 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
7231  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
7232  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
7233  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
7234  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
7235 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
7236 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
7237 
7238 /* Bit definition for Ethernet DMA Interrupt Enable Register */
7239 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
7240 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
7241 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
7242 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
7243 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
7244 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
7245 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
7246 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
7247 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
7248 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
7249 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
7250 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
7251 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
7252 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
7253 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
7254 
7255 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
7256 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
7257 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
7258 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
7259 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
7260 
7261 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
7262 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
7263 
7264 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
7265 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
7266 
7267 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
7268 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
7269 
7270 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
7271 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
7272 
7273 /******************************************************************************/
7274 /* */
7275 /* USB_OTG */
7276 /* */
7277 /******************************************************************************/
7278 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
7279 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
7280 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
7281 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
7282 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
7283 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
7284 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
7285 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
7286 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
7287 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
7288 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
7290 /******************** Bit definition forUSB_OTG_HCFG register ********************/
7291 
7292 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
7293 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
7294 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
7295 #define USB_OTG_HCFG_FSLSS 0x00000004U
7297 /******************** Bit definition forUSB_OTG_DCFG register ********************/
7298 
7299 #define USB_OTG_DCFG_DSPD 0x00000003U
7300 #define USB_OTG_DCFG_DSPD_0 0x00000001U
7301 #define USB_OTG_DCFG_DSPD_1 0x00000002U
7302 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
7304 #define USB_OTG_DCFG_DAD 0x000007F0U
7305 #define USB_OTG_DCFG_DAD_0 0x00000010U
7306 #define USB_OTG_DCFG_DAD_1 0x00000020U
7307 #define USB_OTG_DCFG_DAD_2 0x00000040U
7308 #define USB_OTG_DCFG_DAD_3 0x00000080U
7309 #define USB_OTG_DCFG_DAD_4 0x00000100U
7310 #define USB_OTG_DCFG_DAD_5 0x00000200U
7311 #define USB_OTG_DCFG_DAD_6 0x00000400U
7313 #define USB_OTG_DCFG_PFIVL 0x00001800U
7314 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
7315 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
7317 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
7318 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
7319 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
7321 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
7322 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
7323 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
7324 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
7326 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
7327 #define USB_OTG_GOTGINT_SEDET 0x00000004U
7328 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
7329 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
7330 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
7331 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
7332 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
7334 /******************** Bit definition forUSB_OTG_DCTL register ********************/
7335 #define USB_OTG_DCTL_RWUSIG 0x00000001U
7336 #define USB_OTG_DCTL_SDIS 0x00000002U
7337 #define USB_OTG_DCTL_GINSTS 0x00000004U
7338 #define USB_OTG_DCTL_GONSTS 0x00000008U
7340 #define USB_OTG_DCTL_TCTL 0x00000070U
7341 #define USB_OTG_DCTL_TCTL_0 0x00000010U
7342 #define USB_OTG_DCTL_TCTL_1 0x00000020U
7343 #define USB_OTG_DCTL_TCTL_2 0x00000040U
7344 #define USB_OTG_DCTL_SGINAK 0x00000080U
7345 #define USB_OTG_DCTL_CGINAK 0x00000100U
7346 #define USB_OTG_DCTL_SGONAK 0x00000200U
7347 #define USB_OTG_DCTL_CGONAK 0x00000400U
7348 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
7350 /******************** Bit definition forUSB_OTG_HFIR register ********************/
7351 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
7353 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
7354 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
7355 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
7357 /******************** Bit definition forUSB_OTG_DSTS register ********************/
7358 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
7360 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
7361 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
7362 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
7363 #define USB_OTG_DSTS_EERR 0x00000008U
7364 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
7366 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
7367 #define USB_OTG_GAHBCFG_GINT 0x00000001U
7369 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
7370 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
7371 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
7372 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
7373 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
7374 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
7375 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
7376 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
7378 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
7379 
7380 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
7381 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
7382 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
7383 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
7384 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
7385 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
7386 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
7388 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
7389 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
7390 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
7391 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
7392 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
7393 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
7394 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
7395 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
7396 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
7397 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
7398 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
7399 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
7400 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
7401 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
7402 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
7403 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
7404 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
7405 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
7407 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
7408 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
7409 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
7410 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
7411 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
7412 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
7414 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
7415 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
7416 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
7417 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
7418 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
7419 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
7420 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
7421 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
7423 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
7424 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
7425 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
7426 #define USB_OTG_DIEPMSK_TOM 0x00000008U
7427 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
7428 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
7429 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
7430 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
7431 #define USB_OTG_DIEPMSK_BIM 0x00000200U
7433 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
7434 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
7436 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
7437 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
7438 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
7439 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
7440 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
7441 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
7442 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
7443 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
7444 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
7446 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
7447 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
7448 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
7449 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
7450 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
7451 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
7452 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
7453 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
7454 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
7456 /******************** Bit definition forUSB_OTG_HAINT register ********************/
7457 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
7459 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
7460 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
7461 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
7462 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
7463 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
7464 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
7465 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
7466 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
7468 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
7469 #define USB_OTG_GINTSTS_CMOD 0x00000001U
7470 #define USB_OTG_GINTSTS_MMIS 0x00000002U
7471 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
7472 #define USB_OTG_GINTSTS_SOF 0x00000008U
7473 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
7474 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
7475 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
7476 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
7477 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
7478 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
7479 #define USB_OTG_GINTSTS_USBRST 0x00001000U
7480 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
7481 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
7482 #define USB_OTG_GINTSTS_EOPF 0x00008000U
7483 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
7484 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
7485 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
7486 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
7487 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
7488 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
7489 #define USB_OTG_GINTSTS_HCINT 0x02000000U
7490 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
7491 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
7492 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
7493 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
7494 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
7496 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
7497 #define USB_OTG_GINTMSK_MMISM 0x00000002U
7498 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
7499 #define USB_OTG_GINTMSK_SOFM 0x00000008U
7500 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
7501 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
7502 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
7503 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
7504 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
7505 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
7506 #define USB_OTG_GINTMSK_USBRST 0x00001000U
7507 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
7508 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
7509 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
7510 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
7511 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
7512 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
7513 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
7514 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
7515 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
7516 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
7517 #define USB_OTG_GINTMSK_HCIM 0x02000000U
7518 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
7519 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
7520 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
7521 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
7522 #define USB_OTG_GINTMSK_WUIM 0x80000000U
7524 /******************** Bit definition forUSB_OTG_DAINT register ********************/
7525 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
7526 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
7528 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
7529 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
7531 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
7532 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
7533 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
7534 #define USB_OTG_GRXSTSP_DPID 0x00018000U
7535 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
7537 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
7538 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
7539 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
7541 /******************** Bit definition for OTG register ********************/
7542 
7543 #define USB_OTG_CHNUM 0x0000000FU
7544 #define USB_OTG_CHNUM_0 0x00000001U
7545 #define USB_OTG_CHNUM_1 0x00000002U
7546 #define USB_OTG_CHNUM_2 0x00000004U
7547 #define USB_OTG_CHNUM_3 0x00000008U
7548 #define USB_OTG_BCNT 0x00007FF0U
7550 #define USB_OTG_DPID 0x00018000U
7551 #define USB_OTG_DPID_0 0x00008000U
7552 #define USB_OTG_DPID_1 0x00010000U
7554 #define USB_OTG_PKTSTS 0x001E0000U
7555 #define USB_OTG_PKTSTS_0 0x00020000U
7556 #define USB_OTG_PKTSTS_1 0x00040000U
7557 #define USB_OTG_PKTSTS_2 0x00080000U
7558 #define USB_OTG_PKTSTS_3 0x00100000U
7560 #define USB_OTG_EPNUM 0x0000000FU
7561 #define USB_OTG_EPNUM_0 0x00000001U
7562 #define USB_OTG_EPNUM_1 0x00000002U
7563 #define USB_OTG_EPNUM_2 0x00000004U
7564 #define USB_OTG_EPNUM_3 0x00000008U
7566 #define USB_OTG_FRMNUM 0x01E00000U
7567 #define USB_OTG_FRMNUM_0 0x00200000U
7568 #define USB_OTG_FRMNUM_1 0x00400000U
7569 #define USB_OTG_FRMNUM_2 0x00800000U
7570 #define USB_OTG_FRMNUM_3 0x01000000U
7572 /******************** Bit definition for OTG register ********************/
7573 
7574 #define USB_OTG_CHNUM 0x0000000FU
7575 #define USB_OTG_CHNUM_0 0x00000001U
7576 #define USB_OTG_CHNUM_1 0x00000002U
7577 #define USB_OTG_CHNUM_2 0x00000004U
7578 #define USB_OTG_CHNUM_3 0x00000008U
7579 #define USB_OTG_BCNT 0x00007FF0U
7581 #define USB_OTG_DPID 0x00018000U
7582 #define USB_OTG_DPID_0 0x00008000U
7583 #define USB_OTG_DPID_1 0x00010000U
7585 #define USB_OTG_PKTSTS 0x001E0000U
7586 #define USB_OTG_PKTSTS_0 0x00020000U
7587 #define USB_OTG_PKTSTS_1 0x00040000U
7588 #define USB_OTG_PKTSTS_2 0x00080000U
7589 #define USB_OTG_PKTSTS_3 0x00100000U
7591 #define USB_OTG_EPNUM 0x0000000FU
7592 #define USB_OTG_EPNUM_0 0x00000001U
7593 #define USB_OTG_EPNUM_1 0x00000002U
7594 #define USB_OTG_EPNUM_2 0x00000004U
7595 #define USB_OTG_EPNUM_3 0x00000008U
7597 #define USB_OTG_FRMNUM 0x01E00000U
7598 #define USB_OTG_FRMNUM_0 0x00200000U
7599 #define USB_OTG_FRMNUM_1 0x00400000U
7600 #define USB_OTG_FRMNUM_2 0x00800000U
7601 #define USB_OTG_FRMNUM_3 0x01000000U
7603 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
7604 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
7606 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
7607 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
7609 /******************** Bit definition for OTG register ********************/
7610 #define USB_OTG_NPTXFSA 0x0000FFFFU
7611 #define USB_OTG_NPTXFD 0xFFFF0000U
7612 #define USB_OTG_TX0FSA 0x0000FFFFU
7613 #define USB_OTG_TX0FD 0xFFFF0000U
7615 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
7616 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
7618 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
7619 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
7621 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
7622 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
7623 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
7624 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
7625 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
7626 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
7627 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
7628 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
7629 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
7631 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
7632 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
7633 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
7634 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
7635 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
7636 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
7637 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
7638 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
7640 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
7641 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
7642 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
7644 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
7645 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
7646 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
7647 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
7648 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
7649 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
7650 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
7651 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
7652 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
7653 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
7654 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
7656 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
7657 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
7658 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
7659 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
7660 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
7661 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
7662 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
7663 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
7664 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
7665 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
7666 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
7668 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
7669 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
7671 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
7672 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
7673 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
7675 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
7676 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
7677 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
7678 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
7679 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
7680 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
7681 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
7683 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
7684 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
7685 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
7687 /******************** Bit definition forUSB_OTG_CID register ********************/
7688 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
7690 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
7691 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
7692 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
7693 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
7694 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
7695 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
7696 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
7697 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
7698 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
7699 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
7701 /******************** Bit definition forUSB_OTG_HPRT register ********************/
7702 #define USB_OTG_HPRT_PCSTS 0x00000001U
7703 #define USB_OTG_HPRT_PCDET 0x00000002U
7704 #define USB_OTG_HPRT_PENA 0x00000004U
7705 #define USB_OTG_HPRT_PENCHNG 0x00000008U
7706 #define USB_OTG_HPRT_POCA 0x00000010U
7707 #define USB_OTG_HPRT_POCCHNG 0x00000020U
7708 #define USB_OTG_HPRT_PRES 0x00000040U
7709 #define USB_OTG_HPRT_PSUSP 0x00000080U
7710 #define USB_OTG_HPRT_PRST 0x00000100U
7712 #define USB_OTG_HPRT_PLSTS 0x00000C00U
7713 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
7714 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
7715 #define USB_OTG_HPRT_PPWR 0x00001000U
7717 #define USB_OTG_HPRT_PTCTL 0x0001E000U
7718 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
7719 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
7720 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
7721 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
7723 #define USB_OTG_HPRT_PSPD 0x00060000U
7724 #define USB_OTG_HPRT_PSPD_0 0x00020000U
7725 #define USB_OTG_HPRT_PSPD_1 0x00040000U
7727 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
7728 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
7729 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
7730 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
7731 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
7732 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
7733 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
7734 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
7735 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
7736 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
7737 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
7738 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
7740 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
7741 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
7742 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
7744 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
7745 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
7746 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
7747 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
7748 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
7750 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
7751 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
7752 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
7753 #define USB_OTG_DIEPCTL_STALL 0x00200000U
7755 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
7756 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
7757 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
7758 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
7759 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
7760 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
7761 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
7762 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
7763 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
7764 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
7765 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
7767 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
7768 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
7770 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
7771 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
7772 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
7773 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
7774 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
7775 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
7776 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
7778 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
7779 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
7780 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
7782 #define USB_OTG_HCCHAR_MC 0x00300000U
7783 #define USB_OTG_HCCHAR_MC_0 0x00100000U
7784 #define USB_OTG_HCCHAR_MC_1 0x00200000U
7786 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
7787 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
7788 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
7789 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
7790 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
7791 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
7792 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
7793 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
7794 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
7795 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
7796 #define USB_OTG_HCCHAR_CHENA 0x80000000U
7798 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
7799 
7800 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
7801 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
7802 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
7803 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
7804 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
7805 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
7806 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
7807 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
7809 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
7810 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
7811 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
7812 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
7813 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
7814 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
7815 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
7816 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
7818 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
7819 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
7820 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
7821 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
7822 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
7824 /******************** Bit definition forUSB_OTG_HCINT register ********************/
7825 #define USB_OTG_HCINT_XFRC 0x00000001U
7826 #define USB_OTG_HCINT_CHH 0x00000002U
7827 #define USB_OTG_HCINT_AHBERR 0x00000004U
7828 #define USB_OTG_HCINT_STALL 0x00000008U
7829 #define USB_OTG_HCINT_NAK 0x00000010U
7830 #define USB_OTG_HCINT_ACK 0x00000020U
7831 #define USB_OTG_HCINT_NYET 0x00000040U
7832 #define USB_OTG_HCINT_TXERR 0x00000080U
7833 #define USB_OTG_HCINT_BBERR 0x00000100U
7834 #define USB_OTG_HCINT_FRMOR 0x00000200U
7835 #define USB_OTG_HCINT_DTERR 0x00000400U
7837 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
7838 #define USB_OTG_DIEPINT_XFRC 0x00000001U
7839 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
7840 #define USB_OTG_DIEPINT_TOC 0x00000008U
7841 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
7842 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
7843 #define USB_OTG_DIEPINT_TXFE 0x00000080U
7844 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
7845 #define USB_OTG_DIEPINT_BNA 0x00000200U
7846 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
7847 #define USB_OTG_DIEPINT_BERR 0x00001000U
7848 #define USB_OTG_DIEPINT_NAK 0x00002000U
7850 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
7851 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
7852 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
7853 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
7854 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
7855 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
7856 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
7857 #define USB_OTG_HCINTMSK_NYET 0x00000040U
7858 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
7859 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
7860 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
7861 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
7863 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
7864 
7865 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
7866 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
7867 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
7868 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
7869 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
7870 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
7871 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
7872 #define USB_OTG_HCTSIZ_DPID 0x60000000U
7873 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
7874 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
7876 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
7877 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
7879 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
7880 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
7882 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
7883 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
7885 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
7886 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
7887 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
7889 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
7890 
7891 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
7892 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
7893 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
7894 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
7895 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
7896 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
7897 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
7898 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
7899 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
7900 #define USB_OTG_DOEPCTL_STALL 0x00200000U
7901 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
7902 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
7903 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
7904 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
7906 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
7907 #define USB_OTG_DOEPINT_XFRC 0x00000001U
7908 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
7909 #define USB_OTG_DOEPINT_STUP 0x00000008U
7910 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
7911 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
7912 #define USB_OTG_DOEPINT_NYET 0x00004000U
7914 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
7915 
7916 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
7917 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
7919 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
7920 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
7921 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
7923 /******************** Bit definition for PCGCCTL register ********************/
7924 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
7925 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
7926 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
7940 /******************************* ADC Instances ********************************/
7941 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
7942  ((INSTANCE) == ADC2) || \
7943  ((INSTANCE) == ADC3))
7944 
7945 /******************************* CAN Instances ********************************/
7946 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
7947  ((INSTANCE) == CAN2))
7948 
7949 /******************************* CRC Instances ********************************/
7950 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7951 
7952 /******************************* DAC Instances ********************************/
7953 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
7954 
7955 /******************************* DCMI Instances *******************************/
7956 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
7957 
7958 /******************************** DMA Instances *******************************/
7959 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7960  ((INSTANCE) == DMA1_Stream1) || \
7961  ((INSTANCE) == DMA1_Stream2) || \
7962  ((INSTANCE) == DMA1_Stream3) || \
7963  ((INSTANCE) == DMA1_Stream4) || \
7964  ((INSTANCE) == DMA1_Stream5) || \
7965  ((INSTANCE) == DMA1_Stream6) || \
7966  ((INSTANCE) == DMA1_Stream7) || \
7967  ((INSTANCE) == DMA2_Stream0) || \
7968  ((INSTANCE) == DMA2_Stream1) || \
7969  ((INSTANCE) == DMA2_Stream2) || \
7970  ((INSTANCE) == DMA2_Stream3) || \
7971  ((INSTANCE) == DMA2_Stream4) || \
7972  ((INSTANCE) == DMA2_Stream5) || \
7973  ((INSTANCE) == DMA2_Stream6) || \
7974  ((INSTANCE) == DMA2_Stream7))
7975 
7976 /******************************* GPIO Instances *******************************/
7977 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7978  ((INSTANCE) == GPIOB) || \
7979  ((INSTANCE) == GPIOC) || \
7980  ((INSTANCE) == GPIOD) || \
7981  ((INSTANCE) == GPIOE) || \
7982  ((INSTANCE) == GPIOF) || \
7983  ((INSTANCE) == GPIOG) || \
7984  ((INSTANCE) == GPIOH) || \
7985  ((INSTANCE) == GPIOI))
7986 
7987 /******************************** I2C Instances *******************************/
7988 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7989  ((INSTANCE) == I2C2) || \
7990  ((INSTANCE) == I2C3))
7991 
7992 /******************************** I2S Instances *******************************/
7993 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
7994  ((INSTANCE) == SPI3))
7995 
7996 /*************************** I2S Extended Instances ***************************/
7997 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
7998  ((INSTANCE) == SPI3) || \
7999  ((INSTANCE) == I2S2ext) || \
8000  ((INSTANCE) == I2S3ext))
8001 
8002 /******************************* RNG Instances ********************************/
8003 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
8004 
8005 /****************************** RTC Instances *********************************/
8006 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
8007 
8008 /******************************** SPI Instances *******************************/
8009 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8010  ((INSTANCE) == SPI2) || \
8011  ((INSTANCE) == SPI3))
8012 
8013 /*************************** SPI Extended Instances ***************************/
8014 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
8015  ((INSTANCE) == SPI2) || \
8016  ((INSTANCE) == SPI3) || \
8017  ((INSTANCE) == I2S2ext) || \
8018  ((INSTANCE) == I2S3ext))
8019 
8020 /****************** TIM Instances : All supported instances *******************/
8021 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8022  ((INSTANCE) == TIM2) || \
8023  ((INSTANCE) == TIM3) || \
8024  ((INSTANCE) == TIM4) || \
8025  ((INSTANCE) == TIM5) || \
8026  ((INSTANCE) == TIM6) || \
8027  ((INSTANCE) == TIM7) || \
8028  ((INSTANCE) == TIM8) || \
8029  ((INSTANCE) == TIM9) || \
8030  ((INSTANCE) == TIM10) || \
8031  ((INSTANCE) == TIM11) || \
8032  ((INSTANCE) == TIM12) || \
8033  ((INSTANCE) == TIM13) || \
8034  ((INSTANCE) == TIM14))
8035 
8036 /************* TIM Instances : at least 1 capture/compare channel *************/
8037 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8038  ((INSTANCE) == TIM2) || \
8039  ((INSTANCE) == TIM3) || \
8040  ((INSTANCE) == TIM4) || \
8041  ((INSTANCE) == TIM5) || \
8042  ((INSTANCE) == TIM8) || \
8043  ((INSTANCE) == TIM9) || \
8044  ((INSTANCE) == TIM10) || \
8045  ((INSTANCE) == TIM11) || \
8046  ((INSTANCE) == TIM12) || \
8047  ((INSTANCE) == TIM13) || \
8048  ((INSTANCE) == TIM14))
8049 
8050 /************ TIM Instances : at least 2 capture/compare channels *************/
8051 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8052  ((INSTANCE) == TIM2) || \
8053  ((INSTANCE) == TIM3) || \
8054  ((INSTANCE) == TIM4) || \
8055  ((INSTANCE) == TIM5) || \
8056  ((INSTANCE) == TIM8) || \
8057  ((INSTANCE) == TIM9) || \
8058  ((INSTANCE) == TIM12))
8059 
8060 /************ TIM Instances : at least 3 capture/compare channels *************/
8061 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8062  ((INSTANCE) == TIM2) || \
8063  ((INSTANCE) == TIM3) || \
8064  ((INSTANCE) == TIM4) || \
8065  ((INSTANCE) == TIM5) || \
8066  ((INSTANCE) == TIM8))
8067 
8068 /************ TIM Instances : at least 4 capture/compare channels *************/
8069 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8070  ((INSTANCE) == TIM2) || \
8071  ((INSTANCE) == TIM3) || \
8072  ((INSTANCE) == TIM4) || \
8073  ((INSTANCE) == TIM5) || \
8074  ((INSTANCE) == TIM8))
8075 
8076 /******************** TIM Instances : Advanced-control timers *****************/
8077 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8078  ((INSTANCE) == TIM8))
8079 
8080 /******************* TIM Instances : Timer input XOR function *****************/
8081 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8082  ((INSTANCE) == TIM2) || \
8083  ((INSTANCE) == TIM3) || \
8084  ((INSTANCE) == TIM4) || \
8085  ((INSTANCE) == TIM5) || \
8086  ((INSTANCE) == TIM8))
8087 
8088 /****************** TIM Instances : DMA requests generation (UDE) *************/
8089 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8090  ((INSTANCE) == TIM2) || \
8091  ((INSTANCE) == TIM3) || \
8092  ((INSTANCE) == TIM4) || \
8093  ((INSTANCE) == TIM5) || \
8094  ((INSTANCE) == TIM6) || \
8095  ((INSTANCE) == TIM7) || \
8096  ((INSTANCE) == TIM8))
8097 
8098 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8099 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8100  ((INSTANCE) == TIM2) || \
8101  ((INSTANCE) == TIM3) || \
8102  ((INSTANCE) == TIM4) || \
8103  ((INSTANCE) == TIM5) || \
8104  ((INSTANCE) == TIM8))
8105 
8106 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8107 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8108  ((INSTANCE) == TIM2) || \
8109  ((INSTANCE) == TIM3) || \
8110  ((INSTANCE) == TIM4) || \
8111  ((INSTANCE) == TIM5) || \
8112  ((INSTANCE) == TIM8))
8113 
8114 /******************** TIM Instances : DMA burst feature ***********************/
8115 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8116  ((INSTANCE) == TIM2) || \
8117  ((INSTANCE) == TIM3) || \
8118  ((INSTANCE) == TIM4) || \
8119  ((INSTANCE) == TIM5) || \
8120  ((INSTANCE) == TIM8))
8121 
8122 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8123 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8124  ((INSTANCE) == TIM2) || \
8125  ((INSTANCE) == TIM3) || \
8126  ((INSTANCE) == TIM4) || \
8127  ((INSTANCE) == TIM5) || \
8128  ((INSTANCE) == TIM6) || \
8129  ((INSTANCE) == TIM7) || \
8130  ((INSTANCE) == TIM8) || \
8131  ((INSTANCE) == TIM9) || \
8132  ((INSTANCE) == TIM12))
8133 
8134 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8135 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8136  ((INSTANCE) == TIM2) || \
8137  ((INSTANCE) == TIM3) || \
8138  ((INSTANCE) == TIM4) || \
8139  ((INSTANCE) == TIM5) || \
8140  ((INSTANCE) == TIM8) || \
8141  ((INSTANCE) == TIM9) || \
8142  ((INSTANCE) == TIM12))
8143 
8144 /********************** TIM Instances : 32 bit Counter ************************/
8145 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
8146  ((INSTANCE) == TIM5))
8147 
8148 /***************** TIM Instances : external trigger input availabe ************/
8149 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8150  ((INSTANCE) == TIM2) || \
8151  ((INSTANCE) == TIM3) || \
8152  ((INSTANCE) == TIM4) || \
8153  ((INSTANCE) == TIM5) || \
8154  ((INSTANCE) == TIM8))
8155 
8156 /****************** TIM Instances : remapping capability **********************/
8157 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8158  ((INSTANCE) == TIM5) || \
8159  ((INSTANCE) == TIM11))
8160 
8161 /******************* TIM Instances : output(s) available **********************/
8162 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8163  ((((INSTANCE) == TIM1) && \
8164  (((CHANNEL) == TIM_CHANNEL_1) || \
8165  ((CHANNEL) == TIM_CHANNEL_2) || \
8166  ((CHANNEL) == TIM_CHANNEL_3) || \
8167  ((CHANNEL) == TIM_CHANNEL_4))) \
8168  || \
8169  (((INSTANCE) == TIM2) && \
8170  (((CHANNEL) == TIM_CHANNEL_1) || \
8171  ((CHANNEL) == TIM_CHANNEL_2) || \
8172  ((CHANNEL) == TIM_CHANNEL_3) || \
8173  ((CHANNEL) == TIM_CHANNEL_4))) \
8174  || \
8175  (((INSTANCE) == TIM3) && \
8176  (((CHANNEL) == TIM_CHANNEL_1) || \
8177  ((CHANNEL) == TIM_CHANNEL_2) || \
8178  ((CHANNEL) == TIM_CHANNEL_3) || \
8179  ((CHANNEL) == TIM_CHANNEL_4))) \
8180  || \
8181  (((INSTANCE) == TIM4) && \
8182  (((CHANNEL) == TIM_CHANNEL_1) || \
8183  ((CHANNEL) == TIM_CHANNEL_2) || \
8184  ((CHANNEL) == TIM_CHANNEL_3) || \
8185  ((CHANNEL) == TIM_CHANNEL_4))) \
8186  || \
8187  (((INSTANCE) == TIM5) && \
8188  (((CHANNEL) == TIM_CHANNEL_1) || \
8189  ((CHANNEL) == TIM_CHANNEL_2) || \
8190  ((CHANNEL) == TIM_CHANNEL_3) || \
8191  ((CHANNEL) == TIM_CHANNEL_4))) \
8192  || \
8193  (((INSTANCE) == TIM8) && \
8194  (((CHANNEL) == TIM_CHANNEL_1) || \
8195  ((CHANNEL) == TIM_CHANNEL_2) || \
8196  ((CHANNEL) == TIM_CHANNEL_3) || \
8197  ((CHANNEL) == TIM_CHANNEL_4))) \
8198  || \
8199  (((INSTANCE) == TIM9) && \
8200  (((CHANNEL) == TIM_CHANNEL_1) || \
8201  ((CHANNEL) == TIM_CHANNEL_2))) \
8202  || \
8203  (((INSTANCE) == TIM10) && \
8204  (((CHANNEL) == TIM_CHANNEL_1))) \
8205  || \
8206  (((INSTANCE) == TIM11) && \
8207  (((CHANNEL) == TIM_CHANNEL_1))) \
8208  || \
8209  (((INSTANCE) == TIM12) && \
8210  (((CHANNEL) == TIM_CHANNEL_1) || \
8211  ((CHANNEL) == TIM_CHANNEL_2))) \
8212  || \
8213  (((INSTANCE) == TIM13) && \
8214  (((CHANNEL) == TIM_CHANNEL_1))) \
8215  || \
8216  (((INSTANCE) == TIM14) && \
8217  (((CHANNEL) == TIM_CHANNEL_1))))
8218 
8219 /************ TIM Instances : complementary output(s) available ***************/
8220 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8221  ((((INSTANCE) == TIM1) && \
8222  (((CHANNEL) == TIM_CHANNEL_1) || \
8223  ((CHANNEL) == TIM_CHANNEL_2) || \
8224  ((CHANNEL) == TIM_CHANNEL_3))) \
8225  || \
8226  (((INSTANCE) == TIM8) && \
8227  (((CHANNEL) == TIM_CHANNEL_1) || \
8228  ((CHANNEL) == TIM_CHANNEL_2) || \
8229  ((CHANNEL) == TIM_CHANNEL_3))))
8230 
8231 /******************** USART Instances : Synchronous mode **********************/
8232 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8233  ((INSTANCE) == USART2) || \
8234  ((INSTANCE) == USART3) || \
8235  ((INSTANCE) == USART6))
8236 
8237 /******************** UART Instances : Asynchronous mode **********************/
8238 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8239  ((INSTANCE) == USART2) || \
8240  ((INSTANCE) == USART3) || \
8241  ((INSTANCE) == UART4) || \
8242  ((INSTANCE) == UART5) || \
8243  ((INSTANCE) == USART6))
8244 
8245 /****************** UART Instances : Hardware Flow control ********************/
8246 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8247  ((INSTANCE) == USART2) || \
8248  ((INSTANCE) == USART3) || \
8249  ((INSTANCE) == USART6))
8250 
8251 /********************* UART Instances : Smard card mode ***********************/
8252 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8253  ((INSTANCE) == USART2) || \
8254  ((INSTANCE) == USART3) || \
8255  ((INSTANCE) == USART6))
8256 
8257 /*********************** UART Instances : IRDA mode ***************************/
8258 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8259  ((INSTANCE) == USART2) || \
8260  ((INSTANCE) == USART3) || \
8261  ((INSTANCE) == UART4) || \
8262  ((INSTANCE) == UART5) || \
8263  ((INSTANCE) == USART6))
8264 
8265 /*********************** PCD Instances ****************************************/
8266 /*********************** PCD Instances ****************************************/
8267 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
8268  ((INSTANCE) == USB_OTG_HS))
8269 
8270 /*********************** HCD Instances ****************************************/
8271 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
8272  ((INSTANCE) == USB_OTG_HS))
8273 
8274 /****************************** IWDG Instances ********************************/
8275 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
8276 
8277 /****************************** WWDG Instances ********************************/
8278 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8279 
8280 /****************************** SDIO Instances ********************************/
8281 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
8282 
8283 /****************************** USB Exported Constants ************************/
8284 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
8285 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
8286 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
8287 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
8288 
8289 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
8290 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
8291 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
8292 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
8293 
8294 /******************************************************************************/
8295 /* For a painless codes migration between the STM32F4xx device product */
8296 /* lines, the aliases defined below are put in place to overcome the */
8297 /* differences in the interrupt handlers and IRQn definitions. */
8298 /* No need to update developed interrupt code when moving across */
8299 /* product lines within the same STM32F4 Family */
8300 /******************************************************************************/
8301 
8302 /* Aliases for __IRQn */
8303 #define FMC_IRQn FSMC_IRQn
8304 
8305 /* Aliases for __IRQHandler */
8306 #define FMC_IRQHandler FSMC_IRQHandler
8307 
8320 #ifdef __cplusplus
8321 }
8322 #endif /* __cplusplus */
8323 
8324 #endif /* __STM32F4xx_H */
8325 
8326 
8327 
8328 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
TAMP_STAMP_IRQn
Definition: stm32f417xx.h:99
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f405xx.h:395
TIM2_IRQn
Definition: stm32f417xx.h:125
UART4_IRQn
Definition: stm32f417xx.h:149
UART5_IRQn
Definition: stm32f417xx.h:150
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f417xx.h:123
EXTI2_IRQn
Definition: stm32f417xx.h:105
EXTI4_IRQn
Definition: stm32f417xx.h:107
USART1_IRQn
Definition: stm32f417xx.h:134
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
ETH_WKUP_IRQn
Definition: stm32f417xx.h:159
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f417xx.h:142
TIM4_IRQn
Definition: stm32f417xx.h:127
RTC_Alarm_IRQn
Definition: stm32f417xx.h:138
CAN2_SCE_IRQn
Definition: stm32f417xx.h:163
CRYP_IRQn
Definition: stm32f417xx.h:176
PendSV_IRQn
Definition: stm32f417xx.h:94
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f417xx.h:100
CAN1_RX1_IRQn
Definition: stm32f417xx.h:118
TIM6_DAC_IRQn
Definition: stm32f417xx.h:151
CAN1_TX_IRQn
Definition: stm32f417xx.h:116
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f417xx.h:132
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
OTG_FS_WKUP_IRQn
Definition: stm32f417xx.h:139
DMA_TypeDef
Definition: stm32f401xc.h:243
ETH_IRQn
Definition: stm32f417xx.h:158
DMA1_Stream2_IRQn
Definition: stm32f417xx.h:110
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f417xx.h:133
__I
#define __I
Definition: core_cm0.h:210
DMA2_Stream5_IRQn
Definition: stm32f417xx.h:165
ADC_IRQn
Definition: stm32f417xx.h:115
CAN1_RX0_IRQn
Definition: stm32f417xx.h:117
RCC_IRQn
Definition: stm32f417xx.h:102
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32f415xx.h:768
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f417xx.h:93
DMA2_Stream3_IRQn
Definition: stm32f417xx.h:156
NonMaskableInt_IRQn
Definition: stm32f417xx.h:88
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f417xx.h:85
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f417xx.h:141
DMA1_Stream1_IRQn
Definition: stm32f417xx.h:109
DMA2_Stream7_IRQn
Definition: stm32f417xx.h:167
DMA2_Stream6_IRQn
Definition: stm32f417xx.h:166
BusFault_IRQn
Definition: stm32f417xx.h:90
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
I2C3_ER_IRQn
Definition: stm32f417xx.h:170
CAN2_RX0_IRQn
Definition: stm32f417xx.h:161
USART6_IRQn
Definition: stm32f417xx.h:168
PVD_IRQn
Definition: stm32f417xx.h:98
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f417xx.h:112
DMA1_Stream0_IRQn
Definition: stm32f417xx.h:108
OTG_HS_IRQn
Definition: stm32f417xx.h:174
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
TIM8_CC_IRQn
Definition: stm32f417xx.h:143
DMA1_Stream3_IRQn
Definition: stm32f417xx.h:111
FPU_IRQn
Definition: stm32f417xx.h:178
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:386
OTG_FS_IRQn
Definition: stm32f417xx.h:164
DMA2_Stream2_IRQn
Definition: stm32f417xx.h:155
OTG_HS_EP1_OUT_IRQn
Definition: stm32f417xx.h:171
OTG_HS_EP1_IN_IRQn
Definition: stm32f417xx.h:172
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f417xx.h:146
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f417xx.h:169
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f417xx.h:135
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f417xx.h:152
I2C2_EV_IRQn
Definition: stm32f417xx.h:130
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f417xx.h:126
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f417xx.h:104
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f417xx.h:92
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f417xx.h:124
TIM8_BRK_TIM12_IRQn
Definition: stm32f417xx.h:140
HASH_RNG_IRQn
Definition: stm32f417xx.h:177
FLASH_IRQn
Definition: stm32f417xx.h:101
DMA1_Stream5_IRQn
Definition: stm32f417xx.h:113
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f417xx.h:95
TIM1_UP_TIM10_IRQn
Definition: stm32f417xx.h:122
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f417xx.h:131
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:344
UsageFault_IRQn
Definition: stm32f417xx.h:91
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f405xx.h:404
SPI3_IRQn
Definition: stm32f417xx.h:148
DMA2_Stream1_IRQn
Definition: stm32f417xx.h:154
EXTI9_5_IRQn
Definition: stm32f417xx.h:120
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f417xx.h:128
DMA1_Stream6_IRQn
Definition: stm32f417xx.h:114
OTG_HS_WKUP_IRQn
Definition: stm32f417xx.h:173
I2C1_ER_IRQn
Definition: stm32f417xx.h:129
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
FSMC_IRQn
Definition: stm32f417xx.h:145
HASH_TypeDef
HASH.
Definition: stm32f415xx.h:752
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
FSMC_Bank2_3_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f405xx.h:413
CAN2_RX1_IRQn
Definition: stm32f417xx.h:162
DMA2_Stream4_IRQn
Definition: stm32f417xx.h:157
WWDG_IRQn
Definition: stm32f417xx.h:97
CRYP_TypeDef
Crypto Processor.
Definition: stm32f415xx.h:708
DMA1_Stream7_IRQn
Definition: stm32f417xx.h:144
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
EXTI15_10_IRQn
Definition: stm32f417xx.h:137
CAN1_SCE_IRQn
Definition: stm32f417xx.h:119
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f417xx.h:103
DMA2_Stream0_IRQn
Definition: stm32f417xx.h:153
TIM1_BRK_TIM9_IRQn
Definition: stm32f417xx.h:121
CAN2_TX_IRQn
Definition: stm32f417xx.h:160
TIM5_IRQn
Definition: stm32f417xx.h:147
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f417xx.h:106
USART3_IRQn
Definition: stm32f417xx.h:136
DCMI_IRQn
Definition: stm32f417xx.h:175
MemoryManagement_IRQn
Definition: stm32f417xx.h:89
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f405xx.h:435