STM CMSIS
stm32f427xx.h
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1 
52 #ifndef __stm32f427xx_H
53 #define __stm32f427xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
66 #define __CM4_REV 0x0001U
67 #define __MPU_PRESENT 1U
68 #define __NVIC_PRIO_BITS 4U
69 #define __Vendor_SysTickConfig 0U
70 #define __FPU_PRESENT 1U
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87  NonMaskableInt_IRQn = -14,
88  MemoryManagement_IRQn = -12,
89  BusFault_IRQn = -11,
90  UsageFault_IRQn = -10,
91  SVCall_IRQn = -5,
92  DebugMonitor_IRQn = -4,
93  PendSV_IRQn = -2,
94  SysTick_IRQn = -1,
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96  WWDG_IRQn = 0,
97  PVD_IRQn = 1,
98  TAMP_STAMP_IRQn = 2,
99  RTC_WKUP_IRQn = 3,
100  FLASH_IRQn = 4,
101  RCC_IRQn = 5,
102  EXTI0_IRQn = 6,
103  EXTI1_IRQn = 7,
104  EXTI2_IRQn = 8,
105  EXTI3_IRQn = 9,
106  EXTI4_IRQn = 10,
107  DMA1_Stream0_IRQn = 11,
108  DMA1_Stream1_IRQn = 12,
109  DMA1_Stream2_IRQn = 13,
110  DMA1_Stream3_IRQn = 14,
111  DMA1_Stream4_IRQn = 15,
112  DMA1_Stream5_IRQn = 16,
113  DMA1_Stream6_IRQn = 17,
114  ADC_IRQn = 18,
115  CAN1_TX_IRQn = 19,
116  CAN1_RX0_IRQn = 20,
117  CAN1_RX1_IRQn = 21,
118  CAN1_SCE_IRQn = 22,
119  EXTI9_5_IRQn = 23,
120  TIM1_BRK_TIM9_IRQn = 24,
121  TIM1_UP_TIM10_IRQn = 25,
122  TIM1_TRG_COM_TIM11_IRQn = 26,
123  TIM1_CC_IRQn = 27,
124  TIM2_IRQn = 28,
125  TIM3_IRQn = 29,
126  TIM4_IRQn = 30,
127  I2C1_EV_IRQn = 31,
128  I2C1_ER_IRQn = 32,
129  I2C2_EV_IRQn = 33,
130  I2C2_ER_IRQn = 34,
131  SPI1_IRQn = 35,
132  SPI2_IRQn = 36,
133  USART1_IRQn = 37,
134  USART2_IRQn = 38,
135  USART3_IRQn = 39,
136  EXTI15_10_IRQn = 40,
137  RTC_Alarm_IRQn = 41,
138  OTG_FS_WKUP_IRQn = 42,
139  TIM8_BRK_TIM12_IRQn = 43,
140  TIM8_UP_TIM13_IRQn = 44,
141  TIM8_TRG_COM_TIM14_IRQn = 45,
142  TIM8_CC_IRQn = 46,
143  DMA1_Stream7_IRQn = 47,
144  FMC_IRQn = 48,
145  SDIO_IRQn = 49,
146  TIM5_IRQn = 50,
147  SPI3_IRQn = 51,
148  UART4_IRQn = 52,
149  UART5_IRQn = 53,
150  TIM6_DAC_IRQn = 54,
151  TIM7_IRQn = 55,
152  DMA2_Stream0_IRQn = 56,
153  DMA2_Stream1_IRQn = 57,
154  DMA2_Stream2_IRQn = 58,
155  DMA2_Stream3_IRQn = 59,
156  DMA2_Stream4_IRQn = 60,
157  ETH_IRQn = 61,
158  ETH_WKUP_IRQn = 62,
159  CAN2_TX_IRQn = 63,
160  CAN2_RX0_IRQn = 64,
161  CAN2_RX1_IRQn = 65,
162  CAN2_SCE_IRQn = 66,
163  OTG_FS_IRQn = 67,
164  DMA2_Stream5_IRQn = 68,
165  DMA2_Stream6_IRQn = 69,
166  DMA2_Stream7_IRQn = 70,
167  USART6_IRQn = 71,
168  I2C3_EV_IRQn = 72,
169  I2C3_ER_IRQn = 73,
170  OTG_HS_EP1_OUT_IRQn = 74,
171  OTG_HS_EP1_IN_IRQn = 75,
172  OTG_HS_WKUP_IRQn = 76,
173  OTG_HS_IRQn = 77,
174  DCMI_IRQn = 78,
175  HASH_RNG_IRQn = 80,
176  FPU_IRQn = 81,
177  UART7_IRQn = 82,
178  UART8_IRQn = 83,
179  SPI4_IRQn = 84,
180  SPI5_IRQn = 85,
181  SPI6_IRQn = 86,
182  SAI1_IRQn = 87,
183  DMA2D_IRQn = 90
184 } IRQn_Type;
185 
190 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
191 #include "system_stm32f4xx.h"
192 #include <stdint.h>
193 
202 typedef struct
203 {
204  __IO uint32_t SR;
205  __IO uint32_t CR1;
206  __IO uint32_t CR2;
207  __IO uint32_t SMPR1;
208  __IO uint32_t SMPR2;
209  __IO uint32_t JOFR1;
210  __IO uint32_t JOFR2;
211  __IO uint32_t JOFR3;
212  __IO uint32_t JOFR4;
213  __IO uint32_t HTR;
214  __IO uint32_t LTR;
215  __IO uint32_t SQR1;
216  __IO uint32_t SQR2;
217  __IO uint32_t SQR3;
218  __IO uint32_t JSQR;
219  __IO uint32_t JDR1;
220  __IO uint32_t JDR2;
221  __IO uint32_t JDR3;
222  __IO uint32_t JDR4;
223  __IO uint32_t DR;
224 } ADC_TypeDef;
225 
226 typedef struct
227 {
228  __IO uint32_t CSR;
229  __IO uint32_t CCR;
230  __IO uint32_t CDR;
232 } ADC_Common_TypeDef;
233 
234 
239 typedef struct
240 {
241  __IO uint32_t TIR;
242  __IO uint32_t TDTR;
243  __IO uint32_t TDLR;
244  __IO uint32_t TDHR;
245 } CAN_TxMailBox_TypeDef;
246 
251 typedef struct
252 {
253  __IO uint32_t RIR;
254  __IO uint32_t RDTR;
255  __IO uint32_t RDLR;
256  __IO uint32_t RDHR;
257 } CAN_FIFOMailBox_TypeDef;
258 
263 typedef struct
264 {
265  __IO uint32_t FR1;
266  __IO uint32_t FR2;
267 } CAN_FilterRegister_TypeDef;
268 
273 typedef struct
274 {
275  __IO uint32_t MCR;
276  __IO uint32_t MSR;
277  __IO uint32_t TSR;
278  __IO uint32_t RF0R;
279  __IO uint32_t RF1R;
280  __IO uint32_t IER;
281  __IO uint32_t ESR;
282  __IO uint32_t BTR;
283  uint32_t RESERVED0[88];
284  CAN_TxMailBox_TypeDef sTxMailBox[3];
285  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
286  uint32_t RESERVED1[12];
287  __IO uint32_t FMR;
288  __IO uint32_t FM1R;
289  uint32_t RESERVED2;
290  __IO uint32_t FS1R;
291  uint32_t RESERVED3;
292  __IO uint32_t FFA1R;
293  uint32_t RESERVED4;
294  __IO uint32_t FA1R;
295  uint32_t RESERVED5[8];
296  CAN_FilterRegister_TypeDef sFilterRegister[28];
297 } CAN_TypeDef;
298 
303 typedef struct
304 {
305  __IO uint32_t DR;
306  __IO uint8_t IDR;
307  uint8_t RESERVED0;
308  uint16_t RESERVED1;
309  __IO uint32_t CR;
310 } CRC_TypeDef;
311 
316 typedef struct
317 {
318  __IO uint32_t CR;
319  __IO uint32_t SWTRIGR;
320  __IO uint32_t DHR12R1;
321  __IO uint32_t DHR12L1;
322  __IO uint32_t DHR8R1;
323  __IO uint32_t DHR12R2;
324  __IO uint32_t DHR12L2;
325  __IO uint32_t DHR8R2;
326  __IO uint32_t DHR12RD;
327  __IO uint32_t DHR12LD;
328  __IO uint32_t DHR8RD;
329  __IO uint32_t DOR1;
330  __IO uint32_t DOR2;
331  __IO uint32_t SR;
332 } DAC_TypeDef;
333 
338 typedef struct
339 {
340  __IO uint32_t IDCODE;
341  __IO uint32_t CR;
342  __IO uint32_t APB1FZ;
343  __IO uint32_t APB2FZ;
344 }DBGMCU_TypeDef;
345 
350 typedef struct
351 {
352  __IO uint32_t CR;
353  __IO uint32_t SR;
354  __IO uint32_t RISR;
355  __IO uint32_t IER;
356  __IO uint32_t MISR;
357  __IO uint32_t ICR;
358  __IO uint32_t ESCR;
359  __IO uint32_t ESUR;
360  __IO uint32_t CWSTRTR;
361  __IO uint32_t CWSIZER;
362  __IO uint32_t DR;
363 } DCMI_TypeDef;
364 
369 typedef struct
370 {
371  __IO uint32_t CR;
372  __IO uint32_t NDTR;
373  __IO uint32_t PAR;
374  __IO uint32_t M0AR;
375  __IO uint32_t M1AR;
376  __IO uint32_t FCR;
377 } DMA_Stream_TypeDef;
378 
379 typedef struct
380 {
381  __IO uint32_t LISR;
382  __IO uint32_t HISR;
383  __IO uint32_t LIFCR;
384  __IO uint32_t HIFCR;
385 } DMA_TypeDef;
386 
391 typedef struct
392 {
393  __IO uint32_t CR;
394  __IO uint32_t ISR;
395  __IO uint32_t IFCR;
396  __IO uint32_t FGMAR;
397  __IO uint32_t FGOR;
398  __IO uint32_t BGMAR;
399  __IO uint32_t BGOR;
400  __IO uint32_t FGPFCCR;
401  __IO uint32_t FGCOLR;
402  __IO uint32_t BGPFCCR;
403  __IO uint32_t BGCOLR;
404  __IO uint32_t FGCMAR;
405  __IO uint32_t BGCMAR;
406  __IO uint32_t OPFCCR;
407  __IO uint32_t OCOLR;
408  __IO uint32_t OMAR;
409  __IO uint32_t OOR;
410  __IO uint32_t NLR;
411  __IO uint32_t LWR;
412  __IO uint32_t AMTCR;
413  uint32_t RESERVED[236];
414  __IO uint32_t FGCLUT[256];
415  __IO uint32_t BGCLUT[256];
416 } DMA2D_TypeDef;
417 
422 typedef struct
423 {
424  __IO uint32_t MACCR;
425  __IO uint32_t MACFFR;
426  __IO uint32_t MACHTHR;
427  __IO uint32_t MACHTLR;
428  __IO uint32_t MACMIIAR;
429  __IO uint32_t MACMIIDR;
430  __IO uint32_t MACFCR;
431  __IO uint32_t MACVLANTR; /* 8 */
432  uint32_t RESERVED0[2];
433  __IO uint32_t MACRWUFFR; /* 11 */
434  __IO uint32_t MACPMTCSR;
435  uint32_t RESERVED1[2];
436  __IO uint32_t MACSR; /* 15 */
437  __IO uint32_t MACIMR;
438  __IO uint32_t MACA0HR;
439  __IO uint32_t MACA0LR;
440  __IO uint32_t MACA1HR;
441  __IO uint32_t MACA1LR;
442  __IO uint32_t MACA2HR;
443  __IO uint32_t MACA2LR;
444  __IO uint32_t MACA3HR;
445  __IO uint32_t MACA3LR; /* 24 */
446  uint32_t RESERVED2[40];
447  __IO uint32_t MMCCR; /* 65 */
448  __IO uint32_t MMCRIR;
449  __IO uint32_t MMCTIR;
450  __IO uint32_t MMCRIMR;
451  __IO uint32_t MMCTIMR; /* 69 */
452  uint32_t RESERVED3[14];
453  __IO uint32_t MMCTGFSCCR; /* 84 */
454  __IO uint32_t MMCTGFMSCCR;
455  uint32_t RESERVED4[5];
456  __IO uint32_t MMCTGFCR;
457  uint32_t RESERVED5[10];
458  __IO uint32_t MMCRFCECR;
459  __IO uint32_t MMCRFAECR;
460  uint32_t RESERVED6[10];
461  __IO uint32_t MMCRGUFCR;
462  uint32_t RESERVED7[334];
463  __IO uint32_t PTPTSCR;
464  __IO uint32_t PTPSSIR;
465  __IO uint32_t PTPTSHR;
466  __IO uint32_t PTPTSLR;
467  __IO uint32_t PTPTSHUR;
468  __IO uint32_t PTPTSLUR;
469  __IO uint32_t PTPTSAR;
470  __IO uint32_t PTPTTHR;
471  __IO uint32_t PTPTTLR;
472  __IO uint32_t RESERVED8;
473  __IO uint32_t PTPTSSR;
474  uint32_t RESERVED9[565];
475  __IO uint32_t DMABMR;
476  __IO uint32_t DMATPDR;
477  __IO uint32_t DMARPDR;
478  __IO uint32_t DMARDLAR;
479  __IO uint32_t DMATDLAR;
480  __IO uint32_t DMASR;
481  __IO uint32_t DMAOMR;
482  __IO uint32_t DMAIER;
483  __IO uint32_t DMAMFBOCR;
484  __IO uint32_t DMARSWTR;
485  uint32_t RESERVED10[8];
486  __IO uint32_t DMACHTDR;
487  __IO uint32_t DMACHRDR;
488  __IO uint32_t DMACHTBAR;
489  __IO uint32_t DMACHRBAR;
490 } ETH_TypeDef;
491 
496 typedef struct
497 {
498  __IO uint32_t IMR;
499  __IO uint32_t EMR;
500  __IO uint32_t RTSR;
501  __IO uint32_t FTSR;
502  __IO uint32_t SWIER;
503  __IO uint32_t PR;
504 } EXTI_TypeDef;
505 
510 typedef struct
511 {
512  __IO uint32_t ACR;
513  __IO uint32_t KEYR;
514  __IO uint32_t OPTKEYR;
515  __IO uint32_t SR;
516  __IO uint32_t CR;
517  __IO uint32_t OPTCR;
518  __IO uint32_t OPTCR1;
519 } FLASH_TypeDef;
520 
525 typedef struct
526 {
527  __IO uint32_t BTCR[8];
528 } FMC_Bank1_TypeDef;
529 
534 typedef struct
535 {
536  __IO uint32_t BWTR[7];
537 } FMC_Bank1E_TypeDef;
538 
543 typedef struct
544 {
545  __IO uint32_t PCR2;
546  __IO uint32_t SR2;
547  __IO uint32_t PMEM2;
548  __IO uint32_t PATT2;
549  uint32_t RESERVED0;
550  __IO uint32_t ECCR2;
551  uint32_t RESERVED1;
552  uint32_t RESERVED2;
553  __IO uint32_t PCR3;
554  __IO uint32_t SR3;
555  __IO uint32_t PMEM3;
556  __IO uint32_t PATT3;
557  uint32_t RESERVED3;
558  __IO uint32_t ECCR3;
559 } FMC_Bank2_3_TypeDef;
560 
565 typedef struct
566 {
567  __IO uint32_t PCR4;
568  __IO uint32_t SR4;
569  __IO uint32_t PMEM4;
570  __IO uint32_t PATT4;
571  __IO uint32_t PIO4;
572 } FMC_Bank4_TypeDef;
573 
578 typedef struct
579 {
580  __IO uint32_t SDCR[2];
581  __IO uint32_t SDTR[2];
582  __IO uint32_t SDCMR;
583  __IO uint32_t SDRTR;
584  __IO uint32_t SDSR;
585 } FMC_Bank5_6_TypeDef;
586 
591 typedef struct
592 {
593  __IO uint32_t MODER;
594  __IO uint32_t OTYPER;
595  __IO uint32_t OSPEEDR;
596  __IO uint32_t PUPDR;
597  __IO uint32_t IDR;
598  __IO uint32_t ODR;
599  __IO uint32_t BSRR;
600  __IO uint32_t LCKR;
601  __IO uint32_t AFR[2];
602 } GPIO_TypeDef;
603 
608 typedef struct
609 {
610  __IO uint32_t MEMRMP;
611  __IO uint32_t PMC;
612  __IO uint32_t EXTICR[4];
613  uint32_t RESERVED[2];
614  __IO uint32_t CMPCR;
615 } SYSCFG_TypeDef;
616 
621 typedef struct
622 {
623  __IO uint32_t CR1;
624  __IO uint32_t CR2;
625  __IO uint32_t OAR1;
626  __IO uint32_t OAR2;
627  __IO uint32_t DR;
628  __IO uint32_t SR1;
629  __IO uint32_t SR2;
630  __IO uint32_t CCR;
631  __IO uint32_t TRISE;
632  __IO uint32_t FLTR;
633 } I2C_TypeDef;
634 
639 typedef struct
640 {
641  __IO uint32_t KR;
642  __IO uint32_t PR;
643  __IO uint32_t RLR;
644  __IO uint32_t SR;
645 } IWDG_TypeDef;
646 
651 typedef struct
652 {
653  __IO uint32_t CR;
654  __IO uint32_t CSR;
655 } PWR_TypeDef;
656 
661 typedef struct
662 {
663  __IO uint32_t CR;
664  __IO uint32_t PLLCFGR;
665  __IO uint32_t CFGR;
666  __IO uint32_t CIR;
667  __IO uint32_t AHB1RSTR;
668  __IO uint32_t AHB2RSTR;
669  __IO uint32_t AHB3RSTR;
670  uint32_t RESERVED0;
671  __IO uint32_t APB1RSTR;
672  __IO uint32_t APB2RSTR;
673  uint32_t RESERVED1[2];
674  __IO uint32_t AHB1ENR;
675  __IO uint32_t AHB2ENR;
676  __IO uint32_t AHB3ENR;
677  uint32_t RESERVED2;
678  __IO uint32_t APB1ENR;
679  __IO uint32_t APB2ENR;
680  uint32_t RESERVED3[2];
681  __IO uint32_t AHB1LPENR;
682  __IO uint32_t AHB2LPENR;
683  __IO uint32_t AHB3LPENR;
684  uint32_t RESERVED4;
685  __IO uint32_t APB1LPENR;
686  __IO uint32_t APB2LPENR;
687  uint32_t RESERVED5[2];
688  __IO uint32_t BDCR;
689  __IO uint32_t CSR;
690  uint32_t RESERVED6[2];
691  __IO uint32_t SSCGR;
692  __IO uint32_t PLLI2SCFGR;
693  __IO uint32_t PLLSAICFGR;
694  __IO uint32_t DCKCFGR;
696 } RCC_TypeDef;
697 
702 typedef struct
703 {
704  __IO uint32_t TR;
705  __IO uint32_t DR;
706  __IO uint32_t CR;
707  __IO uint32_t ISR;
708  __IO uint32_t PRER;
709  __IO uint32_t WUTR;
710  __IO uint32_t CALIBR;
711  __IO uint32_t ALRMAR;
712  __IO uint32_t ALRMBR;
713  __IO uint32_t WPR;
714  __IO uint32_t SSR;
715  __IO uint32_t SHIFTR;
716  __IO uint32_t TSTR;
717  __IO uint32_t TSDR;
718  __IO uint32_t TSSSR;
719  __IO uint32_t CALR;
720  __IO uint32_t TAFCR;
721  __IO uint32_t ALRMASSR;
722  __IO uint32_t ALRMBSSR;
723  uint32_t RESERVED7;
724  __IO uint32_t BKP0R;
725  __IO uint32_t BKP1R;
726  __IO uint32_t BKP2R;
727  __IO uint32_t BKP3R;
728  __IO uint32_t BKP4R;
729  __IO uint32_t BKP5R;
730  __IO uint32_t BKP6R;
731  __IO uint32_t BKP7R;
732  __IO uint32_t BKP8R;
733  __IO uint32_t BKP9R;
734  __IO uint32_t BKP10R;
735  __IO uint32_t BKP11R;
736  __IO uint32_t BKP12R;
737  __IO uint32_t BKP13R;
738  __IO uint32_t BKP14R;
739  __IO uint32_t BKP15R;
740  __IO uint32_t BKP16R;
741  __IO uint32_t BKP17R;
742  __IO uint32_t BKP18R;
743  __IO uint32_t BKP19R;
744 } RTC_TypeDef;
745 
750 typedef struct
751 {
752  __IO uint32_t GCR;
753 } SAI_TypeDef;
754 
755 typedef struct
756 {
757  __IO uint32_t CR1;
758  __IO uint32_t CR2;
759  __IO uint32_t FRCR;
760  __IO uint32_t SLOTR;
761  __IO uint32_t IMR;
762  __IO uint32_t SR;
763  __IO uint32_t CLRFR;
764  __IO uint32_t DR;
765 } SAI_Block_TypeDef;
766 
771 typedef struct
772 {
773  __IO uint32_t POWER;
774  __IO uint32_t CLKCR;
775  __IO uint32_t ARG;
776  __IO uint32_t CMD;
777  __I uint32_t RESPCMD;
778  __I uint32_t RESP1;
779  __I uint32_t RESP2;
780  __I uint32_t RESP3;
781  __I uint32_t RESP4;
782  __IO uint32_t DTIMER;
783  __IO uint32_t DLEN;
784  __IO uint32_t DCTRL;
785  __I uint32_t DCOUNT;
786  __I uint32_t STA;
787  __IO uint32_t ICR;
788  __IO uint32_t MASK;
789  uint32_t RESERVED0[2];
790  __I uint32_t FIFOCNT;
791  uint32_t RESERVED1[13];
792  __IO uint32_t FIFO;
793 } SDIO_TypeDef;
794 
799 typedef struct
800 {
801  __IO uint32_t CR1;
802  __IO uint32_t CR2;
803  __IO uint32_t SR;
804  __IO uint32_t DR;
805  __IO uint32_t CRCPR;
806  __IO uint32_t RXCRCR;
807  __IO uint32_t TXCRCR;
808  __IO uint32_t I2SCFGR;
809  __IO uint32_t I2SPR;
810 } SPI_TypeDef;
811 
816 typedef struct
817 {
818  __IO uint32_t CR1;
819  __IO uint32_t CR2;
820  __IO uint32_t SMCR;
821  __IO uint32_t DIER;
822  __IO uint32_t SR;
823  __IO uint32_t EGR;
824  __IO uint32_t CCMR1;
825  __IO uint32_t CCMR2;
826  __IO uint32_t CCER;
827  __IO uint32_t CNT;
828  __IO uint32_t PSC;
829  __IO uint32_t ARR;
830  __IO uint32_t RCR;
831  __IO uint32_t CCR1;
832  __IO uint32_t CCR2;
833  __IO uint32_t CCR3;
834  __IO uint32_t CCR4;
835  __IO uint32_t BDTR;
836  __IO uint32_t DCR;
837  __IO uint32_t DMAR;
838  __IO uint32_t OR;
839 } TIM_TypeDef;
840 
845 typedef struct
846 {
847  __IO uint32_t SR;
848  __IO uint32_t DR;
849  __IO uint32_t BRR;
850  __IO uint32_t CR1;
851  __IO uint32_t CR2;
852  __IO uint32_t CR3;
853  __IO uint32_t GTPR;
854 } USART_TypeDef;
855 
860 typedef struct
861 {
862  __IO uint32_t CR;
863  __IO uint32_t CFR;
864  __IO uint32_t SR;
865 } WWDG_TypeDef;
866 
867 
872 typedef struct
873 {
874  __IO uint32_t CR;
875  __IO uint32_t SR;
876  __IO uint32_t DR;
877 } RNG_TypeDef;
878 
879 
883 typedef struct
884 {
885  __IO uint32_t GOTGCTL;
886  __IO uint32_t GOTGINT;
887  __IO uint32_t GAHBCFG;
888  __IO uint32_t GUSBCFG;
889  __IO uint32_t GRSTCTL;
890  __IO uint32_t GINTSTS;
891  __IO uint32_t GINTMSK;
892  __IO uint32_t GRXSTSR;
893  __IO uint32_t GRXSTSP;
894  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
895  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
896  __IO uint32_t HNPTXSTS;
897  uint32_t Reserved30[2]; /* Reserved 030h*/
898  __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
899  __IO uint32_t CID; /* User ID Register 03Ch*/
900  uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
901  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
902  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
903 }
904 USB_OTG_GlobalTypeDef;
905 
906 
910 typedef struct
911 {
912  __IO uint32_t DCFG; /* dev Configuration Register 800h*/
913  __IO uint32_t DCTL; /* dev Control Register 804h*/
914  __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
915  uint32_t Reserved0C; /* Reserved 80Ch*/
916  __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
917  __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
918  __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
919  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
920  uint32_t Reserved20; /* Reserved 820h*/
921  uint32_t Reserved9; /* Reserved 824h*/
922  __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
923  __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
924  __IO uint32_t DTHRCTL; /* dev thr 830h*/
925  __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
926  __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
927  __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
928  uint32_t Reserved40; /* dedicated EP mask 840h*/
929  __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
930  uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
931  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
932 }
933 USB_OTG_DeviceTypeDef;
934 
935 
939 typedef struct
940 {
941  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
942  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
943  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
944  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
945  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
946  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
947  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
948  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
949 }
950 USB_OTG_INEndpointTypeDef;
951 
952 
956 typedef struct
957 {
958  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
959  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
960  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
961  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
962  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
963  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
964  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
965 }
966 USB_OTG_OUTEndpointTypeDef;
967 
968 
972 typedef struct
973 {
974  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
975  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
976  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
977  uint32_t Reserved40C; /* Reserved 40Ch*/
978  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
979  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
980  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
981 }
982 USB_OTG_HostTypeDef;
983 
987 typedef struct
988 {
989  __IO uint32_t HCCHAR;
990  __IO uint32_t HCSPLT;
991  __IO uint32_t HCINT;
992  __IO uint32_t HCINTMSK;
993  __IO uint32_t HCTSIZ;
994  __IO uint32_t HCDMA;
995  uint32_t Reserved[2];
996 }
997 USB_OTG_HostChannelTypeDef;
1005 #define FLASH_BASE 0x08000000U
1006 #define CCMDATARAM_BASE 0x10000000U
1007 #define SRAM1_BASE 0x20000000U
1008 #define SRAM2_BASE 0x2001C000U
1009 #define PERIPH_BASE 0x40000000U
1010 #define BKPSRAM_BASE 0x40024000U
1011 #define FMC_R_BASE 0xA0000000U
1012 #define SRAM1_BB_BASE 0x22000000U
1013 #define SRAM2_BB_BASE 0x22380000U
1014 #define PERIPH_BB_BASE 0x42000000U
1015 #define BKPSRAM_BB_BASE 0x42480000U
1016 #define FLASH_END 0x081FFFFFU
1017 #define CCMDATARAM_END 0x1000FFFFU
1019 /* Legacy defines */
1020 #define SRAM_BASE SRAM1_BASE
1021 #define SRAM_BB_BASE SRAM1_BB_BASE
1022 
1023 
1025 #define APB1PERIPH_BASE PERIPH_BASE
1026 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1027 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1028 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1029 
1031 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1032 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1033 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1034 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1035 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1036 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1037 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1038 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1039 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1040 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1041 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1042 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1043 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1044 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1045 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1046 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1047 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1048 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1049 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1050 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1051 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1052 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1053 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1054 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1055 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1056 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1057 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1058 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1059 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1060 
1062 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1063 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1064 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1065 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1066 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1067 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1068 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1069 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1070 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1071 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1072 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1073 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1074 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1075 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1076 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1077 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1078 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1079 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1080 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1081 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1082 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1083 
1085 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1086 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1087 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1088 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1089 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1090 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1091 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1092 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1093 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1094 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1095 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1096 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1097 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1098 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1099 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1100 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1101 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1102 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1103 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1104 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1105 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1106 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1107 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1108 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1109 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1110 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1111 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1112 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1113 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1114 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1115 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1116 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1117 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1118 #define ETH_MAC_BASE (ETH_BASE)
1119 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1120 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1121 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1122 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1123 
1125 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1126 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1127 
1129 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1130 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1131 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
1132 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
1133 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1134 
1135 /* Debug MCU registers base address */
1136 #define DBGMCU_BASE 0xE0042000U
1137 
1139 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1140 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1141 
1142 #define USB_OTG_GLOBAL_BASE 0x000U
1143 #define USB_OTG_DEVICE_BASE 0x800U
1144 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1145 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1146 #define USB_OTG_EP_REG_SIZE 0x20U
1147 #define USB_OTG_HOST_BASE 0x400U
1148 #define USB_OTG_HOST_PORT_BASE 0x440U
1149 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1150 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1151 #define USB_OTG_PCGCCTL_BASE 0xE00U
1152 #define USB_OTG_FIFO_BASE 0x1000U
1153 #define USB_OTG_FIFO_SIZE 0x1000U
1154 
1162 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1163 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1164 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1165 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1166 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1167 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1168 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1169 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1170 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1171 #define RTC ((RTC_TypeDef *) RTC_BASE)
1172 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1173 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1174 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1175 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1176 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1177 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1178 #define USART2 ((USART_TypeDef *) USART2_BASE)
1179 #define USART3 ((USART_TypeDef *) USART3_BASE)
1180 #define UART4 ((USART_TypeDef *) UART4_BASE)
1181 #define UART5 ((USART_TypeDef *) UART5_BASE)
1182 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1183 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1184 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1185 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1186 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1187 #define PWR ((PWR_TypeDef *) PWR_BASE)
1188 #define DAC ((DAC_TypeDef *) DAC_BASE)
1189 #define UART7 ((USART_TypeDef *) UART7_BASE)
1190 #define UART8 ((USART_TypeDef *) UART8_BASE)
1191 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1192 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1193 #define USART1 ((USART_TypeDef *) USART1_BASE)
1194 #define USART6 ((USART_TypeDef *) USART6_BASE)
1195 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1196 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1197 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1198 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1199 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1200 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1201 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1202 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1203 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1204 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1205 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1206 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1207 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1208 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1209 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1210 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1211 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1212 
1213 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1214 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1215 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1216 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1217 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1218 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1219 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1220 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1221 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1222 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1223 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1224 #define CRC ((CRC_TypeDef *) CRC_BASE)
1225 #define RCC ((RCC_TypeDef *) RCC_BASE)
1226 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1227 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1228 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1229 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1230 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1231 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1232 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1233 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1234 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1235 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1236 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1237 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1238 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1239 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1240 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1241 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1242 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1243 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1244 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1245 #define ETH ((ETH_TypeDef *) ETH_BASE)
1246 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1247 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1248 #define RNG ((RNG_TypeDef *) RNG_BASE)
1249 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1250 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1251 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1252 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1253 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1254 
1255 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1256 
1257 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1258 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1259 
1272 /******************************************************************************/
1273 /* Peripheral Registers_Bits_Definition */
1274 /******************************************************************************/
1275 
1276 /******************************************************************************/
1277 /* */
1278 /* Analog to Digital Converter */
1279 /* */
1280 /******************************************************************************/
1281 /******************** Bit definition for ADC_SR register ********************/
1282 #define ADC_SR_AWD 0x00000001U
1283 #define ADC_SR_EOC 0x00000002U
1284 #define ADC_SR_JEOC 0x00000004U
1285 #define ADC_SR_JSTRT 0x00000008U
1286 #define ADC_SR_STRT 0x00000010U
1287 #define ADC_SR_OVR 0x00000020U
1289 /******************* Bit definition for ADC_CR1 register ********************/
1290 #define ADC_CR1_AWDCH 0x0000001FU
1291 #define ADC_CR1_AWDCH_0 0x00000001U
1292 #define ADC_CR1_AWDCH_1 0x00000002U
1293 #define ADC_CR1_AWDCH_2 0x00000004U
1294 #define ADC_CR1_AWDCH_3 0x00000008U
1295 #define ADC_CR1_AWDCH_4 0x00000010U
1296 #define ADC_CR1_EOCIE 0x00000020U
1297 #define ADC_CR1_AWDIE 0x00000040U
1298 #define ADC_CR1_JEOCIE 0x00000080U
1299 #define ADC_CR1_SCAN 0x00000100U
1300 #define ADC_CR1_AWDSGL 0x00000200U
1301 #define ADC_CR1_JAUTO 0x00000400U
1302 #define ADC_CR1_DISCEN 0x00000800U
1303 #define ADC_CR1_JDISCEN 0x00001000U
1304 #define ADC_CR1_DISCNUM 0x0000E000U
1305 #define ADC_CR1_DISCNUM_0 0x00002000U
1306 #define ADC_CR1_DISCNUM_1 0x00004000U
1307 #define ADC_CR1_DISCNUM_2 0x00008000U
1308 #define ADC_CR1_JAWDEN 0x00400000U
1309 #define ADC_CR1_AWDEN 0x00800000U
1310 #define ADC_CR1_RES 0x03000000U
1311 #define ADC_CR1_RES_0 0x01000000U
1312 #define ADC_CR1_RES_1 0x02000000U
1313 #define ADC_CR1_OVRIE 0x04000000U
1315 /******************* Bit definition for ADC_CR2 register ********************/
1316 #define ADC_CR2_ADON 0x00000001U
1317 #define ADC_CR2_CONT 0x00000002U
1318 #define ADC_CR2_DMA 0x00000100U
1319 #define ADC_CR2_DDS 0x00000200U
1320 #define ADC_CR2_EOCS 0x00000400U
1321 #define ADC_CR2_ALIGN 0x00000800U
1322 #define ADC_CR2_JEXTSEL 0x000F0000U
1323 #define ADC_CR2_JEXTSEL_0 0x00010000U
1324 #define ADC_CR2_JEXTSEL_1 0x00020000U
1325 #define ADC_CR2_JEXTSEL_2 0x00040000U
1326 #define ADC_CR2_JEXTSEL_3 0x00080000U
1327 #define ADC_CR2_JEXTEN 0x00300000U
1328 #define ADC_CR2_JEXTEN_0 0x00100000U
1329 #define ADC_CR2_JEXTEN_1 0x00200000U
1330 #define ADC_CR2_JSWSTART 0x00400000U
1331 #define ADC_CR2_EXTSEL 0x0F000000U
1332 #define ADC_CR2_EXTSEL_0 0x01000000U
1333 #define ADC_CR2_EXTSEL_1 0x02000000U
1334 #define ADC_CR2_EXTSEL_2 0x04000000U
1335 #define ADC_CR2_EXTSEL_3 0x08000000U
1336 #define ADC_CR2_EXTEN 0x30000000U
1337 #define ADC_CR2_EXTEN_0 0x10000000U
1338 #define ADC_CR2_EXTEN_1 0x20000000U
1339 #define ADC_CR2_SWSTART 0x40000000U
1341 /****************** Bit definition for ADC_SMPR1 register *******************/
1342 #define ADC_SMPR1_SMP10 0x00000007U
1343 #define ADC_SMPR1_SMP10_0 0x00000001U
1344 #define ADC_SMPR1_SMP10_1 0x00000002U
1345 #define ADC_SMPR1_SMP10_2 0x00000004U
1346 #define ADC_SMPR1_SMP11 0x00000038U
1347 #define ADC_SMPR1_SMP11_0 0x00000008U
1348 #define ADC_SMPR1_SMP11_1 0x00000010U
1349 #define ADC_SMPR1_SMP11_2 0x00000020U
1350 #define ADC_SMPR1_SMP12 0x000001C0U
1351 #define ADC_SMPR1_SMP12_0 0x00000040U
1352 #define ADC_SMPR1_SMP12_1 0x00000080U
1353 #define ADC_SMPR1_SMP12_2 0x00000100U
1354 #define ADC_SMPR1_SMP13 0x00000E00U
1355 #define ADC_SMPR1_SMP13_0 0x00000200U
1356 #define ADC_SMPR1_SMP13_1 0x00000400U
1357 #define ADC_SMPR1_SMP13_2 0x00000800U
1358 #define ADC_SMPR1_SMP14 0x00007000U
1359 #define ADC_SMPR1_SMP14_0 0x00001000U
1360 #define ADC_SMPR1_SMP14_1 0x00002000U
1361 #define ADC_SMPR1_SMP14_2 0x00004000U
1362 #define ADC_SMPR1_SMP15 0x00038000U
1363 #define ADC_SMPR1_SMP15_0 0x00008000U
1364 #define ADC_SMPR1_SMP15_1 0x00010000U
1365 #define ADC_SMPR1_SMP15_2 0x00020000U
1366 #define ADC_SMPR1_SMP16 0x001C0000U
1367 #define ADC_SMPR1_SMP16_0 0x00040000U
1368 #define ADC_SMPR1_SMP16_1 0x00080000U
1369 #define ADC_SMPR1_SMP16_2 0x00100000U
1370 #define ADC_SMPR1_SMP17 0x00E00000U
1371 #define ADC_SMPR1_SMP17_0 0x00200000U
1372 #define ADC_SMPR1_SMP17_1 0x00400000U
1373 #define ADC_SMPR1_SMP17_2 0x00800000U
1374 #define ADC_SMPR1_SMP18 0x07000000U
1375 #define ADC_SMPR1_SMP18_0 0x01000000U
1376 #define ADC_SMPR1_SMP18_1 0x02000000U
1377 #define ADC_SMPR1_SMP18_2 0x04000000U
1379 /****************** Bit definition for ADC_SMPR2 register *******************/
1380 #define ADC_SMPR2_SMP0 0x00000007U
1381 #define ADC_SMPR2_SMP0_0 0x00000001U
1382 #define ADC_SMPR2_SMP0_1 0x00000002U
1383 #define ADC_SMPR2_SMP0_2 0x00000004U
1384 #define ADC_SMPR2_SMP1 0x00000038U
1385 #define ADC_SMPR2_SMP1_0 0x00000008U
1386 #define ADC_SMPR2_SMP1_1 0x00000010U
1387 #define ADC_SMPR2_SMP1_2 0x00000020U
1388 #define ADC_SMPR2_SMP2 0x000001C0U
1389 #define ADC_SMPR2_SMP2_0 0x00000040U
1390 #define ADC_SMPR2_SMP2_1 0x00000080U
1391 #define ADC_SMPR2_SMP2_2 0x00000100U
1392 #define ADC_SMPR2_SMP3 0x00000E00U
1393 #define ADC_SMPR2_SMP3_0 0x00000200U
1394 #define ADC_SMPR2_SMP3_1 0x00000400U
1395 #define ADC_SMPR2_SMP3_2 0x00000800U
1396 #define ADC_SMPR2_SMP4 0x00007000U
1397 #define ADC_SMPR2_SMP4_0 0x00001000U
1398 #define ADC_SMPR2_SMP4_1 0x00002000U
1399 #define ADC_SMPR2_SMP4_2 0x00004000U
1400 #define ADC_SMPR2_SMP5 0x00038000U
1401 #define ADC_SMPR2_SMP5_0 0x00008000U
1402 #define ADC_SMPR2_SMP5_1 0x00010000U
1403 #define ADC_SMPR2_SMP5_2 0x00020000U
1404 #define ADC_SMPR2_SMP6 0x001C0000U
1405 #define ADC_SMPR2_SMP6_0 0x00040000U
1406 #define ADC_SMPR2_SMP6_1 0x00080000U
1407 #define ADC_SMPR2_SMP6_2 0x00100000U
1408 #define ADC_SMPR2_SMP7 0x00E00000U
1409 #define ADC_SMPR2_SMP7_0 0x00200000U
1410 #define ADC_SMPR2_SMP7_1 0x00400000U
1411 #define ADC_SMPR2_SMP7_2 0x00800000U
1412 #define ADC_SMPR2_SMP8 0x07000000U
1413 #define ADC_SMPR2_SMP8_0 0x01000000U
1414 #define ADC_SMPR2_SMP8_1 0x02000000U
1415 #define ADC_SMPR2_SMP8_2 0x04000000U
1416 #define ADC_SMPR2_SMP9 0x38000000U
1417 #define ADC_SMPR2_SMP9_0 0x08000000U
1418 #define ADC_SMPR2_SMP9_1 0x10000000U
1419 #define ADC_SMPR2_SMP9_2 0x20000000U
1421 /****************** Bit definition for ADC_JOFR1 register *******************/
1422 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1424 /****************** Bit definition for ADC_JOFR2 register *******************/
1425 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1427 /****************** Bit definition for ADC_JOFR3 register *******************/
1428 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1430 /****************** Bit definition for ADC_JOFR4 register *******************/
1431 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1433 /******************* Bit definition for ADC_HTR register ********************/
1434 #define ADC_HTR_HT 0x0FFFU
1436 /******************* Bit definition for ADC_LTR register ********************/
1437 #define ADC_LTR_LT 0x0FFFU
1439 /******************* Bit definition for ADC_SQR1 register *******************/
1440 #define ADC_SQR1_SQ13 0x0000001FU
1441 #define ADC_SQR1_SQ13_0 0x00000001U
1442 #define ADC_SQR1_SQ13_1 0x00000002U
1443 #define ADC_SQR1_SQ13_2 0x00000004U
1444 #define ADC_SQR1_SQ13_3 0x00000008U
1445 #define ADC_SQR1_SQ13_4 0x00000010U
1446 #define ADC_SQR1_SQ14 0x000003E0U
1447 #define ADC_SQR1_SQ14_0 0x00000020U
1448 #define ADC_SQR1_SQ14_1 0x00000040U
1449 #define ADC_SQR1_SQ14_2 0x00000080U
1450 #define ADC_SQR1_SQ14_3 0x00000100U
1451 #define ADC_SQR1_SQ14_4 0x00000200U
1452 #define ADC_SQR1_SQ15 0x00007C00U
1453 #define ADC_SQR1_SQ15_0 0x00000400U
1454 #define ADC_SQR1_SQ15_1 0x00000800U
1455 #define ADC_SQR1_SQ15_2 0x00001000U
1456 #define ADC_SQR1_SQ15_3 0x00002000U
1457 #define ADC_SQR1_SQ15_4 0x00004000U
1458 #define ADC_SQR1_SQ16 0x000F8000U
1459 #define ADC_SQR1_SQ16_0 0x00008000U
1460 #define ADC_SQR1_SQ16_1 0x00010000U
1461 #define ADC_SQR1_SQ16_2 0x00020000U
1462 #define ADC_SQR1_SQ16_3 0x00040000U
1463 #define ADC_SQR1_SQ16_4 0x00080000U
1464 #define ADC_SQR1_L 0x00F00000U
1465 #define ADC_SQR1_L_0 0x00100000U
1466 #define ADC_SQR1_L_1 0x00200000U
1467 #define ADC_SQR1_L_2 0x00400000U
1468 #define ADC_SQR1_L_3 0x00800000U
1470 /******************* Bit definition for ADC_SQR2 register *******************/
1471 #define ADC_SQR2_SQ7 0x0000001FU
1472 #define ADC_SQR2_SQ7_0 0x00000001U
1473 #define ADC_SQR2_SQ7_1 0x00000002U
1474 #define ADC_SQR2_SQ7_2 0x00000004U
1475 #define ADC_SQR2_SQ7_3 0x00000008U
1476 #define ADC_SQR2_SQ7_4 0x00000010U
1477 #define ADC_SQR2_SQ8 0x000003E0U
1478 #define ADC_SQR2_SQ8_0 0x00000020U
1479 #define ADC_SQR2_SQ8_1 0x00000040U
1480 #define ADC_SQR2_SQ8_2 0x00000080U
1481 #define ADC_SQR2_SQ8_3 0x00000100U
1482 #define ADC_SQR2_SQ8_4 0x00000200U
1483 #define ADC_SQR2_SQ9 0x00007C00U
1484 #define ADC_SQR2_SQ9_0 0x00000400U
1485 #define ADC_SQR2_SQ9_1 0x00000800U
1486 #define ADC_SQR2_SQ9_2 0x00001000U
1487 #define ADC_SQR2_SQ9_3 0x00002000U
1488 #define ADC_SQR2_SQ9_4 0x00004000U
1489 #define ADC_SQR2_SQ10 0x000F8000U
1490 #define ADC_SQR2_SQ10_0 0x00008000U
1491 #define ADC_SQR2_SQ10_1 0x00010000U
1492 #define ADC_SQR2_SQ10_2 0x00020000U
1493 #define ADC_SQR2_SQ10_3 0x00040000U
1494 #define ADC_SQR2_SQ10_4 0x00080000U
1495 #define ADC_SQR2_SQ11 0x01F00000U
1496 #define ADC_SQR2_SQ11_0 0x00100000U
1497 #define ADC_SQR2_SQ11_1 0x00200000U
1498 #define ADC_SQR2_SQ11_2 0x00400000U
1499 #define ADC_SQR2_SQ11_3 0x00800000U
1500 #define ADC_SQR2_SQ11_4 0x01000000U
1501 #define ADC_SQR2_SQ12 0x3E000000U
1502 #define ADC_SQR2_SQ12_0 0x02000000U
1503 #define ADC_SQR2_SQ12_1 0x04000000U
1504 #define ADC_SQR2_SQ12_2 0x08000000U
1505 #define ADC_SQR2_SQ12_3 0x10000000U
1506 #define ADC_SQR2_SQ12_4 0x20000000U
1508 /******************* Bit definition for ADC_SQR3 register *******************/
1509 #define ADC_SQR3_SQ1 0x0000001FU
1510 #define ADC_SQR3_SQ1_0 0x00000001U
1511 #define ADC_SQR3_SQ1_1 0x00000002U
1512 #define ADC_SQR3_SQ1_2 0x00000004U
1513 #define ADC_SQR3_SQ1_3 0x00000008U
1514 #define ADC_SQR3_SQ1_4 0x00000010U
1515 #define ADC_SQR3_SQ2 0x000003E0U
1516 #define ADC_SQR3_SQ2_0 0x00000020U
1517 #define ADC_SQR3_SQ2_1 0x00000040U
1518 #define ADC_SQR3_SQ2_2 0x00000080U
1519 #define ADC_SQR3_SQ2_3 0x00000100U
1520 #define ADC_SQR3_SQ2_4 0x00000200U
1521 #define ADC_SQR3_SQ3 0x00007C00U
1522 #define ADC_SQR3_SQ3_0 0x00000400U
1523 #define ADC_SQR3_SQ3_1 0x00000800U
1524 #define ADC_SQR3_SQ3_2 0x00001000U
1525 #define ADC_SQR3_SQ3_3 0x00002000U
1526 #define ADC_SQR3_SQ3_4 0x00004000U
1527 #define ADC_SQR3_SQ4 0x000F8000U
1528 #define ADC_SQR3_SQ4_0 0x00008000U
1529 #define ADC_SQR3_SQ4_1 0x00010000U
1530 #define ADC_SQR3_SQ4_2 0x00020000U
1531 #define ADC_SQR3_SQ4_3 0x00040000U
1532 #define ADC_SQR3_SQ4_4 0x00080000U
1533 #define ADC_SQR3_SQ5 0x01F00000U
1534 #define ADC_SQR3_SQ5_0 0x00100000U
1535 #define ADC_SQR3_SQ5_1 0x00200000U
1536 #define ADC_SQR3_SQ5_2 0x00400000U
1537 #define ADC_SQR3_SQ5_3 0x00800000U
1538 #define ADC_SQR3_SQ5_4 0x01000000U
1539 #define ADC_SQR3_SQ6 0x3E000000U
1540 #define ADC_SQR3_SQ6_0 0x02000000U
1541 #define ADC_SQR3_SQ6_1 0x04000000U
1542 #define ADC_SQR3_SQ6_2 0x08000000U
1543 #define ADC_SQR3_SQ6_3 0x10000000U
1544 #define ADC_SQR3_SQ6_4 0x20000000U
1546 /******************* Bit definition for ADC_JSQR register *******************/
1547 #define ADC_JSQR_JSQ1 0x0000001FU
1548 #define ADC_JSQR_JSQ1_0 0x00000001U
1549 #define ADC_JSQR_JSQ1_1 0x00000002U
1550 #define ADC_JSQR_JSQ1_2 0x00000004U
1551 #define ADC_JSQR_JSQ1_3 0x00000008U
1552 #define ADC_JSQR_JSQ1_4 0x00000010U
1553 #define ADC_JSQR_JSQ2 0x000003E0U
1554 #define ADC_JSQR_JSQ2_0 0x00000020U
1555 #define ADC_JSQR_JSQ2_1 0x00000040U
1556 #define ADC_JSQR_JSQ2_2 0x00000080U
1557 #define ADC_JSQR_JSQ2_3 0x00000100U
1558 #define ADC_JSQR_JSQ2_4 0x00000200U
1559 #define ADC_JSQR_JSQ3 0x00007C00U
1560 #define ADC_JSQR_JSQ3_0 0x00000400U
1561 #define ADC_JSQR_JSQ3_1 0x00000800U
1562 #define ADC_JSQR_JSQ3_2 0x00001000U
1563 #define ADC_JSQR_JSQ3_3 0x00002000U
1564 #define ADC_JSQR_JSQ3_4 0x00004000U
1565 #define ADC_JSQR_JSQ4 0x000F8000U
1566 #define ADC_JSQR_JSQ4_0 0x00008000U
1567 #define ADC_JSQR_JSQ4_1 0x00010000U
1568 #define ADC_JSQR_JSQ4_2 0x00020000U
1569 #define ADC_JSQR_JSQ4_3 0x00040000U
1570 #define ADC_JSQR_JSQ4_4 0x00080000U
1571 #define ADC_JSQR_JL 0x00300000U
1572 #define ADC_JSQR_JL_0 0x00100000U
1573 #define ADC_JSQR_JL_1 0x00200000U
1575 /******************* Bit definition for ADC_JDR1 register *******************/
1576 #define ADC_JDR1_JDATA 0xFFFFU
1578 /******************* Bit definition for ADC_JDR2 register *******************/
1579 #define ADC_JDR2_JDATA 0xFFFFU
1581 /******************* Bit definition for ADC_JDR3 register *******************/
1582 #define ADC_JDR3_JDATA 0xFFFFU
1584 /******************* Bit definition for ADC_JDR4 register *******************/
1585 #define ADC_JDR4_JDATA 0xFFFFU
1587 /******************** Bit definition for ADC_DR register ********************/
1588 #define ADC_DR_DATA 0x0000FFFFU
1589 #define ADC_DR_ADC2DATA 0xFFFF0000U
1591 /******************* Bit definition for ADC_CSR register ********************/
1592 #define ADC_CSR_AWD1 0x00000001U
1593 #define ADC_CSR_EOC1 0x00000002U
1594 #define ADC_CSR_JEOC1 0x00000004U
1595 #define ADC_CSR_JSTRT1 0x00000008U
1596 #define ADC_CSR_STRT1 0x00000010U
1597 #define ADC_CSR_OVR1 0x00000020U
1598 #define ADC_CSR_AWD2 0x00000100U
1599 #define ADC_CSR_EOC2 0x00000200U
1600 #define ADC_CSR_JEOC2 0x00000400U
1601 #define ADC_CSR_JSTRT2 0x00000800U
1602 #define ADC_CSR_STRT2 0x00001000U
1603 #define ADC_CSR_OVR2 0x00002000U
1604 #define ADC_CSR_AWD3 0x00010000U
1605 #define ADC_CSR_EOC3 0x00020000U
1606 #define ADC_CSR_JEOC3 0x00040000U
1607 #define ADC_CSR_JSTRT3 0x00080000U
1608 #define ADC_CSR_STRT3 0x00100000U
1609 #define ADC_CSR_OVR3 0x00200000U
1611 /* Legacy defines */
1612 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1613 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1614 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1615 
1616 /******************* Bit definition for ADC_CCR register ********************/
1617 #define ADC_CCR_MULTI 0x0000001FU
1618 #define ADC_CCR_MULTI_0 0x00000001U
1619 #define ADC_CCR_MULTI_1 0x00000002U
1620 #define ADC_CCR_MULTI_2 0x00000004U
1621 #define ADC_CCR_MULTI_3 0x00000008U
1622 #define ADC_CCR_MULTI_4 0x00000010U
1623 #define ADC_CCR_DELAY 0x00000F00U
1624 #define ADC_CCR_DELAY_0 0x00000100U
1625 #define ADC_CCR_DELAY_1 0x00000200U
1626 #define ADC_CCR_DELAY_2 0x00000400U
1627 #define ADC_CCR_DELAY_3 0x00000800U
1628 #define ADC_CCR_DDS 0x00002000U
1629 #define ADC_CCR_DMA 0x0000C000U
1630 #define ADC_CCR_DMA_0 0x00004000U
1631 #define ADC_CCR_DMA_1 0x00008000U
1632 #define ADC_CCR_ADCPRE 0x00030000U
1633 #define ADC_CCR_ADCPRE_0 0x00010000U
1634 #define ADC_CCR_ADCPRE_1 0x00020000U
1635 #define ADC_CCR_VBATE 0x00400000U
1636 #define ADC_CCR_TSVREFE 0x00800000U
1638 /******************* Bit definition for ADC_CDR register ********************/
1639 #define ADC_CDR_DATA1 0x0000FFFFU
1640 #define ADC_CDR_DATA2 0xFFFF0000U
1642 /******************************************************************************/
1643 /* */
1644 /* Controller Area Network */
1645 /* */
1646 /******************************************************************************/
1648 /******************* Bit definition for CAN_MCR register ********************/
1649 #define CAN_MCR_INRQ 0x00000001U
1650 #define CAN_MCR_SLEEP 0x00000002U
1651 #define CAN_MCR_TXFP 0x00000004U
1652 #define CAN_MCR_RFLM 0x00000008U
1653 #define CAN_MCR_NART 0x00000010U
1654 #define CAN_MCR_AWUM 0x00000020U
1655 #define CAN_MCR_ABOM 0x00000040U
1656 #define CAN_MCR_TTCM 0x00000080U
1657 #define CAN_MCR_RESET 0x00008000U
1658 #define CAN_MCR_DBF 0x00010000U
1659 /******************* Bit definition for CAN_MSR register ********************/
1660 #define CAN_MSR_INAK 0x0001U
1661 #define CAN_MSR_SLAK 0x0002U
1662 #define CAN_MSR_ERRI 0x0004U
1663 #define CAN_MSR_WKUI 0x0008U
1664 #define CAN_MSR_SLAKI 0x0010U
1665 #define CAN_MSR_TXM 0x0100U
1666 #define CAN_MSR_RXM 0x0200U
1667 #define CAN_MSR_SAMP 0x0400U
1668 #define CAN_MSR_RX 0x0800U
1670 /******************* Bit definition for CAN_TSR register ********************/
1671 #define CAN_TSR_RQCP0 0x00000001U
1672 #define CAN_TSR_TXOK0 0x00000002U
1673 #define CAN_TSR_ALST0 0x00000004U
1674 #define CAN_TSR_TERR0 0x00000008U
1675 #define CAN_TSR_ABRQ0 0x00000080U
1676 #define CAN_TSR_RQCP1 0x00000100U
1677 #define CAN_TSR_TXOK1 0x00000200U
1678 #define CAN_TSR_ALST1 0x00000400U
1679 #define CAN_TSR_TERR1 0x00000800U
1680 #define CAN_TSR_ABRQ1 0x00008000U
1681 #define CAN_TSR_RQCP2 0x00010000U
1682 #define CAN_TSR_TXOK2 0x00020000U
1683 #define CAN_TSR_ALST2 0x00040000U
1684 #define CAN_TSR_TERR2 0x00080000U
1685 #define CAN_TSR_ABRQ2 0x00800000U
1686 #define CAN_TSR_CODE 0x03000000U
1688 #define CAN_TSR_TME 0x1C000000U
1689 #define CAN_TSR_TME0 0x04000000U
1690 #define CAN_TSR_TME1 0x08000000U
1691 #define CAN_TSR_TME2 0x10000000U
1693 #define CAN_TSR_LOW 0xE0000000U
1694 #define CAN_TSR_LOW0 0x20000000U
1695 #define CAN_TSR_LOW1 0x40000000U
1696 #define CAN_TSR_LOW2 0x80000000U
1698 /******************* Bit definition for CAN_RF0R register *******************/
1699 #define CAN_RF0R_FMP0 0x03U
1700 #define CAN_RF0R_FULL0 0x08U
1701 #define CAN_RF0R_FOVR0 0x10U
1702 #define CAN_RF0R_RFOM0 0x20U
1704 /******************* Bit definition for CAN_RF1R register *******************/
1705 #define CAN_RF1R_FMP1 0x03U
1706 #define CAN_RF1R_FULL1 0x08U
1707 #define CAN_RF1R_FOVR1 0x10U
1708 #define CAN_RF1R_RFOM1 0x20U
1710 /******************** Bit definition for CAN_IER register *******************/
1711 #define CAN_IER_TMEIE 0x00000001U
1712 #define CAN_IER_FMPIE0 0x00000002U
1713 #define CAN_IER_FFIE0 0x00000004U
1714 #define CAN_IER_FOVIE0 0x00000008U
1715 #define CAN_IER_FMPIE1 0x00000010U
1716 #define CAN_IER_FFIE1 0x00000020U
1717 #define CAN_IER_FOVIE1 0x00000040U
1718 #define CAN_IER_EWGIE 0x00000100U
1719 #define CAN_IER_EPVIE 0x00000200U
1720 #define CAN_IER_BOFIE 0x00000400U
1721 #define CAN_IER_LECIE 0x00000800U
1722 #define CAN_IER_ERRIE 0x00008000U
1723 #define CAN_IER_WKUIE 0x00010000U
1724 #define CAN_IER_SLKIE 0x00020000U
1725 #define CAN_IER_EWGIE 0x00000100U
1726 #define CAN_IER_EPVIE 0x00000200U
1727 #define CAN_IER_BOFIE 0x00000400U
1728 #define CAN_IER_LECIE 0x00000800U
1729 #define CAN_IER_ERRIE 0x00008000U
1732 /******************** Bit definition for CAN_ESR register *******************/
1733 #define CAN_ESR_EWGF 0x00000001U
1734 #define CAN_ESR_EPVF 0x00000002U
1735 #define CAN_ESR_BOFF 0x00000004U
1737 #define CAN_ESR_LEC 0x00000070U
1738 #define CAN_ESR_LEC_0 0x00000010U
1739 #define CAN_ESR_LEC_1 0x00000020U
1740 #define CAN_ESR_LEC_2 0x00000040U
1742 #define CAN_ESR_TEC 0x00FF0000U
1743 #define CAN_ESR_REC 0xFF000000U
1745 /******************* Bit definition for CAN_BTR register ********************/
1746 #define CAN_BTR_BRP 0x000003FFU
1747 #define CAN_BTR_TS1 0x000F0000U
1748 #define CAN_BTR_TS1_0 0x00010000U
1749 #define CAN_BTR_TS1_1 0x00020000U
1750 #define CAN_BTR_TS1_2 0x00040000U
1751 #define CAN_BTR_TS1_3 0x00080000U
1752 #define CAN_BTR_TS2 0x00700000U
1753 #define CAN_BTR_TS2_0 0x00100000U
1754 #define CAN_BTR_TS2_1 0x00200000U
1755 #define CAN_BTR_TS2_2 0x00400000U
1756 #define CAN_BTR_SJW 0x03000000U
1757 #define CAN_BTR_SJW_0 0x01000000U
1758 #define CAN_BTR_SJW_1 0x02000000U
1759 #define CAN_BTR_LBKM 0x40000000U
1760 #define CAN_BTR_SILM 0x80000000U
1764 /****************** Bit definition for CAN_TI0R register ********************/
1765 #define CAN_TI0R_TXRQ 0x00000001U
1766 #define CAN_TI0R_RTR 0x00000002U
1767 #define CAN_TI0R_IDE 0x00000004U
1768 #define CAN_TI0R_EXID 0x001FFFF8U
1769 #define CAN_TI0R_STID 0xFFE00000U
1771 /****************** Bit definition for CAN_TDT0R register *******************/
1772 #define CAN_TDT0R_DLC 0x0000000FU
1773 #define CAN_TDT0R_TGT 0x00000100U
1774 #define CAN_TDT0R_TIME 0xFFFF0000U
1776 /****************** Bit definition for CAN_TDL0R register *******************/
1777 #define CAN_TDL0R_DATA0 0x000000FFU
1778 #define CAN_TDL0R_DATA1 0x0000FF00U
1779 #define CAN_TDL0R_DATA2 0x00FF0000U
1780 #define CAN_TDL0R_DATA3 0xFF000000U
1782 /****************** Bit definition for CAN_TDH0R register *******************/
1783 #define CAN_TDH0R_DATA4 0x000000FFU
1784 #define CAN_TDH0R_DATA5 0x0000FF00U
1785 #define CAN_TDH0R_DATA6 0x00FF0000U
1786 #define CAN_TDH0R_DATA7 0xFF000000U
1788 /******************* Bit definition for CAN_TI1R register *******************/
1789 #define CAN_TI1R_TXRQ 0x00000001U
1790 #define CAN_TI1R_RTR 0x00000002U
1791 #define CAN_TI1R_IDE 0x00000004U
1792 #define CAN_TI1R_EXID 0x001FFFF8U
1793 #define CAN_TI1R_STID 0xFFE00000U
1795 /******************* Bit definition for CAN_TDT1R register ******************/
1796 #define CAN_TDT1R_DLC 0x0000000FU
1797 #define CAN_TDT1R_TGT 0x00000100U
1798 #define CAN_TDT1R_TIME 0xFFFF0000U
1800 /******************* Bit definition for CAN_TDL1R register ******************/
1801 #define CAN_TDL1R_DATA0 0x000000FFU
1802 #define CAN_TDL1R_DATA1 0x0000FF00U
1803 #define CAN_TDL1R_DATA2 0x00FF0000U
1804 #define CAN_TDL1R_DATA3 0xFF000000U
1806 /******************* Bit definition for CAN_TDH1R register ******************/
1807 #define CAN_TDH1R_DATA4 0x000000FFU
1808 #define CAN_TDH1R_DATA5 0x0000FF00U
1809 #define CAN_TDH1R_DATA6 0x00FF0000U
1810 #define CAN_TDH1R_DATA7 0xFF000000U
1812 /******************* Bit definition for CAN_TI2R register *******************/
1813 #define CAN_TI2R_TXRQ 0x00000001U
1814 #define CAN_TI2R_RTR 0x00000002U
1815 #define CAN_TI2R_IDE 0x00000004U
1816 #define CAN_TI2R_EXID 0x001FFFF8U
1817 #define CAN_TI2R_STID 0xFFE00000U
1819 /******************* Bit definition for CAN_TDT2R register ******************/
1820 #define CAN_TDT2R_DLC 0x0000000FU
1821 #define CAN_TDT2R_TGT 0x00000100U
1822 #define CAN_TDT2R_TIME 0xFFFF0000U
1824 /******************* Bit definition for CAN_TDL2R register ******************/
1825 #define CAN_TDL2R_DATA0 0x000000FFU
1826 #define CAN_TDL2R_DATA1 0x0000FF00U
1827 #define CAN_TDL2R_DATA2 0x00FF0000U
1828 #define CAN_TDL2R_DATA3 0xFF000000U
1830 /******************* Bit definition for CAN_TDH2R register ******************/
1831 #define CAN_TDH2R_DATA4 0x000000FFU
1832 #define CAN_TDH2R_DATA5 0x0000FF00U
1833 #define CAN_TDH2R_DATA6 0x00FF0000U
1834 #define CAN_TDH2R_DATA7 0xFF000000U
1836 /******************* Bit definition for CAN_RI0R register *******************/
1837 #define CAN_RI0R_RTR 0x00000002U
1838 #define CAN_RI0R_IDE 0x00000004U
1839 #define CAN_RI0R_EXID 0x001FFFF8U
1840 #define CAN_RI0R_STID 0xFFE00000U
1842 /******************* Bit definition for CAN_RDT0R register ******************/
1843 #define CAN_RDT0R_DLC 0x0000000FU
1844 #define CAN_RDT0R_FMI 0x0000FF00U
1845 #define CAN_RDT0R_TIME 0xFFFF0000U
1847 /******************* Bit definition for CAN_RDL0R register ******************/
1848 #define CAN_RDL0R_DATA0 0x000000FFU
1849 #define CAN_RDL0R_DATA1 0x0000FF00U
1850 #define CAN_RDL0R_DATA2 0x00FF0000U
1851 #define CAN_RDL0R_DATA3 0xFF000000U
1853 /******************* Bit definition for CAN_RDH0R register ******************/
1854 #define CAN_RDH0R_DATA4 0x000000FFU
1855 #define CAN_RDH0R_DATA5 0x0000FF00U
1856 #define CAN_RDH0R_DATA6 0x00FF0000U
1857 #define CAN_RDH0R_DATA7 0xFF000000U
1859 /******************* Bit definition for CAN_RI1R register *******************/
1860 #define CAN_RI1R_RTR 0x00000002U
1861 #define CAN_RI1R_IDE 0x00000004U
1862 #define CAN_RI1R_EXID 0x001FFFF8U
1863 #define CAN_RI1R_STID 0xFFE00000U
1865 /******************* Bit definition for CAN_RDT1R register ******************/
1866 #define CAN_RDT1R_DLC 0x0000000FU
1867 #define CAN_RDT1R_FMI 0x0000FF00U
1868 #define CAN_RDT1R_TIME 0xFFFF0000U
1870 /******************* Bit definition for CAN_RDL1R register ******************/
1871 #define CAN_RDL1R_DATA0 0x000000FFU
1872 #define CAN_RDL1R_DATA1 0x0000FF00U
1873 #define CAN_RDL1R_DATA2 0x00FF0000U
1874 #define CAN_RDL1R_DATA3 0xFF000000U
1876 /******************* Bit definition for CAN_RDH1R register ******************/
1877 #define CAN_RDH1R_DATA4 0x000000FFU
1878 #define CAN_RDH1R_DATA5 0x0000FF00U
1879 #define CAN_RDH1R_DATA6 0x00FF0000U
1880 #define CAN_RDH1R_DATA7 0xFF000000U
1883 /******************* Bit definition for CAN_FMR register ********************/
1884 #define CAN_FMR_FINIT 0x01U
1885 #define CAN_FMR_CAN2SB 0x00003F00U
1887 /******************* Bit definition for CAN_FM1R register *******************/
1888 #define CAN_FM1R_FBM 0x0FFFFFFFU
1889 #define CAN_FM1R_FBM0 0x00000001U
1890 #define CAN_FM1R_FBM1 0x00000002U
1891 #define CAN_FM1R_FBM2 0x00000004U
1892 #define CAN_FM1R_FBM3 0x00000008U
1893 #define CAN_FM1R_FBM4 0x00000010U
1894 #define CAN_FM1R_FBM5 0x00000020U
1895 #define CAN_FM1R_FBM6 0x00000040U
1896 #define CAN_FM1R_FBM7 0x00000080U
1897 #define CAN_FM1R_FBM8 0x00000100U
1898 #define CAN_FM1R_FBM9 0x00000200U
1899 #define CAN_FM1R_FBM10 0x00000400U
1900 #define CAN_FM1R_FBM11 0x00000800U
1901 #define CAN_FM1R_FBM12 0x00001000U
1902 #define CAN_FM1R_FBM13 0x00002000U
1903 #define CAN_FM1R_FBM14 0x00004000U
1904 #define CAN_FM1R_FBM15 0x00008000U
1905 #define CAN_FM1R_FBM16 0x00010000U
1906 #define CAN_FM1R_FBM17 0x00020000U
1907 #define CAN_FM1R_FBM18 0x00040000U
1908 #define CAN_FM1R_FBM19 0x00080000U
1909 #define CAN_FM1R_FBM20 0x00100000U
1910 #define CAN_FM1R_FBM21 0x00200000U
1911 #define CAN_FM1R_FBM22 0x00400000U
1912 #define CAN_FM1R_FBM23 0x00800000U
1913 #define CAN_FM1R_FBM24 0x01000000U
1914 #define CAN_FM1R_FBM25 0x02000000U
1915 #define CAN_FM1R_FBM26 0x04000000U
1916 #define CAN_FM1R_FBM27 0x08000000U
1918 /******************* Bit definition for CAN_FS1R register *******************/
1919 #define CAN_FS1R_FSC 0x0FFFFFFFU
1920 #define CAN_FS1R_FSC0 0x00000001U
1921 #define CAN_FS1R_FSC1 0x00000002U
1922 #define CAN_FS1R_FSC2 0x00000004U
1923 #define CAN_FS1R_FSC3 0x00000008U
1924 #define CAN_FS1R_FSC4 0x00000010U
1925 #define CAN_FS1R_FSC5 0x00000020U
1926 #define CAN_FS1R_FSC6 0x00000040U
1927 #define CAN_FS1R_FSC7 0x00000080U
1928 #define CAN_FS1R_FSC8 0x00000100U
1929 #define CAN_FS1R_FSC9 0x00000200U
1930 #define CAN_FS1R_FSC10 0x00000400U
1931 #define CAN_FS1R_FSC11 0x00000800U
1932 #define CAN_FS1R_FSC12 0x00001000U
1933 #define CAN_FS1R_FSC13 0x00002000U
1934 #define CAN_FS1R_FSC14 0x00004000U
1935 #define CAN_FS1R_FSC15 0x00008000U
1936 #define CAN_FS1R_FSC16 0x00010000U
1937 #define CAN_FS1R_FSC17 0x00020000U
1938 #define CAN_FS1R_FSC18 0x00040000U
1939 #define CAN_FS1R_FSC19 0x00080000U
1940 #define CAN_FS1R_FSC20 0x00100000U
1941 #define CAN_FS1R_FSC21 0x00200000U
1942 #define CAN_FS1R_FSC22 0x00400000U
1943 #define CAN_FS1R_FSC23 0x00800000U
1944 #define CAN_FS1R_FSC24 0x01000000U
1945 #define CAN_FS1R_FSC25 0x02000000U
1946 #define CAN_FS1R_FSC26 0x04000000U
1947 #define CAN_FS1R_FSC27 0x08000000U
1949 /****************** Bit definition for CAN_FFA1R register *******************/
1950 #define CAN_FFA1R_FFA 0x0FFFFFFFU
1951 #define CAN_FFA1R_FFA0 0x00000001U
1952 #define CAN_FFA1R_FFA1 0x00000002U
1953 #define CAN_FFA1R_FFA2 0x00000004U
1954 #define CAN_FFA1R_FFA3 0x00000008U
1955 #define CAN_FFA1R_FFA4 0x00000010U
1956 #define CAN_FFA1R_FFA5 0x00000020U
1957 #define CAN_FFA1R_FFA6 0x00000040U
1958 #define CAN_FFA1R_FFA7 0x00000080U
1959 #define CAN_FFA1R_FFA8 0x00000100U
1960 #define CAN_FFA1R_FFA9 0x00000200U
1961 #define CAN_FFA1R_FFA10 0x00000400U
1962 #define CAN_FFA1R_FFA11 0x00000800U
1963 #define CAN_FFA1R_FFA12 0x00001000U
1964 #define CAN_FFA1R_FFA13 0x00002000U
1965 #define CAN_FFA1R_FFA14 0x00004000U
1966 #define CAN_FFA1R_FFA15 0x00008000U
1967 #define CAN_FFA1R_FFA16 0x00010000U
1968 #define CAN_FFA1R_FFA17 0x00020000U
1969 #define CAN_FFA1R_FFA18 0x00040000U
1970 #define CAN_FFA1R_FFA19 0x00080000U
1971 #define CAN_FFA1R_FFA20 0x00100000U
1972 #define CAN_FFA1R_FFA21 0x00200000U
1973 #define CAN_FFA1R_FFA22 0x00400000U
1974 #define CAN_FFA1R_FFA23 0x00800000U
1975 #define CAN_FFA1R_FFA24 0x01000000U
1976 #define CAN_FFA1R_FFA25 0x02000000U
1977 #define CAN_FFA1R_FFA26 0x04000000U
1978 #define CAN_FFA1R_FFA27 0x08000000U
1980 /******************* Bit definition for CAN_FA1R register *******************/
1981 #define CAN_FA1R_FACT 0x0FFFFFFFU
1982 #define CAN_FA1R_FACT0 0x00000001U
1983 #define CAN_FA1R_FACT1 0x00000002U
1984 #define CAN_FA1R_FACT2 0x00000004U
1985 #define CAN_FA1R_FACT3 0x00000008U
1986 #define CAN_FA1R_FACT4 0x00000010U
1987 #define CAN_FA1R_FACT5 0x00000020U
1988 #define CAN_FA1R_FACT6 0x00000040U
1989 #define CAN_FA1R_FACT7 0x00000080U
1990 #define CAN_FA1R_FACT8 0x00000100U
1991 #define CAN_FA1R_FACT9 0x00000200U
1992 #define CAN_FA1R_FACT10 0x00000400U
1993 #define CAN_FA1R_FACT11 0x00000800U
1994 #define CAN_FA1R_FACT12 0x00001000U
1995 #define CAN_FA1R_FACT13 0x00002000U
1996 #define CAN_FA1R_FACT14 0x00004000U
1997 #define CAN_FA1R_FACT15 0x00008000U
1998 #define CAN_FA1R_FACT16 0x00010000U
1999 #define CAN_FA1R_FACT17 0x00020000U
2000 #define CAN_FA1R_FACT18 0x00040000U
2001 #define CAN_FA1R_FACT19 0x00080000U
2002 #define CAN_FA1R_FACT20 0x00100000U
2003 #define CAN_FA1R_FACT21 0x00200000U
2004 #define CAN_FA1R_FACT22 0x00400000U
2005 #define CAN_FA1R_FACT23 0x00800000U
2006 #define CAN_FA1R_FACT24 0x01000000U
2007 #define CAN_FA1R_FACT25 0x02000000U
2008 #define CAN_FA1R_FACT26 0x04000000U
2009 #define CAN_FA1R_FACT27 0x08000000U
2011 /******************* Bit definition for CAN_F0R1 register *******************/
2012 #define CAN_F0R1_FB0 0x00000001U
2013 #define CAN_F0R1_FB1 0x00000002U
2014 #define CAN_F0R1_FB2 0x00000004U
2015 #define CAN_F0R1_FB3 0x00000008U
2016 #define CAN_F0R1_FB4 0x00000010U
2017 #define CAN_F0R1_FB5 0x00000020U
2018 #define CAN_F0R1_FB6 0x00000040U
2019 #define CAN_F0R1_FB7 0x00000080U
2020 #define CAN_F0R1_FB8 0x00000100U
2021 #define CAN_F0R1_FB9 0x00000200U
2022 #define CAN_F0R1_FB10 0x00000400U
2023 #define CAN_F0R1_FB11 0x00000800U
2024 #define CAN_F0R1_FB12 0x00001000U
2025 #define CAN_F0R1_FB13 0x00002000U
2026 #define CAN_F0R1_FB14 0x00004000U
2027 #define CAN_F0R1_FB15 0x00008000U
2028 #define CAN_F0R1_FB16 0x00010000U
2029 #define CAN_F0R1_FB17 0x00020000U
2030 #define CAN_F0R1_FB18 0x00040000U
2031 #define CAN_F0R1_FB19 0x00080000U
2032 #define CAN_F0R1_FB20 0x00100000U
2033 #define CAN_F0R1_FB21 0x00200000U
2034 #define CAN_F0R1_FB22 0x00400000U
2035 #define CAN_F0R1_FB23 0x00800000U
2036 #define CAN_F0R1_FB24 0x01000000U
2037 #define CAN_F0R1_FB25 0x02000000U
2038 #define CAN_F0R1_FB26 0x04000000U
2039 #define CAN_F0R1_FB27 0x08000000U
2040 #define CAN_F0R1_FB28 0x10000000U
2041 #define CAN_F0R1_FB29 0x20000000U
2042 #define CAN_F0R1_FB30 0x40000000U
2043 #define CAN_F0R1_FB31 0x80000000U
2045 /******************* Bit definition for CAN_F1R1 register *******************/
2046 #define CAN_F1R1_FB0 0x00000001U
2047 #define CAN_F1R1_FB1 0x00000002U
2048 #define CAN_F1R1_FB2 0x00000004U
2049 #define CAN_F1R1_FB3 0x00000008U
2050 #define CAN_F1R1_FB4 0x00000010U
2051 #define CAN_F1R1_FB5 0x00000020U
2052 #define CAN_F1R1_FB6 0x00000040U
2053 #define CAN_F1R1_FB7 0x00000080U
2054 #define CAN_F1R1_FB8 0x00000100U
2055 #define CAN_F1R1_FB9 0x00000200U
2056 #define CAN_F1R1_FB10 0x00000400U
2057 #define CAN_F1R1_FB11 0x00000800U
2058 #define CAN_F1R1_FB12 0x00001000U
2059 #define CAN_F1R1_FB13 0x00002000U
2060 #define CAN_F1R1_FB14 0x00004000U
2061 #define CAN_F1R1_FB15 0x00008000U
2062 #define CAN_F1R1_FB16 0x00010000U
2063 #define CAN_F1R1_FB17 0x00020000U
2064 #define CAN_F1R1_FB18 0x00040000U
2065 #define CAN_F1R1_FB19 0x00080000U
2066 #define CAN_F1R1_FB20 0x00100000U
2067 #define CAN_F1R1_FB21 0x00200000U
2068 #define CAN_F1R1_FB22 0x00400000U
2069 #define CAN_F1R1_FB23 0x00800000U
2070 #define CAN_F1R1_FB24 0x01000000U
2071 #define CAN_F1R1_FB25 0x02000000U
2072 #define CAN_F1R1_FB26 0x04000000U
2073 #define CAN_F1R1_FB27 0x08000000U
2074 #define CAN_F1R1_FB28 0x10000000U
2075 #define CAN_F1R1_FB29 0x20000000U
2076 #define CAN_F1R1_FB30 0x40000000U
2077 #define CAN_F1R1_FB31 0x80000000U
2079 /******************* Bit definition for CAN_F2R1 register *******************/
2080 #define CAN_F2R1_FB0 0x00000001U
2081 #define CAN_F2R1_FB1 0x00000002U
2082 #define CAN_F2R1_FB2 0x00000004U
2083 #define CAN_F2R1_FB3 0x00000008U
2084 #define CAN_F2R1_FB4 0x00000010U
2085 #define CAN_F2R1_FB5 0x00000020U
2086 #define CAN_F2R1_FB6 0x00000040U
2087 #define CAN_F2R1_FB7 0x00000080U
2088 #define CAN_F2R1_FB8 0x00000100U
2089 #define CAN_F2R1_FB9 0x00000200U
2090 #define CAN_F2R1_FB10 0x00000400U
2091 #define CAN_F2R1_FB11 0x00000800U
2092 #define CAN_F2R1_FB12 0x00001000U
2093 #define CAN_F2R1_FB13 0x00002000U
2094 #define CAN_F2R1_FB14 0x00004000U
2095 #define CAN_F2R1_FB15 0x00008000U
2096 #define CAN_F2R1_FB16 0x00010000U
2097 #define CAN_F2R1_FB17 0x00020000U
2098 #define CAN_F2R1_FB18 0x00040000U
2099 #define CAN_F2R1_FB19 0x00080000U
2100 #define CAN_F2R1_FB20 0x00100000U
2101 #define CAN_F2R1_FB21 0x00200000U
2102 #define CAN_F2R1_FB22 0x00400000U
2103 #define CAN_F2R1_FB23 0x00800000U
2104 #define CAN_F2R1_FB24 0x01000000U
2105 #define CAN_F2R1_FB25 0x02000000U
2106 #define CAN_F2R1_FB26 0x04000000U
2107 #define CAN_F2R1_FB27 0x08000000U
2108 #define CAN_F2R1_FB28 0x10000000U
2109 #define CAN_F2R1_FB29 0x20000000U
2110 #define CAN_F2R1_FB30 0x40000000U
2111 #define CAN_F2R1_FB31 0x80000000U
2113 /******************* Bit definition for CAN_F3R1 register *******************/
2114 #define CAN_F3R1_FB0 0x00000001U
2115 #define CAN_F3R1_FB1 0x00000002U
2116 #define CAN_F3R1_FB2 0x00000004U
2117 #define CAN_F3R1_FB3 0x00000008U
2118 #define CAN_F3R1_FB4 0x00000010U
2119 #define CAN_F3R1_FB5 0x00000020U
2120 #define CAN_F3R1_FB6 0x00000040U
2121 #define CAN_F3R1_FB7 0x00000080U
2122 #define CAN_F3R1_FB8 0x00000100U
2123 #define CAN_F3R1_FB9 0x00000200U
2124 #define CAN_F3R1_FB10 0x00000400U
2125 #define CAN_F3R1_FB11 0x00000800U
2126 #define CAN_F3R1_FB12 0x00001000U
2127 #define CAN_F3R1_FB13 0x00002000U
2128 #define CAN_F3R1_FB14 0x00004000U
2129 #define CAN_F3R1_FB15 0x00008000U
2130 #define CAN_F3R1_FB16 0x00010000U
2131 #define CAN_F3R1_FB17 0x00020000U
2132 #define CAN_F3R1_FB18 0x00040000U
2133 #define CAN_F3R1_FB19 0x00080000U
2134 #define CAN_F3R1_FB20 0x00100000U
2135 #define CAN_F3R1_FB21 0x00200000U
2136 #define CAN_F3R1_FB22 0x00400000U
2137 #define CAN_F3R1_FB23 0x00800000U
2138 #define CAN_F3R1_FB24 0x01000000U
2139 #define CAN_F3R1_FB25 0x02000000U
2140 #define CAN_F3R1_FB26 0x04000000U
2141 #define CAN_F3R1_FB27 0x08000000U
2142 #define CAN_F3R1_FB28 0x10000000U
2143 #define CAN_F3R1_FB29 0x20000000U
2144 #define CAN_F3R1_FB30 0x40000000U
2145 #define CAN_F3R1_FB31 0x80000000U
2147 /******************* Bit definition for CAN_F4R1 register *******************/
2148 #define CAN_F4R1_FB0 0x00000001U
2149 #define CAN_F4R1_FB1 0x00000002U
2150 #define CAN_F4R1_FB2 0x00000004U
2151 #define CAN_F4R1_FB3 0x00000008U
2152 #define CAN_F4R1_FB4 0x00000010U
2153 #define CAN_F4R1_FB5 0x00000020U
2154 #define CAN_F4R1_FB6 0x00000040U
2155 #define CAN_F4R1_FB7 0x00000080U
2156 #define CAN_F4R1_FB8 0x00000100U
2157 #define CAN_F4R1_FB9 0x00000200U
2158 #define CAN_F4R1_FB10 0x00000400U
2159 #define CAN_F4R1_FB11 0x00000800U
2160 #define CAN_F4R1_FB12 0x00001000U
2161 #define CAN_F4R1_FB13 0x00002000U
2162 #define CAN_F4R1_FB14 0x00004000U
2163 #define CAN_F4R1_FB15 0x00008000U
2164 #define CAN_F4R1_FB16 0x00010000U
2165 #define CAN_F4R1_FB17 0x00020000U
2166 #define CAN_F4R1_FB18 0x00040000U
2167 #define CAN_F4R1_FB19 0x00080000U
2168 #define CAN_F4R1_FB20 0x00100000U
2169 #define CAN_F4R1_FB21 0x00200000U
2170 #define CAN_F4R1_FB22 0x00400000U
2171 #define CAN_F4R1_FB23 0x00800000U
2172 #define CAN_F4R1_FB24 0x01000000U
2173 #define CAN_F4R1_FB25 0x02000000U
2174 #define CAN_F4R1_FB26 0x04000000U
2175 #define CAN_F4R1_FB27 0x08000000U
2176 #define CAN_F4R1_FB28 0x10000000U
2177 #define CAN_F4R1_FB29 0x20000000U
2178 #define CAN_F4R1_FB30 0x40000000U
2179 #define CAN_F4R1_FB31 0x80000000U
2181 /******************* Bit definition for CAN_F5R1 register *******************/
2182 #define CAN_F5R1_FB0 0x00000001U
2183 #define CAN_F5R1_FB1 0x00000002U
2184 #define CAN_F5R1_FB2 0x00000004U
2185 #define CAN_F5R1_FB3 0x00000008U
2186 #define CAN_F5R1_FB4 0x00000010U
2187 #define CAN_F5R1_FB5 0x00000020U
2188 #define CAN_F5R1_FB6 0x00000040U
2189 #define CAN_F5R1_FB7 0x00000080U
2190 #define CAN_F5R1_FB8 0x00000100U
2191 #define CAN_F5R1_FB9 0x00000200U
2192 #define CAN_F5R1_FB10 0x00000400U
2193 #define CAN_F5R1_FB11 0x00000800U
2194 #define CAN_F5R1_FB12 0x00001000U
2195 #define CAN_F5R1_FB13 0x00002000U
2196 #define CAN_F5R1_FB14 0x00004000U
2197 #define CAN_F5R1_FB15 0x00008000U
2198 #define CAN_F5R1_FB16 0x00010000U
2199 #define CAN_F5R1_FB17 0x00020000U
2200 #define CAN_F5R1_FB18 0x00040000U
2201 #define CAN_F5R1_FB19 0x00080000U
2202 #define CAN_F5R1_FB20 0x00100000U
2203 #define CAN_F5R1_FB21 0x00200000U
2204 #define CAN_F5R1_FB22 0x00400000U
2205 #define CAN_F5R1_FB23 0x00800000U
2206 #define CAN_F5R1_FB24 0x01000000U
2207 #define CAN_F5R1_FB25 0x02000000U
2208 #define CAN_F5R1_FB26 0x04000000U
2209 #define CAN_F5R1_FB27 0x08000000U
2210 #define CAN_F5R1_FB28 0x10000000U
2211 #define CAN_F5R1_FB29 0x20000000U
2212 #define CAN_F5R1_FB30 0x40000000U
2213 #define CAN_F5R1_FB31 0x80000000U
2215 /******************* Bit definition for CAN_F6R1 register *******************/
2216 #define CAN_F6R1_FB0 0x00000001U
2217 #define CAN_F6R1_FB1 0x00000002U
2218 #define CAN_F6R1_FB2 0x00000004U
2219 #define CAN_F6R1_FB3 0x00000008U
2220 #define CAN_F6R1_FB4 0x00000010U
2221 #define CAN_F6R1_FB5 0x00000020U
2222 #define CAN_F6R1_FB6 0x00000040U
2223 #define CAN_F6R1_FB7 0x00000080U
2224 #define CAN_F6R1_FB8 0x00000100U
2225 #define CAN_F6R1_FB9 0x00000200U
2226 #define CAN_F6R1_FB10 0x00000400U
2227 #define CAN_F6R1_FB11 0x00000800U
2228 #define CAN_F6R1_FB12 0x00001000U
2229 #define CAN_F6R1_FB13 0x00002000U
2230 #define CAN_F6R1_FB14 0x00004000U
2231 #define CAN_F6R1_FB15 0x00008000U
2232 #define CAN_F6R1_FB16 0x00010000U
2233 #define CAN_F6R1_FB17 0x00020000U
2234 #define CAN_F6R1_FB18 0x00040000U
2235 #define CAN_F6R1_FB19 0x00080000U
2236 #define CAN_F6R1_FB20 0x00100000U
2237 #define CAN_F6R1_FB21 0x00200000U
2238 #define CAN_F6R1_FB22 0x00400000U
2239 #define CAN_F6R1_FB23 0x00800000U
2240 #define CAN_F6R1_FB24 0x01000000U
2241 #define CAN_F6R1_FB25 0x02000000U
2242 #define CAN_F6R1_FB26 0x04000000U
2243 #define CAN_F6R1_FB27 0x08000000U
2244 #define CAN_F6R1_FB28 0x10000000U
2245 #define CAN_F6R1_FB29 0x20000000U
2246 #define CAN_F6R1_FB30 0x40000000U
2247 #define CAN_F6R1_FB31 0x80000000U
2249 /******************* Bit definition for CAN_F7R1 register *******************/
2250 #define CAN_F7R1_FB0 0x00000001U
2251 #define CAN_F7R1_FB1 0x00000002U
2252 #define CAN_F7R1_FB2 0x00000004U
2253 #define CAN_F7R1_FB3 0x00000008U
2254 #define CAN_F7R1_FB4 0x00000010U
2255 #define CAN_F7R1_FB5 0x00000020U
2256 #define CAN_F7R1_FB6 0x00000040U
2257 #define CAN_F7R1_FB7 0x00000080U
2258 #define CAN_F7R1_FB8 0x00000100U
2259 #define CAN_F7R1_FB9 0x00000200U
2260 #define CAN_F7R1_FB10 0x00000400U
2261 #define CAN_F7R1_FB11 0x00000800U
2262 #define CAN_F7R1_FB12 0x00001000U
2263 #define CAN_F7R1_FB13 0x00002000U
2264 #define CAN_F7R1_FB14 0x00004000U
2265 #define CAN_F7R1_FB15 0x00008000U
2266 #define CAN_F7R1_FB16 0x00010000U
2267 #define CAN_F7R1_FB17 0x00020000U
2268 #define CAN_F7R1_FB18 0x00040000U
2269 #define CAN_F7R1_FB19 0x00080000U
2270 #define CAN_F7R1_FB20 0x00100000U
2271 #define CAN_F7R1_FB21 0x00200000U
2272 #define CAN_F7R1_FB22 0x00400000U
2273 #define CAN_F7R1_FB23 0x00800000U
2274 #define CAN_F7R1_FB24 0x01000000U
2275 #define CAN_F7R1_FB25 0x02000000U
2276 #define CAN_F7R1_FB26 0x04000000U
2277 #define CAN_F7R1_FB27 0x08000000U
2278 #define CAN_F7R1_FB28 0x10000000U
2279 #define CAN_F7R1_FB29 0x20000000U
2280 #define CAN_F7R1_FB30 0x40000000U
2281 #define CAN_F7R1_FB31 0x80000000U
2283 /******************* Bit definition for CAN_F8R1 register *******************/
2284 #define CAN_F8R1_FB0 0x00000001U
2285 #define CAN_F8R1_FB1 0x00000002U
2286 #define CAN_F8R1_FB2 0x00000004U
2287 #define CAN_F8R1_FB3 0x00000008U
2288 #define CAN_F8R1_FB4 0x00000010U
2289 #define CAN_F8R1_FB5 0x00000020U
2290 #define CAN_F8R1_FB6 0x00000040U
2291 #define CAN_F8R1_FB7 0x00000080U
2292 #define CAN_F8R1_FB8 0x00000100U
2293 #define CAN_F8R1_FB9 0x00000200U
2294 #define CAN_F8R1_FB10 0x00000400U
2295 #define CAN_F8R1_FB11 0x00000800U
2296 #define CAN_F8R1_FB12 0x00001000U
2297 #define CAN_F8R1_FB13 0x00002000U
2298 #define CAN_F8R1_FB14 0x00004000U
2299 #define CAN_F8R1_FB15 0x00008000U
2300 #define CAN_F8R1_FB16 0x00010000U
2301 #define CAN_F8R1_FB17 0x00020000U
2302 #define CAN_F8R1_FB18 0x00040000U
2303 #define CAN_F8R1_FB19 0x00080000U
2304 #define CAN_F8R1_FB20 0x00100000U
2305 #define CAN_F8R1_FB21 0x00200000U
2306 #define CAN_F8R1_FB22 0x00400000U
2307 #define CAN_F8R1_FB23 0x00800000U
2308 #define CAN_F8R1_FB24 0x01000000U
2309 #define CAN_F8R1_FB25 0x02000000U
2310 #define CAN_F8R1_FB26 0x04000000U
2311 #define CAN_F8R1_FB27 0x08000000U
2312 #define CAN_F8R1_FB28 0x10000000U
2313 #define CAN_F8R1_FB29 0x20000000U
2314 #define CAN_F8R1_FB30 0x40000000U
2315 #define CAN_F8R1_FB31 0x80000000U
2317 /******************* Bit definition for CAN_F9R1 register *******************/
2318 #define CAN_F9R1_FB0 0x00000001U
2319 #define CAN_F9R1_FB1 0x00000002U
2320 #define CAN_F9R1_FB2 0x00000004U
2321 #define CAN_F9R1_FB3 0x00000008U
2322 #define CAN_F9R1_FB4 0x00000010U
2323 #define CAN_F9R1_FB5 0x00000020U
2324 #define CAN_F9R1_FB6 0x00000040U
2325 #define CAN_F9R1_FB7 0x00000080U
2326 #define CAN_F9R1_FB8 0x00000100U
2327 #define CAN_F9R1_FB9 0x00000200U
2328 #define CAN_F9R1_FB10 0x00000400U
2329 #define CAN_F9R1_FB11 0x00000800U
2330 #define CAN_F9R1_FB12 0x00001000U
2331 #define CAN_F9R1_FB13 0x00002000U
2332 #define CAN_F9R1_FB14 0x00004000U
2333 #define CAN_F9R1_FB15 0x00008000U
2334 #define CAN_F9R1_FB16 0x00010000U
2335 #define CAN_F9R1_FB17 0x00020000U
2336 #define CAN_F9R1_FB18 0x00040000U
2337 #define CAN_F9R1_FB19 0x00080000U
2338 #define CAN_F9R1_FB20 0x00100000U
2339 #define CAN_F9R1_FB21 0x00200000U
2340 #define CAN_F9R1_FB22 0x00400000U
2341 #define CAN_F9R1_FB23 0x00800000U
2342 #define CAN_F9R1_FB24 0x01000000U
2343 #define CAN_F9R1_FB25 0x02000000U
2344 #define CAN_F9R1_FB26 0x04000000U
2345 #define CAN_F9R1_FB27 0x08000000U
2346 #define CAN_F9R1_FB28 0x10000000U
2347 #define CAN_F9R1_FB29 0x20000000U
2348 #define CAN_F9R1_FB30 0x40000000U
2349 #define CAN_F9R1_FB31 0x80000000U
2351 /******************* Bit definition for CAN_F10R1 register ******************/
2352 #define CAN_F10R1_FB0 0x00000001U
2353 #define CAN_F10R1_FB1 0x00000002U
2354 #define CAN_F10R1_FB2 0x00000004U
2355 #define CAN_F10R1_FB3 0x00000008U
2356 #define CAN_F10R1_FB4 0x00000010U
2357 #define CAN_F10R1_FB5 0x00000020U
2358 #define CAN_F10R1_FB6 0x00000040U
2359 #define CAN_F10R1_FB7 0x00000080U
2360 #define CAN_F10R1_FB8 0x00000100U
2361 #define CAN_F10R1_FB9 0x00000200U
2362 #define CAN_F10R1_FB10 0x00000400U
2363 #define CAN_F10R1_FB11 0x00000800U
2364 #define CAN_F10R1_FB12 0x00001000U
2365 #define CAN_F10R1_FB13 0x00002000U
2366 #define CAN_F10R1_FB14 0x00004000U
2367 #define CAN_F10R1_FB15 0x00008000U
2368 #define CAN_F10R1_FB16 0x00010000U
2369 #define CAN_F10R1_FB17 0x00020000U
2370 #define CAN_F10R1_FB18 0x00040000U
2371 #define CAN_F10R1_FB19 0x00080000U
2372 #define CAN_F10R1_FB20 0x00100000U
2373 #define CAN_F10R1_FB21 0x00200000U
2374 #define CAN_F10R1_FB22 0x00400000U
2375 #define CAN_F10R1_FB23 0x00800000U
2376 #define CAN_F10R1_FB24 0x01000000U
2377 #define CAN_F10R1_FB25 0x02000000U
2378 #define CAN_F10R1_FB26 0x04000000U
2379 #define CAN_F10R1_FB27 0x08000000U
2380 #define CAN_F10R1_FB28 0x10000000U
2381 #define CAN_F10R1_FB29 0x20000000U
2382 #define CAN_F10R1_FB30 0x40000000U
2383 #define CAN_F10R1_FB31 0x80000000U
2385 /******************* Bit definition for CAN_F11R1 register ******************/
2386 #define CAN_F11R1_FB0 0x00000001U
2387 #define CAN_F11R1_FB1 0x00000002U
2388 #define CAN_F11R1_FB2 0x00000004U
2389 #define CAN_F11R1_FB3 0x00000008U
2390 #define CAN_F11R1_FB4 0x00000010U
2391 #define CAN_F11R1_FB5 0x00000020U
2392 #define CAN_F11R1_FB6 0x00000040U
2393 #define CAN_F11R1_FB7 0x00000080U
2394 #define CAN_F11R1_FB8 0x00000100U
2395 #define CAN_F11R1_FB9 0x00000200U
2396 #define CAN_F11R1_FB10 0x00000400U
2397 #define CAN_F11R1_FB11 0x00000800U
2398 #define CAN_F11R1_FB12 0x00001000U
2399 #define CAN_F11R1_FB13 0x00002000U
2400 #define CAN_F11R1_FB14 0x00004000U
2401 #define CAN_F11R1_FB15 0x00008000U
2402 #define CAN_F11R1_FB16 0x00010000U
2403 #define CAN_F11R1_FB17 0x00020000U
2404 #define CAN_F11R1_FB18 0x00040000U
2405 #define CAN_F11R1_FB19 0x00080000U
2406 #define CAN_F11R1_FB20 0x00100000U
2407 #define CAN_F11R1_FB21 0x00200000U
2408 #define CAN_F11R1_FB22 0x00400000U
2409 #define CAN_F11R1_FB23 0x00800000U
2410 #define CAN_F11R1_FB24 0x01000000U
2411 #define CAN_F11R1_FB25 0x02000000U
2412 #define CAN_F11R1_FB26 0x04000000U
2413 #define CAN_F11R1_FB27 0x08000000U
2414 #define CAN_F11R1_FB28 0x10000000U
2415 #define CAN_F11R1_FB29 0x20000000U
2416 #define CAN_F11R1_FB30 0x40000000U
2417 #define CAN_F11R1_FB31 0x80000000U
2419 /******************* Bit definition for CAN_F12R1 register ******************/
2420 #define CAN_F12R1_FB0 0x00000001U
2421 #define CAN_F12R1_FB1 0x00000002U
2422 #define CAN_F12R1_FB2 0x00000004U
2423 #define CAN_F12R1_FB3 0x00000008U
2424 #define CAN_F12R1_FB4 0x00000010U
2425 #define CAN_F12R1_FB5 0x00000020U
2426 #define CAN_F12R1_FB6 0x00000040U
2427 #define CAN_F12R1_FB7 0x00000080U
2428 #define CAN_F12R1_FB8 0x00000100U
2429 #define CAN_F12R1_FB9 0x00000200U
2430 #define CAN_F12R1_FB10 0x00000400U
2431 #define CAN_F12R1_FB11 0x00000800U
2432 #define CAN_F12R1_FB12 0x00001000U
2433 #define CAN_F12R1_FB13 0x00002000U
2434 #define CAN_F12R1_FB14 0x00004000U
2435 #define CAN_F12R1_FB15 0x00008000U
2436 #define CAN_F12R1_FB16 0x00010000U
2437 #define CAN_F12R1_FB17 0x00020000U
2438 #define CAN_F12R1_FB18 0x00040000U
2439 #define CAN_F12R1_FB19 0x00080000U
2440 #define CAN_F12R1_FB20 0x00100000U
2441 #define CAN_F12R1_FB21 0x00200000U
2442 #define CAN_F12R1_FB22 0x00400000U
2443 #define CAN_F12R1_FB23 0x00800000U
2444 #define CAN_F12R1_FB24 0x01000000U
2445 #define CAN_F12R1_FB25 0x02000000U
2446 #define CAN_F12R1_FB26 0x04000000U
2447 #define CAN_F12R1_FB27 0x08000000U
2448 #define CAN_F12R1_FB28 0x10000000U
2449 #define CAN_F12R1_FB29 0x20000000U
2450 #define CAN_F12R1_FB30 0x40000000U
2451 #define CAN_F12R1_FB31 0x80000000U
2453 /******************* Bit definition for CAN_F13R1 register ******************/
2454 #define CAN_F13R1_FB0 0x00000001U
2455 #define CAN_F13R1_FB1 0x00000002U
2456 #define CAN_F13R1_FB2 0x00000004U
2457 #define CAN_F13R1_FB3 0x00000008U
2458 #define CAN_F13R1_FB4 0x00000010U
2459 #define CAN_F13R1_FB5 0x00000020U
2460 #define CAN_F13R1_FB6 0x00000040U
2461 #define CAN_F13R1_FB7 0x00000080U
2462 #define CAN_F13R1_FB8 0x00000100U
2463 #define CAN_F13R1_FB9 0x00000200U
2464 #define CAN_F13R1_FB10 0x00000400U
2465 #define CAN_F13R1_FB11 0x00000800U
2466 #define CAN_F13R1_FB12 0x00001000U
2467 #define CAN_F13R1_FB13 0x00002000U
2468 #define CAN_F13R1_FB14 0x00004000U
2469 #define CAN_F13R1_FB15 0x00008000U
2470 #define CAN_F13R1_FB16 0x00010000U
2471 #define CAN_F13R1_FB17 0x00020000U
2472 #define CAN_F13R1_FB18 0x00040000U
2473 #define CAN_F13R1_FB19 0x00080000U
2474 #define CAN_F13R1_FB20 0x00100000U
2475 #define CAN_F13R1_FB21 0x00200000U
2476 #define CAN_F13R1_FB22 0x00400000U
2477 #define CAN_F13R1_FB23 0x00800000U
2478 #define CAN_F13R1_FB24 0x01000000U
2479 #define CAN_F13R1_FB25 0x02000000U
2480 #define CAN_F13R1_FB26 0x04000000U
2481 #define CAN_F13R1_FB27 0x08000000U
2482 #define CAN_F13R1_FB28 0x10000000U
2483 #define CAN_F13R1_FB29 0x20000000U
2484 #define CAN_F13R1_FB30 0x40000000U
2485 #define CAN_F13R1_FB31 0x80000000U
2487 /******************* Bit definition for CAN_F0R2 register *******************/
2488 #define CAN_F0R2_FB0 0x00000001U
2489 #define CAN_F0R2_FB1 0x00000002U
2490 #define CAN_F0R2_FB2 0x00000004U
2491 #define CAN_F0R2_FB3 0x00000008U
2492 #define CAN_F0R2_FB4 0x00000010U
2493 #define CAN_F0R2_FB5 0x00000020U
2494 #define CAN_F0R2_FB6 0x00000040U
2495 #define CAN_F0R2_FB7 0x00000080U
2496 #define CAN_F0R2_FB8 0x00000100U
2497 #define CAN_F0R2_FB9 0x00000200U
2498 #define CAN_F0R2_FB10 0x00000400U
2499 #define CAN_F0R2_FB11 0x00000800U
2500 #define CAN_F0R2_FB12 0x00001000U
2501 #define CAN_F0R2_FB13 0x00002000U
2502 #define CAN_F0R2_FB14 0x00004000U
2503 #define CAN_F0R2_FB15 0x00008000U
2504 #define CAN_F0R2_FB16 0x00010000U
2505 #define CAN_F0R2_FB17 0x00020000U
2506 #define CAN_F0R2_FB18 0x00040000U
2507 #define CAN_F0R2_FB19 0x00080000U
2508 #define CAN_F0R2_FB20 0x00100000U
2509 #define CAN_F0R2_FB21 0x00200000U
2510 #define CAN_F0R2_FB22 0x00400000U
2511 #define CAN_F0R2_FB23 0x00800000U
2512 #define CAN_F0R2_FB24 0x01000000U
2513 #define CAN_F0R2_FB25 0x02000000U
2514 #define CAN_F0R2_FB26 0x04000000U
2515 #define CAN_F0R2_FB27 0x08000000U
2516 #define CAN_F0R2_FB28 0x10000000U
2517 #define CAN_F0R2_FB29 0x20000000U
2518 #define CAN_F0R2_FB30 0x40000000U
2519 #define CAN_F0R2_FB31 0x80000000U
2521 /******************* Bit definition for CAN_F1R2 register *******************/
2522 #define CAN_F1R2_FB0 0x00000001U
2523 #define CAN_F1R2_FB1 0x00000002U
2524 #define CAN_F1R2_FB2 0x00000004U
2525 #define CAN_F1R2_FB3 0x00000008U
2526 #define CAN_F1R2_FB4 0x00000010U
2527 #define CAN_F1R2_FB5 0x00000020U
2528 #define CAN_F1R2_FB6 0x00000040U
2529 #define CAN_F1R2_FB7 0x00000080U
2530 #define CAN_F1R2_FB8 0x00000100U
2531 #define CAN_F1R2_FB9 0x00000200U
2532 #define CAN_F1R2_FB10 0x00000400U
2533 #define CAN_F1R2_FB11 0x00000800U
2534 #define CAN_F1R2_FB12 0x00001000U
2535 #define CAN_F1R2_FB13 0x00002000U
2536 #define CAN_F1R2_FB14 0x00004000U
2537 #define CAN_F1R2_FB15 0x00008000U
2538 #define CAN_F1R2_FB16 0x00010000U
2539 #define CAN_F1R2_FB17 0x00020000U
2540 #define CAN_F1R2_FB18 0x00040000U
2541 #define CAN_F1R2_FB19 0x00080000U
2542 #define CAN_F1R2_FB20 0x00100000U
2543 #define CAN_F1R2_FB21 0x00200000U
2544 #define CAN_F1R2_FB22 0x00400000U
2545 #define CAN_F1R2_FB23 0x00800000U
2546 #define CAN_F1R2_FB24 0x01000000U
2547 #define CAN_F1R2_FB25 0x02000000U
2548 #define CAN_F1R2_FB26 0x04000000U
2549 #define CAN_F1R2_FB27 0x08000000U
2550 #define CAN_F1R2_FB28 0x10000000U
2551 #define CAN_F1R2_FB29 0x20000000U
2552 #define CAN_F1R2_FB30 0x40000000U
2553 #define CAN_F1R2_FB31 0x80000000U
2555 /******************* Bit definition for CAN_F2R2 register *******************/
2556 #define CAN_F2R2_FB0 0x00000001U
2557 #define CAN_F2R2_FB1 0x00000002U
2558 #define CAN_F2R2_FB2 0x00000004U
2559 #define CAN_F2R2_FB3 0x00000008U
2560 #define CAN_F2R2_FB4 0x00000010U
2561 #define CAN_F2R2_FB5 0x00000020U
2562 #define CAN_F2R2_FB6 0x00000040U
2563 #define CAN_F2R2_FB7 0x00000080U
2564 #define CAN_F2R2_FB8 0x00000100U
2565 #define CAN_F2R2_FB9 0x00000200U
2566 #define CAN_F2R2_FB10 0x00000400U
2567 #define CAN_F2R2_FB11 0x00000800U
2568 #define CAN_F2R2_FB12 0x00001000U
2569 #define CAN_F2R2_FB13 0x00002000U
2570 #define CAN_F2R2_FB14 0x00004000U
2571 #define CAN_F2R2_FB15 0x00008000U
2572 #define CAN_F2R2_FB16 0x00010000U
2573 #define CAN_F2R2_FB17 0x00020000U
2574 #define CAN_F2R2_FB18 0x00040000U
2575 #define CAN_F2R2_FB19 0x00080000U
2576 #define CAN_F2R2_FB20 0x00100000U
2577 #define CAN_F2R2_FB21 0x00200000U
2578 #define CAN_F2R2_FB22 0x00400000U
2579 #define CAN_F2R2_FB23 0x00800000U
2580 #define CAN_F2R2_FB24 0x01000000U
2581 #define CAN_F2R2_FB25 0x02000000U
2582 #define CAN_F2R2_FB26 0x04000000U
2583 #define CAN_F2R2_FB27 0x08000000U
2584 #define CAN_F2R2_FB28 0x10000000U
2585 #define CAN_F2R2_FB29 0x20000000U
2586 #define CAN_F2R2_FB30 0x40000000U
2587 #define CAN_F2R2_FB31 0x80000000U
2589 /******************* Bit definition for CAN_F3R2 register *******************/
2590 #define CAN_F3R2_FB0 0x00000001U
2591 #define CAN_F3R2_FB1 0x00000002U
2592 #define CAN_F3R2_FB2 0x00000004U
2593 #define CAN_F3R2_FB3 0x00000008U
2594 #define CAN_F3R2_FB4 0x00000010U
2595 #define CAN_F3R2_FB5 0x00000020U
2596 #define CAN_F3R2_FB6 0x00000040U
2597 #define CAN_F3R2_FB7 0x00000080U
2598 #define CAN_F3R2_FB8 0x00000100U
2599 #define CAN_F3R2_FB9 0x00000200U
2600 #define CAN_F3R2_FB10 0x00000400U
2601 #define CAN_F3R2_FB11 0x00000800U
2602 #define CAN_F3R2_FB12 0x00001000U
2603 #define CAN_F3R2_FB13 0x00002000U
2604 #define CAN_F3R2_FB14 0x00004000U
2605 #define CAN_F3R2_FB15 0x00008000U
2606 #define CAN_F3R2_FB16 0x00010000U
2607 #define CAN_F3R2_FB17 0x00020000U
2608 #define CAN_F3R2_FB18 0x00040000U
2609 #define CAN_F3R2_FB19 0x00080000U
2610 #define CAN_F3R2_FB20 0x00100000U
2611 #define CAN_F3R2_FB21 0x00200000U
2612 #define CAN_F3R2_FB22 0x00400000U
2613 #define CAN_F3R2_FB23 0x00800000U
2614 #define CAN_F3R2_FB24 0x01000000U
2615 #define CAN_F3R2_FB25 0x02000000U
2616 #define CAN_F3R2_FB26 0x04000000U
2617 #define CAN_F3R2_FB27 0x08000000U
2618 #define CAN_F3R2_FB28 0x10000000U
2619 #define CAN_F3R2_FB29 0x20000000U
2620 #define CAN_F3R2_FB30 0x40000000U
2621 #define CAN_F3R2_FB31 0x80000000U
2623 /******************* Bit definition for CAN_F4R2 register *******************/
2624 #define CAN_F4R2_FB0 0x00000001U
2625 #define CAN_F4R2_FB1 0x00000002U
2626 #define CAN_F4R2_FB2 0x00000004U
2627 #define CAN_F4R2_FB3 0x00000008U
2628 #define CAN_F4R2_FB4 0x00000010U
2629 #define CAN_F4R2_FB5 0x00000020U
2630 #define CAN_F4R2_FB6 0x00000040U
2631 #define CAN_F4R2_FB7 0x00000080U
2632 #define CAN_F4R2_FB8 0x00000100U
2633 #define CAN_F4R2_FB9 0x00000200U
2634 #define CAN_F4R2_FB10 0x00000400U
2635 #define CAN_F4R2_FB11 0x00000800U
2636 #define CAN_F4R2_FB12 0x00001000U
2637 #define CAN_F4R2_FB13 0x00002000U
2638 #define CAN_F4R2_FB14 0x00004000U
2639 #define CAN_F4R2_FB15 0x00008000U
2640 #define CAN_F4R2_FB16 0x00010000U
2641 #define CAN_F4R2_FB17 0x00020000U
2642 #define CAN_F4R2_FB18 0x00040000U
2643 #define CAN_F4R2_FB19 0x00080000U
2644 #define CAN_F4R2_FB20 0x00100000U
2645 #define CAN_F4R2_FB21 0x00200000U
2646 #define CAN_F4R2_FB22 0x00400000U
2647 #define CAN_F4R2_FB23 0x00800000U
2648 #define CAN_F4R2_FB24 0x01000000U
2649 #define CAN_F4R2_FB25 0x02000000U
2650 #define CAN_F4R2_FB26 0x04000000U
2651 #define CAN_F4R2_FB27 0x08000000U
2652 #define CAN_F4R2_FB28 0x10000000U
2653 #define CAN_F4R2_FB29 0x20000000U
2654 #define CAN_F4R2_FB30 0x40000000U
2655 #define CAN_F4R2_FB31 0x80000000U
2657 /******************* Bit definition for CAN_F5R2 register *******************/
2658 #define CAN_F5R2_FB0 0x00000001U
2659 #define CAN_F5R2_FB1 0x00000002U
2660 #define CAN_F5R2_FB2 0x00000004U
2661 #define CAN_F5R2_FB3 0x00000008U
2662 #define CAN_F5R2_FB4 0x00000010U
2663 #define CAN_F5R2_FB5 0x00000020U
2664 #define CAN_F5R2_FB6 0x00000040U
2665 #define CAN_F5R2_FB7 0x00000080U
2666 #define CAN_F5R2_FB8 0x00000100U
2667 #define CAN_F5R2_FB9 0x00000200U
2668 #define CAN_F5R2_FB10 0x00000400U
2669 #define CAN_F5R2_FB11 0x00000800U
2670 #define CAN_F5R2_FB12 0x00001000U
2671 #define CAN_F5R2_FB13 0x00002000U
2672 #define CAN_F5R2_FB14 0x00004000U
2673 #define CAN_F5R2_FB15 0x00008000U
2674 #define CAN_F5R2_FB16 0x00010000U
2675 #define CAN_F5R2_FB17 0x00020000U
2676 #define CAN_F5R2_FB18 0x00040000U
2677 #define CAN_F5R2_FB19 0x00080000U
2678 #define CAN_F5R2_FB20 0x00100000U
2679 #define CAN_F5R2_FB21 0x00200000U
2680 #define CAN_F5R2_FB22 0x00400000U
2681 #define CAN_F5R2_FB23 0x00800000U
2682 #define CAN_F5R2_FB24 0x01000000U
2683 #define CAN_F5R2_FB25 0x02000000U
2684 #define CAN_F5R2_FB26 0x04000000U
2685 #define CAN_F5R2_FB27 0x08000000U
2686 #define CAN_F5R2_FB28 0x10000000U
2687 #define CAN_F5R2_FB29 0x20000000U
2688 #define CAN_F5R2_FB30 0x40000000U
2689 #define CAN_F5R2_FB31 0x80000000U
2691 /******************* Bit definition for CAN_F6R2 register *******************/
2692 #define CAN_F6R2_FB0 0x00000001U
2693 #define CAN_F6R2_FB1 0x00000002U
2694 #define CAN_F6R2_FB2 0x00000004U
2695 #define CAN_F6R2_FB3 0x00000008U
2696 #define CAN_F6R2_FB4 0x00000010U
2697 #define CAN_F6R2_FB5 0x00000020U
2698 #define CAN_F6R2_FB6 0x00000040U
2699 #define CAN_F6R2_FB7 0x00000080U
2700 #define CAN_F6R2_FB8 0x00000100U
2701 #define CAN_F6R2_FB9 0x00000200U
2702 #define CAN_F6R2_FB10 0x00000400U
2703 #define CAN_F6R2_FB11 0x00000800U
2704 #define CAN_F6R2_FB12 0x00001000U
2705 #define CAN_F6R2_FB13 0x00002000U
2706 #define CAN_F6R2_FB14 0x00004000U
2707 #define CAN_F6R2_FB15 0x00008000U
2708 #define CAN_F6R2_FB16 0x00010000U
2709 #define CAN_F6R2_FB17 0x00020000U
2710 #define CAN_F6R2_FB18 0x00040000U
2711 #define CAN_F6R2_FB19 0x00080000U
2712 #define CAN_F6R2_FB20 0x00100000U
2713 #define CAN_F6R2_FB21 0x00200000U
2714 #define CAN_F6R2_FB22 0x00400000U
2715 #define CAN_F6R2_FB23 0x00800000U
2716 #define CAN_F6R2_FB24 0x01000000U
2717 #define CAN_F6R2_FB25 0x02000000U
2718 #define CAN_F6R2_FB26 0x04000000U
2719 #define CAN_F6R2_FB27 0x08000000U
2720 #define CAN_F6R2_FB28 0x10000000U
2721 #define CAN_F6R2_FB29 0x20000000U
2722 #define CAN_F6R2_FB30 0x40000000U
2723 #define CAN_F6R2_FB31 0x80000000U
2725 /******************* Bit definition for CAN_F7R2 register *******************/
2726 #define CAN_F7R2_FB0 0x00000001U
2727 #define CAN_F7R2_FB1 0x00000002U
2728 #define CAN_F7R2_FB2 0x00000004U
2729 #define CAN_F7R2_FB3 0x00000008U
2730 #define CAN_F7R2_FB4 0x00000010U
2731 #define CAN_F7R2_FB5 0x00000020U
2732 #define CAN_F7R2_FB6 0x00000040U
2733 #define CAN_F7R2_FB7 0x00000080U
2734 #define CAN_F7R2_FB8 0x00000100U
2735 #define CAN_F7R2_FB9 0x00000200U
2736 #define CAN_F7R2_FB10 0x00000400U
2737 #define CAN_F7R2_FB11 0x00000800U
2738 #define CAN_F7R2_FB12 0x00001000U
2739 #define CAN_F7R2_FB13 0x00002000U
2740 #define CAN_F7R2_FB14 0x00004000U
2741 #define CAN_F7R2_FB15 0x00008000U
2742 #define CAN_F7R2_FB16 0x00010000U
2743 #define CAN_F7R2_FB17 0x00020000U
2744 #define CAN_F7R2_FB18 0x00040000U
2745 #define CAN_F7R2_FB19 0x00080000U
2746 #define CAN_F7R2_FB20 0x00100000U
2747 #define CAN_F7R2_FB21 0x00200000U
2748 #define CAN_F7R2_FB22 0x00400000U
2749 #define CAN_F7R2_FB23 0x00800000U
2750 #define CAN_F7R2_FB24 0x01000000U
2751 #define CAN_F7R2_FB25 0x02000000U
2752 #define CAN_F7R2_FB26 0x04000000U
2753 #define CAN_F7R2_FB27 0x08000000U
2754 #define CAN_F7R2_FB28 0x10000000U
2755 #define CAN_F7R2_FB29 0x20000000U
2756 #define CAN_F7R2_FB30 0x40000000U
2757 #define CAN_F7R2_FB31 0x80000000U
2759 /******************* Bit definition for CAN_F8R2 register *******************/
2760 #define CAN_F8R2_FB0 0x00000001U
2761 #define CAN_F8R2_FB1 0x00000002U
2762 #define CAN_F8R2_FB2 0x00000004U
2763 #define CAN_F8R2_FB3 0x00000008U
2764 #define CAN_F8R2_FB4 0x00000010U
2765 #define CAN_F8R2_FB5 0x00000020U
2766 #define CAN_F8R2_FB6 0x00000040U
2767 #define CAN_F8R2_FB7 0x00000080U
2768 #define CAN_F8R2_FB8 0x00000100U
2769 #define CAN_F8R2_FB9 0x00000200U
2770 #define CAN_F8R2_FB10 0x00000400U
2771 #define CAN_F8R2_FB11 0x00000800U
2772 #define CAN_F8R2_FB12 0x00001000U
2773 #define CAN_F8R2_FB13 0x00002000U
2774 #define CAN_F8R2_FB14 0x00004000U
2775 #define CAN_F8R2_FB15 0x00008000U
2776 #define CAN_F8R2_FB16 0x00010000U
2777 #define CAN_F8R2_FB17 0x00020000U
2778 #define CAN_F8R2_FB18 0x00040000U
2779 #define CAN_F8R2_FB19 0x00080000U
2780 #define CAN_F8R2_FB20 0x00100000U
2781 #define CAN_F8R2_FB21 0x00200000U
2782 #define CAN_F8R2_FB22 0x00400000U
2783 #define CAN_F8R2_FB23 0x00800000U
2784 #define CAN_F8R2_FB24 0x01000000U
2785 #define CAN_F8R2_FB25 0x02000000U
2786 #define CAN_F8R2_FB26 0x04000000U
2787 #define CAN_F8R2_FB27 0x08000000U
2788 #define CAN_F8R2_FB28 0x10000000U
2789 #define CAN_F8R2_FB29 0x20000000U
2790 #define CAN_F8R2_FB30 0x40000000U
2791 #define CAN_F8R2_FB31 0x80000000U
2793 /******************* Bit definition for CAN_F9R2 register *******************/
2794 #define CAN_F9R2_FB0 0x00000001U
2795 #define CAN_F9R2_FB1 0x00000002U
2796 #define CAN_F9R2_FB2 0x00000004U
2797 #define CAN_F9R2_FB3 0x00000008U
2798 #define CAN_F9R2_FB4 0x00000010U
2799 #define CAN_F9R2_FB5 0x00000020U
2800 #define CAN_F9R2_FB6 0x00000040U
2801 #define CAN_F9R2_FB7 0x00000080U
2802 #define CAN_F9R2_FB8 0x00000100U
2803 #define CAN_F9R2_FB9 0x00000200U
2804 #define CAN_F9R2_FB10 0x00000400U
2805 #define CAN_F9R2_FB11 0x00000800U
2806 #define CAN_F9R2_FB12 0x00001000U
2807 #define CAN_F9R2_FB13 0x00002000U
2808 #define CAN_F9R2_FB14 0x00004000U
2809 #define CAN_F9R2_FB15 0x00008000U
2810 #define CAN_F9R2_FB16 0x00010000U
2811 #define CAN_F9R2_FB17 0x00020000U
2812 #define CAN_F9R2_FB18 0x00040000U
2813 #define CAN_F9R2_FB19 0x00080000U
2814 #define CAN_F9R2_FB20 0x00100000U
2815 #define CAN_F9R2_FB21 0x00200000U
2816 #define CAN_F9R2_FB22 0x00400000U
2817 #define CAN_F9R2_FB23 0x00800000U
2818 #define CAN_F9R2_FB24 0x01000000U
2819 #define CAN_F9R2_FB25 0x02000000U
2820 #define CAN_F9R2_FB26 0x04000000U
2821 #define CAN_F9R2_FB27 0x08000000U
2822 #define CAN_F9R2_FB28 0x10000000U
2823 #define CAN_F9R2_FB29 0x20000000U
2824 #define CAN_F9R2_FB30 0x40000000U
2825 #define CAN_F9R2_FB31 0x80000000U
2827 /******************* Bit definition for CAN_F10R2 register ******************/
2828 #define CAN_F10R2_FB0 0x00000001U
2829 #define CAN_F10R2_FB1 0x00000002U
2830 #define CAN_F10R2_FB2 0x00000004U
2831 #define CAN_F10R2_FB3 0x00000008U
2832 #define CAN_F10R2_FB4 0x00000010U
2833 #define CAN_F10R2_FB5 0x00000020U
2834 #define CAN_F10R2_FB6 0x00000040U
2835 #define CAN_F10R2_FB7 0x00000080U
2836 #define CAN_F10R2_FB8 0x00000100U
2837 #define CAN_F10R2_FB9 0x00000200U
2838 #define CAN_F10R2_FB10 0x00000400U
2839 #define CAN_F10R2_FB11 0x00000800U
2840 #define CAN_F10R2_FB12 0x00001000U
2841 #define CAN_F10R2_FB13 0x00002000U
2842 #define CAN_F10R2_FB14 0x00004000U
2843 #define CAN_F10R2_FB15 0x00008000U
2844 #define CAN_F10R2_FB16 0x00010000U
2845 #define CAN_F10R2_FB17 0x00020000U
2846 #define CAN_F10R2_FB18 0x00040000U
2847 #define CAN_F10R2_FB19 0x00080000U
2848 #define CAN_F10R2_FB20 0x00100000U
2849 #define CAN_F10R2_FB21 0x00200000U
2850 #define CAN_F10R2_FB22 0x00400000U
2851 #define CAN_F10R2_FB23 0x00800000U
2852 #define CAN_F10R2_FB24 0x01000000U
2853 #define CAN_F10R2_FB25 0x02000000U
2854 #define CAN_F10R2_FB26 0x04000000U
2855 #define CAN_F10R2_FB27 0x08000000U
2856 #define CAN_F10R2_FB28 0x10000000U
2857 #define CAN_F10R2_FB29 0x20000000U
2858 #define CAN_F10R2_FB30 0x40000000U
2859 #define CAN_F10R2_FB31 0x80000000U
2861 /******************* Bit definition for CAN_F11R2 register ******************/
2862 #define CAN_F11R2_FB0 0x00000001U
2863 #define CAN_F11R2_FB1 0x00000002U
2864 #define CAN_F11R2_FB2 0x00000004U
2865 #define CAN_F11R2_FB3 0x00000008U
2866 #define CAN_F11R2_FB4 0x00000010U
2867 #define CAN_F11R2_FB5 0x00000020U
2868 #define CAN_F11R2_FB6 0x00000040U
2869 #define CAN_F11R2_FB7 0x00000080U
2870 #define CAN_F11R2_FB8 0x00000100U
2871 #define CAN_F11R2_FB9 0x00000200U
2872 #define CAN_F11R2_FB10 0x00000400U
2873 #define CAN_F11R2_FB11 0x00000800U
2874 #define CAN_F11R2_FB12 0x00001000U
2875 #define CAN_F11R2_FB13 0x00002000U
2876 #define CAN_F11R2_FB14 0x00004000U
2877 #define CAN_F11R2_FB15 0x00008000U
2878 #define CAN_F11R2_FB16 0x00010000U
2879 #define CAN_F11R2_FB17 0x00020000U
2880 #define CAN_F11R2_FB18 0x00040000U
2881 #define CAN_F11R2_FB19 0x00080000U
2882 #define CAN_F11R2_FB20 0x00100000U
2883 #define CAN_F11R2_FB21 0x00200000U
2884 #define CAN_F11R2_FB22 0x00400000U
2885 #define CAN_F11R2_FB23 0x00800000U
2886 #define CAN_F11R2_FB24 0x01000000U
2887 #define CAN_F11R2_FB25 0x02000000U
2888 #define CAN_F11R2_FB26 0x04000000U
2889 #define CAN_F11R2_FB27 0x08000000U
2890 #define CAN_F11R2_FB28 0x10000000U
2891 #define CAN_F11R2_FB29 0x20000000U
2892 #define CAN_F11R2_FB30 0x40000000U
2893 #define CAN_F11R2_FB31 0x80000000U
2895 /******************* Bit definition for CAN_F12R2 register ******************/
2896 #define CAN_F12R2_FB0 0x00000001U
2897 #define CAN_F12R2_FB1 0x00000002U
2898 #define CAN_F12R2_FB2 0x00000004U
2899 #define CAN_F12R2_FB3 0x00000008U
2900 #define CAN_F12R2_FB4 0x00000010U
2901 #define CAN_F12R2_FB5 0x00000020U
2902 #define CAN_F12R2_FB6 0x00000040U
2903 #define CAN_F12R2_FB7 0x00000080U
2904 #define CAN_F12R2_FB8 0x00000100U
2905 #define CAN_F12R2_FB9 0x00000200U
2906 #define CAN_F12R2_FB10 0x00000400U
2907 #define CAN_F12R2_FB11 0x00000800U
2908 #define CAN_F12R2_FB12 0x00001000U
2909 #define CAN_F12R2_FB13 0x00002000U
2910 #define CAN_F12R2_FB14 0x00004000U
2911 #define CAN_F12R2_FB15 0x00008000U
2912 #define CAN_F12R2_FB16 0x00010000U
2913 #define CAN_F12R2_FB17 0x00020000U
2914 #define CAN_F12R2_FB18 0x00040000U
2915 #define CAN_F12R2_FB19 0x00080000U
2916 #define CAN_F12R2_FB20 0x00100000U
2917 #define CAN_F12R2_FB21 0x00200000U
2918 #define CAN_F12R2_FB22 0x00400000U
2919 #define CAN_F12R2_FB23 0x00800000U
2920 #define CAN_F12R2_FB24 0x01000000U
2921 #define CAN_F12R2_FB25 0x02000000U
2922 #define CAN_F12R2_FB26 0x04000000U
2923 #define CAN_F12R2_FB27 0x08000000U
2924 #define CAN_F12R2_FB28 0x10000000U
2925 #define CAN_F12R2_FB29 0x20000000U
2926 #define CAN_F12R2_FB30 0x40000000U
2927 #define CAN_F12R2_FB31 0x80000000U
2929 /******************* Bit definition for CAN_F13R2 register ******************/
2930 #define CAN_F13R2_FB0 0x00000001U
2931 #define CAN_F13R2_FB1 0x00000002U
2932 #define CAN_F13R2_FB2 0x00000004U
2933 #define CAN_F13R2_FB3 0x00000008U
2934 #define CAN_F13R2_FB4 0x00000010U
2935 #define CAN_F13R2_FB5 0x00000020U
2936 #define CAN_F13R2_FB6 0x00000040U
2937 #define CAN_F13R2_FB7 0x00000080U
2938 #define CAN_F13R2_FB8 0x00000100U
2939 #define CAN_F13R2_FB9 0x00000200U
2940 #define CAN_F13R2_FB10 0x00000400U
2941 #define CAN_F13R2_FB11 0x00000800U
2942 #define CAN_F13R2_FB12 0x00001000U
2943 #define CAN_F13R2_FB13 0x00002000U
2944 #define CAN_F13R2_FB14 0x00004000U
2945 #define CAN_F13R2_FB15 0x00008000U
2946 #define CAN_F13R2_FB16 0x00010000U
2947 #define CAN_F13R2_FB17 0x00020000U
2948 #define CAN_F13R2_FB18 0x00040000U
2949 #define CAN_F13R2_FB19 0x00080000U
2950 #define CAN_F13R2_FB20 0x00100000U
2951 #define CAN_F13R2_FB21 0x00200000U
2952 #define CAN_F13R2_FB22 0x00400000U
2953 #define CAN_F13R2_FB23 0x00800000U
2954 #define CAN_F13R2_FB24 0x01000000U
2955 #define CAN_F13R2_FB25 0x02000000U
2956 #define CAN_F13R2_FB26 0x04000000U
2957 #define CAN_F13R2_FB27 0x08000000U
2958 #define CAN_F13R2_FB28 0x10000000U
2959 #define CAN_F13R2_FB29 0x20000000U
2960 #define CAN_F13R2_FB30 0x40000000U
2961 #define CAN_F13R2_FB31 0x80000000U
2963 /******************************************************************************/
2964 /* */
2965 /* CRC calculation unit */
2966 /* */
2967 /******************************************************************************/
2968 /******************* Bit definition for CRC_DR register *********************/
2969 #define CRC_DR_DR 0xFFFFFFFFU
2972 /******************* Bit definition for CRC_IDR register ********************/
2973 #define CRC_IDR_IDR 0xFFU
2976 /******************** Bit definition for CRC_CR register ********************/
2977 #define CRC_CR_RESET 0x01U
2979 /******************************************************************************/
2980 /* */
2981 /* Digital to Analog Converter */
2982 /* */
2983 /******************************************************************************/
2984 /******************** Bit definition for DAC_CR register ********************/
2985 #define DAC_CR_EN1 0x00000001U
2986 #define DAC_CR_BOFF1 0x00000002U
2987 #define DAC_CR_TEN1 0x00000004U
2989 #define DAC_CR_TSEL1 0x00000038U
2990 #define DAC_CR_TSEL1_0 0x00000008U
2991 #define DAC_CR_TSEL1_1 0x00000010U
2992 #define DAC_CR_TSEL1_2 0x00000020U
2994 #define DAC_CR_WAVE1 0x000000C0U
2995 #define DAC_CR_WAVE1_0 0x00000040U
2996 #define DAC_CR_WAVE1_1 0x00000080U
2998 #define DAC_CR_MAMP1 0x00000F00U
2999 #define DAC_CR_MAMP1_0 0x00000100U
3000 #define DAC_CR_MAMP1_1 0x00000200U
3001 #define DAC_CR_MAMP1_2 0x00000400U
3002 #define DAC_CR_MAMP1_3 0x00000800U
3004 #define DAC_CR_DMAEN1 0x00001000U
3005 #define DAC_CR_DMAUDRIE1 0x00002000U
3006 #define DAC_CR_EN2 0x00010000U
3007 #define DAC_CR_BOFF2 0x00020000U
3008 #define DAC_CR_TEN2 0x00040000U
3010 #define DAC_CR_TSEL2 0x00380000U
3011 #define DAC_CR_TSEL2_0 0x00080000U
3012 #define DAC_CR_TSEL2_1 0x00100000U
3013 #define DAC_CR_TSEL2_2 0x00200000U
3015 #define DAC_CR_WAVE2 0x00C00000U
3016 #define DAC_CR_WAVE2_0 0x00400000U
3017 #define DAC_CR_WAVE2_1 0x00800000U
3019 #define DAC_CR_MAMP2 0x0F000000U
3020 #define DAC_CR_MAMP2_0 0x01000000U
3021 #define DAC_CR_MAMP2_1 0x02000000U
3022 #define DAC_CR_MAMP2_2 0x04000000U
3023 #define DAC_CR_MAMP2_3 0x08000000U
3025 #define DAC_CR_DMAEN2 0x10000000U
3026 #define DAC_CR_DMAUDRIE2 0x20000000U
3028 /***************** Bit definition for DAC_SWTRIGR register ******************/
3029 #define DAC_SWTRIGR_SWTRIG1 0x01U
3030 #define DAC_SWTRIGR_SWTRIG2 0x02U
3032 /***************** Bit definition for DAC_DHR12R1 register ******************/
3033 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3035 /***************** Bit definition for DAC_DHR12L1 register ******************/
3036 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3038 /****************** Bit definition for DAC_DHR8R1 register ******************/
3039 #define DAC_DHR8R1_DACC1DHR 0xFFU
3041 /***************** Bit definition for DAC_DHR12R2 register ******************/
3042 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3044 /***************** Bit definition for DAC_DHR12L2 register ******************/
3045 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3047 /****************** Bit definition for DAC_DHR8R2 register ******************/
3048 #define DAC_DHR8R2_DACC2DHR 0xFFU
3050 /***************** Bit definition for DAC_DHR12RD register ******************/
3051 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3052 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3054 /***************** Bit definition for DAC_DHR12LD register ******************/
3055 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3056 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3058 /****************** Bit definition for DAC_DHR8RD register ******************/
3059 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3060 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3062 /******************* Bit definition for DAC_DOR1 register *******************/
3063 #define DAC_DOR1_DACC1DOR 0x0FFFU
3065 /******************* Bit definition for DAC_DOR2 register *******************/
3066 #define DAC_DOR2_DACC2DOR 0x0FFFU
3068 /******************** Bit definition for DAC_SR register ********************/
3069 #define DAC_SR_DMAUDR1 0x00002000U
3070 #define DAC_SR_DMAUDR2 0x20000000U
3072 /******************************************************************************/
3073 /* */
3074 /* Debug MCU */
3075 /* */
3076 /******************************************************************************/
3077 
3078 /******************************************************************************/
3079 /* */
3080 /* DCMI */
3081 /* */
3082 /******************************************************************************/
3083 /******************** Bits definition for DCMI_CR register ******************/
3084 #define DCMI_CR_CAPTURE 0x00000001U
3085 #define DCMI_CR_CM 0x00000002U
3086 #define DCMI_CR_CROP 0x00000004U
3087 #define DCMI_CR_JPEG 0x00000008U
3088 #define DCMI_CR_ESS 0x00000010U
3089 #define DCMI_CR_PCKPOL 0x00000020U
3090 #define DCMI_CR_HSPOL 0x00000040U
3091 #define DCMI_CR_VSPOL 0x00000080U
3092 #define DCMI_CR_FCRC_0 0x00000100U
3093 #define DCMI_CR_FCRC_1 0x00000200U
3094 #define DCMI_CR_EDM_0 0x00000400U
3095 #define DCMI_CR_EDM_1 0x00000800U
3096 #define DCMI_CR_CRE 0x00001000U
3097 #define DCMI_CR_ENABLE 0x00004000U
3098 
3099 /******************** Bits definition for DCMI_SR register ******************/
3100 #define DCMI_SR_HSYNC 0x00000001U
3101 #define DCMI_SR_VSYNC 0x00000002U
3102 #define DCMI_SR_FNE 0x00000004U
3103 
3104 /******************** Bits definition for DCMI_RIS register *****************/
3105 #define DCMI_RIS_FRAME_RIS 0x00000001U
3106 #define DCMI_RIS_OVR_RIS 0x00000002U
3107 #define DCMI_RIS_ERR_RIS 0x00000004U
3108 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3109 #define DCMI_RIS_LINE_RIS 0x00000010U
3110 /* Legacy defines */
3111 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3112 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
3113 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3114 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3115 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3116 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3117 
3118 /******************** Bits definition for DCMI_IER register *****************/
3119 #define DCMI_IER_FRAME_IE 0x00000001U
3120 #define DCMI_IER_OVR_IE 0x00000002U
3121 #define DCMI_IER_ERR_IE 0x00000004U
3122 #define DCMI_IER_VSYNC_IE 0x00000008U
3123 #define DCMI_IER_LINE_IE 0x00000010U
3124 /* Legacy defines */
3125 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3126 
3127 /******************** Bits definition for DCMI_MIS register *****************/
3128 #define DCMI_MIS_FRAME_MIS 0x00000001U
3129 #define DCMI_MIS_OVR_MIS 0x00000002U
3130 #define DCMI_MIS_ERR_MIS 0x00000004U
3131 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3132 #define DCMI_MIS_LINE_MIS 0x00000010U
3133 
3134 /* Legacy defines */
3135 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3136 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3137 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3138 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3139 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3140 
3141 /******************** Bits definition for DCMI_ICR register *****************/
3142 #define DCMI_ICR_FRAME_ISC 0x00000001U
3143 #define DCMI_ICR_OVR_ISC 0x00000002U
3144 #define DCMI_ICR_ERR_ISC 0x00000004U
3145 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3146 #define DCMI_ICR_LINE_ISC 0x00000010U
3147 
3148 /* Legacy defines */
3149 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3150 
3151 /******************** Bits definition for DCMI_ESCR register ******************/
3152 #define DCMI_ESCR_FSC 0x000000FFU
3153 #define DCMI_ESCR_LSC 0x0000FF00U
3154 #define DCMI_ESCR_LEC 0x00FF0000U
3155 #define DCMI_ESCR_FEC 0xFF000000U
3156 
3157 /******************** Bits definition for DCMI_ESUR register ******************/
3158 #define DCMI_ESUR_FSU 0x000000FFU
3159 #define DCMI_ESUR_LSU 0x0000FF00U
3160 #define DCMI_ESUR_LEU 0x00FF0000U
3161 #define DCMI_ESUR_FEU 0xFF000000U
3162 
3163 /******************** Bits definition for DCMI_CWSTRT register ******************/
3164 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3165 #define DCMI_CWSTRT_VST 0x1FFF0000U
3166 
3167 /******************** Bits definition for DCMI_CWSIZE register ******************/
3168 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3169 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3170 
3171 /******************** Bits definition for DCMI_DR register ******************/
3172 #define DCMI_DR_BYTE0 0x000000FFU
3173 #define DCMI_DR_BYTE1 0x0000FF00U
3174 #define DCMI_DR_BYTE2 0x00FF0000U
3175 #define DCMI_DR_BYTE3 0xFF000000U
3176 
3177 /******************************************************************************/
3178 /* */
3179 /* DMA Controller */
3180 /* */
3181 /******************************************************************************/
3182 /******************** Bits definition for DMA_SxCR register *****************/
3183 #define DMA_SxCR_CHSEL 0x0E000000U
3184 #define DMA_SxCR_CHSEL_0 0x02000000U
3185 #define DMA_SxCR_CHSEL_1 0x04000000U
3186 #define DMA_SxCR_CHSEL_2 0x08000000U
3187 #define DMA_SxCR_MBURST 0x01800000U
3188 #define DMA_SxCR_MBURST_0 0x00800000U
3189 #define DMA_SxCR_MBURST_1 0x01000000U
3190 #define DMA_SxCR_PBURST 0x00600000U
3191 #define DMA_SxCR_PBURST_0 0x00200000U
3192 #define DMA_SxCR_PBURST_1 0x00400000U
3193 #define DMA_SxCR_CT 0x00080000U
3194 #define DMA_SxCR_DBM 0x00040000U
3195 #define DMA_SxCR_PL 0x00030000U
3196 #define DMA_SxCR_PL_0 0x00010000U
3197 #define DMA_SxCR_PL_1 0x00020000U
3198 #define DMA_SxCR_PINCOS 0x00008000U
3199 #define DMA_SxCR_MSIZE 0x00006000U
3200 #define DMA_SxCR_MSIZE_0 0x00002000U
3201 #define DMA_SxCR_MSIZE_1 0x00004000U
3202 #define DMA_SxCR_PSIZE 0x00001800U
3203 #define DMA_SxCR_PSIZE_0 0x00000800U
3204 #define DMA_SxCR_PSIZE_1 0x00001000U
3205 #define DMA_SxCR_MINC 0x00000400U
3206 #define DMA_SxCR_PINC 0x00000200U
3207 #define DMA_SxCR_CIRC 0x00000100U
3208 #define DMA_SxCR_DIR 0x000000C0U
3209 #define DMA_SxCR_DIR_0 0x00000040U
3210 #define DMA_SxCR_DIR_1 0x00000080U
3211 #define DMA_SxCR_PFCTRL 0x00000020U
3212 #define DMA_SxCR_TCIE 0x00000010U
3213 #define DMA_SxCR_HTIE 0x00000008U
3214 #define DMA_SxCR_TEIE 0x00000004U
3215 #define DMA_SxCR_DMEIE 0x00000002U
3216 #define DMA_SxCR_EN 0x00000001U
3217 
3218 /* Legacy defines */
3219 #define DMA_SxCR_ACK 0x00100000U
3220 
3221 /******************** Bits definition for DMA_SxCNDTR register **************/
3222 #define DMA_SxNDT 0x0000FFFFU
3223 #define DMA_SxNDT_0 0x00000001U
3224 #define DMA_SxNDT_1 0x00000002U
3225 #define DMA_SxNDT_2 0x00000004U
3226 #define DMA_SxNDT_3 0x00000008U
3227 #define DMA_SxNDT_4 0x00000010U
3228 #define DMA_SxNDT_5 0x00000020U
3229 #define DMA_SxNDT_6 0x00000040U
3230 #define DMA_SxNDT_7 0x00000080U
3231 #define DMA_SxNDT_8 0x00000100U
3232 #define DMA_SxNDT_9 0x00000200U
3233 #define DMA_SxNDT_10 0x00000400U
3234 #define DMA_SxNDT_11 0x00000800U
3235 #define DMA_SxNDT_12 0x00001000U
3236 #define DMA_SxNDT_13 0x00002000U
3237 #define DMA_SxNDT_14 0x00004000U
3238 #define DMA_SxNDT_15 0x00008000U
3239 
3240 /******************** Bits definition for DMA_SxFCR register ****************/
3241 #define DMA_SxFCR_FEIE 0x00000080U
3242 #define DMA_SxFCR_FS 0x00000038U
3243 #define DMA_SxFCR_FS_0 0x00000008U
3244 #define DMA_SxFCR_FS_1 0x00000010U
3245 #define DMA_SxFCR_FS_2 0x00000020U
3246 #define DMA_SxFCR_DMDIS 0x00000004U
3247 #define DMA_SxFCR_FTH 0x00000003U
3248 #define DMA_SxFCR_FTH_0 0x00000001U
3249 #define DMA_SxFCR_FTH_1 0x00000002U
3250 
3251 /******************** Bits definition for DMA_LISR register *****************/
3252 #define DMA_LISR_TCIF3 0x08000000U
3253 #define DMA_LISR_HTIF3 0x04000000U
3254 #define DMA_LISR_TEIF3 0x02000000U
3255 #define DMA_LISR_DMEIF3 0x01000000U
3256 #define DMA_LISR_FEIF3 0x00400000U
3257 #define DMA_LISR_TCIF2 0x00200000U
3258 #define DMA_LISR_HTIF2 0x00100000U
3259 #define DMA_LISR_TEIF2 0x00080000U
3260 #define DMA_LISR_DMEIF2 0x00040000U
3261 #define DMA_LISR_FEIF2 0x00010000U
3262 #define DMA_LISR_TCIF1 0x00000800U
3263 #define DMA_LISR_HTIF1 0x00000400U
3264 #define DMA_LISR_TEIF1 0x00000200U
3265 #define DMA_LISR_DMEIF1 0x00000100U
3266 #define DMA_LISR_FEIF1 0x00000040U
3267 #define DMA_LISR_TCIF0 0x00000020U
3268 #define DMA_LISR_HTIF0 0x00000010U
3269 #define DMA_LISR_TEIF0 0x00000008U
3270 #define DMA_LISR_DMEIF0 0x00000004U
3271 #define DMA_LISR_FEIF0 0x00000001U
3272 
3273 /******************** Bits definition for DMA_HISR register *****************/
3274 #define DMA_HISR_TCIF7 0x08000000U
3275 #define DMA_HISR_HTIF7 0x04000000U
3276 #define DMA_HISR_TEIF7 0x02000000U
3277 #define DMA_HISR_DMEIF7 0x01000000U
3278 #define DMA_HISR_FEIF7 0x00400000U
3279 #define DMA_HISR_TCIF6 0x00200000U
3280 #define DMA_HISR_HTIF6 0x00100000U
3281 #define DMA_HISR_TEIF6 0x00080000U
3282 #define DMA_HISR_DMEIF6 0x00040000U
3283 #define DMA_HISR_FEIF6 0x00010000U
3284 #define DMA_HISR_TCIF5 0x00000800U
3285 #define DMA_HISR_HTIF5 0x00000400U
3286 #define DMA_HISR_TEIF5 0x00000200U
3287 #define DMA_HISR_DMEIF5 0x00000100U
3288 #define DMA_HISR_FEIF5 0x00000040U
3289 #define DMA_HISR_TCIF4 0x00000020U
3290 #define DMA_HISR_HTIF4 0x00000010U
3291 #define DMA_HISR_TEIF4 0x00000008U
3292 #define DMA_HISR_DMEIF4 0x00000004U
3293 #define DMA_HISR_FEIF4 0x00000001U
3294 
3295 /******************** Bits definition for DMA_LIFCR register ****************/
3296 #define DMA_LIFCR_CTCIF3 0x08000000U
3297 #define DMA_LIFCR_CHTIF3 0x04000000U
3298 #define DMA_LIFCR_CTEIF3 0x02000000U
3299 #define DMA_LIFCR_CDMEIF3 0x01000000U
3300 #define DMA_LIFCR_CFEIF3 0x00400000U
3301 #define DMA_LIFCR_CTCIF2 0x00200000U
3302 #define DMA_LIFCR_CHTIF2 0x00100000U
3303 #define DMA_LIFCR_CTEIF2 0x00080000U
3304 #define DMA_LIFCR_CDMEIF2 0x00040000U
3305 #define DMA_LIFCR_CFEIF2 0x00010000U
3306 #define DMA_LIFCR_CTCIF1 0x00000800U
3307 #define DMA_LIFCR_CHTIF1 0x00000400U
3308 #define DMA_LIFCR_CTEIF1 0x00000200U
3309 #define DMA_LIFCR_CDMEIF1 0x00000100U
3310 #define DMA_LIFCR_CFEIF1 0x00000040U
3311 #define DMA_LIFCR_CTCIF0 0x00000020U
3312 #define DMA_LIFCR_CHTIF0 0x00000010U
3313 #define DMA_LIFCR_CTEIF0 0x00000008U
3314 #define DMA_LIFCR_CDMEIF0 0x00000004U
3315 #define DMA_LIFCR_CFEIF0 0x00000001U
3316 
3317 /******************** Bits definition for DMA_HIFCR register ****************/
3318 #define DMA_HIFCR_CTCIF7 0x08000000U
3319 #define DMA_HIFCR_CHTIF7 0x04000000U
3320 #define DMA_HIFCR_CTEIF7 0x02000000U
3321 #define DMA_HIFCR_CDMEIF7 0x01000000U
3322 #define DMA_HIFCR_CFEIF7 0x00400000U
3323 #define DMA_HIFCR_CTCIF6 0x00200000U
3324 #define DMA_HIFCR_CHTIF6 0x00100000U
3325 #define DMA_HIFCR_CTEIF6 0x00080000U
3326 #define DMA_HIFCR_CDMEIF6 0x00040000U
3327 #define DMA_HIFCR_CFEIF6 0x00010000U
3328 #define DMA_HIFCR_CTCIF5 0x00000800U
3329 #define DMA_HIFCR_CHTIF5 0x00000400U
3330 #define DMA_HIFCR_CTEIF5 0x00000200U
3331 #define DMA_HIFCR_CDMEIF5 0x00000100U
3332 #define DMA_HIFCR_CFEIF5 0x00000040U
3333 #define DMA_HIFCR_CTCIF4 0x00000020U
3334 #define DMA_HIFCR_CHTIF4 0x00000010U
3335 #define DMA_HIFCR_CTEIF4 0x00000008U
3336 #define DMA_HIFCR_CDMEIF4 0x00000004U
3337 #define DMA_HIFCR_CFEIF4 0x00000001U
3338 
3339 
3340 /******************************************************************************/
3341 /* */
3342 /* AHB Master DMA2D Controller (DMA2D) */
3343 /* */
3344 /******************************************************************************/
3345 
3346 /******************** Bit definition for DMA2D_CR register ******************/
3347 
3348 #define DMA2D_CR_START 0x00000001U
3349 #define DMA2D_CR_SUSP 0x00000002U
3350 #define DMA2D_CR_ABORT 0x00000004U
3351 #define DMA2D_CR_TEIE 0x00000100U
3352 #define DMA2D_CR_TCIE 0x00000200U
3353 #define DMA2D_CR_TWIE 0x00000400U
3354 #define DMA2D_CR_CAEIE 0x00000800U
3355 #define DMA2D_CR_CTCIE 0x00001000U
3356 #define DMA2D_CR_CEIE 0x00002000U
3357 #define DMA2D_CR_MODE 0x00030000U
3358 #define DMA2D_CR_MODE_0 0x00010000U
3359 #define DMA2D_CR_MODE_1 0x00020000U
3361 /******************** Bit definition for DMA2D_ISR register *****************/
3362 
3363 #define DMA2D_ISR_TEIF 0x00000001U
3364 #define DMA2D_ISR_TCIF 0x00000002U
3365 #define DMA2D_ISR_TWIF 0x00000004U
3366 #define DMA2D_ISR_CAEIF 0x00000008U
3367 #define DMA2D_ISR_CTCIF 0x00000010U
3368 #define DMA2D_ISR_CEIF 0x00000020U
3370 /******************** Bit definition for DMA2D_IFCR register ****************/
3371 
3372 #define DMA2D_IFCR_CTEIF 0x00000001U
3373 #define DMA2D_IFCR_CTCIF 0x00000002U
3374 #define DMA2D_IFCR_CTWIF 0x00000004U
3375 #define DMA2D_IFCR_CAECIF 0x00000008U
3376 #define DMA2D_IFCR_CCTCIF 0x00000010U
3377 #define DMA2D_IFCR_CCEIF 0x00000020U
3379 /* Legacy defines */
3380 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3381 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3382 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3383 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3384 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3385 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3387 /******************** Bit definition for DMA2D_FGMAR register ***************/
3388 
3389 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3391 /******************** Bit definition for DMA2D_FGOR register ****************/
3392 
3393 #define DMA2D_FGOR_LO 0x00003FFFU
3395 /******************** Bit definition for DMA2D_BGMAR register ***************/
3396 
3397 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3399 /******************** Bit definition for DMA2D_BGOR register ****************/
3400 
3401 #define DMA2D_BGOR_LO 0x00003FFFU
3403 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3404 
3405 #define DMA2D_FGPFCCR_CM 0x0000000FU
3406 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3407 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3408 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3409 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3410 #define DMA2D_FGPFCCR_CCM 0x00000010U
3411 #define DMA2D_FGPFCCR_START 0x00000020U
3412 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3413 #define DMA2D_FGPFCCR_AM 0x00030000U
3414 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3415 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3416 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3418 /******************** Bit definition for DMA2D_FGCOLR register **************/
3419 
3420 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3421 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3422 #define DMA2D_FGCOLR_RED 0x00FF0000U
3424 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3425 
3426 #define DMA2D_BGPFCCR_CM 0x0000000FU
3427 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3428 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3429 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3430 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3431 #define DMA2D_BGPFCCR_CCM 0x00000010U
3432 #define DMA2D_BGPFCCR_START 0x00000020U
3433 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3434 #define DMA2D_BGPFCCR_AM 0x00030000U
3435 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3436 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3437 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3439 /******************** Bit definition for DMA2D_BGCOLR register **************/
3440 
3441 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3442 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3443 #define DMA2D_BGCOLR_RED 0x00FF0000U
3445 /******************** Bit definition for DMA2D_FGCMAR register **************/
3446 
3447 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3449 /******************** Bit definition for DMA2D_BGCMAR register **************/
3450 
3451 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3453 /******************** Bit definition for DMA2D_OPFCCR register **************/
3454 
3455 #define DMA2D_OPFCCR_CM 0x00000007U
3456 #define DMA2D_OPFCCR_CM_0 0x00000001U
3457 #define DMA2D_OPFCCR_CM_1 0x00000002U
3458 #define DMA2D_OPFCCR_CM_2 0x00000004U
3460 /******************** Bit definition for DMA2D_OCOLR register ***************/
3461 
3464 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3465 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3466 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3467 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3470 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3471 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3472 #define DMA2D_OCOLR_RED_2 0x0000F800U
3475 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3476 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3477 #define DMA2D_OCOLR_RED_3 0x00007C00U
3478 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3481 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3482 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3483 #define DMA2D_OCOLR_RED_4 0x00000F00U
3484 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3486 /******************** Bit definition for DMA2D_OMAR register ****************/
3487 
3488 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3490 /******************** Bit definition for DMA2D_OOR register *****************/
3491 
3492 #define DMA2D_OOR_LO 0x00003FFFU
3494 /******************** Bit definition for DMA2D_NLR register *****************/
3495 
3496 #define DMA2D_NLR_NL 0x0000FFFFU
3497 #define DMA2D_NLR_PL 0x3FFF0000U
3499 /******************** Bit definition for DMA2D_LWR register *****************/
3500 
3501 #define DMA2D_LWR_LW 0x0000FFFFU
3503 /******************** Bit definition for DMA2D_AMTCR register ***************/
3504 
3505 #define DMA2D_AMTCR_EN 0x00000001U
3506 #define DMA2D_AMTCR_DT 0x0000FF00U
3508 /******************** Bit definition for DMA2D_FGCLUT register **************/
3509 
3510 /******************** Bit definition for DMA2D_BGCLUT register **************/
3511 
3512 
3513 
3514 /******************************************************************************/
3515 /* */
3516 /* External Interrupt/Event Controller */
3517 /* */
3518 /******************************************************************************/
3519 /******************* Bit definition for EXTI_IMR register *******************/
3520 #define EXTI_IMR_MR0 0x00000001U
3521 #define EXTI_IMR_MR1 0x00000002U
3522 #define EXTI_IMR_MR2 0x00000004U
3523 #define EXTI_IMR_MR3 0x00000008U
3524 #define EXTI_IMR_MR4 0x00000010U
3525 #define EXTI_IMR_MR5 0x00000020U
3526 #define EXTI_IMR_MR6 0x00000040U
3527 #define EXTI_IMR_MR7 0x00000080U
3528 #define EXTI_IMR_MR8 0x00000100U
3529 #define EXTI_IMR_MR9 0x00000200U
3530 #define EXTI_IMR_MR10 0x00000400U
3531 #define EXTI_IMR_MR11 0x00000800U
3532 #define EXTI_IMR_MR12 0x00001000U
3533 #define EXTI_IMR_MR13 0x00002000U
3534 #define EXTI_IMR_MR14 0x00004000U
3535 #define EXTI_IMR_MR15 0x00008000U
3536 #define EXTI_IMR_MR16 0x00010000U
3537 #define EXTI_IMR_MR17 0x00020000U
3538 #define EXTI_IMR_MR18 0x00040000U
3539 #define EXTI_IMR_MR19 0x00080000U
3540 #define EXTI_IMR_MR20 0x00100000U
3541 #define EXTI_IMR_MR21 0x00200000U
3542 #define EXTI_IMR_MR22 0x00400000U
3544 /******************* Bit definition for EXTI_EMR register *******************/
3545 #define EXTI_EMR_MR0 0x00000001U
3546 #define EXTI_EMR_MR1 0x00000002U
3547 #define EXTI_EMR_MR2 0x00000004U
3548 #define EXTI_EMR_MR3 0x00000008U
3549 #define EXTI_EMR_MR4 0x00000010U
3550 #define EXTI_EMR_MR5 0x00000020U
3551 #define EXTI_EMR_MR6 0x00000040U
3552 #define EXTI_EMR_MR7 0x00000080U
3553 #define EXTI_EMR_MR8 0x00000100U
3554 #define EXTI_EMR_MR9 0x00000200U
3555 #define EXTI_EMR_MR10 0x00000400U
3556 #define EXTI_EMR_MR11 0x00000800U
3557 #define EXTI_EMR_MR12 0x00001000U
3558 #define EXTI_EMR_MR13 0x00002000U
3559 #define EXTI_EMR_MR14 0x00004000U
3560 #define EXTI_EMR_MR15 0x00008000U
3561 #define EXTI_EMR_MR16 0x00010000U
3562 #define EXTI_EMR_MR17 0x00020000U
3563 #define EXTI_EMR_MR18 0x00040000U
3564 #define EXTI_EMR_MR19 0x00080000U
3565 #define EXTI_EMR_MR20 0x00100000U
3566 #define EXTI_EMR_MR21 0x00200000U
3567 #define EXTI_EMR_MR22 0x00400000U
3569 /****************** Bit definition for EXTI_RTSR register *******************/
3570 #define EXTI_RTSR_TR0 0x00000001U
3571 #define EXTI_RTSR_TR1 0x00000002U
3572 #define EXTI_RTSR_TR2 0x00000004U
3573 #define EXTI_RTSR_TR3 0x00000008U
3574 #define EXTI_RTSR_TR4 0x00000010U
3575 #define EXTI_RTSR_TR5 0x00000020U
3576 #define EXTI_RTSR_TR6 0x00000040U
3577 #define EXTI_RTSR_TR7 0x00000080U
3578 #define EXTI_RTSR_TR8 0x00000100U
3579 #define EXTI_RTSR_TR9 0x00000200U
3580 #define EXTI_RTSR_TR10 0x00000400U
3581 #define EXTI_RTSR_TR11 0x00000800U
3582 #define EXTI_RTSR_TR12 0x00001000U
3583 #define EXTI_RTSR_TR13 0x00002000U
3584 #define EXTI_RTSR_TR14 0x00004000U
3585 #define EXTI_RTSR_TR15 0x00008000U
3586 #define EXTI_RTSR_TR16 0x00010000U
3587 #define EXTI_RTSR_TR17 0x00020000U
3588 #define EXTI_RTSR_TR18 0x00040000U
3589 #define EXTI_RTSR_TR19 0x00080000U
3590 #define EXTI_RTSR_TR20 0x00100000U
3591 #define EXTI_RTSR_TR21 0x00200000U
3592 #define EXTI_RTSR_TR22 0x00400000U
3594 /****************** Bit definition for EXTI_FTSR register *******************/
3595 #define EXTI_FTSR_TR0 0x00000001U
3596 #define EXTI_FTSR_TR1 0x00000002U
3597 #define EXTI_FTSR_TR2 0x00000004U
3598 #define EXTI_FTSR_TR3 0x00000008U
3599 #define EXTI_FTSR_TR4 0x00000010U
3600 #define EXTI_FTSR_TR5 0x00000020U
3601 #define EXTI_FTSR_TR6 0x00000040U
3602 #define EXTI_FTSR_TR7 0x00000080U
3603 #define EXTI_FTSR_TR8 0x00000100U
3604 #define EXTI_FTSR_TR9 0x00000200U
3605 #define EXTI_FTSR_TR10 0x00000400U
3606 #define EXTI_FTSR_TR11 0x00000800U
3607 #define EXTI_FTSR_TR12 0x00001000U
3608 #define EXTI_FTSR_TR13 0x00002000U
3609 #define EXTI_FTSR_TR14 0x00004000U
3610 #define EXTI_FTSR_TR15 0x00008000U
3611 #define EXTI_FTSR_TR16 0x00010000U
3612 #define EXTI_FTSR_TR17 0x00020000U
3613 #define EXTI_FTSR_TR18 0x00040000U
3614 #define EXTI_FTSR_TR19 0x00080000U
3615 #define EXTI_FTSR_TR20 0x00100000U
3616 #define EXTI_FTSR_TR21 0x00200000U
3617 #define EXTI_FTSR_TR22 0x00400000U
3619 /****************** Bit definition for EXTI_SWIER register ******************/
3620 #define EXTI_SWIER_SWIER0 0x00000001U
3621 #define EXTI_SWIER_SWIER1 0x00000002U
3622 #define EXTI_SWIER_SWIER2 0x00000004U
3623 #define EXTI_SWIER_SWIER3 0x00000008U
3624 #define EXTI_SWIER_SWIER4 0x00000010U
3625 #define EXTI_SWIER_SWIER5 0x00000020U
3626 #define EXTI_SWIER_SWIER6 0x00000040U
3627 #define EXTI_SWIER_SWIER7 0x00000080U
3628 #define EXTI_SWIER_SWIER8 0x00000100U
3629 #define EXTI_SWIER_SWIER9 0x00000200U
3630 #define EXTI_SWIER_SWIER10 0x00000400U
3631 #define EXTI_SWIER_SWIER11 0x00000800U
3632 #define EXTI_SWIER_SWIER12 0x00001000U
3633 #define EXTI_SWIER_SWIER13 0x00002000U
3634 #define EXTI_SWIER_SWIER14 0x00004000U
3635 #define EXTI_SWIER_SWIER15 0x00008000U
3636 #define EXTI_SWIER_SWIER16 0x00010000U
3637 #define EXTI_SWIER_SWIER17 0x00020000U
3638 #define EXTI_SWIER_SWIER18 0x00040000U
3639 #define EXTI_SWIER_SWIER19 0x00080000U
3640 #define EXTI_SWIER_SWIER20 0x00100000U
3641 #define EXTI_SWIER_SWIER21 0x00200000U
3642 #define EXTI_SWIER_SWIER22 0x00400000U
3644 /******************* Bit definition for EXTI_PR register ********************/
3645 #define EXTI_PR_PR0 0x00000001U
3646 #define EXTI_PR_PR1 0x00000002U
3647 #define EXTI_PR_PR2 0x00000004U
3648 #define EXTI_PR_PR3 0x00000008U
3649 #define EXTI_PR_PR4 0x00000010U
3650 #define EXTI_PR_PR5 0x00000020U
3651 #define EXTI_PR_PR6 0x00000040U
3652 #define EXTI_PR_PR7 0x00000080U
3653 #define EXTI_PR_PR8 0x00000100U
3654 #define EXTI_PR_PR9 0x00000200U
3655 #define EXTI_PR_PR10 0x00000400U
3656 #define EXTI_PR_PR11 0x00000800U
3657 #define EXTI_PR_PR12 0x00001000U
3658 #define EXTI_PR_PR13 0x00002000U
3659 #define EXTI_PR_PR14 0x00004000U
3660 #define EXTI_PR_PR15 0x00008000U
3661 #define EXTI_PR_PR16 0x00010000U
3662 #define EXTI_PR_PR17 0x00020000U
3663 #define EXTI_PR_PR18 0x00040000U
3664 #define EXTI_PR_PR19 0x00080000U
3665 #define EXTI_PR_PR20 0x00100000U
3666 #define EXTI_PR_PR21 0x00200000U
3667 #define EXTI_PR_PR22 0x00400000U
3669 /******************************************************************************/
3670 /* */
3671 /* FLASH */
3672 /* */
3673 /******************************************************************************/
3674 /******************* Bits definition for FLASH_ACR register *****************/
3675 #define FLASH_ACR_LATENCY 0x0000000FU
3676 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3677 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3678 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3679 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3680 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3681 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3682 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3683 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3684 #define FLASH_ACR_LATENCY_8WS 0x00000008U
3685 #define FLASH_ACR_LATENCY_9WS 0x00000009U
3686 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
3687 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
3688 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
3689 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
3690 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
3691 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
3692 #define FLASH_ACR_PRFTEN 0x00000100U
3693 #define FLASH_ACR_ICEN 0x00000200U
3694 #define FLASH_ACR_DCEN 0x00000400U
3695 #define FLASH_ACR_ICRST 0x00000800U
3696 #define FLASH_ACR_DCRST 0x00001000U
3697 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3698 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3699 
3700 /******************* Bits definition for FLASH_SR register ******************/
3701 #define FLASH_SR_EOP 0x00000001U
3702 #define FLASH_SR_SOP 0x00000002U
3703 #define FLASH_SR_WRPERR 0x00000010U
3704 #define FLASH_SR_PGAERR 0x00000020U
3705 #define FLASH_SR_PGPERR 0x00000040U
3706 #define FLASH_SR_PGSERR 0x00000080U
3707 #define FLASH_SR_BSY 0x00010000U
3708 
3709 /******************* Bits definition for FLASH_CR register ******************/
3710 #define FLASH_CR_PG 0x00000001U
3711 #define FLASH_CR_SER 0x00000002U
3712 #define FLASH_CR_MER 0x00000004U
3713 #define FLASH_CR_MER1 FLASH_CR_MER
3714 #define FLASH_CR_SNB 0x000000F8U
3715 #define FLASH_CR_SNB_0 0x00000008U
3716 #define FLASH_CR_SNB_1 0x00000010U
3717 #define FLASH_CR_SNB_2 0x00000020U
3718 #define FLASH_CR_SNB_3 0x00000040U
3719 #define FLASH_CR_SNB_4 0x00000080U
3720 #define FLASH_CR_PSIZE 0x00000300U
3721 #define FLASH_CR_PSIZE_0 0x00000100U
3722 #define FLASH_CR_PSIZE_1 0x00000200U
3723 #define FLASH_CR_MER2 0x00008000U
3724 #define FLASH_CR_STRT 0x00010000U
3725 #define FLASH_CR_EOPIE 0x01000000U
3726 #define FLASH_CR_LOCK 0x80000000U
3727 
3728 /******************* Bits definition for FLASH_OPTCR register ***************/
3729 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3730 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3731 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3732 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3733 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3734 #define FLASH_OPTCR_BFB2 0x00000010U
3735 #define FLASH_OPTCR_WDG_SW 0x00000020U
3736 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3737 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3738 #define FLASH_OPTCR_RDP 0x0000FF00U
3739 #define FLASH_OPTCR_RDP_0 0x00000100U
3740 #define FLASH_OPTCR_RDP_1 0x00000200U
3741 #define FLASH_OPTCR_RDP_2 0x00000400U
3742 #define FLASH_OPTCR_RDP_3 0x00000800U
3743 #define FLASH_OPTCR_RDP_4 0x00001000U
3744 #define FLASH_OPTCR_RDP_5 0x00002000U
3745 #define FLASH_OPTCR_RDP_6 0x00004000U
3746 #define FLASH_OPTCR_RDP_7 0x00008000U
3747 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3748 #define FLASH_OPTCR_nWRP_0 0x00010000U
3749 #define FLASH_OPTCR_nWRP_1 0x00020000U
3750 #define FLASH_OPTCR_nWRP_2 0x00040000U
3751 #define FLASH_OPTCR_nWRP_3 0x00080000U
3752 #define FLASH_OPTCR_nWRP_4 0x00100000U
3753 #define FLASH_OPTCR_nWRP_5 0x00200000U
3754 #define FLASH_OPTCR_nWRP_6 0x00400000U
3755 #define FLASH_OPTCR_nWRP_7 0x00800000U
3756 #define FLASH_OPTCR_nWRP_8 0x01000000U
3757 #define FLASH_OPTCR_nWRP_9 0x02000000U
3758 #define FLASH_OPTCR_nWRP_10 0x04000000U
3759 #define FLASH_OPTCR_nWRP_11 0x08000000U
3760 #define FLASH_OPTCR_DB1M 0x40000000U
3761 #define FLASH_OPTCR_SPRMOD 0x80000000U
3762 
3763 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3764 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3765 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3766 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3767 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3768 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3769 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3770 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3771 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3772 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3773 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3774 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3775 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3776 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3777 
3778 /******************************************************************************/
3779 /* */
3780 /* Flexible Memory Controller */
3781 /* */
3782 /******************************************************************************/
3783 /****************** Bit definition for FMC_BCR1 register *******************/
3784 #define FMC_BCR1_MBKEN 0x00000001U
3785 #define FMC_BCR1_MUXEN 0x00000002U
3787 #define FMC_BCR1_MTYP 0x0000000CU
3788 #define FMC_BCR1_MTYP_0 0x00000004U
3789 #define FMC_BCR1_MTYP_1 0x00000008U
3791 #define FMC_BCR1_MWID 0x00000030U
3792 #define FMC_BCR1_MWID_0 0x00000010U
3793 #define FMC_BCR1_MWID_1 0x00000020U
3795 #define FMC_BCR1_FACCEN 0x00000040U
3796 #define FMC_BCR1_BURSTEN 0x00000100U
3797 #define FMC_BCR1_WAITPOL 0x00000200U
3798 #define FMC_BCR1_WRAPMOD 0x00000400U
3799 #define FMC_BCR1_WAITCFG 0x00000800U
3800 #define FMC_BCR1_WREN 0x00001000U
3801 #define FMC_BCR1_WAITEN 0x00002000U
3802 #define FMC_BCR1_EXTMOD 0x00004000U
3803 #define FMC_BCR1_ASYNCWAIT 0x00008000U
3804 #define FMC_BCR1_CPSIZE 0x00070000U
3805 #define FMC_BCR1_CPSIZE_0 0x00010000U
3806 #define FMC_BCR1_CPSIZE_1 0x00020000U
3807 #define FMC_BCR1_CPSIZE_2 0x00040000U
3808 #define FMC_BCR1_CBURSTRW 0x00080000U
3809 #define FMC_BCR1_CCLKEN 0x00100000U
3811 /****************** Bit definition for FMC_BCR2 register *******************/
3812 #define FMC_BCR2_MBKEN 0x00000001U
3813 #define FMC_BCR2_MUXEN 0x00000002U
3815 #define FMC_BCR2_MTYP 0x0000000CU
3816 #define FMC_BCR2_MTYP_0 0x00000004U
3817 #define FMC_BCR2_MTYP_1 0x00000008U
3819 #define FMC_BCR2_MWID 0x00000030U
3820 #define FMC_BCR2_MWID_0 0x00000010U
3821 #define FMC_BCR2_MWID_1 0x00000020U
3823 #define FMC_BCR2_FACCEN 0x00000040U
3824 #define FMC_BCR2_BURSTEN 0x00000100U
3825 #define FMC_BCR2_WAITPOL 0x00000200U
3826 #define FMC_BCR2_WRAPMOD 0x00000400U
3827 #define FMC_BCR2_WAITCFG 0x00000800U
3828 #define FMC_BCR2_WREN 0x00001000U
3829 #define FMC_BCR2_WAITEN 0x00002000U
3830 #define FMC_BCR2_EXTMOD 0x00004000U
3831 #define FMC_BCR2_ASYNCWAIT 0x00008000U
3832 #define FMC_BCR2_CPSIZE 0x00070000U
3833 #define FMC_BCR2_CPSIZE_0 0x00010000U
3834 #define FMC_BCR2_CPSIZE_1 0x00020000U
3835 #define FMC_BCR2_CPSIZE_2 0x00040000U
3836 #define FMC_BCR2_CBURSTRW 0x00080000U
3838 /****************** Bit definition for FMC_BCR3 register *******************/
3839 #define FMC_BCR3_MBKEN 0x00000001U
3840 #define FMC_BCR3_MUXEN 0x00000002U
3842 #define FMC_BCR3_MTYP 0x0000000CU
3843 #define FMC_BCR3_MTYP_0 0x00000004U
3844 #define FMC_BCR3_MTYP_1 0x00000008U
3846 #define FMC_BCR3_MWID 0x00000030U
3847 #define FMC_BCR3_MWID_0 0x00000010U
3848 #define FMC_BCR3_MWID_1 0x00000020U
3850 #define FMC_BCR3_FACCEN 0x00000040U
3851 #define FMC_BCR3_BURSTEN 0x00000100U
3852 #define FMC_BCR3_WAITPOL 0x00000200U
3853 #define FMC_BCR3_WRAPMOD 0x00000400U
3854 #define FMC_BCR3_WAITCFG 0x00000800U
3855 #define FMC_BCR3_WREN 0x00001000U
3856 #define FMC_BCR3_WAITEN 0x00002000U
3857 #define FMC_BCR3_EXTMOD 0x00004000U
3858 #define FMC_BCR3_ASYNCWAIT 0x00008000U
3859 #define FMC_BCR3_CPSIZE 0x00070000U
3860 #define FMC_BCR3_CPSIZE_0 0x00010000U
3861 #define FMC_BCR3_CPSIZE_1 0x00020000U
3862 #define FMC_BCR3_CPSIZE_2 0x00040000U
3863 #define FMC_BCR3_CBURSTRW 0x00080000U
3865 /****************** Bit definition for FMC_BCR4 register *******************/
3866 #define FMC_BCR4_MBKEN 0x00000001U
3867 #define FMC_BCR4_MUXEN 0x00000002U
3869 #define FMC_BCR4_MTYP 0x0000000CU
3870 #define FMC_BCR4_MTYP_0 0x00000004U
3871 #define FMC_BCR4_MTYP_1 0x00000008U
3873 #define FMC_BCR4_MWID 0x00000030U
3874 #define FMC_BCR4_MWID_0 0x00000010U
3875 #define FMC_BCR4_MWID_1 0x00000020U
3877 #define FMC_BCR4_FACCEN 0x00000040U
3878 #define FMC_BCR4_BURSTEN 0x00000100U
3879 #define FMC_BCR4_WAITPOL 0x00000200U
3880 #define FMC_BCR4_WRAPMOD 0x00000400U
3881 #define FMC_BCR4_WAITCFG 0x00000800U
3882 #define FMC_BCR4_WREN 0x00001000U
3883 #define FMC_BCR4_WAITEN 0x00002000U
3884 #define FMC_BCR4_EXTMOD 0x00004000U
3885 #define FMC_BCR4_ASYNCWAIT 0x00008000U
3886 #define FMC_BCR4_CPSIZE 0x00070000U
3887 #define FMC_BCR4_CPSIZE_0 0x00010000U
3888 #define FMC_BCR4_CPSIZE_1 0x00020000U
3889 #define FMC_BCR4_CPSIZE_2 0x00040000U
3890 #define FMC_BCR4_CBURSTRW 0x00080000U
3892 /****************** Bit definition for FMC_BTR1 register ******************/
3893 #define FMC_BTR1_ADDSET 0x0000000FU
3894 #define FMC_BTR1_ADDSET_0 0x00000001U
3895 #define FMC_BTR1_ADDSET_1 0x00000002U
3896 #define FMC_BTR1_ADDSET_2 0x00000004U
3897 #define FMC_BTR1_ADDSET_3 0x00000008U
3899 #define FMC_BTR1_ADDHLD 0x000000F0U
3900 #define FMC_BTR1_ADDHLD_0 0x00000010U
3901 #define FMC_BTR1_ADDHLD_1 0x00000020U
3902 #define FMC_BTR1_ADDHLD_2 0x00000040U
3903 #define FMC_BTR1_ADDHLD_3 0x00000080U
3905 #define FMC_BTR1_DATAST 0x0000FF00U
3906 #define FMC_BTR1_DATAST_0 0x00000100U
3907 #define FMC_BTR1_DATAST_1 0x00000200U
3908 #define FMC_BTR1_DATAST_2 0x00000400U
3909 #define FMC_BTR1_DATAST_3 0x00000800U
3910 #define FMC_BTR1_DATAST_4 0x00001000U
3911 #define FMC_BTR1_DATAST_5 0x00002000U
3912 #define FMC_BTR1_DATAST_6 0x00004000U
3913 #define FMC_BTR1_DATAST_7 0x00008000U
3915 #define FMC_BTR1_BUSTURN 0x000F0000U
3916 #define FMC_BTR1_BUSTURN_0 0x00010000U
3917 #define FMC_BTR1_BUSTURN_1 0x00020000U
3918 #define FMC_BTR1_BUSTURN_2 0x00040000U
3919 #define FMC_BTR1_BUSTURN_3 0x00080000U
3921 #define FMC_BTR1_CLKDIV 0x00F00000U
3922 #define FMC_BTR1_CLKDIV_0 0x00100000U
3923 #define FMC_BTR1_CLKDIV_1 0x00200000U
3924 #define FMC_BTR1_CLKDIV_2 0x00400000U
3925 #define FMC_BTR1_CLKDIV_3 0x00800000U
3927 #define FMC_BTR1_DATLAT 0x0F000000U
3928 #define FMC_BTR1_DATLAT_0 0x01000000U
3929 #define FMC_BTR1_DATLAT_1 0x02000000U
3930 #define FMC_BTR1_DATLAT_2 0x04000000U
3931 #define FMC_BTR1_DATLAT_3 0x08000000U
3933 #define FMC_BTR1_ACCMOD 0x30000000U
3934 #define FMC_BTR1_ACCMOD_0 0x10000000U
3935 #define FMC_BTR1_ACCMOD_1 0x20000000U
3937 /****************** Bit definition for FMC_BTR2 register *******************/
3938 #define FMC_BTR2_ADDSET 0x0000000FU
3939 #define FMC_BTR2_ADDSET_0 0x00000001U
3940 #define FMC_BTR2_ADDSET_1 0x00000002U
3941 #define FMC_BTR2_ADDSET_2 0x00000004U
3942 #define FMC_BTR2_ADDSET_3 0x00000008U
3944 #define FMC_BTR2_ADDHLD 0x000000F0U
3945 #define FMC_BTR2_ADDHLD_0 0x00000010U
3946 #define FMC_BTR2_ADDHLD_1 0x00000020U
3947 #define FMC_BTR2_ADDHLD_2 0x00000040U
3948 #define FMC_BTR2_ADDHLD_3 0x00000080U
3950 #define FMC_BTR2_DATAST 0x0000FF00U
3951 #define FMC_BTR2_DATAST_0 0x00000100U
3952 #define FMC_BTR2_DATAST_1 0x00000200U
3953 #define FMC_BTR2_DATAST_2 0x00000400U
3954 #define FMC_BTR2_DATAST_3 0x00000800U
3955 #define FMC_BTR2_DATAST_4 0x00001000U
3956 #define FMC_BTR2_DATAST_5 0x00002000U
3957 #define FMC_BTR2_DATAST_6 0x00004000U
3958 #define FMC_BTR2_DATAST_7 0x00008000U
3960 #define FMC_BTR2_BUSTURN 0x000F0000U
3961 #define FMC_BTR2_BUSTURN_0 0x00010000U
3962 #define FMC_BTR2_BUSTURN_1 0x00020000U
3963 #define FMC_BTR2_BUSTURN_2 0x00040000U
3964 #define FMC_BTR2_BUSTURN_3 0x00080000U
3966 #define FMC_BTR2_CLKDIV 0x00F00000U
3967 #define FMC_BTR2_CLKDIV_0 0x00100000U
3968 #define FMC_BTR2_CLKDIV_1 0x00200000U
3969 #define FMC_BTR2_CLKDIV_2 0x00400000U
3970 #define FMC_BTR2_CLKDIV_3 0x00800000U
3972 #define FMC_BTR2_DATLAT 0x0F000000U
3973 #define FMC_BTR2_DATLAT_0 0x01000000U
3974 #define FMC_BTR2_DATLAT_1 0x02000000U
3975 #define FMC_BTR2_DATLAT_2 0x04000000U
3976 #define FMC_BTR2_DATLAT_3 0x08000000U
3978 #define FMC_BTR2_ACCMOD 0x30000000U
3979 #define FMC_BTR2_ACCMOD_0 0x10000000U
3980 #define FMC_BTR2_ACCMOD_1 0x20000000U
3982 /******************* Bit definition for FMC_BTR3 register *******************/
3983 #define FMC_BTR3_ADDSET 0x0000000FU
3984 #define FMC_BTR3_ADDSET_0 0x00000001U
3985 #define FMC_BTR3_ADDSET_1 0x00000002U
3986 #define FMC_BTR3_ADDSET_2 0x00000004U
3987 #define FMC_BTR3_ADDSET_3 0x00000008U
3989 #define FMC_BTR3_ADDHLD 0x000000F0U
3990 #define FMC_BTR3_ADDHLD_0 0x00000010U
3991 #define FMC_BTR3_ADDHLD_1 0x00000020U
3992 #define FMC_BTR3_ADDHLD_2 0x00000040U
3993 #define FMC_BTR3_ADDHLD_3 0x00000080U
3995 #define FMC_BTR3_DATAST 0x0000FF00U
3996 #define FMC_BTR3_DATAST_0 0x00000100U
3997 #define FMC_BTR3_DATAST_1 0x00000200U
3998 #define FMC_BTR3_DATAST_2 0x00000400U
3999 #define FMC_BTR3_DATAST_3 0x00000800U
4000 #define FMC_BTR3_DATAST_4 0x00001000U
4001 #define FMC_BTR3_DATAST_5 0x00002000U
4002 #define FMC_BTR3_DATAST_6 0x00004000U
4003 #define FMC_BTR3_DATAST_7 0x00008000U
4005 #define FMC_BTR3_BUSTURN 0x000F0000U
4006 #define FMC_BTR3_BUSTURN_0 0x00010000U
4007 #define FMC_BTR3_BUSTURN_1 0x00020000U
4008 #define FMC_BTR3_BUSTURN_2 0x00040000U
4009 #define FMC_BTR3_BUSTURN_3 0x00080000U
4011 #define FMC_BTR3_CLKDIV 0x00F00000U
4012 #define FMC_BTR3_CLKDIV_0 0x00100000U
4013 #define FMC_BTR3_CLKDIV_1 0x00200000U
4014 #define FMC_BTR3_CLKDIV_2 0x00400000U
4015 #define FMC_BTR3_CLKDIV_3 0x00800000U
4017 #define FMC_BTR3_DATLAT 0x0F000000U
4018 #define FMC_BTR3_DATLAT_0 0x01000000U
4019 #define FMC_BTR3_DATLAT_1 0x02000000U
4020 #define FMC_BTR3_DATLAT_2 0x04000000U
4021 #define FMC_BTR3_DATLAT_3 0x08000000U
4023 #define FMC_BTR3_ACCMOD 0x30000000U
4024 #define FMC_BTR3_ACCMOD_0 0x10000000U
4025 #define FMC_BTR3_ACCMOD_1 0x20000000U
4027 /****************** Bit definition for FMC_BTR4 register *******************/
4028 #define FMC_BTR4_ADDSET 0x0000000FU
4029 #define FMC_BTR4_ADDSET_0 0x00000001U
4030 #define FMC_BTR4_ADDSET_1 0x00000002U
4031 #define FMC_BTR4_ADDSET_2 0x00000004U
4032 #define FMC_BTR4_ADDSET_3 0x00000008U
4034 #define FMC_BTR4_ADDHLD 0x000000F0U
4035 #define FMC_BTR4_ADDHLD_0 0x00000010U
4036 #define FMC_BTR4_ADDHLD_1 0x00000020U
4037 #define FMC_BTR4_ADDHLD_2 0x00000040U
4038 #define FMC_BTR4_ADDHLD_3 0x00000080U
4040 #define FMC_BTR4_DATAST 0x0000FF00U
4041 #define FMC_BTR4_DATAST_0 0x00000100U
4042 #define FMC_BTR4_DATAST_1 0x00000200U
4043 #define FMC_BTR4_DATAST_2 0x00000400U
4044 #define FMC_BTR4_DATAST_3 0x00000800U
4045 #define FMC_BTR4_DATAST_4 0x00001000U
4046 #define FMC_BTR4_DATAST_5 0x00002000U
4047 #define FMC_BTR4_DATAST_6 0x00004000U
4048 #define FMC_BTR4_DATAST_7 0x00008000U
4050 #define FMC_BTR4_BUSTURN 0x000F0000U
4051 #define FMC_BTR4_BUSTURN_0 0x00010000U
4052 #define FMC_BTR4_BUSTURN_1 0x00020000U
4053 #define FMC_BTR4_BUSTURN_2 0x00040000U
4054 #define FMC_BTR4_BUSTURN_3 0x00080000U
4056 #define FMC_BTR4_CLKDIV 0x00F00000U
4057 #define FMC_BTR4_CLKDIV_0 0x00100000U
4058 #define FMC_BTR4_CLKDIV_1 0x00200000U
4059 #define FMC_BTR4_CLKDIV_2 0x00400000U
4060 #define FMC_BTR4_CLKDIV_3 0x00800000U
4062 #define FMC_BTR4_DATLAT 0x0F000000U
4063 #define FMC_BTR4_DATLAT_0 0x01000000U
4064 #define FMC_BTR4_DATLAT_1 0x02000000U
4065 #define FMC_BTR4_DATLAT_2 0x04000000U
4066 #define FMC_BTR4_DATLAT_3 0x08000000U
4068 #define FMC_BTR4_ACCMOD 0x30000000U
4069 #define FMC_BTR4_ACCMOD_0 0x10000000U
4070 #define FMC_BTR4_ACCMOD_1 0x20000000U
4072 /****************** Bit definition for FMC_BWTR1 register ******************/
4073 #define FMC_BWTR1_ADDSET 0x0000000FU
4074 #define FMC_BWTR1_ADDSET_0 0x00000001U
4075 #define FMC_BWTR1_ADDSET_1 0x00000002U
4076 #define FMC_BWTR1_ADDSET_2 0x00000004U
4077 #define FMC_BWTR1_ADDSET_3 0x00000008U
4079 #define FMC_BWTR1_ADDHLD 0x000000F0U
4080 #define FMC_BWTR1_ADDHLD_0 0x00000010U
4081 #define FMC_BWTR1_ADDHLD_1 0x00000020U
4082 #define FMC_BWTR1_ADDHLD_2 0x00000040U
4083 #define FMC_BWTR1_ADDHLD_3 0x00000080U
4085 #define FMC_BWTR1_DATAST 0x0000FF00U
4086 #define FMC_BWTR1_DATAST_0 0x00000100U
4087 #define FMC_BWTR1_DATAST_1 0x00000200U
4088 #define FMC_BWTR1_DATAST_2 0x00000400U
4089 #define FMC_BWTR1_DATAST_3 0x00000800U
4090 #define FMC_BWTR1_DATAST_4 0x00001000U
4091 #define FMC_BWTR1_DATAST_5 0x00002000U
4092 #define FMC_BWTR1_DATAST_6 0x00004000U
4093 #define FMC_BWTR1_DATAST_7 0x00008000U
4095 #define FMC_BWTR1_BUSTURN 0x000F0000U
4096 #define FMC_BWTR1_BUSTURN_0 0x00010000U
4097 #define FMC_BWTR1_BUSTURN_1 0x00020000U
4098 #define FMC_BWTR1_BUSTURN_2 0x00040000U
4099 #define FMC_BWTR1_BUSTURN_3 0x00080000U
4101 #define FMC_BWTR1_ACCMOD 0x30000000U
4102 #define FMC_BWTR1_ACCMOD_0 0x10000000U
4103 #define FMC_BWTR1_ACCMOD_1 0x20000000U
4105 /****************** Bit definition for FMC_BWTR2 register ******************/
4106 #define FMC_BWTR2_ADDSET 0x0000000FU
4107 #define FMC_BWTR2_ADDSET_0 0x00000001U
4108 #define FMC_BWTR2_ADDSET_1 0x00000002U
4109 #define FMC_BWTR2_ADDSET_2 0x00000004U
4110 #define FMC_BWTR2_ADDSET_3 0x00000008U
4112 #define FMC_BWTR2_ADDHLD 0x000000F0U
4113 #define FMC_BWTR2_ADDHLD_0 0x00000010U
4114 #define FMC_BWTR2_ADDHLD_1 0x00000020U
4115 #define FMC_BWTR2_ADDHLD_2 0x00000040U
4116 #define FMC_BWTR2_ADDHLD_3 0x00000080U
4118 #define FMC_BWTR2_DATAST 0x0000FF00U
4119 #define FMC_BWTR2_DATAST_0 0x00000100U
4120 #define FMC_BWTR2_DATAST_1 0x00000200U
4121 #define FMC_BWTR2_DATAST_2 0x00000400U
4122 #define FMC_BWTR2_DATAST_3 0x00000800U
4123 #define FMC_BWTR2_DATAST_4 0x00001000U
4124 #define FMC_BWTR2_DATAST_5 0x00002000U
4125 #define FMC_BWTR2_DATAST_6 0x00004000U
4126 #define FMC_BWTR2_DATAST_7 0x00008000U
4128 #define FMC_BWTR2_BUSTURN 0x000F0000U
4129 #define FMC_BWTR2_BUSTURN_0 0x00010000U
4130 #define FMC_BWTR2_BUSTURN_1 0x00020000U
4131 #define FMC_BWTR2_BUSTURN_2 0x00040000U
4132 #define FMC_BWTR2_BUSTURN_3 0x00080000U
4134 #define FMC_BWTR2_ACCMOD 0x30000000U
4135 #define FMC_BWTR2_ACCMOD_0 0x10000000U
4136 #define FMC_BWTR2_ACCMOD_1 0x20000000U
4138 /****************** Bit definition for FMC_BWTR3 register ******************/
4139 #define FMC_BWTR3_ADDSET 0x0000000FU
4140 #define FMC_BWTR3_ADDSET_0 0x00000001U
4141 #define FMC_BWTR3_ADDSET_1 0x00000002U
4142 #define FMC_BWTR3_ADDSET_2 0x00000004U
4143 #define FMC_BWTR3_ADDSET_3 0x00000008U
4145 #define FMC_BWTR3_ADDHLD 0x000000F0U
4146 #define FMC_BWTR3_ADDHLD_0 0x00000010U
4147 #define FMC_BWTR3_ADDHLD_1 0x00000020U
4148 #define FMC_BWTR3_ADDHLD_2 0x00000040U
4149 #define FMC_BWTR3_ADDHLD_3 0x00000080U
4151 #define FMC_BWTR3_DATAST 0x0000FF00U
4152 #define FMC_BWTR3_DATAST_0 0x00000100U
4153 #define FMC_BWTR3_DATAST_1 0x00000200U
4154 #define FMC_BWTR3_DATAST_2 0x00000400U
4155 #define FMC_BWTR3_DATAST_3 0x00000800U
4156 #define FMC_BWTR3_DATAST_4 0x00001000U
4157 #define FMC_BWTR3_DATAST_5 0x00002000U
4158 #define FMC_BWTR3_DATAST_6 0x00004000U
4159 #define FMC_BWTR3_DATAST_7 0x00008000U
4161 #define FMC_BWTR3_BUSTURN 0x000F0000U
4162 #define FMC_BWTR3_BUSTURN_0 0x00010000U
4163 #define FMC_BWTR3_BUSTURN_1 0x00020000U
4164 #define FMC_BWTR3_BUSTURN_2 0x00040000U
4165 #define FMC_BWTR3_BUSTURN_3 0x00080000U
4167 #define FMC_BWTR3_ACCMOD 0x30000000U
4168 #define FMC_BWTR3_ACCMOD_0 0x10000000U
4169 #define FMC_BWTR3_ACCMOD_1 0x20000000U
4171 /****************** Bit definition for FMC_BWTR4 register ******************/
4172 #define FMC_BWTR4_ADDSET 0x0000000FU
4173 #define FMC_BWTR4_ADDSET_0 0x00000001U
4174 #define FMC_BWTR4_ADDSET_1 0x00000002U
4175 #define FMC_BWTR4_ADDSET_2 0x00000004U
4176 #define FMC_BWTR4_ADDSET_3 0x00000008U
4178 #define FMC_BWTR4_ADDHLD 0x000000F0U
4179 #define FMC_BWTR4_ADDHLD_0 0x00000010U
4180 #define FMC_BWTR4_ADDHLD_1 0x00000020U
4181 #define FMC_BWTR4_ADDHLD_2 0x00000040U
4182 #define FMC_BWTR4_ADDHLD_3 0x00000080U
4184 #define FMC_BWTR4_DATAST 0x0000FF00U
4185 #define FMC_BWTR4_DATAST_0 0x00000100U
4186 #define FMC_BWTR4_DATAST_1 0x00000200U
4187 #define FMC_BWTR4_DATAST_2 0x00000400U
4188 #define FMC_BWTR4_DATAST_3 0x00000800U
4189 #define FMC_BWTR4_DATAST_4 0x00001000U
4190 #define FMC_BWTR4_DATAST_5 0x00002000U
4191 #define FMC_BWTR4_DATAST_6 0x00004000U
4192 #define FMC_BWTR4_DATAST_7 0x00008000U
4194 #define FMC_BWTR4_BUSTURN 0x000F0000U
4195 #define FMC_BWTR4_BUSTURN_0 0x00010000U
4196 #define FMC_BWTR4_BUSTURN_1 0x00020000U
4197 #define FMC_BWTR4_BUSTURN_2 0x00040000U
4198 #define FMC_BWTR4_BUSTURN_3 0x00080000U
4200 #define FMC_BWTR4_ACCMOD 0x30000000U
4201 #define FMC_BWTR4_ACCMOD_0 0x10000000U
4202 #define FMC_BWTR4_ACCMOD_1 0x20000000U
4204 /****************** Bit definition for FMC_PCR2 register *******************/
4205 #define FMC_PCR2_PWAITEN 0x00000002U
4206 #define FMC_PCR2_PBKEN 0x00000004U
4207 #define FMC_PCR2_PTYP 0x00000008U
4209 #define FMC_PCR2_PWID 0x00000030U
4210 #define FMC_PCR2_PWID_0 0x00000010U
4211 #define FMC_PCR2_PWID_1 0x00000020U
4213 #define FMC_PCR2_ECCEN 0x00000040U
4215 #define FMC_PCR2_TCLR 0x00001E00U
4216 #define FMC_PCR2_TCLR_0 0x00000200U
4217 #define FMC_PCR2_TCLR_1 0x00000400U
4218 #define FMC_PCR2_TCLR_2 0x00000800U
4219 #define FMC_PCR2_TCLR_3 0x00001000U
4221 #define FMC_PCR2_TAR 0x0001E000U
4222 #define FMC_PCR2_TAR_0 0x00002000U
4223 #define FMC_PCR2_TAR_1 0x00004000U
4224 #define FMC_PCR2_TAR_2 0x00008000U
4225 #define FMC_PCR2_TAR_3 0x00010000U
4227 #define FMC_PCR2_ECCPS 0x000E0000U
4228 #define FMC_PCR2_ECCPS_0 0x00020000U
4229 #define FMC_PCR2_ECCPS_1 0x00040000U
4230 #define FMC_PCR2_ECCPS_2 0x00080000U
4232 /****************** Bit definition for FMC_PCR3 register *******************/
4233 #define FMC_PCR3_PWAITEN 0x00000002U
4234 #define FMC_PCR3_PBKEN 0x00000004U
4235 #define FMC_PCR3_PTYP 0x00000008U
4237 #define FMC_PCR3_PWID 0x00000030U
4238 #define FMC_PCR3_PWID_0 0x00000010U
4239 #define FMC_PCR3_PWID_1 0x00000020U
4241 #define FMC_PCR3_ECCEN 0x00000040U
4243 #define FMC_PCR3_TCLR 0x00001E00U
4244 #define FMC_PCR3_TCLR_0 0x00000200U
4245 #define FMC_PCR3_TCLR_1 0x00000400U
4246 #define FMC_PCR3_TCLR_2 0x00000800U
4247 #define FMC_PCR3_TCLR_3 0x00001000U
4249 #define FMC_PCR3_TAR 0x0001E000U
4250 #define FMC_PCR3_TAR_0 0x00002000U
4251 #define FMC_PCR3_TAR_1 0x00004000U
4252 #define FMC_PCR3_TAR_2 0x00008000U
4253 #define FMC_PCR3_TAR_3 0x00010000U
4255 #define FMC_PCR3_ECCPS 0x000E0000U
4256 #define FMC_PCR3_ECCPS_0 0x00020000U
4257 #define FMC_PCR3_ECCPS_1 0x00040000U
4258 #define FMC_PCR3_ECCPS_2 0x00080000U
4260 /****************** Bit definition for FMC_PCR4 register *******************/
4261 #define FMC_PCR4_PWAITEN 0x00000002U
4262 #define FMC_PCR4_PBKEN 0x00000004U
4263 #define FMC_PCR4_PTYP 0x00000008U
4265 #define FMC_PCR4_PWID 0x00000030U
4266 #define FMC_PCR4_PWID_0 0x00000010U
4267 #define FMC_PCR4_PWID_1 0x00000020U
4269 #define FMC_PCR4_ECCEN 0x00000040U
4271 #define FMC_PCR4_TCLR 0x00001E00U
4272 #define FMC_PCR4_TCLR_0 0x00000200U
4273 #define FMC_PCR4_TCLR_1 0x00000400U
4274 #define FMC_PCR4_TCLR_2 0x00000800U
4275 #define FMC_PCR4_TCLR_3 0x00001000U
4277 #define FMC_PCR4_TAR 0x0001E000U
4278 #define FMC_PCR4_TAR_0 0x00002000U
4279 #define FMC_PCR4_TAR_1 0x00004000U
4280 #define FMC_PCR4_TAR_2 0x00008000U
4281 #define FMC_PCR4_TAR_3 0x00010000U
4283 #define FMC_PCR4_ECCPS 0x000E0000U
4284 #define FMC_PCR4_ECCPS_0 0x00020000U
4285 #define FMC_PCR4_ECCPS_1 0x00040000U
4286 #define FMC_PCR4_ECCPS_2 0x00080000U
4288 /******************* Bit definition for FMC_SR2 register *******************/
4289 #define FMC_SR2_IRS 0x01U
4290 #define FMC_SR2_ILS 0x02U
4291 #define FMC_SR2_IFS 0x04U
4292 #define FMC_SR2_IREN 0x08U
4293 #define FMC_SR2_ILEN 0x10U
4294 #define FMC_SR2_IFEN 0x20U
4295 #define FMC_SR2_FEMPT 0x40U
4297 /******************* Bit definition for FMC_SR3 register *******************/
4298 #define FMC_SR3_IRS 0x01U
4299 #define FMC_SR3_ILS 0x02U
4300 #define FMC_SR3_IFS 0x04U
4301 #define FMC_SR3_IREN 0x08U
4302 #define FMC_SR3_ILEN 0x10U
4303 #define FMC_SR3_IFEN 0x20U
4304 #define FMC_SR3_FEMPT 0x40U
4306 /******************* Bit definition for FMC_SR4 register *******************/
4307 #define FMC_SR4_IRS 0x01U
4308 #define FMC_SR4_ILS 0x02U
4309 #define FMC_SR4_IFS 0x04U
4310 #define FMC_SR4_IREN 0x08U
4311 #define FMC_SR4_ILEN 0x10U
4312 #define FMC_SR4_IFEN 0x20U
4313 #define FMC_SR4_FEMPT 0x40U
4315 /****************** Bit definition for FMC_PMEM2 register ******************/
4316 #define FMC_PMEM2_MEMSET2 0x000000FFU
4317 #define FMC_PMEM2_MEMSET2_0 0x00000001U
4318 #define FMC_PMEM2_MEMSET2_1 0x00000002U
4319 #define FMC_PMEM2_MEMSET2_2 0x00000004U
4320 #define FMC_PMEM2_MEMSET2_3 0x00000008U
4321 #define FMC_PMEM2_MEMSET2_4 0x00000010U
4322 #define FMC_PMEM2_MEMSET2_5 0x00000020U
4323 #define FMC_PMEM2_MEMSET2_6 0x00000040U
4324 #define FMC_PMEM2_MEMSET2_7 0x00000080U
4326 #define FMC_PMEM2_MEMWAIT2 0x0000FF00U
4327 #define FMC_PMEM2_MEMWAIT2_0 0x00000100U
4328 #define FMC_PMEM2_MEMWAIT2_1 0x00000200U
4329 #define FMC_PMEM2_MEMWAIT2_2 0x00000400U
4330 #define FMC_PMEM2_MEMWAIT2_3 0x00000800U
4331 #define FMC_PMEM2_MEMWAIT2_4 0x00001000U
4332 #define FMC_PMEM2_MEMWAIT2_5 0x00002000U
4333 #define FMC_PMEM2_MEMWAIT2_6 0x00004000U
4334 #define FMC_PMEM2_MEMWAIT2_7 0x00008000U
4336 #define FMC_PMEM2_MEMHOLD2 0x00FF0000U
4337 #define FMC_PMEM2_MEMHOLD2_0 0x00010000U
4338 #define FMC_PMEM2_MEMHOLD2_1 0x00020000U
4339 #define FMC_PMEM2_MEMHOLD2_2 0x00040000U
4340 #define FMC_PMEM2_MEMHOLD2_3 0x00080000U
4341 #define FMC_PMEM2_MEMHOLD2_4 0x00100000U
4342 #define FMC_PMEM2_MEMHOLD2_5 0x00200000U
4343 #define FMC_PMEM2_MEMHOLD2_6 0x00400000U
4344 #define FMC_PMEM2_MEMHOLD2_7 0x00800000U
4346 #define FMC_PMEM2_MEMHIZ2 0xFF000000U
4347 #define FMC_PMEM2_MEMHIZ2_0 0x01000000U
4348 #define FMC_PMEM2_MEMHIZ2_1 0x02000000U
4349 #define FMC_PMEM2_MEMHIZ2_2 0x04000000U
4350 #define FMC_PMEM2_MEMHIZ2_3 0x08000000U
4351 #define FMC_PMEM2_MEMHIZ2_4 0x10000000U
4352 #define FMC_PMEM2_MEMHIZ2_5 0x20000000U
4353 #define FMC_PMEM2_MEMHIZ2_6 0x40000000U
4354 #define FMC_PMEM2_MEMHIZ2_7 0x80000000U
4356 /****************** Bit definition for FMC_PMEM3 register ******************/
4357 #define FMC_PMEM3_MEMSET3 0x000000FFU
4358 #define FMC_PMEM3_MEMSET3_0 0x00000001U
4359 #define FMC_PMEM3_MEMSET3_1 0x00000002U
4360 #define FMC_PMEM3_MEMSET3_2 0x00000004U
4361 #define FMC_PMEM3_MEMSET3_3 0x00000008U
4362 #define FMC_PMEM3_MEMSET3_4 0x00000010U
4363 #define FMC_PMEM3_MEMSET3_5 0x00000020U
4364 #define FMC_PMEM3_MEMSET3_6 0x00000040U
4365 #define FMC_PMEM3_MEMSET3_7 0x00000080U
4367 #define FMC_PMEM3_MEMWAIT3 0x0000FF00U
4368 #define FMC_PMEM3_MEMWAIT3_0 0x00000100U
4369 #define FMC_PMEM3_MEMWAIT3_1 0x00000200U
4370 #define FMC_PMEM3_MEMWAIT3_2 0x00000400U
4371 #define FMC_PMEM3_MEMWAIT3_3 0x00000800U
4372 #define FMC_PMEM3_MEMWAIT3_4 0x00001000U
4373 #define FMC_PMEM3_MEMWAIT3_5 0x00002000U
4374 #define FMC_PMEM3_MEMWAIT3_6 0x00004000U
4375 #define FMC_PMEM3_MEMWAIT3_7 0x00008000U
4377 #define FMC_PMEM3_MEMHOLD3 0x00FF0000U
4378 #define FMC_PMEM3_MEMHOLD3_0 0x00010000U
4379 #define FMC_PMEM3_MEMHOLD3_1 0x00020000U
4380 #define FMC_PMEM3_MEMHOLD3_2 0x00040000U
4381 #define FMC_PMEM3_MEMHOLD3_3 0x00080000U
4382 #define FMC_PMEM3_MEMHOLD3_4 0x00100000U
4383 #define FMC_PMEM3_MEMHOLD3_5 0x00200000U
4384 #define FMC_PMEM3_MEMHOLD3_6 0x00400000U
4385 #define FMC_PMEM3_MEMHOLD3_7 0x00800000U
4387 #define FMC_PMEM3_MEMHIZ3 0xFF000000U
4388 #define FMC_PMEM3_MEMHIZ3_0 0x01000000U
4389 #define FMC_PMEM3_MEMHIZ3_1 0x02000000U
4390 #define FMC_PMEM3_MEMHIZ3_2 0x04000000U
4391 #define FMC_PMEM3_MEMHIZ3_3 0x08000000U
4392 #define FMC_PMEM3_MEMHIZ3_4 0x10000000U
4393 #define FMC_PMEM3_MEMHIZ3_5 0x20000000U
4394 #define FMC_PMEM3_MEMHIZ3_6 0x40000000U
4395 #define FMC_PMEM3_MEMHIZ3_7 0x80000000U
4397 /****************** Bit definition for FMC_PMEM4 register ******************/
4398 #define FMC_PMEM4_MEMSET4 0x000000FFU
4399 #define FMC_PMEM4_MEMSET4_0 0x00000001U
4400 #define FMC_PMEM4_MEMSET4_1 0x00000002U
4401 #define FMC_PMEM4_MEMSET4_2 0x00000004U
4402 #define FMC_PMEM4_MEMSET4_3 0x00000008U
4403 #define FMC_PMEM4_MEMSET4_4 0x00000010U
4404 #define FMC_PMEM4_MEMSET4_5 0x00000020U
4405 #define FMC_PMEM4_MEMSET4_6 0x00000040U
4406 #define FMC_PMEM4_MEMSET4_7 0x00000080U
4408 #define FMC_PMEM4_MEMWAIT4 0x0000FF00U
4409 #define FMC_PMEM4_MEMWAIT4_0 0x00000100U
4410 #define FMC_PMEM4_MEMWAIT4_1 0x00000200U
4411 #define FMC_PMEM4_MEMWAIT4_2 0x00000400U
4412 #define FMC_PMEM4_MEMWAIT4_3 0x00000800U
4413 #define FMC_PMEM4_MEMWAIT4_4 0x00001000U
4414 #define FMC_PMEM4_MEMWAIT4_5 0x00002000U
4415 #define FMC_PMEM4_MEMWAIT4_6 0x00004000U
4416 #define FMC_PMEM4_MEMWAIT4_7 0x00008000U
4418 #define FMC_PMEM4_MEMHOLD4 0x00FF0000U
4419 #define FMC_PMEM4_MEMHOLD4_0 0x00010000U
4420 #define FMC_PMEM4_MEMHOLD4_1 0x00020000U
4421 #define FMC_PMEM4_MEMHOLD4_2 0x00040000U
4422 #define FMC_PMEM4_MEMHOLD4_3 0x00080000U
4423 #define FMC_PMEM4_MEMHOLD4_4 0x00100000U
4424 #define FMC_PMEM4_MEMHOLD4_5 0x00200000U
4425 #define FMC_PMEM4_MEMHOLD4_6 0x00400000U
4426 #define FMC_PMEM4_MEMHOLD4_7 0x00800000U
4428 #define FMC_PMEM4_MEMHIZ4 0xFF000000U
4429 #define FMC_PMEM4_MEMHIZ4_0 0x01000000U
4430 #define FMC_PMEM4_MEMHIZ4_1 0x02000000U
4431 #define FMC_PMEM4_MEMHIZ4_2 0x04000000U
4432 #define FMC_PMEM4_MEMHIZ4_3 0x08000000U
4433 #define FMC_PMEM4_MEMHIZ4_4 0x10000000U
4434 #define FMC_PMEM4_MEMHIZ4_5 0x20000000U
4435 #define FMC_PMEM4_MEMHIZ4_6 0x40000000U
4436 #define FMC_PMEM4_MEMHIZ4_7 0x80000000U
4438 /****************** Bit definition for FMC_PATT2 register ******************/
4439 #define FMC_PATT2_ATTSET2 0x000000FFU
4440 #define FMC_PATT2_ATTSET2_0 0x00000001U
4441 #define FMC_PATT2_ATTSET2_1 0x00000002U
4442 #define FMC_PATT2_ATTSET2_2 0x00000004U
4443 #define FMC_PATT2_ATTSET2_3 0x00000008U
4444 #define FMC_PATT2_ATTSET2_4 0x00000010U
4445 #define FMC_PATT2_ATTSET2_5 0x00000020U
4446 #define FMC_PATT2_ATTSET2_6 0x00000040U
4447 #define FMC_PATT2_ATTSET2_7 0x00000080U
4449 #define FMC_PATT2_ATTWAIT2 0x0000FF00U
4450 #define FMC_PATT2_ATTWAIT2_0 0x00000100U
4451 #define FMC_PATT2_ATTWAIT2_1 0x00000200U
4452 #define FMC_PATT2_ATTWAIT2_2 0x00000400U
4453 #define FMC_PATT2_ATTWAIT2_3 0x00000800U
4454 #define FMC_PATT2_ATTWAIT2_4 0x00001000U
4455 #define FMC_PATT2_ATTWAIT2_5 0x00002000U
4456 #define FMC_PATT2_ATTWAIT2_6 0x00004000U
4457 #define FMC_PATT2_ATTWAIT2_7 0x00008000U
4459 #define FMC_PATT2_ATTHOLD2 0x00FF0000U
4460 #define FMC_PATT2_ATTHOLD2_0 0x00010000U
4461 #define FMC_PATT2_ATTHOLD2_1 0x00020000U
4462 #define FMC_PATT2_ATTHOLD2_2 0x00040000U
4463 #define FMC_PATT2_ATTHOLD2_3 0x00080000U
4464 #define FMC_PATT2_ATTHOLD2_4 0x00100000U
4465 #define FMC_PATT2_ATTHOLD2_5 0x00200000U
4466 #define FMC_PATT2_ATTHOLD2_6 0x00400000U
4467 #define FMC_PATT2_ATTHOLD2_7 0x00800000U
4469 #define FMC_PATT2_ATTHIZ2 0xFF000000U
4470 #define FMC_PATT2_ATTHIZ2_0 0x01000000U
4471 #define FMC_PATT2_ATTHIZ2_1 0x02000000U
4472 #define FMC_PATT2_ATTHIZ2_2 0x04000000U
4473 #define FMC_PATT2_ATTHIZ2_3 0x08000000U
4474 #define FMC_PATT2_ATTHIZ2_4 0x10000000U
4475 #define FMC_PATT2_ATTHIZ2_5 0x20000000U
4476 #define FMC_PATT2_ATTHIZ2_6 0x40000000U
4477 #define FMC_PATT2_ATTHIZ2_7 0x80000000U
4479 /****************** Bit definition for FMC_PATT3 register ******************/
4480 #define FMC_PATT3_ATTSET3 0x000000FFU
4481 #define FMC_PATT3_ATTSET3_0 0x00000001U
4482 #define FMC_PATT3_ATTSET3_1 0x00000002U
4483 #define FMC_PATT3_ATTSET3_2 0x00000004U
4484 #define FMC_PATT3_ATTSET3_3 0x00000008U
4485 #define FMC_PATT3_ATTSET3_4 0x00000010U
4486 #define FMC_PATT3_ATTSET3_5 0x00000020U
4487 #define FMC_PATT3_ATTSET3_6 0x00000040U
4488 #define FMC_PATT3_ATTSET3_7 0x00000080U
4490 #define FMC_PATT3_ATTWAIT3 0x0000FF00U
4491 #define FMC_PATT3_ATTWAIT3_0 0x00000100U
4492 #define FMC_PATT3_ATTWAIT3_1 0x00000200U
4493 #define FMC_PATT3_ATTWAIT3_2 0x00000400U
4494 #define FMC_PATT3_ATTWAIT3_3 0x00000800U
4495 #define FMC_PATT3_ATTWAIT3_4 0x00001000U
4496 #define FMC_PATT3_ATTWAIT3_5 0x00002000U
4497 #define FMC_PATT3_ATTWAIT3_6 0x00004000U
4498 #define FMC_PATT3_ATTWAIT3_7 0x00008000U
4500 #define FMC_PATT3_ATTHOLD3 0x00FF0000U
4501 #define FMC_PATT3_ATTHOLD3_0 0x00010000U
4502 #define FMC_PATT3_ATTHOLD3_1 0x00020000U
4503 #define FMC_PATT3_ATTHOLD3_2 0x00040000U
4504 #define FMC_PATT3_ATTHOLD3_3 0x00080000U
4505 #define FMC_PATT3_ATTHOLD3_4 0x00100000U
4506 #define FMC_PATT3_ATTHOLD3_5 0x00200000U
4507 #define FMC_PATT3_ATTHOLD3_6 0x00400000U
4508 #define FMC_PATT3_ATTHOLD3_7 0x00800000U
4510 #define FMC_PATT3_ATTHIZ3 0xFF000000U
4511 #define FMC_PATT3_ATTHIZ3_0 0x01000000U
4512 #define FMC_PATT3_ATTHIZ3_1 0x02000000U
4513 #define FMC_PATT3_ATTHIZ3_2 0x04000000U
4514 #define FMC_PATT3_ATTHIZ3_3 0x08000000U
4515 #define FMC_PATT3_ATTHIZ3_4 0x10000000U
4516 #define FMC_PATT3_ATTHIZ3_5 0x20000000U
4517 #define FMC_PATT3_ATTHIZ3_6 0x40000000U
4518 #define FMC_PATT3_ATTHIZ3_7 0x80000000U
4520 /****************** Bit definition for FMC_PATT4 register ******************/
4521 #define FMC_PATT4_ATTSET4 0x000000FFU
4522 #define FMC_PATT4_ATTSET4_0 0x00000001U
4523 #define FMC_PATT4_ATTSET4_1 0x00000002U
4524 #define FMC_PATT4_ATTSET4_2 0x00000004U
4525 #define FMC_PATT4_ATTSET4_3 0x00000008U
4526 #define FMC_PATT4_ATTSET4_4 0x00000010U
4527 #define FMC_PATT4_ATTSET4_5 0x00000020U
4528 #define FMC_PATT4_ATTSET4_6 0x00000040U
4529 #define FMC_PATT4_ATTSET4_7 0x00000080U
4531 #define FMC_PATT4_ATTWAIT4 0x0000FF00U
4532 #define FMC_PATT4_ATTWAIT4_0 0x00000100U
4533 #define FMC_PATT4_ATTWAIT4_1 0x00000200U
4534 #define FMC_PATT4_ATTWAIT4_2 0x00000400U
4535 #define FMC_PATT4_ATTWAIT4_3 0x00000800U
4536 #define FMC_PATT4_ATTWAIT4_4 0x00001000U
4537 #define FMC_PATT4_ATTWAIT4_5 0x00002000U
4538 #define FMC_PATT4_ATTWAIT4_6 0x00004000U
4539 #define FMC_PATT4_ATTWAIT4_7 0x00008000U
4541 #define FMC_PATT4_ATTHOLD4 0x00FF0000U
4542 #define FMC_PATT4_ATTHOLD4_0 0x00010000U
4543 #define FMC_PATT4_ATTHOLD4_1 0x00020000U
4544 #define FMC_PATT4_ATTHOLD4_2 0x00040000U
4545 #define FMC_PATT4_ATTHOLD4_3 0x00080000U
4546 #define FMC_PATT4_ATTHOLD4_4 0x00100000U
4547 #define FMC_PATT4_ATTHOLD4_5 0x00200000U
4548 #define FMC_PATT4_ATTHOLD4_6 0x00400000U
4549 #define FMC_PATT4_ATTHOLD4_7 0x00800000U
4551 #define FMC_PATT4_ATTHIZ4 0xFF000000U
4552 #define FMC_PATT4_ATTHIZ4_0 0x01000000U
4553 #define FMC_PATT4_ATTHIZ4_1 0x02000000U
4554 #define FMC_PATT4_ATTHIZ4_2 0x04000000U
4555 #define FMC_PATT4_ATTHIZ4_3 0x08000000U
4556 #define FMC_PATT4_ATTHIZ4_4 0x10000000U
4557 #define FMC_PATT4_ATTHIZ4_5 0x20000000U
4558 #define FMC_PATT4_ATTHIZ4_6 0x40000000U
4559 #define FMC_PATT4_ATTHIZ4_7 0x80000000U
4561 /****************** Bit definition for FMC_PIO4 register *******************/
4562 #define FMC_PIO4_IOSET4 0x000000FFU
4563 #define FMC_PIO4_IOSET4_0 0x00000001U
4564 #define FMC_PIO4_IOSET4_1 0x00000002U
4565 #define FMC_PIO4_IOSET4_2 0x00000004U
4566 #define FMC_PIO4_IOSET4_3 0x00000008U
4567 #define FMC_PIO4_IOSET4_4 0x00000010U
4568 #define FMC_PIO4_IOSET4_5 0x00000020U
4569 #define FMC_PIO4_IOSET4_6 0x00000040U
4570 #define FMC_PIO4_IOSET4_7 0x00000080U
4572 #define FMC_PIO4_IOWAIT4 0x0000FF00U
4573 #define FMC_PIO4_IOWAIT4_0 0x00000100U
4574 #define FMC_PIO4_IOWAIT4_1 0x00000200U
4575 #define FMC_PIO4_IOWAIT4_2 0x00000400U
4576 #define FMC_PIO4_IOWAIT4_3 0x00000800U
4577 #define FMC_PIO4_IOWAIT4_4 0x00001000U
4578 #define FMC_PIO4_IOWAIT4_5 0x00002000U
4579 #define FMC_PIO4_IOWAIT4_6 0x00004000U
4580 #define FMC_PIO4_IOWAIT4_7 0x00008000U
4582 #define FMC_PIO4_IOHOLD4 0x00FF0000U
4583 #define FMC_PIO4_IOHOLD4_0 0x00010000U
4584 #define FMC_PIO4_IOHOLD4_1 0x00020000U
4585 #define FMC_PIO4_IOHOLD4_2 0x00040000U
4586 #define FMC_PIO4_IOHOLD4_3 0x00080000U
4587 #define FMC_PIO4_IOHOLD4_4 0x00100000U
4588 #define FMC_PIO4_IOHOLD4_5 0x00200000U
4589 #define FMC_PIO4_IOHOLD4_6 0x00400000U
4590 #define FMC_PIO4_IOHOLD4_7 0x00800000U
4592 #define FMC_PIO4_IOHIZ4 0xFF000000U
4593 #define FMC_PIO4_IOHIZ4_0 0x01000000U
4594 #define FMC_PIO4_IOHIZ4_1 0x02000000U
4595 #define FMC_PIO4_IOHIZ4_2 0x04000000U
4596 #define FMC_PIO4_IOHIZ4_3 0x08000000U
4597 #define FMC_PIO4_IOHIZ4_4 0x10000000U
4598 #define FMC_PIO4_IOHIZ4_5 0x20000000U
4599 #define FMC_PIO4_IOHIZ4_6 0x40000000U
4600 #define FMC_PIO4_IOHIZ4_7 0x80000000U
4602 /****************** Bit definition for FMC_ECCR2 register ******************/
4603 #define FMC_ECCR2_ECC2 0xFFFFFFFFU
4605 /****************** Bit definition for FMC_ECCR3 register ******************/
4606 #define FMC_ECCR3_ECC3 0xFFFFFFFFU
4608 /****************** Bit definition for FMC_SDCR1 register ******************/
4609 #define FMC_SDCR1_NC 0x00000003U
4610 #define FMC_SDCR1_NC_0 0x00000001U
4611 #define FMC_SDCR1_NC_1 0x00000002U
4613 #define FMC_SDCR1_NR 0x0000000CU
4614 #define FMC_SDCR1_NR_0 0x00000004U
4615 #define FMC_SDCR1_NR_1 0x00000008U
4617 #define FMC_SDCR1_MWID 0x00000030U
4618 #define FMC_SDCR1_MWID_0 0x00000010U
4619 #define FMC_SDCR1_MWID_1 0x00000020U
4621 #define FMC_SDCR1_NB 0x00000040U
4623 #define FMC_SDCR1_CAS 0x00000180U
4624 #define FMC_SDCR1_CAS_0 0x00000080U
4625 #define FMC_SDCR1_CAS_1 0x00000100U
4627 #define FMC_SDCR1_WP 0x00000200U
4629 #define FMC_SDCR1_SDCLK 0x00000C00U
4630 #define FMC_SDCR1_SDCLK_0 0x00000400U
4631 #define FMC_SDCR1_SDCLK_1 0x00000800U
4633 #define FMC_SDCR1_RBURST 0x00001000U
4635 #define FMC_SDCR1_RPIPE 0x00006000U
4636 #define FMC_SDCR1_RPIPE_0 0x00002000U
4637 #define FMC_SDCR1_RPIPE_1 0x00004000U
4639 /****************** Bit definition for FMC_SDCR2 register ******************/
4640 #define FMC_SDCR2_NC 0x00000003U
4641 #define FMC_SDCR2_NC_0 0x00000001U
4642 #define FMC_SDCR2_NC_1 0x00000002U
4644 #define FMC_SDCR2_NR 0x0000000CU
4645 #define FMC_SDCR2_NR_0 0x00000004U
4646 #define FMC_SDCR2_NR_1 0x00000008U
4648 #define FMC_SDCR2_MWID 0x00000030U
4649 #define FMC_SDCR2_MWID_0 0x00000010U
4650 #define FMC_SDCR2_MWID_1 0x00000020U
4652 #define FMC_SDCR2_NB 0x00000040U
4654 #define FMC_SDCR2_CAS 0x00000180U
4655 #define FMC_SDCR2_CAS_0 0x00000080U
4656 #define FMC_SDCR2_CAS_1 0x00000100U
4658 #define FMC_SDCR2_WP 0x00000200U
4660 #define FMC_SDCR2_SDCLK 0x00000C00U
4661 #define FMC_SDCR2_SDCLK_0 0x00000400U
4662 #define FMC_SDCR2_SDCLK_1 0x00000800U
4664 #define FMC_SDCR2_RBURST 0x00001000U
4666 #define FMC_SDCR2_RPIPE 0x00006000U
4667 #define FMC_SDCR2_RPIPE_0 0x00002000U
4668 #define FMC_SDCR2_RPIPE_1 0x00004000U
4670 /****************** Bit definition for FMC_SDTR1 register ******************/
4671 #define FMC_SDTR1_TMRD 0x0000000FU
4672 #define FMC_SDTR1_TMRD_0 0x00000001U
4673 #define FMC_SDTR1_TMRD_1 0x00000002U
4674 #define FMC_SDTR1_TMRD_2 0x00000004U
4675 #define FMC_SDTR1_TMRD_3 0x00000008U
4677 #define FMC_SDTR1_TXSR 0x000000F0U
4678 #define FMC_SDTR1_TXSR_0 0x00000010U
4679 #define FMC_SDTR1_TXSR_1 0x00000020U
4680 #define FMC_SDTR1_TXSR_2 0x00000040U
4681 #define FMC_SDTR1_TXSR_3 0x00000080U
4683 #define FMC_SDTR1_TRAS 0x00000F00U
4684 #define FMC_SDTR1_TRAS_0 0x00000100U
4685 #define FMC_SDTR1_TRAS_1 0x00000200U
4686 #define FMC_SDTR1_TRAS_2 0x00000400U
4687 #define FMC_SDTR1_TRAS_3 0x00000800U
4689 #define FMC_SDTR1_TRC 0x0000F000U
4690 #define FMC_SDTR1_TRC_0 0x00001000U
4691 #define FMC_SDTR1_TRC_1 0x00002000U
4692 #define FMC_SDTR1_TRC_2 0x00004000U
4694 #define FMC_SDTR1_TWR 0x000F0000U
4695 #define FMC_SDTR1_TWR_0 0x00010000U
4696 #define FMC_SDTR1_TWR_1 0x00020000U
4697 #define FMC_SDTR1_TWR_2 0x00040000U
4699 #define FMC_SDTR1_TRP 0x00F00000U
4700 #define FMC_SDTR1_TRP_0 0x00100000U
4701 #define FMC_SDTR1_TRP_1 0x00200000U
4702 #define FMC_SDTR1_TRP_2 0x00400000U
4704 #define FMC_SDTR1_TRCD 0x0F000000U
4705 #define FMC_SDTR1_TRCD_0 0x01000000U
4706 #define FMC_SDTR1_TRCD_1 0x02000000U
4707 #define FMC_SDTR1_TRCD_2 0x04000000U
4709 /****************** Bit definition for FMC_SDTR2 register ******************/
4710 #define FMC_SDTR2_TMRD 0x0000000FU
4711 #define FMC_SDTR2_TMRD_0 0x00000001U
4712 #define FMC_SDTR2_TMRD_1 0x00000002U
4713 #define FMC_SDTR2_TMRD_2 0x00000004U
4714 #define FMC_SDTR2_TMRD_3 0x00000008U
4716 #define FMC_SDTR2_TXSR 0x000000F0U
4717 #define FMC_SDTR2_TXSR_0 0x00000010U
4718 #define FMC_SDTR2_TXSR_1 0x00000020U
4719 #define FMC_SDTR2_TXSR_2 0x00000040U
4720 #define FMC_SDTR2_TXSR_3 0x00000080U
4722 #define FMC_SDTR2_TRAS 0x00000F00U
4723 #define FMC_SDTR2_TRAS_0 0x00000100U
4724 #define FMC_SDTR2_TRAS_1 0x00000200U
4725 #define FMC_SDTR2_TRAS_2 0x00000400U
4726 #define FMC_SDTR2_TRAS_3 0x00000800U
4728 #define FMC_SDTR2_TRC 0x0000F000U
4729 #define FMC_SDTR2_TRC_0 0x00001000U
4730 #define FMC_SDTR2_TRC_1 0x00002000U
4731 #define FMC_SDTR2_TRC_2 0x00004000U
4733 #define FMC_SDTR2_TWR 0x000F0000U
4734 #define FMC_SDTR2_TWR_0 0x00010000U
4735 #define FMC_SDTR2_TWR_1 0x00020000U
4736 #define FMC_SDTR2_TWR_2 0x00040000U
4738 #define FMC_SDTR2_TRP 0x00F00000U
4739 #define FMC_SDTR2_TRP_0 0x00100000U
4740 #define FMC_SDTR2_TRP_1 0x00200000U
4741 #define FMC_SDTR2_TRP_2 0x00400000U
4743 #define FMC_SDTR2_TRCD 0x0F000000U
4744 #define FMC_SDTR2_TRCD_0 0x01000000U
4745 #define FMC_SDTR2_TRCD_1 0x02000000U
4746 #define FMC_SDTR2_TRCD_2 0x04000000U
4748 /****************** Bit definition for FMC_SDCMR register ******************/
4749 #define FMC_SDCMR_MODE 0x00000007U
4750 #define FMC_SDCMR_MODE_0 0x00000001U
4751 #define FMC_SDCMR_MODE_1 0x00000002U
4752 #define FMC_SDCMR_MODE_2 0x00000004U
4754 #define FMC_SDCMR_CTB2 0x00000008U
4756 #define FMC_SDCMR_CTB1 0x00000010U
4758 #define FMC_SDCMR_NRFS 0x000001E0U
4759 #define FMC_SDCMR_NRFS_0 0x00000020U
4760 #define FMC_SDCMR_NRFS_1 0x00000040U
4761 #define FMC_SDCMR_NRFS_2 0x00000080U
4762 #define FMC_SDCMR_NRFS_3 0x00000100U
4764 #define FMC_SDCMR_MRD 0x003FFE00U
4766 /****************** Bit definition for FMC_SDRTR register ******************/
4767 #define FMC_SDRTR_CRE 0x00000001U
4769 #define FMC_SDRTR_COUNT 0x00003FFEU
4771 #define FMC_SDRTR_REIE 0x00004000U
4773 /****************** Bit definition for FMC_SDSR register ******************/
4774 #define FMC_SDSR_RE 0x00000001U
4776 #define FMC_SDSR_MODES1 0x00000006U
4777 #define FMC_SDSR_MODES1_0 0x00000002U
4778 #define FMC_SDSR_MODES1_1 0x00000004U
4780 #define FMC_SDSR_MODES2 0x00000018U
4781 #define FMC_SDSR_MODES2_0 0x00000008U
4782 #define FMC_SDSR_MODES2_1 0x00000010U
4783 #define FMC_SDSR_BUSY 0x00000020U
4787 /******************************************************************************/
4788 /* */
4789 /* General Purpose I/O */
4790 /* */
4791 /******************************************************************************/
4792 /****************** Bits definition for GPIO_MODER register *****************/
4793 #define GPIO_MODER_MODER0 0x00000003U
4794 #define GPIO_MODER_MODER0_0 0x00000001U
4795 #define GPIO_MODER_MODER0_1 0x00000002U
4796 
4797 #define GPIO_MODER_MODER1 0x0000000CU
4798 #define GPIO_MODER_MODER1_0 0x00000004U
4799 #define GPIO_MODER_MODER1_1 0x00000008U
4800 
4801 #define GPIO_MODER_MODER2 0x00000030U
4802 #define GPIO_MODER_MODER2_0 0x00000010U
4803 #define GPIO_MODER_MODER2_1 0x00000020U
4804 
4805 #define GPIO_MODER_MODER3 0x000000C0U
4806 #define GPIO_MODER_MODER3_0 0x00000040U
4807 #define GPIO_MODER_MODER3_1 0x00000080U
4808 
4809 #define GPIO_MODER_MODER4 0x00000300U
4810 #define GPIO_MODER_MODER4_0 0x00000100U
4811 #define GPIO_MODER_MODER4_1 0x00000200U
4812 
4813 #define GPIO_MODER_MODER5 0x00000C00U
4814 #define GPIO_MODER_MODER5_0 0x00000400U
4815 #define GPIO_MODER_MODER5_1 0x00000800U
4816 
4817 #define GPIO_MODER_MODER6 0x00003000U
4818 #define GPIO_MODER_MODER6_0 0x00001000U
4819 #define GPIO_MODER_MODER6_1 0x00002000U
4820 
4821 #define GPIO_MODER_MODER7 0x0000C000U
4822 #define GPIO_MODER_MODER7_0 0x00004000U
4823 #define GPIO_MODER_MODER7_1 0x00008000U
4824 
4825 #define GPIO_MODER_MODER8 0x00030000U
4826 #define GPIO_MODER_MODER8_0 0x00010000U
4827 #define GPIO_MODER_MODER8_1 0x00020000U
4828 
4829 #define GPIO_MODER_MODER9 0x000C0000U
4830 #define GPIO_MODER_MODER9_0 0x00040000U
4831 #define GPIO_MODER_MODER9_1 0x00080000U
4832 
4833 #define GPIO_MODER_MODER10 0x00300000U
4834 #define GPIO_MODER_MODER10_0 0x00100000U
4835 #define GPIO_MODER_MODER10_1 0x00200000U
4836 
4837 #define GPIO_MODER_MODER11 0x00C00000U
4838 #define GPIO_MODER_MODER11_0 0x00400000U
4839 #define GPIO_MODER_MODER11_1 0x00800000U
4840 
4841 #define GPIO_MODER_MODER12 0x03000000U
4842 #define GPIO_MODER_MODER12_0 0x01000000U
4843 #define GPIO_MODER_MODER12_1 0x02000000U
4844 
4845 #define GPIO_MODER_MODER13 0x0C000000U
4846 #define GPIO_MODER_MODER13_0 0x04000000U
4847 #define GPIO_MODER_MODER13_1 0x08000000U
4848 
4849 #define GPIO_MODER_MODER14 0x30000000U
4850 #define GPIO_MODER_MODER14_0 0x10000000U
4851 #define GPIO_MODER_MODER14_1 0x20000000U
4852 
4853 #define GPIO_MODER_MODER15 0xC0000000U
4854 #define GPIO_MODER_MODER15_0 0x40000000U
4855 #define GPIO_MODER_MODER15_1 0x80000000U
4856 
4857 /****************** Bits definition for GPIO_OTYPER register ****************/
4858 #define GPIO_OTYPER_OT_0 0x00000001U
4859 #define GPIO_OTYPER_OT_1 0x00000002U
4860 #define GPIO_OTYPER_OT_2 0x00000004U
4861 #define GPIO_OTYPER_OT_3 0x00000008U
4862 #define GPIO_OTYPER_OT_4 0x00000010U
4863 #define GPIO_OTYPER_OT_5 0x00000020U
4864 #define GPIO_OTYPER_OT_6 0x00000040U
4865 #define GPIO_OTYPER_OT_7 0x00000080U
4866 #define GPIO_OTYPER_OT_8 0x00000100U
4867 #define GPIO_OTYPER_OT_9 0x00000200U
4868 #define GPIO_OTYPER_OT_10 0x00000400U
4869 #define GPIO_OTYPER_OT_11 0x00000800U
4870 #define GPIO_OTYPER_OT_12 0x00001000U
4871 #define GPIO_OTYPER_OT_13 0x00002000U
4872 #define GPIO_OTYPER_OT_14 0x00004000U
4873 #define GPIO_OTYPER_OT_15 0x00008000U
4874 
4875 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4876 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4877 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4878 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4879 
4880 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4881 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4882 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4883 
4884 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4885 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4886 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4887 
4888 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4889 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4890 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4891 
4892 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4893 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4894 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4895 
4896 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4897 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4898 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4899 
4900 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4901 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4902 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4903 
4904 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4905 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4906 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4907 
4908 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4909 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4910 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4911 
4912 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4913 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4914 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4915 
4916 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4917 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4918 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4919 
4920 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4921 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4922 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4923 
4924 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4925 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4926 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4927 
4928 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4929 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4930 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4931 
4932 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4933 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4934 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4935 
4936 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4937 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4938 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4939 
4940 /****************** Bits definition for GPIO_PUPDR register *****************/
4941 #define GPIO_PUPDR_PUPDR0 0x00000003U
4942 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4943 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4944 
4945 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4946 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4947 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4948 
4949 #define GPIO_PUPDR_PUPDR2 0x00000030U
4950 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4951 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4952 
4953 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4954 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4955 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4956 
4957 #define GPIO_PUPDR_PUPDR4 0x00000300U
4958 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4959 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4960 
4961 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4962 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4963 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4964 
4965 #define GPIO_PUPDR_PUPDR6 0x00003000U
4966 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4967 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4968 
4969 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4970 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4971 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4972 
4973 #define GPIO_PUPDR_PUPDR8 0x00030000U
4974 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4975 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4976 
4977 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4978 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4979 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4980 
4981 #define GPIO_PUPDR_PUPDR10 0x00300000U
4982 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4983 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4984 
4985 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4986 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4987 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4988 
4989 #define GPIO_PUPDR_PUPDR12 0x03000000U
4990 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4991 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4992 
4993 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4994 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4995 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4996 
4997 #define GPIO_PUPDR_PUPDR14 0x30000000U
4998 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4999 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
5000 
5001 #define GPIO_PUPDR_PUPDR15 0xC0000000U
5002 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
5003 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
5004 
5005 /****************** Bits definition for GPIO_IDR register *******************/
5006 #define GPIO_IDR_IDR_0 0x00000001U
5007 #define GPIO_IDR_IDR_1 0x00000002U
5008 #define GPIO_IDR_IDR_2 0x00000004U
5009 #define GPIO_IDR_IDR_3 0x00000008U
5010 #define GPIO_IDR_IDR_4 0x00000010U
5011 #define GPIO_IDR_IDR_5 0x00000020U
5012 #define GPIO_IDR_IDR_6 0x00000040U
5013 #define GPIO_IDR_IDR_7 0x00000080U
5014 #define GPIO_IDR_IDR_8 0x00000100U
5015 #define GPIO_IDR_IDR_9 0x00000200U
5016 #define GPIO_IDR_IDR_10 0x00000400U
5017 #define GPIO_IDR_IDR_11 0x00000800U
5018 #define GPIO_IDR_IDR_12 0x00001000U
5019 #define GPIO_IDR_IDR_13 0x00002000U
5020 #define GPIO_IDR_IDR_14 0x00004000U
5021 #define GPIO_IDR_IDR_15 0x00008000U
5022 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5023 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
5024 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
5025 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
5026 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
5027 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
5028 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
5029 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
5030 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
5031 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
5032 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
5033 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
5034 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
5035 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
5036 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
5037 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
5038 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
5039 
5040 /****************** Bits definition for GPIO_ODR register *******************/
5041 #define GPIO_ODR_ODR_0 0x00000001U
5042 #define GPIO_ODR_ODR_1 0x00000002U
5043 #define GPIO_ODR_ODR_2 0x00000004U
5044 #define GPIO_ODR_ODR_3 0x00000008U
5045 #define GPIO_ODR_ODR_4 0x00000010U
5046 #define GPIO_ODR_ODR_5 0x00000020U
5047 #define GPIO_ODR_ODR_6 0x00000040U
5048 #define GPIO_ODR_ODR_7 0x00000080U
5049 #define GPIO_ODR_ODR_8 0x00000100U
5050 #define GPIO_ODR_ODR_9 0x00000200U
5051 #define GPIO_ODR_ODR_10 0x00000400U
5052 #define GPIO_ODR_ODR_11 0x00000800U
5053 #define GPIO_ODR_ODR_12 0x00001000U
5054 #define GPIO_ODR_ODR_13 0x00002000U
5055 #define GPIO_ODR_ODR_14 0x00004000U
5056 #define GPIO_ODR_ODR_15 0x00008000U
5057 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
5058 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
5059 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
5060 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
5061 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
5062 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
5063 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
5064 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
5065 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
5066 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
5067 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
5068 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
5069 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
5070 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
5071 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
5072 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
5073 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
5074 
5075 /****************** Bits definition for GPIO_BSRR register ******************/
5076 #define GPIO_BSRR_BS_0 0x00000001U
5077 #define GPIO_BSRR_BS_1 0x00000002U
5078 #define GPIO_BSRR_BS_2 0x00000004U
5079 #define GPIO_BSRR_BS_3 0x00000008U
5080 #define GPIO_BSRR_BS_4 0x00000010U
5081 #define GPIO_BSRR_BS_5 0x00000020U
5082 #define GPIO_BSRR_BS_6 0x00000040U
5083 #define GPIO_BSRR_BS_7 0x00000080U
5084 #define GPIO_BSRR_BS_8 0x00000100U
5085 #define GPIO_BSRR_BS_9 0x00000200U
5086 #define GPIO_BSRR_BS_10 0x00000400U
5087 #define GPIO_BSRR_BS_11 0x00000800U
5088 #define GPIO_BSRR_BS_12 0x00001000U
5089 #define GPIO_BSRR_BS_13 0x00002000U
5090 #define GPIO_BSRR_BS_14 0x00004000U
5091 #define GPIO_BSRR_BS_15 0x00008000U
5092 #define GPIO_BSRR_BR_0 0x00010000U
5093 #define GPIO_BSRR_BR_1 0x00020000U
5094 #define GPIO_BSRR_BR_2 0x00040000U
5095 #define GPIO_BSRR_BR_3 0x00080000U
5096 #define GPIO_BSRR_BR_4 0x00100000U
5097 #define GPIO_BSRR_BR_5 0x00200000U
5098 #define GPIO_BSRR_BR_6 0x00400000U
5099 #define GPIO_BSRR_BR_7 0x00800000U
5100 #define GPIO_BSRR_BR_8 0x01000000U
5101 #define GPIO_BSRR_BR_9 0x02000000U
5102 #define GPIO_BSRR_BR_10 0x04000000U
5103 #define GPIO_BSRR_BR_11 0x08000000U
5104 #define GPIO_BSRR_BR_12 0x10000000U
5105 #define GPIO_BSRR_BR_13 0x20000000U
5106 #define GPIO_BSRR_BR_14 0x40000000U
5107 #define GPIO_BSRR_BR_15 0x80000000U
5108 
5109 /****************** Bit definition for GPIO_LCKR register *********************/
5110 #define GPIO_LCKR_LCK0 0x00000001U
5111 #define GPIO_LCKR_LCK1 0x00000002U
5112 #define GPIO_LCKR_LCK2 0x00000004U
5113 #define GPIO_LCKR_LCK3 0x00000008U
5114 #define GPIO_LCKR_LCK4 0x00000010U
5115 #define GPIO_LCKR_LCK5 0x00000020U
5116 #define GPIO_LCKR_LCK6 0x00000040U
5117 #define GPIO_LCKR_LCK7 0x00000080U
5118 #define GPIO_LCKR_LCK8 0x00000100U
5119 #define GPIO_LCKR_LCK9 0x00000200U
5120 #define GPIO_LCKR_LCK10 0x00000400U
5121 #define GPIO_LCKR_LCK11 0x00000800U
5122 #define GPIO_LCKR_LCK12 0x00001000U
5123 #define GPIO_LCKR_LCK13 0x00002000U
5124 #define GPIO_LCKR_LCK14 0x00004000U
5125 #define GPIO_LCKR_LCK15 0x00008000U
5126 #define GPIO_LCKR_LCKK 0x00010000U
5127 
5128 /******************************************************************************/
5129 /* */
5130 /* Inter-integrated Circuit Interface */
5131 /* */
5132 /******************************************************************************/
5133 /******************* Bit definition for I2C_CR1 register ********************/
5134 #define I2C_CR1_PE 0x00000001U
5135 #define I2C_CR1_SMBUS 0x00000002U
5136 #define I2C_CR1_SMBTYPE 0x00000008U
5137 #define I2C_CR1_ENARP 0x00000010U
5138 #define I2C_CR1_ENPEC 0x00000020U
5139 #define I2C_CR1_ENGC 0x00000040U
5140 #define I2C_CR1_NOSTRETCH 0x00000080U
5141 #define I2C_CR1_START 0x00000100U
5142 #define I2C_CR1_STOP 0x00000200U
5143 #define I2C_CR1_ACK 0x00000400U
5144 #define I2C_CR1_POS 0x00000800U
5145 #define I2C_CR1_PEC 0x00001000U
5146 #define I2C_CR1_ALERT 0x00002000U
5147 #define I2C_CR1_SWRST 0x00008000U
5149 /******************* Bit definition for I2C_CR2 register ********************/
5150 #define I2C_CR2_FREQ 0x0000003FU
5151 #define I2C_CR2_FREQ_0 0x00000001U
5152 #define I2C_CR2_FREQ_1 0x00000002U
5153 #define I2C_CR2_FREQ_2 0x00000004U
5154 #define I2C_CR2_FREQ_3 0x00000008U
5155 #define I2C_CR2_FREQ_4 0x00000010U
5156 #define I2C_CR2_FREQ_5 0x00000020U
5158 #define I2C_CR2_ITERREN 0x00000100U
5159 #define I2C_CR2_ITEVTEN 0x00000200U
5160 #define I2C_CR2_ITBUFEN 0x00000400U
5161 #define I2C_CR2_DMAEN 0x00000800U
5162 #define I2C_CR2_LAST 0x00001000U
5164 /******************* Bit definition for I2C_OAR1 register *******************/
5165 #define I2C_OAR1_ADD1_7 0x000000FEU
5166 #define I2C_OAR1_ADD8_9 0x00000300U
5168 #define I2C_OAR1_ADD0 0x00000001U
5169 #define I2C_OAR1_ADD1 0x00000002U
5170 #define I2C_OAR1_ADD2 0x00000004U
5171 #define I2C_OAR1_ADD3 0x00000008U
5172 #define I2C_OAR1_ADD4 0x00000010U
5173 #define I2C_OAR1_ADD5 0x00000020U
5174 #define I2C_OAR1_ADD6 0x00000040U
5175 #define I2C_OAR1_ADD7 0x00000080U
5176 #define I2C_OAR1_ADD8 0x00000100U
5177 #define I2C_OAR1_ADD9 0x00000200U
5179 #define I2C_OAR1_ADDMODE 0x00008000U
5181 /******************* Bit definition for I2C_OAR2 register *******************/
5182 #define I2C_OAR2_ENDUAL 0x00000001U
5183 #define I2C_OAR2_ADD2 0x000000FEU
5185 /******************** Bit definition for I2C_DR register ********************/
5186 #define I2C_DR_DR 0x000000FFU
5188 /******************* Bit definition for I2C_SR1 register ********************/
5189 #define I2C_SR1_SB 0x00000001U
5190 #define I2C_SR1_ADDR 0x00000002U
5191 #define I2C_SR1_BTF 0x00000004U
5192 #define I2C_SR1_ADD10 0x00000008U
5193 #define I2C_SR1_STOPF 0x00000010U
5194 #define I2C_SR1_RXNE 0x00000040U
5195 #define I2C_SR1_TXE 0x00000080U
5196 #define I2C_SR1_BERR 0x00000100U
5197 #define I2C_SR1_ARLO 0x00000200U
5198 #define I2C_SR1_AF 0x00000400U
5199 #define I2C_SR1_OVR 0x00000800U
5200 #define I2C_SR1_PECERR 0x00001000U
5201 #define I2C_SR1_TIMEOUT 0x00004000U
5202 #define I2C_SR1_SMBALERT 0x00008000U
5204 /******************* Bit definition for I2C_SR2 register ********************/
5205 #define I2C_SR2_MSL 0x00000001U
5206 #define I2C_SR2_BUSY 0x00000002U
5207 #define I2C_SR2_TRA 0x00000004U
5208 #define I2C_SR2_GENCALL 0x00000010U
5209 #define I2C_SR2_SMBDEFAULT 0x00000020U
5210 #define I2C_SR2_SMBHOST 0x00000040U
5211 #define I2C_SR2_DUALF 0x00000080U
5212 #define I2C_SR2_PEC 0x0000FF00U
5214 /******************* Bit definition for I2C_CCR register ********************/
5215 #define I2C_CCR_CCR 0x00000FFFU
5216 #define I2C_CCR_DUTY 0x00004000U
5217 #define I2C_CCR_FS 0x00008000U
5219 /****************** Bit definition for I2C_TRISE register *******************/
5220 #define I2C_TRISE_TRISE 0x0000003FU
5222 /****************** Bit definition for I2C_FLTR register *******************/
5223 #define I2C_FLTR_DNF 0x0000000FU
5224 #define I2C_FLTR_ANOFF 0x00000010U
5226 /******************************************************************************/
5227 /* */
5228 /* Independent WATCHDOG */
5229 /* */
5230 /******************************************************************************/
5231 /******************* Bit definition for IWDG_KR register ********************/
5232 #define IWDG_KR_KEY 0xFFFFU
5234 /******************* Bit definition for IWDG_PR register ********************/
5235 #define IWDG_PR_PR 0x07U
5236 #define IWDG_PR_PR_0 0x01U
5237 #define IWDG_PR_PR_1 0x02U
5238 #define IWDG_PR_PR_2 0x04U
5240 /******************* Bit definition for IWDG_RLR register *******************/
5241 #define IWDG_RLR_RL 0x0FFFU
5243 /******************* Bit definition for IWDG_SR register ********************/
5244 #define IWDG_SR_PVU 0x01U
5245 #define IWDG_SR_RVU 0x02U
5248 /******************************************************************************/
5249 /* */
5250 /* Power Control */
5251 /* */
5252 /******************************************************************************/
5253 /******************** Bit definition for PWR_CR register ********************/
5254 #define PWR_CR_LPDS 0x00000001U
5255 #define PWR_CR_PDDS 0x00000002U
5256 #define PWR_CR_CWUF 0x00000004U
5257 #define PWR_CR_CSBF 0x00000008U
5258 #define PWR_CR_PVDE 0x00000010U
5260 #define PWR_CR_PLS 0x000000E0U
5261 #define PWR_CR_PLS_0 0x00000020U
5262 #define PWR_CR_PLS_1 0x00000040U
5263 #define PWR_CR_PLS_2 0x00000080U
5266 #define PWR_CR_PLS_LEV0 0x00000000U
5267 #define PWR_CR_PLS_LEV1 0x00000020U
5268 #define PWR_CR_PLS_LEV2 0x00000040U
5269 #define PWR_CR_PLS_LEV3 0x00000060U
5270 #define PWR_CR_PLS_LEV4 0x00000080U
5271 #define PWR_CR_PLS_LEV5 0x000000A0U
5272 #define PWR_CR_PLS_LEV6 0x000000C0U
5273 #define PWR_CR_PLS_LEV7 0x000000E0U
5274 #define PWR_CR_DBP 0x00000100U
5275 #define PWR_CR_FPDS 0x00000200U
5276 #define PWR_CR_LPLVDS 0x00000400U
5277 #define PWR_CR_MRLVDS 0x00000800U
5278 #define PWR_CR_ADCDC1 0x00002000U
5279 #define PWR_CR_VOS 0x0000C000U
5280 #define PWR_CR_VOS_0 0x00004000U
5281 #define PWR_CR_VOS_1 0x00008000U
5282 #define PWR_CR_ODEN 0x00010000U
5283 #define PWR_CR_ODSWEN 0x00020000U
5284 #define PWR_CR_UDEN 0x000C0000U
5285 #define PWR_CR_UDEN_0 0x00040000U
5286 #define PWR_CR_UDEN_1 0x00080000U
5288 /* Legacy define */
5289 #define PWR_CR_PMODE PWR_CR_VOS
5290 #define PWR_CR_LPUDS PWR_CR_LPLVDS
5291 #define PWR_CR_MRUDS PWR_CR_MRLVDS
5293 /******************* Bit definition for PWR_CSR register ********************/
5294 #define PWR_CSR_WUF 0x00000001U
5295 #define PWR_CSR_SBF 0x00000002U
5296 #define PWR_CSR_PVDO 0x00000004U
5297 #define PWR_CSR_BRR 0x00000008U
5298 #define PWR_CSR_EWUP 0x00000100U
5299 #define PWR_CSR_BRE 0x00000200U
5300 #define PWR_CSR_VOSRDY 0x00004000U
5301 #define PWR_CSR_ODRDY 0x00010000U
5302 #define PWR_CSR_ODSWRDY 0x00020000U
5303 #define PWR_CSR_UDSWRDY 0x000C0000U
5305 /* Legacy define */
5306 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
5307 
5308 /******************************************************************************/
5309 /* */
5310 /* Reset and Clock Control */
5311 /* */
5312 /******************************************************************************/
5313 /******************** Bit definition for RCC_CR register ********************/
5314 #define RCC_CR_HSION 0x00000001U
5315 #define RCC_CR_HSIRDY 0x00000002U
5316 
5317 #define RCC_CR_HSITRIM 0x000000F8U
5318 #define RCC_CR_HSITRIM_0 0x00000008U
5319 #define RCC_CR_HSITRIM_1 0x00000010U
5320 #define RCC_CR_HSITRIM_2 0x00000020U
5321 #define RCC_CR_HSITRIM_3 0x00000040U
5322 #define RCC_CR_HSITRIM_4 0x00000080U
5324 #define RCC_CR_HSICAL 0x0000FF00U
5325 #define RCC_CR_HSICAL_0 0x00000100U
5326 #define RCC_CR_HSICAL_1 0x00000200U
5327 #define RCC_CR_HSICAL_2 0x00000400U
5328 #define RCC_CR_HSICAL_3 0x00000800U
5329 #define RCC_CR_HSICAL_4 0x00001000U
5330 #define RCC_CR_HSICAL_5 0x00002000U
5331 #define RCC_CR_HSICAL_6 0x00004000U
5332 #define RCC_CR_HSICAL_7 0x00008000U
5334 #define RCC_CR_HSEON 0x00010000U
5335 #define RCC_CR_HSERDY 0x00020000U
5336 #define RCC_CR_HSEBYP 0x00040000U
5337 #define RCC_CR_CSSON 0x00080000U
5338 #define RCC_CR_PLLON 0x01000000U
5339 #define RCC_CR_PLLRDY 0x02000000U
5340 #define RCC_CR_PLLI2SON 0x04000000U
5341 #define RCC_CR_PLLI2SRDY 0x08000000U
5342 #define RCC_CR_PLLSAION 0x10000000U
5343 #define RCC_CR_PLLSAIRDY 0x20000000U
5344 
5345 /******************** Bit definition for RCC_PLLCFGR register ***************/
5346 #define RCC_PLLCFGR_PLLM 0x0000003FU
5347 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5348 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5349 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5350 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5351 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5352 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5353 
5354 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5355 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5356 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5357 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5358 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5359 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5360 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5361 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5362 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5363 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5364 
5365 #define RCC_PLLCFGR_PLLP 0x00030000U
5366 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5367 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5368 
5369 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5370 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5371 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5372 
5373 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5374 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5375 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5376 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5377 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5378 
5379 /******************** Bit definition for RCC_CFGR register ******************/
5381 #define RCC_CFGR_SW 0x00000003U
5382 #define RCC_CFGR_SW_0 0x00000001U
5383 #define RCC_CFGR_SW_1 0x00000002U
5385 #define RCC_CFGR_SW_HSI 0x00000000U
5386 #define RCC_CFGR_SW_HSE 0x00000001U
5387 #define RCC_CFGR_SW_PLL 0x00000002U
5390 #define RCC_CFGR_SWS 0x0000000CU
5391 #define RCC_CFGR_SWS_0 0x00000004U
5392 #define RCC_CFGR_SWS_1 0x00000008U
5394 #define RCC_CFGR_SWS_HSI 0x00000000U
5395 #define RCC_CFGR_SWS_HSE 0x00000004U
5396 #define RCC_CFGR_SWS_PLL 0x00000008U
5399 #define RCC_CFGR_HPRE 0x000000F0U
5400 #define RCC_CFGR_HPRE_0 0x00000010U
5401 #define RCC_CFGR_HPRE_1 0x00000020U
5402 #define RCC_CFGR_HPRE_2 0x00000040U
5403 #define RCC_CFGR_HPRE_3 0x00000080U
5405 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5406 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5407 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5408 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5409 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5410 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5411 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5412 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5413 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5416 #define RCC_CFGR_PPRE1 0x00001C00U
5417 #define RCC_CFGR_PPRE1_0 0x00000400U
5418 #define RCC_CFGR_PPRE1_1 0x00000800U
5419 #define RCC_CFGR_PPRE1_2 0x00001000U
5421 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5422 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5423 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5424 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5425 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5428 #define RCC_CFGR_PPRE2 0x0000E000U
5429 #define RCC_CFGR_PPRE2_0 0x00002000U
5430 #define RCC_CFGR_PPRE2_1 0x00004000U
5431 #define RCC_CFGR_PPRE2_2 0x00008000U
5433 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5434 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5435 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5436 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5437 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5440 #define RCC_CFGR_RTCPRE 0x001F0000U
5441 #define RCC_CFGR_RTCPRE_0 0x00010000U
5442 #define RCC_CFGR_RTCPRE_1 0x00020000U
5443 #define RCC_CFGR_RTCPRE_2 0x00040000U
5444 #define RCC_CFGR_RTCPRE_3 0x00080000U
5445 #define RCC_CFGR_RTCPRE_4 0x00100000U
5446 
5448 #define RCC_CFGR_MCO1 0x00600000U
5449 #define RCC_CFGR_MCO1_0 0x00200000U
5450 #define RCC_CFGR_MCO1_1 0x00400000U
5451 
5452 #define RCC_CFGR_I2SSRC 0x00800000U
5453 
5454 #define RCC_CFGR_MCO1PRE 0x07000000U
5455 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5456 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5457 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5458 
5459 #define RCC_CFGR_MCO2PRE 0x38000000U
5460 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5461 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5462 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5463 
5464 #define RCC_CFGR_MCO2 0xC0000000U
5465 #define RCC_CFGR_MCO2_0 0x40000000U
5466 #define RCC_CFGR_MCO2_1 0x80000000U
5467 
5468 /******************** Bit definition for RCC_CIR register *******************/
5469 #define RCC_CIR_LSIRDYF 0x00000001U
5470 #define RCC_CIR_LSERDYF 0x00000002U
5471 #define RCC_CIR_HSIRDYF 0x00000004U
5472 #define RCC_CIR_HSERDYF 0x00000008U
5473 #define RCC_CIR_PLLRDYF 0x00000010U
5474 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5475 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5476 #define RCC_CIR_CSSF 0x00000080U
5477 #define RCC_CIR_LSIRDYIE 0x00000100U
5478 #define RCC_CIR_LSERDYIE 0x00000200U
5479 #define RCC_CIR_HSIRDYIE 0x00000400U
5480 #define RCC_CIR_HSERDYIE 0x00000800U
5481 #define RCC_CIR_PLLRDYIE 0x00001000U
5482 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5483 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5484 #define RCC_CIR_LSIRDYC 0x00010000U
5485 #define RCC_CIR_LSERDYC 0x00020000U
5486 #define RCC_CIR_HSIRDYC 0x00040000U
5487 #define RCC_CIR_HSERDYC 0x00080000U
5488 #define RCC_CIR_PLLRDYC 0x00100000U
5489 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5490 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5491 #define RCC_CIR_CSSC 0x00800000U
5492 
5493 /******************** Bit definition for RCC_AHB1RSTR register **************/
5494 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5495 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5496 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5497 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5498 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5499 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5500 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5501 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5502 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5503 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
5504 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
5505 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5506 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5507 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5508 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
5509 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5510 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5511 
5512 /******************** Bit definition for RCC_AHB2RSTR register **************/
5513 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5514 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5515 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5516 
5517 /******************** Bit definition for RCC_AHB3RSTR register **************/
5518 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5519 
5520 /******************** Bit definition for RCC_APB1RSTR register **************/
5521 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5522 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5523 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5524 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5525 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5526 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5527 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5528 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5529 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5530 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5531 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5532 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5533 #define RCC_APB1RSTR_USART2RST 0x00020000U
5534 #define RCC_APB1RSTR_USART3RST 0x00040000U
5535 #define RCC_APB1RSTR_UART4RST 0x00080000U
5536 #define RCC_APB1RSTR_UART5RST 0x00100000U
5537 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5538 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5539 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5540 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5541 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5542 #define RCC_APB1RSTR_PWRRST 0x10000000U
5543 #define RCC_APB1RSTR_DACRST 0x20000000U
5544 #define RCC_APB1RSTR_UART7RST 0x40000000U
5545 #define RCC_APB1RSTR_UART8RST 0x80000000U
5546 
5547 /******************** Bit definition for RCC_APB2RSTR register **************/
5548 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5549 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5550 #define RCC_APB2RSTR_USART1RST 0x00000010U
5551 #define RCC_APB2RSTR_USART6RST 0x00000020U
5552 #define RCC_APB2RSTR_ADCRST 0x00000100U
5553 #define RCC_APB2RSTR_SDIORST 0x00000800U
5554 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5555 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5556 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5557 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5558 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5559 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5560 #define RCC_APB2RSTR_SPI5RST 0x00100000U
5561 #define RCC_APB2RSTR_SPI6RST 0x00200000U
5562 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5563 
5564 /* Old SPI1RST bit definition, maintained for legacy purpose */
5565 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5566 
5567 /******************** Bit definition for RCC_AHB1ENR register ***************/
5568 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5569 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5570 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5571 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5572 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5573 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5574 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5575 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5576 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5577 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
5578 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
5579 
5580 #define RCC_AHB1ENR_CRCEN 0x00001000U
5581 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5582 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
5583 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5584 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5585 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
5586 
5587 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5588 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5589 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5590 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5591 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5592 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5593 
5594 /******************** Bit definition for RCC_AHB2ENR register ***************/
5595 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5596 #define RCC_AHB2ENR_RNGEN 0x00000040U
5597 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5598 
5599 /******************** Bit definition for RCC_AHB3ENR register ***************/
5600 #define RCC_AHB3ENR_FMCEN 0x00000001U
5601 
5602 /******************** Bit definition for RCC_APB1ENR register ***************/
5603 #define RCC_APB1ENR_TIM2EN 0x00000001U
5604 #define RCC_APB1ENR_TIM3EN 0x00000002U
5605 #define RCC_APB1ENR_TIM4EN 0x00000004U
5606 #define RCC_APB1ENR_TIM5EN 0x00000008U
5607 #define RCC_APB1ENR_TIM6EN 0x00000010U
5608 #define RCC_APB1ENR_TIM7EN 0x00000020U
5609 #define RCC_APB1ENR_TIM12EN 0x00000040U
5610 #define RCC_APB1ENR_TIM13EN 0x00000080U
5611 #define RCC_APB1ENR_TIM14EN 0x00000100U
5612 #define RCC_APB1ENR_WWDGEN 0x00000800U
5613 #define RCC_APB1ENR_SPI2EN 0x00004000U
5614 #define RCC_APB1ENR_SPI3EN 0x00008000U
5615 #define RCC_APB1ENR_USART2EN 0x00020000U
5616 #define RCC_APB1ENR_USART3EN 0x00040000U
5617 #define RCC_APB1ENR_UART4EN 0x00080000U
5618 #define RCC_APB1ENR_UART5EN 0x00100000U
5619 #define RCC_APB1ENR_I2C1EN 0x00200000U
5620 #define RCC_APB1ENR_I2C2EN 0x00400000U
5621 #define RCC_APB1ENR_I2C3EN 0x00800000U
5622 #define RCC_APB1ENR_CAN1EN 0x02000000U
5623 #define RCC_APB1ENR_CAN2EN 0x04000000U
5624 #define RCC_APB1ENR_PWREN 0x10000000U
5625 #define RCC_APB1ENR_DACEN 0x20000000U
5626 #define RCC_APB1ENR_UART7EN 0x40000000U
5627 #define RCC_APB1ENR_UART8EN 0x80000000U
5628 
5629 /******************** Bit definition for RCC_APB2ENR register ***************/
5630 #define RCC_APB2ENR_TIM1EN 0x00000001U
5631 #define RCC_APB2ENR_TIM8EN 0x00000002U
5632 #define RCC_APB2ENR_USART1EN 0x00000010U
5633 #define RCC_APB2ENR_USART6EN 0x00000020U
5634 #define RCC_APB2ENR_ADC1EN 0x00000100U
5635 #define RCC_APB2ENR_ADC2EN 0x00000200U
5636 #define RCC_APB2ENR_ADC3EN 0x00000400U
5637 #define RCC_APB2ENR_SDIOEN 0x00000800U
5638 #define RCC_APB2ENR_SPI1EN 0x00001000U
5639 #define RCC_APB2ENR_SPI4EN 0x00002000U
5640 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5641 #define RCC_APB2ENR_TIM9EN 0x00010000U
5642 #define RCC_APB2ENR_TIM10EN 0x00020000U
5643 #define RCC_APB2ENR_TIM11EN 0x00040000U
5644 #define RCC_APB2ENR_SPI5EN 0x00100000U
5645 #define RCC_APB2ENR_SPI6EN 0x00200000U
5646 #define RCC_APB2ENR_SAI1EN 0x00400000U
5647 
5648 /******************** Bit definition for RCC_AHB1LPENR register *************/
5649 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5650 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5651 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5652 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5653 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5654 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5655 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5656 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5657 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5658 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
5659 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
5660 
5661 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5662 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5663 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5664 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5665 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5666 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5667 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5668 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
5669 
5670 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5671 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5672 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5673 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5674 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5675 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5676 
5677 /******************** Bit definition for RCC_AHB2LPENR register *************/
5678 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5679 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5680 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5681 
5682 /******************** Bit definition for RCC_AHB3LPENR register *************/
5683 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
5684 
5685 /******************** Bit definition for RCC_APB1LPENR register *************/
5686 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5687 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5688 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5689 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5690 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5691 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5692 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5693 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5694 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5695 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5696 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5697 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5698 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5699 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5700 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5701 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5702 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5703 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5704 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5705 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5706 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5707 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5708 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5709 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
5710 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
5711 
5712 /******************** Bit definition for RCC_APB2LPENR register *************/
5713 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5714 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5715 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5716 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5717 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5718 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5719 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5720 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
5721 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5722 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
5723 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5724 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5725 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5726 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5727 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
5728 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
5729 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
5730 
5731 /******************** Bit definition for RCC_BDCR register ******************/
5732 #define RCC_BDCR_LSEON 0x00000001U
5733 #define RCC_BDCR_LSERDY 0x00000002U
5734 #define RCC_BDCR_LSEBYP 0x00000004U
5735 
5736 #define RCC_BDCR_RTCSEL 0x00000300U
5737 #define RCC_BDCR_RTCSEL_0 0x00000100U
5738 #define RCC_BDCR_RTCSEL_1 0x00000200U
5739 
5740 #define RCC_BDCR_RTCEN 0x00008000U
5741 #define RCC_BDCR_BDRST 0x00010000U
5742 
5743 /******************** Bit definition for RCC_CSR register *******************/
5744 #define RCC_CSR_LSION 0x00000001U
5745 #define RCC_CSR_LSIRDY 0x00000002U
5746 #define RCC_CSR_RMVF 0x01000000U
5747 #define RCC_CSR_BORRSTF 0x02000000U
5748 #define RCC_CSR_PADRSTF 0x04000000U
5749 #define RCC_CSR_PORRSTF 0x08000000U
5750 #define RCC_CSR_SFTRSTF 0x10000000U
5751 #define RCC_CSR_WDGRSTF 0x20000000U
5752 #define RCC_CSR_WWDGRSTF 0x40000000U
5753 #define RCC_CSR_LPWRRSTF 0x80000000U
5754 
5755 /******************** Bit definition for RCC_SSCGR register *****************/
5756 #define RCC_SSCGR_MODPER 0x00001FFFU
5757 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5758 #define RCC_SSCGR_SPREADSEL 0x40000000U
5759 #define RCC_SSCGR_SSCGEN 0x80000000U
5760 
5761 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5762 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5763 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5764 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5765 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5766 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5767 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5768 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5769 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5770 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5771 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5772 
5773 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
5774 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
5775 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
5776 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
5777 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
5778 
5779 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5780 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5781 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5782 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5783 
5784 
5785 /******************** Bit definition for RCC_PLLSAICFGR register ************/
5786 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
5787 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
5788 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
5789 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
5790 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
5791 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
5792 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
5793 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
5794 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
5795 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
5796 
5797 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
5798 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
5799 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
5800 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
5801 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
5802 
5803 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
5804 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
5805 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
5806 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
5807 
5808 /******************** Bit definition for RCC_DCKCFGR register ***************/
5809 #define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
5810 #define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
5811 #define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
5812 #define RCC_DCKCFGR_SAI1ASRC 0x00300000U
5813 #define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
5814 #define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
5815 #define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
5816 #define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
5817 #define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
5818 #define RCC_DCKCFGR_TIMPRE 0x01000000U
5819 
5820 
5821 /******************************************************************************/
5822 /* */
5823 /* RNG */
5824 /* */
5825 /******************************************************************************/
5826 /******************** Bits definition for RNG_CR register *******************/
5827 #define RNG_CR_RNGEN 0x00000004U
5828 #define RNG_CR_IE 0x00000008U
5829 
5830 /******************** Bits definition for RNG_SR register *******************/
5831 #define RNG_SR_DRDY 0x00000001U
5832 #define RNG_SR_CECS 0x00000002U
5833 #define RNG_SR_SECS 0x00000004U
5834 #define RNG_SR_CEIS 0x00000020U
5835 #define RNG_SR_SEIS 0x00000040U
5836 
5837 /******************************************************************************/
5838 /* */
5839 /* Real-Time Clock (RTC) */
5840 /* */
5841 /******************************************************************************/
5842 /******************** Bits definition for RTC_TR register *******************/
5843 #define RTC_TR_PM 0x00400000U
5844 #define RTC_TR_HT 0x00300000U
5845 #define RTC_TR_HT_0 0x00100000U
5846 #define RTC_TR_HT_1 0x00200000U
5847 #define RTC_TR_HU 0x000F0000U
5848 #define RTC_TR_HU_0 0x00010000U
5849 #define RTC_TR_HU_1 0x00020000U
5850 #define RTC_TR_HU_2 0x00040000U
5851 #define RTC_TR_HU_3 0x00080000U
5852 #define RTC_TR_MNT 0x00007000U
5853 #define RTC_TR_MNT_0 0x00001000U
5854 #define RTC_TR_MNT_1 0x00002000U
5855 #define RTC_TR_MNT_2 0x00004000U
5856 #define RTC_TR_MNU 0x00000F00U
5857 #define RTC_TR_MNU_0 0x00000100U
5858 #define RTC_TR_MNU_1 0x00000200U
5859 #define RTC_TR_MNU_2 0x00000400U
5860 #define RTC_TR_MNU_3 0x00000800U
5861 #define RTC_TR_ST 0x00000070U
5862 #define RTC_TR_ST_0 0x00000010U
5863 #define RTC_TR_ST_1 0x00000020U
5864 #define RTC_TR_ST_2 0x00000040U
5865 #define RTC_TR_SU 0x0000000FU
5866 #define RTC_TR_SU_0 0x00000001U
5867 #define RTC_TR_SU_1 0x00000002U
5868 #define RTC_TR_SU_2 0x00000004U
5869 #define RTC_TR_SU_3 0x00000008U
5870 
5871 /******************** Bits definition for RTC_DR register *******************/
5872 #define RTC_DR_YT 0x00F00000U
5873 #define RTC_DR_YT_0 0x00100000U
5874 #define RTC_DR_YT_1 0x00200000U
5875 #define RTC_DR_YT_2 0x00400000U
5876 #define RTC_DR_YT_3 0x00800000U
5877 #define RTC_DR_YU 0x000F0000U
5878 #define RTC_DR_YU_0 0x00010000U
5879 #define RTC_DR_YU_1 0x00020000U
5880 #define RTC_DR_YU_2 0x00040000U
5881 #define RTC_DR_YU_3 0x00080000U
5882 #define RTC_DR_WDU 0x0000E000U
5883 #define RTC_DR_WDU_0 0x00002000U
5884 #define RTC_DR_WDU_1 0x00004000U
5885 #define RTC_DR_WDU_2 0x00008000U
5886 #define RTC_DR_MT 0x00001000U
5887 #define RTC_DR_MU 0x00000F00U
5888 #define RTC_DR_MU_0 0x00000100U
5889 #define RTC_DR_MU_1 0x00000200U
5890 #define RTC_DR_MU_2 0x00000400U
5891 #define RTC_DR_MU_3 0x00000800U
5892 #define RTC_DR_DT 0x00000030U
5893 #define RTC_DR_DT_0 0x00000010U
5894 #define RTC_DR_DT_1 0x00000020U
5895 #define RTC_DR_DU 0x0000000FU
5896 #define RTC_DR_DU_0 0x00000001U
5897 #define RTC_DR_DU_1 0x00000002U
5898 #define RTC_DR_DU_2 0x00000004U
5899 #define RTC_DR_DU_3 0x00000008U
5900 
5901 /******************** Bits definition for RTC_CR register *******************/
5902 #define RTC_CR_COE 0x00800000U
5903 #define RTC_CR_OSEL 0x00600000U
5904 #define RTC_CR_OSEL_0 0x00200000U
5905 #define RTC_CR_OSEL_1 0x00400000U
5906 #define RTC_CR_POL 0x00100000U
5907 #define RTC_CR_COSEL 0x00080000U
5908 #define RTC_CR_BCK 0x00040000U
5909 #define RTC_CR_SUB1H 0x00020000U
5910 #define RTC_CR_ADD1H 0x00010000U
5911 #define RTC_CR_TSIE 0x00008000U
5912 #define RTC_CR_WUTIE 0x00004000U
5913 #define RTC_CR_ALRBIE 0x00002000U
5914 #define RTC_CR_ALRAIE 0x00001000U
5915 #define RTC_CR_TSE 0x00000800U
5916 #define RTC_CR_WUTE 0x00000400U
5917 #define RTC_CR_ALRBE 0x00000200U
5918 #define RTC_CR_ALRAE 0x00000100U
5919 #define RTC_CR_DCE 0x00000080U
5920 #define RTC_CR_FMT 0x00000040U
5921 #define RTC_CR_BYPSHAD 0x00000020U
5922 #define RTC_CR_REFCKON 0x00000010U
5923 #define RTC_CR_TSEDGE 0x00000008U
5924 #define RTC_CR_WUCKSEL 0x00000007U
5925 #define RTC_CR_WUCKSEL_0 0x00000001U
5926 #define RTC_CR_WUCKSEL_1 0x00000002U
5927 #define RTC_CR_WUCKSEL_2 0x00000004U
5928 
5929 /******************** Bits definition for RTC_ISR register ******************/
5930 #define RTC_ISR_RECALPF 0x00010000U
5931 #define RTC_ISR_TAMP1F 0x00002000U
5932 #define RTC_ISR_TAMP2F 0x00004000U
5933 #define RTC_ISR_TSOVF 0x00001000U
5934 #define RTC_ISR_TSF 0x00000800U
5935 #define RTC_ISR_WUTF 0x00000400U
5936 #define RTC_ISR_ALRBF 0x00000200U
5937 #define RTC_ISR_ALRAF 0x00000100U
5938 #define RTC_ISR_INIT 0x00000080U
5939 #define RTC_ISR_INITF 0x00000040U
5940 #define RTC_ISR_RSF 0x00000020U
5941 #define RTC_ISR_INITS 0x00000010U
5942 #define RTC_ISR_SHPF 0x00000008U
5943 #define RTC_ISR_WUTWF 0x00000004U
5944 #define RTC_ISR_ALRBWF 0x00000002U
5945 #define RTC_ISR_ALRAWF 0x00000001U
5946 
5947 /******************** Bits definition for RTC_PRER register *****************/
5948 #define RTC_PRER_PREDIV_A 0x007F0000U
5949 #define RTC_PRER_PREDIV_S 0x00007FFFU
5950 
5951 /******************** Bits definition for RTC_WUTR register *****************/
5952 #define RTC_WUTR_WUT 0x0000FFFFU
5953 
5954 /******************** Bits definition for RTC_CALIBR register ***************/
5955 #define RTC_CALIBR_DCS 0x00000080U
5956 #define RTC_CALIBR_DC 0x0000001FU
5957 
5958 /******************** Bits definition for RTC_ALRMAR register ***************/
5959 #define RTC_ALRMAR_MSK4 0x80000000U
5960 #define RTC_ALRMAR_WDSEL 0x40000000U
5961 #define RTC_ALRMAR_DT 0x30000000U
5962 #define RTC_ALRMAR_DT_0 0x10000000U
5963 #define RTC_ALRMAR_DT_1 0x20000000U
5964 #define RTC_ALRMAR_DU 0x0F000000U
5965 #define RTC_ALRMAR_DU_0 0x01000000U
5966 #define RTC_ALRMAR_DU_1 0x02000000U
5967 #define RTC_ALRMAR_DU_2 0x04000000U
5968 #define RTC_ALRMAR_DU_3 0x08000000U
5969 #define RTC_ALRMAR_MSK3 0x00800000U
5970 #define RTC_ALRMAR_PM 0x00400000U
5971 #define RTC_ALRMAR_HT 0x00300000U
5972 #define RTC_ALRMAR_HT_0 0x00100000U
5973 #define RTC_ALRMAR_HT_1 0x00200000U
5974 #define RTC_ALRMAR_HU 0x000F0000U
5975 #define RTC_ALRMAR_HU_0 0x00010000U
5976 #define RTC_ALRMAR_HU_1 0x00020000U
5977 #define RTC_ALRMAR_HU_2 0x00040000U
5978 #define RTC_ALRMAR_HU_3 0x00080000U
5979 #define RTC_ALRMAR_MSK2 0x00008000U
5980 #define RTC_ALRMAR_MNT 0x00007000U
5981 #define RTC_ALRMAR_MNT_0 0x00001000U
5982 #define RTC_ALRMAR_MNT_1 0x00002000U
5983 #define RTC_ALRMAR_MNT_2 0x00004000U
5984 #define RTC_ALRMAR_MNU 0x00000F00U
5985 #define RTC_ALRMAR_MNU_0 0x00000100U
5986 #define RTC_ALRMAR_MNU_1 0x00000200U
5987 #define RTC_ALRMAR_MNU_2 0x00000400U
5988 #define RTC_ALRMAR_MNU_3 0x00000800U
5989 #define RTC_ALRMAR_MSK1 0x00000080U
5990 #define RTC_ALRMAR_ST 0x00000070U
5991 #define RTC_ALRMAR_ST_0 0x00000010U
5992 #define RTC_ALRMAR_ST_1 0x00000020U
5993 #define RTC_ALRMAR_ST_2 0x00000040U
5994 #define RTC_ALRMAR_SU 0x0000000FU
5995 #define RTC_ALRMAR_SU_0 0x00000001U
5996 #define RTC_ALRMAR_SU_1 0x00000002U
5997 #define RTC_ALRMAR_SU_2 0x00000004U
5998 #define RTC_ALRMAR_SU_3 0x00000008U
5999 
6000 /******************** Bits definition for RTC_ALRMBR register ***************/
6001 #define RTC_ALRMBR_MSK4 0x80000000U
6002 #define RTC_ALRMBR_WDSEL 0x40000000U
6003 #define RTC_ALRMBR_DT 0x30000000U
6004 #define RTC_ALRMBR_DT_0 0x10000000U
6005 #define RTC_ALRMBR_DT_1 0x20000000U
6006 #define RTC_ALRMBR_DU 0x0F000000U
6007 #define RTC_ALRMBR_DU_0 0x01000000U
6008 #define RTC_ALRMBR_DU_1 0x02000000U
6009 #define RTC_ALRMBR_DU_2 0x04000000U
6010 #define RTC_ALRMBR_DU_3 0x08000000U
6011 #define RTC_ALRMBR_MSK3 0x00800000U
6012 #define RTC_ALRMBR_PM 0x00400000U
6013 #define RTC_ALRMBR_HT 0x00300000U
6014 #define RTC_ALRMBR_HT_0 0x00100000U
6015 #define RTC_ALRMBR_HT_1 0x00200000U
6016 #define RTC_ALRMBR_HU 0x000F0000U
6017 #define RTC_ALRMBR_HU_0 0x00010000U
6018 #define RTC_ALRMBR_HU_1 0x00020000U
6019 #define RTC_ALRMBR_HU_2 0x00040000U
6020 #define RTC_ALRMBR_HU_3 0x00080000U
6021 #define RTC_ALRMBR_MSK2 0x00008000U
6022 #define RTC_ALRMBR_MNT 0x00007000U
6023 #define RTC_ALRMBR_MNT_0 0x00001000U
6024 #define RTC_ALRMBR_MNT_1 0x00002000U
6025 #define RTC_ALRMBR_MNT_2 0x00004000U
6026 #define RTC_ALRMBR_MNU 0x00000F00U
6027 #define RTC_ALRMBR_MNU_0 0x00000100U
6028 #define RTC_ALRMBR_MNU_1 0x00000200U
6029 #define RTC_ALRMBR_MNU_2 0x00000400U
6030 #define RTC_ALRMBR_MNU_3 0x00000800U
6031 #define RTC_ALRMBR_MSK1 0x00000080U
6032 #define RTC_ALRMBR_ST 0x00000070U
6033 #define RTC_ALRMBR_ST_0 0x00000010U
6034 #define RTC_ALRMBR_ST_1 0x00000020U
6035 #define RTC_ALRMBR_ST_2 0x00000040U
6036 #define RTC_ALRMBR_SU 0x0000000FU
6037 #define RTC_ALRMBR_SU_0 0x00000001U
6038 #define RTC_ALRMBR_SU_1 0x00000002U
6039 #define RTC_ALRMBR_SU_2 0x00000004U
6040 #define RTC_ALRMBR_SU_3 0x00000008U
6041 
6042 /******************** Bits definition for RTC_WPR register ******************/
6043 #define RTC_WPR_KEY 0x000000FFU
6044 
6045 /******************** Bits definition for RTC_SSR register ******************/
6046 #define RTC_SSR_SS 0x0000FFFFU
6047 
6048 /******************** Bits definition for RTC_SHIFTR register ***************/
6049 #define RTC_SHIFTR_SUBFS 0x00007FFFU
6050 #define RTC_SHIFTR_ADD1S 0x80000000U
6051 
6052 /******************** Bits definition for RTC_TSTR register *****************/
6053 #define RTC_TSTR_PM 0x00400000U
6054 #define RTC_TSTR_HT 0x00300000U
6055 #define RTC_TSTR_HT_0 0x00100000U
6056 #define RTC_TSTR_HT_1 0x00200000U
6057 #define RTC_TSTR_HU 0x000F0000U
6058 #define RTC_TSTR_HU_0 0x00010000U
6059 #define RTC_TSTR_HU_1 0x00020000U
6060 #define RTC_TSTR_HU_2 0x00040000U
6061 #define RTC_TSTR_HU_3 0x00080000U
6062 #define RTC_TSTR_MNT 0x00007000U
6063 #define RTC_TSTR_MNT_0 0x00001000U
6064 #define RTC_TSTR_MNT_1 0x00002000U
6065 #define RTC_TSTR_MNT_2 0x00004000U
6066 #define RTC_TSTR_MNU 0x00000F00U
6067 #define RTC_TSTR_MNU_0 0x00000100U
6068 #define RTC_TSTR_MNU_1 0x00000200U
6069 #define RTC_TSTR_MNU_2 0x00000400U
6070 #define RTC_TSTR_MNU_3 0x00000800U
6071 #define RTC_TSTR_ST 0x00000070U
6072 #define RTC_TSTR_ST_0 0x00000010U
6073 #define RTC_TSTR_ST_1 0x00000020U
6074 #define RTC_TSTR_ST_2 0x00000040U
6075 #define RTC_TSTR_SU 0x0000000FU
6076 #define RTC_TSTR_SU_0 0x00000001U
6077 #define RTC_TSTR_SU_1 0x00000002U
6078 #define RTC_TSTR_SU_2 0x00000004U
6079 #define RTC_TSTR_SU_3 0x00000008U
6080 
6081 /******************** Bits definition for RTC_TSDR register *****************/
6082 #define RTC_TSDR_WDU 0x0000E000U
6083 #define RTC_TSDR_WDU_0 0x00002000U
6084 #define RTC_TSDR_WDU_1 0x00004000U
6085 #define RTC_TSDR_WDU_2 0x00008000U
6086 #define RTC_TSDR_MT 0x00001000U
6087 #define RTC_TSDR_MU 0x00000F00U
6088 #define RTC_TSDR_MU_0 0x00000100U
6089 #define RTC_TSDR_MU_1 0x00000200U
6090 #define RTC_TSDR_MU_2 0x00000400U
6091 #define RTC_TSDR_MU_3 0x00000800U
6092 #define RTC_TSDR_DT 0x00000030U
6093 #define RTC_TSDR_DT_0 0x00000010U
6094 #define RTC_TSDR_DT_1 0x00000020U
6095 #define RTC_TSDR_DU 0x0000000FU
6096 #define RTC_TSDR_DU_0 0x00000001U
6097 #define RTC_TSDR_DU_1 0x00000002U
6098 #define RTC_TSDR_DU_2 0x00000004U
6099 #define RTC_TSDR_DU_3 0x00000008U
6100 
6101 /******************** Bits definition for RTC_TSSSR register ****************/
6102 #define RTC_TSSSR_SS 0x0000FFFFU
6103 
6104 /******************** Bits definition for RTC_CAL register *****************/
6105 #define RTC_CALR_CALP 0x00008000U
6106 #define RTC_CALR_CALW8 0x00004000U
6107 #define RTC_CALR_CALW16 0x00002000U
6108 #define RTC_CALR_CALM 0x000001FFU
6109 #define RTC_CALR_CALM_0 0x00000001U
6110 #define RTC_CALR_CALM_1 0x00000002U
6111 #define RTC_CALR_CALM_2 0x00000004U
6112 #define RTC_CALR_CALM_3 0x00000008U
6113 #define RTC_CALR_CALM_4 0x00000010U
6114 #define RTC_CALR_CALM_5 0x00000020U
6115 #define RTC_CALR_CALM_6 0x00000040U
6116 #define RTC_CALR_CALM_7 0x00000080U
6117 #define RTC_CALR_CALM_8 0x00000100U
6118 
6119 /******************** Bits definition for RTC_TAFCR register ****************/
6120 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
6121 #define RTC_TAFCR_TSINSEL 0x00020000U
6122 #define RTC_TAFCR_TAMPINSEL 0x00010000U
6123 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
6124 #define RTC_TAFCR_TAMPPRCH 0x00006000U
6125 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
6126 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
6127 #define RTC_TAFCR_TAMPFLT 0x00001800U
6128 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
6129 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
6130 #define RTC_TAFCR_TAMPFREQ 0x00000700U
6131 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
6132 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
6133 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
6134 #define RTC_TAFCR_TAMPTS 0x00000080U
6135 #define RTC_TAFCR_TAMP2TRG 0x00000010U
6136 #define RTC_TAFCR_TAMP2E 0x00000008U
6137 #define RTC_TAFCR_TAMPIE 0x00000004U
6138 #define RTC_TAFCR_TAMP1TRG 0x00000002U
6139 #define RTC_TAFCR_TAMP1E 0x00000001U
6140 
6141 /******************** Bits definition for RTC_ALRMASSR register *************/
6142 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6143 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6144 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6145 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6146 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6147 #define RTC_ALRMASSR_SS 0x00007FFFU
6148 
6149 /******************** Bits definition for RTC_ALRMBSSR register *************/
6150 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6151 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6152 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6153 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6154 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6155 #define RTC_ALRMBSSR_SS 0x00007FFFU
6156 
6157 /******************** Bits definition for RTC_BKP0R register ****************/
6158 #define RTC_BKP0R 0xFFFFFFFFU
6159 
6160 /******************** Bits definition for RTC_BKP1R register ****************/
6161 #define RTC_BKP1R 0xFFFFFFFFU
6162 
6163 /******************** Bits definition for RTC_BKP2R register ****************/
6164 #define RTC_BKP2R 0xFFFFFFFFU
6165 
6166 /******************** Bits definition for RTC_BKP3R register ****************/
6167 #define RTC_BKP3R 0xFFFFFFFFU
6168 
6169 /******************** Bits definition for RTC_BKP4R register ****************/
6170 #define RTC_BKP4R 0xFFFFFFFFU
6171 
6172 /******************** Bits definition for RTC_BKP5R register ****************/
6173 #define RTC_BKP5R 0xFFFFFFFFU
6174 
6175 /******************** Bits definition for RTC_BKP6R register ****************/
6176 #define RTC_BKP6R 0xFFFFFFFFU
6177 
6178 /******************** Bits definition for RTC_BKP7R register ****************/
6179 #define RTC_BKP7R 0xFFFFFFFFU
6180 
6181 /******************** Bits definition for RTC_BKP8R register ****************/
6182 #define RTC_BKP8R 0xFFFFFFFFU
6183 
6184 /******************** Bits definition for RTC_BKP9R register ****************/
6185 #define RTC_BKP9R 0xFFFFFFFFU
6186 
6187 /******************** Bits definition for RTC_BKP10R register ***************/
6188 #define RTC_BKP10R 0xFFFFFFFFU
6189 
6190 /******************** Bits definition for RTC_BKP11R register ***************/
6191 #define RTC_BKP11R 0xFFFFFFFFU
6192 
6193 /******************** Bits definition for RTC_BKP12R register ***************/
6194 #define RTC_BKP12R 0xFFFFFFFFU
6195 
6196 /******************** Bits definition for RTC_BKP13R register ***************/
6197 #define RTC_BKP13R 0xFFFFFFFFU
6198 
6199 /******************** Bits definition for RTC_BKP14R register ***************/
6200 #define RTC_BKP14R 0xFFFFFFFFU
6201 
6202 /******************** Bits definition for RTC_BKP15R register ***************/
6203 #define RTC_BKP15R 0xFFFFFFFFU
6204 
6205 /******************** Bits definition for RTC_BKP16R register ***************/
6206 #define RTC_BKP16R 0xFFFFFFFFU
6207 
6208 /******************** Bits definition for RTC_BKP17R register ***************/
6209 #define RTC_BKP17R 0xFFFFFFFFU
6210 
6211 /******************** Bits definition for RTC_BKP18R register ***************/
6212 #define RTC_BKP18R 0xFFFFFFFFU
6213 
6214 /******************** Bits definition for RTC_BKP19R register ***************/
6215 #define RTC_BKP19R 0xFFFFFFFFU
6216 
6217 /******************************************************************************/
6218 /* */
6219 /* Serial Audio Interface */
6220 /* */
6221 /******************************************************************************/
6222 /******************** Bit definition for SAI_GCR register *******************/
6223 #define SAI_GCR_SYNCIN 0x00000003U
6224 #define SAI_GCR_SYNCIN_0 0x00000001U
6225 #define SAI_GCR_SYNCIN_1 0x00000002U
6227 #define SAI_GCR_SYNCOUT 0x00000030U
6228 #define SAI_GCR_SYNCOUT_0 0x00000010U
6229 #define SAI_GCR_SYNCOUT_1 0x00000020U
6231 /******************* Bit definition for SAI_xCR1 register *******************/
6232 #define SAI_xCR1_MODE 0x00000003U
6233 #define SAI_xCR1_MODE_0 0x00000001U
6234 #define SAI_xCR1_MODE_1 0x00000002U
6236 #define SAI_xCR1_PRTCFG 0x0000000CU
6237 #define SAI_xCR1_PRTCFG_0 0x00000004U
6238 #define SAI_xCR1_PRTCFG_1 0x00000008U
6240 #define SAI_xCR1_DS 0x000000E0U
6241 #define SAI_xCR1_DS_0 0x00000020U
6242 #define SAI_xCR1_DS_1 0x00000040U
6243 #define SAI_xCR1_DS_2 0x00000080U
6245 #define SAI_xCR1_LSBFIRST 0x00000100U
6246 #define SAI_xCR1_CKSTR 0x00000200U
6248 #define SAI_xCR1_SYNCEN 0x00000C00U
6249 #define SAI_xCR1_SYNCEN_0 0x00000400U
6250 #define SAI_xCR1_SYNCEN_1 0x00000800U
6252 #define SAI_xCR1_MONO 0x00001000U
6253 #define SAI_xCR1_OUTDRIV 0x00002000U
6254 #define SAI_xCR1_SAIEN 0x00010000U
6255 #define SAI_xCR1_DMAEN 0x00020000U
6256 #define SAI_xCR1_NODIV 0x00080000U
6258 #define SAI_xCR1_MCKDIV 0x00F00000U
6259 #define SAI_xCR1_MCKDIV_0 0x00100000U
6260 #define SAI_xCR1_MCKDIV_1 0x00200000U
6261 #define SAI_xCR1_MCKDIV_2 0x00400000U
6262 #define SAI_xCR1_MCKDIV_3 0x00800000U
6264 /******************* Bit definition for SAI_xCR2 register *******************/
6265 #define SAI_xCR2_FTH 0x00000007U
6266 #define SAI_xCR2_FTH_0 0x00000001U
6267 #define SAI_xCR2_FTH_1 0x00000002U
6268 #define SAI_xCR2_FTH_2 0x00000004U
6270 #define SAI_xCR2_FFLUSH 0x00000008U
6271 #define SAI_xCR2_TRIS 0x00000010U
6272 #define SAI_xCR2_MUTE 0x00000020U
6273 #define SAI_xCR2_MUTEVAL 0x00000040U
6275 #define SAI_xCR2_MUTECNT 0x00001F80U
6276 #define SAI_xCR2_MUTECNT_0 0x00000080U
6277 #define SAI_xCR2_MUTECNT_1 0x00000100U
6278 #define SAI_xCR2_MUTECNT_2 0x00000200U
6279 #define SAI_xCR2_MUTECNT_3 0x00000400U
6280 #define SAI_xCR2_MUTECNT_4 0x00000800U
6281 #define SAI_xCR2_MUTECNT_5 0x00001000U
6283 #define SAI_xCR2_CPL 0x00002000U
6285 #define SAI_xCR2_COMP 0x0000C000U
6286 #define SAI_xCR2_COMP_0 0x00004000U
6287 #define SAI_xCR2_COMP_1 0x00008000U
6289 /****************** Bit definition for SAI_xFRCR register *******************/
6290 #define SAI_xFRCR_FRL 0x000000FFU
6291 #define SAI_xFRCR_FRL_0 0x00000001U
6292 #define SAI_xFRCR_FRL_1 0x00000002U
6293 #define SAI_xFRCR_FRL_2 0x00000004U
6294 #define SAI_xFRCR_FRL_3 0x00000008U
6295 #define SAI_xFRCR_FRL_4 0x00000010U
6296 #define SAI_xFRCR_FRL_5 0x00000020U
6297 #define SAI_xFRCR_FRL_6 0x00000040U
6298 #define SAI_xFRCR_FRL_7 0x00000080U
6300 #define SAI_xFRCR_FSALL 0x00007F00U
6301 #define SAI_xFRCR_FSALL_0 0x00000100U
6302 #define SAI_xFRCR_FSALL_1 0x00000200U
6303 #define SAI_xFRCR_FSALL_2 0x00000400U
6304 #define SAI_xFRCR_FSALL_3 0x00000800U
6305 #define SAI_xFRCR_FSALL_4 0x00001000U
6306 #define SAI_xFRCR_FSALL_5 0x00002000U
6307 #define SAI_xFRCR_FSALL_6 0x00004000U
6309 #define SAI_xFRCR_FSDEF 0x00010000U
6310 #define SAI_xFRCR_FSPOL 0x00020000U
6311 #define SAI_xFRCR_FSOFF 0x00040000U
6312 /* Legacy defines */
6313 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6314 
6315 /****************** Bit definition for SAI_xSLOTR register *******************/
6316 #define SAI_xSLOTR_FBOFF 0x0000001FU
6317 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6318 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6319 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6320 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6321 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6323 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6324 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6325 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6327 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6328 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6329 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6330 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6331 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6333 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6335 /******************* Bit definition for SAI_xIMR register *******************/
6336 #define SAI_xIMR_OVRUDRIE 0x00000001U
6337 #define SAI_xIMR_MUTEDETIE 0x00000002U
6338 #define SAI_xIMR_WCKCFGIE 0x00000004U
6339 #define SAI_xIMR_FREQIE 0x00000008U
6340 #define SAI_xIMR_CNRDYIE 0x00000010U
6341 #define SAI_xIMR_AFSDETIE 0x00000020U
6342 #define SAI_xIMR_LFSDETIE 0x00000040U
6344 /******************** Bit definition for SAI_xSR register *******************/
6345 #define SAI_xSR_OVRUDR 0x00000001U
6346 #define SAI_xSR_MUTEDET 0x00000002U
6347 #define SAI_xSR_WCKCFG 0x00000004U
6348 #define SAI_xSR_FREQ 0x00000008U
6349 #define SAI_xSR_CNRDY 0x00000010U
6350 #define SAI_xSR_AFSDET 0x00000020U
6351 #define SAI_xSR_LFSDET 0x00000040U
6353 #define SAI_xSR_FLVL 0x00070000U
6354 #define SAI_xSR_FLVL_0 0x00010000U
6355 #define SAI_xSR_FLVL_1 0x00020000U
6356 #define SAI_xSR_FLVL_2 0x00040000U
6358 /****************** Bit definition for SAI_xCLRFR register ******************/
6359 #define SAI_xCLRFR_COVRUDR 0x00000001U
6360 #define SAI_xCLRFR_CMUTEDET 0x00000002U
6361 #define SAI_xCLRFR_CWCKCFG 0x00000004U
6362 #define SAI_xCLRFR_CFREQ 0x00000008U
6363 #define SAI_xCLRFR_CCNRDY 0x00000010U
6364 #define SAI_xCLRFR_CAFSDET 0x00000020U
6365 #define SAI_xCLRFR_CLFSDET 0x00000040U
6367 /****************** Bit definition for SAI_xDR register ******************/
6368 #define SAI_xDR_DATA 0xFFFFFFFFU
6369 
6370 
6371 /******************************************************************************/
6372 /* */
6373 /* SD host Interface */
6374 /* */
6375 /******************************************************************************/
6376 /****************** Bit definition for SDIO_POWER register ******************/
6377 #define SDIO_POWER_PWRCTRL 0x03U
6378 #define SDIO_POWER_PWRCTRL_0 0x01U
6379 #define SDIO_POWER_PWRCTRL_1 0x02U
6381 /****************** Bit definition for SDIO_CLKCR register ******************/
6382 #define SDIO_CLKCR_CLKDIV 0x00FFU
6383 #define SDIO_CLKCR_CLKEN 0x0100U
6384 #define SDIO_CLKCR_PWRSAV 0x0200U
6385 #define SDIO_CLKCR_BYPASS 0x0400U
6387 #define SDIO_CLKCR_WIDBUS 0x1800U
6388 #define SDIO_CLKCR_WIDBUS_0 0x0800U
6389 #define SDIO_CLKCR_WIDBUS_1 0x1000U
6391 #define SDIO_CLKCR_NEGEDGE 0x2000U
6392 #define SDIO_CLKCR_HWFC_EN 0x4000U
6394 /******************* Bit definition for SDIO_ARG register *******************/
6395 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
6397 /******************* Bit definition for SDIO_CMD register *******************/
6398 #define SDIO_CMD_CMDINDEX 0x003FU
6400 #define SDIO_CMD_WAITRESP 0x00C0U
6401 #define SDIO_CMD_WAITRESP_0 0x0040U
6402 #define SDIO_CMD_WAITRESP_1 0x0080U
6404 #define SDIO_CMD_WAITINT 0x0100U
6405 #define SDIO_CMD_WAITPEND 0x0200U
6406 #define SDIO_CMD_CPSMEN 0x0400U
6407 #define SDIO_CMD_SDIOSUSPEND 0x0800U
6408 #define SDIO_CMD_ENCMDCOMPL 0x1000U
6409 #define SDIO_CMD_NIEN 0x2000U
6410 #define SDIO_CMD_CEATACMD 0x4000U
6412 /***************** Bit definition for SDIO_RESPCMD register *****************/
6413 #define SDIO_RESPCMD_RESPCMD 0x3FU
6415 /****************** Bit definition for SDIO_RESP0 register ******************/
6416 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
6418 /****************** Bit definition for SDIO_RESP1 register ******************/
6419 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
6421 /****************** Bit definition for SDIO_RESP2 register ******************/
6422 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
6424 /****************** Bit definition for SDIO_RESP3 register ******************/
6425 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
6427 /****************** Bit definition for SDIO_RESP4 register ******************/
6428 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
6430 /****************** Bit definition for SDIO_DTIMER register *****************/
6431 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
6433 /****************** Bit definition for SDIO_DLEN register *******************/
6434 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
6436 /****************** Bit definition for SDIO_DCTRL register ******************/
6437 #define SDIO_DCTRL_DTEN 0x0001U
6438 #define SDIO_DCTRL_DTDIR 0x0002U
6439 #define SDIO_DCTRL_DTMODE 0x0004U
6440 #define SDIO_DCTRL_DMAEN 0x0008U
6442 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
6443 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
6444 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
6445 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
6446 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
6448 #define SDIO_DCTRL_RWSTART 0x0100U
6449 #define SDIO_DCTRL_RWSTOP 0x0200U
6450 #define SDIO_DCTRL_RWMOD 0x0400U
6451 #define SDIO_DCTRL_SDIOEN 0x0800U
6453 /****************** Bit definition for SDIO_DCOUNT register *****************/
6454 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
6456 /****************** Bit definition for SDIO_STA register ********************/
6457 #define SDIO_STA_CCRCFAIL 0x00000001U
6458 #define SDIO_STA_DCRCFAIL 0x00000002U
6459 #define SDIO_STA_CTIMEOUT 0x00000004U
6460 #define SDIO_STA_DTIMEOUT 0x00000008U
6461 #define SDIO_STA_TXUNDERR 0x00000010U
6462 #define SDIO_STA_RXOVERR 0x00000020U
6463 #define SDIO_STA_CMDREND 0x00000040U
6464 #define SDIO_STA_CMDSENT 0x00000080U
6465 #define SDIO_STA_DATAEND 0x00000100U
6466 #define SDIO_STA_STBITERR 0x00000200U
6467 #define SDIO_STA_DBCKEND 0x00000400U
6468 #define SDIO_STA_CMDACT 0x00000800U
6469 #define SDIO_STA_TXACT 0x00001000U
6470 #define SDIO_STA_RXACT 0x00002000U
6471 #define SDIO_STA_TXFIFOHE 0x00004000U
6472 #define SDIO_STA_RXFIFOHF 0x00008000U
6473 #define SDIO_STA_TXFIFOF 0x00010000U
6474 #define SDIO_STA_RXFIFOF 0x00020000U
6475 #define SDIO_STA_TXFIFOE 0x00040000U
6476 #define SDIO_STA_RXFIFOE 0x00080000U
6477 #define SDIO_STA_TXDAVL 0x00100000U
6478 #define SDIO_STA_RXDAVL 0x00200000U
6479 #define SDIO_STA_SDIOIT 0x00400000U
6480 #define SDIO_STA_CEATAEND 0x00800000U
6482 /******************* Bit definition for SDIO_ICR register *******************/
6483 #define SDIO_ICR_CCRCFAILC 0x00000001U
6484 #define SDIO_ICR_DCRCFAILC 0x00000002U
6485 #define SDIO_ICR_CTIMEOUTC 0x00000004U
6486 #define SDIO_ICR_DTIMEOUTC 0x00000008U
6487 #define SDIO_ICR_TXUNDERRC 0x00000010U
6488 #define SDIO_ICR_RXOVERRC 0x00000020U
6489 #define SDIO_ICR_CMDRENDC 0x00000040U
6490 #define SDIO_ICR_CMDSENTC 0x00000080U
6491 #define SDIO_ICR_DATAENDC 0x00000100U
6492 #define SDIO_ICR_STBITERRC 0x00000200U
6493 #define SDIO_ICR_DBCKENDC 0x00000400U
6494 #define SDIO_ICR_SDIOITC 0x00400000U
6495 #define SDIO_ICR_CEATAENDC 0x00800000U
6497 /****************** Bit definition for SDIO_MASK register *******************/
6498 #define SDIO_MASK_CCRCFAILIE 0x00000001U
6499 #define SDIO_MASK_DCRCFAILIE 0x00000002U
6500 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
6501 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
6502 #define SDIO_MASK_TXUNDERRIE 0x00000010U
6503 #define SDIO_MASK_RXOVERRIE 0x00000020U
6504 #define SDIO_MASK_CMDRENDIE 0x00000040U
6505 #define SDIO_MASK_CMDSENTIE 0x00000080U
6506 #define SDIO_MASK_DATAENDIE 0x00000100U
6507 #define SDIO_MASK_STBITERRIE 0x00000200U
6508 #define SDIO_MASK_DBCKENDIE 0x00000400U
6509 #define SDIO_MASK_CMDACTIE 0x00000800U
6510 #define SDIO_MASK_TXACTIE 0x00001000U
6511 #define SDIO_MASK_RXACTIE 0x00002000U
6512 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
6513 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
6514 #define SDIO_MASK_TXFIFOFIE 0x00010000U
6515 #define SDIO_MASK_RXFIFOFIE 0x00020000U
6516 #define SDIO_MASK_TXFIFOEIE 0x00040000U
6517 #define SDIO_MASK_RXFIFOEIE 0x00080000U
6518 #define SDIO_MASK_TXDAVLIE 0x00100000U
6519 #define SDIO_MASK_RXDAVLIE 0x00200000U
6520 #define SDIO_MASK_SDIOITIE 0x00400000U
6521 #define SDIO_MASK_CEATAENDIE 0x00800000U
6523 /***************** Bit definition for SDIO_FIFOCNT register *****************/
6524 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6526 /****************** Bit definition for SDIO_FIFO register *******************/
6527 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
6529 /******************************************************************************/
6530 /* */
6531 /* Serial Peripheral Interface */
6532 /* */
6533 /******************************************************************************/
6534 /******************* Bit definition for SPI_CR1 register ********************/
6535 #define SPI_CR1_CPHA 0x00000001U
6536 #define SPI_CR1_CPOL 0x00000002U
6537 #define SPI_CR1_MSTR 0x00000004U
6539 #define SPI_CR1_BR 0x00000038U
6540 #define SPI_CR1_BR_0 0x00000008U
6541 #define SPI_CR1_BR_1 0x00000010U
6542 #define SPI_CR1_BR_2 0x00000020U
6544 #define SPI_CR1_SPE 0x00000040U
6545 #define SPI_CR1_LSBFIRST 0x00000080U
6546 #define SPI_CR1_SSI 0x00000100U
6547 #define SPI_CR1_SSM 0x00000200U
6548 #define SPI_CR1_RXONLY 0x00000400U
6549 #define SPI_CR1_DFF 0x00000800U
6550 #define SPI_CR1_CRCNEXT 0x00001000U
6551 #define SPI_CR1_CRCEN 0x00002000U
6552 #define SPI_CR1_BIDIOE 0x00004000U
6553 #define SPI_CR1_BIDIMODE 0x00008000U
6555 /******************* Bit definition for SPI_CR2 register ********************/
6556 #define SPI_CR2_RXDMAEN 0x00000001U
6557 #define SPI_CR2_TXDMAEN 0x00000002U
6558 #define SPI_CR2_SSOE 0x00000004U
6559 #define SPI_CR2_FRF 0x00000010U
6560 #define SPI_CR2_ERRIE 0x00000020U
6561 #define SPI_CR2_RXNEIE 0x00000040U
6562 #define SPI_CR2_TXEIE 0x00000080U
6564 /******************** Bit definition for SPI_SR register ********************/
6565 #define SPI_SR_RXNE 0x00000001U
6566 #define SPI_SR_TXE 0x00000002U
6567 #define SPI_SR_CHSIDE 0x00000004U
6568 #define SPI_SR_UDR 0x00000008U
6569 #define SPI_SR_CRCERR 0x00000010U
6570 #define SPI_SR_MODF 0x00000020U
6571 #define SPI_SR_OVR 0x00000040U
6572 #define SPI_SR_BSY 0x00000080U
6573 #define SPI_SR_FRE 0x00000100U
6575 /******************** Bit definition for SPI_DR register ********************/
6576 #define SPI_DR_DR 0x0000FFFFU
6578 /******************* Bit definition for SPI_CRCPR register ******************/
6579 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
6581 /****************** Bit definition for SPI_RXCRCR register ******************/
6582 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
6584 /****************** Bit definition for SPI_TXCRCR register ******************/
6585 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
6587 /****************** Bit definition for SPI_I2SCFGR register *****************/
6588 #define SPI_I2SCFGR_CHLEN 0x00000001U
6590 #define SPI_I2SCFGR_DATLEN 0x00000006U
6591 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
6592 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
6594 #define SPI_I2SCFGR_CKPOL 0x00000008U
6596 #define SPI_I2SCFGR_I2SSTD 0x00000030U
6597 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
6598 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
6600 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
6602 #define SPI_I2SCFGR_I2SCFG 0x00000300U
6603 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
6604 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
6606 #define SPI_I2SCFGR_I2SE 0x00000400U
6607 #define SPI_I2SCFGR_I2SMOD 0x00000800U
6609 /****************** Bit definition for SPI_I2SPR register *******************/
6610 #define SPI_I2SPR_I2SDIV 0x000000FFU
6611 #define SPI_I2SPR_ODD 0x00000100U
6612 #define SPI_I2SPR_MCKOE 0x00000200U
6614 /******************************************************************************/
6615 /* */
6616 /* SYSCFG */
6617 /* */
6618 /******************************************************************************/
6619 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6620 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
6621 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
6622 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
6623 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
6624 
6625 #define SYSCFG_MEMRMP_UFB_MODE 0x00000100U
6626 #define SYSCFG_SWP_FMC 0x00000C00U
6628 /****************** Bit definition for SYSCFG_PMC register ******************/
6629 #define SYSCFG_PMC_ADCxDC2 0x00070000U
6630 #define SYSCFG_PMC_ADC1DC2 0x00010000U
6631 #define SYSCFG_PMC_ADC2DC2 0x00020000U
6632 #define SYSCFG_PMC_ADC3DC2 0x00040000U
6634 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
6635 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
6636 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
6637 
6638 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6639 #define SYSCFG_EXTICR1_EXTI0 0x000FU
6640 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
6641 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
6642 #define SYSCFG_EXTICR1_EXTI3 0xF000U
6646 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
6647 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
6648 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
6649 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
6650 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
6651 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
6652 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
6653 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
6654 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
6655 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
6656 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
6661 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
6662 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
6663 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
6664 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
6665 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
6666 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
6667 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
6668 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
6669 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
6670 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
6671 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
6677 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
6678 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
6679 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
6680 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
6681 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
6682 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
6683 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
6684 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
6685 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
6686 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
6687 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
6693 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
6694 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
6695 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
6696 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
6697 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
6698 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
6699 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
6700 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
6701 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
6702 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
6703 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
6706 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6707 #define SYSCFG_EXTICR2_EXTI4 0x000FU
6708 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
6709 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
6710 #define SYSCFG_EXTICR2_EXTI7 0xF000U
6714 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
6715 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
6716 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
6717 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
6718 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
6719 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
6720 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
6721 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
6722 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
6723 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
6724 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
6729 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
6730 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
6731 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
6732 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
6733 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
6734 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
6735 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
6736 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
6737 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
6738 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
6739 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
6744 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
6745 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
6746 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
6747 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
6748 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
6749 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
6750 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
6751 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
6752 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
6753 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
6754 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
6760 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
6761 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
6762 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
6763 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
6764 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
6765 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
6766 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
6767 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
6768 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
6769 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
6770 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
6772 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6773 #define SYSCFG_EXTICR3_EXTI8 0x000FU
6774 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
6775 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
6776 #define SYSCFG_EXTICR3_EXTI11 0xF000U
6781 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
6782 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
6783 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
6784 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
6785 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
6786 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
6787 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
6788 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
6789 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
6790 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
6795 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
6796 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
6797 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
6798 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
6799 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
6800 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
6801 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
6802 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
6803 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
6804 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
6810 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
6811 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
6812 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
6813 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
6814 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
6815 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
6816 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
6817 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
6818 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
6819 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
6825 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
6826 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
6827 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
6828 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
6829 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
6830 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
6831 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
6832 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
6833 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
6834 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
6837 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6838 #define SYSCFG_EXTICR4_EXTI12 0x000FU
6839 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
6840 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
6841 #define SYSCFG_EXTICR4_EXTI15 0xF000U
6845 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
6846 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
6847 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
6848 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
6849 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
6850 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
6851 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
6852 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
6853 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
6854 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
6860 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
6861 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
6862 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
6863 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
6864 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
6865 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
6866 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
6867 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
6868 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
6869 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
6875 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
6876 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
6877 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
6878 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
6879 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
6880 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
6881 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
6882 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
6883 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
6884 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
6890 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
6891 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
6892 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
6893 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
6894 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
6895 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
6896 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
6897 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
6898 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
6899 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
6901 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6902 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
6903 #define SYSCFG_CMPCR_READY 0x00000100U
6905 /******************************************************************************/
6906 /* */
6907 /* TIM */
6908 /* */
6909 /******************************************************************************/
6910 /******************* Bit definition for TIM_CR1 register ********************/
6911 #define TIM_CR1_CEN 0x0001U
6912 #define TIM_CR1_UDIS 0x0002U
6913 #define TIM_CR1_URS 0x0004U
6914 #define TIM_CR1_OPM 0x0008U
6915 #define TIM_CR1_DIR 0x0010U
6917 #define TIM_CR1_CMS 0x0060U
6918 #define TIM_CR1_CMS_0 0x0020U
6919 #define TIM_CR1_CMS_1 0x0040U
6921 #define TIM_CR1_ARPE 0x0080U
6923 #define TIM_CR1_CKD 0x0300U
6924 #define TIM_CR1_CKD_0 0x0100U
6925 #define TIM_CR1_CKD_1 0x0200U
6927 /******************* Bit definition for TIM_CR2 register ********************/
6928 #define TIM_CR2_CCPC 0x0001U
6929 #define TIM_CR2_CCUS 0x0004U
6930 #define TIM_CR2_CCDS 0x0008U
6932 #define TIM_CR2_MMS 0x0070U
6933 #define TIM_CR2_MMS_0 0x0010U
6934 #define TIM_CR2_MMS_1 0x0020U
6935 #define TIM_CR2_MMS_2 0x0040U
6937 #define TIM_CR2_TI1S 0x0080U
6938 #define TIM_CR2_OIS1 0x0100U
6939 #define TIM_CR2_OIS1N 0x0200U
6940 #define TIM_CR2_OIS2 0x0400U
6941 #define TIM_CR2_OIS2N 0x0800U
6942 #define TIM_CR2_OIS3 0x1000U
6943 #define TIM_CR2_OIS3N 0x2000U
6944 #define TIM_CR2_OIS4 0x4000U
6946 /******************* Bit definition for TIM_SMCR register *******************/
6947 #define TIM_SMCR_SMS 0x0007U
6948 #define TIM_SMCR_SMS_0 0x0001U
6949 #define TIM_SMCR_SMS_1 0x0002U
6950 #define TIM_SMCR_SMS_2 0x0004U
6952 #define TIM_SMCR_TS 0x0070U
6953 #define TIM_SMCR_TS_0 0x0010U
6954 #define TIM_SMCR_TS_1 0x0020U
6955 #define TIM_SMCR_TS_2 0x0040U
6957 #define TIM_SMCR_MSM 0x0080U
6959 #define TIM_SMCR_ETF 0x0F00U
6960 #define TIM_SMCR_ETF_0 0x0100U
6961 #define TIM_SMCR_ETF_1 0x0200U
6962 #define TIM_SMCR_ETF_2 0x0400U
6963 #define TIM_SMCR_ETF_3 0x0800U
6965 #define TIM_SMCR_ETPS 0x3000U
6966 #define TIM_SMCR_ETPS_0 0x1000U
6967 #define TIM_SMCR_ETPS_1 0x2000U
6969 #define TIM_SMCR_ECE 0x4000U
6970 #define TIM_SMCR_ETP 0x8000U
6972 /******************* Bit definition for TIM_DIER register *******************/
6973 #define TIM_DIER_UIE 0x0001U
6974 #define TIM_DIER_CC1IE 0x0002U
6975 #define TIM_DIER_CC2IE 0x0004U
6976 #define TIM_DIER_CC3IE 0x0008U
6977 #define TIM_DIER_CC4IE 0x0010U
6978 #define TIM_DIER_COMIE 0x0020U
6979 #define TIM_DIER_TIE 0x0040U
6980 #define TIM_DIER_BIE 0x0080U
6981 #define TIM_DIER_UDE 0x0100U
6982 #define TIM_DIER_CC1DE 0x0200U
6983 #define TIM_DIER_CC2DE 0x0400U
6984 #define TIM_DIER_CC3DE 0x0800U
6985 #define TIM_DIER_CC4DE 0x1000U
6986 #define TIM_DIER_COMDE 0x2000U
6987 #define TIM_DIER_TDE 0x4000U
6989 /******************** Bit definition for TIM_SR register ********************/
6990 #define TIM_SR_UIF 0x0001U
6991 #define TIM_SR_CC1IF 0x0002U
6992 #define TIM_SR_CC2IF 0x0004U
6993 #define TIM_SR_CC3IF 0x0008U
6994 #define TIM_SR_CC4IF 0x0010U
6995 #define TIM_SR_COMIF 0x0020U
6996 #define TIM_SR_TIF 0x0040U
6997 #define TIM_SR_BIF 0x0080U
6998 #define TIM_SR_CC1OF 0x0200U
6999 #define TIM_SR_CC2OF 0x0400U
7000 #define TIM_SR_CC3OF 0x0800U
7001 #define TIM_SR_CC4OF 0x1000U
7003 /******************* Bit definition for TIM_EGR register ********************/
7004 #define TIM_EGR_UG 0x01U
7005 #define TIM_EGR_CC1G 0x02U
7006 #define TIM_EGR_CC2G 0x04U
7007 #define TIM_EGR_CC3G 0x08U
7008 #define TIM_EGR_CC4G 0x10U
7009 #define TIM_EGR_COMG 0x20U
7010 #define TIM_EGR_TG 0x40U
7011 #define TIM_EGR_BG 0x80U
7013 /****************** Bit definition for TIM_CCMR1 register *******************/
7014 #define TIM_CCMR1_CC1S 0x0003U
7015 #define TIM_CCMR1_CC1S_0 0x0001U
7016 #define TIM_CCMR1_CC1S_1 0x0002U
7018 #define TIM_CCMR1_OC1FE 0x0004U
7019 #define TIM_CCMR1_OC1PE 0x0008U
7021 #define TIM_CCMR1_OC1M 0x0070U
7022 #define TIM_CCMR1_OC1M_0 0x0010U
7023 #define TIM_CCMR1_OC1M_1 0x0020U
7024 #define TIM_CCMR1_OC1M_2 0x0040U
7026 #define TIM_CCMR1_OC1CE 0x0080U
7028 #define TIM_CCMR1_CC2S 0x0300U
7029 #define TIM_CCMR1_CC2S_0 0x0100U
7030 #define TIM_CCMR1_CC2S_1 0x0200U
7032 #define TIM_CCMR1_OC2FE 0x0400U
7033 #define TIM_CCMR1_OC2PE 0x0800U
7035 #define TIM_CCMR1_OC2M 0x7000U
7036 #define TIM_CCMR1_OC2M_0 0x1000U
7037 #define TIM_CCMR1_OC2M_1 0x2000U
7038 #define TIM_CCMR1_OC2M_2 0x4000U
7040 #define TIM_CCMR1_OC2CE 0x8000U
7042 /*----------------------------------------------------------------------------*/
7043 
7044 #define TIM_CCMR1_IC1PSC 0x000CU
7045 #define TIM_CCMR1_IC1PSC_0 0x0004U
7046 #define TIM_CCMR1_IC1PSC_1 0x0008U
7048 #define TIM_CCMR1_IC1F 0x00F0U
7049 #define TIM_CCMR1_IC1F_0 0x0010U
7050 #define TIM_CCMR1_IC1F_1 0x0020U
7051 #define TIM_CCMR1_IC1F_2 0x0040U
7052 #define TIM_CCMR1_IC1F_3 0x0080U
7054 #define TIM_CCMR1_IC2PSC 0x0C00U
7055 #define TIM_CCMR1_IC2PSC_0 0x0400U
7056 #define TIM_CCMR1_IC2PSC_1 0x0800U
7058 #define TIM_CCMR1_IC2F 0xF000U
7059 #define TIM_CCMR1_IC2F_0 0x1000U
7060 #define TIM_CCMR1_IC2F_1 0x2000U
7061 #define TIM_CCMR1_IC2F_2 0x4000U
7062 #define TIM_CCMR1_IC2F_3 0x8000U
7064 /****************** Bit definition for TIM_CCMR2 register *******************/
7065 #define TIM_CCMR2_CC3S 0x0003U
7066 #define TIM_CCMR2_CC3S_0 0x0001U
7067 #define TIM_CCMR2_CC3S_1 0x0002U
7069 #define TIM_CCMR2_OC3FE 0x0004U
7070 #define TIM_CCMR2_OC3PE 0x0008U
7072 #define TIM_CCMR2_OC3M 0x0070U
7073 #define TIM_CCMR2_OC3M_0 0x0010U
7074 #define TIM_CCMR2_OC3M_1 0x0020U
7075 #define TIM_CCMR2_OC3M_2 0x0040U
7077 #define TIM_CCMR2_OC3CE 0x0080U
7079 #define TIM_CCMR2_CC4S 0x0300U
7080 #define TIM_CCMR2_CC4S_0 0x0100U
7081 #define TIM_CCMR2_CC4S_1 0x0200U
7083 #define TIM_CCMR2_OC4FE 0x0400U
7084 #define TIM_CCMR2_OC4PE 0x0800U
7086 #define TIM_CCMR2_OC4M 0x7000U
7087 #define TIM_CCMR2_OC4M_0 0x1000U
7088 #define TIM_CCMR2_OC4M_1 0x2000U
7089 #define TIM_CCMR2_OC4M_2 0x4000U
7091 #define TIM_CCMR2_OC4CE 0x8000U
7093 /*----------------------------------------------------------------------------*/
7094 
7095 #define TIM_CCMR2_IC3PSC 0x000CU
7096 #define TIM_CCMR2_IC3PSC_0 0x0004U
7097 #define TIM_CCMR2_IC3PSC_1 0x0008U
7099 #define TIM_CCMR2_IC3F 0x00F0U
7100 #define TIM_CCMR2_IC3F_0 0x0010U
7101 #define TIM_CCMR2_IC3F_1 0x0020U
7102 #define TIM_CCMR2_IC3F_2 0x0040U
7103 #define TIM_CCMR2_IC3F_3 0x0080U
7105 #define TIM_CCMR2_IC4PSC 0x0C00U
7106 #define TIM_CCMR2_IC4PSC_0 0x0400U
7107 #define TIM_CCMR2_IC4PSC_1 0x0800U
7109 #define TIM_CCMR2_IC4F 0xF000U
7110 #define TIM_CCMR2_IC4F_0 0x1000U
7111 #define TIM_CCMR2_IC4F_1 0x2000U
7112 #define TIM_CCMR2_IC4F_2 0x4000U
7113 #define TIM_CCMR2_IC4F_3 0x8000U
7115 /******************* Bit definition for TIM_CCER register *******************/
7116 #define TIM_CCER_CC1E 0x0001U
7117 #define TIM_CCER_CC1P 0x0002U
7118 #define TIM_CCER_CC1NE 0x0004U
7119 #define TIM_CCER_CC1NP 0x0008U
7120 #define TIM_CCER_CC2E 0x0010U
7121 #define TIM_CCER_CC2P 0x0020U
7122 #define TIM_CCER_CC2NE 0x0040U
7123 #define TIM_CCER_CC2NP 0x0080U
7124 #define TIM_CCER_CC3E 0x0100U
7125 #define TIM_CCER_CC3P 0x0200U
7126 #define TIM_CCER_CC3NE 0x0400U
7127 #define TIM_CCER_CC3NP 0x0800U
7128 #define TIM_CCER_CC4E 0x1000U
7129 #define TIM_CCER_CC4P 0x2000U
7130 #define TIM_CCER_CC4NP 0x8000U
7132 /******************* Bit definition for TIM_CNT register ********************/
7133 #define TIM_CNT_CNT 0xFFFFU
7135 /******************* Bit definition for TIM_PSC register ********************/
7136 #define TIM_PSC_PSC 0xFFFFU
7138 /******************* Bit definition for TIM_ARR register ********************/
7139 #define TIM_ARR_ARR 0xFFFFU
7141 /******************* Bit definition for TIM_RCR register ********************/
7142 #define TIM_RCR_REP 0xFFU
7144 /******************* Bit definition for TIM_CCR1 register *******************/
7145 #define TIM_CCR1_CCR1 0xFFFFU
7147 /******************* Bit definition for TIM_CCR2 register *******************/
7148 #define TIM_CCR2_CCR2 0xFFFFU
7150 /******************* Bit definition for TIM_CCR3 register *******************/
7151 #define TIM_CCR3_CCR3 0xFFFFU
7153 /******************* Bit definition for TIM_CCR4 register *******************/
7154 #define TIM_CCR4_CCR4 0xFFFFU
7156 /******************* Bit definition for TIM_BDTR register *******************/
7157 #define TIM_BDTR_DTG 0x00FFU
7158 #define TIM_BDTR_DTG_0 0x0001U
7159 #define TIM_BDTR_DTG_1 0x0002U
7160 #define TIM_BDTR_DTG_2 0x0004U
7161 #define TIM_BDTR_DTG_3 0x0008U
7162 #define TIM_BDTR_DTG_4 0x0010U
7163 #define TIM_BDTR_DTG_5 0x0020U
7164 #define TIM_BDTR_DTG_6 0x0040U
7165 #define TIM_BDTR_DTG_7 0x0080U
7167 #define TIM_BDTR_LOCK 0x0300U
7168 #define TIM_BDTR_LOCK_0 0x0100U
7169 #define TIM_BDTR_LOCK_1 0x0200U
7171 #define TIM_BDTR_OSSI 0x0400U
7172 #define TIM_BDTR_OSSR 0x0800U
7173 #define TIM_BDTR_BKE 0x1000U
7174 #define TIM_BDTR_BKP 0x2000U
7175 #define TIM_BDTR_AOE 0x4000U
7176 #define TIM_BDTR_MOE 0x8000U
7178 /******************* Bit definition for TIM_DCR register ********************/
7179 #define TIM_DCR_DBA 0x001FU
7180 #define TIM_DCR_DBA_0 0x0001U
7181 #define TIM_DCR_DBA_1 0x0002U
7182 #define TIM_DCR_DBA_2 0x0004U
7183 #define TIM_DCR_DBA_3 0x0008U
7184 #define TIM_DCR_DBA_4 0x0010U
7186 #define TIM_DCR_DBL 0x1F00U
7187 #define TIM_DCR_DBL_0 0x0100U
7188 #define TIM_DCR_DBL_1 0x0200U
7189 #define TIM_DCR_DBL_2 0x0400U
7190 #define TIM_DCR_DBL_3 0x0800U
7191 #define TIM_DCR_DBL_4 0x1000U
7193 /******************* Bit definition for TIM_DMAR register *******************/
7194 #define TIM_DMAR_DMAB 0xFFFFU
7196 /******************* Bit definition for TIM_OR register *********************/
7197 #define TIM_OR_TI4_RMP 0x00C0U
7198 #define TIM_OR_TI4_RMP_0 0x0040U
7199 #define TIM_OR_TI4_RMP_1 0x0080U
7200 #define TIM_OR_ITR1_RMP 0x0C00U
7201 #define TIM_OR_ITR1_RMP_0 0x0400U
7202 #define TIM_OR_ITR1_RMP_1 0x0800U
7205 /******************************************************************************/
7206 /* */
7207 /* Universal Synchronous Asynchronous Receiver Transmitter */
7208 /* */
7209 /******************************************************************************/
7210 /******************* Bit definition for USART_SR register *******************/
7211 #define USART_SR_PE 0x0001U
7212 #define USART_SR_FE 0x0002U
7213 #define USART_SR_NE 0x0004U
7214 #define USART_SR_ORE 0x0008U
7215 #define USART_SR_IDLE 0x0010U
7216 #define USART_SR_RXNE 0x0020U
7217 #define USART_SR_TC 0x0040U
7218 #define USART_SR_TXE 0x0080U
7219 #define USART_SR_LBD 0x0100U
7220 #define USART_SR_CTS 0x0200U
7222 /******************* Bit definition for USART_DR register *******************/
7223 #define USART_DR_DR 0x01FFU
7225 /****************** Bit definition for USART_BRR register *******************/
7226 #define USART_BRR_DIV_Fraction 0x000FU
7227 #define USART_BRR_DIV_Mantissa 0xFFF0U
7229 /****************** Bit definition for USART_CR1 register *******************/
7230 #define USART_CR1_SBK 0x0001U
7231 #define USART_CR1_RWU 0x0002U
7232 #define USART_CR1_RE 0x0004U
7233 #define USART_CR1_TE 0x0008U
7234 #define USART_CR1_IDLEIE 0x0010U
7235 #define USART_CR1_RXNEIE 0x0020U
7236 #define USART_CR1_TCIE 0x0040U
7237 #define USART_CR1_TXEIE 0x0080U
7238 #define USART_CR1_PEIE 0x0100U
7239 #define USART_CR1_PS 0x0200U
7240 #define USART_CR1_PCE 0x0400U
7241 #define USART_CR1_WAKE 0x0800U
7242 #define USART_CR1_M 0x1000U
7243 #define USART_CR1_UE 0x2000U
7244 #define USART_CR1_OVER8 0x8000U
7246 /****************** Bit definition for USART_CR2 register *******************/
7247 #define USART_CR2_ADD 0x000FU
7248 #define USART_CR2_LBDL 0x0020U
7249 #define USART_CR2_LBDIE 0x0040U
7250 #define USART_CR2_LBCL 0x0100U
7251 #define USART_CR2_CPHA 0x0200U
7252 #define USART_CR2_CPOL 0x0400U
7253 #define USART_CR2_CLKEN 0x0800U
7255 #define USART_CR2_STOP 0x3000U
7256 #define USART_CR2_STOP_0 0x1000U
7257 #define USART_CR2_STOP_1 0x2000U
7259 #define USART_CR2_LINEN 0x4000U
7261 /****************** Bit definition for USART_CR3 register *******************/
7262 #define USART_CR3_EIE 0x0001U
7263 #define USART_CR3_IREN 0x0002U
7264 #define USART_CR3_IRLP 0x0004U
7265 #define USART_CR3_HDSEL 0x0008U
7266 #define USART_CR3_NACK 0x0010U
7267 #define USART_CR3_SCEN 0x0020U
7268 #define USART_CR3_DMAR 0x0040U
7269 #define USART_CR3_DMAT 0x0080U
7270 #define USART_CR3_RTSE 0x0100U
7271 #define USART_CR3_CTSE 0x0200U
7272 #define USART_CR3_CTSIE 0x0400U
7273 #define USART_CR3_ONEBIT 0x0800U
7275 /****************** Bit definition for USART_GTPR register ******************/
7276 #define USART_GTPR_PSC 0x00FFU
7277 #define USART_GTPR_PSC_0 0x0001U
7278 #define USART_GTPR_PSC_1 0x0002U
7279 #define USART_GTPR_PSC_2 0x0004U
7280 #define USART_GTPR_PSC_3 0x0008U
7281 #define USART_GTPR_PSC_4 0x0010U
7282 #define USART_GTPR_PSC_5 0x0020U
7283 #define USART_GTPR_PSC_6 0x0040U
7284 #define USART_GTPR_PSC_7 0x0080U
7286 #define USART_GTPR_GT 0xFF00U
7288 /******************************************************************************/
7289 /* */
7290 /* Window WATCHDOG */
7291 /* */
7292 /******************************************************************************/
7293 /******************* Bit definition for WWDG_CR register ********************/
7294 #define WWDG_CR_T 0x7FU
7295 #define WWDG_CR_T_0 0x01U
7296 #define WWDG_CR_T_1 0x02U
7297 #define WWDG_CR_T_2 0x04U
7298 #define WWDG_CR_T_3 0x08U
7299 #define WWDG_CR_T_4 0x10U
7300 #define WWDG_CR_T_5 0x20U
7301 #define WWDG_CR_T_6 0x40U
7302 /* Legacy defines */
7303 #define WWDG_CR_T0 WWDG_CR_T_0
7304 #define WWDG_CR_T1 WWDG_CR_T_1
7305 #define WWDG_CR_T2 WWDG_CR_T_2
7306 #define WWDG_CR_T3 WWDG_CR_T_3
7307 #define WWDG_CR_T4 WWDG_CR_T_4
7308 #define WWDG_CR_T5 WWDG_CR_T_5
7309 #define WWDG_CR_T6 WWDG_CR_T_6
7310 
7311 #define WWDG_CR_WDGA 0x80U
7313 /******************* Bit definition for WWDG_CFR register *******************/
7314 #define WWDG_CFR_W 0x007FU
7315 #define WWDG_CFR_W_0 0x0001U
7316 #define WWDG_CFR_W_1 0x0002U
7317 #define WWDG_CFR_W_2 0x0004U
7318 #define WWDG_CFR_W_3 0x0008U
7319 #define WWDG_CFR_W_4 0x0010U
7320 #define WWDG_CFR_W_5 0x0020U
7321 #define WWDG_CFR_W_6 0x0040U
7322 /* Legacy defines */
7323 #define WWDG_CFR_W0 WWDG_CFR_W_0
7324 #define WWDG_CFR_W1 WWDG_CFR_W_1
7325 #define WWDG_CFR_W2 WWDG_CFR_W_2
7326 #define WWDG_CFR_W3 WWDG_CFR_W_3
7327 #define WWDG_CFR_W4 WWDG_CFR_W_4
7328 #define WWDG_CFR_W5 WWDG_CFR_W_5
7329 #define WWDG_CFR_W6 WWDG_CFR_W_6
7330 
7331 #define WWDG_CFR_WDGTB 0x0180U
7332 #define WWDG_CFR_WDGTB_0 0x0080U
7333 #define WWDG_CFR_WDGTB_1 0x0100U
7334 /* Legacy defines */
7335 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
7336 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
7337 
7338 #define WWDG_CFR_EWI 0x0200U
7340 /******************* Bit definition for WWDG_SR register ********************/
7341 #define WWDG_SR_EWIF 0x01U
7344 /******************************************************************************/
7345 /* */
7346 /* DBG */
7347 /* */
7348 /******************************************************************************/
7349 /******************** Bit definition for DBGMCU_IDCODE register *************/
7350 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
7351 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
7352 
7353 /******************** Bit definition for DBGMCU_CR register *****************/
7354 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
7355 #define DBGMCU_CR_DBG_STOP 0x00000002U
7356 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
7357 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
7358 
7359 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
7360 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
7361 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
7363 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
7364 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
7365 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
7366 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
7367 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
7368 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
7369 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
7370 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
7371 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
7372 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
7373 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
7374 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
7375 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
7376 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
7377 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
7378 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
7379 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
7380 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
7381 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
7382 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
7383 
7384 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
7385 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
7386 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
7387 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
7388 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
7389 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
7390 
7391 /******************************************************************************/
7392 /* */
7393 /* Ethernet MAC Registers bits definitions */
7394 /* */
7395 /******************************************************************************/
7396 /* Bit definition for Ethernet MAC Control Register register */
7397 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
7398 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
7399 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
7400 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
7401  #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
7402  #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
7403  #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
7404  #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
7405  #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
7406  #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
7407  #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
7408 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
7409 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
7410 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
7411 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
7412 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
7413 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
7414 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
7415 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
7416 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7417  a transmission attempt during retries after a collision: 0 =< r <2^k */
7418  #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
7419  #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
7420  #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
7421  #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
7422 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
7423 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
7424 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
7425 
7426 /* Bit definition for Ethernet MAC Frame Filter Register */
7427 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
7428 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
7429 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
7430 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
7431 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
7432  #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
7433  #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
7434  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
7435 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
7436 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
7437 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
7438 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
7439 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
7440 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
7441 
7442 /* Bit definition for Ethernet MAC Hash Table High Register */
7443 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
7444 
7445 /* Bit definition for Ethernet MAC Hash Table Low Register */
7446 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
7447 
7448 /* Bit definition for Ethernet MAC MII Address Register */
7449 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
7450 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
7451 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
7452  #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
7453  #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
7454  #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7455  #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7456  #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
7457 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
7458 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
7459 
7460 /* Bit definition for Ethernet MAC MII Data Register */
7461 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
7462 
7463 /* Bit definition for Ethernet MAC Flow Control Register */
7464 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
7465 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
7466 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
7467  #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
7468  #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
7469  #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
7470  #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
7471 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
7472 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
7473 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
7474 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
7475 
7476 /* Bit definition for Ethernet MAC VLAN Tag Register */
7477 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
7478 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
7479 
7480 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7481 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
7482 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7483  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7484 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7485  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7486  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7487  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7488  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7489  RSVD - Filter1 Command - RSVD - Filter0 Command
7490  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7491  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7492  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7493 
7494 /* Bit definition for Ethernet MAC PMT Control and Status Register */
7495 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
7496 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
7497 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
7498 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
7499 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
7500 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
7501 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
7502 
7503 /* Bit definition for Ethernet MAC Status Register */
7504 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
7505 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
7506 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
7507 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
7508 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
7509 
7510 /* Bit definition for Ethernet MAC Interrupt Mask Register */
7511 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
7512 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
7513 
7514 /* Bit definition for Ethernet MAC Address0 High Register */
7515 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
7516 
7517 /* Bit definition for Ethernet MAC Address0 Low Register */
7518 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
7519 
7520 /* Bit definition for Ethernet MAC Address1 High Register */
7521 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
7522 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
7523 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7524  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7525  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7526  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7527  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7528  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7529  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
7530 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
7531 
7532 /* Bit definition for Ethernet MAC Address1 Low Register */
7533 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
7534 
7535 /* Bit definition for Ethernet MAC Address2 High Register */
7536 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
7537 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
7538 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
7539  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7540  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7541  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7542  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7543  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7544  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7545 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
7546 
7547 /* Bit definition for Ethernet MAC Address2 Low Register */
7548 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
7549 
7550 /* Bit definition for Ethernet MAC Address3 High Register */
7551 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
7552 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
7553 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
7554  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7555  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7556  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7557  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7558  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7559  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7560 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
7561 
7562 /* Bit definition for Ethernet MAC Address3 Low Register */
7563 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
7564 
7565 /******************************************************************************/
7566 /* Ethernet MMC Registers bits definition */
7567 /******************************************************************************/
7568 
7569 /* Bit definition for Ethernet MMC Contol Register */
7570 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
7571 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
7572 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
7573 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
7574 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
7575 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
7576 
7577 /* Bit definition for Ethernet MMC Receive Interrupt Register */
7578 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
7579 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
7580 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
7581 
7582 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
7583 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
7584 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
7585 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
7586 
7587 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
7588 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
7589 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
7590 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
7591 
7592 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
7593 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
7594 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
7595 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
7596 
7597 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
7598 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
7599 
7600 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
7601 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
7602 
7603 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
7604 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
7605 
7606 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
7607 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
7608 
7609 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
7610 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
7611 
7612 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
7613 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
7614 
7615 /******************************************************************************/
7616 /* Ethernet PTP Registers bits definition */
7617 /******************************************************************************/
7618 
7619 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
7620 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
7621 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
7622 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
7623 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
7624 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
7625 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
7626 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
7627 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
7628 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
7629 
7630 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
7631 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
7632 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
7633 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
7634 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
7635 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
7636 
7637 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
7638 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
7639 
7640 /* Bit definition for Ethernet PTP Time Stamp High Register */
7641 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
7642 
7643 /* Bit definition for Ethernet PTP Time Stamp Low Register */
7644 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
7645 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
7646 
7647 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
7648 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
7649 
7650 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7651 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
7652 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
7653 
7654 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
7655 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
7656 
7657 /* Bit definition for Ethernet PTP Target Time High Register */
7658 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
7659 
7660 /* Bit definition for Ethernet PTP Target Time Low Register */
7661 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
7662 
7663 /* Bit definition for Ethernet PTP Time Stamp Status Register */
7664 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
7665 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
7666 
7667 /******************************************************************************/
7668 /* Ethernet DMA Registers bits definition */
7669 /******************************************************************************/
7670 
7671 /* Bit definition for Ethernet DMA Bus Mode Register */
7672 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
7673 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
7674 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
7675 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
7676  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7677  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7678  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7679  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7680  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7681  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7682  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7683  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7684  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7685  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7686  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7687  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7688 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
7689 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
7690  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
7691  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
7692  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
7693  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
7694 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
7695  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7696  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7697  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7698  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7699  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7700  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7701  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7702  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7703  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7704  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7705  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7706  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7707 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
7708 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
7709 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
7710 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
7711 
7712 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7713 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
7714 
7715 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
7716 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
7717 
7718 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7719 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
7720 
7721 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7722 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
7723 
7724 /* Bit definition for Ethernet DMA Status Register */
7725 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
7726 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
7727 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
7728 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
7729  /* combination with EBS[2:0] for GetFlagStatus function */
7730  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
7731  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
7732  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
7733 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
7734  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
7735  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
7736  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
7737  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
7738  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
7739  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
7740 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
7741  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
7742  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
7743  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
7744  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
7745  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
7746  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
7747 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
7748 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
7749 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
7750 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
7751 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
7752 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
7753 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
7754 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
7755 #define ETH_DMASR_RS 0x00000040U /* Receive status */
7756 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
7757 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
7758 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
7759 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
7760 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
7761 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
7762 
7763 /* Bit definition for Ethernet DMA Operation Mode Register */
7764 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
7765 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
7766 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
7767 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
7768 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
7769 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
7770  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7771  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7772  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7773  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7774  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7775  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7776  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7777  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7778 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
7779 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
7780 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
7781 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
7782  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
7783  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
7784  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
7785  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
7786 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
7787 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
7788 
7789 /* Bit definition for Ethernet DMA Interrupt Enable Register */
7790 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
7791 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
7792 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
7793 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
7794 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
7795 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
7796 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
7797 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
7798 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
7799 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
7800 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
7801 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
7802 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
7803 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
7804 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
7805 
7806 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
7807 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
7808 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
7809 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
7810 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
7811 
7812 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
7813 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
7814 
7815 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
7816 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
7817 
7818 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
7819 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
7820 
7821 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
7822 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
7823 
7824 /******************************************************************************/
7825 /* */
7826 /* USB_OTG */
7827 /* */
7828 /******************************************************************************/
7829 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
7830 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
7831 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
7832 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
7833 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
7834 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
7835 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
7836 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
7837 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
7838 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
7839 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
7841 /******************** Bit definition forUSB_OTG_HCFG register ********************/
7842 
7843 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
7844 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
7845 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
7846 #define USB_OTG_HCFG_FSLSS 0x00000004U
7848 /******************** Bit definition forUSB_OTG_DCFG register ********************/
7849 
7850 #define USB_OTG_DCFG_DSPD 0x00000003U
7851 #define USB_OTG_DCFG_DSPD_0 0x00000001U
7852 #define USB_OTG_DCFG_DSPD_1 0x00000002U
7853 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
7855 #define USB_OTG_DCFG_DAD 0x000007F0U
7856 #define USB_OTG_DCFG_DAD_0 0x00000010U
7857 #define USB_OTG_DCFG_DAD_1 0x00000020U
7858 #define USB_OTG_DCFG_DAD_2 0x00000040U
7859 #define USB_OTG_DCFG_DAD_3 0x00000080U
7860 #define USB_OTG_DCFG_DAD_4 0x00000100U
7861 #define USB_OTG_DCFG_DAD_5 0x00000200U
7862 #define USB_OTG_DCFG_DAD_6 0x00000400U
7864 #define USB_OTG_DCFG_PFIVL 0x00001800U
7865 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
7866 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
7868 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
7869 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
7870 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
7872 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
7873 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
7874 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
7875 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
7877 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
7878 #define USB_OTG_GOTGINT_SEDET 0x00000004U
7879 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
7880 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
7881 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
7882 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
7883 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
7885 /******************** Bit definition forUSB_OTG_DCTL register ********************/
7886 #define USB_OTG_DCTL_RWUSIG 0x00000001U
7887 #define USB_OTG_DCTL_SDIS 0x00000002U
7888 #define USB_OTG_DCTL_GINSTS 0x00000004U
7889 #define USB_OTG_DCTL_GONSTS 0x00000008U
7891 #define USB_OTG_DCTL_TCTL 0x00000070U
7892 #define USB_OTG_DCTL_TCTL_0 0x00000010U
7893 #define USB_OTG_DCTL_TCTL_1 0x00000020U
7894 #define USB_OTG_DCTL_TCTL_2 0x00000040U
7895 #define USB_OTG_DCTL_SGINAK 0x00000080U
7896 #define USB_OTG_DCTL_CGINAK 0x00000100U
7897 #define USB_OTG_DCTL_SGONAK 0x00000200U
7898 #define USB_OTG_DCTL_CGONAK 0x00000400U
7899 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
7901 /******************** Bit definition forUSB_OTG_HFIR register ********************/
7902 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
7904 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
7905 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
7906 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
7908 /******************** Bit definition forUSB_OTG_DSTS register ********************/
7909 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
7911 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
7912 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
7913 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
7914 #define USB_OTG_DSTS_EERR 0x00000008U
7915 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
7917 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
7918 #define USB_OTG_GAHBCFG_GINT 0x00000001U
7920 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
7921 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
7922 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
7923 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
7924 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
7925 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
7926 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
7927 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
7929 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
7930 
7931 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
7932 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
7933 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
7934 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
7935 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
7936 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
7937 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
7939 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
7940 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
7941 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
7942 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
7943 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
7944 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
7945 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
7946 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
7947 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
7948 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
7949 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
7950 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
7951 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
7952 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
7953 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
7954 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
7955 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
7956 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
7958 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
7959 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
7960 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
7961 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
7962 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
7963 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
7965 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
7966 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
7967 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
7968 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
7969 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
7970 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
7971 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
7972 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
7974 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
7975 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
7976 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
7977 #define USB_OTG_DIEPMSK_TOM 0x00000008U
7978 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
7979 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
7980 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
7981 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
7982 #define USB_OTG_DIEPMSK_BIM 0x00000200U
7984 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
7985 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
7987 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
7988 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
7989 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
7990 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
7991 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
7992 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
7993 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
7994 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
7995 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
7997 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
7998 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
7999 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
8000 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
8001 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
8002 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
8003 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
8004 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
8005 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
8007 /******************** Bit definition forUSB_OTG_HAINT register ********************/
8008 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
8010 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
8011 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
8012 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
8013 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
8014 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
8015 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
8016 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
8017 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
8019 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
8020 #define USB_OTG_GINTSTS_CMOD 0x00000001U
8021 #define USB_OTG_GINTSTS_MMIS 0x00000002U
8022 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
8023 #define USB_OTG_GINTSTS_SOF 0x00000008U
8024 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
8025 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
8026 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
8027 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
8028 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
8029 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
8030 #define USB_OTG_GINTSTS_USBRST 0x00001000U
8031 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
8032 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
8033 #define USB_OTG_GINTSTS_EOPF 0x00008000U
8034 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
8035 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
8036 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
8037 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
8038 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
8039 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
8040 #define USB_OTG_GINTSTS_HCINT 0x02000000U
8041 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
8042 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
8043 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
8044 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
8045 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
8047 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
8048 #define USB_OTG_GINTMSK_MMISM 0x00000002U
8049 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
8050 #define USB_OTG_GINTMSK_SOFM 0x00000008U
8051 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
8052 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
8053 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
8054 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
8055 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
8056 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
8057 #define USB_OTG_GINTMSK_USBRST 0x00001000U
8058 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
8059 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
8060 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
8061 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
8062 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
8063 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
8064 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
8065 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
8066 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
8067 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
8068 #define USB_OTG_GINTMSK_HCIM 0x02000000U
8069 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
8070 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
8071 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
8072 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
8073 #define USB_OTG_GINTMSK_WUIM 0x80000000U
8075 /******************** Bit definition forUSB_OTG_DAINT register ********************/
8076 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
8077 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
8079 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
8080 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
8082 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8083 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
8084 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
8085 #define USB_OTG_GRXSTSP_DPID 0x00018000U
8086 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
8088 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
8089 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
8090 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
8092 /******************** Bit definition for OTG register ********************/
8093 
8094 #define USB_OTG_CHNUM 0x0000000FU
8095 #define USB_OTG_CHNUM_0 0x00000001U
8096 #define USB_OTG_CHNUM_1 0x00000002U
8097 #define USB_OTG_CHNUM_2 0x00000004U
8098 #define USB_OTG_CHNUM_3 0x00000008U
8099 #define USB_OTG_BCNT 0x00007FF0U
8101 #define USB_OTG_DPID 0x00018000U
8102 #define USB_OTG_DPID_0 0x00008000U
8103 #define USB_OTG_DPID_1 0x00010000U
8105 #define USB_OTG_PKTSTS 0x001E0000U
8106 #define USB_OTG_PKTSTS_0 0x00020000U
8107 #define USB_OTG_PKTSTS_1 0x00040000U
8108 #define USB_OTG_PKTSTS_2 0x00080000U
8109 #define USB_OTG_PKTSTS_3 0x00100000U
8111 #define USB_OTG_EPNUM 0x0000000FU
8112 #define USB_OTG_EPNUM_0 0x00000001U
8113 #define USB_OTG_EPNUM_1 0x00000002U
8114 #define USB_OTG_EPNUM_2 0x00000004U
8115 #define USB_OTG_EPNUM_3 0x00000008U
8117 #define USB_OTG_FRMNUM 0x01E00000U
8118 #define USB_OTG_FRMNUM_0 0x00200000U
8119 #define USB_OTG_FRMNUM_1 0x00400000U
8120 #define USB_OTG_FRMNUM_2 0x00800000U
8121 #define USB_OTG_FRMNUM_3 0x01000000U
8123 /******************** Bit definition for OTG register ********************/
8124 
8125 #define USB_OTG_CHNUM 0x0000000FU
8126 #define USB_OTG_CHNUM_0 0x00000001U
8127 #define USB_OTG_CHNUM_1 0x00000002U
8128 #define USB_OTG_CHNUM_2 0x00000004U
8129 #define USB_OTG_CHNUM_3 0x00000008U
8130 #define USB_OTG_BCNT 0x00007FF0U
8132 #define USB_OTG_DPID 0x00018000U
8133 #define USB_OTG_DPID_0 0x00008000U
8134 #define USB_OTG_DPID_1 0x00010000U
8136 #define USB_OTG_PKTSTS 0x001E0000U
8137 #define USB_OTG_PKTSTS_0 0x00020000U
8138 #define USB_OTG_PKTSTS_1 0x00040000U
8139 #define USB_OTG_PKTSTS_2 0x00080000U
8140 #define USB_OTG_PKTSTS_3 0x00100000U
8142 #define USB_OTG_EPNUM 0x0000000FU
8143 #define USB_OTG_EPNUM_0 0x00000001U
8144 #define USB_OTG_EPNUM_1 0x00000002U
8145 #define USB_OTG_EPNUM_2 0x00000004U
8146 #define USB_OTG_EPNUM_3 0x00000008U
8148 #define USB_OTG_FRMNUM 0x01E00000U
8149 #define USB_OTG_FRMNUM_0 0x00200000U
8150 #define USB_OTG_FRMNUM_1 0x00400000U
8151 #define USB_OTG_FRMNUM_2 0x00800000U
8152 #define USB_OTG_FRMNUM_3 0x01000000U
8154 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
8155 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
8157 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
8158 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
8160 /******************** Bit definition for OTG register ********************/
8161 #define USB_OTG_NPTXFSA 0x0000FFFFU
8162 #define USB_OTG_NPTXFD 0xFFFF0000U
8163 #define USB_OTG_TX0FSA 0x0000FFFFU
8164 #define USB_OTG_TX0FD 0xFFFF0000U
8166 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
8167 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
8169 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
8170 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
8172 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
8173 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
8174 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
8175 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
8176 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
8177 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
8178 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
8179 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
8180 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
8182 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
8183 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
8184 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
8185 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
8186 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
8187 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
8188 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
8189 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
8191 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
8192 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
8193 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
8195 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
8196 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
8197 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
8198 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
8199 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
8200 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
8201 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
8202 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
8203 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
8204 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
8205 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
8207 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
8208 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
8209 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
8210 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
8211 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
8212 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
8213 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
8214 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
8215 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
8216 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
8217 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
8219 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
8220 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
8222 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
8223 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
8224 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
8226 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
8227 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
8228 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
8229 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
8230 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
8231 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
8232 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
8234 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
8235 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
8236 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
8238 /******************** Bit definition forUSB_OTG_CID register ********************/
8239 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
8241 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
8242 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
8243 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
8244 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
8245 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
8246 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
8247 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
8248 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
8249 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
8250 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
8252 /******************** Bit definition forUSB_OTG_HPRT register ********************/
8253 #define USB_OTG_HPRT_PCSTS 0x00000001U
8254 #define USB_OTG_HPRT_PCDET 0x00000002U
8255 #define USB_OTG_HPRT_PENA 0x00000004U
8256 #define USB_OTG_HPRT_PENCHNG 0x00000008U
8257 #define USB_OTG_HPRT_POCA 0x00000010U
8258 #define USB_OTG_HPRT_POCCHNG 0x00000020U
8259 #define USB_OTG_HPRT_PRES 0x00000040U
8260 #define USB_OTG_HPRT_PSUSP 0x00000080U
8261 #define USB_OTG_HPRT_PRST 0x00000100U
8263 #define USB_OTG_HPRT_PLSTS 0x00000C00U
8264 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
8265 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
8266 #define USB_OTG_HPRT_PPWR 0x00001000U
8268 #define USB_OTG_HPRT_PTCTL 0x0001E000U
8269 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
8270 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
8271 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
8272 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
8274 #define USB_OTG_HPRT_PSPD 0x00060000U
8275 #define USB_OTG_HPRT_PSPD_0 0x00020000U
8276 #define USB_OTG_HPRT_PSPD_1 0x00040000U
8278 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
8279 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
8280 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
8281 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
8282 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
8283 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
8284 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
8285 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
8286 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
8287 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
8288 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
8289 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
8291 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
8292 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
8293 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
8295 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
8296 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
8297 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
8298 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
8299 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
8301 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
8302 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
8303 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
8304 #define USB_OTG_DIEPCTL_STALL 0x00200000U
8306 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
8307 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
8308 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
8309 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
8310 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
8311 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
8312 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
8313 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
8314 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
8315 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
8316 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
8318 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
8319 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
8321 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
8322 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
8323 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
8324 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
8325 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
8326 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
8327 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
8329 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
8330 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
8331 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
8333 #define USB_OTG_HCCHAR_MC 0x00300000U
8334 #define USB_OTG_HCCHAR_MC_0 0x00100000U
8335 #define USB_OTG_HCCHAR_MC_1 0x00200000U
8337 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
8338 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
8339 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
8340 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
8341 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
8342 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
8343 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
8344 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
8345 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
8346 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
8347 #define USB_OTG_HCCHAR_CHENA 0x80000000U
8349 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
8350 
8351 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
8352 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
8353 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
8354 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
8355 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
8356 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
8357 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
8358 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
8360 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
8361 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
8362 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
8363 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
8364 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
8365 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
8366 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
8367 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
8369 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
8370 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
8371 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
8372 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
8373 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
8375 /******************** Bit definition forUSB_OTG_HCINT register ********************/
8376 #define USB_OTG_HCINT_XFRC 0x00000001U
8377 #define USB_OTG_HCINT_CHH 0x00000002U
8378 #define USB_OTG_HCINT_AHBERR 0x00000004U
8379 #define USB_OTG_HCINT_STALL 0x00000008U
8380 #define USB_OTG_HCINT_NAK 0x00000010U
8381 #define USB_OTG_HCINT_ACK 0x00000020U
8382 #define USB_OTG_HCINT_NYET 0x00000040U
8383 #define USB_OTG_HCINT_TXERR 0x00000080U
8384 #define USB_OTG_HCINT_BBERR 0x00000100U
8385 #define USB_OTG_HCINT_FRMOR 0x00000200U
8386 #define USB_OTG_HCINT_DTERR 0x00000400U
8388 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
8389 #define USB_OTG_DIEPINT_XFRC 0x00000001U
8390 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
8391 #define USB_OTG_DIEPINT_TOC 0x00000008U
8392 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
8393 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
8394 #define USB_OTG_DIEPINT_TXFE 0x00000080U
8395 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
8396 #define USB_OTG_DIEPINT_BNA 0x00000200U
8397 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
8398 #define USB_OTG_DIEPINT_BERR 0x00001000U
8399 #define USB_OTG_DIEPINT_NAK 0x00002000U
8401 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
8402 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
8403 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
8404 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
8405 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
8406 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
8407 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
8408 #define USB_OTG_HCINTMSK_NYET 0x00000040U
8409 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
8410 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
8411 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
8412 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
8414 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8415 
8416 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
8417 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
8418 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
8419 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
8420 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
8421 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
8422 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
8423 #define USB_OTG_HCTSIZ_DPID 0x60000000U
8424 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
8425 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
8427 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
8428 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
8430 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
8431 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
8433 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
8434 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
8436 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
8437 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
8438 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
8440 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
8441 
8442 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
8443 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
8444 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
8445 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
8446 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
8447 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
8448 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
8449 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
8450 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
8451 #define USB_OTG_DOEPCTL_STALL 0x00200000U
8452 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
8453 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
8454 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
8455 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
8457 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
8458 #define USB_OTG_DOEPINT_XFRC 0x00000001U
8459 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
8460 #define USB_OTG_DOEPINT_STUP 0x00000008U
8461 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
8462 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
8463 #define USB_OTG_DOEPINT_NYET 0x00004000U
8465 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
8466 
8467 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
8468 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
8470 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
8471 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
8472 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
8474 /******************** Bit definition for PCGCCTL register ********************/
8475 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
8476 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
8477 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
8492 /******************************* ADC Instances ********************************/
8493 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
8494  ((INSTANCE) == ADC2) || \
8495  ((INSTANCE) == ADC3))
8496 
8497 /******************************* CAN Instances ********************************/
8498 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
8499  ((INSTANCE) == CAN2))
8500 
8501 /******************************* CRC Instances ********************************/
8502 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8503 
8504 /******************************* DAC Instances ********************************/
8505 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
8506 
8507 /******************************* DCMI Instances *******************************/
8508 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
8509 
8510 /******************************* DMA2D Instances *******************************/
8511 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
8512 
8513 /******************************** DMA Instances *******************************/
8514 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
8515  ((INSTANCE) == DMA1_Stream1) || \
8516  ((INSTANCE) == DMA1_Stream2) || \
8517  ((INSTANCE) == DMA1_Stream3) || \
8518  ((INSTANCE) == DMA1_Stream4) || \
8519  ((INSTANCE) == DMA1_Stream5) || \
8520  ((INSTANCE) == DMA1_Stream6) || \
8521  ((INSTANCE) == DMA1_Stream7) || \
8522  ((INSTANCE) == DMA2_Stream0) || \
8523  ((INSTANCE) == DMA2_Stream1) || \
8524  ((INSTANCE) == DMA2_Stream2) || \
8525  ((INSTANCE) == DMA2_Stream3) || \
8526  ((INSTANCE) == DMA2_Stream4) || \
8527  ((INSTANCE) == DMA2_Stream5) || \
8528  ((INSTANCE) == DMA2_Stream6) || \
8529  ((INSTANCE) == DMA2_Stream7))
8530 
8531 /******************************* GPIO Instances *******************************/
8532 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8533  ((INSTANCE) == GPIOB) || \
8534  ((INSTANCE) == GPIOC) || \
8535  ((INSTANCE) == GPIOD) || \
8536  ((INSTANCE) == GPIOE) || \
8537  ((INSTANCE) == GPIOF) || \
8538  ((INSTANCE) == GPIOG) || \
8539  ((INSTANCE) == GPIOH) || \
8540  ((INSTANCE) == GPIOI) || \
8541  ((INSTANCE) == GPIOJ) || \
8542  ((INSTANCE) == GPIOK))
8543 
8544 /******************************** I2C Instances *******************************/
8545 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8546  ((INSTANCE) == I2C2) || \
8547  ((INSTANCE) == I2C3))
8548 
8549 /******************************** I2S Instances *******************************/
8550 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
8551  ((INSTANCE) == SPI3))
8552 
8553 /*************************** I2S Extended Instances ***************************/
8554 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
8555  ((INSTANCE) == SPI3) || \
8556  ((INSTANCE) == I2S2ext) || \
8557  ((INSTANCE) == I2S3ext))
8558 
8559 /******************************* RNG Instances ********************************/
8560 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
8561 
8562 /****************************** RTC Instances *********************************/
8563 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
8564 
8565 /******************************* SAI Instances ********************************/
8566 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
8567  ((PERIPH) == SAI1_Block_B))
8568 /* Legacy define */
8569 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
8570 
8571 /******************************** SPI Instances *******************************/
8572 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8573  ((INSTANCE) == SPI2) || \
8574  ((INSTANCE) == SPI3) || \
8575  ((INSTANCE) == SPI4) || \
8576  ((INSTANCE) == SPI5) || \
8577  ((INSTANCE) == SPI6))
8578 
8579 /*************************** SPI Extended Instances ***************************/
8580 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
8581  ((INSTANCE) == SPI2) || \
8582  ((INSTANCE) == SPI3) || \
8583  ((INSTANCE) == SPI4) || \
8584  ((INSTANCE) == SPI5) || \
8585  ((INSTANCE) == SPI6) || \
8586  ((INSTANCE) == I2S2ext) || \
8587  ((INSTANCE) == I2S3ext))
8588 
8589 /****************** TIM Instances : All supported instances *******************/
8590 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8591  ((INSTANCE) == TIM2) || \
8592  ((INSTANCE) == TIM3) || \
8593  ((INSTANCE) == TIM4) || \
8594  ((INSTANCE) == TIM5) || \
8595  ((INSTANCE) == TIM6) || \
8596  ((INSTANCE) == TIM7) || \
8597  ((INSTANCE) == TIM8) || \
8598  ((INSTANCE) == TIM9) || \
8599  ((INSTANCE) == TIM10) || \
8600  ((INSTANCE) == TIM11) || \
8601  ((INSTANCE) == TIM12) || \
8602  ((INSTANCE) == TIM13) || \
8603  ((INSTANCE) == TIM14))
8604 
8605 /************* TIM Instances : at least 1 capture/compare channel *************/
8606 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8607  ((INSTANCE) == TIM2) || \
8608  ((INSTANCE) == TIM3) || \
8609  ((INSTANCE) == TIM4) || \
8610  ((INSTANCE) == TIM5) || \
8611  ((INSTANCE) == TIM8) || \
8612  ((INSTANCE) == TIM9) || \
8613  ((INSTANCE) == TIM10) || \
8614  ((INSTANCE) == TIM11) || \
8615  ((INSTANCE) == TIM12) || \
8616  ((INSTANCE) == TIM13) || \
8617  ((INSTANCE) == TIM14))
8618 
8619 /************ TIM Instances : at least 2 capture/compare channels *************/
8620 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8621  ((INSTANCE) == TIM2) || \
8622  ((INSTANCE) == TIM3) || \
8623  ((INSTANCE) == TIM4) || \
8624  ((INSTANCE) == TIM5) || \
8625  ((INSTANCE) == TIM8) || \
8626  ((INSTANCE) == TIM9) || \
8627  ((INSTANCE) == TIM12))
8628 
8629 /************ TIM Instances : at least 3 capture/compare channels *************/
8630 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8631  ((INSTANCE) == TIM2) || \
8632  ((INSTANCE) == TIM3) || \
8633  ((INSTANCE) == TIM4) || \
8634  ((INSTANCE) == TIM5) || \
8635  ((INSTANCE) == TIM8))
8636 
8637 /************ TIM Instances : at least 4 capture/compare channels *************/
8638 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8639  ((INSTANCE) == TIM2) || \
8640  ((INSTANCE) == TIM3) || \
8641  ((INSTANCE) == TIM4) || \
8642  ((INSTANCE) == TIM5) || \
8643  ((INSTANCE) == TIM8))
8644 
8645 /******************** TIM Instances : Advanced-control timers *****************/
8646 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8647  ((INSTANCE) == TIM8))
8648 
8649 /******************* TIM Instances : Timer input XOR function *****************/
8650 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8651  ((INSTANCE) == TIM2) || \
8652  ((INSTANCE) == TIM3) || \
8653  ((INSTANCE) == TIM4) || \
8654  ((INSTANCE) == TIM5) || \
8655  ((INSTANCE) == TIM8))
8656 
8657 /****************** TIM Instances : DMA requests generation (UDE) *************/
8658 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8659  ((INSTANCE) == TIM2) || \
8660  ((INSTANCE) == TIM3) || \
8661  ((INSTANCE) == TIM4) || \
8662  ((INSTANCE) == TIM5) || \
8663  ((INSTANCE) == TIM6) || \
8664  ((INSTANCE) == TIM7) || \
8665  ((INSTANCE) == TIM8))
8666 
8667 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8668 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8669  ((INSTANCE) == TIM2) || \
8670  ((INSTANCE) == TIM3) || \
8671  ((INSTANCE) == TIM4) || \
8672  ((INSTANCE) == TIM5) || \
8673  ((INSTANCE) == TIM8))
8674 
8675 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8676 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8677  ((INSTANCE) == TIM2) || \
8678  ((INSTANCE) == TIM3) || \
8679  ((INSTANCE) == TIM4) || \
8680  ((INSTANCE) == TIM5) || \
8681  ((INSTANCE) == TIM8))
8682 
8683 /******************** TIM Instances : DMA burst feature ***********************/
8684 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8685  ((INSTANCE) == TIM2) || \
8686  ((INSTANCE) == TIM3) || \
8687  ((INSTANCE) == TIM4) || \
8688  ((INSTANCE) == TIM5) || \
8689  ((INSTANCE) == TIM8))
8690 
8691 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8692 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8693  ((INSTANCE) == TIM2) || \
8694  ((INSTANCE) == TIM3) || \
8695  ((INSTANCE) == TIM4) || \
8696  ((INSTANCE) == TIM5) || \
8697  ((INSTANCE) == TIM6) || \
8698  ((INSTANCE) == TIM7) || \
8699  ((INSTANCE) == TIM8) || \
8700  ((INSTANCE) == TIM9) || \
8701  ((INSTANCE) == TIM12))
8702 
8703 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8704 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8705  ((INSTANCE) == TIM2) || \
8706  ((INSTANCE) == TIM3) || \
8707  ((INSTANCE) == TIM4) || \
8708  ((INSTANCE) == TIM5) || \
8709  ((INSTANCE) == TIM8) || \
8710  ((INSTANCE) == TIM9) || \
8711  ((INSTANCE) == TIM12))
8712 
8713 /********************** TIM Instances : 32 bit Counter ************************/
8714 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
8715  ((INSTANCE) == TIM5))
8716 
8717 /***************** TIM Instances : external trigger input availabe ************/
8718 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8719  ((INSTANCE) == TIM2) || \
8720  ((INSTANCE) == TIM3) || \
8721  ((INSTANCE) == TIM4) || \
8722  ((INSTANCE) == TIM5) || \
8723  ((INSTANCE) == TIM8))
8724 
8725 /****************** TIM Instances : remapping capability **********************/
8726 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8727  ((INSTANCE) == TIM5) || \
8728  ((INSTANCE) == TIM11))
8729 
8730 /******************* TIM Instances : output(s) available **********************/
8731 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8732  ((((INSTANCE) == TIM1) && \
8733  (((CHANNEL) == TIM_CHANNEL_1) || \
8734  ((CHANNEL) == TIM_CHANNEL_2) || \
8735  ((CHANNEL) == TIM_CHANNEL_3) || \
8736  ((CHANNEL) == TIM_CHANNEL_4))) \
8737  || \
8738  (((INSTANCE) == TIM2) && \
8739  (((CHANNEL) == TIM_CHANNEL_1) || \
8740  ((CHANNEL) == TIM_CHANNEL_2) || \
8741  ((CHANNEL) == TIM_CHANNEL_3) || \
8742  ((CHANNEL) == TIM_CHANNEL_4))) \
8743  || \
8744  (((INSTANCE) == TIM3) && \
8745  (((CHANNEL) == TIM_CHANNEL_1) || \
8746  ((CHANNEL) == TIM_CHANNEL_2) || \
8747  ((CHANNEL) == TIM_CHANNEL_3) || \
8748  ((CHANNEL) == TIM_CHANNEL_4))) \
8749  || \
8750  (((INSTANCE) == TIM4) && \
8751  (((CHANNEL) == TIM_CHANNEL_1) || \
8752  ((CHANNEL) == TIM_CHANNEL_2) || \
8753  ((CHANNEL) == TIM_CHANNEL_3) || \
8754  ((CHANNEL) == TIM_CHANNEL_4))) \
8755  || \
8756  (((INSTANCE) == TIM5) && \
8757  (((CHANNEL) == TIM_CHANNEL_1) || \
8758  ((CHANNEL) == TIM_CHANNEL_2) || \
8759  ((CHANNEL) == TIM_CHANNEL_3) || \
8760  ((CHANNEL) == TIM_CHANNEL_4))) \
8761  || \
8762  (((INSTANCE) == TIM8) && \
8763  (((CHANNEL) == TIM_CHANNEL_1) || \
8764  ((CHANNEL) == TIM_CHANNEL_2) || \
8765  ((CHANNEL) == TIM_CHANNEL_3) || \
8766  ((CHANNEL) == TIM_CHANNEL_4))) \
8767  || \
8768  (((INSTANCE) == TIM9) && \
8769  (((CHANNEL) == TIM_CHANNEL_1) || \
8770  ((CHANNEL) == TIM_CHANNEL_2))) \
8771  || \
8772  (((INSTANCE) == TIM10) && \
8773  (((CHANNEL) == TIM_CHANNEL_1))) \
8774  || \
8775  (((INSTANCE) == TIM11) && \
8776  (((CHANNEL) == TIM_CHANNEL_1))) \
8777  || \
8778  (((INSTANCE) == TIM12) && \
8779  (((CHANNEL) == TIM_CHANNEL_1) || \
8780  ((CHANNEL) == TIM_CHANNEL_2))) \
8781  || \
8782  (((INSTANCE) == TIM13) && \
8783  (((CHANNEL) == TIM_CHANNEL_1))) \
8784  || \
8785  (((INSTANCE) == TIM14) && \
8786  (((CHANNEL) == TIM_CHANNEL_1))))
8787 
8788 /************ TIM Instances : complementary output(s) available ***************/
8789 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8790  ((((INSTANCE) == TIM1) && \
8791  (((CHANNEL) == TIM_CHANNEL_1) || \
8792  ((CHANNEL) == TIM_CHANNEL_2) || \
8793  ((CHANNEL) == TIM_CHANNEL_3))) \
8794  || \
8795  (((INSTANCE) == TIM8) && \
8796  (((CHANNEL) == TIM_CHANNEL_1) || \
8797  ((CHANNEL) == TIM_CHANNEL_2) || \
8798  ((CHANNEL) == TIM_CHANNEL_3))))
8799 
8800 /******************** USART Instances : Synchronous mode **********************/
8801 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8802  ((INSTANCE) == USART2) || \
8803  ((INSTANCE) == USART3) || \
8804  ((INSTANCE) == USART6))
8805 
8806 /******************** UART Instances : Asynchronous mode **********************/
8807 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8808  ((INSTANCE) == USART2) || \
8809  ((INSTANCE) == USART3) || \
8810  ((INSTANCE) == UART4) || \
8811  ((INSTANCE) == UART5) || \
8812  ((INSTANCE) == USART6) || \
8813  ((INSTANCE) == UART7) || \
8814  ((INSTANCE) == UART8))
8815 
8816 /****************** UART Instances : Hardware Flow control ********************/
8817 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8818  ((INSTANCE) == USART2) || \
8819  ((INSTANCE) == USART3) || \
8820  ((INSTANCE) == USART6))
8821 
8822 /********************* UART Instances : Smard card mode ***********************/
8823 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8824  ((INSTANCE) == USART2) || \
8825  ((INSTANCE) == USART3) || \
8826  ((INSTANCE) == USART6))
8827 
8828 /*********************** UART Instances : IRDA mode ***************************/
8829 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8830  ((INSTANCE) == USART2) || \
8831  ((INSTANCE) == USART3) || \
8832  ((INSTANCE) == UART4) || \
8833  ((INSTANCE) == UART5) || \
8834  ((INSTANCE) == USART6) || \
8835  ((INSTANCE) == UART7) || \
8836  ((INSTANCE) == UART8))
8837 
8838 /*********************** PCD Instances ****************************************/
8839 /*********************** PCD Instances ****************************************/
8840 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
8841  ((INSTANCE) == USB_OTG_HS))
8842 
8843 /*********************** HCD Instances ****************************************/
8844 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
8845  ((INSTANCE) == USB_OTG_HS))
8846 
8847 /****************************** IWDG Instances ********************************/
8848 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
8849 
8850 /****************************** WWDG Instances ********************************/
8851 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8852 
8853 /****************************** SDIO Instances ********************************/
8854 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
8855 
8856 /****************************** USB Exported Constants ************************/
8857 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
8858 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
8859 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
8860 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
8861 
8862 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
8863 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
8864 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
8865 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
8866 
8867 /******************************************************************************/
8868 /* For a painless codes migration between the STM32F4xx device product */
8869 /* lines, the aliases defined below are put in place to overcome the */
8870 /* differences in the interrupt handlers and IRQn definitions. */
8871 /* No need to update developed interrupt code when moving across */
8872 /* product lines within the same STM32F4 Family */
8873 /******************************************************************************/
8874 
8875 /* Aliases for __IRQn */
8876 #define FSMC_IRQn FMC_IRQn
8877 
8878 /* Aliases for __IRQHandler */
8879 #define FSMC_IRQHandler FMC_IRQHandler
8880 
8893 #ifdef __cplusplus
8894 }
8895 #endif /* __cplusplus */
8896 
8897 #endif /* __stm32f427xx_H */
8898 
8899 
8900 
8901 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DMA2D_TypeDef::AMTCR
__IO uint32_t AMTCR
Definition: stm32f427xx.h:412
FMC_Bank4_TypeDef::SR4
__IO uint32_t SR4
Definition: stm32f427xx.h:568
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
FMC_Bank4_TypeDef::PIO4
__IO uint32_t PIO4
Definition: stm32f427xx.h:571
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
SAI1_IRQn
Definition: stm32f427xx.h:182
TAMP_STAMP_IRQn
Definition: stm32f427xx.h:98
FMC_Bank2_3_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f427xx.h:552
FMC_Bank2_3_TypeDef::PCR2
__IO uint32_t PCR2
Definition: stm32f427xx.h:545
TIM2_IRQn
Definition: stm32f427xx.h:124
UART4_IRQn
Definition: stm32f427xx.h:148
UART5_IRQn
Definition: stm32f427xx.h:149
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f427xx.h:122
EXTI2_IRQn
Definition: stm32f427xx.h:104
EXTI4_IRQn
Definition: stm32f427xx.h:106
USART1_IRQn
Definition: stm32f427xx.h:133
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
ETH_WKUP_IRQn
Definition: stm32f427xx.h:158
DMA2D_IRQn
Definition: stm32f427xx.h:183
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f427xx.h:757
DMA2D_TypeDef::LWR
__IO uint32_t LWR
Definition: stm32f427xx.h:411
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition: stm32f427xx.h:763
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f427xx.h:141
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition: stm32f427xx.h:759
TIM4_IRQn
Definition: stm32f427xx.h:126
FMC_Bank2_3_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f427xx.h:551
RTC_Alarm_IRQn
Definition: stm32f427xx.h:137
CAN2_SCE_IRQn
Definition: stm32f427xx.h:162
PendSV_IRQn
Definition: stm32f427xx.h:93
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f427xx.h:99
DMA2D_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f427xx.h:394
FMC_Bank2_3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f427xx.h:549
DMA2D_TypeDef::CR
__IO uint32_t CR
Definition: stm32f427xx.h:393
CAN1_RX1_IRQn
Definition: stm32f427xx.h:117
TIM6_DAC_IRQn
Definition: stm32f427xx.h:150
CAN1_TX_IRQn
Definition: stm32f427xx.h:115
DMA2D_TypeDef::FGPFCCR
__IO uint32_t FGPFCCR
Definition: stm32f427xx.h:400
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
FMC_Bank5_6_TypeDef::SDCMR
__IO uint32_t SDCMR
Definition: stm32f427xx.h:582
SPI1_IRQn
Definition: stm32f427xx.h:131
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f427xx.h:534
OTG_FS_WKUP_IRQn
Definition: stm32f427xx.h:138
DMA_TypeDef
Definition: stm32f401xc.h:243
ETH_IRQn
Definition: stm32f427xx.h:157
DMA1_Stream2_IRQn
Definition: stm32f427xx.h:109
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f427xx.h:132
FMC_Bank2_3_TypeDef::PCR3
__IO uint32_t PCR3
Definition: stm32f427xx.h:553
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition: stm32f427xx.h:760
FMC_Bank2_3_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32f427xx.h:543
FMC_Bank4_TypeDef::PCR4
__IO uint32_t PCR4
Definition: stm32f427xx.h:567
__I
#define __I
Definition: core_cm0.h:210
FMC_Bank2_3_TypeDef::PATT3
__IO uint32_t PATT3
Definition: stm32f427xx.h:556
FMC_Bank2_3_TypeDef::SR3
__IO uint32_t SR3
Definition: stm32f427xx.h:554
DMA2_Stream5_IRQn
Definition: stm32f427xx.h:164
ADC_IRQn
Definition: stm32f427xx.h:114
CAN1_RX0_IRQn
Definition: stm32f427xx.h:116
DMA2D_TypeDef::OCOLR
__IO uint32_t OCOLR
Definition: stm32f427xx.h:407
RCC_IRQn
Definition: stm32f427xx.h:101
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f427xx.h:758
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f427xx.h:92
DMA2D_TypeDef::OMAR
__IO uint32_t OMAR
Definition: stm32f427xx.h:408
DMA2_Stream3_IRQn
Definition: stm32f427xx.h:155
NonMaskableInt_IRQn
Definition: stm32f427xx.h:87
UART8_IRQn
Definition: stm32f427xx.h:178
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f427xx.h:84
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f427xx.h:140
DMA1_Stream1_IRQn
Definition: stm32f427xx.h:108
DMA2_Stream7_IRQn
Definition: stm32f427xx.h:166
FMC_Bank2_3_TypeDef::PATT2
__IO uint32_t PATT2
Definition: stm32f427xx.h:548
DMA2_Stream6_IRQn
Definition: stm32f427xx.h:165
BusFault_IRQn
Definition: stm32f427xx.h:89
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
I2C3_ER_IRQn
Definition: stm32f427xx.h:169
CAN2_RX0_IRQn
Definition: stm32f427xx.h:160
USART6_IRQn
Definition: stm32f427xx.h:167
PVD_IRQn
Definition: stm32f427xx.h:97
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f427xx.h:391
FMC_Bank4_TypeDef
Flexible Memory Controller Bank4.
Definition: stm32f427xx.h:565
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f427xx.h:111
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f427xx.h:750
DMA1_Stream0_IRQn
Definition: stm32f427xx.h:107
OTG_HS_IRQn
Definition: stm32f427xx.h:173
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f427xx.h:179
TIM8_CC_IRQn
Definition: stm32f427xx.h:142
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32f427xx.h:752
DMA1_Stream3_IRQn
Definition: stm32f427xx.h:110
DMA2D_TypeDef::BGCOLR
__IO uint32_t BGCOLR
Definition: stm32f427xx.h:403
FPU_IRQn
Definition: stm32f427xx.h:176
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:386
OTG_FS_IRQn
Definition: stm32f427xx.h:163
DMA2_Stream2_IRQn
Definition: stm32f427xx.h:154
FMC_Bank2_3_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f427xx.h:546
OTG_HS_EP1_OUT_IRQn
Definition: stm32f427xx.h:170
OTG_HS_EP1_IN_IRQn
Definition: stm32f427xx.h:171
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
DMA2D_TypeDef::OPFCCR
__IO uint32_t OPFCCR
Definition: stm32f427xx.h:406
SDIO_IRQn
Definition: stm32f427xx.h:145
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
DMA2D_TypeDef::OOR
__IO uint32_t OOR
Definition: stm32f427xx.h:409
I2C3_EV_IRQn
Definition: stm32f427xx.h:168
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f427xx.h:134
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
DMA2D_TypeDef::FGOR
__IO uint32_t FGOR
Definition: stm32f427xx.h:397
TIM7_IRQn
Definition: stm32f427xx.h:151
I2C2_EV_IRQn
Definition: stm32f427xx.h:129
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
DMA2D_TypeDef::NLR
__IO uint32_t NLR
Definition: stm32f427xx.h:410
TIM3_IRQn
Definition: stm32f427xx.h:125
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f427xx.h:103
DMA2D_TypeDef::BGPFCCR
__IO uint32_t BGPFCCR
Definition: stm32f427xx.h:402
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f427xx.h:91
FMC_Bank4_TypeDef::PATT4
__IO uint32_t PATT4
Definition: stm32f427xx.h:570
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f427xx.h:123
TIM8_BRK_TIM12_IRQn
Definition: stm32f427xx.h:139
FMC_Bank2_3_TypeDef::PMEM3
__IO uint32_t PMEM3
Definition: stm32f427xx.h:555
HASH_RNG_IRQn
Definition: stm32f427xx.h:175
FLASH_IRQn
Definition: stm32f427xx.h:100
DMA1_Stream5_IRQn
Definition: stm32f427xx.h:112
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f427xx.h:94
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f427xx.h:525
SPI6_IRQn
Definition: stm32f427xx.h:181
TIM1_UP_TIM10_IRQn
Definition: stm32f427xx.h:121
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f427xx.h:130
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:344
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f427xx.h:578
UsageFault_IRQn
Definition: stm32f427xx.h:90
DMA2D_TypeDef::FGMAR
__IO uint32_t FGMAR
Definition: stm32f427xx.h:396
DMA2D_TypeDef::FGCOLR
__IO uint32_t FGCOLR
Definition: stm32f427xx.h:401
FMC_IRQn
Definition: stm32f427xx.h:144
SPI3_IRQn
Definition: stm32f427xx.h:147
DMA2D_TypeDef::FGCMAR
__IO uint32_t FGCMAR
Definition: stm32f427xx.h:404
DMA2_Stream1_IRQn
Definition: stm32f427xx.h:153
EXTI9_5_IRQn
Definition: stm32f427xx.h:119
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
RCC_TypeDef::PLLSAICFGR
__IO uint32_t PLLSAICFGR
Definition: stm32f427xx.h:693
I2C1_EV_IRQn
Definition: stm32f427xx.h:127
DMA1_Stream6_IRQn
Definition: stm32f427xx.h:113
OTG_HS_WKUP_IRQn
Definition: stm32f427xx.h:172
I2C1_ER_IRQn
Definition: stm32f427xx.h:128
FMC_Bank2_3_TypeDef::ECCR3
__IO uint32_t ECCR3
Definition: stm32f427xx.h:558
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
FMC_Bank5_6_TypeDef::SDRTR
__IO uint32_t SDRTR
Definition: stm32f427xx.h:583
UART7_IRQn
Definition: stm32f427xx.h:177
DMA2D_TypeDef::BGMAR
__IO uint32_t BGMAR
Definition: stm32f427xx.h:398
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
DMA2D_TypeDef::BGCMAR
__IO uint32_t BGCMAR
Definition: stm32f427xx.h:405
SAI_Block_TypeDef
Definition: stm32f427xx.h:755
CAN2_RX1_IRQn
Definition: stm32f427xx.h:161
DMA2D_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32f427xx.h:395
DMA2_Stream4_IRQn
Definition: stm32f427xx.h:156
WWDG_IRQn
Definition: stm32f427xx.h:96
DMA1_Stream7_IRQn
Definition: stm32f427xx.h:143
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
FMC_Bank5_6_TypeDef::SDSR
__IO uint32_t SDSR
Definition: stm32f427xx.h:584
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f427xx.h:761
FMC_Bank2_3_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f427xx.h:557
SPI5_IRQn
Definition: stm32f427xx.h:180
FMC_Bank2_3_TypeDef::PMEM2
__IO uint32_t PMEM2
Definition: stm32f427xx.h:547
EXTI15_10_IRQn
Definition: stm32f427xx.h:136
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition: stm32f427xx.h:764
CAN1_SCE_IRQn
Definition: stm32f427xx.h:118
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f427xx.h:102
DMA2_Stream0_IRQn
Definition: stm32f427xx.h:152
TIM1_BRK_TIM9_IRQn
Definition: stm32f427xx.h:120
CAN2_TX_IRQn
Definition: stm32f427xx.h:159
TIM5_IRQn
Definition: stm32f427xx.h:146
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f427xx.h:105
USART3_IRQn
Definition: stm32f427xx.h:135
DCMI_IRQn
Definition: stm32f427xx.h:174
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition: stm32f427xx.h:762
DMA2D_TypeDef::BGOR
__IO uint32_t BGOR
Definition: stm32f427xx.h:399
FMC_Bank4_TypeDef::PMEM4
__IO uint32_t PMEM4
Definition: stm32f427xx.h:569
FMC_Bank2_3_TypeDef::ECCR2
__IO uint32_t ECCR2
Definition: stm32f427xx.h:550
MemoryManagement_IRQn
Definition: stm32f427xx.h:88