STM CMSIS
stm32f429xx.h
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1 
52 #ifndef __STM32F429xx_H
53 #define __STM32F429xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
66 #define __CM4_REV 0x0001U
67 #define __MPU_PRESENT 1U
68 #define __NVIC_PRIO_BITS 4U
69 #define __Vendor_SysTickConfig 0U
70 #define __FPU_PRESENT 1U
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87  NonMaskableInt_IRQn = -14,
88  MemoryManagement_IRQn = -12,
89  BusFault_IRQn = -11,
90  UsageFault_IRQn = -10,
91  SVCall_IRQn = -5,
92  DebugMonitor_IRQn = -4,
93  PendSV_IRQn = -2,
94  SysTick_IRQn = -1,
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96  WWDG_IRQn = 0,
97  PVD_IRQn = 1,
98  TAMP_STAMP_IRQn = 2,
99  RTC_WKUP_IRQn = 3,
100  FLASH_IRQn = 4,
101  RCC_IRQn = 5,
102  EXTI0_IRQn = 6,
103  EXTI1_IRQn = 7,
104  EXTI2_IRQn = 8,
105  EXTI3_IRQn = 9,
106  EXTI4_IRQn = 10,
107  DMA1_Stream0_IRQn = 11,
108  DMA1_Stream1_IRQn = 12,
109  DMA1_Stream2_IRQn = 13,
110  DMA1_Stream3_IRQn = 14,
111  DMA1_Stream4_IRQn = 15,
112  DMA1_Stream5_IRQn = 16,
113  DMA1_Stream6_IRQn = 17,
114  ADC_IRQn = 18,
115  CAN1_TX_IRQn = 19,
116  CAN1_RX0_IRQn = 20,
117  CAN1_RX1_IRQn = 21,
118  CAN1_SCE_IRQn = 22,
119  EXTI9_5_IRQn = 23,
120  TIM1_BRK_TIM9_IRQn = 24,
121  TIM1_UP_TIM10_IRQn = 25,
122  TIM1_TRG_COM_TIM11_IRQn = 26,
123  TIM1_CC_IRQn = 27,
124  TIM2_IRQn = 28,
125  TIM3_IRQn = 29,
126  TIM4_IRQn = 30,
127  I2C1_EV_IRQn = 31,
128  I2C1_ER_IRQn = 32,
129  I2C2_EV_IRQn = 33,
130  I2C2_ER_IRQn = 34,
131  SPI1_IRQn = 35,
132  SPI2_IRQn = 36,
133  USART1_IRQn = 37,
134  USART2_IRQn = 38,
135  USART3_IRQn = 39,
136  EXTI15_10_IRQn = 40,
137  RTC_Alarm_IRQn = 41,
138  OTG_FS_WKUP_IRQn = 42,
139  TIM8_BRK_TIM12_IRQn = 43,
140  TIM8_UP_TIM13_IRQn = 44,
141  TIM8_TRG_COM_TIM14_IRQn = 45,
142  TIM8_CC_IRQn = 46,
143  DMA1_Stream7_IRQn = 47,
144  FMC_IRQn = 48,
145  SDIO_IRQn = 49,
146  TIM5_IRQn = 50,
147  SPI3_IRQn = 51,
148  UART4_IRQn = 52,
149  UART5_IRQn = 53,
150  TIM6_DAC_IRQn = 54,
151  TIM7_IRQn = 55,
152  DMA2_Stream0_IRQn = 56,
153  DMA2_Stream1_IRQn = 57,
154  DMA2_Stream2_IRQn = 58,
155  DMA2_Stream3_IRQn = 59,
156  DMA2_Stream4_IRQn = 60,
157  ETH_IRQn = 61,
158  ETH_WKUP_IRQn = 62,
159  CAN2_TX_IRQn = 63,
160  CAN2_RX0_IRQn = 64,
161  CAN2_RX1_IRQn = 65,
162  CAN2_SCE_IRQn = 66,
163  OTG_FS_IRQn = 67,
164  DMA2_Stream5_IRQn = 68,
165  DMA2_Stream6_IRQn = 69,
166  DMA2_Stream7_IRQn = 70,
167  USART6_IRQn = 71,
168  I2C3_EV_IRQn = 72,
169  I2C3_ER_IRQn = 73,
170  OTG_HS_EP1_OUT_IRQn = 74,
171  OTG_HS_EP1_IN_IRQn = 75,
172  OTG_HS_WKUP_IRQn = 76,
173  OTG_HS_IRQn = 77,
174  DCMI_IRQn = 78,
175  HASH_RNG_IRQn = 80,
176  FPU_IRQn = 81,
177  UART7_IRQn = 82,
178  UART8_IRQn = 83,
179  SPI4_IRQn = 84,
180  SPI5_IRQn = 85,
181  SPI6_IRQn = 86,
182  SAI1_IRQn = 87,
183  LTDC_IRQn = 88,
184  LTDC_ER_IRQn = 89,
185  DMA2D_IRQn = 90
186 } IRQn_Type;
187 
192 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
193 #include "system_stm32f4xx.h"
194 #include <stdint.h>
195 
204 typedef struct
205 {
206  __IO uint32_t SR;
207  __IO uint32_t CR1;
208  __IO uint32_t CR2;
209  __IO uint32_t SMPR1;
210  __IO uint32_t SMPR2;
211  __IO uint32_t JOFR1;
212  __IO uint32_t JOFR2;
213  __IO uint32_t JOFR3;
214  __IO uint32_t JOFR4;
215  __IO uint32_t HTR;
216  __IO uint32_t LTR;
217  __IO uint32_t SQR1;
218  __IO uint32_t SQR2;
219  __IO uint32_t SQR3;
220  __IO uint32_t JSQR;
221  __IO uint32_t JDR1;
222  __IO uint32_t JDR2;
223  __IO uint32_t JDR3;
224  __IO uint32_t JDR4;
225  __IO uint32_t DR;
226 } ADC_TypeDef;
227 
228 typedef struct
229 {
230  __IO uint32_t CSR;
231  __IO uint32_t CCR;
232  __IO uint32_t CDR;
234 } ADC_Common_TypeDef;
235 
236 
241 typedef struct
242 {
243  __IO uint32_t TIR;
244  __IO uint32_t TDTR;
245  __IO uint32_t TDLR;
246  __IO uint32_t TDHR;
247 } CAN_TxMailBox_TypeDef;
248 
253 typedef struct
254 {
255  __IO uint32_t RIR;
256  __IO uint32_t RDTR;
257  __IO uint32_t RDLR;
258  __IO uint32_t RDHR;
259 } CAN_FIFOMailBox_TypeDef;
260 
265 typedef struct
266 {
267  __IO uint32_t FR1;
268  __IO uint32_t FR2;
269 } CAN_FilterRegister_TypeDef;
270 
275 typedef struct
276 {
277  __IO uint32_t MCR;
278  __IO uint32_t MSR;
279  __IO uint32_t TSR;
280  __IO uint32_t RF0R;
281  __IO uint32_t RF1R;
282  __IO uint32_t IER;
283  __IO uint32_t ESR;
284  __IO uint32_t BTR;
285  uint32_t RESERVED0[88];
286  CAN_TxMailBox_TypeDef sTxMailBox[3];
287  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
288  uint32_t RESERVED1[12];
289  __IO uint32_t FMR;
290  __IO uint32_t FM1R;
291  uint32_t RESERVED2;
292  __IO uint32_t FS1R;
293  uint32_t RESERVED3;
294  __IO uint32_t FFA1R;
295  uint32_t RESERVED4;
296  __IO uint32_t FA1R;
297  uint32_t RESERVED5[8];
298  CAN_FilterRegister_TypeDef sFilterRegister[28];
299 } CAN_TypeDef;
300 
305 typedef struct
306 {
307  __IO uint32_t DR;
308  __IO uint8_t IDR;
309  uint8_t RESERVED0;
310  uint16_t RESERVED1;
311  __IO uint32_t CR;
312 } CRC_TypeDef;
313 
318 typedef struct
319 {
320  __IO uint32_t CR;
321  __IO uint32_t SWTRIGR;
322  __IO uint32_t DHR12R1;
323  __IO uint32_t DHR12L1;
324  __IO uint32_t DHR8R1;
325  __IO uint32_t DHR12R2;
326  __IO uint32_t DHR12L2;
327  __IO uint32_t DHR8R2;
328  __IO uint32_t DHR12RD;
329  __IO uint32_t DHR12LD;
330  __IO uint32_t DHR8RD;
331  __IO uint32_t DOR1;
332  __IO uint32_t DOR2;
333  __IO uint32_t SR;
334 } DAC_TypeDef;
335 
340 typedef struct
341 {
342  __IO uint32_t IDCODE;
343  __IO uint32_t CR;
344  __IO uint32_t APB1FZ;
345  __IO uint32_t APB2FZ;
346 }DBGMCU_TypeDef;
347 
352 typedef struct
353 {
354  __IO uint32_t CR;
355  __IO uint32_t SR;
356  __IO uint32_t RISR;
357  __IO uint32_t IER;
358  __IO uint32_t MISR;
359  __IO uint32_t ICR;
360  __IO uint32_t ESCR;
361  __IO uint32_t ESUR;
362  __IO uint32_t CWSTRTR;
363  __IO uint32_t CWSIZER;
364  __IO uint32_t DR;
365 } DCMI_TypeDef;
366 
371 typedef struct
372 {
373  __IO uint32_t CR;
374  __IO uint32_t NDTR;
375  __IO uint32_t PAR;
376  __IO uint32_t M0AR;
377  __IO uint32_t M1AR;
378  __IO uint32_t FCR;
379 } DMA_Stream_TypeDef;
380 
381 typedef struct
382 {
383  __IO uint32_t LISR;
384  __IO uint32_t HISR;
385  __IO uint32_t LIFCR;
386  __IO uint32_t HIFCR;
387 } DMA_TypeDef;
388 
393 typedef struct
394 {
395  __IO uint32_t CR;
396  __IO uint32_t ISR;
397  __IO uint32_t IFCR;
398  __IO uint32_t FGMAR;
399  __IO uint32_t FGOR;
400  __IO uint32_t BGMAR;
401  __IO uint32_t BGOR;
402  __IO uint32_t FGPFCCR;
403  __IO uint32_t FGCOLR;
404  __IO uint32_t BGPFCCR;
405  __IO uint32_t BGCOLR;
406  __IO uint32_t FGCMAR;
407  __IO uint32_t BGCMAR;
408  __IO uint32_t OPFCCR;
409  __IO uint32_t OCOLR;
410  __IO uint32_t OMAR;
411  __IO uint32_t OOR;
412  __IO uint32_t NLR;
413  __IO uint32_t LWR;
414  __IO uint32_t AMTCR;
415  uint32_t RESERVED[236];
416  __IO uint32_t FGCLUT[256];
417  __IO uint32_t BGCLUT[256];
418 } DMA2D_TypeDef;
419 
424 typedef struct
425 {
426  __IO uint32_t MACCR;
427  __IO uint32_t MACFFR;
428  __IO uint32_t MACHTHR;
429  __IO uint32_t MACHTLR;
430  __IO uint32_t MACMIIAR;
431  __IO uint32_t MACMIIDR;
432  __IO uint32_t MACFCR;
433  __IO uint32_t MACVLANTR; /* 8 */
434  uint32_t RESERVED0[2];
435  __IO uint32_t MACRWUFFR; /* 11 */
436  __IO uint32_t MACPMTCSR;
437  uint32_t RESERVED1[2];
438  __IO uint32_t MACSR; /* 15 */
439  __IO uint32_t MACIMR;
440  __IO uint32_t MACA0HR;
441  __IO uint32_t MACA0LR;
442  __IO uint32_t MACA1HR;
443  __IO uint32_t MACA1LR;
444  __IO uint32_t MACA2HR;
445  __IO uint32_t MACA2LR;
446  __IO uint32_t MACA3HR;
447  __IO uint32_t MACA3LR; /* 24 */
448  uint32_t RESERVED2[40];
449  __IO uint32_t MMCCR; /* 65 */
450  __IO uint32_t MMCRIR;
451  __IO uint32_t MMCTIR;
452  __IO uint32_t MMCRIMR;
453  __IO uint32_t MMCTIMR; /* 69 */
454  uint32_t RESERVED3[14];
455  __IO uint32_t MMCTGFSCCR; /* 84 */
456  __IO uint32_t MMCTGFMSCCR;
457  uint32_t RESERVED4[5];
458  __IO uint32_t MMCTGFCR;
459  uint32_t RESERVED5[10];
460  __IO uint32_t MMCRFCECR;
461  __IO uint32_t MMCRFAECR;
462  uint32_t RESERVED6[10];
463  __IO uint32_t MMCRGUFCR;
464  uint32_t RESERVED7[334];
465  __IO uint32_t PTPTSCR;
466  __IO uint32_t PTPSSIR;
467  __IO uint32_t PTPTSHR;
468  __IO uint32_t PTPTSLR;
469  __IO uint32_t PTPTSHUR;
470  __IO uint32_t PTPTSLUR;
471  __IO uint32_t PTPTSAR;
472  __IO uint32_t PTPTTHR;
473  __IO uint32_t PTPTTLR;
474  __IO uint32_t RESERVED8;
475  __IO uint32_t PTPTSSR;
476  uint32_t RESERVED9[565];
477  __IO uint32_t DMABMR;
478  __IO uint32_t DMATPDR;
479  __IO uint32_t DMARPDR;
480  __IO uint32_t DMARDLAR;
481  __IO uint32_t DMATDLAR;
482  __IO uint32_t DMASR;
483  __IO uint32_t DMAOMR;
484  __IO uint32_t DMAIER;
485  __IO uint32_t DMAMFBOCR;
486  __IO uint32_t DMARSWTR;
487  uint32_t RESERVED10[8];
488  __IO uint32_t DMACHTDR;
489  __IO uint32_t DMACHRDR;
490  __IO uint32_t DMACHTBAR;
491  __IO uint32_t DMACHRBAR;
492 } ETH_TypeDef;
493 
498 typedef struct
499 {
500  __IO uint32_t IMR;
501  __IO uint32_t EMR;
502  __IO uint32_t RTSR;
503  __IO uint32_t FTSR;
504  __IO uint32_t SWIER;
505  __IO uint32_t PR;
506 } EXTI_TypeDef;
507 
512 typedef struct
513 {
514  __IO uint32_t ACR;
515  __IO uint32_t KEYR;
516  __IO uint32_t OPTKEYR;
517  __IO uint32_t SR;
518  __IO uint32_t CR;
519  __IO uint32_t OPTCR;
520  __IO uint32_t OPTCR1;
521 } FLASH_TypeDef;
522 
527 typedef struct
528 {
529  __IO uint32_t BTCR[8];
530 } FMC_Bank1_TypeDef;
531 
536 typedef struct
537 {
538  __IO uint32_t BWTR[7];
539 } FMC_Bank1E_TypeDef;
540 
545 typedef struct
546 {
547  __IO uint32_t PCR2;
548  __IO uint32_t SR2;
549  __IO uint32_t PMEM2;
550  __IO uint32_t PATT2;
551  uint32_t RESERVED0;
552  __IO uint32_t ECCR2;
553  uint32_t RESERVED1;
554  uint32_t RESERVED2;
555  __IO uint32_t PCR3;
556  __IO uint32_t SR3;
557  __IO uint32_t PMEM3;
558  __IO uint32_t PATT3;
559  uint32_t RESERVED3;
560  __IO uint32_t ECCR3;
561 } FMC_Bank2_3_TypeDef;
562 
567 typedef struct
568 {
569  __IO uint32_t PCR4;
570  __IO uint32_t SR4;
571  __IO uint32_t PMEM4;
572  __IO uint32_t PATT4;
573  __IO uint32_t PIO4;
574 } FMC_Bank4_TypeDef;
575 
580 typedef struct
581 {
582  __IO uint32_t SDCR[2];
583  __IO uint32_t SDTR[2];
584  __IO uint32_t SDCMR;
585  __IO uint32_t SDRTR;
586  __IO uint32_t SDSR;
587 } FMC_Bank5_6_TypeDef;
588 
593 typedef struct
594 {
595  __IO uint32_t MODER;
596  __IO uint32_t OTYPER;
597  __IO uint32_t OSPEEDR;
598  __IO uint32_t PUPDR;
599  __IO uint32_t IDR;
600  __IO uint32_t ODR;
601  __IO uint32_t BSRR;
602  __IO uint32_t LCKR;
603  __IO uint32_t AFR[2];
604 } GPIO_TypeDef;
605 
610 typedef struct
611 {
612  __IO uint32_t MEMRMP;
613  __IO uint32_t PMC;
614  __IO uint32_t EXTICR[4];
615  uint32_t RESERVED[2];
616  __IO uint32_t CMPCR;
617 } SYSCFG_TypeDef;
618 
623 typedef struct
624 {
625  __IO uint32_t CR1;
626  __IO uint32_t CR2;
627  __IO uint32_t OAR1;
628  __IO uint32_t OAR2;
629  __IO uint32_t DR;
630  __IO uint32_t SR1;
631  __IO uint32_t SR2;
632  __IO uint32_t CCR;
633  __IO uint32_t TRISE;
634  __IO uint32_t FLTR;
635 } I2C_TypeDef;
636 
641 typedef struct
642 {
643  __IO uint32_t KR;
644  __IO uint32_t PR;
645  __IO uint32_t RLR;
646  __IO uint32_t SR;
647 } IWDG_TypeDef;
648 
653 typedef struct
654 {
655  uint32_t RESERVED0[2];
656  __IO uint32_t SSCR;
657  __IO uint32_t BPCR;
658  __IO uint32_t AWCR;
659  __IO uint32_t TWCR;
660  __IO uint32_t GCR;
661  uint32_t RESERVED1[2];
662  __IO uint32_t SRCR;
663  uint32_t RESERVED2[1];
664  __IO uint32_t BCCR;
665  uint32_t RESERVED3[1];
666  __IO uint32_t IER;
667  __IO uint32_t ISR;
668  __IO uint32_t ICR;
669  __IO uint32_t LIPCR;
670  __IO uint32_t CPSR;
671  __IO uint32_t CDSR;
672 } LTDC_TypeDef;
673 
678 typedef struct
679 {
680  __IO uint32_t CR;
681  __IO uint32_t WHPCR;
682  __IO uint32_t WVPCR;
683  __IO uint32_t CKCR;
684  __IO uint32_t PFCR;
685  __IO uint32_t CACR;
686  __IO uint32_t DCCR;
687  __IO uint32_t BFCR;
688  uint32_t RESERVED0[2];
689  __IO uint32_t CFBAR;
690  __IO uint32_t CFBLR;
691  __IO uint32_t CFBLNR;
692  uint32_t RESERVED1[3];
693  __IO uint32_t CLUTWR;
695 } LTDC_Layer_TypeDef;
696 
701 typedef struct
702 {
703  __IO uint32_t CR;
704  __IO uint32_t CSR;
705 } PWR_TypeDef;
706 
711 typedef struct
712 {
713  __IO uint32_t CR;
714  __IO uint32_t PLLCFGR;
715  __IO uint32_t CFGR;
716  __IO uint32_t CIR;
717  __IO uint32_t AHB1RSTR;
718  __IO uint32_t AHB2RSTR;
719  __IO uint32_t AHB3RSTR;
720  uint32_t RESERVED0;
721  __IO uint32_t APB1RSTR;
722  __IO uint32_t APB2RSTR;
723  uint32_t RESERVED1[2];
724  __IO uint32_t AHB1ENR;
725  __IO uint32_t AHB2ENR;
726  __IO uint32_t AHB3ENR;
727  uint32_t RESERVED2;
728  __IO uint32_t APB1ENR;
729  __IO uint32_t APB2ENR;
730  uint32_t RESERVED3[2];
731  __IO uint32_t AHB1LPENR;
732  __IO uint32_t AHB2LPENR;
733  __IO uint32_t AHB3LPENR;
734  uint32_t RESERVED4;
735  __IO uint32_t APB1LPENR;
736  __IO uint32_t APB2LPENR;
737  uint32_t RESERVED5[2];
738  __IO uint32_t BDCR;
739  __IO uint32_t CSR;
740  uint32_t RESERVED6[2];
741  __IO uint32_t SSCGR;
742  __IO uint32_t PLLI2SCFGR;
743  __IO uint32_t PLLSAICFGR;
744  __IO uint32_t DCKCFGR;
746 } RCC_TypeDef;
747 
752 typedef struct
753 {
754  __IO uint32_t TR;
755  __IO uint32_t DR;
756  __IO uint32_t CR;
757  __IO uint32_t ISR;
758  __IO uint32_t PRER;
759  __IO uint32_t WUTR;
760  __IO uint32_t CALIBR;
761  __IO uint32_t ALRMAR;
762  __IO uint32_t ALRMBR;
763  __IO uint32_t WPR;
764  __IO uint32_t SSR;
765  __IO uint32_t SHIFTR;
766  __IO uint32_t TSTR;
767  __IO uint32_t TSDR;
768  __IO uint32_t TSSSR;
769  __IO uint32_t CALR;
770  __IO uint32_t TAFCR;
771  __IO uint32_t ALRMASSR;
772  __IO uint32_t ALRMBSSR;
773  uint32_t RESERVED7;
774  __IO uint32_t BKP0R;
775  __IO uint32_t BKP1R;
776  __IO uint32_t BKP2R;
777  __IO uint32_t BKP3R;
778  __IO uint32_t BKP4R;
779  __IO uint32_t BKP5R;
780  __IO uint32_t BKP6R;
781  __IO uint32_t BKP7R;
782  __IO uint32_t BKP8R;
783  __IO uint32_t BKP9R;
784  __IO uint32_t BKP10R;
785  __IO uint32_t BKP11R;
786  __IO uint32_t BKP12R;
787  __IO uint32_t BKP13R;
788  __IO uint32_t BKP14R;
789  __IO uint32_t BKP15R;
790  __IO uint32_t BKP16R;
791  __IO uint32_t BKP17R;
792  __IO uint32_t BKP18R;
793  __IO uint32_t BKP19R;
794 } RTC_TypeDef;
795 
800 typedef struct
801 {
802  __IO uint32_t GCR;
803 } SAI_TypeDef;
804 
805 typedef struct
806 {
807  __IO uint32_t CR1;
808  __IO uint32_t CR2;
809  __IO uint32_t FRCR;
810  __IO uint32_t SLOTR;
811  __IO uint32_t IMR;
812  __IO uint32_t SR;
813  __IO uint32_t CLRFR;
814  __IO uint32_t DR;
815 } SAI_Block_TypeDef;
816 
821 typedef struct
822 {
823  __IO uint32_t POWER;
824  __IO uint32_t CLKCR;
825  __IO uint32_t ARG;
826  __IO uint32_t CMD;
827  __I uint32_t RESPCMD;
828  __I uint32_t RESP1;
829  __I uint32_t RESP2;
830  __I uint32_t RESP3;
831  __I uint32_t RESP4;
832  __IO uint32_t DTIMER;
833  __IO uint32_t DLEN;
834  __IO uint32_t DCTRL;
835  __I uint32_t DCOUNT;
836  __I uint32_t STA;
837  __IO uint32_t ICR;
838  __IO uint32_t MASK;
839  uint32_t RESERVED0[2];
840  __I uint32_t FIFOCNT;
841  uint32_t RESERVED1[13];
842  __IO uint32_t FIFO;
843 } SDIO_TypeDef;
844 
849 typedef struct
850 {
851  __IO uint32_t CR1;
852  __IO uint32_t CR2;
853  __IO uint32_t SR;
854  __IO uint32_t DR;
855  __IO uint32_t CRCPR;
856  __IO uint32_t RXCRCR;
857  __IO uint32_t TXCRCR;
858  __IO uint32_t I2SCFGR;
859  __IO uint32_t I2SPR;
860 } SPI_TypeDef;
861 
866 typedef struct
867 {
868  __IO uint32_t CR1;
869  __IO uint32_t CR2;
870  __IO uint32_t SMCR;
871  __IO uint32_t DIER;
872  __IO uint32_t SR;
873  __IO uint32_t EGR;
874  __IO uint32_t CCMR1;
875  __IO uint32_t CCMR2;
876  __IO uint32_t CCER;
877  __IO uint32_t CNT;
878  __IO uint32_t PSC;
879  __IO uint32_t ARR;
880  __IO uint32_t RCR;
881  __IO uint32_t CCR1;
882  __IO uint32_t CCR2;
883  __IO uint32_t CCR3;
884  __IO uint32_t CCR4;
885  __IO uint32_t BDTR;
886  __IO uint32_t DCR;
887  __IO uint32_t DMAR;
888  __IO uint32_t OR;
889 } TIM_TypeDef;
890 
895 typedef struct
896 {
897  __IO uint32_t SR;
898  __IO uint32_t DR;
899  __IO uint32_t BRR;
900  __IO uint32_t CR1;
901  __IO uint32_t CR2;
902  __IO uint32_t CR3;
903  __IO uint32_t GTPR;
904 } USART_TypeDef;
905 
910 typedef struct
911 {
912  __IO uint32_t CR;
913  __IO uint32_t CFR;
914  __IO uint32_t SR;
915 } WWDG_TypeDef;
916 
917 
922 typedef struct
923 {
924  __IO uint32_t CR;
925  __IO uint32_t SR;
926  __IO uint32_t DR;
927 } RNG_TypeDef;
928 
929 
933 typedef struct
934 {
935  __IO uint32_t GOTGCTL;
936  __IO uint32_t GOTGINT;
937  __IO uint32_t GAHBCFG;
938  __IO uint32_t GUSBCFG;
939  __IO uint32_t GRSTCTL;
940  __IO uint32_t GINTSTS;
941  __IO uint32_t GINTMSK;
942  __IO uint32_t GRXSTSR;
943  __IO uint32_t GRXSTSP;
944  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
945  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
946  __IO uint32_t HNPTXSTS;
947  uint32_t Reserved30[2]; /* Reserved 030h*/
948  __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
949  __IO uint32_t CID; /* User ID Register 03Ch*/
950  uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
951  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
952  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
953 }
954 USB_OTG_GlobalTypeDef;
955 
956 
960 typedef struct
961 {
962  __IO uint32_t DCFG; /* dev Configuration Register 800h*/
963  __IO uint32_t DCTL; /* dev Control Register 804h*/
964  __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
965  uint32_t Reserved0C; /* Reserved 80Ch*/
966  __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
967  __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
968  __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
969  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
970  uint32_t Reserved20; /* Reserved 820h*/
971  uint32_t Reserved9; /* Reserved 824h*/
972  __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
973  __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
974  __IO uint32_t DTHRCTL; /* dev thr 830h*/
975  __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
976  __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
977  __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
978  uint32_t Reserved40; /* dedicated EP mask 840h*/
979  __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
980  uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
981  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
982 }
983 USB_OTG_DeviceTypeDef;
984 
985 
989 typedef struct
990 {
991  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
992  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
993  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
994  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
995  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
996  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
997  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
998  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
999 }
1000 USB_OTG_INEndpointTypeDef;
1001 
1002 
1006 typedef struct
1007 {
1008  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1009  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1010  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1011  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1012  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1013  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1014  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1015 }
1016 USB_OTG_OUTEndpointTypeDef;
1017 
1018 
1022 typedef struct
1023 {
1024  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1025  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1026  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1027  uint32_t Reserved40C; /* Reserved 40Ch*/
1028  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1029  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1030  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1031 }
1032 USB_OTG_HostTypeDef;
1033 
1037 typedef struct
1038 {
1039  __IO uint32_t HCCHAR;
1040  __IO uint32_t HCSPLT;
1041  __IO uint32_t HCINT;
1042  __IO uint32_t HCINTMSK;
1043  __IO uint32_t HCTSIZ;
1044  __IO uint32_t HCDMA;
1045  uint32_t Reserved[2];
1046 }
1047 USB_OTG_HostChannelTypeDef;
1055 #define FLASH_BASE 0x08000000U
1056 #define CCMDATARAM_BASE 0x10000000U
1057 #define SRAM1_BASE 0x20000000U
1058 #define SRAM2_BASE 0x2001C000U
1059 #define SRAM3_BASE 0x20020000U
1060 #define PERIPH_BASE 0x40000000U
1061 #define BKPSRAM_BASE 0x40024000U
1062 #define FMC_R_BASE 0xA0000000U
1063 #define SRAM1_BB_BASE 0x22000000U
1064 #define SRAM2_BB_BASE 0x22380000U
1065 #define SRAM3_BB_BASE 0x22400000U
1066 #define PERIPH_BB_BASE 0x42000000U
1067 #define BKPSRAM_BB_BASE 0x42480000U
1068 #define FLASH_END 0x081FFFFFU
1069 #define CCMDATARAM_END 0x1000FFFFU
1071 /* Legacy defines */
1072 #define SRAM_BASE SRAM1_BASE
1073 #define SRAM_BB_BASE SRAM1_BB_BASE
1074 
1075 
1077 #define APB1PERIPH_BASE PERIPH_BASE
1078 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1079 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1080 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1081 
1083 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1084 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1085 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1086 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1087 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1088 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1089 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1090 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1091 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1092 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1093 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1094 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1095 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1096 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1097 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1098 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1099 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1100 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1101 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1102 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1103 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1104 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1105 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1106 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1107 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1108 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1109 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1110 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1111 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1112 
1114 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1115 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1116 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1117 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1118 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1119 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1120 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1121 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1122 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1123 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1124 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1125 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1126 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1127 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1128 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1129 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1130 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1131 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1132 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1133 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1134 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1135 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1136 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1137 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1138 
1140 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1141 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1142 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1143 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1144 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1145 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1146 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1147 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1148 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1149 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1150 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1151 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1152 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1153 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1154 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1155 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1156 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1157 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1158 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1159 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1160 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1161 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1162 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1163 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1164 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1165 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1166 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1167 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1168 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1169 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1170 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1171 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1172 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1173 #define ETH_MAC_BASE (ETH_BASE)
1174 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1175 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1176 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1177 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1178 
1180 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1181 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1182 
1184 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1185 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1186 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
1187 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
1188 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1189 
1190 /* Debug MCU registers base address */
1191 #define DBGMCU_BASE 0xE0042000U
1192 
1194 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1195 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1196 
1197 #define USB_OTG_GLOBAL_BASE 0x000U
1198 #define USB_OTG_DEVICE_BASE 0x800U
1199 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1200 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1201 #define USB_OTG_EP_REG_SIZE 0x20U
1202 #define USB_OTG_HOST_BASE 0x400U
1203 #define USB_OTG_HOST_PORT_BASE 0x440U
1204 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1205 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1206 #define USB_OTG_PCGCCTL_BASE 0xE00U
1207 #define USB_OTG_FIFO_BASE 0x1000U
1208 #define USB_OTG_FIFO_SIZE 0x1000U
1209 
1217 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1218 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1219 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1220 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1221 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1222 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1223 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1224 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1225 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1226 #define RTC ((RTC_TypeDef *) RTC_BASE)
1227 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1228 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1229 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1230 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1231 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1232 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1233 #define USART2 ((USART_TypeDef *) USART2_BASE)
1234 #define USART3 ((USART_TypeDef *) USART3_BASE)
1235 #define UART4 ((USART_TypeDef *) UART4_BASE)
1236 #define UART5 ((USART_TypeDef *) UART5_BASE)
1237 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1238 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1239 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1240 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1241 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1242 #define PWR ((PWR_TypeDef *) PWR_BASE)
1243 #define DAC ((DAC_TypeDef *) DAC_BASE)
1244 #define UART7 ((USART_TypeDef *) UART7_BASE)
1245 #define UART8 ((USART_TypeDef *) UART8_BASE)
1246 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1247 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1248 #define USART1 ((USART_TypeDef *) USART1_BASE)
1249 #define USART6 ((USART_TypeDef *) USART6_BASE)
1250 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1251 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1252 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1253 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1254 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1255 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1256 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1257 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1258 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1259 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1260 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1261 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1262 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1263 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1264 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1265 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1266 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1267 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1268 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1269 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1270 
1271 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1272 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1273 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1274 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1275 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1276 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1277 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1278 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1279 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1280 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1281 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1282 #define CRC ((CRC_TypeDef *) CRC_BASE)
1283 #define RCC ((RCC_TypeDef *) RCC_BASE)
1284 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1285 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1286 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1287 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1288 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1289 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1290 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1291 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1292 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1293 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1294 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1295 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1296 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1297 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1298 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1299 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1300 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1301 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1302 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1303 #define ETH ((ETH_TypeDef *) ETH_BASE)
1304 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1305 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1306 #define RNG ((RNG_TypeDef *) RNG_BASE)
1307 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1308 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1309 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1310 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1311 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1312 
1313 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1314 
1315 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1316 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1317 
1330 /******************************************************************************/
1331 /* Peripheral Registers_Bits_Definition */
1332 /******************************************************************************/
1333 
1334 /******************************************************************************/
1335 /* */
1336 /* Analog to Digital Converter */
1337 /* */
1338 /******************************************************************************/
1339 /******************** Bit definition for ADC_SR register ********************/
1340 #define ADC_SR_AWD 0x00000001U
1341 #define ADC_SR_EOC 0x00000002U
1342 #define ADC_SR_JEOC 0x00000004U
1343 #define ADC_SR_JSTRT 0x00000008U
1344 #define ADC_SR_STRT 0x00000010U
1345 #define ADC_SR_OVR 0x00000020U
1347 /******************* Bit definition for ADC_CR1 register ********************/
1348 #define ADC_CR1_AWDCH 0x0000001FU
1349 #define ADC_CR1_AWDCH_0 0x00000001U
1350 #define ADC_CR1_AWDCH_1 0x00000002U
1351 #define ADC_CR1_AWDCH_2 0x00000004U
1352 #define ADC_CR1_AWDCH_3 0x00000008U
1353 #define ADC_CR1_AWDCH_4 0x00000010U
1354 #define ADC_CR1_EOCIE 0x00000020U
1355 #define ADC_CR1_AWDIE 0x00000040U
1356 #define ADC_CR1_JEOCIE 0x00000080U
1357 #define ADC_CR1_SCAN 0x00000100U
1358 #define ADC_CR1_AWDSGL 0x00000200U
1359 #define ADC_CR1_JAUTO 0x00000400U
1360 #define ADC_CR1_DISCEN 0x00000800U
1361 #define ADC_CR1_JDISCEN 0x00001000U
1362 #define ADC_CR1_DISCNUM 0x0000E000U
1363 #define ADC_CR1_DISCNUM_0 0x00002000U
1364 #define ADC_CR1_DISCNUM_1 0x00004000U
1365 #define ADC_CR1_DISCNUM_2 0x00008000U
1366 #define ADC_CR1_JAWDEN 0x00400000U
1367 #define ADC_CR1_AWDEN 0x00800000U
1368 #define ADC_CR1_RES 0x03000000U
1369 #define ADC_CR1_RES_0 0x01000000U
1370 #define ADC_CR1_RES_1 0x02000000U
1371 #define ADC_CR1_OVRIE 0x04000000U
1373 /******************* Bit definition for ADC_CR2 register ********************/
1374 #define ADC_CR2_ADON 0x00000001U
1375 #define ADC_CR2_CONT 0x00000002U
1376 #define ADC_CR2_DMA 0x00000100U
1377 #define ADC_CR2_DDS 0x00000200U
1378 #define ADC_CR2_EOCS 0x00000400U
1379 #define ADC_CR2_ALIGN 0x00000800U
1380 #define ADC_CR2_JEXTSEL 0x000F0000U
1381 #define ADC_CR2_JEXTSEL_0 0x00010000U
1382 #define ADC_CR2_JEXTSEL_1 0x00020000U
1383 #define ADC_CR2_JEXTSEL_2 0x00040000U
1384 #define ADC_CR2_JEXTSEL_3 0x00080000U
1385 #define ADC_CR2_JEXTEN 0x00300000U
1386 #define ADC_CR2_JEXTEN_0 0x00100000U
1387 #define ADC_CR2_JEXTEN_1 0x00200000U
1388 #define ADC_CR2_JSWSTART 0x00400000U
1389 #define ADC_CR2_EXTSEL 0x0F000000U
1390 #define ADC_CR2_EXTSEL_0 0x01000000U
1391 #define ADC_CR2_EXTSEL_1 0x02000000U
1392 #define ADC_CR2_EXTSEL_2 0x04000000U
1393 #define ADC_CR2_EXTSEL_3 0x08000000U
1394 #define ADC_CR2_EXTEN 0x30000000U
1395 #define ADC_CR2_EXTEN_0 0x10000000U
1396 #define ADC_CR2_EXTEN_1 0x20000000U
1397 #define ADC_CR2_SWSTART 0x40000000U
1399 /****************** Bit definition for ADC_SMPR1 register *******************/
1400 #define ADC_SMPR1_SMP10 0x00000007U
1401 #define ADC_SMPR1_SMP10_0 0x00000001U
1402 #define ADC_SMPR1_SMP10_1 0x00000002U
1403 #define ADC_SMPR1_SMP10_2 0x00000004U
1404 #define ADC_SMPR1_SMP11 0x00000038U
1405 #define ADC_SMPR1_SMP11_0 0x00000008U
1406 #define ADC_SMPR1_SMP11_1 0x00000010U
1407 #define ADC_SMPR1_SMP11_2 0x00000020U
1408 #define ADC_SMPR1_SMP12 0x000001C0U
1409 #define ADC_SMPR1_SMP12_0 0x00000040U
1410 #define ADC_SMPR1_SMP12_1 0x00000080U
1411 #define ADC_SMPR1_SMP12_2 0x00000100U
1412 #define ADC_SMPR1_SMP13 0x00000E00U
1413 #define ADC_SMPR1_SMP13_0 0x00000200U
1414 #define ADC_SMPR1_SMP13_1 0x00000400U
1415 #define ADC_SMPR1_SMP13_2 0x00000800U
1416 #define ADC_SMPR1_SMP14 0x00007000U
1417 #define ADC_SMPR1_SMP14_0 0x00001000U
1418 #define ADC_SMPR1_SMP14_1 0x00002000U
1419 #define ADC_SMPR1_SMP14_2 0x00004000U
1420 #define ADC_SMPR1_SMP15 0x00038000U
1421 #define ADC_SMPR1_SMP15_0 0x00008000U
1422 #define ADC_SMPR1_SMP15_1 0x00010000U
1423 #define ADC_SMPR1_SMP15_2 0x00020000U
1424 #define ADC_SMPR1_SMP16 0x001C0000U
1425 #define ADC_SMPR1_SMP16_0 0x00040000U
1426 #define ADC_SMPR1_SMP16_1 0x00080000U
1427 #define ADC_SMPR1_SMP16_2 0x00100000U
1428 #define ADC_SMPR1_SMP17 0x00E00000U
1429 #define ADC_SMPR1_SMP17_0 0x00200000U
1430 #define ADC_SMPR1_SMP17_1 0x00400000U
1431 #define ADC_SMPR1_SMP17_2 0x00800000U
1432 #define ADC_SMPR1_SMP18 0x07000000U
1433 #define ADC_SMPR1_SMP18_0 0x01000000U
1434 #define ADC_SMPR1_SMP18_1 0x02000000U
1435 #define ADC_SMPR1_SMP18_2 0x04000000U
1437 /****************** Bit definition for ADC_SMPR2 register *******************/
1438 #define ADC_SMPR2_SMP0 0x00000007U
1439 #define ADC_SMPR2_SMP0_0 0x00000001U
1440 #define ADC_SMPR2_SMP0_1 0x00000002U
1441 #define ADC_SMPR2_SMP0_2 0x00000004U
1442 #define ADC_SMPR2_SMP1 0x00000038U
1443 #define ADC_SMPR2_SMP1_0 0x00000008U
1444 #define ADC_SMPR2_SMP1_1 0x00000010U
1445 #define ADC_SMPR2_SMP1_2 0x00000020U
1446 #define ADC_SMPR2_SMP2 0x000001C0U
1447 #define ADC_SMPR2_SMP2_0 0x00000040U
1448 #define ADC_SMPR2_SMP2_1 0x00000080U
1449 #define ADC_SMPR2_SMP2_2 0x00000100U
1450 #define ADC_SMPR2_SMP3 0x00000E00U
1451 #define ADC_SMPR2_SMP3_0 0x00000200U
1452 #define ADC_SMPR2_SMP3_1 0x00000400U
1453 #define ADC_SMPR2_SMP3_2 0x00000800U
1454 #define ADC_SMPR2_SMP4 0x00007000U
1455 #define ADC_SMPR2_SMP4_0 0x00001000U
1456 #define ADC_SMPR2_SMP4_1 0x00002000U
1457 #define ADC_SMPR2_SMP4_2 0x00004000U
1458 #define ADC_SMPR2_SMP5 0x00038000U
1459 #define ADC_SMPR2_SMP5_0 0x00008000U
1460 #define ADC_SMPR2_SMP5_1 0x00010000U
1461 #define ADC_SMPR2_SMP5_2 0x00020000U
1462 #define ADC_SMPR2_SMP6 0x001C0000U
1463 #define ADC_SMPR2_SMP6_0 0x00040000U
1464 #define ADC_SMPR2_SMP6_1 0x00080000U
1465 #define ADC_SMPR2_SMP6_2 0x00100000U
1466 #define ADC_SMPR2_SMP7 0x00E00000U
1467 #define ADC_SMPR2_SMP7_0 0x00200000U
1468 #define ADC_SMPR2_SMP7_1 0x00400000U
1469 #define ADC_SMPR2_SMP7_2 0x00800000U
1470 #define ADC_SMPR2_SMP8 0x07000000U
1471 #define ADC_SMPR2_SMP8_0 0x01000000U
1472 #define ADC_SMPR2_SMP8_1 0x02000000U
1473 #define ADC_SMPR2_SMP8_2 0x04000000U
1474 #define ADC_SMPR2_SMP9 0x38000000U
1475 #define ADC_SMPR2_SMP9_0 0x08000000U
1476 #define ADC_SMPR2_SMP9_1 0x10000000U
1477 #define ADC_SMPR2_SMP9_2 0x20000000U
1479 /****************** Bit definition for ADC_JOFR1 register *******************/
1480 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1482 /****************** Bit definition for ADC_JOFR2 register *******************/
1483 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1485 /****************** Bit definition for ADC_JOFR3 register *******************/
1486 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1488 /****************** Bit definition for ADC_JOFR4 register *******************/
1489 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1491 /******************* Bit definition for ADC_HTR register ********************/
1492 #define ADC_HTR_HT 0x0FFFU
1494 /******************* Bit definition for ADC_LTR register ********************/
1495 #define ADC_LTR_LT 0x0FFFU
1497 /******************* Bit definition for ADC_SQR1 register *******************/
1498 #define ADC_SQR1_SQ13 0x0000001FU
1499 #define ADC_SQR1_SQ13_0 0x00000001U
1500 #define ADC_SQR1_SQ13_1 0x00000002U
1501 #define ADC_SQR1_SQ13_2 0x00000004U
1502 #define ADC_SQR1_SQ13_3 0x00000008U
1503 #define ADC_SQR1_SQ13_4 0x00000010U
1504 #define ADC_SQR1_SQ14 0x000003E0U
1505 #define ADC_SQR1_SQ14_0 0x00000020U
1506 #define ADC_SQR1_SQ14_1 0x00000040U
1507 #define ADC_SQR1_SQ14_2 0x00000080U
1508 #define ADC_SQR1_SQ14_3 0x00000100U
1509 #define ADC_SQR1_SQ14_4 0x00000200U
1510 #define ADC_SQR1_SQ15 0x00007C00U
1511 #define ADC_SQR1_SQ15_0 0x00000400U
1512 #define ADC_SQR1_SQ15_1 0x00000800U
1513 #define ADC_SQR1_SQ15_2 0x00001000U
1514 #define ADC_SQR1_SQ15_3 0x00002000U
1515 #define ADC_SQR1_SQ15_4 0x00004000U
1516 #define ADC_SQR1_SQ16 0x000F8000U
1517 #define ADC_SQR1_SQ16_0 0x00008000U
1518 #define ADC_SQR1_SQ16_1 0x00010000U
1519 #define ADC_SQR1_SQ16_2 0x00020000U
1520 #define ADC_SQR1_SQ16_3 0x00040000U
1521 #define ADC_SQR1_SQ16_4 0x00080000U
1522 #define ADC_SQR1_L 0x00F00000U
1523 #define ADC_SQR1_L_0 0x00100000U
1524 #define ADC_SQR1_L_1 0x00200000U
1525 #define ADC_SQR1_L_2 0x00400000U
1526 #define ADC_SQR1_L_3 0x00800000U
1528 /******************* Bit definition for ADC_SQR2 register *******************/
1529 #define ADC_SQR2_SQ7 0x0000001FU
1530 #define ADC_SQR2_SQ7_0 0x00000001U
1531 #define ADC_SQR2_SQ7_1 0x00000002U
1532 #define ADC_SQR2_SQ7_2 0x00000004U
1533 #define ADC_SQR2_SQ7_3 0x00000008U
1534 #define ADC_SQR2_SQ7_4 0x00000010U
1535 #define ADC_SQR2_SQ8 0x000003E0U
1536 #define ADC_SQR2_SQ8_0 0x00000020U
1537 #define ADC_SQR2_SQ8_1 0x00000040U
1538 #define ADC_SQR2_SQ8_2 0x00000080U
1539 #define ADC_SQR2_SQ8_3 0x00000100U
1540 #define ADC_SQR2_SQ8_4 0x00000200U
1541 #define ADC_SQR2_SQ9 0x00007C00U
1542 #define ADC_SQR2_SQ9_0 0x00000400U
1543 #define ADC_SQR2_SQ9_1 0x00000800U
1544 #define ADC_SQR2_SQ9_2 0x00001000U
1545 #define ADC_SQR2_SQ9_3 0x00002000U
1546 #define ADC_SQR2_SQ9_4 0x00004000U
1547 #define ADC_SQR2_SQ10 0x000F8000U
1548 #define ADC_SQR2_SQ10_0 0x00008000U
1549 #define ADC_SQR2_SQ10_1 0x00010000U
1550 #define ADC_SQR2_SQ10_2 0x00020000U
1551 #define ADC_SQR2_SQ10_3 0x00040000U
1552 #define ADC_SQR2_SQ10_4 0x00080000U
1553 #define ADC_SQR2_SQ11 0x01F00000U
1554 #define ADC_SQR2_SQ11_0 0x00100000U
1555 #define ADC_SQR2_SQ11_1 0x00200000U
1556 #define ADC_SQR2_SQ11_2 0x00400000U
1557 #define ADC_SQR2_SQ11_3 0x00800000U
1558 #define ADC_SQR2_SQ11_4 0x01000000U
1559 #define ADC_SQR2_SQ12 0x3E000000U
1560 #define ADC_SQR2_SQ12_0 0x02000000U
1561 #define ADC_SQR2_SQ12_1 0x04000000U
1562 #define ADC_SQR2_SQ12_2 0x08000000U
1563 #define ADC_SQR2_SQ12_3 0x10000000U
1564 #define ADC_SQR2_SQ12_4 0x20000000U
1566 /******************* Bit definition for ADC_SQR3 register *******************/
1567 #define ADC_SQR3_SQ1 0x0000001FU
1568 #define ADC_SQR3_SQ1_0 0x00000001U
1569 #define ADC_SQR3_SQ1_1 0x00000002U
1570 #define ADC_SQR3_SQ1_2 0x00000004U
1571 #define ADC_SQR3_SQ1_3 0x00000008U
1572 #define ADC_SQR3_SQ1_4 0x00000010U
1573 #define ADC_SQR3_SQ2 0x000003E0U
1574 #define ADC_SQR3_SQ2_0 0x00000020U
1575 #define ADC_SQR3_SQ2_1 0x00000040U
1576 #define ADC_SQR3_SQ2_2 0x00000080U
1577 #define ADC_SQR3_SQ2_3 0x00000100U
1578 #define ADC_SQR3_SQ2_4 0x00000200U
1579 #define ADC_SQR3_SQ3 0x00007C00U
1580 #define ADC_SQR3_SQ3_0 0x00000400U
1581 #define ADC_SQR3_SQ3_1 0x00000800U
1582 #define ADC_SQR3_SQ3_2 0x00001000U
1583 #define ADC_SQR3_SQ3_3 0x00002000U
1584 #define ADC_SQR3_SQ3_4 0x00004000U
1585 #define ADC_SQR3_SQ4 0x000F8000U
1586 #define ADC_SQR3_SQ4_0 0x00008000U
1587 #define ADC_SQR3_SQ4_1 0x00010000U
1588 #define ADC_SQR3_SQ4_2 0x00020000U
1589 #define ADC_SQR3_SQ4_3 0x00040000U
1590 #define ADC_SQR3_SQ4_4 0x00080000U
1591 #define ADC_SQR3_SQ5 0x01F00000U
1592 #define ADC_SQR3_SQ5_0 0x00100000U
1593 #define ADC_SQR3_SQ5_1 0x00200000U
1594 #define ADC_SQR3_SQ5_2 0x00400000U
1595 #define ADC_SQR3_SQ5_3 0x00800000U
1596 #define ADC_SQR3_SQ5_4 0x01000000U
1597 #define ADC_SQR3_SQ6 0x3E000000U
1598 #define ADC_SQR3_SQ6_0 0x02000000U
1599 #define ADC_SQR3_SQ6_1 0x04000000U
1600 #define ADC_SQR3_SQ6_2 0x08000000U
1601 #define ADC_SQR3_SQ6_3 0x10000000U
1602 #define ADC_SQR3_SQ6_4 0x20000000U
1604 /******************* Bit definition for ADC_JSQR register *******************/
1605 #define ADC_JSQR_JSQ1 0x0000001FU
1606 #define ADC_JSQR_JSQ1_0 0x00000001U
1607 #define ADC_JSQR_JSQ1_1 0x00000002U
1608 #define ADC_JSQR_JSQ1_2 0x00000004U
1609 #define ADC_JSQR_JSQ1_3 0x00000008U
1610 #define ADC_JSQR_JSQ1_4 0x00000010U
1611 #define ADC_JSQR_JSQ2 0x000003E0U
1612 #define ADC_JSQR_JSQ2_0 0x00000020U
1613 #define ADC_JSQR_JSQ2_1 0x00000040U
1614 #define ADC_JSQR_JSQ2_2 0x00000080U
1615 #define ADC_JSQR_JSQ2_3 0x00000100U
1616 #define ADC_JSQR_JSQ2_4 0x00000200U
1617 #define ADC_JSQR_JSQ3 0x00007C00U
1618 #define ADC_JSQR_JSQ3_0 0x00000400U
1619 #define ADC_JSQR_JSQ3_1 0x00000800U
1620 #define ADC_JSQR_JSQ3_2 0x00001000U
1621 #define ADC_JSQR_JSQ3_3 0x00002000U
1622 #define ADC_JSQR_JSQ3_4 0x00004000U
1623 #define ADC_JSQR_JSQ4 0x000F8000U
1624 #define ADC_JSQR_JSQ4_0 0x00008000U
1625 #define ADC_JSQR_JSQ4_1 0x00010000U
1626 #define ADC_JSQR_JSQ4_2 0x00020000U
1627 #define ADC_JSQR_JSQ4_3 0x00040000U
1628 #define ADC_JSQR_JSQ4_4 0x00080000U
1629 #define ADC_JSQR_JL 0x00300000U
1630 #define ADC_JSQR_JL_0 0x00100000U
1631 #define ADC_JSQR_JL_1 0x00200000U
1633 /******************* Bit definition for ADC_JDR1 register *******************/
1634 #define ADC_JDR1_JDATA 0xFFFFU
1636 /******************* Bit definition for ADC_JDR2 register *******************/
1637 #define ADC_JDR2_JDATA 0xFFFFU
1639 /******************* Bit definition for ADC_JDR3 register *******************/
1640 #define ADC_JDR3_JDATA 0xFFFFU
1642 /******************* Bit definition for ADC_JDR4 register *******************/
1643 #define ADC_JDR4_JDATA 0xFFFFU
1645 /******************** Bit definition for ADC_DR register ********************/
1646 #define ADC_DR_DATA 0x0000FFFFU
1647 #define ADC_DR_ADC2DATA 0xFFFF0000U
1649 /******************* Bit definition for ADC_CSR register ********************/
1650 #define ADC_CSR_AWD1 0x00000001U
1651 #define ADC_CSR_EOC1 0x00000002U
1652 #define ADC_CSR_JEOC1 0x00000004U
1653 #define ADC_CSR_JSTRT1 0x00000008U
1654 #define ADC_CSR_STRT1 0x00000010U
1655 #define ADC_CSR_OVR1 0x00000020U
1656 #define ADC_CSR_AWD2 0x00000100U
1657 #define ADC_CSR_EOC2 0x00000200U
1658 #define ADC_CSR_JEOC2 0x00000400U
1659 #define ADC_CSR_JSTRT2 0x00000800U
1660 #define ADC_CSR_STRT2 0x00001000U
1661 #define ADC_CSR_OVR2 0x00002000U
1662 #define ADC_CSR_AWD3 0x00010000U
1663 #define ADC_CSR_EOC3 0x00020000U
1664 #define ADC_CSR_JEOC3 0x00040000U
1665 #define ADC_CSR_JSTRT3 0x00080000U
1666 #define ADC_CSR_STRT3 0x00100000U
1667 #define ADC_CSR_OVR3 0x00200000U
1669 /* Legacy defines */
1670 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1671 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1672 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1673 
1674 /******************* Bit definition for ADC_CCR register ********************/
1675 #define ADC_CCR_MULTI 0x0000001FU
1676 #define ADC_CCR_MULTI_0 0x00000001U
1677 #define ADC_CCR_MULTI_1 0x00000002U
1678 #define ADC_CCR_MULTI_2 0x00000004U
1679 #define ADC_CCR_MULTI_3 0x00000008U
1680 #define ADC_CCR_MULTI_4 0x00000010U
1681 #define ADC_CCR_DELAY 0x00000F00U
1682 #define ADC_CCR_DELAY_0 0x00000100U
1683 #define ADC_CCR_DELAY_1 0x00000200U
1684 #define ADC_CCR_DELAY_2 0x00000400U
1685 #define ADC_CCR_DELAY_3 0x00000800U
1686 #define ADC_CCR_DDS 0x00002000U
1687 #define ADC_CCR_DMA 0x0000C000U
1688 #define ADC_CCR_DMA_0 0x00004000U
1689 #define ADC_CCR_DMA_1 0x00008000U
1690 #define ADC_CCR_ADCPRE 0x00030000U
1691 #define ADC_CCR_ADCPRE_0 0x00010000U
1692 #define ADC_CCR_ADCPRE_1 0x00020000U
1693 #define ADC_CCR_VBATE 0x00400000U
1694 #define ADC_CCR_TSVREFE 0x00800000U
1696 /******************* Bit definition for ADC_CDR register ********************/
1697 #define ADC_CDR_DATA1 0x0000FFFFU
1698 #define ADC_CDR_DATA2 0xFFFF0000U
1700 /******************************************************************************/
1701 /* */
1702 /* Controller Area Network */
1703 /* */
1704 /******************************************************************************/
1706 /******************* Bit definition for CAN_MCR register ********************/
1707 #define CAN_MCR_INRQ 0x00000001U
1708 #define CAN_MCR_SLEEP 0x00000002U
1709 #define CAN_MCR_TXFP 0x00000004U
1710 #define CAN_MCR_RFLM 0x00000008U
1711 #define CAN_MCR_NART 0x00000010U
1712 #define CAN_MCR_AWUM 0x00000020U
1713 #define CAN_MCR_ABOM 0x00000040U
1714 #define CAN_MCR_TTCM 0x00000080U
1715 #define CAN_MCR_RESET 0x00008000U
1716 #define CAN_MCR_DBF 0x00010000U
1717 /******************* Bit definition for CAN_MSR register ********************/
1718 #define CAN_MSR_INAK 0x0001U
1719 #define CAN_MSR_SLAK 0x0002U
1720 #define CAN_MSR_ERRI 0x0004U
1721 #define CAN_MSR_WKUI 0x0008U
1722 #define CAN_MSR_SLAKI 0x0010U
1723 #define CAN_MSR_TXM 0x0100U
1724 #define CAN_MSR_RXM 0x0200U
1725 #define CAN_MSR_SAMP 0x0400U
1726 #define CAN_MSR_RX 0x0800U
1728 /******************* Bit definition for CAN_TSR register ********************/
1729 #define CAN_TSR_RQCP0 0x00000001U
1730 #define CAN_TSR_TXOK0 0x00000002U
1731 #define CAN_TSR_ALST0 0x00000004U
1732 #define CAN_TSR_TERR0 0x00000008U
1733 #define CAN_TSR_ABRQ0 0x00000080U
1734 #define CAN_TSR_RQCP1 0x00000100U
1735 #define CAN_TSR_TXOK1 0x00000200U
1736 #define CAN_TSR_ALST1 0x00000400U
1737 #define CAN_TSR_TERR1 0x00000800U
1738 #define CAN_TSR_ABRQ1 0x00008000U
1739 #define CAN_TSR_RQCP2 0x00010000U
1740 #define CAN_TSR_TXOK2 0x00020000U
1741 #define CAN_TSR_ALST2 0x00040000U
1742 #define CAN_TSR_TERR2 0x00080000U
1743 #define CAN_TSR_ABRQ2 0x00800000U
1744 #define CAN_TSR_CODE 0x03000000U
1746 #define CAN_TSR_TME 0x1C000000U
1747 #define CAN_TSR_TME0 0x04000000U
1748 #define CAN_TSR_TME1 0x08000000U
1749 #define CAN_TSR_TME2 0x10000000U
1751 #define CAN_TSR_LOW 0xE0000000U
1752 #define CAN_TSR_LOW0 0x20000000U
1753 #define CAN_TSR_LOW1 0x40000000U
1754 #define CAN_TSR_LOW2 0x80000000U
1756 /******************* Bit definition for CAN_RF0R register *******************/
1757 #define CAN_RF0R_FMP0 0x03U
1758 #define CAN_RF0R_FULL0 0x08U
1759 #define CAN_RF0R_FOVR0 0x10U
1760 #define CAN_RF0R_RFOM0 0x20U
1762 /******************* Bit definition for CAN_RF1R register *******************/
1763 #define CAN_RF1R_FMP1 0x03U
1764 #define CAN_RF1R_FULL1 0x08U
1765 #define CAN_RF1R_FOVR1 0x10U
1766 #define CAN_RF1R_RFOM1 0x20U
1768 /******************** Bit definition for CAN_IER register *******************/
1769 #define CAN_IER_TMEIE 0x00000001U
1770 #define CAN_IER_FMPIE0 0x00000002U
1771 #define CAN_IER_FFIE0 0x00000004U
1772 #define CAN_IER_FOVIE0 0x00000008U
1773 #define CAN_IER_FMPIE1 0x00000010U
1774 #define CAN_IER_FFIE1 0x00000020U
1775 #define CAN_IER_FOVIE1 0x00000040U
1776 #define CAN_IER_EWGIE 0x00000100U
1777 #define CAN_IER_EPVIE 0x00000200U
1778 #define CAN_IER_BOFIE 0x00000400U
1779 #define CAN_IER_LECIE 0x00000800U
1780 #define CAN_IER_ERRIE 0x00008000U
1781 #define CAN_IER_WKUIE 0x00010000U
1782 #define CAN_IER_SLKIE 0x00020000U
1783 #define CAN_IER_EWGIE 0x00000100U
1784 #define CAN_IER_EPVIE 0x00000200U
1785 #define CAN_IER_BOFIE 0x00000400U
1786 #define CAN_IER_LECIE 0x00000800U
1787 #define CAN_IER_ERRIE 0x00008000U
1790 /******************** Bit definition for CAN_ESR register *******************/
1791 #define CAN_ESR_EWGF 0x00000001U
1792 #define CAN_ESR_EPVF 0x00000002U
1793 #define CAN_ESR_BOFF 0x00000004U
1795 #define CAN_ESR_LEC 0x00000070U
1796 #define CAN_ESR_LEC_0 0x00000010U
1797 #define CAN_ESR_LEC_1 0x00000020U
1798 #define CAN_ESR_LEC_2 0x00000040U
1800 #define CAN_ESR_TEC 0x00FF0000U
1801 #define CAN_ESR_REC 0xFF000000U
1803 /******************* Bit definition for CAN_BTR register ********************/
1804 #define CAN_BTR_BRP 0x000003FFU
1805 #define CAN_BTR_TS1 0x000F0000U
1806 #define CAN_BTR_TS1_0 0x00010000U
1807 #define CAN_BTR_TS1_1 0x00020000U
1808 #define CAN_BTR_TS1_2 0x00040000U
1809 #define CAN_BTR_TS1_3 0x00080000U
1810 #define CAN_BTR_TS2 0x00700000U
1811 #define CAN_BTR_TS2_0 0x00100000U
1812 #define CAN_BTR_TS2_1 0x00200000U
1813 #define CAN_BTR_TS2_2 0x00400000U
1814 #define CAN_BTR_SJW 0x03000000U
1815 #define CAN_BTR_SJW_0 0x01000000U
1816 #define CAN_BTR_SJW_1 0x02000000U
1817 #define CAN_BTR_LBKM 0x40000000U
1818 #define CAN_BTR_SILM 0x80000000U
1822 /****************** Bit definition for CAN_TI0R register ********************/
1823 #define CAN_TI0R_TXRQ 0x00000001U
1824 #define CAN_TI0R_RTR 0x00000002U
1825 #define CAN_TI0R_IDE 0x00000004U
1826 #define CAN_TI0R_EXID 0x001FFFF8U
1827 #define CAN_TI0R_STID 0xFFE00000U
1829 /****************** Bit definition for CAN_TDT0R register *******************/
1830 #define CAN_TDT0R_DLC 0x0000000FU
1831 #define CAN_TDT0R_TGT 0x00000100U
1832 #define CAN_TDT0R_TIME 0xFFFF0000U
1834 /****************** Bit definition for CAN_TDL0R register *******************/
1835 #define CAN_TDL0R_DATA0 0x000000FFU
1836 #define CAN_TDL0R_DATA1 0x0000FF00U
1837 #define CAN_TDL0R_DATA2 0x00FF0000U
1838 #define CAN_TDL0R_DATA3 0xFF000000U
1840 /****************** Bit definition for CAN_TDH0R register *******************/
1841 #define CAN_TDH0R_DATA4 0x000000FFU
1842 #define CAN_TDH0R_DATA5 0x0000FF00U
1843 #define CAN_TDH0R_DATA6 0x00FF0000U
1844 #define CAN_TDH0R_DATA7 0xFF000000U
1846 /******************* Bit definition for CAN_TI1R register *******************/
1847 #define CAN_TI1R_TXRQ 0x00000001U
1848 #define CAN_TI1R_RTR 0x00000002U
1849 #define CAN_TI1R_IDE 0x00000004U
1850 #define CAN_TI1R_EXID 0x001FFFF8U
1851 #define CAN_TI1R_STID 0xFFE00000U
1853 /******************* Bit definition for CAN_TDT1R register ******************/
1854 #define CAN_TDT1R_DLC 0x0000000FU
1855 #define CAN_TDT1R_TGT 0x00000100U
1856 #define CAN_TDT1R_TIME 0xFFFF0000U
1858 /******************* Bit definition for CAN_TDL1R register ******************/
1859 #define CAN_TDL1R_DATA0 0x000000FFU
1860 #define CAN_TDL1R_DATA1 0x0000FF00U
1861 #define CAN_TDL1R_DATA2 0x00FF0000U
1862 #define CAN_TDL1R_DATA3 0xFF000000U
1864 /******************* Bit definition for CAN_TDH1R register ******************/
1865 #define CAN_TDH1R_DATA4 0x000000FFU
1866 #define CAN_TDH1R_DATA5 0x0000FF00U
1867 #define CAN_TDH1R_DATA6 0x00FF0000U
1868 #define CAN_TDH1R_DATA7 0xFF000000U
1870 /******************* Bit definition for CAN_TI2R register *******************/
1871 #define CAN_TI2R_TXRQ 0x00000001U
1872 #define CAN_TI2R_RTR 0x00000002U
1873 #define CAN_TI2R_IDE 0x00000004U
1874 #define CAN_TI2R_EXID 0x001FFFF8U
1875 #define CAN_TI2R_STID 0xFFE00000U
1877 /******************* Bit definition for CAN_TDT2R register ******************/
1878 #define CAN_TDT2R_DLC 0x0000000FU
1879 #define CAN_TDT2R_TGT 0x00000100U
1880 #define CAN_TDT2R_TIME 0xFFFF0000U
1882 /******************* Bit definition for CAN_TDL2R register ******************/
1883 #define CAN_TDL2R_DATA0 0x000000FFU
1884 #define CAN_TDL2R_DATA1 0x0000FF00U
1885 #define CAN_TDL2R_DATA2 0x00FF0000U
1886 #define CAN_TDL2R_DATA3 0xFF000000U
1888 /******************* Bit definition for CAN_TDH2R register ******************/
1889 #define CAN_TDH2R_DATA4 0x000000FFU
1890 #define CAN_TDH2R_DATA5 0x0000FF00U
1891 #define CAN_TDH2R_DATA6 0x00FF0000U
1892 #define CAN_TDH2R_DATA7 0xFF000000U
1894 /******************* Bit definition for CAN_RI0R register *******************/
1895 #define CAN_RI0R_RTR 0x00000002U
1896 #define CAN_RI0R_IDE 0x00000004U
1897 #define CAN_RI0R_EXID 0x001FFFF8U
1898 #define CAN_RI0R_STID 0xFFE00000U
1900 /******************* Bit definition for CAN_RDT0R register ******************/
1901 #define CAN_RDT0R_DLC 0x0000000FU
1902 #define CAN_RDT0R_FMI 0x0000FF00U
1903 #define CAN_RDT0R_TIME 0xFFFF0000U
1905 /******************* Bit definition for CAN_RDL0R register ******************/
1906 #define CAN_RDL0R_DATA0 0x000000FFU
1907 #define CAN_RDL0R_DATA1 0x0000FF00U
1908 #define CAN_RDL0R_DATA2 0x00FF0000U
1909 #define CAN_RDL0R_DATA3 0xFF000000U
1911 /******************* Bit definition for CAN_RDH0R register ******************/
1912 #define CAN_RDH0R_DATA4 0x000000FFU
1913 #define CAN_RDH0R_DATA5 0x0000FF00U
1914 #define CAN_RDH0R_DATA6 0x00FF0000U
1915 #define CAN_RDH0R_DATA7 0xFF000000U
1917 /******************* Bit definition for CAN_RI1R register *******************/
1918 #define CAN_RI1R_RTR 0x00000002U
1919 #define CAN_RI1R_IDE 0x00000004U
1920 #define CAN_RI1R_EXID 0x001FFFF8U
1921 #define CAN_RI1R_STID 0xFFE00000U
1923 /******************* Bit definition for CAN_RDT1R register ******************/
1924 #define CAN_RDT1R_DLC 0x0000000FU
1925 #define CAN_RDT1R_FMI 0x0000FF00U
1926 #define CAN_RDT1R_TIME 0xFFFF0000U
1928 /******************* Bit definition for CAN_RDL1R register ******************/
1929 #define CAN_RDL1R_DATA0 0x000000FFU
1930 #define CAN_RDL1R_DATA1 0x0000FF00U
1931 #define CAN_RDL1R_DATA2 0x00FF0000U
1932 #define CAN_RDL1R_DATA3 0xFF000000U
1934 /******************* Bit definition for CAN_RDH1R register ******************/
1935 #define CAN_RDH1R_DATA4 0x000000FFU
1936 #define CAN_RDH1R_DATA5 0x0000FF00U
1937 #define CAN_RDH1R_DATA6 0x00FF0000U
1938 #define CAN_RDH1R_DATA7 0xFF000000U
1941 /******************* Bit definition for CAN_FMR register ********************/
1942 #define CAN_FMR_FINIT 0x01U
1943 #define CAN_FMR_CAN2SB 0x00003F00U
1945 /******************* Bit definition for CAN_FM1R register *******************/
1946 #define CAN_FM1R_FBM 0x0FFFFFFFU
1947 #define CAN_FM1R_FBM0 0x00000001U
1948 #define CAN_FM1R_FBM1 0x00000002U
1949 #define CAN_FM1R_FBM2 0x00000004U
1950 #define CAN_FM1R_FBM3 0x00000008U
1951 #define CAN_FM1R_FBM4 0x00000010U
1952 #define CAN_FM1R_FBM5 0x00000020U
1953 #define CAN_FM1R_FBM6 0x00000040U
1954 #define CAN_FM1R_FBM7 0x00000080U
1955 #define CAN_FM1R_FBM8 0x00000100U
1956 #define CAN_FM1R_FBM9 0x00000200U
1957 #define CAN_FM1R_FBM10 0x00000400U
1958 #define CAN_FM1R_FBM11 0x00000800U
1959 #define CAN_FM1R_FBM12 0x00001000U
1960 #define CAN_FM1R_FBM13 0x00002000U
1961 #define CAN_FM1R_FBM14 0x00004000U
1962 #define CAN_FM1R_FBM15 0x00008000U
1963 #define CAN_FM1R_FBM16 0x00010000U
1964 #define CAN_FM1R_FBM17 0x00020000U
1965 #define CAN_FM1R_FBM18 0x00040000U
1966 #define CAN_FM1R_FBM19 0x00080000U
1967 #define CAN_FM1R_FBM20 0x00100000U
1968 #define CAN_FM1R_FBM21 0x00200000U
1969 #define CAN_FM1R_FBM22 0x00400000U
1970 #define CAN_FM1R_FBM23 0x00800000U
1971 #define CAN_FM1R_FBM24 0x01000000U
1972 #define CAN_FM1R_FBM25 0x02000000U
1973 #define CAN_FM1R_FBM26 0x04000000U
1974 #define CAN_FM1R_FBM27 0x08000000U
1976 /******************* Bit definition for CAN_FS1R register *******************/
1977 #define CAN_FS1R_FSC 0x0FFFFFFFU
1978 #define CAN_FS1R_FSC0 0x00000001U
1979 #define CAN_FS1R_FSC1 0x00000002U
1980 #define CAN_FS1R_FSC2 0x00000004U
1981 #define CAN_FS1R_FSC3 0x00000008U
1982 #define CAN_FS1R_FSC4 0x00000010U
1983 #define CAN_FS1R_FSC5 0x00000020U
1984 #define CAN_FS1R_FSC6 0x00000040U
1985 #define CAN_FS1R_FSC7 0x00000080U
1986 #define CAN_FS1R_FSC8 0x00000100U
1987 #define CAN_FS1R_FSC9 0x00000200U
1988 #define CAN_FS1R_FSC10 0x00000400U
1989 #define CAN_FS1R_FSC11 0x00000800U
1990 #define CAN_FS1R_FSC12 0x00001000U
1991 #define CAN_FS1R_FSC13 0x00002000U
1992 #define CAN_FS1R_FSC14 0x00004000U
1993 #define CAN_FS1R_FSC15 0x00008000U
1994 #define CAN_FS1R_FSC16 0x00010000U
1995 #define CAN_FS1R_FSC17 0x00020000U
1996 #define CAN_FS1R_FSC18 0x00040000U
1997 #define CAN_FS1R_FSC19 0x00080000U
1998 #define CAN_FS1R_FSC20 0x00100000U
1999 #define CAN_FS1R_FSC21 0x00200000U
2000 #define CAN_FS1R_FSC22 0x00400000U
2001 #define CAN_FS1R_FSC23 0x00800000U
2002 #define CAN_FS1R_FSC24 0x01000000U
2003 #define CAN_FS1R_FSC25 0x02000000U
2004 #define CAN_FS1R_FSC26 0x04000000U
2005 #define CAN_FS1R_FSC27 0x08000000U
2007 /****************** Bit definition for CAN_FFA1R register *******************/
2008 #define CAN_FFA1R_FFA 0x0FFFFFFFU
2009 #define CAN_FFA1R_FFA0 0x00000001U
2010 #define CAN_FFA1R_FFA1 0x00000002U
2011 #define CAN_FFA1R_FFA2 0x00000004U
2012 #define CAN_FFA1R_FFA3 0x00000008U
2013 #define CAN_FFA1R_FFA4 0x00000010U
2014 #define CAN_FFA1R_FFA5 0x00000020U
2015 #define CAN_FFA1R_FFA6 0x00000040U
2016 #define CAN_FFA1R_FFA7 0x00000080U
2017 #define CAN_FFA1R_FFA8 0x00000100U
2018 #define CAN_FFA1R_FFA9 0x00000200U
2019 #define CAN_FFA1R_FFA10 0x00000400U
2020 #define CAN_FFA1R_FFA11 0x00000800U
2021 #define CAN_FFA1R_FFA12 0x00001000U
2022 #define CAN_FFA1R_FFA13 0x00002000U
2023 #define CAN_FFA1R_FFA14 0x00004000U
2024 #define CAN_FFA1R_FFA15 0x00008000U
2025 #define CAN_FFA1R_FFA16 0x00010000U
2026 #define CAN_FFA1R_FFA17 0x00020000U
2027 #define CAN_FFA1R_FFA18 0x00040000U
2028 #define CAN_FFA1R_FFA19 0x00080000U
2029 #define CAN_FFA1R_FFA20 0x00100000U
2030 #define CAN_FFA1R_FFA21 0x00200000U
2031 #define CAN_FFA1R_FFA22 0x00400000U
2032 #define CAN_FFA1R_FFA23 0x00800000U
2033 #define CAN_FFA1R_FFA24 0x01000000U
2034 #define CAN_FFA1R_FFA25 0x02000000U
2035 #define CAN_FFA1R_FFA26 0x04000000U
2036 #define CAN_FFA1R_FFA27 0x08000000U
2038 /******************* Bit definition for CAN_FA1R register *******************/
2039 #define CAN_FA1R_FACT 0x0FFFFFFFU
2040 #define CAN_FA1R_FACT0 0x00000001U
2041 #define CAN_FA1R_FACT1 0x00000002U
2042 #define CAN_FA1R_FACT2 0x00000004U
2043 #define CAN_FA1R_FACT3 0x00000008U
2044 #define CAN_FA1R_FACT4 0x00000010U
2045 #define CAN_FA1R_FACT5 0x00000020U
2046 #define CAN_FA1R_FACT6 0x00000040U
2047 #define CAN_FA1R_FACT7 0x00000080U
2048 #define CAN_FA1R_FACT8 0x00000100U
2049 #define CAN_FA1R_FACT9 0x00000200U
2050 #define CAN_FA1R_FACT10 0x00000400U
2051 #define CAN_FA1R_FACT11 0x00000800U
2052 #define CAN_FA1R_FACT12 0x00001000U
2053 #define CAN_FA1R_FACT13 0x00002000U
2054 #define CAN_FA1R_FACT14 0x00004000U
2055 #define CAN_FA1R_FACT15 0x00008000U
2056 #define CAN_FA1R_FACT16 0x00010000U
2057 #define CAN_FA1R_FACT17 0x00020000U
2058 #define CAN_FA1R_FACT18 0x00040000U
2059 #define CAN_FA1R_FACT19 0x00080000U
2060 #define CAN_FA1R_FACT20 0x00100000U
2061 #define CAN_FA1R_FACT21 0x00200000U
2062 #define CAN_FA1R_FACT22 0x00400000U
2063 #define CAN_FA1R_FACT23 0x00800000U
2064 #define CAN_FA1R_FACT24 0x01000000U
2065 #define CAN_FA1R_FACT25 0x02000000U
2066 #define CAN_FA1R_FACT26 0x04000000U
2067 #define CAN_FA1R_FACT27 0x08000000U
2069 /******************* Bit definition for CAN_F0R1 register *******************/
2070 #define CAN_F0R1_FB0 0x00000001U
2071 #define CAN_F0R1_FB1 0x00000002U
2072 #define CAN_F0R1_FB2 0x00000004U
2073 #define CAN_F0R1_FB3 0x00000008U
2074 #define CAN_F0R1_FB4 0x00000010U
2075 #define CAN_F0R1_FB5 0x00000020U
2076 #define CAN_F0R1_FB6 0x00000040U
2077 #define CAN_F0R1_FB7 0x00000080U
2078 #define CAN_F0R1_FB8 0x00000100U
2079 #define CAN_F0R1_FB9 0x00000200U
2080 #define CAN_F0R1_FB10 0x00000400U
2081 #define CAN_F0R1_FB11 0x00000800U
2082 #define CAN_F0R1_FB12 0x00001000U
2083 #define CAN_F0R1_FB13 0x00002000U
2084 #define CAN_F0R1_FB14 0x00004000U
2085 #define CAN_F0R1_FB15 0x00008000U
2086 #define CAN_F0R1_FB16 0x00010000U
2087 #define CAN_F0R1_FB17 0x00020000U
2088 #define CAN_F0R1_FB18 0x00040000U
2089 #define CAN_F0R1_FB19 0x00080000U
2090 #define CAN_F0R1_FB20 0x00100000U
2091 #define CAN_F0R1_FB21 0x00200000U
2092 #define CAN_F0R1_FB22 0x00400000U
2093 #define CAN_F0R1_FB23 0x00800000U
2094 #define CAN_F0R1_FB24 0x01000000U
2095 #define CAN_F0R1_FB25 0x02000000U
2096 #define CAN_F0R1_FB26 0x04000000U
2097 #define CAN_F0R1_FB27 0x08000000U
2098 #define CAN_F0R1_FB28 0x10000000U
2099 #define CAN_F0R1_FB29 0x20000000U
2100 #define CAN_F0R1_FB30 0x40000000U
2101 #define CAN_F0R1_FB31 0x80000000U
2103 /******************* Bit definition for CAN_F1R1 register *******************/
2104 #define CAN_F1R1_FB0 0x00000001U
2105 #define CAN_F1R1_FB1 0x00000002U
2106 #define CAN_F1R1_FB2 0x00000004U
2107 #define CAN_F1R1_FB3 0x00000008U
2108 #define CAN_F1R1_FB4 0x00000010U
2109 #define CAN_F1R1_FB5 0x00000020U
2110 #define CAN_F1R1_FB6 0x00000040U
2111 #define CAN_F1R1_FB7 0x00000080U
2112 #define CAN_F1R1_FB8 0x00000100U
2113 #define CAN_F1R1_FB9 0x00000200U
2114 #define CAN_F1R1_FB10 0x00000400U
2115 #define CAN_F1R1_FB11 0x00000800U
2116 #define CAN_F1R1_FB12 0x00001000U
2117 #define CAN_F1R1_FB13 0x00002000U
2118 #define CAN_F1R1_FB14 0x00004000U
2119 #define CAN_F1R1_FB15 0x00008000U
2120 #define CAN_F1R1_FB16 0x00010000U
2121 #define CAN_F1R1_FB17 0x00020000U
2122 #define CAN_F1R1_FB18 0x00040000U
2123 #define CAN_F1R1_FB19 0x00080000U
2124 #define CAN_F1R1_FB20 0x00100000U
2125 #define CAN_F1R1_FB21 0x00200000U
2126 #define CAN_F1R1_FB22 0x00400000U
2127 #define CAN_F1R1_FB23 0x00800000U
2128 #define CAN_F1R1_FB24 0x01000000U
2129 #define CAN_F1R1_FB25 0x02000000U
2130 #define CAN_F1R1_FB26 0x04000000U
2131 #define CAN_F1R1_FB27 0x08000000U
2132 #define CAN_F1R1_FB28 0x10000000U
2133 #define CAN_F1R1_FB29 0x20000000U
2134 #define CAN_F1R1_FB30 0x40000000U
2135 #define CAN_F1R1_FB31 0x80000000U
2137 /******************* Bit definition for CAN_F2R1 register *******************/
2138 #define CAN_F2R1_FB0 0x00000001U
2139 #define CAN_F2R1_FB1 0x00000002U
2140 #define CAN_F2R1_FB2 0x00000004U
2141 #define CAN_F2R1_FB3 0x00000008U
2142 #define CAN_F2R1_FB4 0x00000010U
2143 #define CAN_F2R1_FB5 0x00000020U
2144 #define CAN_F2R1_FB6 0x00000040U
2145 #define CAN_F2R1_FB7 0x00000080U
2146 #define CAN_F2R1_FB8 0x00000100U
2147 #define CAN_F2R1_FB9 0x00000200U
2148 #define CAN_F2R1_FB10 0x00000400U
2149 #define CAN_F2R1_FB11 0x00000800U
2150 #define CAN_F2R1_FB12 0x00001000U
2151 #define CAN_F2R1_FB13 0x00002000U
2152 #define CAN_F2R1_FB14 0x00004000U
2153 #define CAN_F2R1_FB15 0x00008000U
2154 #define CAN_F2R1_FB16 0x00010000U
2155 #define CAN_F2R1_FB17 0x00020000U
2156 #define CAN_F2R1_FB18 0x00040000U
2157 #define CAN_F2R1_FB19 0x00080000U
2158 #define CAN_F2R1_FB20 0x00100000U
2159 #define CAN_F2R1_FB21 0x00200000U
2160 #define CAN_F2R1_FB22 0x00400000U
2161 #define CAN_F2R1_FB23 0x00800000U
2162 #define CAN_F2R1_FB24 0x01000000U
2163 #define CAN_F2R1_FB25 0x02000000U
2164 #define CAN_F2R1_FB26 0x04000000U
2165 #define CAN_F2R1_FB27 0x08000000U
2166 #define CAN_F2R1_FB28 0x10000000U
2167 #define CAN_F2R1_FB29 0x20000000U
2168 #define CAN_F2R1_FB30 0x40000000U
2169 #define CAN_F2R1_FB31 0x80000000U
2171 /******************* Bit definition for CAN_F3R1 register *******************/
2172 #define CAN_F3R1_FB0 0x00000001U
2173 #define CAN_F3R1_FB1 0x00000002U
2174 #define CAN_F3R1_FB2 0x00000004U
2175 #define CAN_F3R1_FB3 0x00000008U
2176 #define CAN_F3R1_FB4 0x00000010U
2177 #define CAN_F3R1_FB5 0x00000020U
2178 #define CAN_F3R1_FB6 0x00000040U
2179 #define CAN_F3R1_FB7 0x00000080U
2180 #define CAN_F3R1_FB8 0x00000100U
2181 #define CAN_F3R1_FB9 0x00000200U
2182 #define CAN_F3R1_FB10 0x00000400U
2183 #define CAN_F3R1_FB11 0x00000800U
2184 #define CAN_F3R1_FB12 0x00001000U
2185 #define CAN_F3R1_FB13 0x00002000U
2186 #define CAN_F3R1_FB14 0x00004000U
2187 #define CAN_F3R1_FB15 0x00008000U
2188 #define CAN_F3R1_FB16 0x00010000U
2189 #define CAN_F3R1_FB17 0x00020000U
2190 #define CAN_F3R1_FB18 0x00040000U
2191 #define CAN_F3R1_FB19 0x00080000U
2192 #define CAN_F3R1_FB20 0x00100000U
2193 #define CAN_F3R1_FB21 0x00200000U
2194 #define CAN_F3R1_FB22 0x00400000U
2195 #define CAN_F3R1_FB23 0x00800000U
2196 #define CAN_F3R1_FB24 0x01000000U
2197 #define CAN_F3R1_FB25 0x02000000U
2198 #define CAN_F3R1_FB26 0x04000000U
2199 #define CAN_F3R1_FB27 0x08000000U
2200 #define CAN_F3R1_FB28 0x10000000U
2201 #define CAN_F3R1_FB29 0x20000000U
2202 #define CAN_F3R1_FB30 0x40000000U
2203 #define CAN_F3R1_FB31 0x80000000U
2205 /******************* Bit definition for CAN_F4R1 register *******************/
2206 #define CAN_F4R1_FB0 0x00000001U
2207 #define CAN_F4R1_FB1 0x00000002U
2208 #define CAN_F4R1_FB2 0x00000004U
2209 #define CAN_F4R1_FB3 0x00000008U
2210 #define CAN_F4R1_FB4 0x00000010U
2211 #define CAN_F4R1_FB5 0x00000020U
2212 #define CAN_F4R1_FB6 0x00000040U
2213 #define CAN_F4R1_FB7 0x00000080U
2214 #define CAN_F4R1_FB8 0x00000100U
2215 #define CAN_F4R1_FB9 0x00000200U
2216 #define CAN_F4R1_FB10 0x00000400U
2217 #define CAN_F4R1_FB11 0x00000800U
2218 #define CAN_F4R1_FB12 0x00001000U
2219 #define CAN_F4R1_FB13 0x00002000U
2220 #define CAN_F4R1_FB14 0x00004000U
2221 #define CAN_F4R1_FB15 0x00008000U
2222 #define CAN_F4R1_FB16 0x00010000U
2223 #define CAN_F4R1_FB17 0x00020000U
2224 #define CAN_F4R1_FB18 0x00040000U
2225 #define CAN_F4R1_FB19 0x00080000U
2226 #define CAN_F4R1_FB20 0x00100000U
2227 #define CAN_F4R1_FB21 0x00200000U
2228 #define CAN_F4R1_FB22 0x00400000U
2229 #define CAN_F4R1_FB23 0x00800000U
2230 #define CAN_F4R1_FB24 0x01000000U
2231 #define CAN_F4R1_FB25 0x02000000U
2232 #define CAN_F4R1_FB26 0x04000000U
2233 #define CAN_F4R1_FB27 0x08000000U
2234 #define CAN_F4R1_FB28 0x10000000U
2235 #define CAN_F4R1_FB29 0x20000000U
2236 #define CAN_F4R1_FB30 0x40000000U
2237 #define CAN_F4R1_FB31 0x80000000U
2239 /******************* Bit definition for CAN_F5R1 register *******************/
2240 #define CAN_F5R1_FB0 0x00000001U
2241 #define CAN_F5R1_FB1 0x00000002U
2242 #define CAN_F5R1_FB2 0x00000004U
2243 #define CAN_F5R1_FB3 0x00000008U
2244 #define CAN_F5R1_FB4 0x00000010U
2245 #define CAN_F5R1_FB5 0x00000020U
2246 #define CAN_F5R1_FB6 0x00000040U
2247 #define CAN_F5R1_FB7 0x00000080U
2248 #define CAN_F5R1_FB8 0x00000100U
2249 #define CAN_F5R1_FB9 0x00000200U
2250 #define CAN_F5R1_FB10 0x00000400U
2251 #define CAN_F5R1_FB11 0x00000800U
2252 #define CAN_F5R1_FB12 0x00001000U
2253 #define CAN_F5R1_FB13 0x00002000U
2254 #define CAN_F5R1_FB14 0x00004000U
2255 #define CAN_F5R1_FB15 0x00008000U
2256 #define CAN_F5R1_FB16 0x00010000U
2257 #define CAN_F5R1_FB17 0x00020000U
2258 #define CAN_F5R1_FB18 0x00040000U
2259 #define CAN_F5R1_FB19 0x00080000U
2260 #define CAN_F5R1_FB20 0x00100000U
2261 #define CAN_F5R1_FB21 0x00200000U
2262 #define CAN_F5R1_FB22 0x00400000U
2263 #define CAN_F5R1_FB23 0x00800000U
2264 #define CAN_F5R1_FB24 0x01000000U
2265 #define CAN_F5R1_FB25 0x02000000U
2266 #define CAN_F5R1_FB26 0x04000000U
2267 #define CAN_F5R1_FB27 0x08000000U
2268 #define CAN_F5R1_FB28 0x10000000U
2269 #define CAN_F5R1_FB29 0x20000000U
2270 #define CAN_F5R1_FB30 0x40000000U
2271 #define CAN_F5R1_FB31 0x80000000U
2273 /******************* Bit definition for CAN_F6R1 register *******************/
2274 #define CAN_F6R1_FB0 0x00000001U
2275 #define CAN_F6R1_FB1 0x00000002U
2276 #define CAN_F6R1_FB2 0x00000004U
2277 #define CAN_F6R1_FB3 0x00000008U
2278 #define CAN_F6R1_FB4 0x00000010U
2279 #define CAN_F6R1_FB5 0x00000020U
2280 #define CAN_F6R1_FB6 0x00000040U
2281 #define CAN_F6R1_FB7 0x00000080U
2282 #define CAN_F6R1_FB8 0x00000100U
2283 #define CAN_F6R1_FB9 0x00000200U
2284 #define CAN_F6R1_FB10 0x00000400U
2285 #define CAN_F6R1_FB11 0x00000800U
2286 #define CAN_F6R1_FB12 0x00001000U
2287 #define CAN_F6R1_FB13 0x00002000U
2288 #define CAN_F6R1_FB14 0x00004000U
2289 #define CAN_F6R1_FB15 0x00008000U
2290 #define CAN_F6R1_FB16 0x00010000U
2291 #define CAN_F6R1_FB17 0x00020000U
2292 #define CAN_F6R1_FB18 0x00040000U
2293 #define CAN_F6R1_FB19 0x00080000U
2294 #define CAN_F6R1_FB20 0x00100000U
2295 #define CAN_F6R1_FB21 0x00200000U
2296 #define CAN_F6R1_FB22 0x00400000U
2297 #define CAN_F6R1_FB23 0x00800000U
2298 #define CAN_F6R1_FB24 0x01000000U
2299 #define CAN_F6R1_FB25 0x02000000U
2300 #define CAN_F6R1_FB26 0x04000000U
2301 #define CAN_F6R1_FB27 0x08000000U
2302 #define CAN_F6R1_FB28 0x10000000U
2303 #define CAN_F6R1_FB29 0x20000000U
2304 #define CAN_F6R1_FB30 0x40000000U
2305 #define CAN_F6R1_FB31 0x80000000U
2307 /******************* Bit definition for CAN_F7R1 register *******************/
2308 #define CAN_F7R1_FB0 0x00000001U
2309 #define CAN_F7R1_FB1 0x00000002U
2310 #define CAN_F7R1_FB2 0x00000004U
2311 #define CAN_F7R1_FB3 0x00000008U
2312 #define CAN_F7R1_FB4 0x00000010U
2313 #define CAN_F7R1_FB5 0x00000020U
2314 #define CAN_F7R1_FB6 0x00000040U
2315 #define CAN_F7R1_FB7 0x00000080U
2316 #define CAN_F7R1_FB8 0x00000100U
2317 #define CAN_F7R1_FB9 0x00000200U
2318 #define CAN_F7R1_FB10 0x00000400U
2319 #define CAN_F7R1_FB11 0x00000800U
2320 #define CAN_F7R1_FB12 0x00001000U
2321 #define CAN_F7R1_FB13 0x00002000U
2322 #define CAN_F7R1_FB14 0x00004000U
2323 #define CAN_F7R1_FB15 0x00008000U
2324 #define CAN_F7R1_FB16 0x00010000U
2325 #define CAN_F7R1_FB17 0x00020000U
2326 #define CAN_F7R1_FB18 0x00040000U
2327 #define CAN_F7R1_FB19 0x00080000U
2328 #define CAN_F7R1_FB20 0x00100000U
2329 #define CAN_F7R1_FB21 0x00200000U
2330 #define CAN_F7R1_FB22 0x00400000U
2331 #define CAN_F7R1_FB23 0x00800000U
2332 #define CAN_F7R1_FB24 0x01000000U
2333 #define CAN_F7R1_FB25 0x02000000U
2334 #define CAN_F7R1_FB26 0x04000000U
2335 #define CAN_F7R1_FB27 0x08000000U
2336 #define CAN_F7R1_FB28 0x10000000U
2337 #define CAN_F7R1_FB29 0x20000000U
2338 #define CAN_F7R1_FB30 0x40000000U
2339 #define CAN_F7R1_FB31 0x80000000U
2341 /******************* Bit definition for CAN_F8R1 register *******************/
2342 #define CAN_F8R1_FB0 0x00000001U
2343 #define CAN_F8R1_FB1 0x00000002U
2344 #define CAN_F8R1_FB2 0x00000004U
2345 #define CAN_F8R1_FB3 0x00000008U
2346 #define CAN_F8R1_FB4 0x00000010U
2347 #define CAN_F8R1_FB5 0x00000020U
2348 #define CAN_F8R1_FB6 0x00000040U
2349 #define CAN_F8R1_FB7 0x00000080U
2350 #define CAN_F8R1_FB8 0x00000100U
2351 #define CAN_F8R1_FB9 0x00000200U
2352 #define CAN_F8R1_FB10 0x00000400U
2353 #define CAN_F8R1_FB11 0x00000800U
2354 #define CAN_F8R1_FB12 0x00001000U
2355 #define CAN_F8R1_FB13 0x00002000U
2356 #define CAN_F8R1_FB14 0x00004000U
2357 #define CAN_F8R1_FB15 0x00008000U
2358 #define CAN_F8R1_FB16 0x00010000U
2359 #define CAN_F8R1_FB17 0x00020000U
2360 #define CAN_F8R1_FB18 0x00040000U
2361 #define CAN_F8R1_FB19 0x00080000U
2362 #define CAN_F8R1_FB20 0x00100000U
2363 #define CAN_F8R1_FB21 0x00200000U
2364 #define CAN_F8R1_FB22 0x00400000U
2365 #define CAN_F8R1_FB23 0x00800000U
2366 #define CAN_F8R1_FB24 0x01000000U
2367 #define CAN_F8R1_FB25 0x02000000U
2368 #define CAN_F8R1_FB26 0x04000000U
2369 #define CAN_F8R1_FB27 0x08000000U
2370 #define CAN_F8R1_FB28 0x10000000U
2371 #define CAN_F8R1_FB29 0x20000000U
2372 #define CAN_F8R1_FB30 0x40000000U
2373 #define CAN_F8R1_FB31 0x80000000U
2375 /******************* Bit definition for CAN_F9R1 register *******************/
2376 #define CAN_F9R1_FB0 0x00000001U
2377 #define CAN_F9R1_FB1 0x00000002U
2378 #define CAN_F9R1_FB2 0x00000004U
2379 #define CAN_F9R1_FB3 0x00000008U
2380 #define CAN_F9R1_FB4 0x00000010U
2381 #define CAN_F9R1_FB5 0x00000020U
2382 #define CAN_F9R1_FB6 0x00000040U
2383 #define CAN_F9R1_FB7 0x00000080U
2384 #define CAN_F9R1_FB8 0x00000100U
2385 #define CAN_F9R1_FB9 0x00000200U
2386 #define CAN_F9R1_FB10 0x00000400U
2387 #define CAN_F9R1_FB11 0x00000800U
2388 #define CAN_F9R1_FB12 0x00001000U
2389 #define CAN_F9R1_FB13 0x00002000U
2390 #define CAN_F9R1_FB14 0x00004000U
2391 #define CAN_F9R1_FB15 0x00008000U
2392 #define CAN_F9R1_FB16 0x00010000U
2393 #define CAN_F9R1_FB17 0x00020000U
2394 #define CAN_F9R1_FB18 0x00040000U
2395 #define CAN_F9R1_FB19 0x00080000U
2396 #define CAN_F9R1_FB20 0x00100000U
2397 #define CAN_F9R1_FB21 0x00200000U
2398 #define CAN_F9R1_FB22 0x00400000U
2399 #define CAN_F9R1_FB23 0x00800000U
2400 #define CAN_F9R1_FB24 0x01000000U
2401 #define CAN_F9R1_FB25 0x02000000U
2402 #define CAN_F9R1_FB26 0x04000000U
2403 #define CAN_F9R1_FB27 0x08000000U
2404 #define CAN_F9R1_FB28 0x10000000U
2405 #define CAN_F9R1_FB29 0x20000000U
2406 #define CAN_F9R1_FB30 0x40000000U
2407 #define CAN_F9R1_FB31 0x80000000U
2409 /******************* Bit definition for CAN_F10R1 register ******************/
2410 #define CAN_F10R1_FB0 0x00000001U
2411 #define CAN_F10R1_FB1 0x00000002U
2412 #define CAN_F10R1_FB2 0x00000004U
2413 #define CAN_F10R1_FB3 0x00000008U
2414 #define CAN_F10R1_FB4 0x00000010U
2415 #define CAN_F10R1_FB5 0x00000020U
2416 #define CAN_F10R1_FB6 0x00000040U
2417 #define CAN_F10R1_FB7 0x00000080U
2418 #define CAN_F10R1_FB8 0x00000100U
2419 #define CAN_F10R1_FB9 0x00000200U
2420 #define CAN_F10R1_FB10 0x00000400U
2421 #define CAN_F10R1_FB11 0x00000800U
2422 #define CAN_F10R1_FB12 0x00001000U
2423 #define CAN_F10R1_FB13 0x00002000U
2424 #define CAN_F10R1_FB14 0x00004000U
2425 #define CAN_F10R1_FB15 0x00008000U
2426 #define CAN_F10R1_FB16 0x00010000U
2427 #define CAN_F10R1_FB17 0x00020000U
2428 #define CAN_F10R1_FB18 0x00040000U
2429 #define CAN_F10R1_FB19 0x00080000U
2430 #define CAN_F10R1_FB20 0x00100000U
2431 #define CAN_F10R1_FB21 0x00200000U
2432 #define CAN_F10R1_FB22 0x00400000U
2433 #define CAN_F10R1_FB23 0x00800000U
2434 #define CAN_F10R1_FB24 0x01000000U
2435 #define CAN_F10R1_FB25 0x02000000U
2436 #define CAN_F10R1_FB26 0x04000000U
2437 #define CAN_F10R1_FB27 0x08000000U
2438 #define CAN_F10R1_FB28 0x10000000U
2439 #define CAN_F10R1_FB29 0x20000000U
2440 #define CAN_F10R1_FB30 0x40000000U
2441 #define CAN_F10R1_FB31 0x80000000U
2443 /******************* Bit definition for CAN_F11R1 register ******************/
2444 #define CAN_F11R1_FB0 0x00000001U
2445 #define CAN_F11R1_FB1 0x00000002U
2446 #define CAN_F11R1_FB2 0x00000004U
2447 #define CAN_F11R1_FB3 0x00000008U
2448 #define CAN_F11R1_FB4 0x00000010U
2449 #define CAN_F11R1_FB5 0x00000020U
2450 #define CAN_F11R1_FB6 0x00000040U
2451 #define CAN_F11R1_FB7 0x00000080U
2452 #define CAN_F11R1_FB8 0x00000100U
2453 #define CAN_F11R1_FB9 0x00000200U
2454 #define CAN_F11R1_FB10 0x00000400U
2455 #define CAN_F11R1_FB11 0x00000800U
2456 #define CAN_F11R1_FB12 0x00001000U
2457 #define CAN_F11R1_FB13 0x00002000U
2458 #define CAN_F11R1_FB14 0x00004000U
2459 #define CAN_F11R1_FB15 0x00008000U
2460 #define CAN_F11R1_FB16 0x00010000U
2461 #define CAN_F11R1_FB17 0x00020000U
2462 #define CAN_F11R1_FB18 0x00040000U
2463 #define CAN_F11R1_FB19 0x00080000U
2464 #define CAN_F11R1_FB20 0x00100000U
2465 #define CAN_F11R1_FB21 0x00200000U
2466 #define CAN_F11R1_FB22 0x00400000U
2467 #define CAN_F11R1_FB23 0x00800000U
2468 #define CAN_F11R1_FB24 0x01000000U
2469 #define CAN_F11R1_FB25 0x02000000U
2470 #define CAN_F11R1_FB26 0x04000000U
2471 #define CAN_F11R1_FB27 0x08000000U
2472 #define CAN_F11R1_FB28 0x10000000U
2473 #define CAN_F11R1_FB29 0x20000000U
2474 #define CAN_F11R1_FB30 0x40000000U
2475 #define CAN_F11R1_FB31 0x80000000U
2477 /******************* Bit definition for CAN_F12R1 register ******************/
2478 #define CAN_F12R1_FB0 0x00000001U
2479 #define CAN_F12R1_FB1 0x00000002U
2480 #define CAN_F12R1_FB2 0x00000004U
2481 #define CAN_F12R1_FB3 0x00000008U
2482 #define CAN_F12R1_FB4 0x00000010U
2483 #define CAN_F12R1_FB5 0x00000020U
2484 #define CAN_F12R1_FB6 0x00000040U
2485 #define CAN_F12R1_FB7 0x00000080U
2486 #define CAN_F12R1_FB8 0x00000100U
2487 #define CAN_F12R1_FB9 0x00000200U
2488 #define CAN_F12R1_FB10 0x00000400U
2489 #define CAN_F12R1_FB11 0x00000800U
2490 #define CAN_F12R1_FB12 0x00001000U
2491 #define CAN_F12R1_FB13 0x00002000U
2492 #define CAN_F12R1_FB14 0x00004000U
2493 #define CAN_F12R1_FB15 0x00008000U
2494 #define CAN_F12R1_FB16 0x00010000U
2495 #define CAN_F12R1_FB17 0x00020000U
2496 #define CAN_F12R1_FB18 0x00040000U
2497 #define CAN_F12R1_FB19 0x00080000U
2498 #define CAN_F12R1_FB20 0x00100000U
2499 #define CAN_F12R1_FB21 0x00200000U
2500 #define CAN_F12R1_FB22 0x00400000U
2501 #define CAN_F12R1_FB23 0x00800000U
2502 #define CAN_F12R1_FB24 0x01000000U
2503 #define CAN_F12R1_FB25 0x02000000U
2504 #define CAN_F12R1_FB26 0x04000000U
2505 #define CAN_F12R1_FB27 0x08000000U
2506 #define CAN_F12R1_FB28 0x10000000U
2507 #define CAN_F12R1_FB29 0x20000000U
2508 #define CAN_F12R1_FB30 0x40000000U
2509 #define CAN_F12R1_FB31 0x80000000U
2511 /******************* Bit definition for CAN_F13R1 register ******************/
2512 #define CAN_F13R1_FB0 0x00000001U
2513 #define CAN_F13R1_FB1 0x00000002U
2514 #define CAN_F13R1_FB2 0x00000004U
2515 #define CAN_F13R1_FB3 0x00000008U
2516 #define CAN_F13R1_FB4 0x00000010U
2517 #define CAN_F13R1_FB5 0x00000020U
2518 #define CAN_F13R1_FB6 0x00000040U
2519 #define CAN_F13R1_FB7 0x00000080U
2520 #define CAN_F13R1_FB8 0x00000100U
2521 #define CAN_F13R1_FB9 0x00000200U
2522 #define CAN_F13R1_FB10 0x00000400U
2523 #define CAN_F13R1_FB11 0x00000800U
2524 #define CAN_F13R1_FB12 0x00001000U
2525 #define CAN_F13R1_FB13 0x00002000U
2526 #define CAN_F13R1_FB14 0x00004000U
2527 #define CAN_F13R1_FB15 0x00008000U
2528 #define CAN_F13R1_FB16 0x00010000U
2529 #define CAN_F13R1_FB17 0x00020000U
2530 #define CAN_F13R1_FB18 0x00040000U
2531 #define CAN_F13R1_FB19 0x00080000U
2532 #define CAN_F13R1_FB20 0x00100000U
2533 #define CAN_F13R1_FB21 0x00200000U
2534 #define CAN_F13R1_FB22 0x00400000U
2535 #define CAN_F13R1_FB23 0x00800000U
2536 #define CAN_F13R1_FB24 0x01000000U
2537 #define CAN_F13R1_FB25 0x02000000U
2538 #define CAN_F13R1_FB26 0x04000000U
2539 #define CAN_F13R1_FB27 0x08000000U
2540 #define CAN_F13R1_FB28 0x10000000U
2541 #define CAN_F13R1_FB29 0x20000000U
2542 #define CAN_F13R1_FB30 0x40000000U
2543 #define CAN_F13R1_FB31 0x80000000U
2545 /******************* Bit definition for CAN_F0R2 register *******************/
2546 #define CAN_F0R2_FB0 0x00000001U
2547 #define CAN_F0R2_FB1 0x00000002U
2548 #define CAN_F0R2_FB2 0x00000004U
2549 #define CAN_F0R2_FB3 0x00000008U
2550 #define CAN_F0R2_FB4 0x00000010U
2551 #define CAN_F0R2_FB5 0x00000020U
2552 #define CAN_F0R2_FB6 0x00000040U
2553 #define CAN_F0R2_FB7 0x00000080U
2554 #define CAN_F0R2_FB8 0x00000100U
2555 #define CAN_F0R2_FB9 0x00000200U
2556 #define CAN_F0R2_FB10 0x00000400U
2557 #define CAN_F0R2_FB11 0x00000800U
2558 #define CAN_F0R2_FB12 0x00001000U
2559 #define CAN_F0R2_FB13 0x00002000U
2560 #define CAN_F0R2_FB14 0x00004000U
2561 #define CAN_F0R2_FB15 0x00008000U
2562 #define CAN_F0R2_FB16 0x00010000U
2563 #define CAN_F0R2_FB17 0x00020000U
2564 #define CAN_F0R2_FB18 0x00040000U
2565 #define CAN_F0R2_FB19 0x00080000U
2566 #define CAN_F0R2_FB20 0x00100000U
2567 #define CAN_F0R2_FB21 0x00200000U
2568 #define CAN_F0R2_FB22 0x00400000U
2569 #define CAN_F0R2_FB23 0x00800000U
2570 #define CAN_F0R2_FB24 0x01000000U
2571 #define CAN_F0R2_FB25 0x02000000U
2572 #define CAN_F0R2_FB26 0x04000000U
2573 #define CAN_F0R2_FB27 0x08000000U
2574 #define CAN_F0R2_FB28 0x10000000U
2575 #define CAN_F0R2_FB29 0x20000000U
2576 #define CAN_F0R2_FB30 0x40000000U
2577 #define CAN_F0R2_FB31 0x80000000U
2579 /******************* Bit definition for CAN_F1R2 register *******************/
2580 #define CAN_F1R2_FB0 0x00000001U
2581 #define CAN_F1R2_FB1 0x00000002U
2582 #define CAN_F1R2_FB2 0x00000004U
2583 #define CAN_F1R2_FB3 0x00000008U
2584 #define CAN_F1R2_FB4 0x00000010U
2585 #define CAN_F1R2_FB5 0x00000020U
2586 #define CAN_F1R2_FB6 0x00000040U
2587 #define CAN_F1R2_FB7 0x00000080U
2588 #define CAN_F1R2_FB8 0x00000100U
2589 #define CAN_F1R2_FB9 0x00000200U
2590 #define CAN_F1R2_FB10 0x00000400U
2591 #define CAN_F1R2_FB11 0x00000800U
2592 #define CAN_F1R2_FB12 0x00001000U
2593 #define CAN_F1R2_FB13 0x00002000U
2594 #define CAN_F1R2_FB14 0x00004000U
2595 #define CAN_F1R2_FB15 0x00008000U
2596 #define CAN_F1R2_FB16 0x00010000U
2597 #define CAN_F1R2_FB17 0x00020000U
2598 #define CAN_F1R2_FB18 0x00040000U
2599 #define CAN_F1R2_FB19 0x00080000U
2600 #define CAN_F1R2_FB20 0x00100000U
2601 #define CAN_F1R2_FB21 0x00200000U
2602 #define CAN_F1R2_FB22 0x00400000U
2603 #define CAN_F1R2_FB23 0x00800000U
2604 #define CAN_F1R2_FB24 0x01000000U
2605 #define CAN_F1R2_FB25 0x02000000U
2606 #define CAN_F1R2_FB26 0x04000000U
2607 #define CAN_F1R2_FB27 0x08000000U
2608 #define CAN_F1R2_FB28 0x10000000U
2609 #define CAN_F1R2_FB29 0x20000000U
2610 #define CAN_F1R2_FB30 0x40000000U
2611 #define CAN_F1R2_FB31 0x80000000U
2613 /******************* Bit definition for CAN_F2R2 register *******************/
2614 #define CAN_F2R2_FB0 0x00000001U
2615 #define CAN_F2R2_FB1 0x00000002U
2616 #define CAN_F2R2_FB2 0x00000004U
2617 #define CAN_F2R2_FB3 0x00000008U
2618 #define CAN_F2R2_FB4 0x00000010U
2619 #define CAN_F2R2_FB5 0x00000020U
2620 #define CAN_F2R2_FB6 0x00000040U
2621 #define CAN_F2R2_FB7 0x00000080U
2622 #define CAN_F2R2_FB8 0x00000100U
2623 #define CAN_F2R2_FB9 0x00000200U
2624 #define CAN_F2R2_FB10 0x00000400U
2625 #define CAN_F2R2_FB11 0x00000800U
2626 #define CAN_F2R2_FB12 0x00001000U
2627 #define CAN_F2R2_FB13 0x00002000U
2628 #define CAN_F2R2_FB14 0x00004000U
2629 #define CAN_F2R2_FB15 0x00008000U
2630 #define CAN_F2R2_FB16 0x00010000U
2631 #define CAN_F2R2_FB17 0x00020000U
2632 #define CAN_F2R2_FB18 0x00040000U
2633 #define CAN_F2R2_FB19 0x00080000U
2634 #define CAN_F2R2_FB20 0x00100000U
2635 #define CAN_F2R2_FB21 0x00200000U
2636 #define CAN_F2R2_FB22 0x00400000U
2637 #define CAN_F2R2_FB23 0x00800000U
2638 #define CAN_F2R2_FB24 0x01000000U
2639 #define CAN_F2R2_FB25 0x02000000U
2640 #define CAN_F2R2_FB26 0x04000000U
2641 #define CAN_F2R2_FB27 0x08000000U
2642 #define CAN_F2R2_FB28 0x10000000U
2643 #define CAN_F2R2_FB29 0x20000000U
2644 #define CAN_F2R2_FB30 0x40000000U
2645 #define CAN_F2R2_FB31 0x80000000U
2647 /******************* Bit definition for CAN_F3R2 register *******************/
2648 #define CAN_F3R2_FB0 0x00000001U
2649 #define CAN_F3R2_FB1 0x00000002U
2650 #define CAN_F3R2_FB2 0x00000004U
2651 #define CAN_F3R2_FB3 0x00000008U
2652 #define CAN_F3R2_FB4 0x00000010U
2653 #define CAN_F3R2_FB5 0x00000020U
2654 #define CAN_F3R2_FB6 0x00000040U
2655 #define CAN_F3R2_FB7 0x00000080U
2656 #define CAN_F3R2_FB8 0x00000100U
2657 #define CAN_F3R2_FB9 0x00000200U
2658 #define CAN_F3R2_FB10 0x00000400U
2659 #define CAN_F3R2_FB11 0x00000800U
2660 #define CAN_F3R2_FB12 0x00001000U
2661 #define CAN_F3R2_FB13 0x00002000U
2662 #define CAN_F3R2_FB14 0x00004000U
2663 #define CAN_F3R2_FB15 0x00008000U
2664 #define CAN_F3R2_FB16 0x00010000U
2665 #define CAN_F3R2_FB17 0x00020000U
2666 #define CAN_F3R2_FB18 0x00040000U
2667 #define CAN_F3R2_FB19 0x00080000U
2668 #define CAN_F3R2_FB20 0x00100000U
2669 #define CAN_F3R2_FB21 0x00200000U
2670 #define CAN_F3R2_FB22 0x00400000U
2671 #define CAN_F3R2_FB23 0x00800000U
2672 #define CAN_F3R2_FB24 0x01000000U
2673 #define CAN_F3R2_FB25 0x02000000U
2674 #define CAN_F3R2_FB26 0x04000000U
2675 #define CAN_F3R2_FB27 0x08000000U
2676 #define CAN_F3R2_FB28 0x10000000U
2677 #define CAN_F3R2_FB29 0x20000000U
2678 #define CAN_F3R2_FB30 0x40000000U
2679 #define CAN_F3R2_FB31 0x80000000U
2681 /******************* Bit definition for CAN_F4R2 register *******************/
2682 #define CAN_F4R2_FB0 0x00000001U
2683 #define CAN_F4R2_FB1 0x00000002U
2684 #define CAN_F4R2_FB2 0x00000004U
2685 #define CAN_F4R2_FB3 0x00000008U
2686 #define CAN_F4R2_FB4 0x00000010U
2687 #define CAN_F4R2_FB5 0x00000020U
2688 #define CAN_F4R2_FB6 0x00000040U
2689 #define CAN_F4R2_FB7 0x00000080U
2690 #define CAN_F4R2_FB8 0x00000100U
2691 #define CAN_F4R2_FB9 0x00000200U
2692 #define CAN_F4R2_FB10 0x00000400U
2693 #define CAN_F4R2_FB11 0x00000800U
2694 #define CAN_F4R2_FB12 0x00001000U
2695 #define CAN_F4R2_FB13 0x00002000U
2696 #define CAN_F4R2_FB14 0x00004000U
2697 #define CAN_F4R2_FB15 0x00008000U
2698 #define CAN_F4R2_FB16 0x00010000U
2699 #define CAN_F4R2_FB17 0x00020000U
2700 #define CAN_F4R2_FB18 0x00040000U
2701 #define CAN_F4R2_FB19 0x00080000U
2702 #define CAN_F4R2_FB20 0x00100000U
2703 #define CAN_F4R2_FB21 0x00200000U
2704 #define CAN_F4R2_FB22 0x00400000U
2705 #define CAN_F4R2_FB23 0x00800000U
2706 #define CAN_F4R2_FB24 0x01000000U
2707 #define CAN_F4R2_FB25 0x02000000U
2708 #define CAN_F4R2_FB26 0x04000000U
2709 #define CAN_F4R2_FB27 0x08000000U
2710 #define CAN_F4R2_FB28 0x10000000U
2711 #define CAN_F4R2_FB29 0x20000000U
2712 #define CAN_F4R2_FB30 0x40000000U
2713 #define CAN_F4R2_FB31 0x80000000U
2715 /******************* Bit definition for CAN_F5R2 register *******************/
2716 #define CAN_F5R2_FB0 0x00000001U
2717 #define CAN_F5R2_FB1 0x00000002U
2718 #define CAN_F5R2_FB2 0x00000004U
2719 #define CAN_F5R2_FB3 0x00000008U
2720 #define CAN_F5R2_FB4 0x00000010U
2721 #define CAN_F5R2_FB5 0x00000020U
2722 #define CAN_F5R2_FB6 0x00000040U
2723 #define CAN_F5R2_FB7 0x00000080U
2724 #define CAN_F5R2_FB8 0x00000100U
2725 #define CAN_F5R2_FB9 0x00000200U
2726 #define CAN_F5R2_FB10 0x00000400U
2727 #define CAN_F5R2_FB11 0x00000800U
2728 #define CAN_F5R2_FB12 0x00001000U
2729 #define CAN_F5R2_FB13 0x00002000U
2730 #define CAN_F5R2_FB14 0x00004000U
2731 #define CAN_F5R2_FB15 0x00008000U
2732 #define CAN_F5R2_FB16 0x00010000U
2733 #define CAN_F5R2_FB17 0x00020000U
2734 #define CAN_F5R2_FB18 0x00040000U
2735 #define CAN_F5R2_FB19 0x00080000U
2736 #define CAN_F5R2_FB20 0x00100000U
2737 #define CAN_F5R2_FB21 0x00200000U
2738 #define CAN_F5R2_FB22 0x00400000U
2739 #define CAN_F5R2_FB23 0x00800000U
2740 #define CAN_F5R2_FB24 0x01000000U
2741 #define CAN_F5R2_FB25 0x02000000U
2742 #define CAN_F5R2_FB26 0x04000000U
2743 #define CAN_F5R2_FB27 0x08000000U
2744 #define CAN_F5R2_FB28 0x10000000U
2745 #define CAN_F5R2_FB29 0x20000000U
2746 #define CAN_F5R2_FB30 0x40000000U
2747 #define CAN_F5R2_FB31 0x80000000U
2749 /******************* Bit definition for CAN_F6R2 register *******************/
2750 #define CAN_F6R2_FB0 0x00000001U
2751 #define CAN_F6R2_FB1 0x00000002U
2752 #define CAN_F6R2_FB2 0x00000004U
2753 #define CAN_F6R2_FB3 0x00000008U
2754 #define CAN_F6R2_FB4 0x00000010U
2755 #define CAN_F6R2_FB5 0x00000020U
2756 #define CAN_F6R2_FB6 0x00000040U
2757 #define CAN_F6R2_FB7 0x00000080U
2758 #define CAN_F6R2_FB8 0x00000100U
2759 #define CAN_F6R2_FB9 0x00000200U
2760 #define CAN_F6R2_FB10 0x00000400U
2761 #define CAN_F6R2_FB11 0x00000800U
2762 #define CAN_F6R2_FB12 0x00001000U
2763 #define CAN_F6R2_FB13 0x00002000U
2764 #define CAN_F6R2_FB14 0x00004000U
2765 #define CAN_F6R2_FB15 0x00008000U
2766 #define CAN_F6R2_FB16 0x00010000U
2767 #define CAN_F6R2_FB17 0x00020000U
2768 #define CAN_F6R2_FB18 0x00040000U
2769 #define CAN_F6R2_FB19 0x00080000U
2770 #define CAN_F6R2_FB20 0x00100000U
2771 #define CAN_F6R2_FB21 0x00200000U
2772 #define CAN_F6R2_FB22 0x00400000U
2773 #define CAN_F6R2_FB23 0x00800000U
2774 #define CAN_F6R2_FB24 0x01000000U
2775 #define CAN_F6R2_FB25 0x02000000U
2776 #define CAN_F6R2_FB26 0x04000000U
2777 #define CAN_F6R2_FB27 0x08000000U
2778 #define CAN_F6R2_FB28 0x10000000U
2779 #define CAN_F6R2_FB29 0x20000000U
2780 #define CAN_F6R2_FB30 0x40000000U
2781 #define CAN_F6R2_FB31 0x80000000U
2783 /******************* Bit definition for CAN_F7R2 register *******************/
2784 #define CAN_F7R2_FB0 0x00000001U
2785 #define CAN_F7R2_FB1 0x00000002U
2786 #define CAN_F7R2_FB2 0x00000004U
2787 #define CAN_F7R2_FB3 0x00000008U
2788 #define CAN_F7R2_FB4 0x00000010U
2789 #define CAN_F7R2_FB5 0x00000020U
2790 #define CAN_F7R2_FB6 0x00000040U
2791 #define CAN_F7R2_FB7 0x00000080U
2792 #define CAN_F7R2_FB8 0x00000100U
2793 #define CAN_F7R2_FB9 0x00000200U
2794 #define CAN_F7R2_FB10 0x00000400U
2795 #define CAN_F7R2_FB11 0x00000800U
2796 #define CAN_F7R2_FB12 0x00001000U
2797 #define CAN_F7R2_FB13 0x00002000U
2798 #define CAN_F7R2_FB14 0x00004000U
2799 #define CAN_F7R2_FB15 0x00008000U
2800 #define CAN_F7R2_FB16 0x00010000U
2801 #define CAN_F7R2_FB17 0x00020000U
2802 #define CAN_F7R2_FB18 0x00040000U
2803 #define CAN_F7R2_FB19 0x00080000U
2804 #define CAN_F7R2_FB20 0x00100000U
2805 #define CAN_F7R2_FB21 0x00200000U
2806 #define CAN_F7R2_FB22 0x00400000U
2807 #define CAN_F7R2_FB23 0x00800000U
2808 #define CAN_F7R2_FB24 0x01000000U
2809 #define CAN_F7R2_FB25 0x02000000U
2810 #define CAN_F7R2_FB26 0x04000000U
2811 #define CAN_F7R2_FB27 0x08000000U
2812 #define CAN_F7R2_FB28 0x10000000U
2813 #define CAN_F7R2_FB29 0x20000000U
2814 #define CAN_F7R2_FB30 0x40000000U
2815 #define CAN_F7R2_FB31 0x80000000U
2817 /******************* Bit definition for CAN_F8R2 register *******************/
2818 #define CAN_F8R2_FB0 0x00000001U
2819 #define CAN_F8R2_FB1 0x00000002U
2820 #define CAN_F8R2_FB2 0x00000004U
2821 #define CAN_F8R2_FB3 0x00000008U
2822 #define CAN_F8R2_FB4 0x00000010U
2823 #define CAN_F8R2_FB5 0x00000020U
2824 #define CAN_F8R2_FB6 0x00000040U
2825 #define CAN_F8R2_FB7 0x00000080U
2826 #define CAN_F8R2_FB8 0x00000100U
2827 #define CAN_F8R2_FB9 0x00000200U
2828 #define CAN_F8R2_FB10 0x00000400U
2829 #define CAN_F8R2_FB11 0x00000800U
2830 #define CAN_F8R2_FB12 0x00001000U
2831 #define CAN_F8R2_FB13 0x00002000U
2832 #define CAN_F8R2_FB14 0x00004000U
2833 #define CAN_F8R2_FB15 0x00008000U
2834 #define CAN_F8R2_FB16 0x00010000U
2835 #define CAN_F8R2_FB17 0x00020000U
2836 #define CAN_F8R2_FB18 0x00040000U
2837 #define CAN_F8R2_FB19 0x00080000U
2838 #define CAN_F8R2_FB20 0x00100000U
2839 #define CAN_F8R2_FB21 0x00200000U
2840 #define CAN_F8R2_FB22 0x00400000U
2841 #define CAN_F8R2_FB23 0x00800000U
2842 #define CAN_F8R2_FB24 0x01000000U
2843 #define CAN_F8R2_FB25 0x02000000U
2844 #define CAN_F8R2_FB26 0x04000000U
2845 #define CAN_F8R2_FB27 0x08000000U
2846 #define CAN_F8R2_FB28 0x10000000U
2847 #define CAN_F8R2_FB29 0x20000000U
2848 #define CAN_F8R2_FB30 0x40000000U
2849 #define CAN_F8R2_FB31 0x80000000U
2851 /******************* Bit definition for CAN_F9R2 register *******************/
2852 #define CAN_F9R2_FB0 0x00000001U
2853 #define CAN_F9R2_FB1 0x00000002U
2854 #define CAN_F9R2_FB2 0x00000004U
2855 #define CAN_F9R2_FB3 0x00000008U
2856 #define CAN_F9R2_FB4 0x00000010U
2857 #define CAN_F9R2_FB5 0x00000020U
2858 #define CAN_F9R2_FB6 0x00000040U
2859 #define CAN_F9R2_FB7 0x00000080U
2860 #define CAN_F9R2_FB8 0x00000100U
2861 #define CAN_F9R2_FB9 0x00000200U
2862 #define CAN_F9R2_FB10 0x00000400U
2863 #define CAN_F9R2_FB11 0x00000800U
2864 #define CAN_F9R2_FB12 0x00001000U
2865 #define CAN_F9R2_FB13 0x00002000U
2866 #define CAN_F9R2_FB14 0x00004000U
2867 #define CAN_F9R2_FB15 0x00008000U
2868 #define CAN_F9R2_FB16 0x00010000U
2869 #define CAN_F9R2_FB17 0x00020000U
2870 #define CAN_F9R2_FB18 0x00040000U
2871 #define CAN_F9R2_FB19 0x00080000U
2872 #define CAN_F9R2_FB20 0x00100000U
2873 #define CAN_F9R2_FB21 0x00200000U
2874 #define CAN_F9R2_FB22 0x00400000U
2875 #define CAN_F9R2_FB23 0x00800000U
2876 #define CAN_F9R2_FB24 0x01000000U
2877 #define CAN_F9R2_FB25 0x02000000U
2878 #define CAN_F9R2_FB26 0x04000000U
2879 #define CAN_F9R2_FB27 0x08000000U
2880 #define CAN_F9R2_FB28 0x10000000U
2881 #define CAN_F9R2_FB29 0x20000000U
2882 #define CAN_F9R2_FB30 0x40000000U
2883 #define CAN_F9R2_FB31 0x80000000U
2885 /******************* Bit definition for CAN_F10R2 register ******************/
2886 #define CAN_F10R2_FB0 0x00000001U
2887 #define CAN_F10R2_FB1 0x00000002U
2888 #define CAN_F10R2_FB2 0x00000004U
2889 #define CAN_F10R2_FB3 0x00000008U
2890 #define CAN_F10R2_FB4 0x00000010U
2891 #define CAN_F10R2_FB5 0x00000020U
2892 #define CAN_F10R2_FB6 0x00000040U
2893 #define CAN_F10R2_FB7 0x00000080U
2894 #define CAN_F10R2_FB8 0x00000100U
2895 #define CAN_F10R2_FB9 0x00000200U
2896 #define CAN_F10R2_FB10 0x00000400U
2897 #define CAN_F10R2_FB11 0x00000800U
2898 #define CAN_F10R2_FB12 0x00001000U
2899 #define CAN_F10R2_FB13 0x00002000U
2900 #define CAN_F10R2_FB14 0x00004000U
2901 #define CAN_F10R2_FB15 0x00008000U
2902 #define CAN_F10R2_FB16 0x00010000U
2903 #define CAN_F10R2_FB17 0x00020000U
2904 #define CAN_F10R2_FB18 0x00040000U
2905 #define CAN_F10R2_FB19 0x00080000U
2906 #define CAN_F10R2_FB20 0x00100000U
2907 #define CAN_F10R2_FB21 0x00200000U
2908 #define CAN_F10R2_FB22 0x00400000U
2909 #define CAN_F10R2_FB23 0x00800000U
2910 #define CAN_F10R2_FB24 0x01000000U
2911 #define CAN_F10R2_FB25 0x02000000U
2912 #define CAN_F10R2_FB26 0x04000000U
2913 #define CAN_F10R2_FB27 0x08000000U
2914 #define CAN_F10R2_FB28 0x10000000U
2915 #define CAN_F10R2_FB29 0x20000000U
2916 #define CAN_F10R2_FB30 0x40000000U
2917 #define CAN_F10R2_FB31 0x80000000U
2919 /******************* Bit definition for CAN_F11R2 register ******************/
2920 #define CAN_F11R2_FB0 0x00000001U
2921 #define CAN_F11R2_FB1 0x00000002U
2922 #define CAN_F11R2_FB2 0x00000004U
2923 #define CAN_F11R2_FB3 0x00000008U
2924 #define CAN_F11R2_FB4 0x00000010U
2925 #define CAN_F11R2_FB5 0x00000020U
2926 #define CAN_F11R2_FB6 0x00000040U
2927 #define CAN_F11R2_FB7 0x00000080U
2928 #define CAN_F11R2_FB8 0x00000100U
2929 #define CAN_F11R2_FB9 0x00000200U
2930 #define CAN_F11R2_FB10 0x00000400U
2931 #define CAN_F11R2_FB11 0x00000800U
2932 #define CAN_F11R2_FB12 0x00001000U
2933 #define CAN_F11R2_FB13 0x00002000U
2934 #define CAN_F11R2_FB14 0x00004000U
2935 #define CAN_F11R2_FB15 0x00008000U
2936 #define CAN_F11R2_FB16 0x00010000U
2937 #define CAN_F11R2_FB17 0x00020000U
2938 #define CAN_F11R2_FB18 0x00040000U
2939 #define CAN_F11R2_FB19 0x00080000U
2940 #define CAN_F11R2_FB20 0x00100000U
2941 #define CAN_F11R2_FB21 0x00200000U
2942 #define CAN_F11R2_FB22 0x00400000U
2943 #define CAN_F11R2_FB23 0x00800000U
2944 #define CAN_F11R2_FB24 0x01000000U
2945 #define CAN_F11R2_FB25 0x02000000U
2946 #define CAN_F11R2_FB26 0x04000000U
2947 #define CAN_F11R2_FB27 0x08000000U
2948 #define CAN_F11R2_FB28 0x10000000U
2949 #define CAN_F11R2_FB29 0x20000000U
2950 #define CAN_F11R2_FB30 0x40000000U
2951 #define CAN_F11R2_FB31 0x80000000U
2953 /******************* Bit definition for CAN_F12R2 register ******************/
2954 #define CAN_F12R2_FB0 0x00000001U
2955 #define CAN_F12R2_FB1 0x00000002U
2956 #define CAN_F12R2_FB2 0x00000004U
2957 #define CAN_F12R2_FB3 0x00000008U
2958 #define CAN_F12R2_FB4 0x00000010U
2959 #define CAN_F12R2_FB5 0x00000020U
2960 #define CAN_F12R2_FB6 0x00000040U
2961 #define CAN_F12R2_FB7 0x00000080U
2962 #define CAN_F12R2_FB8 0x00000100U
2963 #define CAN_F12R2_FB9 0x00000200U
2964 #define CAN_F12R2_FB10 0x00000400U
2965 #define CAN_F12R2_FB11 0x00000800U
2966 #define CAN_F12R2_FB12 0x00001000U
2967 #define CAN_F12R2_FB13 0x00002000U
2968 #define CAN_F12R2_FB14 0x00004000U
2969 #define CAN_F12R2_FB15 0x00008000U
2970 #define CAN_F12R2_FB16 0x00010000U
2971 #define CAN_F12R2_FB17 0x00020000U
2972 #define CAN_F12R2_FB18 0x00040000U
2973 #define CAN_F12R2_FB19 0x00080000U
2974 #define CAN_F12R2_FB20 0x00100000U
2975 #define CAN_F12R2_FB21 0x00200000U
2976 #define CAN_F12R2_FB22 0x00400000U
2977 #define CAN_F12R2_FB23 0x00800000U
2978 #define CAN_F12R2_FB24 0x01000000U
2979 #define CAN_F12R2_FB25 0x02000000U
2980 #define CAN_F12R2_FB26 0x04000000U
2981 #define CAN_F12R2_FB27 0x08000000U
2982 #define CAN_F12R2_FB28 0x10000000U
2983 #define CAN_F12R2_FB29 0x20000000U
2984 #define CAN_F12R2_FB30 0x40000000U
2985 #define CAN_F12R2_FB31 0x80000000U
2987 /******************* Bit definition for CAN_F13R2 register ******************/
2988 #define CAN_F13R2_FB0 0x00000001U
2989 #define CAN_F13R2_FB1 0x00000002U
2990 #define CAN_F13R2_FB2 0x00000004U
2991 #define CAN_F13R2_FB3 0x00000008U
2992 #define CAN_F13R2_FB4 0x00000010U
2993 #define CAN_F13R2_FB5 0x00000020U
2994 #define CAN_F13R2_FB6 0x00000040U
2995 #define CAN_F13R2_FB7 0x00000080U
2996 #define CAN_F13R2_FB8 0x00000100U
2997 #define CAN_F13R2_FB9 0x00000200U
2998 #define CAN_F13R2_FB10 0x00000400U
2999 #define CAN_F13R2_FB11 0x00000800U
3000 #define CAN_F13R2_FB12 0x00001000U
3001 #define CAN_F13R2_FB13 0x00002000U
3002 #define CAN_F13R2_FB14 0x00004000U
3003 #define CAN_F13R2_FB15 0x00008000U
3004 #define CAN_F13R2_FB16 0x00010000U
3005 #define CAN_F13R2_FB17 0x00020000U
3006 #define CAN_F13R2_FB18 0x00040000U
3007 #define CAN_F13R2_FB19 0x00080000U
3008 #define CAN_F13R2_FB20 0x00100000U
3009 #define CAN_F13R2_FB21 0x00200000U
3010 #define CAN_F13R2_FB22 0x00400000U
3011 #define CAN_F13R2_FB23 0x00800000U
3012 #define CAN_F13R2_FB24 0x01000000U
3013 #define CAN_F13R2_FB25 0x02000000U
3014 #define CAN_F13R2_FB26 0x04000000U
3015 #define CAN_F13R2_FB27 0x08000000U
3016 #define CAN_F13R2_FB28 0x10000000U
3017 #define CAN_F13R2_FB29 0x20000000U
3018 #define CAN_F13R2_FB30 0x40000000U
3019 #define CAN_F13R2_FB31 0x80000000U
3021 /******************************************************************************/
3022 /* */
3023 /* CRC calculation unit */
3024 /* */
3025 /******************************************************************************/
3026 /******************* Bit definition for CRC_DR register *********************/
3027 #define CRC_DR_DR 0xFFFFFFFFU
3030 /******************* Bit definition for CRC_IDR register ********************/
3031 #define CRC_IDR_IDR 0xFFU
3034 /******************** Bit definition for CRC_CR register ********************/
3035 #define CRC_CR_RESET 0x01U
3037 /******************************************************************************/
3038 /* */
3039 /* Digital to Analog Converter */
3040 /* */
3041 /******************************************************************************/
3042 /******************** Bit definition for DAC_CR register ********************/
3043 #define DAC_CR_EN1 0x00000001U
3044 #define DAC_CR_BOFF1 0x00000002U
3045 #define DAC_CR_TEN1 0x00000004U
3047 #define DAC_CR_TSEL1 0x00000038U
3048 #define DAC_CR_TSEL1_0 0x00000008U
3049 #define DAC_CR_TSEL1_1 0x00000010U
3050 #define DAC_CR_TSEL1_2 0x00000020U
3052 #define DAC_CR_WAVE1 0x000000C0U
3053 #define DAC_CR_WAVE1_0 0x00000040U
3054 #define DAC_CR_WAVE1_1 0x00000080U
3056 #define DAC_CR_MAMP1 0x00000F00U
3057 #define DAC_CR_MAMP1_0 0x00000100U
3058 #define DAC_CR_MAMP1_1 0x00000200U
3059 #define DAC_CR_MAMP1_2 0x00000400U
3060 #define DAC_CR_MAMP1_3 0x00000800U
3062 #define DAC_CR_DMAEN1 0x00001000U
3063 #define DAC_CR_DMAUDRIE1 0x00002000U
3064 #define DAC_CR_EN2 0x00010000U
3065 #define DAC_CR_BOFF2 0x00020000U
3066 #define DAC_CR_TEN2 0x00040000U
3068 #define DAC_CR_TSEL2 0x00380000U
3069 #define DAC_CR_TSEL2_0 0x00080000U
3070 #define DAC_CR_TSEL2_1 0x00100000U
3071 #define DAC_CR_TSEL2_2 0x00200000U
3073 #define DAC_CR_WAVE2 0x00C00000U
3074 #define DAC_CR_WAVE2_0 0x00400000U
3075 #define DAC_CR_WAVE2_1 0x00800000U
3077 #define DAC_CR_MAMP2 0x0F000000U
3078 #define DAC_CR_MAMP2_0 0x01000000U
3079 #define DAC_CR_MAMP2_1 0x02000000U
3080 #define DAC_CR_MAMP2_2 0x04000000U
3081 #define DAC_CR_MAMP2_3 0x08000000U
3083 #define DAC_CR_DMAEN2 0x10000000U
3084 #define DAC_CR_DMAUDRIE2 0x20000000U
3086 /***************** Bit definition for DAC_SWTRIGR register ******************/
3087 #define DAC_SWTRIGR_SWTRIG1 0x01U
3088 #define DAC_SWTRIGR_SWTRIG2 0x02U
3090 /***************** Bit definition for DAC_DHR12R1 register ******************/
3091 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3093 /***************** Bit definition for DAC_DHR12L1 register ******************/
3094 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3096 /****************** Bit definition for DAC_DHR8R1 register ******************/
3097 #define DAC_DHR8R1_DACC1DHR 0xFFU
3099 /***************** Bit definition for DAC_DHR12R2 register ******************/
3100 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3102 /***************** Bit definition for DAC_DHR12L2 register ******************/
3103 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3105 /****************** Bit definition for DAC_DHR8R2 register ******************/
3106 #define DAC_DHR8R2_DACC2DHR 0xFFU
3108 /***************** Bit definition for DAC_DHR12RD register ******************/
3109 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3110 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3112 /***************** Bit definition for DAC_DHR12LD register ******************/
3113 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3114 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3116 /****************** Bit definition for DAC_DHR8RD register ******************/
3117 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3118 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3120 /******************* Bit definition for DAC_DOR1 register *******************/
3121 #define DAC_DOR1_DACC1DOR 0x0FFFU
3123 /******************* Bit definition for DAC_DOR2 register *******************/
3124 #define DAC_DOR2_DACC2DOR 0x0FFFU
3126 /******************** Bit definition for DAC_SR register ********************/
3127 #define DAC_SR_DMAUDR1 0x00002000U
3128 #define DAC_SR_DMAUDR2 0x20000000U
3130 /******************************************************************************/
3131 /* */
3132 /* Debug MCU */
3133 /* */
3134 /******************************************************************************/
3135 
3136 /******************************************************************************/
3137 /* */
3138 /* DCMI */
3139 /* */
3140 /******************************************************************************/
3141 /******************** Bits definition for DCMI_CR register ******************/
3142 #define DCMI_CR_CAPTURE 0x00000001U
3143 #define DCMI_CR_CM 0x00000002U
3144 #define DCMI_CR_CROP 0x00000004U
3145 #define DCMI_CR_JPEG 0x00000008U
3146 #define DCMI_CR_ESS 0x00000010U
3147 #define DCMI_CR_PCKPOL 0x00000020U
3148 #define DCMI_CR_HSPOL 0x00000040U
3149 #define DCMI_CR_VSPOL 0x00000080U
3150 #define DCMI_CR_FCRC_0 0x00000100U
3151 #define DCMI_CR_FCRC_1 0x00000200U
3152 #define DCMI_CR_EDM_0 0x00000400U
3153 #define DCMI_CR_EDM_1 0x00000800U
3154 #define DCMI_CR_CRE 0x00001000U
3155 #define DCMI_CR_ENABLE 0x00004000U
3156 
3157 /******************** Bits definition for DCMI_SR register ******************/
3158 #define DCMI_SR_HSYNC 0x00000001U
3159 #define DCMI_SR_VSYNC 0x00000002U
3160 #define DCMI_SR_FNE 0x00000004U
3161 
3162 /******************** Bits definition for DCMI_RIS register *****************/
3163 #define DCMI_RIS_FRAME_RIS 0x00000001U
3164 #define DCMI_RIS_OVR_RIS 0x00000002U
3165 #define DCMI_RIS_ERR_RIS 0x00000004U
3166 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3167 #define DCMI_RIS_LINE_RIS 0x00000010U
3168 /* Legacy defines */
3169 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3170 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
3171 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3172 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3173 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3174 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3175 
3176 /******************** Bits definition for DCMI_IER register *****************/
3177 #define DCMI_IER_FRAME_IE 0x00000001U
3178 #define DCMI_IER_OVR_IE 0x00000002U
3179 #define DCMI_IER_ERR_IE 0x00000004U
3180 #define DCMI_IER_VSYNC_IE 0x00000008U
3181 #define DCMI_IER_LINE_IE 0x00000010U
3182 /* Legacy defines */
3183 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3184 
3185 /******************** Bits definition for DCMI_MIS register *****************/
3186 #define DCMI_MIS_FRAME_MIS 0x00000001U
3187 #define DCMI_MIS_OVR_MIS 0x00000002U
3188 #define DCMI_MIS_ERR_MIS 0x00000004U
3189 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3190 #define DCMI_MIS_LINE_MIS 0x00000010U
3191 
3192 /* Legacy defines */
3193 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3194 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3195 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3196 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3197 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3198 
3199 /******************** Bits definition for DCMI_ICR register *****************/
3200 #define DCMI_ICR_FRAME_ISC 0x00000001U
3201 #define DCMI_ICR_OVR_ISC 0x00000002U
3202 #define DCMI_ICR_ERR_ISC 0x00000004U
3203 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3204 #define DCMI_ICR_LINE_ISC 0x00000010U
3205 
3206 /* Legacy defines */
3207 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3208 
3209 /******************** Bits definition for DCMI_ESCR register ******************/
3210 #define DCMI_ESCR_FSC 0x000000FFU
3211 #define DCMI_ESCR_LSC 0x0000FF00U
3212 #define DCMI_ESCR_LEC 0x00FF0000U
3213 #define DCMI_ESCR_FEC 0xFF000000U
3214 
3215 /******************** Bits definition for DCMI_ESUR register ******************/
3216 #define DCMI_ESUR_FSU 0x000000FFU
3217 #define DCMI_ESUR_LSU 0x0000FF00U
3218 #define DCMI_ESUR_LEU 0x00FF0000U
3219 #define DCMI_ESUR_FEU 0xFF000000U
3220 
3221 /******************** Bits definition for DCMI_CWSTRT register ******************/
3222 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3223 #define DCMI_CWSTRT_VST 0x1FFF0000U
3224 
3225 /******************** Bits definition for DCMI_CWSIZE register ******************/
3226 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3227 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3228 
3229 /******************** Bits definition for DCMI_DR register ******************/
3230 #define DCMI_DR_BYTE0 0x000000FFU
3231 #define DCMI_DR_BYTE1 0x0000FF00U
3232 #define DCMI_DR_BYTE2 0x00FF0000U
3233 #define DCMI_DR_BYTE3 0xFF000000U
3234 
3235 /******************************************************************************/
3236 /* */
3237 /* DMA Controller */
3238 /* */
3239 /******************************************************************************/
3240 /******************** Bits definition for DMA_SxCR register *****************/
3241 #define DMA_SxCR_CHSEL 0x0E000000U
3242 #define DMA_SxCR_CHSEL_0 0x02000000U
3243 #define DMA_SxCR_CHSEL_1 0x04000000U
3244 #define DMA_SxCR_CHSEL_2 0x08000000U
3245 #define DMA_SxCR_MBURST 0x01800000U
3246 #define DMA_SxCR_MBURST_0 0x00800000U
3247 #define DMA_SxCR_MBURST_1 0x01000000U
3248 #define DMA_SxCR_PBURST 0x00600000U
3249 #define DMA_SxCR_PBURST_0 0x00200000U
3250 #define DMA_SxCR_PBURST_1 0x00400000U
3251 #define DMA_SxCR_CT 0x00080000U
3252 #define DMA_SxCR_DBM 0x00040000U
3253 #define DMA_SxCR_PL 0x00030000U
3254 #define DMA_SxCR_PL_0 0x00010000U
3255 #define DMA_SxCR_PL_1 0x00020000U
3256 #define DMA_SxCR_PINCOS 0x00008000U
3257 #define DMA_SxCR_MSIZE 0x00006000U
3258 #define DMA_SxCR_MSIZE_0 0x00002000U
3259 #define DMA_SxCR_MSIZE_1 0x00004000U
3260 #define DMA_SxCR_PSIZE 0x00001800U
3261 #define DMA_SxCR_PSIZE_0 0x00000800U
3262 #define DMA_SxCR_PSIZE_1 0x00001000U
3263 #define DMA_SxCR_MINC 0x00000400U
3264 #define DMA_SxCR_PINC 0x00000200U
3265 #define DMA_SxCR_CIRC 0x00000100U
3266 #define DMA_SxCR_DIR 0x000000C0U
3267 #define DMA_SxCR_DIR_0 0x00000040U
3268 #define DMA_SxCR_DIR_1 0x00000080U
3269 #define DMA_SxCR_PFCTRL 0x00000020U
3270 #define DMA_SxCR_TCIE 0x00000010U
3271 #define DMA_SxCR_HTIE 0x00000008U
3272 #define DMA_SxCR_TEIE 0x00000004U
3273 #define DMA_SxCR_DMEIE 0x00000002U
3274 #define DMA_SxCR_EN 0x00000001U
3275 
3276 /* Legacy defines */
3277 #define DMA_SxCR_ACK 0x00100000U
3278 
3279 /******************** Bits definition for DMA_SxCNDTR register **************/
3280 #define DMA_SxNDT 0x0000FFFFU
3281 #define DMA_SxNDT_0 0x00000001U
3282 #define DMA_SxNDT_1 0x00000002U
3283 #define DMA_SxNDT_2 0x00000004U
3284 #define DMA_SxNDT_3 0x00000008U
3285 #define DMA_SxNDT_4 0x00000010U
3286 #define DMA_SxNDT_5 0x00000020U
3287 #define DMA_SxNDT_6 0x00000040U
3288 #define DMA_SxNDT_7 0x00000080U
3289 #define DMA_SxNDT_8 0x00000100U
3290 #define DMA_SxNDT_9 0x00000200U
3291 #define DMA_SxNDT_10 0x00000400U
3292 #define DMA_SxNDT_11 0x00000800U
3293 #define DMA_SxNDT_12 0x00001000U
3294 #define DMA_SxNDT_13 0x00002000U
3295 #define DMA_SxNDT_14 0x00004000U
3296 #define DMA_SxNDT_15 0x00008000U
3297 
3298 /******************** Bits definition for DMA_SxFCR register ****************/
3299 #define DMA_SxFCR_FEIE 0x00000080U
3300 #define DMA_SxFCR_FS 0x00000038U
3301 #define DMA_SxFCR_FS_0 0x00000008U
3302 #define DMA_SxFCR_FS_1 0x00000010U
3303 #define DMA_SxFCR_FS_2 0x00000020U
3304 #define DMA_SxFCR_DMDIS 0x00000004U
3305 #define DMA_SxFCR_FTH 0x00000003U
3306 #define DMA_SxFCR_FTH_0 0x00000001U
3307 #define DMA_SxFCR_FTH_1 0x00000002U
3308 
3309 /******************** Bits definition for DMA_LISR register *****************/
3310 #define DMA_LISR_TCIF3 0x08000000U
3311 #define DMA_LISR_HTIF3 0x04000000U
3312 #define DMA_LISR_TEIF3 0x02000000U
3313 #define DMA_LISR_DMEIF3 0x01000000U
3314 #define DMA_LISR_FEIF3 0x00400000U
3315 #define DMA_LISR_TCIF2 0x00200000U
3316 #define DMA_LISR_HTIF2 0x00100000U
3317 #define DMA_LISR_TEIF2 0x00080000U
3318 #define DMA_LISR_DMEIF2 0x00040000U
3319 #define DMA_LISR_FEIF2 0x00010000U
3320 #define DMA_LISR_TCIF1 0x00000800U
3321 #define DMA_LISR_HTIF1 0x00000400U
3322 #define DMA_LISR_TEIF1 0x00000200U
3323 #define DMA_LISR_DMEIF1 0x00000100U
3324 #define DMA_LISR_FEIF1 0x00000040U
3325 #define DMA_LISR_TCIF0 0x00000020U
3326 #define DMA_LISR_HTIF0 0x00000010U
3327 #define DMA_LISR_TEIF0 0x00000008U
3328 #define DMA_LISR_DMEIF0 0x00000004U
3329 #define DMA_LISR_FEIF0 0x00000001U
3330 
3331 /******************** Bits definition for DMA_HISR register *****************/
3332 #define DMA_HISR_TCIF7 0x08000000U
3333 #define DMA_HISR_HTIF7 0x04000000U
3334 #define DMA_HISR_TEIF7 0x02000000U
3335 #define DMA_HISR_DMEIF7 0x01000000U
3336 #define DMA_HISR_FEIF7 0x00400000U
3337 #define DMA_HISR_TCIF6 0x00200000U
3338 #define DMA_HISR_HTIF6 0x00100000U
3339 #define DMA_HISR_TEIF6 0x00080000U
3340 #define DMA_HISR_DMEIF6 0x00040000U
3341 #define DMA_HISR_FEIF6 0x00010000U
3342 #define DMA_HISR_TCIF5 0x00000800U
3343 #define DMA_HISR_HTIF5 0x00000400U
3344 #define DMA_HISR_TEIF5 0x00000200U
3345 #define DMA_HISR_DMEIF5 0x00000100U
3346 #define DMA_HISR_FEIF5 0x00000040U
3347 #define DMA_HISR_TCIF4 0x00000020U
3348 #define DMA_HISR_HTIF4 0x00000010U
3349 #define DMA_HISR_TEIF4 0x00000008U
3350 #define DMA_HISR_DMEIF4 0x00000004U
3351 #define DMA_HISR_FEIF4 0x00000001U
3352 
3353 /******************** Bits definition for DMA_LIFCR register ****************/
3354 #define DMA_LIFCR_CTCIF3 0x08000000U
3355 #define DMA_LIFCR_CHTIF3 0x04000000U
3356 #define DMA_LIFCR_CTEIF3 0x02000000U
3357 #define DMA_LIFCR_CDMEIF3 0x01000000U
3358 #define DMA_LIFCR_CFEIF3 0x00400000U
3359 #define DMA_LIFCR_CTCIF2 0x00200000U
3360 #define DMA_LIFCR_CHTIF2 0x00100000U
3361 #define DMA_LIFCR_CTEIF2 0x00080000U
3362 #define DMA_LIFCR_CDMEIF2 0x00040000U
3363 #define DMA_LIFCR_CFEIF2 0x00010000U
3364 #define DMA_LIFCR_CTCIF1 0x00000800U
3365 #define DMA_LIFCR_CHTIF1 0x00000400U
3366 #define DMA_LIFCR_CTEIF1 0x00000200U
3367 #define DMA_LIFCR_CDMEIF1 0x00000100U
3368 #define DMA_LIFCR_CFEIF1 0x00000040U
3369 #define DMA_LIFCR_CTCIF0 0x00000020U
3370 #define DMA_LIFCR_CHTIF0 0x00000010U
3371 #define DMA_LIFCR_CTEIF0 0x00000008U
3372 #define DMA_LIFCR_CDMEIF0 0x00000004U
3373 #define DMA_LIFCR_CFEIF0 0x00000001U
3374 
3375 /******************** Bits definition for DMA_HIFCR register ****************/
3376 #define DMA_HIFCR_CTCIF7 0x08000000U
3377 #define DMA_HIFCR_CHTIF7 0x04000000U
3378 #define DMA_HIFCR_CTEIF7 0x02000000U
3379 #define DMA_HIFCR_CDMEIF7 0x01000000U
3380 #define DMA_HIFCR_CFEIF7 0x00400000U
3381 #define DMA_HIFCR_CTCIF6 0x00200000U
3382 #define DMA_HIFCR_CHTIF6 0x00100000U
3383 #define DMA_HIFCR_CTEIF6 0x00080000U
3384 #define DMA_HIFCR_CDMEIF6 0x00040000U
3385 #define DMA_HIFCR_CFEIF6 0x00010000U
3386 #define DMA_HIFCR_CTCIF5 0x00000800U
3387 #define DMA_HIFCR_CHTIF5 0x00000400U
3388 #define DMA_HIFCR_CTEIF5 0x00000200U
3389 #define DMA_HIFCR_CDMEIF5 0x00000100U
3390 #define DMA_HIFCR_CFEIF5 0x00000040U
3391 #define DMA_HIFCR_CTCIF4 0x00000020U
3392 #define DMA_HIFCR_CHTIF4 0x00000010U
3393 #define DMA_HIFCR_CTEIF4 0x00000008U
3394 #define DMA_HIFCR_CDMEIF4 0x00000004U
3395 #define DMA_HIFCR_CFEIF4 0x00000001U
3396 
3397 
3398 /******************************************************************************/
3399 /* */
3400 /* AHB Master DMA2D Controller (DMA2D) */
3401 /* */
3402 /******************************************************************************/
3403 
3404 /******************** Bit definition for DMA2D_CR register ******************/
3405 
3406 #define DMA2D_CR_START 0x00000001U
3407 #define DMA2D_CR_SUSP 0x00000002U
3408 #define DMA2D_CR_ABORT 0x00000004U
3409 #define DMA2D_CR_TEIE 0x00000100U
3410 #define DMA2D_CR_TCIE 0x00000200U
3411 #define DMA2D_CR_TWIE 0x00000400U
3412 #define DMA2D_CR_CAEIE 0x00000800U
3413 #define DMA2D_CR_CTCIE 0x00001000U
3414 #define DMA2D_CR_CEIE 0x00002000U
3415 #define DMA2D_CR_MODE 0x00030000U
3416 #define DMA2D_CR_MODE_0 0x00010000U
3417 #define DMA2D_CR_MODE_1 0x00020000U
3419 /******************** Bit definition for DMA2D_ISR register *****************/
3420 
3421 #define DMA2D_ISR_TEIF 0x00000001U
3422 #define DMA2D_ISR_TCIF 0x00000002U
3423 #define DMA2D_ISR_TWIF 0x00000004U
3424 #define DMA2D_ISR_CAEIF 0x00000008U
3425 #define DMA2D_ISR_CTCIF 0x00000010U
3426 #define DMA2D_ISR_CEIF 0x00000020U
3428 /******************** Bit definition for DMA2D_IFCR register ****************/
3429 
3430 #define DMA2D_IFCR_CTEIF 0x00000001U
3431 #define DMA2D_IFCR_CTCIF 0x00000002U
3432 #define DMA2D_IFCR_CTWIF 0x00000004U
3433 #define DMA2D_IFCR_CAECIF 0x00000008U
3434 #define DMA2D_IFCR_CCTCIF 0x00000010U
3435 #define DMA2D_IFCR_CCEIF 0x00000020U
3437 /* Legacy defines */
3438 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3439 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3440 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3441 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3442 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3443 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3445 /******************** Bit definition for DMA2D_FGMAR register ***************/
3446 
3447 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3449 /******************** Bit definition for DMA2D_FGOR register ****************/
3450 
3451 #define DMA2D_FGOR_LO 0x00003FFFU
3453 /******************** Bit definition for DMA2D_BGMAR register ***************/
3454 
3455 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3457 /******************** Bit definition for DMA2D_BGOR register ****************/
3458 
3459 #define DMA2D_BGOR_LO 0x00003FFFU
3461 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3462 
3463 #define DMA2D_FGPFCCR_CM 0x0000000FU
3464 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3465 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3466 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3467 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3468 #define DMA2D_FGPFCCR_CCM 0x00000010U
3469 #define DMA2D_FGPFCCR_START 0x00000020U
3470 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3471 #define DMA2D_FGPFCCR_AM 0x00030000U
3472 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3473 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3474 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3476 /******************** Bit definition for DMA2D_FGCOLR register **************/
3477 
3478 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3479 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3480 #define DMA2D_FGCOLR_RED 0x00FF0000U
3482 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3483 
3484 #define DMA2D_BGPFCCR_CM 0x0000000FU
3485 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3486 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3487 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3488 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3489 #define DMA2D_BGPFCCR_CCM 0x00000010U
3490 #define DMA2D_BGPFCCR_START 0x00000020U
3491 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3492 #define DMA2D_BGPFCCR_AM 0x00030000U
3493 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3494 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3495 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3497 /******************** Bit definition for DMA2D_BGCOLR register **************/
3498 
3499 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3500 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3501 #define DMA2D_BGCOLR_RED 0x00FF0000U
3503 /******************** Bit definition for DMA2D_FGCMAR register **************/
3504 
3505 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3507 /******************** Bit definition for DMA2D_BGCMAR register **************/
3508 
3509 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3511 /******************** Bit definition for DMA2D_OPFCCR register **************/
3512 
3513 #define DMA2D_OPFCCR_CM 0x00000007U
3514 #define DMA2D_OPFCCR_CM_0 0x00000001U
3515 #define DMA2D_OPFCCR_CM_1 0x00000002U
3516 #define DMA2D_OPFCCR_CM_2 0x00000004U
3518 /******************** Bit definition for DMA2D_OCOLR register ***************/
3519 
3522 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3523 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3524 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3525 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3528 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3529 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3530 #define DMA2D_OCOLR_RED_2 0x0000F800U
3533 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3534 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3535 #define DMA2D_OCOLR_RED_3 0x00007C00U
3536 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3539 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3540 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3541 #define DMA2D_OCOLR_RED_4 0x00000F00U
3542 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3544 /******************** Bit definition for DMA2D_OMAR register ****************/
3545 
3546 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3548 /******************** Bit definition for DMA2D_OOR register *****************/
3549 
3550 #define DMA2D_OOR_LO 0x00003FFFU
3552 /******************** Bit definition for DMA2D_NLR register *****************/
3553 
3554 #define DMA2D_NLR_NL 0x0000FFFFU
3555 #define DMA2D_NLR_PL 0x3FFF0000U
3557 /******************** Bit definition for DMA2D_LWR register *****************/
3558 
3559 #define DMA2D_LWR_LW 0x0000FFFFU
3561 /******************** Bit definition for DMA2D_AMTCR register ***************/
3562 
3563 #define DMA2D_AMTCR_EN 0x00000001U
3564 #define DMA2D_AMTCR_DT 0x0000FF00U
3566 /******************** Bit definition for DMA2D_FGCLUT register **************/
3567 
3568 /******************** Bit definition for DMA2D_BGCLUT register **************/
3569 
3570 
3571 
3572 /******************************************************************************/
3573 /* */
3574 /* External Interrupt/Event Controller */
3575 /* */
3576 /******************************************************************************/
3577 /******************* Bit definition for EXTI_IMR register *******************/
3578 #define EXTI_IMR_MR0 0x00000001U
3579 #define EXTI_IMR_MR1 0x00000002U
3580 #define EXTI_IMR_MR2 0x00000004U
3581 #define EXTI_IMR_MR3 0x00000008U
3582 #define EXTI_IMR_MR4 0x00000010U
3583 #define EXTI_IMR_MR5 0x00000020U
3584 #define EXTI_IMR_MR6 0x00000040U
3585 #define EXTI_IMR_MR7 0x00000080U
3586 #define EXTI_IMR_MR8 0x00000100U
3587 #define EXTI_IMR_MR9 0x00000200U
3588 #define EXTI_IMR_MR10 0x00000400U
3589 #define EXTI_IMR_MR11 0x00000800U
3590 #define EXTI_IMR_MR12 0x00001000U
3591 #define EXTI_IMR_MR13 0x00002000U
3592 #define EXTI_IMR_MR14 0x00004000U
3593 #define EXTI_IMR_MR15 0x00008000U
3594 #define EXTI_IMR_MR16 0x00010000U
3595 #define EXTI_IMR_MR17 0x00020000U
3596 #define EXTI_IMR_MR18 0x00040000U
3597 #define EXTI_IMR_MR19 0x00080000U
3598 #define EXTI_IMR_MR20 0x00100000U
3599 #define EXTI_IMR_MR21 0x00200000U
3600 #define EXTI_IMR_MR22 0x00400000U
3602 /******************* Bit definition for EXTI_EMR register *******************/
3603 #define EXTI_EMR_MR0 0x00000001U
3604 #define EXTI_EMR_MR1 0x00000002U
3605 #define EXTI_EMR_MR2 0x00000004U
3606 #define EXTI_EMR_MR3 0x00000008U
3607 #define EXTI_EMR_MR4 0x00000010U
3608 #define EXTI_EMR_MR5 0x00000020U
3609 #define EXTI_EMR_MR6 0x00000040U
3610 #define EXTI_EMR_MR7 0x00000080U
3611 #define EXTI_EMR_MR8 0x00000100U
3612 #define EXTI_EMR_MR9 0x00000200U
3613 #define EXTI_EMR_MR10 0x00000400U
3614 #define EXTI_EMR_MR11 0x00000800U
3615 #define EXTI_EMR_MR12 0x00001000U
3616 #define EXTI_EMR_MR13 0x00002000U
3617 #define EXTI_EMR_MR14 0x00004000U
3618 #define EXTI_EMR_MR15 0x00008000U
3619 #define EXTI_EMR_MR16 0x00010000U
3620 #define EXTI_EMR_MR17 0x00020000U
3621 #define EXTI_EMR_MR18 0x00040000U
3622 #define EXTI_EMR_MR19 0x00080000U
3623 #define EXTI_EMR_MR20 0x00100000U
3624 #define EXTI_EMR_MR21 0x00200000U
3625 #define EXTI_EMR_MR22 0x00400000U
3627 /****************** Bit definition for EXTI_RTSR register *******************/
3628 #define EXTI_RTSR_TR0 0x00000001U
3629 #define EXTI_RTSR_TR1 0x00000002U
3630 #define EXTI_RTSR_TR2 0x00000004U
3631 #define EXTI_RTSR_TR3 0x00000008U
3632 #define EXTI_RTSR_TR4 0x00000010U
3633 #define EXTI_RTSR_TR5 0x00000020U
3634 #define EXTI_RTSR_TR6 0x00000040U
3635 #define EXTI_RTSR_TR7 0x00000080U
3636 #define EXTI_RTSR_TR8 0x00000100U
3637 #define EXTI_RTSR_TR9 0x00000200U
3638 #define EXTI_RTSR_TR10 0x00000400U
3639 #define EXTI_RTSR_TR11 0x00000800U
3640 #define EXTI_RTSR_TR12 0x00001000U
3641 #define EXTI_RTSR_TR13 0x00002000U
3642 #define EXTI_RTSR_TR14 0x00004000U
3643 #define EXTI_RTSR_TR15 0x00008000U
3644 #define EXTI_RTSR_TR16 0x00010000U
3645 #define EXTI_RTSR_TR17 0x00020000U
3646 #define EXTI_RTSR_TR18 0x00040000U
3647 #define EXTI_RTSR_TR19 0x00080000U
3648 #define EXTI_RTSR_TR20 0x00100000U
3649 #define EXTI_RTSR_TR21 0x00200000U
3650 #define EXTI_RTSR_TR22 0x00400000U
3652 /****************** Bit definition for EXTI_FTSR register *******************/
3653 #define EXTI_FTSR_TR0 0x00000001U
3654 #define EXTI_FTSR_TR1 0x00000002U
3655 #define EXTI_FTSR_TR2 0x00000004U
3656 #define EXTI_FTSR_TR3 0x00000008U
3657 #define EXTI_FTSR_TR4 0x00000010U
3658 #define EXTI_FTSR_TR5 0x00000020U
3659 #define EXTI_FTSR_TR6 0x00000040U
3660 #define EXTI_FTSR_TR7 0x00000080U
3661 #define EXTI_FTSR_TR8 0x00000100U
3662 #define EXTI_FTSR_TR9 0x00000200U
3663 #define EXTI_FTSR_TR10 0x00000400U
3664 #define EXTI_FTSR_TR11 0x00000800U
3665 #define EXTI_FTSR_TR12 0x00001000U
3666 #define EXTI_FTSR_TR13 0x00002000U
3667 #define EXTI_FTSR_TR14 0x00004000U
3668 #define EXTI_FTSR_TR15 0x00008000U
3669 #define EXTI_FTSR_TR16 0x00010000U
3670 #define EXTI_FTSR_TR17 0x00020000U
3671 #define EXTI_FTSR_TR18 0x00040000U
3672 #define EXTI_FTSR_TR19 0x00080000U
3673 #define EXTI_FTSR_TR20 0x00100000U
3674 #define EXTI_FTSR_TR21 0x00200000U
3675 #define EXTI_FTSR_TR22 0x00400000U
3677 /****************** Bit definition for EXTI_SWIER register ******************/
3678 #define EXTI_SWIER_SWIER0 0x00000001U
3679 #define EXTI_SWIER_SWIER1 0x00000002U
3680 #define EXTI_SWIER_SWIER2 0x00000004U
3681 #define EXTI_SWIER_SWIER3 0x00000008U
3682 #define EXTI_SWIER_SWIER4 0x00000010U
3683 #define EXTI_SWIER_SWIER5 0x00000020U
3684 #define EXTI_SWIER_SWIER6 0x00000040U
3685 #define EXTI_SWIER_SWIER7 0x00000080U
3686 #define EXTI_SWIER_SWIER8 0x00000100U
3687 #define EXTI_SWIER_SWIER9 0x00000200U
3688 #define EXTI_SWIER_SWIER10 0x00000400U
3689 #define EXTI_SWIER_SWIER11 0x00000800U
3690 #define EXTI_SWIER_SWIER12 0x00001000U
3691 #define EXTI_SWIER_SWIER13 0x00002000U
3692 #define EXTI_SWIER_SWIER14 0x00004000U
3693 #define EXTI_SWIER_SWIER15 0x00008000U
3694 #define EXTI_SWIER_SWIER16 0x00010000U
3695 #define EXTI_SWIER_SWIER17 0x00020000U
3696 #define EXTI_SWIER_SWIER18 0x00040000U
3697 #define EXTI_SWIER_SWIER19 0x00080000U
3698 #define EXTI_SWIER_SWIER20 0x00100000U
3699 #define EXTI_SWIER_SWIER21 0x00200000U
3700 #define EXTI_SWIER_SWIER22 0x00400000U
3702 /******************* Bit definition for EXTI_PR register ********************/
3703 #define EXTI_PR_PR0 0x00000001U
3704 #define EXTI_PR_PR1 0x00000002U
3705 #define EXTI_PR_PR2 0x00000004U
3706 #define EXTI_PR_PR3 0x00000008U
3707 #define EXTI_PR_PR4 0x00000010U
3708 #define EXTI_PR_PR5 0x00000020U
3709 #define EXTI_PR_PR6 0x00000040U
3710 #define EXTI_PR_PR7 0x00000080U
3711 #define EXTI_PR_PR8 0x00000100U
3712 #define EXTI_PR_PR9 0x00000200U
3713 #define EXTI_PR_PR10 0x00000400U
3714 #define EXTI_PR_PR11 0x00000800U
3715 #define EXTI_PR_PR12 0x00001000U
3716 #define EXTI_PR_PR13 0x00002000U
3717 #define EXTI_PR_PR14 0x00004000U
3718 #define EXTI_PR_PR15 0x00008000U
3719 #define EXTI_PR_PR16 0x00010000U
3720 #define EXTI_PR_PR17 0x00020000U
3721 #define EXTI_PR_PR18 0x00040000U
3722 #define EXTI_PR_PR19 0x00080000U
3723 #define EXTI_PR_PR20 0x00100000U
3724 #define EXTI_PR_PR21 0x00200000U
3725 #define EXTI_PR_PR22 0x00400000U
3727 /******************************************************************************/
3728 /* */
3729 /* FLASH */
3730 /* */
3731 /******************************************************************************/
3732 /******************* Bits definition for FLASH_ACR register *****************/
3733 #define FLASH_ACR_LATENCY 0x0000000FU
3734 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3735 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3736 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3737 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3738 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3739 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3740 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3741 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3742 #define FLASH_ACR_LATENCY_8WS 0x00000008U
3743 #define FLASH_ACR_LATENCY_9WS 0x00000009U
3744 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
3745 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
3746 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
3747 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
3748 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
3749 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
3750 #define FLASH_ACR_PRFTEN 0x00000100U
3751 #define FLASH_ACR_ICEN 0x00000200U
3752 #define FLASH_ACR_DCEN 0x00000400U
3753 #define FLASH_ACR_ICRST 0x00000800U
3754 #define FLASH_ACR_DCRST 0x00001000U
3755 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3756 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3757 
3758 /******************* Bits definition for FLASH_SR register ******************/
3759 #define FLASH_SR_EOP 0x00000001U
3760 #define FLASH_SR_SOP 0x00000002U
3761 #define FLASH_SR_WRPERR 0x00000010U
3762 #define FLASH_SR_PGAERR 0x00000020U
3763 #define FLASH_SR_PGPERR 0x00000040U
3764 #define FLASH_SR_PGSERR 0x00000080U
3765 #define FLASH_SR_BSY 0x00010000U
3766 
3767 /******************* Bits definition for FLASH_CR register ******************/
3768 #define FLASH_CR_PG 0x00000001U
3769 #define FLASH_CR_SER 0x00000002U
3770 #define FLASH_CR_MER 0x00000004U
3771 #define FLASH_CR_MER1 FLASH_CR_MER
3772 #define FLASH_CR_SNB 0x000000F8U
3773 #define FLASH_CR_SNB_0 0x00000008U
3774 #define FLASH_CR_SNB_1 0x00000010U
3775 #define FLASH_CR_SNB_2 0x00000020U
3776 #define FLASH_CR_SNB_3 0x00000040U
3777 #define FLASH_CR_SNB_4 0x00000080U
3778 #define FLASH_CR_PSIZE 0x00000300U
3779 #define FLASH_CR_PSIZE_0 0x00000100U
3780 #define FLASH_CR_PSIZE_1 0x00000200U
3781 #define FLASH_CR_MER2 0x00008000U
3782 #define FLASH_CR_STRT 0x00010000U
3783 #define FLASH_CR_EOPIE 0x01000000U
3784 #define FLASH_CR_LOCK 0x80000000U
3785 
3786 /******************* Bits definition for FLASH_OPTCR register ***************/
3787 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3788 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3789 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3790 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3791 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3792 #define FLASH_OPTCR_BFB2 0x00000010U
3793 #define FLASH_OPTCR_WDG_SW 0x00000020U
3794 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3795 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3796 #define FLASH_OPTCR_RDP 0x0000FF00U
3797 #define FLASH_OPTCR_RDP_0 0x00000100U
3798 #define FLASH_OPTCR_RDP_1 0x00000200U
3799 #define FLASH_OPTCR_RDP_2 0x00000400U
3800 #define FLASH_OPTCR_RDP_3 0x00000800U
3801 #define FLASH_OPTCR_RDP_4 0x00001000U
3802 #define FLASH_OPTCR_RDP_5 0x00002000U
3803 #define FLASH_OPTCR_RDP_6 0x00004000U
3804 #define FLASH_OPTCR_RDP_7 0x00008000U
3805 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3806 #define FLASH_OPTCR_nWRP_0 0x00010000U
3807 #define FLASH_OPTCR_nWRP_1 0x00020000U
3808 #define FLASH_OPTCR_nWRP_2 0x00040000U
3809 #define FLASH_OPTCR_nWRP_3 0x00080000U
3810 #define FLASH_OPTCR_nWRP_4 0x00100000U
3811 #define FLASH_OPTCR_nWRP_5 0x00200000U
3812 #define FLASH_OPTCR_nWRP_6 0x00400000U
3813 #define FLASH_OPTCR_nWRP_7 0x00800000U
3814 #define FLASH_OPTCR_nWRP_8 0x01000000U
3815 #define FLASH_OPTCR_nWRP_9 0x02000000U
3816 #define FLASH_OPTCR_nWRP_10 0x04000000U
3817 #define FLASH_OPTCR_nWRP_11 0x08000000U
3818 #define FLASH_OPTCR_DB1M 0x40000000U
3819 #define FLASH_OPTCR_SPRMOD 0x80000000U
3820 
3821 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3822 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3823 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3824 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3825 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3826 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3827 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3828 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3829 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3830 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3831 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3832 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3833 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3834 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3835 
3836 /******************************************************************************/
3837 /* */
3838 /* Flexible Memory Controller */
3839 /* */
3840 /******************************************************************************/
3841 /****************** Bit definition for FMC_BCR1 register *******************/
3842 #define FMC_BCR1_MBKEN 0x00000001U
3843 #define FMC_BCR1_MUXEN 0x00000002U
3845 #define FMC_BCR1_MTYP 0x0000000CU
3846 #define FMC_BCR1_MTYP_0 0x00000004U
3847 #define FMC_BCR1_MTYP_1 0x00000008U
3849 #define FMC_BCR1_MWID 0x00000030U
3850 #define FMC_BCR1_MWID_0 0x00000010U
3851 #define FMC_BCR1_MWID_1 0x00000020U
3853 #define FMC_BCR1_FACCEN 0x00000040U
3854 #define FMC_BCR1_BURSTEN 0x00000100U
3855 #define FMC_BCR1_WAITPOL 0x00000200U
3856 #define FMC_BCR1_WRAPMOD 0x00000400U
3857 #define FMC_BCR1_WAITCFG 0x00000800U
3858 #define FMC_BCR1_WREN 0x00001000U
3859 #define FMC_BCR1_WAITEN 0x00002000U
3860 #define FMC_BCR1_EXTMOD 0x00004000U
3861 #define FMC_BCR1_ASYNCWAIT 0x00008000U
3862 #define FMC_BCR1_CPSIZE 0x00070000U
3863 #define FMC_BCR1_CPSIZE_0 0x00010000U
3864 #define FMC_BCR1_CPSIZE_1 0x00020000U
3865 #define FMC_BCR1_CPSIZE_2 0x00040000U
3866 #define FMC_BCR1_CBURSTRW 0x00080000U
3867 #define FMC_BCR1_CCLKEN 0x00100000U
3869 /****************** Bit definition for FMC_BCR2 register *******************/
3870 #define FMC_BCR2_MBKEN 0x00000001U
3871 #define FMC_BCR2_MUXEN 0x00000002U
3873 #define FMC_BCR2_MTYP 0x0000000CU
3874 #define FMC_BCR2_MTYP_0 0x00000004U
3875 #define FMC_BCR2_MTYP_1 0x00000008U
3877 #define FMC_BCR2_MWID 0x00000030U
3878 #define FMC_BCR2_MWID_0 0x00000010U
3879 #define FMC_BCR2_MWID_1 0x00000020U
3881 #define FMC_BCR2_FACCEN 0x00000040U
3882 #define FMC_BCR2_BURSTEN 0x00000100U
3883 #define FMC_BCR2_WAITPOL 0x00000200U
3884 #define FMC_BCR2_WRAPMOD 0x00000400U
3885 #define FMC_BCR2_WAITCFG 0x00000800U
3886 #define FMC_BCR2_WREN 0x00001000U
3887 #define FMC_BCR2_WAITEN 0x00002000U
3888 #define FMC_BCR2_EXTMOD 0x00004000U
3889 #define FMC_BCR2_ASYNCWAIT 0x00008000U
3890 #define FMC_BCR2_CPSIZE 0x00070000U
3891 #define FMC_BCR2_CPSIZE_0 0x00010000U
3892 #define FMC_BCR2_CPSIZE_1 0x00020000U
3893 #define FMC_BCR2_CPSIZE_2 0x00040000U
3894 #define FMC_BCR2_CBURSTRW 0x00080000U
3896 /****************** Bit definition for FMC_BCR3 register *******************/
3897 #define FMC_BCR3_MBKEN 0x00000001U
3898 #define FMC_BCR3_MUXEN 0x00000002U
3900 #define FMC_BCR3_MTYP 0x0000000CU
3901 #define FMC_BCR3_MTYP_0 0x00000004U
3902 #define FMC_BCR3_MTYP_1 0x00000008U
3904 #define FMC_BCR3_MWID 0x00000030U
3905 #define FMC_BCR3_MWID_0 0x00000010U
3906 #define FMC_BCR3_MWID_1 0x00000020U
3908 #define FMC_BCR3_FACCEN 0x00000040U
3909 #define FMC_BCR3_BURSTEN 0x00000100U
3910 #define FMC_BCR3_WAITPOL 0x00000200U
3911 #define FMC_BCR3_WRAPMOD 0x00000400U
3912 #define FMC_BCR3_WAITCFG 0x00000800U
3913 #define FMC_BCR3_WREN 0x00001000U
3914 #define FMC_BCR3_WAITEN 0x00002000U
3915 #define FMC_BCR3_EXTMOD 0x00004000U
3916 #define FMC_BCR3_ASYNCWAIT 0x00008000U
3917 #define FMC_BCR3_CPSIZE 0x00070000U
3918 #define FMC_BCR3_CPSIZE_0 0x00010000U
3919 #define FMC_BCR3_CPSIZE_1 0x00020000U
3920 #define FMC_BCR3_CPSIZE_2 0x00040000U
3921 #define FMC_BCR3_CBURSTRW 0x00080000U
3923 /****************** Bit definition for FMC_BCR4 register *******************/
3924 #define FMC_BCR4_MBKEN 0x00000001U
3925 #define FMC_BCR4_MUXEN 0x00000002U
3927 #define FMC_BCR4_MTYP 0x0000000CU
3928 #define FMC_BCR4_MTYP_0 0x00000004U
3929 #define FMC_BCR4_MTYP_1 0x00000008U
3931 #define FMC_BCR4_MWID 0x00000030U
3932 #define FMC_BCR4_MWID_0 0x00000010U
3933 #define FMC_BCR4_MWID_1 0x00000020U
3935 #define FMC_BCR4_FACCEN 0x00000040U
3936 #define FMC_BCR4_BURSTEN 0x00000100U
3937 #define FMC_BCR4_WAITPOL 0x00000200U
3938 #define FMC_BCR4_WRAPMOD 0x00000400U
3939 #define FMC_BCR4_WAITCFG 0x00000800U
3940 #define FMC_BCR4_WREN 0x00001000U
3941 #define FMC_BCR4_WAITEN 0x00002000U
3942 #define FMC_BCR4_EXTMOD 0x00004000U
3943 #define FMC_BCR4_ASYNCWAIT 0x00008000U
3944 #define FMC_BCR4_CPSIZE 0x00070000U
3945 #define FMC_BCR4_CPSIZE_0 0x00010000U
3946 #define FMC_BCR4_CPSIZE_1 0x00020000U
3947 #define FMC_BCR4_CPSIZE_2 0x00040000U
3948 #define FMC_BCR4_CBURSTRW 0x00080000U
3950 /****************** Bit definition for FMC_BTR1 register ******************/
3951 #define FMC_BTR1_ADDSET 0x0000000FU
3952 #define FMC_BTR1_ADDSET_0 0x00000001U
3953 #define FMC_BTR1_ADDSET_1 0x00000002U
3954 #define FMC_BTR1_ADDSET_2 0x00000004U
3955 #define FMC_BTR1_ADDSET_3 0x00000008U
3957 #define FMC_BTR1_ADDHLD 0x000000F0U
3958 #define FMC_BTR1_ADDHLD_0 0x00000010U
3959 #define FMC_BTR1_ADDHLD_1 0x00000020U
3960 #define FMC_BTR1_ADDHLD_2 0x00000040U
3961 #define FMC_BTR1_ADDHLD_3 0x00000080U
3963 #define FMC_BTR1_DATAST 0x0000FF00U
3964 #define FMC_BTR1_DATAST_0 0x00000100U
3965 #define FMC_BTR1_DATAST_1 0x00000200U
3966 #define FMC_BTR1_DATAST_2 0x00000400U
3967 #define FMC_BTR1_DATAST_3 0x00000800U
3968 #define FMC_BTR1_DATAST_4 0x00001000U
3969 #define FMC_BTR1_DATAST_5 0x00002000U
3970 #define FMC_BTR1_DATAST_6 0x00004000U
3971 #define FMC_BTR1_DATAST_7 0x00008000U
3973 #define FMC_BTR1_BUSTURN 0x000F0000U
3974 #define FMC_BTR1_BUSTURN_0 0x00010000U
3975 #define FMC_BTR1_BUSTURN_1 0x00020000U
3976 #define FMC_BTR1_BUSTURN_2 0x00040000U
3977 #define FMC_BTR1_BUSTURN_3 0x00080000U
3979 #define FMC_BTR1_CLKDIV 0x00F00000U
3980 #define FMC_BTR1_CLKDIV_0 0x00100000U
3981 #define FMC_BTR1_CLKDIV_1 0x00200000U
3982 #define FMC_BTR1_CLKDIV_2 0x00400000U
3983 #define FMC_BTR1_CLKDIV_3 0x00800000U
3985 #define FMC_BTR1_DATLAT 0x0F000000U
3986 #define FMC_BTR1_DATLAT_0 0x01000000U
3987 #define FMC_BTR1_DATLAT_1 0x02000000U
3988 #define FMC_BTR1_DATLAT_2 0x04000000U
3989 #define FMC_BTR1_DATLAT_3 0x08000000U
3991 #define FMC_BTR1_ACCMOD 0x30000000U
3992 #define FMC_BTR1_ACCMOD_0 0x10000000U
3993 #define FMC_BTR1_ACCMOD_1 0x20000000U
3995 /****************** Bit definition for FMC_BTR2 register *******************/
3996 #define FMC_BTR2_ADDSET 0x0000000FU
3997 #define FMC_BTR2_ADDSET_0 0x00000001U
3998 #define FMC_BTR2_ADDSET_1 0x00000002U
3999 #define FMC_BTR2_ADDSET_2 0x00000004U
4000 #define FMC_BTR2_ADDSET_3 0x00000008U
4002 #define FMC_BTR2_ADDHLD 0x000000F0U
4003 #define FMC_BTR2_ADDHLD_0 0x00000010U
4004 #define FMC_BTR2_ADDHLD_1 0x00000020U
4005 #define FMC_BTR2_ADDHLD_2 0x00000040U
4006 #define FMC_BTR2_ADDHLD_3 0x00000080U
4008 #define FMC_BTR2_DATAST 0x0000FF00U
4009 #define FMC_BTR2_DATAST_0 0x00000100U
4010 #define FMC_BTR2_DATAST_1 0x00000200U
4011 #define FMC_BTR2_DATAST_2 0x00000400U
4012 #define FMC_BTR2_DATAST_3 0x00000800U
4013 #define FMC_BTR2_DATAST_4 0x00001000U
4014 #define FMC_BTR2_DATAST_5 0x00002000U
4015 #define FMC_BTR2_DATAST_6 0x00004000U
4016 #define FMC_BTR2_DATAST_7 0x00008000U
4018 #define FMC_BTR2_BUSTURN 0x000F0000U
4019 #define FMC_BTR2_BUSTURN_0 0x00010000U
4020 #define FMC_BTR2_BUSTURN_1 0x00020000U
4021 #define FMC_BTR2_BUSTURN_2 0x00040000U
4022 #define FMC_BTR2_BUSTURN_3 0x00080000U
4024 #define FMC_BTR2_CLKDIV 0x00F00000U
4025 #define FMC_BTR2_CLKDIV_0 0x00100000U
4026 #define FMC_BTR2_CLKDIV_1 0x00200000U
4027 #define FMC_BTR2_CLKDIV_2 0x00400000U
4028 #define FMC_BTR2_CLKDIV_3 0x00800000U
4030 #define FMC_BTR2_DATLAT 0x0F000000U
4031 #define FMC_BTR2_DATLAT_0 0x01000000U
4032 #define FMC_BTR2_DATLAT_1 0x02000000U
4033 #define FMC_BTR2_DATLAT_2 0x04000000U
4034 #define FMC_BTR2_DATLAT_3 0x08000000U
4036 #define FMC_BTR2_ACCMOD 0x30000000U
4037 #define FMC_BTR2_ACCMOD_0 0x10000000U
4038 #define FMC_BTR2_ACCMOD_1 0x20000000U
4040 /******************* Bit definition for FMC_BTR3 register *******************/
4041 #define FMC_BTR3_ADDSET 0x0000000FU
4042 #define FMC_BTR3_ADDSET_0 0x00000001U
4043 #define FMC_BTR3_ADDSET_1 0x00000002U
4044 #define FMC_BTR3_ADDSET_2 0x00000004U
4045 #define FMC_BTR3_ADDSET_3 0x00000008U
4047 #define FMC_BTR3_ADDHLD 0x000000F0U
4048 #define FMC_BTR3_ADDHLD_0 0x00000010U
4049 #define FMC_BTR3_ADDHLD_1 0x00000020U
4050 #define FMC_BTR3_ADDHLD_2 0x00000040U
4051 #define FMC_BTR3_ADDHLD_3 0x00000080U
4053 #define FMC_BTR3_DATAST 0x0000FF00U
4054 #define FMC_BTR3_DATAST_0 0x00000100U
4055 #define FMC_BTR3_DATAST_1 0x00000200U
4056 #define FMC_BTR3_DATAST_2 0x00000400U
4057 #define FMC_BTR3_DATAST_3 0x00000800U
4058 #define FMC_BTR3_DATAST_4 0x00001000U
4059 #define FMC_BTR3_DATAST_5 0x00002000U
4060 #define FMC_BTR3_DATAST_6 0x00004000U
4061 #define FMC_BTR3_DATAST_7 0x00008000U
4063 #define FMC_BTR3_BUSTURN 0x000F0000U
4064 #define FMC_BTR3_BUSTURN_0 0x00010000U
4065 #define FMC_BTR3_BUSTURN_1 0x00020000U
4066 #define FMC_BTR3_BUSTURN_2 0x00040000U
4067 #define FMC_BTR3_BUSTURN_3 0x00080000U
4069 #define FMC_BTR3_CLKDIV 0x00F00000U
4070 #define FMC_BTR3_CLKDIV_0 0x00100000U
4071 #define FMC_BTR3_CLKDIV_1 0x00200000U
4072 #define FMC_BTR3_CLKDIV_2 0x00400000U
4073 #define FMC_BTR3_CLKDIV_3 0x00800000U
4075 #define FMC_BTR3_DATLAT 0x0F000000U
4076 #define FMC_BTR3_DATLAT_0 0x01000000U
4077 #define FMC_BTR3_DATLAT_1 0x02000000U
4078 #define FMC_BTR3_DATLAT_2 0x04000000U
4079 #define FMC_BTR3_DATLAT_3 0x08000000U
4081 #define FMC_BTR3_ACCMOD 0x30000000U
4082 #define FMC_BTR3_ACCMOD_0 0x10000000U
4083 #define FMC_BTR3_ACCMOD_1 0x20000000U
4085 /****************** Bit definition for FMC_BTR4 register *******************/
4086 #define FMC_BTR4_ADDSET 0x0000000FU
4087 #define FMC_BTR4_ADDSET_0 0x00000001U
4088 #define FMC_BTR4_ADDSET_1 0x00000002U
4089 #define FMC_BTR4_ADDSET_2 0x00000004U
4090 #define FMC_BTR4_ADDSET_3 0x00000008U
4092 #define FMC_BTR4_ADDHLD 0x000000F0U
4093 #define FMC_BTR4_ADDHLD_0 0x00000010U
4094 #define FMC_BTR4_ADDHLD_1 0x00000020U
4095 #define FMC_BTR4_ADDHLD_2 0x00000040U
4096 #define FMC_BTR4_ADDHLD_3 0x00000080U
4098 #define FMC_BTR4_DATAST 0x0000FF00U
4099 #define FMC_BTR4_DATAST_0 0x00000100U
4100 #define FMC_BTR4_DATAST_1 0x00000200U
4101 #define FMC_BTR4_DATAST_2 0x00000400U
4102 #define FMC_BTR4_DATAST_3 0x00000800U
4103 #define FMC_BTR4_DATAST_4 0x00001000U
4104 #define FMC_BTR4_DATAST_5 0x00002000U
4105 #define FMC_BTR4_DATAST_6 0x00004000U
4106 #define FMC_BTR4_DATAST_7 0x00008000U
4108 #define FMC_BTR4_BUSTURN 0x000F0000U
4109 #define FMC_BTR4_BUSTURN_0 0x00010000U
4110 #define FMC_BTR4_BUSTURN_1 0x00020000U
4111 #define FMC_BTR4_BUSTURN_2 0x00040000U
4112 #define FMC_BTR4_BUSTURN_3 0x00080000U
4114 #define FMC_BTR4_CLKDIV 0x00F00000U
4115 #define FMC_BTR4_CLKDIV_0 0x00100000U
4116 #define FMC_BTR4_CLKDIV_1 0x00200000U
4117 #define FMC_BTR4_CLKDIV_2 0x00400000U
4118 #define FMC_BTR4_CLKDIV_3 0x00800000U
4120 #define FMC_BTR4_DATLAT 0x0F000000U
4121 #define FMC_BTR4_DATLAT_0 0x01000000U
4122 #define FMC_BTR4_DATLAT_1 0x02000000U
4123 #define FMC_BTR4_DATLAT_2 0x04000000U
4124 #define FMC_BTR4_DATLAT_3 0x08000000U
4126 #define FMC_BTR4_ACCMOD 0x30000000U
4127 #define FMC_BTR4_ACCMOD_0 0x10000000U
4128 #define FMC_BTR4_ACCMOD_1 0x20000000U
4130 /****************** Bit definition for FMC_BWTR1 register ******************/
4131 #define FMC_BWTR1_ADDSET 0x0000000FU
4132 #define FMC_BWTR1_ADDSET_0 0x00000001U
4133 #define FMC_BWTR1_ADDSET_1 0x00000002U
4134 #define FMC_BWTR1_ADDSET_2 0x00000004U
4135 #define FMC_BWTR1_ADDSET_3 0x00000008U
4137 #define FMC_BWTR1_ADDHLD 0x000000F0U
4138 #define FMC_BWTR1_ADDHLD_0 0x00000010U
4139 #define FMC_BWTR1_ADDHLD_1 0x00000020U
4140 #define FMC_BWTR1_ADDHLD_2 0x00000040U
4141 #define FMC_BWTR1_ADDHLD_3 0x00000080U
4143 #define FMC_BWTR1_DATAST 0x0000FF00U
4144 #define FMC_BWTR1_DATAST_0 0x00000100U
4145 #define FMC_BWTR1_DATAST_1 0x00000200U
4146 #define FMC_BWTR1_DATAST_2 0x00000400U
4147 #define FMC_BWTR1_DATAST_3 0x00000800U
4148 #define FMC_BWTR1_DATAST_4 0x00001000U
4149 #define FMC_BWTR1_DATAST_5 0x00002000U
4150 #define FMC_BWTR1_DATAST_6 0x00004000U
4151 #define FMC_BWTR1_DATAST_7 0x00008000U
4153 #define FMC_BWTR1_BUSTURN 0x000F0000U
4154 #define FMC_BWTR1_BUSTURN_0 0x00010000U
4155 #define FMC_BWTR1_BUSTURN_1 0x00020000U
4156 #define FMC_BWTR1_BUSTURN_2 0x00040000U
4157 #define FMC_BWTR1_BUSTURN_3 0x00080000U
4159 #define FMC_BWTR1_ACCMOD 0x30000000U
4160 #define FMC_BWTR1_ACCMOD_0 0x10000000U
4161 #define FMC_BWTR1_ACCMOD_1 0x20000000U
4163 /****************** Bit definition for FMC_BWTR2 register ******************/
4164 #define FMC_BWTR2_ADDSET 0x0000000FU
4165 #define FMC_BWTR2_ADDSET_0 0x00000001U
4166 #define FMC_BWTR2_ADDSET_1 0x00000002U
4167 #define FMC_BWTR2_ADDSET_2 0x00000004U
4168 #define FMC_BWTR2_ADDSET_3 0x00000008U
4170 #define FMC_BWTR2_ADDHLD 0x000000F0U
4171 #define FMC_BWTR2_ADDHLD_0 0x00000010U
4172 #define FMC_BWTR2_ADDHLD_1 0x00000020U
4173 #define FMC_BWTR2_ADDHLD_2 0x00000040U
4174 #define FMC_BWTR2_ADDHLD_3 0x00000080U
4176 #define FMC_BWTR2_DATAST 0x0000FF00U
4177 #define FMC_BWTR2_DATAST_0 0x00000100U
4178 #define FMC_BWTR2_DATAST_1 0x00000200U
4179 #define FMC_BWTR2_DATAST_2 0x00000400U
4180 #define FMC_BWTR2_DATAST_3 0x00000800U
4181 #define FMC_BWTR2_DATAST_4 0x00001000U
4182 #define FMC_BWTR2_DATAST_5 0x00002000U
4183 #define FMC_BWTR2_DATAST_6 0x00004000U
4184 #define FMC_BWTR2_DATAST_7 0x00008000U
4186 #define FMC_BWTR2_BUSTURN 0x000F0000U
4187 #define FMC_BWTR2_BUSTURN_0 0x00010000U
4188 #define FMC_BWTR2_BUSTURN_1 0x00020000U
4189 #define FMC_BWTR2_BUSTURN_2 0x00040000U
4190 #define FMC_BWTR2_BUSTURN_3 0x00080000U
4192 #define FMC_BWTR2_ACCMOD 0x30000000U
4193 #define FMC_BWTR2_ACCMOD_0 0x10000000U
4194 #define FMC_BWTR2_ACCMOD_1 0x20000000U
4196 /****************** Bit definition for FMC_BWTR3 register ******************/
4197 #define FMC_BWTR3_ADDSET 0x0000000FU
4198 #define FMC_BWTR3_ADDSET_0 0x00000001U
4199 #define FMC_BWTR3_ADDSET_1 0x00000002U
4200 #define FMC_BWTR3_ADDSET_2 0x00000004U
4201 #define FMC_BWTR3_ADDSET_3 0x00000008U
4203 #define FMC_BWTR3_ADDHLD 0x000000F0U
4204 #define FMC_BWTR3_ADDHLD_0 0x00000010U
4205 #define FMC_BWTR3_ADDHLD_1 0x00000020U
4206 #define FMC_BWTR3_ADDHLD_2 0x00000040U
4207 #define FMC_BWTR3_ADDHLD_3 0x00000080U
4209 #define FMC_BWTR3_DATAST 0x0000FF00U
4210 #define FMC_BWTR3_DATAST_0 0x00000100U
4211 #define FMC_BWTR3_DATAST_1 0x00000200U
4212 #define FMC_BWTR3_DATAST_2 0x00000400U
4213 #define FMC_BWTR3_DATAST_3 0x00000800U
4214 #define FMC_BWTR3_DATAST_4 0x00001000U
4215 #define FMC_BWTR3_DATAST_5 0x00002000U
4216 #define FMC_BWTR3_DATAST_6 0x00004000U
4217 #define FMC_BWTR3_DATAST_7 0x00008000U
4219 #define FMC_BWTR3_BUSTURN 0x000F0000U
4220 #define FMC_BWTR3_BUSTURN_0 0x00010000U
4221 #define FMC_BWTR3_BUSTURN_1 0x00020000U
4222 #define FMC_BWTR3_BUSTURN_2 0x00040000U
4223 #define FMC_BWTR3_BUSTURN_3 0x00080000U
4225 #define FMC_BWTR3_ACCMOD 0x30000000U
4226 #define FMC_BWTR3_ACCMOD_0 0x10000000U
4227 #define FMC_BWTR3_ACCMOD_1 0x20000000U
4229 /****************** Bit definition for FMC_BWTR4 register ******************/
4230 #define FMC_BWTR4_ADDSET 0x0000000FU
4231 #define FMC_BWTR4_ADDSET_0 0x00000001U
4232 #define FMC_BWTR4_ADDSET_1 0x00000002U
4233 #define FMC_BWTR4_ADDSET_2 0x00000004U
4234 #define FMC_BWTR4_ADDSET_3 0x00000008U
4236 #define FMC_BWTR4_ADDHLD 0x000000F0U
4237 #define FMC_BWTR4_ADDHLD_0 0x00000010U
4238 #define FMC_BWTR4_ADDHLD_1 0x00000020U
4239 #define FMC_BWTR4_ADDHLD_2 0x00000040U
4240 #define FMC_BWTR4_ADDHLD_3 0x00000080U
4242 #define FMC_BWTR4_DATAST 0x0000FF00U
4243 #define FMC_BWTR4_DATAST_0 0x00000100U
4244 #define FMC_BWTR4_DATAST_1 0x00000200U
4245 #define FMC_BWTR4_DATAST_2 0x00000400U
4246 #define FMC_BWTR4_DATAST_3 0x00000800U
4247 #define FMC_BWTR4_DATAST_4 0x00001000U
4248 #define FMC_BWTR4_DATAST_5 0x00002000U
4249 #define FMC_BWTR4_DATAST_6 0x00004000U
4250 #define FMC_BWTR4_DATAST_7 0x00008000U
4252 #define FMC_BWTR4_BUSTURN 0x000F0000U
4253 #define FMC_BWTR4_BUSTURN_0 0x00010000U
4254 #define FMC_BWTR4_BUSTURN_1 0x00020000U
4255 #define FMC_BWTR4_BUSTURN_2 0x00040000U
4256 #define FMC_BWTR4_BUSTURN_3 0x00080000U
4258 #define FMC_BWTR4_ACCMOD 0x30000000U
4259 #define FMC_BWTR4_ACCMOD_0 0x10000000U
4260 #define FMC_BWTR4_ACCMOD_1 0x20000000U
4262 /****************** Bit definition for FMC_PCR2 register *******************/
4263 #define FMC_PCR2_PWAITEN 0x00000002U
4264 #define FMC_PCR2_PBKEN 0x00000004U
4265 #define FMC_PCR2_PTYP 0x00000008U
4267 #define FMC_PCR2_PWID 0x00000030U
4268 #define FMC_PCR2_PWID_0 0x00000010U
4269 #define FMC_PCR2_PWID_1 0x00000020U
4271 #define FMC_PCR2_ECCEN 0x00000040U
4273 #define FMC_PCR2_TCLR 0x00001E00U
4274 #define FMC_PCR2_TCLR_0 0x00000200U
4275 #define FMC_PCR2_TCLR_1 0x00000400U
4276 #define FMC_PCR2_TCLR_2 0x00000800U
4277 #define FMC_PCR2_TCLR_3 0x00001000U
4279 #define FMC_PCR2_TAR 0x0001E000U
4280 #define FMC_PCR2_TAR_0 0x00002000U
4281 #define FMC_PCR2_TAR_1 0x00004000U
4282 #define FMC_PCR2_TAR_2 0x00008000U
4283 #define FMC_PCR2_TAR_3 0x00010000U
4285 #define FMC_PCR2_ECCPS 0x000E0000U
4286 #define FMC_PCR2_ECCPS_0 0x00020000U
4287 #define FMC_PCR2_ECCPS_1 0x00040000U
4288 #define FMC_PCR2_ECCPS_2 0x00080000U
4290 /****************** Bit definition for FMC_PCR3 register *******************/
4291 #define FMC_PCR3_PWAITEN 0x00000002U
4292 #define FMC_PCR3_PBKEN 0x00000004U
4293 #define FMC_PCR3_PTYP 0x00000008U
4295 #define FMC_PCR3_PWID 0x00000030U
4296 #define FMC_PCR3_PWID_0 0x00000010U
4297 #define FMC_PCR3_PWID_1 0x00000020U
4299 #define FMC_PCR3_ECCEN 0x00000040U
4301 #define FMC_PCR3_TCLR 0x00001E00U
4302 #define FMC_PCR3_TCLR_0 0x00000200U
4303 #define FMC_PCR3_TCLR_1 0x00000400U
4304 #define FMC_PCR3_TCLR_2 0x00000800U
4305 #define FMC_PCR3_TCLR_3 0x00001000U
4307 #define FMC_PCR3_TAR 0x0001E000U
4308 #define FMC_PCR3_TAR_0 0x00002000U
4309 #define FMC_PCR3_TAR_1 0x00004000U
4310 #define FMC_PCR3_TAR_2 0x00008000U
4311 #define FMC_PCR3_TAR_3 0x00010000U
4313 #define FMC_PCR3_ECCPS 0x000E0000U
4314 #define FMC_PCR3_ECCPS_0 0x00020000U
4315 #define FMC_PCR3_ECCPS_1 0x00040000U
4316 #define FMC_PCR3_ECCPS_2 0x00080000U
4318 /****************** Bit definition for FMC_PCR4 register *******************/
4319 #define FMC_PCR4_PWAITEN 0x00000002U
4320 #define FMC_PCR4_PBKEN 0x00000004U
4321 #define FMC_PCR4_PTYP 0x00000008U
4323 #define FMC_PCR4_PWID 0x00000030U
4324 #define FMC_PCR4_PWID_0 0x00000010U
4325 #define FMC_PCR4_PWID_1 0x00000020U
4327 #define FMC_PCR4_ECCEN 0x00000040U
4329 #define FMC_PCR4_TCLR 0x00001E00U
4330 #define FMC_PCR4_TCLR_0 0x00000200U
4331 #define FMC_PCR4_TCLR_1 0x00000400U
4332 #define FMC_PCR4_TCLR_2 0x00000800U
4333 #define FMC_PCR4_TCLR_3 0x00001000U
4335 #define FMC_PCR4_TAR 0x0001E000U
4336 #define FMC_PCR4_TAR_0 0x00002000U
4337 #define FMC_PCR4_TAR_1 0x00004000U
4338 #define FMC_PCR4_TAR_2 0x00008000U
4339 #define FMC_PCR4_TAR_3 0x00010000U
4341 #define FMC_PCR4_ECCPS 0x000E0000U
4342 #define FMC_PCR4_ECCPS_0 0x00020000U
4343 #define FMC_PCR4_ECCPS_1 0x00040000U
4344 #define FMC_PCR4_ECCPS_2 0x00080000U
4346 /******************* Bit definition for FMC_SR2 register *******************/
4347 #define FMC_SR2_IRS 0x01U
4348 #define FMC_SR2_ILS 0x02U
4349 #define FMC_SR2_IFS 0x04U
4350 #define FMC_SR2_IREN 0x08U
4351 #define FMC_SR2_ILEN 0x10U
4352 #define FMC_SR2_IFEN 0x20U
4353 #define FMC_SR2_FEMPT 0x40U
4355 /******************* Bit definition for FMC_SR3 register *******************/
4356 #define FMC_SR3_IRS 0x01U
4357 #define FMC_SR3_ILS 0x02U
4358 #define FMC_SR3_IFS 0x04U
4359 #define FMC_SR3_IREN 0x08U
4360 #define FMC_SR3_ILEN 0x10U
4361 #define FMC_SR3_IFEN 0x20U
4362 #define FMC_SR3_FEMPT 0x40U
4364 /******************* Bit definition for FMC_SR4 register *******************/
4365 #define FMC_SR4_IRS 0x01U
4366 #define FMC_SR4_ILS 0x02U
4367 #define FMC_SR4_IFS 0x04U
4368 #define FMC_SR4_IREN 0x08U
4369 #define FMC_SR4_ILEN 0x10U
4370 #define FMC_SR4_IFEN 0x20U
4371 #define FMC_SR4_FEMPT 0x40U
4373 /****************** Bit definition for FMC_PMEM2 register ******************/
4374 #define FMC_PMEM2_MEMSET2 0x000000FFU
4375 #define FMC_PMEM2_MEMSET2_0 0x00000001U
4376 #define FMC_PMEM2_MEMSET2_1 0x00000002U
4377 #define FMC_PMEM2_MEMSET2_2 0x00000004U
4378 #define FMC_PMEM2_MEMSET2_3 0x00000008U
4379 #define FMC_PMEM2_MEMSET2_4 0x00000010U
4380 #define FMC_PMEM2_MEMSET2_5 0x00000020U
4381 #define FMC_PMEM2_MEMSET2_6 0x00000040U
4382 #define FMC_PMEM2_MEMSET2_7 0x00000080U
4384 #define FMC_PMEM2_MEMWAIT2 0x0000FF00U
4385 #define FMC_PMEM2_MEMWAIT2_0 0x00000100U
4386 #define FMC_PMEM2_MEMWAIT2_1 0x00000200U
4387 #define FMC_PMEM2_MEMWAIT2_2 0x00000400U
4388 #define FMC_PMEM2_MEMWAIT2_3 0x00000800U
4389 #define FMC_PMEM2_MEMWAIT2_4 0x00001000U
4390 #define FMC_PMEM2_MEMWAIT2_5 0x00002000U
4391 #define FMC_PMEM2_MEMWAIT2_6 0x00004000U
4392 #define FMC_PMEM2_MEMWAIT2_7 0x00008000U
4394 #define FMC_PMEM2_MEMHOLD2 0x00FF0000U
4395 #define FMC_PMEM2_MEMHOLD2_0 0x00010000U
4396 #define FMC_PMEM2_MEMHOLD2_1 0x00020000U
4397 #define FMC_PMEM2_MEMHOLD2_2 0x00040000U
4398 #define FMC_PMEM2_MEMHOLD2_3 0x00080000U
4399 #define FMC_PMEM2_MEMHOLD2_4 0x00100000U
4400 #define FMC_PMEM2_MEMHOLD2_5 0x00200000U
4401 #define FMC_PMEM2_MEMHOLD2_6 0x00400000U
4402 #define FMC_PMEM2_MEMHOLD2_7 0x00800000U
4404 #define FMC_PMEM2_MEMHIZ2 0xFF000000U
4405 #define FMC_PMEM2_MEMHIZ2_0 0x01000000U
4406 #define FMC_PMEM2_MEMHIZ2_1 0x02000000U
4407 #define FMC_PMEM2_MEMHIZ2_2 0x04000000U
4408 #define FMC_PMEM2_MEMHIZ2_3 0x08000000U
4409 #define FMC_PMEM2_MEMHIZ2_4 0x10000000U
4410 #define FMC_PMEM2_MEMHIZ2_5 0x20000000U
4411 #define FMC_PMEM2_MEMHIZ2_6 0x40000000U
4412 #define FMC_PMEM2_MEMHIZ2_7 0x80000000U
4414 /****************** Bit definition for FMC_PMEM3 register ******************/
4415 #define FMC_PMEM3_MEMSET3 0x000000FFU
4416 #define FMC_PMEM3_MEMSET3_0 0x00000001U
4417 #define FMC_PMEM3_MEMSET3_1 0x00000002U
4418 #define FMC_PMEM3_MEMSET3_2 0x00000004U
4419 #define FMC_PMEM3_MEMSET3_3 0x00000008U
4420 #define FMC_PMEM3_MEMSET3_4 0x00000010U
4421 #define FMC_PMEM3_MEMSET3_5 0x00000020U
4422 #define FMC_PMEM3_MEMSET3_6 0x00000040U
4423 #define FMC_PMEM3_MEMSET3_7 0x00000080U
4425 #define FMC_PMEM3_MEMWAIT3 0x0000FF00U
4426 #define FMC_PMEM3_MEMWAIT3_0 0x00000100U
4427 #define FMC_PMEM3_MEMWAIT3_1 0x00000200U
4428 #define FMC_PMEM3_MEMWAIT3_2 0x00000400U
4429 #define FMC_PMEM3_MEMWAIT3_3 0x00000800U
4430 #define FMC_PMEM3_MEMWAIT3_4 0x00001000U
4431 #define FMC_PMEM3_MEMWAIT3_5 0x00002000U
4432 #define FMC_PMEM3_MEMWAIT3_6 0x00004000U
4433 #define FMC_PMEM3_MEMWAIT3_7 0x00008000U
4435 #define FMC_PMEM3_MEMHOLD3 0x00FF0000U
4436 #define FMC_PMEM3_MEMHOLD3_0 0x00010000U
4437 #define FMC_PMEM3_MEMHOLD3_1 0x00020000U
4438 #define FMC_PMEM3_MEMHOLD3_2 0x00040000U
4439 #define FMC_PMEM3_MEMHOLD3_3 0x00080000U
4440 #define FMC_PMEM3_MEMHOLD3_4 0x00100000U
4441 #define FMC_PMEM3_MEMHOLD3_5 0x00200000U
4442 #define FMC_PMEM3_MEMHOLD3_6 0x00400000U
4443 #define FMC_PMEM3_MEMHOLD3_7 0x00800000U
4445 #define FMC_PMEM3_MEMHIZ3 0xFF000000U
4446 #define FMC_PMEM3_MEMHIZ3_0 0x01000000U
4447 #define FMC_PMEM3_MEMHIZ3_1 0x02000000U
4448 #define FMC_PMEM3_MEMHIZ3_2 0x04000000U
4449 #define FMC_PMEM3_MEMHIZ3_3 0x08000000U
4450 #define FMC_PMEM3_MEMHIZ3_4 0x10000000U
4451 #define FMC_PMEM3_MEMHIZ3_5 0x20000000U
4452 #define FMC_PMEM3_MEMHIZ3_6 0x40000000U
4453 #define FMC_PMEM3_MEMHIZ3_7 0x80000000U
4455 /****************** Bit definition for FMC_PMEM4 register ******************/
4456 #define FMC_PMEM4_MEMSET4 0x000000FFU
4457 #define FMC_PMEM4_MEMSET4_0 0x00000001U
4458 #define FMC_PMEM4_MEMSET4_1 0x00000002U
4459 #define FMC_PMEM4_MEMSET4_2 0x00000004U
4460 #define FMC_PMEM4_MEMSET4_3 0x00000008U
4461 #define FMC_PMEM4_MEMSET4_4 0x00000010U
4462 #define FMC_PMEM4_MEMSET4_5 0x00000020U
4463 #define FMC_PMEM4_MEMSET4_6 0x00000040U
4464 #define FMC_PMEM4_MEMSET4_7 0x00000080U
4466 #define FMC_PMEM4_MEMWAIT4 0x0000FF00U
4467 #define FMC_PMEM4_MEMWAIT4_0 0x00000100U
4468 #define FMC_PMEM4_MEMWAIT4_1 0x00000200U
4469 #define FMC_PMEM4_MEMWAIT4_2 0x00000400U
4470 #define FMC_PMEM4_MEMWAIT4_3 0x00000800U
4471 #define FMC_PMEM4_MEMWAIT4_4 0x00001000U
4472 #define FMC_PMEM4_MEMWAIT4_5 0x00002000U
4473 #define FMC_PMEM4_MEMWAIT4_6 0x00004000U
4474 #define FMC_PMEM4_MEMWAIT4_7 0x00008000U
4476 #define FMC_PMEM4_MEMHOLD4 0x00FF0000U
4477 #define FMC_PMEM4_MEMHOLD4_0 0x00010000U
4478 #define FMC_PMEM4_MEMHOLD4_1 0x00020000U
4479 #define FMC_PMEM4_MEMHOLD4_2 0x00040000U
4480 #define FMC_PMEM4_MEMHOLD4_3 0x00080000U
4481 #define FMC_PMEM4_MEMHOLD4_4 0x00100000U
4482 #define FMC_PMEM4_MEMHOLD4_5 0x00200000U
4483 #define FMC_PMEM4_MEMHOLD4_6 0x00400000U
4484 #define FMC_PMEM4_MEMHOLD4_7 0x00800000U
4486 #define FMC_PMEM4_MEMHIZ4 0xFF000000U
4487 #define FMC_PMEM4_MEMHIZ4_0 0x01000000U
4488 #define FMC_PMEM4_MEMHIZ4_1 0x02000000U
4489 #define FMC_PMEM4_MEMHIZ4_2 0x04000000U
4490 #define FMC_PMEM4_MEMHIZ4_3 0x08000000U
4491 #define FMC_PMEM4_MEMHIZ4_4 0x10000000U
4492 #define FMC_PMEM4_MEMHIZ4_5 0x20000000U
4493 #define FMC_PMEM4_MEMHIZ4_6 0x40000000U
4494 #define FMC_PMEM4_MEMHIZ4_7 0x80000000U
4496 /****************** Bit definition for FMC_PATT2 register ******************/
4497 #define FMC_PATT2_ATTSET2 0x000000FFU
4498 #define FMC_PATT2_ATTSET2_0 0x00000001U
4499 #define FMC_PATT2_ATTSET2_1 0x00000002U
4500 #define FMC_PATT2_ATTSET2_2 0x00000004U
4501 #define FMC_PATT2_ATTSET2_3 0x00000008U
4502 #define FMC_PATT2_ATTSET2_4 0x00000010U
4503 #define FMC_PATT2_ATTSET2_5 0x00000020U
4504 #define FMC_PATT2_ATTSET2_6 0x00000040U
4505 #define FMC_PATT2_ATTSET2_7 0x00000080U
4507 #define FMC_PATT2_ATTWAIT2 0x0000FF00U
4508 #define FMC_PATT2_ATTWAIT2_0 0x00000100U
4509 #define FMC_PATT2_ATTWAIT2_1 0x00000200U
4510 #define FMC_PATT2_ATTWAIT2_2 0x00000400U
4511 #define FMC_PATT2_ATTWAIT2_3 0x00000800U
4512 #define FMC_PATT2_ATTWAIT2_4 0x00001000U
4513 #define FMC_PATT2_ATTWAIT2_5 0x00002000U
4514 #define FMC_PATT2_ATTWAIT2_6 0x00004000U
4515 #define FMC_PATT2_ATTWAIT2_7 0x00008000U
4517 #define FMC_PATT2_ATTHOLD2 0x00FF0000U
4518 #define FMC_PATT2_ATTHOLD2_0 0x00010000U
4519 #define FMC_PATT2_ATTHOLD2_1 0x00020000U
4520 #define FMC_PATT2_ATTHOLD2_2 0x00040000U
4521 #define FMC_PATT2_ATTHOLD2_3 0x00080000U
4522 #define FMC_PATT2_ATTHOLD2_4 0x00100000U
4523 #define FMC_PATT2_ATTHOLD2_5 0x00200000U
4524 #define FMC_PATT2_ATTHOLD2_6 0x00400000U
4525 #define FMC_PATT2_ATTHOLD2_7 0x00800000U
4527 #define FMC_PATT2_ATTHIZ2 0xFF000000U
4528 #define FMC_PATT2_ATTHIZ2_0 0x01000000U
4529 #define FMC_PATT2_ATTHIZ2_1 0x02000000U
4530 #define FMC_PATT2_ATTHIZ2_2 0x04000000U
4531 #define FMC_PATT2_ATTHIZ2_3 0x08000000U
4532 #define FMC_PATT2_ATTHIZ2_4 0x10000000U
4533 #define FMC_PATT2_ATTHIZ2_5 0x20000000U
4534 #define FMC_PATT2_ATTHIZ2_6 0x40000000U
4535 #define FMC_PATT2_ATTHIZ2_7 0x80000000U
4537 /****************** Bit definition for FMC_PATT3 register ******************/
4538 #define FMC_PATT3_ATTSET3 0x000000FFU
4539 #define FMC_PATT3_ATTSET3_0 0x00000001U
4540 #define FMC_PATT3_ATTSET3_1 0x00000002U
4541 #define FMC_PATT3_ATTSET3_2 0x00000004U
4542 #define FMC_PATT3_ATTSET3_3 0x00000008U
4543 #define FMC_PATT3_ATTSET3_4 0x00000010U
4544 #define FMC_PATT3_ATTSET3_5 0x00000020U
4545 #define FMC_PATT3_ATTSET3_6 0x00000040U
4546 #define FMC_PATT3_ATTSET3_7 0x00000080U
4548 #define FMC_PATT3_ATTWAIT3 0x0000FF00U
4549 #define FMC_PATT3_ATTWAIT3_0 0x00000100U
4550 #define FMC_PATT3_ATTWAIT3_1 0x00000200U
4551 #define FMC_PATT3_ATTWAIT3_2 0x00000400U
4552 #define FMC_PATT3_ATTWAIT3_3 0x00000800U
4553 #define FMC_PATT3_ATTWAIT3_4 0x00001000U
4554 #define FMC_PATT3_ATTWAIT3_5 0x00002000U
4555 #define FMC_PATT3_ATTWAIT3_6 0x00004000U
4556 #define FMC_PATT3_ATTWAIT3_7 0x00008000U
4558 #define FMC_PATT3_ATTHOLD3 0x00FF0000U
4559 #define FMC_PATT3_ATTHOLD3_0 0x00010000U
4560 #define FMC_PATT3_ATTHOLD3_1 0x00020000U
4561 #define FMC_PATT3_ATTHOLD3_2 0x00040000U
4562 #define FMC_PATT3_ATTHOLD3_3 0x00080000U
4563 #define FMC_PATT3_ATTHOLD3_4 0x00100000U
4564 #define FMC_PATT3_ATTHOLD3_5 0x00200000U
4565 #define FMC_PATT3_ATTHOLD3_6 0x00400000U
4566 #define FMC_PATT3_ATTHOLD3_7 0x00800000U
4568 #define FMC_PATT3_ATTHIZ3 0xFF000000U
4569 #define FMC_PATT3_ATTHIZ3_0 0x01000000U
4570 #define FMC_PATT3_ATTHIZ3_1 0x02000000U
4571 #define FMC_PATT3_ATTHIZ3_2 0x04000000U
4572 #define FMC_PATT3_ATTHIZ3_3 0x08000000U
4573 #define FMC_PATT3_ATTHIZ3_4 0x10000000U
4574 #define FMC_PATT3_ATTHIZ3_5 0x20000000U
4575 #define FMC_PATT3_ATTHIZ3_6 0x40000000U
4576 #define FMC_PATT3_ATTHIZ3_7 0x80000000U
4578 /****************** Bit definition for FMC_PATT4 register ******************/
4579 #define FMC_PATT4_ATTSET4 0x000000FFU
4580 #define FMC_PATT4_ATTSET4_0 0x00000001U
4581 #define FMC_PATT4_ATTSET4_1 0x00000002U
4582 #define FMC_PATT4_ATTSET4_2 0x00000004U
4583 #define FMC_PATT4_ATTSET4_3 0x00000008U
4584 #define FMC_PATT4_ATTSET4_4 0x00000010U
4585 #define FMC_PATT4_ATTSET4_5 0x00000020U
4586 #define FMC_PATT4_ATTSET4_6 0x00000040U
4587 #define FMC_PATT4_ATTSET4_7 0x00000080U
4589 #define FMC_PATT4_ATTWAIT4 0x0000FF00U
4590 #define FMC_PATT4_ATTWAIT4_0 0x00000100U
4591 #define FMC_PATT4_ATTWAIT4_1 0x00000200U
4592 #define FMC_PATT4_ATTWAIT4_2 0x00000400U
4593 #define FMC_PATT4_ATTWAIT4_3 0x00000800U
4594 #define FMC_PATT4_ATTWAIT4_4 0x00001000U
4595 #define FMC_PATT4_ATTWAIT4_5 0x00002000U
4596 #define FMC_PATT4_ATTWAIT4_6 0x00004000U
4597 #define FMC_PATT4_ATTWAIT4_7 0x00008000U
4599 #define FMC_PATT4_ATTHOLD4 0x00FF0000U
4600 #define FMC_PATT4_ATTHOLD4_0 0x00010000U
4601 #define FMC_PATT4_ATTHOLD4_1 0x00020000U
4602 #define FMC_PATT4_ATTHOLD4_2 0x00040000U
4603 #define FMC_PATT4_ATTHOLD4_3 0x00080000U
4604 #define FMC_PATT4_ATTHOLD4_4 0x00100000U
4605 #define FMC_PATT4_ATTHOLD4_5 0x00200000U
4606 #define FMC_PATT4_ATTHOLD4_6 0x00400000U
4607 #define FMC_PATT4_ATTHOLD4_7 0x00800000U
4609 #define FMC_PATT4_ATTHIZ4 0xFF000000U
4610 #define FMC_PATT4_ATTHIZ4_0 0x01000000U
4611 #define FMC_PATT4_ATTHIZ4_1 0x02000000U
4612 #define FMC_PATT4_ATTHIZ4_2 0x04000000U
4613 #define FMC_PATT4_ATTHIZ4_3 0x08000000U
4614 #define FMC_PATT4_ATTHIZ4_4 0x10000000U
4615 #define FMC_PATT4_ATTHIZ4_5 0x20000000U
4616 #define FMC_PATT4_ATTHIZ4_6 0x40000000U
4617 #define FMC_PATT4_ATTHIZ4_7 0x80000000U
4619 /****************** Bit definition for FMC_PIO4 register *******************/
4620 #define FMC_PIO4_IOSET4 0x000000FFU
4621 #define FMC_PIO4_IOSET4_0 0x00000001U
4622 #define FMC_PIO4_IOSET4_1 0x00000002U
4623 #define FMC_PIO4_IOSET4_2 0x00000004U
4624 #define FMC_PIO4_IOSET4_3 0x00000008U
4625 #define FMC_PIO4_IOSET4_4 0x00000010U
4626 #define FMC_PIO4_IOSET4_5 0x00000020U
4627 #define FMC_PIO4_IOSET4_6 0x00000040U
4628 #define FMC_PIO4_IOSET4_7 0x00000080U
4630 #define FMC_PIO4_IOWAIT4 0x0000FF00U
4631 #define FMC_PIO4_IOWAIT4_0 0x00000100U
4632 #define FMC_PIO4_IOWAIT4_1 0x00000200U
4633 #define FMC_PIO4_IOWAIT4_2 0x00000400U
4634 #define FMC_PIO4_IOWAIT4_3 0x00000800U
4635 #define FMC_PIO4_IOWAIT4_4 0x00001000U
4636 #define FMC_PIO4_IOWAIT4_5 0x00002000U
4637 #define FMC_PIO4_IOWAIT4_6 0x00004000U
4638 #define FMC_PIO4_IOWAIT4_7 0x00008000U
4640 #define FMC_PIO4_IOHOLD4 0x00FF0000U
4641 #define FMC_PIO4_IOHOLD4_0 0x00010000U
4642 #define FMC_PIO4_IOHOLD4_1 0x00020000U
4643 #define FMC_PIO4_IOHOLD4_2 0x00040000U
4644 #define FMC_PIO4_IOHOLD4_3 0x00080000U
4645 #define FMC_PIO4_IOHOLD4_4 0x00100000U
4646 #define FMC_PIO4_IOHOLD4_5 0x00200000U
4647 #define FMC_PIO4_IOHOLD4_6 0x00400000U
4648 #define FMC_PIO4_IOHOLD4_7 0x00800000U
4650 #define FMC_PIO4_IOHIZ4 0xFF000000U
4651 #define FMC_PIO4_IOHIZ4_0 0x01000000U
4652 #define FMC_PIO4_IOHIZ4_1 0x02000000U
4653 #define FMC_PIO4_IOHIZ4_2 0x04000000U
4654 #define FMC_PIO4_IOHIZ4_3 0x08000000U
4655 #define FMC_PIO4_IOHIZ4_4 0x10000000U
4656 #define FMC_PIO4_IOHIZ4_5 0x20000000U
4657 #define FMC_PIO4_IOHIZ4_6 0x40000000U
4658 #define FMC_PIO4_IOHIZ4_7 0x80000000U
4660 /****************** Bit definition for FMC_ECCR2 register ******************/
4661 #define FMC_ECCR2_ECC2 0xFFFFFFFFU
4663 /****************** Bit definition for FMC_ECCR3 register ******************/
4664 #define FMC_ECCR3_ECC3 0xFFFFFFFFU
4666 /****************** Bit definition for FMC_SDCR1 register ******************/
4667 #define FMC_SDCR1_NC 0x00000003U
4668 #define FMC_SDCR1_NC_0 0x00000001U
4669 #define FMC_SDCR1_NC_1 0x00000002U
4671 #define FMC_SDCR1_NR 0x0000000CU
4672 #define FMC_SDCR1_NR_0 0x00000004U
4673 #define FMC_SDCR1_NR_1 0x00000008U
4675 #define FMC_SDCR1_MWID 0x00000030U
4676 #define FMC_SDCR1_MWID_0 0x00000010U
4677 #define FMC_SDCR1_MWID_1 0x00000020U
4679 #define FMC_SDCR1_NB 0x00000040U
4681 #define FMC_SDCR1_CAS 0x00000180U
4682 #define FMC_SDCR1_CAS_0 0x00000080U
4683 #define FMC_SDCR1_CAS_1 0x00000100U
4685 #define FMC_SDCR1_WP 0x00000200U
4687 #define FMC_SDCR1_SDCLK 0x00000C00U
4688 #define FMC_SDCR1_SDCLK_0 0x00000400U
4689 #define FMC_SDCR1_SDCLK_1 0x00000800U
4691 #define FMC_SDCR1_RBURST 0x00001000U
4693 #define FMC_SDCR1_RPIPE 0x00006000U
4694 #define FMC_SDCR1_RPIPE_0 0x00002000U
4695 #define FMC_SDCR1_RPIPE_1 0x00004000U
4697 /****************** Bit definition for FMC_SDCR2 register ******************/
4698 #define FMC_SDCR2_NC 0x00000003U
4699 #define FMC_SDCR2_NC_0 0x00000001U
4700 #define FMC_SDCR2_NC_1 0x00000002U
4702 #define FMC_SDCR2_NR 0x0000000CU
4703 #define FMC_SDCR2_NR_0 0x00000004U
4704 #define FMC_SDCR2_NR_1 0x00000008U
4706 #define FMC_SDCR2_MWID 0x00000030U
4707 #define FMC_SDCR2_MWID_0 0x00000010U
4708 #define FMC_SDCR2_MWID_1 0x00000020U
4710 #define FMC_SDCR2_NB 0x00000040U
4712 #define FMC_SDCR2_CAS 0x00000180U
4713 #define FMC_SDCR2_CAS_0 0x00000080U
4714 #define FMC_SDCR2_CAS_1 0x00000100U
4716 #define FMC_SDCR2_WP 0x00000200U
4718 #define FMC_SDCR2_SDCLK 0x00000C00U
4719 #define FMC_SDCR2_SDCLK_0 0x00000400U
4720 #define FMC_SDCR2_SDCLK_1 0x00000800U
4722 #define FMC_SDCR2_RBURST 0x00001000U
4724 #define FMC_SDCR2_RPIPE 0x00006000U
4725 #define FMC_SDCR2_RPIPE_0 0x00002000U
4726 #define FMC_SDCR2_RPIPE_1 0x00004000U
4728 /****************** Bit definition for FMC_SDTR1 register ******************/
4729 #define FMC_SDTR1_TMRD 0x0000000FU
4730 #define FMC_SDTR1_TMRD_0 0x00000001U
4731 #define FMC_SDTR1_TMRD_1 0x00000002U
4732 #define FMC_SDTR1_TMRD_2 0x00000004U
4733 #define FMC_SDTR1_TMRD_3 0x00000008U
4735 #define FMC_SDTR1_TXSR 0x000000F0U
4736 #define FMC_SDTR1_TXSR_0 0x00000010U
4737 #define FMC_SDTR1_TXSR_1 0x00000020U
4738 #define FMC_SDTR1_TXSR_2 0x00000040U
4739 #define FMC_SDTR1_TXSR_3 0x00000080U
4741 #define FMC_SDTR1_TRAS 0x00000F00U
4742 #define FMC_SDTR1_TRAS_0 0x00000100U
4743 #define FMC_SDTR1_TRAS_1 0x00000200U
4744 #define FMC_SDTR1_TRAS_2 0x00000400U
4745 #define FMC_SDTR1_TRAS_3 0x00000800U
4747 #define FMC_SDTR1_TRC 0x0000F000U
4748 #define FMC_SDTR1_TRC_0 0x00001000U
4749 #define FMC_SDTR1_TRC_1 0x00002000U
4750 #define FMC_SDTR1_TRC_2 0x00004000U
4752 #define FMC_SDTR1_TWR 0x000F0000U
4753 #define FMC_SDTR1_TWR_0 0x00010000U
4754 #define FMC_SDTR1_TWR_1 0x00020000U
4755 #define FMC_SDTR1_TWR_2 0x00040000U
4757 #define FMC_SDTR1_TRP 0x00F00000U
4758 #define FMC_SDTR1_TRP_0 0x00100000U
4759 #define FMC_SDTR1_TRP_1 0x00200000U
4760 #define FMC_SDTR1_TRP_2 0x00400000U
4762 #define FMC_SDTR1_TRCD 0x0F000000U
4763 #define FMC_SDTR1_TRCD_0 0x01000000U
4764 #define FMC_SDTR1_TRCD_1 0x02000000U
4765 #define FMC_SDTR1_TRCD_2 0x04000000U
4767 /****************** Bit definition for FMC_SDTR2 register ******************/
4768 #define FMC_SDTR2_TMRD 0x0000000FU
4769 #define FMC_SDTR2_TMRD_0 0x00000001U
4770 #define FMC_SDTR2_TMRD_1 0x00000002U
4771 #define FMC_SDTR2_TMRD_2 0x00000004U
4772 #define FMC_SDTR2_TMRD_3 0x00000008U
4774 #define FMC_SDTR2_TXSR 0x000000F0U
4775 #define FMC_SDTR2_TXSR_0 0x00000010U
4776 #define FMC_SDTR2_TXSR_1 0x00000020U
4777 #define FMC_SDTR2_TXSR_2 0x00000040U
4778 #define FMC_SDTR2_TXSR_3 0x00000080U
4780 #define FMC_SDTR2_TRAS 0x00000F00U
4781 #define FMC_SDTR2_TRAS_0 0x00000100U
4782 #define FMC_SDTR2_TRAS_1 0x00000200U
4783 #define FMC_SDTR2_TRAS_2 0x00000400U
4784 #define FMC_SDTR2_TRAS_3 0x00000800U
4786 #define FMC_SDTR2_TRC 0x0000F000U
4787 #define FMC_SDTR2_TRC_0 0x00001000U
4788 #define FMC_SDTR2_TRC_1 0x00002000U
4789 #define FMC_SDTR2_TRC_2 0x00004000U
4791 #define FMC_SDTR2_TWR 0x000F0000U
4792 #define FMC_SDTR2_TWR_0 0x00010000U
4793 #define FMC_SDTR2_TWR_1 0x00020000U
4794 #define FMC_SDTR2_TWR_2 0x00040000U
4796 #define FMC_SDTR2_TRP 0x00F00000U
4797 #define FMC_SDTR2_TRP_0 0x00100000U
4798 #define FMC_SDTR2_TRP_1 0x00200000U
4799 #define FMC_SDTR2_TRP_2 0x00400000U
4801 #define FMC_SDTR2_TRCD 0x0F000000U
4802 #define FMC_SDTR2_TRCD_0 0x01000000U
4803 #define FMC_SDTR2_TRCD_1 0x02000000U
4804 #define FMC_SDTR2_TRCD_2 0x04000000U
4806 /****************** Bit definition for FMC_SDCMR register ******************/
4807 #define FMC_SDCMR_MODE 0x00000007U
4808 #define FMC_SDCMR_MODE_0 0x00000001U
4809 #define FMC_SDCMR_MODE_1 0x00000002U
4810 #define FMC_SDCMR_MODE_2 0x00000004U
4812 #define FMC_SDCMR_CTB2 0x00000008U
4814 #define FMC_SDCMR_CTB1 0x00000010U
4816 #define FMC_SDCMR_NRFS 0x000001E0U
4817 #define FMC_SDCMR_NRFS_0 0x00000020U
4818 #define FMC_SDCMR_NRFS_1 0x00000040U
4819 #define FMC_SDCMR_NRFS_2 0x00000080U
4820 #define FMC_SDCMR_NRFS_3 0x00000100U
4822 #define FMC_SDCMR_MRD 0x003FFE00U
4824 /****************** Bit definition for FMC_SDRTR register ******************/
4825 #define FMC_SDRTR_CRE 0x00000001U
4827 #define FMC_SDRTR_COUNT 0x00003FFEU
4829 #define FMC_SDRTR_REIE 0x00004000U
4831 /****************** Bit definition for FMC_SDSR register ******************/
4832 #define FMC_SDSR_RE 0x00000001U
4834 #define FMC_SDSR_MODES1 0x00000006U
4835 #define FMC_SDSR_MODES1_0 0x00000002U
4836 #define FMC_SDSR_MODES1_1 0x00000004U
4838 #define FMC_SDSR_MODES2 0x00000018U
4839 #define FMC_SDSR_MODES2_0 0x00000008U
4840 #define FMC_SDSR_MODES2_1 0x00000010U
4841 #define FMC_SDSR_BUSY 0x00000020U
4845 /******************************************************************************/
4846 /* */
4847 /* General Purpose I/O */
4848 /* */
4849 /******************************************************************************/
4850 /****************** Bits definition for GPIO_MODER register *****************/
4851 #define GPIO_MODER_MODER0 0x00000003U
4852 #define GPIO_MODER_MODER0_0 0x00000001U
4853 #define GPIO_MODER_MODER0_1 0x00000002U
4854 
4855 #define GPIO_MODER_MODER1 0x0000000CU
4856 #define GPIO_MODER_MODER1_0 0x00000004U
4857 #define GPIO_MODER_MODER1_1 0x00000008U
4858 
4859 #define GPIO_MODER_MODER2 0x00000030U
4860 #define GPIO_MODER_MODER2_0 0x00000010U
4861 #define GPIO_MODER_MODER2_1 0x00000020U
4862 
4863 #define GPIO_MODER_MODER3 0x000000C0U
4864 #define GPIO_MODER_MODER3_0 0x00000040U
4865 #define GPIO_MODER_MODER3_1 0x00000080U
4866 
4867 #define GPIO_MODER_MODER4 0x00000300U
4868 #define GPIO_MODER_MODER4_0 0x00000100U
4869 #define GPIO_MODER_MODER4_1 0x00000200U
4870 
4871 #define GPIO_MODER_MODER5 0x00000C00U
4872 #define GPIO_MODER_MODER5_0 0x00000400U
4873 #define GPIO_MODER_MODER5_1 0x00000800U
4874 
4875 #define GPIO_MODER_MODER6 0x00003000U
4876 #define GPIO_MODER_MODER6_0 0x00001000U
4877 #define GPIO_MODER_MODER6_1 0x00002000U
4878 
4879 #define GPIO_MODER_MODER7 0x0000C000U
4880 #define GPIO_MODER_MODER7_0 0x00004000U
4881 #define GPIO_MODER_MODER7_1 0x00008000U
4882 
4883 #define GPIO_MODER_MODER8 0x00030000U
4884 #define GPIO_MODER_MODER8_0 0x00010000U
4885 #define GPIO_MODER_MODER8_1 0x00020000U
4886 
4887 #define GPIO_MODER_MODER9 0x000C0000U
4888 #define GPIO_MODER_MODER9_0 0x00040000U
4889 #define GPIO_MODER_MODER9_1 0x00080000U
4890 
4891 #define GPIO_MODER_MODER10 0x00300000U
4892 #define GPIO_MODER_MODER10_0 0x00100000U
4893 #define GPIO_MODER_MODER10_1 0x00200000U
4894 
4895 #define GPIO_MODER_MODER11 0x00C00000U
4896 #define GPIO_MODER_MODER11_0 0x00400000U
4897 #define GPIO_MODER_MODER11_1 0x00800000U
4898 
4899 #define GPIO_MODER_MODER12 0x03000000U
4900 #define GPIO_MODER_MODER12_0 0x01000000U
4901 #define GPIO_MODER_MODER12_1 0x02000000U
4902 
4903 #define GPIO_MODER_MODER13 0x0C000000U
4904 #define GPIO_MODER_MODER13_0 0x04000000U
4905 #define GPIO_MODER_MODER13_1 0x08000000U
4906 
4907 #define GPIO_MODER_MODER14 0x30000000U
4908 #define GPIO_MODER_MODER14_0 0x10000000U
4909 #define GPIO_MODER_MODER14_1 0x20000000U
4910 
4911 #define GPIO_MODER_MODER15 0xC0000000U
4912 #define GPIO_MODER_MODER15_0 0x40000000U
4913 #define GPIO_MODER_MODER15_1 0x80000000U
4914 
4915 /****************** Bits definition for GPIO_OTYPER register ****************/
4916 #define GPIO_OTYPER_OT_0 0x00000001U
4917 #define GPIO_OTYPER_OT_1 0x00000002U
4918 #define GPIO_OTYPER_OT_2 0x00000004U
4919 #define GPIO_OTYPER_OT_3 0x00000008U
4920 #define GPIO_OTYPER_OT_4 0x00000010U
4921 #define GPIO_OTYPER_OT_5 0x00000020U
4922 #define GPIO_OTYPER_OT_6 0x00000040U
4923 #define GPIO_OTYPER_OT_7 0x00000080U
4924 #define GPIO_OTYPER_OT_8 0x00000100U
4925 #define GPIO_OTYPER_OT_9 0x00000200U
4926 #define GPIO_OTYPER_OT_10 0x00000400U
4927 #define GPIO_OTYPER_OT_11 0x00000800U
4928 #define GPIO_OTYPER_OT_12 0x00001000U
4929 #define GPIO_OTYPER_OT_13 0x00002000U
4930 #define GPIO_OTYPER_OT_14 0x00004000U
4931 #define GPIO_OTYPER_OT_15 0x00008000U
4932 
4933 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4934 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4935 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4936 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4937 
4938 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4939 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4940 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4941 
4942 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4943 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4944 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4945 
4946 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4947 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4948 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4949 
4950 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4951 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4952 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4953 
4954 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4955 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4956 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4957 
4958 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4959 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4960 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4961 
4962 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4963 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4964 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4965 
4966 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4967 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4968 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4969 
4970 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4971 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4972 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4973 
4974 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4975 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4976 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4977 
4978 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4979 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4980 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4981 
4982 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4983 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4984 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4985 
4986 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4987 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4988 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4989 
4990 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4991 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4992 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4993 
4994 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4995 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4996 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4997 
4998 /****************** Bits definition for GPIO_PUPDR register *****************/
4999 #define GPIO_PUPDR_PUPDR0 0x00000003U
5000 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
5001 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
5002 
5003 #define GPIO_PUPDR_PUPDR1 0x0000000CU
5004 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
5005 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
5006 
5007 #define GPIO_PUPDR_PUPDR2 0x00000030U
5008 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
5009 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
5010 
5011 #define GPIO_PUPDR_PUPDR3 0x000000C0U
5012 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
5013 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
5014 
5015 #define GPIO_PUPDR_PUPDR4 0x00000300U
5016 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
5017 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
5018 
5019 #define GPIO_PUPDR_PUPDR5 0x00000C00U
5020 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
5021 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
5022 
5023 #define GPIO_PUPDR_PUPDR6 0x00003000U
5024 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
5025 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
5026 
5027 #define GPIO_PUPDR_PUPDR7 0x0000C000U
5028 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
5029 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
5030 
5031 #define GPIO_PUPDR_PUPDR8 0x00030000U
5032 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
5033 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
5034 
5035 #define GPIO_PUPDR_PUPDR9 0x000C0000U
5036 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
5037 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
5038 
5039 #define GPIO_PUPDR_PUPDR10 0x00300000U
5040 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
5041 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
5042 
5043 #define GPIO_PUPDR_PUPDR11 0x00C00000U
5044 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
5045 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
5046 
5047 #define GPIO_PUPDR_PUPDR12 0x03000000U
5048 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
5049 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
5050 
5051 #define GPIO_PUPDR_PUPDR13 0x0C000000U
5052 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
5053 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
5054 
5055 #define GPIO_PUPDR_PUPDR14 0x30000000U
5056 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
5057 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
5058 
5059 #define GPIO_PUPDR_PUPDR15 0xC0000000U
5060 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
5061 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
5062 
5063 /****************** Bits definition for GPIO_IDR register *******************/
5064 #define GPIO_IDR_IDR_0 0x00000001U
5065 #define GPIO_IDR_IDR_1 0x00000002U
5066 #define GPIO_IDR_IDR_2 0x00000004U
5067 #define GPIO_IDR_IDR_3 0x00000008U
5068 #define GPIO_IDR_IDR_4 0x00000010U
5069 #define GPIO_IDR_IDR_5 0x00000020U
5070 #define GPIO_IDR_IDR_6 0x00000040U
5071 #define GPIO_IDR_IDR_7 0x00000080U
5072 #define GPIO_IDR_IDR_8 0x00000100U
5073 #define GPIO_IDR_IDR_9 0x00000200U
5074 #define GPIO_IDR_IDR_10 0x00000400U
5075 #define GPIO_IDR_IDR_11 0x00000800U
5076 #define GPIO_IDR_IDR_12 0x00001000U
5077 #define GPIO_IDR_IDR_13 0x00002000U
5078 #define GPIO_IDR_IDR_14 0x00004000U
5079 #define GPIO_IDR_IDR_15 0x00008000U
5080 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5081 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
5082 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
5083 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
5084 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
5085 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
5086 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
5087 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
5088 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
5089 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
5090 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
5091 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
5092 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
5093 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
5094 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
5095 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
5096 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
5097 
5098 /****************** Bits definition for GPIO_ODR register *******************/
5099 #define GPIO_ODR_ODR_0 0x00000001U
5100 #define GPIO_ODR_ODR_1 0x00000002U
5101 #define GPIO_ODR_ODR_2 0x00000004U
5102 #define GPIO_ODR_ODR_3 0x00000008U
5103 #define GPIO_ODR_ODR_4 0x00000010U
5104 #define GPIO_ODR_ODR_5 0x00000020U
5105 #define GPIO_ODR_ODR_6 0x00000040U
5106 #define GPIO_ODR_ODR_7 0x00000080U
5107 #define GPIO_ODR_ODR_8 0x00000100U
5108 #define GPIO_ODR_ODR_9 0x00000200U
5109 #define GPIO_ODR_ODR_10 0x00000400U
5110 #define GPIO_ODR_ODR_11 0x00000800U
5111 #define GPIO_ODR_ODR_12 0x00001000U
5112 #define GPIO_ODR_ODR_13 0x00002000U
5113 #define GPIO_ODR_ODR_14 0x00004000U
5114 #define GPIO_ODR_ODR_15 0x00008000U
5115 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
5116 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
5117 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
5118 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
5119 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
5120 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
5121 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
5122 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
5123 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
5124 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
5125 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
5126 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
5127 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
5128 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
5129 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
5130 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
5131 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
5132 
5133 /****************** Bits definition for GPIO_BSRR register ******************/
5134 #define GPIO_BSRR_BS_0 0x00000001U
5135 #define GPIO_BSRR_BS_1 0x00000002U
5136 #define GPIO_BSRR_BS_2 0x00000004U
5137 #define GPIO_BSRR_BS_3 0x00000008U
5138 #define GPIO_BSRR_BS_4 0x00000010U
5139 #define GPIO_BSRR_BS_5 0x00000020U
5140 #define GPIO_BSRR_BS_6 0x00000040U
5141 #define GPIO_BSRR_BS_7 0x00000080U
5142 #define GPIO_BSRR_BS_8 0x00000100U
5143 #define GPIO_BSRR_BS_9 0x00000200U
5144 #define GPIO_BSRR_BS_10 0x00000400U
5145 #define GPIO_BSRR_BS_11 0x00000800U
5146 #define GPIO_BSRR_BS_12 0x00001000U
5147 #define GPIO_BSRR_BS_13 0x00002000U
5148 #define GPIO_BSRR_BS_14 0x00004000U
5149 #define GPIO_BSRR_BS_15 0x00008000U
5150 #define GPIO_BSRR_BR_0 0x00010000U
5151 #define GPIO_BSRR_BR_1 0x00020000U
5152 #define GPIO_BSRR_BR_2 0x00040000U
5153 #define GPIO_BSRR_BR_3 0x00080000U
5154 #define GPIO_BSRR_BR_4 0x00100000U
5155 #define GPIO_BSRR_BR_5 0x00200000U
5156 #define GPIO_BSRR_BR_6 0x00400000U
5157 #define GPIO_BSRR_BR_7 0x00800000U
5158 #define GPIO_BSRR_BR_8 0x01000000U
5159 #define GPIO_BSRR_BR_9 0x02000000U
5160 #define GPIO_BSRR_BR_10 0x04000000U
5161 #define GPIO_BSRR_BR_11 0x08000000U
5162 #define GPIO_BSRR_BR_12 0x10000000U
5163 #define GPIO_BSRR_BR_13 0x20000000U
5164 #define GPIO_BSRR_BR_14 0x40000000U
5165 #define GPIO_BSRR_BR_15 0x80000000U
5166 
5167 /****************** Bit definition for GPIO_LCKR register *********************/
5168 #define GPIO_LCKR_LCK0 0x00000001U
5169 #define GPIO_LCKR_LCK1 0x00000002U
5170 #define GPIO_LCKR_LCK2 0x00000004U
5171 #define GPIO_LCKR_LCK3 0x00000008U
5172 #define GPIO_LCKR_LCK4 0x00000010U
5173 #define GPIO_LCKR_LCK5 0x00000020U
5174 #define GPIO_LCKR_LCK6 0x00000040U
5175 #define GPIO_LCKR_LCK7 0x00000080U
5176 #define GPIO_LCKR_LCK8 0x00000100U
5177 #define GPIO_LCKR_LCK9 0x00000200U
5178 #define GPIO_LCKR_LCK10 0x00000400U
5179 #define GPIO_LCKR_LCK11 0x00000800U
5180 #define GPIO_LCKR_LCK12 0x00001000U
5181 #define GPIO_LCKR_LCK13 0x00002000U
5182 #define GPIO_LCKR_LCK14 0x00004000U
5183 #define GPIO_LCKR_LCK15 0x00008000U
5184 #define GPIO_LCKR_LCKK 0x00010000U
5185 
5186 /******************************************************************************/
5187 /* */
5188 /* Inter-integrated Circuit Interface */
5189 /* */
5190 /******************************************************************************/
5191 /******************* Bit definition for I2C_CR1 register ********************/
5192 #define I2C_CR1_PE 0x00000001U
5193 #define I2C_CR1_SMBUS 0x00000002U
5194 #define I2C_CR1_SMBTYPE 0x00000008U
5195 #define I2C_CR1_ENARP 0x00000010U
5196 #define I2C_CR1_ENPEC 0x00000020U
5197 #define I2C_CR1_ENGC 0x00000040U
5198 #define I2C_CR1_NOSTRETCH 0x00000080U
5199 #define I2C_CR1_START 0x00000100U
5200 #define I2C_CR1_STOP 0x00000200U
5201 #define I2C_CR1_ACK 0x00000400U
5202 #define I2C_CR1_POS 0x00000800U
5203 #define I2C_CR1_PEC 0x00001000U
5204 #define I2C_CR1_ALERT 0x00002000U
5205 #define I2C_CR1_SWRST 0x00008000U
5207 /******************* Bit definition for I2C_CR2 register ********************/
5208 #define I2C_CR2_FREQ 0x0000003FU
5209 #define I2C_CR2_FREQ_0 0x00000001U
5210 #define I2C_CR2_FREQ_1 0x00000002U
5211 #define I2C_CR2_FREQ_2 0x00000004U
5212 #define I2C_CR2_FREQ_3 0x00000008U
5213 #define I2C_CR2_FREQ_4 0x00000010U
5214 #define I2C_CR2_FREQ_5 0x00000020U
5216 #define I2C_CR2_ITERREN 0x00000100U
5217 #define I2C_CR2_ITEVTEN 0x00000200U
5218 #define I2C_CR2_ITBUFEN 0x00000400U
5219 #define I2C_CR2_DMAEN 0x00000800U
5220 #define I2C_CR2_LAST 0x00001000U
5222 /******************* Bit definition for I2C_OAR1 register *******************/
5223 #define I2C_OAR1_ADD1_7 0x000000FEU
5224 #define I2C_OAR1_ADD8_9 0x00000300U
5226 #define I2C_OAR1_ADD0 0x00000001U
5227 #define I2C_OAR1_ADD1 0x00000002U
5228 #define I2C_OAR1_ADD2 0x00000004U
5229 #define I2C_OAR1_ADD3 0x00000008U
5230 #define I2C_OAR1_ADD4 0x00000010U
5231 #define I2C_OAR1_ADD5 0x00000020U
5232 #define I2C_OAR1_ADD6 0x00000040U
5233 #define I2C_OAR1_ADD7 0x00000080U
5234 #define I2C_OAR1_ADD8 0x00000100U
5235 #define I2C_OAR1_ADD9 0x00000200U
5237 #define I2C_OAR1_ADDMODE 0x00008000U
5239 /******************* Bit definition for I2C_OAR2 register *******************/
5240 #define I2C_OAR2_ENDUAL 0x00000001U
5241 #define I2C_OAR2_ADD2 0x000000FEU
5243 /******************** Bit definition for I2C_DR register ********************/
5244 #define I2C_DR_DR 0x000000FFU
5246 /******************* Bit definition for I2C_SR1 register ********************/
5247 #define I2C_SR1_SB 0x00000001U
5248 #define I2C_SR1_ADDR 0x00000002U
5249 #define I2C_SR1_BTF 0x00000004U
5250 #define I2C_SR1_ADD10 0x00000008U
5251 #define I2C_SR1_STOPF 0x00000010U
5252 #define I2C_SR1_RXNE 0x00000040U
5253 #define I2C_SR1_TXE 0x00000080U
5254 #define I2C_SR1_BERR 0x00000100U
5255 #define I2C_SR1_ARLO 0x00000200U
5256 #define I2C_SR1_AF 0x00000400U
5257 #define I2C_SR1_OVR 0x00000800U
5258 #define I2C_SR1_PECERR 0x00001000U
5259 #define I2C_SR1_TIMEOUT 0x00004000U
5260 #define I2C_SR1_SMBALERT 0x00008000U
5262 /******************* Bit definition for I2C_SR2 register ********************/
5263 #define I2C_SR2_MSL 0x00000001U
5264 #define I2C_SR2_BUSY 0x00000002U
5265 #define I2C_SR2_TRA 0x00000004U
5266 #define I2C_SR2_GENCALL 0x00000010U
5267 #define I2C_SR2_SMBDEFAULT 0x00000020U
5268 #define I2C_SR2_SMBHOST 0x00000040U
5269 #define I2C_SR2_DUALF 0x00000080U
5270 #define I2C_SR2_PEC 0x0000FF00U
5272 /******************* Bit definition for I2C_CCR register ********************/
5273 #define I2C_CCR_CCR 0x00000FFFU
5274 #define I2C_CCR_DUTY 0x00004000U
5275 #define I2C_CCR_FS 0x00008000U
5277 /****************** Bit definition for I2C_TRISE register *******************/
5278 #define I2C_TRISE_TRISE 0x0000003FU
5280 /****************** Bit definition for I2C_FLTR register *******************/
5281 #define I2C_FLTR_DNF 0x0000000FU
5282 #define I2C_FLTR_ANOFF 0x00000010U
5284 /******************************************************************************/
5285 /* */
5286 /* Independent WATCHDOG */
5287 /* */
5288 /******************************************************************************/
5289 /******************* Bit definition for IWDG_KR register ********************/
5290 #define IWDG_KR_KEY 0xFFFFU
5292 /******************* Bit definition for IWDG_PR register ********************/
5293 #define IWDG_PR_PR 0x07U
5294 #define IWDG_PR_PR_0 0x01U
5295 #define IWDG_PR_PR_1 0x02U
5296 #define IWDG_PR_PR_2 0x04U
5298 /******************* Bit definition for IWDG_RLR register *******************/
5299 #define IWDG_RLR_RL 0x0FFFU
5301 /******************* Bit definition for IWDG_SR register ********************/
5302 #define IWDG_SR_PVU 0x01U
5303 #define IWDG_SR_RVU 0x02U
5306 /******************************************************************************/
5307 /* */
5308 /* LCD-TFT Display Controller (LTDC) */
5309 /* */
5310 /******************************************************************************/
5311 
5312 /******************** Bit definition for LTDC_SSCR register *****************/
5313 
5314 #define LTDC_SSCR_VSH 0x000007FFU
5315 #define LTDC_SSCR_HSW 0x0FFF0000U
5317 /******************** Bit definition for LTDC_BPCR register *****************/
5318 
5319 #define LTDC_BPCR_AVBP 0x000007FFU
5320 #define LTDC_BPCR_AHBP 0x0FFF0000U
5322 /******************** Bit definition for LTDC_AWCR register *****************/
5323 
5324 #define LTDC_AWCR_AAH 0x000007FFU
5325 #define LTDC_AWCR_AAW 0x0FFF0000U
5327 /******************** Bit definition for LTDC_TWCR register *****************/
5328 
5329 #define LTDC_TWCR_TOTALH 0x000007FFU
5330 #define LTDC_TWCR_TOTALW 0x0FFF0000U
5332 /******************** Bit definition for LTDC_GCR register ******************/
5333 
5334 #define LTDC_GCR_LTDCEN 0x00000001U
5335 #define LTDC_GCR_DBW 0x00000070U
5336 #define LTDC_GCR_DGW 0x00000700U
5337 #define LTDC_GCR_DRW 0x00007000U
5338 #define LTDC_GCR_DEN 0x00010000U
5339 #define LTDC_GCR_PCPOL 0x10000000U
5340 #define LTDC_GCR_DEPOL 0x20000000U
5341 #define LTDC_GCR_VSPOL 0x40000000U
5342 #define LTDC_GCR_HSPOL 0x80000000U
5344 /* Legacy defines */
5345 #define LTDC_GCR_DTEN LTDC_GCR_DEN
5346 
5347 /******************** Bit definition for LTDC_SRCR register *****************/
5348 
5349 #define LTDC_SRCR_IMR 0x00000001U
5350 #define LTDC_SRCR_VBR 0x00000002U
5352 /******************** Bit definition for LTDC_BCCR register *****************/
5353 
5354 #define LTDC_BCCR_BCBLUE 0x000000FFU
5355 #define LTDC_BCCR_BCGREEN 0x0000FF00U
5356 #define LTDC_BCCR_BCRED 0x00FF0000U
5358 /******************** Bit definition for LTDC_IER register ******************/
5359 
5360 #define LTDC_IER_LIE 0x00000001U
5361 #define LTDC_IER_FUIE 0x00000002U
5362 #define LTDC_IER_TERRIE 0x00000004U
5363 #define LTDC_IER_RRIE 0x00000008U
5365 /******************** Bit definition for LTDC_ISR register ******************/
5366 
5367 #define LTDC_ISR_LIF 0x00000001U
5368 #define LTDC_ISR_FUIF 0x00000002U
5369 #define LTDC_ISR_TERRIF 0x00000004U
5370 #define LTDC_ISR_RRIF 0x00000008U
5372 /******************** Bit definition for LTDC_ICR register ******************/
5373 
5374 #define LTDC_ICR_CLIF 0x00000001U
5375 #define LTDC_ICR_CFUIF 0x00000002U
5376 #define LTDC_ICR_CTERRIF 0x00000004U
5377 #define LTDC_ICR_CRRIF 0x00000008U
5379 /******************** Bit definition for LTDC_LIPCR register ****************/
5380 
5381 #define LTDC_LIPCR_LIPOS 0x000007FFU
5383 /******************** Bit definition for LTDC_CPSR register *****************/
5384 
5385 #define LTDC_CPSR_CYPOS 0x0000FFFFU
5386 #define LTDC_CPSR_CXPOS 0xFFFF0000U
5388 /******************** Bit definition for LTDC_CDSR register *****************/
5389 
5390 #define LTDC_CDSR_VDES 0x00000001U
5391 #define LTDC_CDSR_HDES 0x00000002U
5392 #define LTDC_CDSR_VSYNCS 0x00000004U
5393 #define LTDC_CDSR_HSYNCS 0x00000008U
5395 /******************** Bit definition for LTDC_LxCR register *****************/
5396 
5397 #define LTDC_LxCR_LEN 0x00000001U
5398 #define LTDC_LxCR_COLKEN 0x00000002U
5399 #define LTDC_LxCR_CLUTEN 0x00000010U
5401 /******************** Bit definition for LTDC_LxWHPCR register **************/
5402 
5403 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU
5404 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U
5406 /******************** Bit definition for LTDC_LxWVPCR register **************/
5407 
5408 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU
5409 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U
5411 /******************** Bit definition for LTDC_LxCKCR register ***************/
5412 
5413 #define LTDC_LxCKCR_CKBLUE 0x000000FFU
5414 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U
5415 #define LTDC_LxCKCR_CKRED 0x00FF0000U
5417 /******************** Bit definition for LTDC_LxPFCR register ***************/
5418 
5419 #define LTDC_LxPFCR_PF 0x00000007U
5421 /******************** Bit definition for LTDC_LxCACR register ***************/
5422 
5423 #define LTDC_LxCACR_CONSTA 0x000000FFU
5425 /******************** Bit definition for LTDC_LxDCCR register ***************/
5426 
5427 #define LTDC_LxDCCR_DCBLUE 0x000000FFU
5428 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U
5429 #define LTDC_LxDCCR_DCRED 0x00FF0000U
5430 #define LTDC_LxDCCR_DCALPHA 0xFF000000U
5432 /******************** Bit definition for LTDC_LxBFCR register ***************/
5433 
5434 #define LTDC_LxBFCR_BF2 0x00000007U
5435 #define LTDC_LxBFCR_BF1 0x00000700U
5437 /******************** Bit definition for LTDC_LxCFBAR register **************/
5438 
5439 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU
5441 /******************** Bit definition for LTDC_LxCFBLR register **************/
5442 
5443 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU
5444 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U
5446 /******************** Bit definition for LTDC_LxCFBLNR register *************/
5447 
5448 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU
5450 /******************** Bit definition for LTDC_LxCLUTWR register *************/
5451 
5452 #define LTDC_LxCLUTWR_BLUE 0x000000FFU
5453 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U
5454 #define LTDC_LxCLUTWR_RED 0x00FF0000U
5455 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U
5458 /******************************************************************************/
5459 /* */
5460 /* Power Control */
5461 /* */
5462 /******************************************************************************/
5463 /******************** Bit definition for PWR_CR register ********************/
5464 #define PWR_CR_LPDS 0x00000001U
5465 #define PWR_CR_PDDS 0x00000002U
5466 #define PWR_CR_CWUF 0x00000004U
5467 #define PWR_CR_CSBF 0x00000008U
5468 #define PWR_CR_PVDE 0x00000010U
5470 #define PWR_CR_PLS 0x000000E0U
5471 #define PWR_CR_PLS_0 0x00000020U
5472 #define PWR_CR_PLS_1 0x00000040U
5473 #define PWR_CR_PLS_2 0x00000080U
5476 #define PWR_CR_PLS_LEV0 0x00000000U
5477 #define PWR_CR_PLS_LEV1 0x00000020U
5478 #define PWR_CR_PLS_LEV2 0x00000040U
5479 #define PWR_CR_PLS_LEV3 0x00000060U
5480 #define PWR_CR_PLS_LEV4 0x00000080U
5481 #define PWR_CR_PLS_LEV5 0x000000A0U
5482 #define PWR_CR_PLS_LEV6 0x000000C0U
5483 #define PWR_CR_PLS_LEV7 0x000000E0U
5484 #define PWR_CR_DBP 0x00000100U
5485 #define PWR_CR_FPDS 0x00000200U
5486 #define PWR_CR_LPLVDS 0x00000400U
5487 #define PWR_CR_MRLVDS 0x00000800U
5488 #define PWR_CR_ADCDC1 0x00002000U
5489 #define PWR_CR_VOS 0x0000C000U
5490 #define PWR_CR_VOS_0 0x00004000U
5491 #define PWR_CR_VOS_1 0x00008000U
5492 #define PWR_CR_ODEN 0x00010000U
5493 #define PWR_CR_ODSWEN 0x00020000U
5494 #define PWR_CR_UDEN 0x000C0000U
5495 #define PWR_CR_UDEN_0 0x00040000U
5496 #define PWR_CR_UDEN_1 0x00080000U
5498 /* Legacy define */
5499 #define PWR_CR_PMODE PWR_CR_VOS
5500 #define PWR_CR_LPUDS PWR_CR_LPLVDS
5501 #define PWR_CR_MRUDS PWR_CR_MRLVDS
5503 /******************* Bit definition for PWR_CSR register ********************/
5504 #define PWR_CSR_WUF 0x00000001U
5505 #define PWR_CSR_SBF 0x00000002U
5506 #define PWR_CSR_PVDO 0x00000004U
5507 #define PWR_CSR_BRR 0x00000008U
5508 #define PWR_CSR_EWUP 0x00000100U
5509 #define PWR_CSR_BRE 0x00000200U
5510 #define PWR_CSR_VOSRDY 0x00004000U
5511 #define PWR_CSR_ODRDY 0x00010000U
5512 #define PWR_CSR_ODSWRDY 0x00020000U
5513 #define PWR_CSR_UDSWRDY 0x000C0000U
5515 /* Legacy define */
5516 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
5517 
5518 /******************************************************************************/
5519 /* */
5520 /* Reset and Clock Control */
5521 /* */
5522 /******************************************************************************/
5523 /******************** Bit definition for RCC_CR register ********************/
5524 #define RCC_CR_HSION 0x00000001U
5525 #define RCC_CR_HSIRDY 0x00000002U
5526 
5527 #define RCC_CR_HSITRIM 0x000000F8U
5528 #define RCC_CR_HSITRIM_0 0x00000008U
5529 #define RCC_CR_HSITRIM_1 0x00000010U
5530 #define RCC_CR_HSITRIM_2 0x00000020U
5531 #define RCC_CR_HSITRIM_3 0x00000040U
5532 #define RCC_CR_HSITRIM_4 0x00000080U
5534 #define RCC_CR_HSICAL 0x0000FF00U
5535 #define RCC_CR_HSICAL_0 0x00000100U
5536 #define RCC_CR_HSICAL_1 0x00000200U
5537 #define RCC_CR_HSICAL_2 0x00000400U
5538 #define RCC_CR_HSICAL_3 0x00000800U
5539 #define RCC_CR_HSICAL_4 0x00001000U
5540 #define RCC_CR_HSICAL_5 0x00002000U
5541 #define RCC_CR_HSICAL_6 0x00004000U
5542 #define RCC_CR_HSICAL_7 0x00008000U
5544 #define RCC_CR_HSEON 0x00010000U
5545 #define RCC_CR_HSERDY 0x00020000U
5546 #define RCC_CR_HSEBYP 0x00040000U
5547 #define RCC_CR_CSSON 0x00080000U
5548 #define RCC_CR_PLLON 0x01000000U
5549 #define RCC_CR_PLLRDY 0x02000000U
5550 #define RCC_CR_PLLI2SON 0x04000000U
5551 #define RCC_CR_PLLI2SRDY 0x08000000U
5552 #define RCC_CR_PLLSAION 0x10000000U
5553 #define RCC_CR_PLLSAIRDY 0x20000000U
5554 
5555 /******************** Bit definition for RCC_PLLCFGR register ***************/
5556 #define RCC_PLLCFGR_PLLM 0x0000003FU
5557 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5558 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5559 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5560 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5561 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5562 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5563 
5564 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5565 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5566 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5567 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5568 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5569 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5570 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5571 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5572 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5573 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5574 
5575 #define RCC_PLLCFGR_PLLP 0x00030000U
5576 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5577 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5578 
5579 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5580 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5581 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5582 
5583 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5584 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5585 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5586 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5587 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5588 
5589 /******************** Bit definition for RCC_CFGR register ******************/
5591 #define RCC_CFGR_SW 0x00000003U
5592 #define RCC_CFGR_SW_0 0x00000001U
5593 #define RCC_CFGR_SW_1 0x00000002U
5595 #define RCC_CFGR_SW_HSI 0x00000000U
5596 #define RCC_CFGR_SW_HSE 0x00000001U
5597 #define RCC_CFGR_SW_PLL 0x00000002U
5600 #define RCC_CFGR_SWS 0x0000000CU
5601 #define RCC_CFGR_SWS_0 0x00000004U
5602 #define RCC_CFGR_SWS_1 0x00000008U
5604 #define RCC_CFGR_SWS_HSI 0x00000000U
5605 #define RCC_CFGR_SWS_HSE 0x00000004U
5606 #define RCC_CFGR_SWS_PLL 0x00000008U
5609 #define RCC_CFGR_HPRE 0x000000F0U
5610 #define RCC_CFGR_HPRE_0 0x00000010U
5611 #define RCC_CFGR_HPRE_1 0x00000020U
5612 #define RCC_CFGR_HPRE_2 0x00000040U
5613 #define RCC_CFGR_HPRE_3 0x00000080U
5615 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5616 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5617 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5618 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5619 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5620 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5621 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5622 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5623 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5626 #define RCC_CFGR_PPRE1 0x00001C00U
5627 #define RCC_CFGR_PPRE1_0 0x00000400U
5628 #define RCC_CFGR_PPRE1_1 0x00000800U
5629 #define RCC_CFGR_PPRE1_2 0x00001000U
5631 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5632 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5633 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5634 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5635 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5638 #define RCC_CFGR_PPRE2 0x0000E000U
5639 #define RCC_CFGR_PPRE2_0 0x00002000U
5640 #define RCC_CFGR_PPRE2_1 0x00004000U
5641 #define RCC_CFGR_PPRE2_2 0x00008000U
5643 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5644 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5645 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5646 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5647 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5650 #define RCC_CFGR_RTCPRE 0x001F0000U
5651 #define RCC_CFGR_RTCPRE_0 0x00010000U
5652 #define RCC_CFGR_RTCPRE_1 0x00020000U
5653 #define RCC_CFGR_RTCPRE_2 0x00040000U
5654 #define RCC_CFGR_RTCPRE_3 0x00080000U
5655 #define RCC_CFGR_RTCPRE_4 0x00100000U
5656 
5658 #define RCC_CFGR_MCO1 0x00600000U
5659 #define RCC_CFGR_MCO1_0 0x00200000U
5660 #define RCC_CFGR_MCO1_1 0x00400000U
5661 
5662 #define RCC_CFGR_I2SSRC 0x00800000U
5663 
5664 #define RCC_CFGR_MCO1PRE 0x07000000U
5665 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5666 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5667 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5668 
5669 #define RCC_CFGR_MCO2PRE 0x38000000U
5670 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5671 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5672 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5673 
5674 #define RCC_CFGR_MCO2 0xC0000000U
5675 #define RCC_CFGR_MCO2_0 0x40000000U
5676 #define RCC_CFGR_MCO2_1 0x80000000U
5677 
5678 /******************** Bit definition for RCC_CIR register *******************/
5679 #define RCC_CIR_LSIRDYF 0x00000001U
5680 #define RCC_CIR_LSERDYF 0x00000002U
5681 #define RCC_CIR_HSIRDYF 0x00000004U
5682 #define RCC_CIR_HSERDYF 0x00000008U
5683 #define RCC_CIR_PLLRDYF 0x00000010U
5684 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5685 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5686 #define RCC_CIR_CSSF 0x00000080U
5687 #define RCC_CIR_LSIRDYIE 0x00000100U
5688 #define RCC_CIR_LSERDYIE 0x00000200U
5689 #define RCC_CIR_HSIRDYIE 0x00000400U
5690 #define RCC_CIR_HSERDYIE 0x00000800U
5691 #define RCC_CIR_PLLRDYIE 0x00001000U
5692 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5693 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5694 #define RCC_CIR_LSIRDYC 0x00010000U
5695 #define RCC_CIR_LSERDYC 0x00020000U
5696 #define RCC_CIR_HSIRDYC 0x00040000U
5697 #define RCC_CIR_HSERDYC 0x00080000U
5698 #define RCC_CIR_PLLRDYC 0x00100000U
5699 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5700 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5701 #define RCC_CIR_CSSC 0x00800000U
5702 
5703 /******************** Bit definition for RCC_AHB1RSTR register **************/
5704 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5705 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5706 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5707 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5708 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5709 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5710 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5711 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5712 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5713 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
5714 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
5715 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5716 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5717 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5718 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
5719 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5720 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5721 
5722 /******************** Bit definition for RCC_AHB2RSTR register **************/
5723 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5724 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5725 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5726 
5727 /******************** Bit definition for RCC_AHB3RSTR register **************/
5728 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5729 
5730 /******************** Bit definition for RCC_APB1RSTR register **************/
5731 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5732 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5733 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5734 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5735 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5736 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5737 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5738 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5739 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5740 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5741 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5742 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5743 #define RCC_APB1RSTR_USART2RST 0x00020000U
5744 #define RCC_APB1RSTR_USART3RST 0x00040000U
5745 #define RCC_APB1RSTR_UART4RST 0x00080000U
5746 #define RCC_APB1RSTR_UART5RST 0x00100000U
5747 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5748 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5749 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5750 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5751 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5752 #define RCC_APB1RSTR_PWRRST 0x10000000U
5753 #define RCC_APB1RSTR_DACRST 0x20000000U
5754 #define RCC_APB1RSTR_UART7RST 0x40000000U
5755 #define RCC_APB1RSTR_UART8RST 0x80000000U
5756 
5757 /******************** Bit definition for RCC_APB2RSTR register **************/
5758 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5759 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5760 #define RCC_APB2RSTR_USART1RST 0x00000010U
5761 #define RCC_APB2RSTR_USART6RST 0x00000020U
5762 #define RCC_APB2RSTR_ADCRST 0x00000100U
5763 #define RCC_APB2RSTR_SDIORST 0x00000800U
5764 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5765 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5766 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5767 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5768 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5769 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5770 #define RCC_APB2RSTR_SPI5RST 0x00100000U
5771 #define RCC_APB2RSTR_SPI6RST 0x00200000U
5772 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5773 #define RCC_APB2RSTR_LTDCRST 0x04000000U
5774 
5775 /* Old SPI1RST bit definition, maintained for legacy purpose */
5776 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5777 
5778 /******************** Bit definition for RCC_AHB1ENR register ***************/
5779 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5780 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5781 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5782 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5783 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5784 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5785 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5786 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5787 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5788 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
5789 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
5790 
5791 #define RCC_AHB1ENR_CRCEN 0x00001000U
5792 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5793 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
5794 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5795 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5796 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
5797 
5798 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5799 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5800 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5801 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5802 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5803 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5804 
5805 /******************** Bit definition for RCC_AHB2ENR register ***************/
5806 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5807 #define RCC_AHB2ENR_RNGEN 0x00000040U
5808 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5809 
5810 /******************** Bit definition for RCC_AHB3ENR register ***************/
5811 #define RCC_AHB3ENR_FMCEN 0x00000001U
5812 
5813 /******************** Bit definition for RCC_APB1ENR register ***************/
5814 #define RCC_APB1ENR_TIM2EN 0x00000001U
5815 #define RCC_APB1ENR_TIM3EN 0x00000002U
5816 #define RCC_APB1ENR_TIM4EN 0x00000004U
5817 #define RCC_APB1ENR_TIM5EN 0x00000008U
5818 #define RCC_APB1ENR_TIM6EN 0x00000010U
5819 #define RCC_APB1ENR_TIM7EN 0x00000020U
5820 #define RCC_APB1ENR_TIM12EN 0x00000040U
5821 #define RCC_APB1ENR_TIM13EN 0x00000080U
5822 #define RCC_APB1ENR_TIM14EN 0x00000100U
5823 #define RCC_APB1ENR_WWDGEN 0x00000800U
5824 #define RCC_APB1ENR_SPI2EN 0x00004000U
5825 #define RCC_APB1ENR_SPI3EN 0x00008000U
5826 #define RCC_APB1ENR_USART2EN 0x00020000U
5827 #define RCC_APB1ENR_USART3EN 0x00040000U
5828 #define RCC_APB1ENR_UART4EN 0x00080000U
5829 #define RCC_APB1ENR_UART5EN 0x00100000U
5830 #define RCC_APB1ENR_I2C1EN 0x00200000U
5831 #define RCC_APB1ENR_I2C2EN 0x00400000U
5832 #define RCC_APB1ENR_I2C3EN 0x00800000U
5833 #define RCC_APB1ENR_CAN1EN 0x02000000U
5834 #define RCC_APB1ENR_CAN2EN 0x04000000U
5835 #define RCC_APB1ENR_PWREN 0x10000000U
5836 #define RCC_APB1ENR_DACEN 0x20000000U
5837 #define RCC_APB1ENR_UART7EN 0x40000000U
5838 #define RCC_APB1ENR_UART8EN 0x80000000U
5839 
5840 /******************** Bit definition for RCC_APB2ENR register ***************/
5841 #define RCC_APB2ENR_TIM1EN 0x00000001U
5842 #define RCC_APB2ENR_TIM8EN 0x00000002U
5843 #define RCC_APB2ENR_USART1EN 0x00000010U
5844 #define RCC_APB2ENR_USART6EN 0x00000020U
5845 #define RCC_APB2ENR_ADC1EN 0x00000100U
5846 #define RCC_APB2ENR_ADC2EN 0x00000200U
5847 #define RCC_APB2ENR_ADC3EN 0x00000400U
5848 #define RCC_APB2ENR_SDIOEN 0x00000800U
5849 #define RCC_APB2ENR_SPI1EN 0x00001000U
5850 #define RCC_APB2ENR_SPI4EN 0x00002000U
5851 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5852 #define RCC_APB2ENR_TIM9EN 0x00010000U
5853 #define RCC_APB2ENR_TIM10EN 0x00020000U
5854 #define RCC_APB2ENR_TIM11EN 0x00040000U
5855 #define RCC_APB2ENR_SPI5EN 0x00100000U
5856 #define RCC_APB2ENR_SPI6EN 0x00200000U
5857 #define RCC_APB2ENR_SAI1EN 0x00400000U
5858 #define RCC_APB2ENR_LTDCEN 0x04000000U
5859 
5860 /******************** Bit definition for RCC_AHB1LPENR register *************/
5861 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5862 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5863 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5864 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5865 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5866 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5867 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5868 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5869 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5870 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
5871 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
5872 
5873 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5874 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5875 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5876 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5877 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5878 #define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
5879 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5880 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5881 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
5882 
5883 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5884 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5885 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5886 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5887 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5888 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5889 
5890 /******************** Bit definition for RCC_AHB2LPENR register *************/
5891 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5892 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5893 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5894 
5895 /******************** Bit definition for RCC_AHB3LPENR register *************/
5896 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
5897 
5898 /******************** Bit definition for RCC_APB1LPENR register *************/
5899 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5900 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5901 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5902 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5903 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5904 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5905 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5906 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5907 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5908 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5909 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5910 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5911 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5912 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5913 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5914 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5915 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5916 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5917 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5918 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5919 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5920 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5921 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5922 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
5923 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
5924 
5925 /******************** Bit definition for RCC_APB2LPENR register *************/
5926 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5927 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5928 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5929 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5930 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5931 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5932 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5933 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
5934 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5935 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
5936 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5937 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5938 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5939 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5940 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
5941 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
5942 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
5943 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
5944 
5945 /******************** Bit definition for RCC_BDCR register ******************/
5946 #define RCC_BDCR_LSEON 0x00000001U
5947 #define RCC_BDCR_LSERDY 0x00000002U
5948 #define RCC_BDCR_LSEBYP 0x00000004U
5949 
5950 #define RCC_BDCR_RTCSEL 0x00000300U
5951 #define RCC_BDCR_RTCSEL_0 0x00000100U
5952 #define RCC_BDCR_RTCSEL_1 0x00000200U
5953 
5954 #define RCC_BDCR_RTCEN 0x00008000U
5955 #define RCC_BDCR_BDRST 0x00010000U
5956 
5957 /******************** Bit definition for RCC_CSR register *******************/
5958 #define RCC_CSR_LSION 0x00000001U
5959 #define RCC_CSR_LSIRDY 0x00000002U
5960 #define RCC_CSR_RMVF 0x01000000U
5961 #define RCC_CSR_BORRSTF 0x02000000U
5962 #define RCC_CSR_PADRSTF 0x04000000U
5963 #define RCC_CSR_PORRSTF 0x08000000U
5964 #define RCC_CSR_SFTRSTF 0x10000000U
5965 #define RCC_CSR_WDGRSTF 0x20000000U
5966 #define RCC_CSR_WWDGRSTF 0x40000000U
5967 #define RCC_CSR_LPWRRSTF 0x80000000U
5968 
5969 /******************** Bit definition for RCC_SSCGR register *****************/
5970 #define RCC_SSCGR_MODPER 0x00001FFFU
5971 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5972 #define RCC_SSCGR_SPREADSEL 0x40000000U
5973 #define RCC_SSCGR_SSCGEN 0x80000000U
5974 
5975 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5976 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5977 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5978 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5979 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5980 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5981 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5982 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5983 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5984 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5985 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5986 
5987 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
5988 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
5989 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
5990 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
5991 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
5992 
5993 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5994 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5995 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5996 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5997 
5998 
5999 /******************** Bit definition for RCC_PLLSAICFGR register ************/
6000 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
6001 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
6002 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
6003 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
6004 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
6005 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
6006 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
6007 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
6008 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
6009 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
6010 
6011 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
6012 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
6013 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
6014 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
6015 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
6016 
6017 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
6018 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
6019 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
6020 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
6021 
6022 /******************** Bit definition for RCC_DCKCFGR register ***************/
6023 #define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
6024 #define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
6025 #define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
6026 #define RCC_DCKCFGR_SAI1ASRC 0x00300000U
6027 #define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
6028 #define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
6029 #define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
6030 #define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
6031 #define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
6032 #define RCC_DCKCFGR_TIMPRE 0x01000000U
6033 
6034 
6035 /******************************************************************************/
6036 /* */
6037 /* RNG */
6038 /* */
6039 /******************************************************************************/
6040 /******************** Bits definition for RNG_CR register *******************/
6041 #define RNG_CR_RNGEN 0x00000004U
6042 #define RNG_CR_IE 0x00000008U
6043 
6044 /******************** Bits definition for RNG_SR register *******************/
6045 #define RNG_SR_DRDY 0x00000001U
6046 #define RNG_SR_CECS 0x00000002U
6047 #define RNG_SR_SECS 0x00000004U
6048 #define RNG_SR_CEIS 0x00000020U
6049 #define RNG_SR_SEIS 0x00000040U
6050 
6051 /******************************************************************************/
6052 /* */
6053 /* Real-Time Clock (RTC) */
6054 /* */
6055 /******************************************************************************/
6056 /******************** Bits definition for RTC_TR register *******************/
6057 #define RTC_TR_PM 0x00400000U
6058 #define RTC_TR_HT 0x00300000U
6059 #define RTC_TR_HT_0 0x00100000U
6060 #define RTC_TR_HT_1 0x00200000U
6061 #define RTC_TR_HU 0x000F0000U
6062 #define RTC_TR_HU_0 0x00010000U
6063 #define RTC_TR_HU_1 0x00020000U
6064 #define RTC_TR_HU_2 0x00040000U
6065 #define RTC_TR_HU_3 0x00080000U
6066 #define RTC_TR_MNT 0x00007000U
6067 #define RTC_TR_MNT_0 0x00001000U
6068 #define RTC_TR_MNT_1 0x00002000U
6069 #define RTC_TR_MNT_2 0x00004000U
6070 #define RTC_TR_MNU 0x00000F00U
6071 #define RTC_TR_MNU_0 0x00000100U
6072 #define RTC_TR_MNU_1 0x00000200U
6073 #define RTC_TR_MNU_2 0x00000400U
6074 #define RTC_TR_MNU_3 0x00000800U
6075 #define RTC_TR_ST 0x00000070U
6076 #define RTC_TR_ST_0 0x00000010U
6077 #define RTC_TR_ST_1 0x00000020U
6078 #define RTC_TR_ST_2 0x00000040U
6079 #define RTC_TR_SU 0x0000000FU
6080 #define RTC_TR_SU_0 0x00000001U
6081 #define RTC_TR_SU_1 0x00000002U
6082 #define RTC_TR_SU_2 0x00000004U
6083 #define RTC_TR_SU_3 0x00000008U
6084 
6085 /******************** Bits definition for RTC_DR register *******************/
6086 #define RTC_DR_YT 0x00F00000U
6087 #define RTC_DR_YT_0 0x00100000U
6088 #define RTC_DR_YT_1 0x00200000U
6089 #define RTC_DR_YT_2 0x00400000U
6090 #define RTC_DR_YT_3 0x00800000U
6091 #define RTC_DR_YU 0x000F0000U
6092 #define RTC_DR_YU_0 0x00010000U
6093 #define RTC_DR_YU_1 0x00020000U
6094 #define RTC_DR_YU_2 0x00040000U
6095 #define RTC_DR_YU_3 0x00080000U
6096 #define RTC_DR_WDU 0x0000E000U
6097 #define RTC_DR_WDU_0 0x00002000U
6098 #define RTC_DR_WDU_1 0x00004000U
6099 #define RTC_DR_WDU_2 0x00008000U
6100 #define RTC_DR_MT 0x00001000U
6101 #define RTC_DR_MU 0x00000F00U
6102 #define RTC_DR_MU_0 0x00000100U
6103 #define RTC_DR_MU_1 0x00000200U
6104 #define RTC_DR_MU_2 0x00000400U
6105 #define RTC_DR_MU_3 0x00000800U
6106 #define RTC_DR_DT 0x00000030U
6107 #define RTC_DR_DT_0 0x00000010U
6108 #define RTC_DR_DT_1 0x00000020U
6109 #define RTC_DR_DU 0x0000000FU
6110 #define RTC_DR_DU_0 0x00000001U
6111 #define RTC_DR_DU_1 0x00000002U
6112 #define RTC_DR_DU_2 0x00000004U
6113 #define RTC_DR_DU_3 0x00000008U
6114 
6115 /******************** Bits definition for RTC_CR register *******************/
6116 #define RTC_CR_COE 0x00800000U
6117 #define RTC_CR_OSEL 0x00600000U
6118 #define RTC_CR_OSEL_0 0x00200000U
6119 #define RTC_CR_OSEL_1 0x00400000U
6120 #define RTC_CR_POL 0x00100000U
6121 #define RTC_CR_COSEL 0x00080000U
6122 #define RTC_CR_BCK 0x00040000U
6123 #define RTC_CR_SUB1H 0x00020000U
6124 #define RTC_CR_ADD1H 0x00010000U
6125 #define RTC_CR_TSIE 0x00008000U
6126 #define RTC_CR_WUTIE 0x00004000U
6127 #define RTC_CR_ALRBIE 0x00002000U
6128 #define RTC_CR_ALRAIE 0x00001000U
6129 #define RTC_CR_TSE 0x00000800U
6130 #define RTC_CR_WUTE 0x00000400U
6131 #define RTC_CR_ALRBE 0x00000200U
6132 #define RTC_CR_ALRAE 0x00000100U
6133 #define RTC_CR_DCE 0x00000080U
6134 #define RTC_CR_FMT 0x00000040U
6135 #define RTC_CR_BYPSHAD 0x00000020U
6136 #define RTC_CR_REFCKON 0x00000010U
6137 #define RTC_CR_TSEDGE 0x00000008U
6138 #define RTC_CR_WUCKSEL 0x00000007U
6139 #define RTC_CR_WUCKSEL_0 0x00000001U
6140 #define RTC_CR_WUCKSEL_1 0x00000002U
6141 #define RTC_CR_WUCKSEL_2 0x00000004U
6142 
6143 /******************** Bits definition for RTC_ISR register ******************/
6144 #define RTC_ISR_RECALPF 0x00010000U
6145 #define RTC_ISR_TAMP1F 0x00002000U
6146 #define RTC_ISR_TAMP2F 0x00004000U
6147 #define RTC_ISR_TSOVF 0x00001000U
6148 #define RTC_ISR_TSF 0x00000800U
6149 #define RTC_ISR_WUTF 0x00000400U
6150 #define RTC_ISR_ALRBF 0x00000200U
6151 #define RTC_ISR_ALRAF 0x00000100U
6152 #define RTC_ISR_INIT 0x00000080U
6153 #define RTC_ISR_INITF 0x00000040U
6154 #define RTC_ISR_RSF 0x00000020U
6155 #define RTC_ISR_INITS 0x00000010U
6156 #define RTC_ISR_SHPF 0x00000008U
6157 #define RTC_ISR_WUTWF 0x00000004U
6158 #define RTC_ISR_ALRBWF 0x00000002U
6159 #define RTC_ISR_ALRAWF 0x00000001U
6160 
6161 /******************** Bits definition for RTC_PRER register *****************/
6162 #define RTC_PRER_PREDIV_A 0x007F0000U
6163 #define RTC_PRER_PREDIV_S 0x00007FFFU
6164 
6165 /******************** Bits definition for RTC_WUTR register *****************/
6166 #define RTC_WUTR_WUT 0x0000FFFFU
6167 
6168 /******************** Bits definition for RTC_CALIBR register ***************/
6169 #define RTC_CALIBR_DCS 0x00000080U
6170 #define RTC_CALIBR_DC 0x0000001FU
6171 
6172 /******************** Bits definition for RTC_ALRMAR register ***************/
6173 #define RTC_ALRMAR_MSK4 0x80000000U
6174 #define RTC_ALRMAR_WDSEL 0x40000000U
6175 #define RTC_ALRMAR_DT 0x30000000U
6176 #define RTC_ALRMAR_DT_0 0x10000000U
6177 #define RTC_ALRMAR_DT_1 0x20000000U
6178 #define RTC_ALRMAR_DU 0x0F000000U
6179 #define RTC_ALRMAR_DU_0 0x01000000U
6180 #define RTC_ALRMAR_DU_1 0x02000000U
6181 #define RTC_ALRMAR_DU_2 0x04000000U
6182 #define RTC_ALRMAR_DU_3 0x08000000U
6183 #define RTC_ALRMAR_MSK3 0x00800000U
6184 #define RTC_ALRMAR_PM 0x00400000U
6185 #define RTC_ALRMAR_HT 0x00300000U
6186 #define RTC_ALRMAR_HT_0 0x00100000U
6187 #define RTC_ALRMAR_HT_1 0x00200000U
6188 #define RTC_ALRMAR_HU 0x000F0000U
6189 #define RTC_ALRMAR_HU_0 0x00010000U
6190 #define RTC_ALRMAR_HU_1 0x00020000U
6191 #define RTC_ALRMAR_HU_2 0x00040000U
6192 #define RTC_ALRMAR_HU_3 0x00080000U
6193 #define RTC_ALRMAR_MSK2 0x00008000U
6194 #define RTC_ALRMAR_MNT 0x00007000U
6195 #define RTC_ALRMAR_MNT_0 0x00001000U
6196 #define RTC_ALRMAR_MNT_1 0x00002000U
6197 #define RTC_ALRMAR_MNT_2 0x00004000U
6198 #define RTC_ALRMAR_MNU 0x00000F00U
6199 #define RTC_ALRMAR_MNU_0 0x00000100U
6200 #define RTC_ALRMAR_MNU_1 0x00000200U
6201 #define RTC_ALRMAR_MNU_2 0x00000400U
6202 #define RTC_ALRMAR_MNU_3 0x00000800U
6203 #define RTC_ALRMAR_MSK1 0x00000080U
6204 #define RTC_ALRMAR_ST 0x00000070U
6205 #define RTC_ALRMAR_ST_0 0x00000010U
6206 #define RTC_ALRMAR_ST_1 0x00000020U
6207 #define RTC_ALRMAR_ST_2 0x00000040U
6208 #define RTC_ALRMAR_SU 0x0000000FU
6209 #define RTC_ALRMAR_SU_0 0x00000001U
6210 #define RTC_ALRMAR_SU_1 0x00000002U
6211 #define RTC_ALRMAR_SU_2 0x00000004U
6212 #define RTC_ALRMAR_SU_3 0x00000008U
6213 
6214 /******************** Bits definition for RTC_ALRMBR register ***************/
6215 #define RTC_ALRMBR_MSK4 0x80000000U
6216 #define RTC_ALRMBR_WDSEL 0x40000000U
6217 #define RTC_ALRMBR_DT 0x30000000U
6218 #define RTC_ALRMBR_DT_0 0x10000000U
6219 #define RTC_ALRMBR_DT_1 0x20000000U
6220 #define RTC_ALRMBR_DU 0x0F000000U
6221 #define RTC_ALRMBR_DU_0 0x01000000U
6222 #define RTC_ALRMBR_DU_1 0x02000000U
6223 #define RTC_ALRMBR_DU_2 0x04000000U
6224 #define RTC_ALRMBR_DU_3 0x08000000U
6225 #define RTC_ALRMBR_MSK3 0x00800000U
6226 #define RTC_ALRMBR_PM 0x00400000U
6227 #define RTC_ALRMBR_HT 0x00300000U
6228 #define RTC_ALRMBR_HT_0 0x00100000U
6229 #define RTC_ALRMBR_HT_1 0x00200000U
6230 #define RTC_ALRMBR_HU 0x000F0000U
6231 #define RTC_ALRMBR_HU_0 0x00010000U
6232 #define RTC_ALRMBR_HU_1 0x00020000U
6233 #define RTC_ALRMBR_HU_2 0x00040000U
6234 #define RTC_ALRMBR_HU_3 0x00080000U
6235 #define RTC_ALRMBR_MSK2 0x00008000U
6236 #define RTC_ALRMBR_MNT 0x00007000U
6237 #define RTC_ALRMBR_MNT_0 0x00001000U
6238 #define RTC_ALRMBR_MNT_1 0x00002000U
6239 #define RTC_ALRMBR_MNT_2 0x00004000U
6240 #define RTC_ALRMBR_MNU 0x00000F00U
6241 #define RTC_ALRMBR_MNU_0 0x00000100U
6242 #define RTC_ALRMBR_MNU_1 0x00000200U
6243 #define RTC_ALRMBR_MNU_2 0x00000400U
6244 #define RTC_ALRMBR_MNU_3 0x00000800U
6245 #define RTC_ALRMBR_MSK1 0x00000080U
6246 #define RTC_ALRMBR_ST 0x00000070U
6247 #define RTC_ALRMBR_ST_0 0x00000010U
6248 #define RTC_ALRMBR_ST_1 0x00000020U
6249 #define RTC_ALRMBR_ST_2 0x00000040U
6250 #define RTC_ALRMBR_SU 0x0000000FU
6251 #define RTC_ALRMBR_SU_0 0x00000001U
6252 #define RTC_ALRMBR_SU_1 0x00000002U
6253 #define RTC_ALRMBR_SU_2 0x00000004U
6254 #define RTC_ALRMBR_SU_3 0x00000008U
6255 
6256 /******************** Bits definition for RTC_WPR register ******************/
6257 #define RTC_WPR_KEY 0x000000FFU
6258 
6259 /******************** Bits definition for RTC_SSR register ******************/
6260 #define RTC_SSR_SS 0x0000FFFFU
6261 
6262 /******************** Bits definition for RTC_SHIFTR register ***************/
6263 #define RTC_SHIFTR_SUBFS 0x00007FFFU
6264 #define RTC_SHIFTR_ADD1S 0x80000000U
6265 
6266 /******************** Bits definition for RTC_TSTR register *****************/
6267 #define RTC_TSTR_PM 0x00400000U
6268 #define RTC_TSTR_HT 0x00300000U
6269 #define RTC_TSTR_HT_0 0x00100000U
6270 #define RTC_TSTR_HT_1 0x00200000U
6271 #define RTC_TSTR_HU 0x000F0000U
6272 #define RTC_TSTR_HU_0 0x00010000U
6273 #define RTC_TSTR_HU_1 0x00020000U
6274 #define RTC_TSTR_HU_2 0x00040000U
6275 #define RTC_TSTR_HU_3 0x00080000U
6276 #define RTC_TSTR_MNT 0x00007000U
6277 #define RTC_TSTR_MNT_0 0x00001000U
6278 #define RTC_TSTR_MNT_1 0x00002000U
6279 #define RTC_TSTR_MNT_2 0x00004000U
6280 #define RTC_TSTR_MNU 0x00000F00U
6281 #define RTC_TSTR_MNU_0 0x00000100U
6282 #define RTC_TSTR_MNU_1 0x00000200U
6283 #define RTC_TSTR_MNU_2 0x00000400U
6284 #define RTC_TSTR_MNU_3 0x00000800U
6285 #define RTC_TSTR_ST 0x00000070U
6286 #define RTC_TSTR_ST_0 0x00000010U
6287 #define RTC_TSTR_ST_1 0x00000020U
6288 #define RTC_TSTR_ST_2 0x00000040U
6289 #define RTC_TSTR_SU 0x0000000FU
6290 #define RTC_TSTR_SU_0 0x00000001U
6291 #define RTC_TSTR_SU_1 0x00000002U
6292 #define RTC_TSTR_SU_2 0x00000004U
6293 #define RTC_TSTR_SU_3 0x00000008U
6294 
6295 /******************** Bits definition for RTC_TSDR register *****************/
6296 #define RTC_TSDR_WDU 0x0000E000U
6297 #define RTC_TSDR_WDU_0 0x00002000U
6298 #define RTC_TSDR_WDU_1 0x00004000U
6299 #define RTC_TSDR_WDU_2 0x00008000U
6300 #define RTC_TSDR_MT 0x00001000U
6301 #define RTC_TSDR_MU 0x00000F00U
6302 #define RTC_TSDR_MU_0 0x00000100U
6303 #define RTC_TSDR_MU_1 0x00000200U
6304 #define RTC_TSDR_MU_2 0x00000400U
6305 #define RTC_TSDR_MU_3 0x00000800U
6306 #define RTC_TSDR_DT 0x00000030U
6307 #define RTC_TSDR_DT_0 0x00000010U
6308 #define RTC_TSDR_DT_1 0x00000020U
6309 #define RTC_TSDR_DU 0x0000000FU
6310 #define RTC_TSDR_DU_0 0x00000001U
6311 #define RTC_TSDR_DU_1 0x00000002U
6312 #define RTC_TSDR_DU_2 0x00000004U
6313 #define RTC_TSDR_DU_3 0x00000008U
6314 
6315 /******************** Bits definition for RTC_TSSSR register ****************/
6316 #define RTC_TSSSR_SS 0x0000FFFFU
6317 
6318 /******************** Bits definition for RTC_CAL register *****************/
6319 #define RTC_CALR_CALP 0x00008000U
6320 #define RTC_CALR_CALW8 0x00004000U
6321 #define RTC_CALR_CALW16 0x00002000U
6322 #define RTC_CALR_CALM 0x000001FFU
6323 #define RTC_CALR_CALM_0 0x00000001U
6324 #define RTC_CALR_CALM_1 0x00000002U
6325 #define RTC_CALR_CALM_2 0x00000004U
6326 #define RTC_CALR_CALM_3 0x00000008U
6327 #define RTC_CALR_CALM_4 0x00000010U
6328 #define RTC_CALR_CALM_5 0x00000020U
6329 #define RTC_CALR_CALM_6 0x00000040U
6330 #define RTC_CALR_CALM_7 0x00000080U
6331 #define RTC_CALR_CALM_8 0x00000100U
6332 
6333 /******************** Bits definition for RTC_TAFCR register ****************/
6334 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
6335 #define RTC_TAFCR_TSINSEL 0x00020000U
6336 #define RTC_TAFCR_TAMPINSEL 0x00010000U
6337 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
6338 #define RTC_TAFCR_TAMPPRCH 0x00006000U
6339 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
6340 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
6341 #define RTC_TAFCR_TAMPFLT 0x00001800U
6342 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
6343 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
6344 #define RTC_TAFCR_TAMPFREQ 0x00000700U
6345 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
6346 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
6347 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
6348 #define RTC_TAFCR_TAMPTS 0x00000080U
6349 #define RTC_TAFCR_TAMP2TRG 0x00000010U
6350 #define RTC_TAFCR_TAMP2E 0x00000008U
6351 #define RTC_TAFCR_TAMPIE 0x00000004U
6352 #define RTC_TAFCR_TAMP1TRG 0x00000002U
6353 #define RTC_TAFCR_TAMP1E 0x00000001U
6354 
6355 /******************** Bits definition for RTC_ALRMASSR register *************/
6356 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6357 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6358 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6359 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6360 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6361 #define RTC_ALRMASSR_SS 0x00007FFFU
6362 
6363 /******************** Bits definition for RTC_ALRMBSSR register *************/
6364 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6365 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6366 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6367 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6368 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6369 #define RTC_ALRMBSSR_SS 0x00007FFFU
6370 
6371 /******************** Bits definition for RTC_BKP0R register ****************/
6372 #define RTC_BKP0R 0xFFFFFFFFU
6373 
6374 /******************** Bits definition for RTC_BKP1R register ****************/
6375 #define RTC_BKP1R 0xFFFFFFFFU
6376 
6377 /******************** Bits definition for RTC_BKP2R register ****************/
6378 #define RTC_BKP2R 0xFFFFFFFFU
6379 
6380 /******************** Bits definition for RTC_BKP3R register ****************/
6381 #define RTC_BKP3R 0xFFFFFFFFU
6382 
6383 /******************** Bits definition for RTC_BKP4R register ****************/
6384 #define RTC_BKP4R 0xFFFFFFFFU
6385 
6386 /******************** Bits definition for RTC_BKP5R register ****************/
6387 #define RTC_BKP5R 0xFFFFFFFFU
6388 
6389 /******************** Bits definition for RTC_BKP6R register ****************/
6390 #define RTC_BKP6R 0xFFFFFFFFU
6391 
6392 /******************** Bits definition for RTC_BKP7R register ****************/
6393 #define RTC_BKP7R 0xFFFFFFFFU
6394 
6395 /******************** Bits definition for RTC_BKP8R register ****************/
6396 #define RTC_BKP8R 0xFFFFFFFFU
6397 
6398 /******************** Bits definition for RTC_BKP9R register ****************/
6399 #define RTC_BKP9R 0xFFFFFFFFU
6400 
6401 /******************** Bits definition for RTC_BKP10R register ***************/
6402 #define RTC_BKP10R 0xFFFFFFFFU
6403 
6404 /******************** Bits definition for RTC_BKP11R register ***************/
6405 #define RTC_BKP11R 0xFFFFFFFFU
6406 
6407 /******************** Bits definition for RTC_BKP12R register ***************/
6408 #define RTC_BKP12R 0xFFFFFFFFU
6409 
6410 /******************** Bits definition for RTC_BKP13R register ***************/
6411 #define RTC_BKP13R 0xFFFFFFFFU
6412 
6413 /******************** Bits definition for RTC_BKP14R register ***************/
6414 #define RTC_BKP14R 0xFFFFFFFFU
6415 
6416 /******************** Bits definition for RTC_BKP15R register ***************/
6417 #define RTC_BKP15R 0xFFFFFFFFU
6418 
6419 /******************** Bits definition for RTC_BKP16R register ***************/
6420 #define RTC_BKP16R 0xFFFFFFFFU
6421 
6422 /******************** Bits definition for RTC_BKP17R register ***************/
6423 #define RTC_BKP17R 0xFFFFFFFFU
6424 
6425 /******************** Bits definition for RTC_BKP18R register ***************/
6426 #define RTC_BKP18R 0xFFFFFFFFU
6427 
6428 /******************** Bits definition for RTC_BKP19R register ***************/
6429 #define RTC_BKP19R 0xFFFFFFFFU
6430 
6431 /******************************************************************************/
6432 /* */
6433 /* Serial Audio Interface */
6434 /* */
6435 /******************************************************************************/
6436 /******************** Bit definition for SAI_GCR register *******************/
6437 #define SAI_GCR_SYNCIN 0x00000003U
6438 #define SAI_GCR_SYNCIN_0 0x00000001U
6439 #define SAI_GCR_SYNCIN_1 0x00000002U
6441 #define SAI_GCR_SYNCOUT 0x00000030U
6442 #define SAI_GCR_SYNCOUT_0 0x00000010U
6443 #define SAI_GCR_SYNCOUT_1 0x00000020U
6445 /******************* Bit definition for SAI_xCR1 register *******************/
6446 #define SAI_xCR1_MODE 0x00000003U
6447 #define SAI_xCR1_MODE_0 0x00000001U
6448 #define SAI_xCR1_MODE_1 0x00000002U
6450 #define SAI_xCR1_PRTCFG 0x0000000CU
6451 #define SAI_xCR1_PRTCFG_0 0x00000004U
6452 #define SAI_xCR1_PRTCFG_1 0x00000008U
6454 #define SAI_xCR1_DS 0x000000E0U
6455 #define SAI_xCR1_DS_0 0x00000020U
6456 #define SAI_xCR1_DS_1 0x00000040U
6457 #define SAI_xCR1_DS_2 0x00000080U
6459 #define SAI_xCR1_LSBFIRST 0x00000100U
6460 #define SAI_xCR1_CKSTR 0x00000200U
6462 #define SAI_xCR1_SYNCEN 0x00000C00U
6463 #define SAI_xCR1_SYNCEN_0 0x00000400U
6464 #define SAI_xCR1_SYNCEN_1 0x00000800U
6466 #define SAI_xCR1_MONO 0x00001000U
6467 #define SAI_xCR1_OUTDRIV 0x00002000U
6468 #define SAI_xCR1_SAIEN 0x00010000U
6469 #define SAI_xCR1_DMAEN 0x00020000U
6470 #define SAI_xCR1_NODIV 0x00080000U
6472 #define SAI_xCR1_MCKDIV 0x00F00000U
6473 #define SAI_xCR1_MCKDIV_0 0x00100000U
6474 #define SAI_xCR1_MCKDIV_1 0x00200000U
6475 #define SAI_xCR1_MCKDIV_2 0x00400000U
6476 #define SAI_xCR1_MCKDIV_3 0x00800000U
6478 /******************* Bit definition for SAI_xCR2 register *******************/
6479 #define SAI_xCR2_FTH 0x00000007U
6480 #define SAI_xCR2_FTH_0 0x00000001U
6481 #define SAI_xCR2_FTH_1 0x00000002U
6482 #define SAI_xCR2_FTH_2 0x00000004U
6484 #define SAI_xCR2_FFLUSH 0x00000008U
6485 #define SAI_xCR2_TRIS 0x00000010U
6486 #define SAI_xCR2_MUTE 0x00000020U
6487 #define SAI_xCR2_MUTEVAL 0x00000040U
6489 #define SAI_xCR2_MUTECNT 0x00001F80U
6490 #define SAI_xCR2_MUTECNT_0 0x00000080U
6491 #define SAI_xCR2_MUTECNT_1 0x00000100U
6492 #define SAI_xCR2_MUTECNT_2 0x00000200U
6493 #define SAI_xCR2_MUTECNT_3 0x00000400U
6494 #define SAI_xCR2_MUTECNT_4 0x00000800U
6495 #define SAI_xCR2_MUTECNT_5 0x00001000U
6497 #define SAI_xCR2_CPL 0x00002000U
6499 #define SAI_xCR2_COMP 0x0000C000U
6500 #define SAI_xCR2_COMP_0 0x00004000U
6501 #define SAI_xCR2_COMP_1 0x00008000U
6503 /****************** Bit definition for SAI_xFRCR register *******************/
6504 #define SAI_xFRCR_FRL 0x000000FFU
6505 #define SAI_xFRCR_FRL_0 0x00000001U
6506 #define SAI_xFRCR_FRL_1 0x00000002U
6507 #define SAI_xFRCR_FRL_2 0x00000004U
6508 #define SAI_xFRCR_FRL_3 0x00000008U
6509 #define SAI_xFRCR_FRL_4 0x00000010U
6510 #define SAI_xFRCR_FRL_5 0x00000020U
6511 #define SAI_xFRCR_FRL_6 0x00000040U
6512 #define SAI_xFRCR_FRL_7 0x00000080U
6514 #define SAI_xFRCR_FSALL 0x00007F00U
6515 #define SAI_xFRCR_FSALL_0 0x00000100U
6516 #define SAI_xFRCR_FSALL_1 0x00000200U
6517 #define SAI_xFRCR_FSALL_2 0x00000400U
6518 #define SAI_xFRCR_FSALL_3 0x00000800U
6519 #define SAI_xFRCR_FSALL_4 0x00001000U
6520 #define SAI_xFRCR_FSALL_5 0x00002000U
6521 #define SAI_xFRCR_FSALL_6 0x00004000U
6523 #define SAI_xFRCR_FSDEF 0x00010000U
6524 #define SAI_xFRCR_FSPOL 0x00020000U
6525 #define SAI_xFRCR_FSOFF 0x00040000U
6526 /* Legacy defines */
6527 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6528 
6529 /****************** Bit definition for SAI_xSLOTR register *******************/
6530 #define SAI_xSLOTR_FBOFF 0x0000001FU
6531 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6532 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6533 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6534 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6535 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6537 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6538 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6539 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6541 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6542 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6543 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6544 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6545 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6547 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6549 /******************* Bit definition for SAI_xIMR register *******************/
6550 #define SAI_xIMR_OVRUDRIE 0x00000001U
6551 #define SAI_xIMR_MUTEDETIE 0x00000002U
6552 #define SAI_xIMR_WCKCFGIE 0x00000004U
6553 #define SAI_xIMR_FREQIE 0x00000008U
6554 #define SAI_xIMR_CNRDYIE 0x00000010U
6555 #define SAI_xIMR_AFSDETIE 0x00000020U
6556 #define SAI_xIMR_LFSDETIE 0x00000040U
6558 /******************** Bit definition for SAI_xSR register *******************/
6559 #define SAI_xSR_OVRUDR 0x00000001U
6560 #define SAI_xSR_MUTEDET 0x00000002U
6561 #define SAI_xSR_WCKCFG 0x00000004U
6562 #define SAI_xSR_FREQ 0x00000008U
6563 #define SAI_xSR_CNRDY 0x00000010U
6564 #define SAI_xSR_AFSDET 0x00000020U
6565 #define SAI_xSR_LFSDET 0x00000040U
6567 #define SAI_xSR_FLVL 0x00070000U
6568 #define SAI_xSR_FLVL_0 0x00010000U
6569 #define SAI_xSR_FLVL_1 0x00020000U
6570 #define SAI_xSR_FLVL_2 0x00040000U
6572 /****************** Bit definition for SAI_xCLRFR register ******************/
6573 #define SAI_xCLRFR_COVRUDR 0x00000001U
6574 #define SAI_xCLRFR_CMUTEDET 0x00000002U
6575 #define SAI_xCLRFR_CWCKCFG 0x00000004U
6576 #define SAI_xCLRFR_CFREQ 0x00000008U
6577 #define SAI_xCLRFR_CCNRDY 0x00000010U
6578 #define SAI_xCLRFR_CAFSDET 0x00000020U
6579 #define SAI_xCLRFR_CLFSDET 0x00000040U
6581 /****************** Bit definition for SAI_xDR register ******************/
6582 #define SAI_xDR_DATA 0xFFFFFFFFU
6583 
6584 
6585 /******************************************************************************/
6586 /* */
6587 /* SD host Interface */
6588 /* */
6589 /******************************************************************************/
6590 /****************** Bit definition for SDIO_POWER register ******************/
6591 #define SDIO_POWER_PWRCTRL 0x03U
6592 #define SDIO_POWER_PWRCTRL_0 0x01U
6593 #define SDIO_POWER_PWRCTRL_1 0x02U
6595 /****************** Bit definition for SDIO_CLKCR register ******************/
6596 #define SDIO_CLKCR_CLKDIV 0x00FFU
6597 #define SDIO_CLKCR_CLKEN 0x0100U
6598 #define SDIO_CLKCR_PWRSAV 0x0200U
6599 #define SDIO_CLKCR_BYPASS 0x0400U
6601 #define SDIO_CLKCR_WIDBUS 0x1800U
6602 #define SDIO_CLKCR_WIDBUS_0 0x0800U
6603 #define SDIO_CLKCR_WIDBUS_1 0x1000U
6605 #define SDIO_CLKCR_NEGEDGE 0x2000U
6606 #define SDIO_CLKCR_HWFC_EN 0x4000U
6608 /******************* Bit definition for SDIO_ARG register *******************/
6609 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
6611 /******************* Bit definition for SDIO_CMD register *******************/
6612 #define SDIO_CMD_CMDINDEX 0x003FU
6614 #define SDIO_CMD_WAITRESP 0x00C0U
6615 #define SDIO_CMD_WAITRESP_0 0x0040U
6616 #define SDIO_CMD_WAITRESP_1 0x0080U
6618 #define SDIO_CMD_WAITINT 0x0100U
6619 #define SDIO_CMD_WAITPEND 0x0200U
6620 #define SDIO_CMD_CPSMEN 0x0400U
6621 #define SDIO_CMD_SDIOSUSPEND 0x0800U
6622 #define SDIO_CMD_ENCMDCOMPL 0x1000U
6623 #define SDIO_CMD_NIEN 0x2000U
6624 #define SDIO_CMD_CEATACMD 0x4000U
6626 /***************** Bit definition for SDIO_RESPCMD register *****************/
6627 #define SDIO_RESPCMD_RESPCMD 0x3FU
6629 /****************** Bit definition for SDIO_RESP0 register ******************/
6630 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
6632 /****************** Bit definition for SDIO_RESP1 register ******************/
6633 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
6635 /****************** Bit definition for SDIO_RESP2 register ******************/
6636 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
6638 /****************** Bit definition for SDIO_RESP3 register ******************/
6639 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
6641 /****************** Bit definition for SDIO_RESP4 register ******************/
6642 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
6644 /****************** Bit definition for SDIO_DTIMER register *****************/
6645 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
6647 /****************** Bit definition for SDIO_DLEN register *******************/
6648 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
6650 /****************** Bit definition for SDIO_DCTRL register ******************/
6651 #define SDIO_DCTRL_DTEN 0x0001U
6652 #define SDIO_DCTRL_DTDIR 0x0002U
6653 #define SDIO_DCTRL_DTMODE 0x0004U
6654 #define SDIO_DCTRL_DMAEN 0x0008U
6656 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
6657 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
6658 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
6659 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
6660 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
6662 #define SDIO_DCTRL_RWSTART 0x0100U
6663 #define SDIO_DCTRL_RWSTOP 0x0200U
6664 #define SDIO_DCTRL_RWMOD 0x0400U
6665 #define SDIO_DCTRL_SDIOEN 0x0800U
6667 /****************** Bit definition for SDIO_DCOUNT register *****************/
6668 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
6670 /****************** Bit definition for SDIO_STA register ********************/
6671 #define SDIO_STA_CCRCFAIL 0x00000001U
6672 #define SDIO_STA_DCRCFAIL 0x00000002U
6673 #define SDIO_STA_CTIMEOUT 0x00000004U
6674 #define SDIO_STA_DTIMEOUT 0x00000008U
6675 #define SDIO_STA_TXUNDERR 0x00000010U
6676 #define SDIO_STA_RXOVERR 0x00000020U
6677 #define SDIO_STA_CMDREND 0x00000040U
6678 #define SDIO_STA_CMDSENT 0x00000080U
6679 #define SDIO_STA_DATAEND 0x00000100U
6680 #define SDIO_STA_STBITERR 0x00000200U
6681 #define SDIO_STA_DBCKEND 0x00000400U
6682 #define SDIO_STA_CMDACT 0x00000800U
6683 #define SDIO_STA_TXACT 0x00001000U
6684 #define SDIO_STA_RXACT 0x00002000U
6685 #define SDIO_STA_TXFIFOHE 0x00004000U
6686 #define SDIO_STA_RXFIFOHF 0x00008000U
6687 #define SDIO_STA_TXFIFOF 0x00010000U
6688 #define SDIO_STA_RXFIFOF 0x00020000U
6689 #define SDIO_STA_TXFIFOE 0x00040000U
6690 #define SDIO_STA_RXFIFOE 0x00080000U
6691 #define SDIO_STA_TXDAVL 0x00100000U
6692 #define SDIO_STA_RXDAVL 0x00200000U
6693 #define SDIO_STA_SDIOIT 0x00400000U
6694 #define SDIO_STA_CEATAEND 0x00800000U
6696 /******************* Bit definition for SDIO_ICR register *******************/
6697 #define SDIO_ICR_CCRCFAILC 0x00000001U
6698 #define SDIO_ICR_DCRCFAILC 0x00000002U
6699 #define SDIO_ICR_CTIMEOUTC 0x00000004U
6700 #define SDIO_ICR_DTIMEOUTC 0x00000008U
6701 #define SDIO_ICR_TXUNDERRC 0x00000010U
6702 #define SDIO_ICR_RXOVERRC 0x00000020U
6703 #define SDIO_ICR_CMDRENDC 0x00000040U
6704 #define SDIO_ICR_CMDSENTC 0x00000080U
6705 #define SDIO_ICR_DATAENDC 0x00000100U
6706 #define SDIO_ICR_STBITERRC 0x00000200U
6707 #define SDIO_ICR_DBCKENDC 0x00000400U
6708 #define SDIO_ICR_SDIOITC 0x00400000U
6709 #define SDIO_ICR_CEATAENDC 0x00800000U
6711 /****************** Bit definition for SDIO_MASK register *******************/
6712 #define SDIO_MASK_CCRCFAILIE 0x00000001U
6713 #define SDIO_MASK_DCRCFAILIE 0x00000002U
6714 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
6715 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
6716 #define SDIO_MASK_TXUNDERRIE 0x00000010U
6717 #define SDIO_MASK_RXOVERRIE 0x00000020U
6718 #define SDIO_MASK_CMDRENDIE 0x00000040U
6719 #define SDIO_MASK_CMDSENTIE 0x00000080U
6720 #define SDIO_MASK_DATAENDIE 0x00000100U
6721 #define SDIO_MASK_STBITERRIE 0x00000200U
6722 #define SDIO_MASK_DBCKENDIE 0x00000400U
6723 #define SDIO_MASK_CMDACTIE 0x00000800U
6724 #define SDIO_MASK_TXACTIE 0x00001000U
6725 #define SDIO_MASK_RXACTIE 0x00002000U
6726 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
6727 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
6728 #define SDIO_MASK_TXFIFOFIE 0x00010000U
6729 #define SDIO_MASK_RXFIFOFIE 0x00020000U
6730 #define SDIO_MASK_TXFIFOEIE 0x00040000U
6731 #define SDIO_MASK_RXFIFOEIE 0x00080000U
6732 #define SDIO_MASK_TXDAVLIE 0x00100000U
6733 #define SDIO_MASK_RXDAVLIE 0x00200000U
6734 #define SDIO_MASK_SDIOITIE 0x00400000U
6735 #define SDIO_MASK_CEATAENDIE 0x00800000U
6737 /***************** Bit definition for SDIO_FIFOCNT register *****************/
6738 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6740 /****************** Bit definition for SDIO_FIFO register *******************/
6741 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
6743 /******************************************************************************/
6744 /* */
6745 /* Serial Peripheral Interface */
6746 /* */
6747 /******************************************************************************/
6748 /******************* Bit definition for SPI_CR1 register ********************/
6749 #define SPI_CR1_CPHA 0x00000001U
6750 #define SPI_CR1_CPOL 0x00000002U
6751 #define SPI_CR1_MSTR 0x00000004U
6753 #define SPI_CR1_BR 0x00000038U
6754 #define SPI_CR1_BR_0 0x00000008U
6755 #define SPI_CR1_BR_1 0x00000010U
6756 #define SPI_CR1_BR_2 0x00000020U
6758 #define SPI_CR1_SPE 0x00000040U
6759 #define SPI_CR1_LSBFIRST 0x00000080U
6760 #define SPI_CR1_SSI 0x00000100U
6761 #define SPI_CR1_SSM 0x00000200U
6762 #define SPI_CR1_RXONLY 0x00000400U
6763 #define SPI_CR1_DFF 0x00000800U
6764 #define SPI_CR1_CRCNEXT 0x00001000U
6765 #define SPI_CR1_CRCEN 0x00002000U
6766 #define SPI_CR1_BIDIOE 0x00004000U
6767 #define SPI_CR1_BIDIMODE 0x00008000U
6769 /******************* Bit definition for SPI_CR2 register ********************/
6770 #define SPI_CR2_RXDMAEN 0x00000001U
6771 #define SPI_CR2_TXDMAEN 0x00000002U
6772 #define SPI_CR2_SSOE 0x00000004U
6773 #define SPI_CR2_FRF 0x00000010U
6774 #define SPI_CR2_ERRIE 0x00000020U
6775 #define SPI_CR2_RXNEIE 0x00000040U
6776 #define SPI_CR2_TXEIE 0x00000080U
6778 /******************** Bit definition for SPI_SR register ********************/
6779 #define SPI_SR_RXNE 0x00000001U
6780 #define SPI_SR_TXE 0x00000002U
6781 #define SPI_SR_CHSIDE 0x00000004U
6782 #define SPI_SR_UDR 0x00000008U
6783 #define SPI_SR_CRCERR 0x00000010U
6784 #define SPI_SR_MODF 0x00000020U
6785 #define SPI_SR_OVR 0x00000040U
6786 #define SPI_SR_BSY 0x00000080U
6787 #define SPI_SR_FRE 0x00000100U
6789 /******************** Bit definition for SPI_DR register ********************/
6790 #define SPI_DR_DR 0x0000FFFFU
6792 /******************* Bit definition for SPI_CRCPR register ******************/
6793 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
6795 /****************** Bit definition for SPI_RXCRCR register ******************/
6796 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
6798 /****************** Bit definition for SPI_TXCRCR register ******************/
6799 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
6801 /****************** Bit definition for SPI_I2SCFGR register *****************/
6802 #define SPI_I2SCFGR_CHLEN 0x00000001U
6804 #define SPI_I2SCFGR_DATLEN 0x00000006U
6805 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
6806 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
6808 #define SPI_I2SCFGR_CKPOL 0x00000008U
6810 #define SPI_I2SCFGR_I2SSTD 0x00000030U
6811 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
6812 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
6814 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
6816 #define SPI_I2SCFGR_I2SCFG 0x00000300U
6817 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
6818 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
6820 #define SPI_I2SCFGR_I2SE 0x00000400U
6821 #define SPI_I2SCFGR_I2SMOD 0x00000800U
6823 /****************** Bit definition for SPI_I2SPR register *******************/
6824 #define SPI_I2SPR_I2SDIV 0x000000FFU
6825 #define SPI_I2SPR_ODD 0x00000100U
6826 #define SPI_I2SPR_MCKOE 0x00000200U
6828 /******************************************************************************/
6829 /* */
6830 /* SYSCFG */
6831 /* */
6832 /******************************************************************************/
6833 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6834 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
6835 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
6836 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
6837 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
6838 
6839 #define SYSCFG_MEMRMP_UFB_MODE 0x00000100U
6840 #define SYSCFG_SWP_FMC 0x00000C00U
6842 /****************** Bit definition for SYSCFG_PMC register ******************/
6843 #define SYSCFG_PMC_ADCxDC2 0x00070000U
6844 #define SYSCFG_PMC_ADC1DC2 0x00010000U
6845 #define SYSCFG_PMC_ADC2DC2 0x00020000U
6846 #define SYSCFG_PMC_ADC3DC2 0x00040000U
6848 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
6849 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
6850 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
6851 
6852 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6853 #define SYSCFG_EXTICR1_EXTI0 0x000FU
6854 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
6855 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
6856 #define SYSCFG_EXTICR1_EXTI3 0xF000U
6860 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
6861 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
6862 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
6863 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
6864 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
6865 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
6866 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
6867 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
6868 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
6869 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
6870 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
6875 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
6876 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
6877 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
6878 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
6879 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
6880 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
6881 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
6882 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
6883 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
6884 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
6885 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
6891 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
6892 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
6893 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
6894 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
6895 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
6896 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
6897 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
6898 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
6899 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
6900 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
6901 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
6907 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
6908 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
6909 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
6910 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
6911 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
6912 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
6913 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
6914 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
6915 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
6916 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
6917 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
6920 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6921 #define SYSCFG_EXTICR2_EXTI4 0x000FU
6922 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
6923 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
6924 #define SYSCFG_EXTICR2_EXTI7 0xF000U
6928 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
6929 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
6930 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
6931 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
6932 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
6933 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
6934 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
6935 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
6936 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
6937 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
6938 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
6943 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
6944 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
6945 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
6946 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
6947 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
6948 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
6949 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
6950 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
6951 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
6952 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
6953 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
6958 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
6959 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
6960 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
6961 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
6962 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
6963 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
6964 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
6965 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
6966 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
6967 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
6968 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
6974 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
6975 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
6976 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
6977 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
6978 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
6979 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
6980 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
6981 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
6982 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
6983 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
6984 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
6986 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6987 #define SYSCFG_EXTICR3_EXTI8 0x000FU
6988 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
6989 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
6990 #define SYSCFG_EXTICR3_EXTI11 0xF000U
6995 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
6996 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
6997 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
6998 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
6999 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
7000 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
7001 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
7002 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
7003 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
7004 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
7009 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
7010 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
7011 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
7012 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
7013 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
7014 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
7015 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
7016 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
7017 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
7018 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
7024 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
7025 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
7026 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
7027 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
7028 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
7029 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
7030 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
7031 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
7032 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
7033 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
7039 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
7040 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
7041 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
7042 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
7043 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
7044 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
7045 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
7046 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
7047 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
7048 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
7051 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7052 #define SYSCFG_EXTICR4_EXTI12 0x000FU
7053 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
7054 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
7055 #define SYSCFG_EXTICR4_EXTI15 0xF000U
7059 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
7060 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
7061 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
7062 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
7063 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
7064 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
7065 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
7066 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
7067 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
7068 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
7074 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
7075 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
7076 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
7077 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
7078 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
7079 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
7080 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
7081 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
7082 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
7083 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
7089 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
7090 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
7091 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
7092 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
7093 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
7094 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
7095 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
7096 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
7097 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
7098 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
7104 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
7105 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
7106 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
7107 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
7108 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
7109 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
7110 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
7111 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
7112 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
7113 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
7115 /****************** Bit definition for SYSCFG_CMPCR register ****************/
7116 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
7117 #define SYSCFG_CMPCR_READY 0x00000100U
7119 /******************************************************************************/
7120 /* */
7121 /* TIM */
7122 /* */
7123 /******************************************************************************/
7124 /******************* Bit definition for TIM_CR1 register ********************/
7125 #define TIM_CR1_CEN 0x0001U
7126 #define TIM_CR1_UDIS 0x0002U
7127 #define TIM_CR1_URS 0x0004U
7128 #define TIM_CR1_OPM 0x0008U
7129 #define TIM_CR1_DIR 0x0010U
7131 #define TIM_CR1_CMS 0x0060U
7132 #define TIM_CR1_CMS_0 0x0020U
7133 #define TIM_CR1_CMS_1 0x0040U
7135 #define TIM_CR1_ARPE 0x0080U
7137 #define TIM_CR1_CKD 0x0300U
7138 #define TIM_CR1_CKD_0 0x0100U
7139 #define TIM_CR1_CKD_1 0x0200U
7141 /******************* Bit definition for TIM_CR2 register ********************/
7142 #define TIM_CR2_CCPC 0x0001U
7143 #define TIM_CR2_CCUS 0x0004U
7144 #define TIM_CR2_CCDS 0x0008U
7146 #define TIM_CR2_MMS 0x0070U
7147 #define TIM_CR2_MMS_0 0x0010U
7148 #define TIM_CR2_MMS_1 0x0020U
7149 #define TIM_CR2_MMS_2 0x0040U
7151 #define TIM_CR2_TI1S 0x0080U
7152 #define TIM_CR2_OIS1 0x0100U
7153 #define TIM_CR2_OIS1N 0x0200U
7154 #define TIM_CR2_OIS2 0x0400U
7155 #define TIM_CR2_OIS2N 0x0800U
7156 #define TIM_CR2_OIS3 0x1000U
7157 #define TIM_CR2_OIS3N 0x2000U
7158 #define TIM_CR2_OIS4 0x4000U
7160 /******************* Bit definition for TIM_SMCR register *******************/
7161 #define TIM_SMCR_SMS 0x0007U
7162 #define TIM_SMCR_SMS_0 0x0001U
7163 #define TIM_SMCR_SMS_1 0x0002U
7164 #define TIM_SMCR_SMS_2 0x0004U
7166 #define TIM_SMCR_TS 0x0070U
7167 #define TIM_SMCR_TS_0 0x0010U
7168 #define TIM_SMCR_TS_1 0x0020U
7169 #define TIM_SMCR_TS_2 0x0040U
7171 #define TIM_SMCR_MSM 0x0080U
7173 #define TIM_SMCR_ETF 0x0F00U
7174 #define TIM_SMCR_ETF_0 0x0100U
7175 #define TIM_SMCR_ETF_1 0x0200U
7176 #define TIM_SMCR_ETF_2 0x0400U
7177 #define TIM_SMCR_ETF_3 0x0800U
7179 #define TIM_SMCR_ETPS 0x3000U
7180 #define TIM_SMCR_ETPS_0 0x1000U
7181 #define TIM_SMCR_ETPS_1 0x2000U
7183 #define TIM_SMCR_ECE 0x4000U
7184 #define TIM_SMCR_ETP 0x8000U
7186 /******************* Bit definition for TIM_DIER register *******************/
7187 #define TIM_DIER_UIE 0x0001U
7188 #define TIM_DIER_CC1IE 0x0002U
7189 #define TIM_DIER_CC2IE 0x0004U
7190 #define TIM_DIER_CC3IE 0x0008U
7191 #define TIM_DIER_CC4IE 0x0010U
7192 #define TIM_DIER_COMIE 0x0020U
7193 #define TIM_DIER_TIE 0x0040U
7194 #define TIM_DIER_BIE 0x0080U
7195 #define TIM_DIER_UDE 0x0100U
7196 #define TIM_DIER_CC1DE 0x0200U
7197 #define TIM_DIER_CC2DE 0x0400U
7198 #define TIM_DIER_CC3DE 0x0800U
7199 #define TIM_DIER_CC4DE 0x1000U
7200 #define TIM_DIER_COMDE 0x2000U
7201 #define TIM_DIER_TDE 0x4000U
7203 /******************** Bit definition for TIM_SR register ********************/
7204 #define TIM_SR_UIF 0x0001U
7205 #define TIM_SR_CC1IF 0x0002U
7206 #define TIM_SR_CC2IF 0x0004U
7207 #define TIM_SR_CC3IF 0x0008U
7208 #define TIM_SR_CC4IF 0x0010U
7209 #define TIM_SR_COMIF 0x0020U
7210 #define TIM_SR_TIF 0x0040U
7211 #define TIM_SR_BIF 0x0080U
7212 #define TIM_SR_CC1OF 0x0200U
7213 #define TIM_SR_CC2OF 0x0400U
7214 #define TIM_SR_CC3OF 0x0800U
7215 #define TIM_SR_CC4OF 0x1000U
7217 /******************* Bit definition for TIM_EGR register ********************/
7218 #define TIM_EGR_UG 0x01U
7219 #define TIM_EGR_CC1G 0x02U
7220 #define TIM_EGR_CC2G 0x04U
7221 #define TIM_EGR_CC3G 0x08U
7222 #define TIM_EGR_CC4G 0x10U
7223 #define TIM_EGR_COMG 0x20U
7224 #define TIM_EGR_TG 0x40U
7225 #define TIM_EGR_BG 0x80U
7227 /****************** Bit definition for TIM_CCMR1 register *******************/
7228 #define TIM_CCMR1_CC1S 0x0003U
7229 #define TIM_CCMR1_CC1S_0 0x0001U
7230 #define TIM_CCMR1_CC1S_1 0x0002U
7232 #define TIM_CCMR1_OC1FE 0x0004U
7233 #define TIM_CCMR1_OC1PE 0x0008U
7235 #define TIM_CCMR1_OC1M 0x0070U
7236 #define TIM_CCMR1_OC1M_0 0x0010U
7237 #define TIM_CCMR1_OC1M_1 0x0020U
7238 #define TIM_CCMR1_OC1M_2 0x0040U
7240 #define TIM_CCMR1_OC1CE 0x0080U
7242 #define TIM_CCMR1_CC2S 0x0300U
7243 #define TIM_CCMR1_CC2S_0 0x0100U
7244 #define TIM_CCMR1_CC2S_1 0x0200U
7246 #define TIM_CCMR1_OC2FE 0x0400U
7247 #define TIM_CCMR1_OC2PE 0x0800U
7249 #define TIM_CCMR1_OC2M 0x7000U
7250 #define TIM_CCMR1_OC2M_0 0x1000U
7251 #define TIM_CCMR1_OC2M_1 0x2000U
7252 #define TIM_CCMR1_OC2M_2 0x4000U
7254 #define TIM_CCMR1_OC2CE 0x8000U
7256 /*----------------------------------------------------------------------------*/
7257 
7258 #define TIM_CCMR1_IC1PSC 0x000CU
7259 #define TIM_CCMR1_IC1PSC_0 0x0004U
7260 #define TIM_CCMR1_IC1PSC_1 0x0008U
7262 #define TIM_CCMR1_IC1F 0x00F0U
7263 #define TIM_CCMR1_IC1F_0 0x0010U
7264 #define TIM_CCMR1_IC1F_1 0x0020U
7265 #define TIM_CCMR1_IC1F_2 0x0040U
7266 #define TIM_CCMR1_IC1F_3 0x0080U
7268 #define TIM_CCMR1_IC2PSC 0x0C00U
7269 #define TIM_CCMR1_IC2PSC_0 0x0400U
7270 #define TIM_CCMR1_IC2PSC_1 0x0800U
7272 #define TIM_CCMR1_IC2F 0xF000U
7273 #define TIM_CCMR1_IC2F_0 0x1000U
7274 #define TIM_CCMR1_IC2F_1 0x2000U
7275 #define TIM_CCMR1_IC2F_2 0x4000U
7276 #define TIM_CCMR1_IC2F_3 0x8000U
7278 /****************** Bit definition for TIM_CCMR2 register *******************/
7279 #define TIM_CCMR2_CC3S 0x0003U
7280 #define TIM_CCMR2_CC3S_0 0x0001U
7281 #define TIM_CCMR2_CC3S_1 0x0002U
7283 #define TIM_CCMR2_OC3FE 0x0004U
7284 #define TIM_CCMR2_OC3PE 0x0008U
7286 #define TIM_CCMR2_OC3M 0x0070U
7287 #define TIM_CCMR2_OC3M_0 0x0010U
7288 #define TIM_CCMR2_OC3M_1 0x0020U
7289 #define TIM_CCMR2_OC3M_2 0x0040U
7291 #define TIM_CCMR2_OC3CE 0x0080U
7293 #define TIM_CCMR2_CC4S 0x0300U
7294 #define TIM_CCMR2_CC4S_0 0x0100U
7295 #define TIM_CCMR2_CC4S_1 0x0200U
7297 #define TIM_CCMR2_OC4FE 0x0400U
7298 #define TIM_CCMR2_OC4PE 0x0800U
7300 #define TIM_CCMR2_OC4M 0x7000U
7301 #define TIM_CCMR2_OC4M_0 0x1000U
7302 #define TIM_CCMR2_OC4M_1 0x2000U
7303 #define TIM_CCMR2_OC4M_2 0x4000U
7305 #define TIM_CCMR2_OC4CE 0x8000U
7307 /*----------------------------------------------------------------------------*/
7308 
7309 #define TIM_CCMR2_IC3PSC 0x000CU
7310 #define TIM_CCMR2_IC3PSC_0 0x0004U
7311 #define TIM_CCMR2_IC3PSC_1 0x0008U
7313 #define TIM_CCMR2_IC3F 0x00F0U
7314 #define TIM_CCMR2_IC3F_0 0x0010U
7315 #define TIM_CCMR2_IC3F_1 0x0020U
7316 #define TIM_CCMR2_IC3F_2 0x0040U
7317 #define TIM_CCMR2_IC3F_3 0x0080U
7319 #define TIM_CCMR2_IC4PSC 0x0C00U
7320 #define TIM_CCMR2_IC4PSC_0 0x0400U
7321 #define TIM_CCMR2_IC4PSC_1 0x0800U
7323 #define TIM_CCMR2_IC4F 0xF000U
7324 #define TIM_CCMR2_IC4F_0 0x1000U
7325 #define TIM_CCMR2_IC4F_1 0x2000U
7326 #define TIM_CCMR2_IC4F_2 0x4000U
7327 #define TIM_CCMR2_IC4F_3 0x8000U
7329 /******************* Bit definition for TIM_CCER register *******************/
7330 #define TIM_CCER_CC1E 0x0001U
7331 #define TIM_CCER_CC1P 0x0002U
7332 #define TIM_CCER_CC1NE 0x0004U
7333 #define TIM_CCER_CC1NP 0x0008U
7334 #define TIM_CCER_CC2E 0x0010U
7335 #define TIM_CCER_CC2P 0x0020U
7336 #define TIM_CCER_CC2NE 0x0040U
7337 #define TIM_CCER_CC2NP 0x0080U
7338 #define TIM_CCER_CC3E 0x0100U
7339 #define TIM_CCER_CC3P 0x0200U
7340 #define TIM_CCER_CC3NE 0x0400U
7341 #define TIM_CCER_CC3NP 0x0800U
7342 #define TIM_CCER_CC4E 0x1000U
7343 #define TIM_CCER_CC4P 0x2000U
7344 #define TIM_CCER_CC4NP 0x8000U
7346 /******************* Bit definition for TIM_CNT register ********************/
7347 #define TIM_CNT_CNT 0xFFFFU
7349 /******************* Bit definition for TIM_PSC register ********************/
7350 #define TIM_PSC_PSC 0xFFFFU
7352 /******************* Bit definition for TIM_ARR register ********************/
7353 #define TIM_ARR_ARR 0xFFFFU
7355 /******************* Bit definition for TIM_RCR register ********************/
7356 #define TIM_RCR_REP 0xFFU
7358 /******************* Bit definition for TIM_CCR1 register *******************/
7359 #define TIM_CCR1_CCR1 0xFFFFU
7361 /******************* Bit definition for TIM_CCR2 register *******************/
7362 #define TIM_CCR2_CCR2 0xFFFFU
7364 /******************* Bit definition for TIM_CCR3 register *******************/
7365 #define TIM_CCR3_CCR3 0xFFFFU
7367 /******************* Bit definition for TIM_CCR4 register *******************/
7368 #define TIM_CCR4_CCR4 0xFFFFU
7370 /******************* Bit definition for TIM_BDTR register *******************/
7371 #define TIM_BDTR_DTG 0x00FFU
7372 #define TIM_BDTR_DTG_0 0x0001U
7373 #define TIM_BDTR_DTG_1 0x0002U
7374 #define TIM_BDTR_DTG_2 0x0004U
7375 #define TIM_BDTR_DTG_3 0x0008U
7376 #define TIM_BDTR_DTG_4 0x0010U
7377 #define TIM_BDTR_DTG_5 0x0020U
7378 #define TIM_BDTR_DTG_6 0x0040U
7379 #define TIM_BDTR_DTG_7 0x0080U
7381 #define TIM_BDTR_LOCK 0x0300U
7382 #define TIM_BDTR_LOCK_0 0x0100U
7383 #define TIM_BDTR_LOCK_1 0x0200U
7385 #define TIM_BDTR_OSSI 0x0400U
7386 #define TIM_BDTR_OSSR 0x0800U
7387 #define TIM_BDTR_BKE 0x1000U
7388 #define TIM_BDTR_BKP 0x2000U
7389 #define TIM_BDTR_AOE 0x4000U
7390 #define TIM_BDTR_MOE 0x8000U
7392 /******************* Bit definition for TIM_DCR register ********************/
7393 #define TIM_DCR_DBA 0x001FU
7394 #define TIM_DCR_DBA_0 0x0001U
7395 #define TIM_DCR_DBA_1 0x0002U
7396 #define TIM_DCR_DBA_2 0x0004U
7397 #define TIM_DCR_DBA_3 0x0008U
7398 #define TIM_DCR_DBA_4 0x0010U
7400 #define TIM_DCR_DBL 0x1F00U
7401 #define TIM_DCR_DBL_0 0x0100U
7402 #define TIM_DCR_DBL_1 0x0200U
7403 #define TIM_DCR_DBL_2 0x0400U
7404 #define TIM_DCR_DBL_3 0x0800U
7405 #define TIM_DCR_DBL_4 0x1000U
7407 /******************* Bit definition for TIM_DMAR register *******************/
7408 #define TIM_DMAR_DMAB 0xFFFFU
7410 /******************* Bit definition for TIM_OR register *********************/
7411 #define TIM_OR_TI4_RMP 0x00C0U
7412 #define TIM_OR_TI4_RMP_0 0x0040U
7413 #define TIM_OR_TI4_RMP_1 0x0080U
7414 #define TIM_OR_ITR1_RMP 0x0C00U
7415 #define TIM_OR_ITR1_RMP_0 0x0400U
7416 #define TIM_OR_ITR1_RMP_1 0x0800U
7419 /******************************************************************************/
7420 /* */
7421 /* Universal Synchronous Asynchronous Receiver Transmitter */
7422 /* */
7423 /******************************************************************************/
7424 /******************* Bit definition for USART_SR register *******************/
7425 #define USART_SR_PE 0x0001U
7426 #define USART_SR_FE 0x0002U
7427 #define USART_SR_NE 0x0004U
7428 #define USART_SR_ORE 0x0008U
7429 #define USART_SR_IDLE 0x0010U
7430 #define USART_SR_RXNE 0x0020U
7431 #define USART_SR_TC 0x0040U
7432 #define USART_SR_TXE 0x0080U
7433 #define USART_SR_LBD 0x0100U
7434 #define USART_SR_CTS 0x0200U
7436 /******************* Bit definition for USART_DR register *******************/
7437 #define USART_DR_DR 0x01FFU
7439 /****************** Bit definition for USART_BRR register *******************/
7440 #define USART_BRR_DIV_Fraction 0x000FU
7441 #define USART_BRR_DIV_Mantissa 0xFFF0U
7443 /****************** Bit definition for USART_CR1 register *******************/
7444 #define USART_CR1_SBK 0x0001U
7445 #define USART_CR1_RWU 0x0002U
7446 #define USART_CR1_RE 0x0004U
7447 #define USART_CR1_TE 0x0008U
7448 #define USART_CR1_IDLEIE 0x0010U
7449 #define USART_CR1_RXNEIE 0x0020U
7450 #define USART_CR1_TCIE 0x0040U
7451 #define USART_CR1_TXEIE 0x0080U
7452 #define USART_CR1_PEIE 0x0100U
7453 #define USART_CR1_PS 0x0200U
7454 #define USART_CR1_PCE 0x0400U
7455 #define USART_CR1_WAKE 0x0800U
7456 #define USART_CR1_M 0x1000U
7457 #define USART_CR1_UE 0x2000U
7458 #define USART_CR1_OVER8 0x8000U
7460 /****************** Bit definition for USART_CR2 register *******************/
7461 #define USART_CR2_ADD 0x000FU
7462 #define USART_CR2_LBDL 0x0020U
7463 #define USART_CR2_LBDIE 0x0040U
7464 #define USART_CR2_LBCL 0x0100U
7465 #define USART_CR2_CPHA 0x0200U
7466 #define USART_CR2_CPOL 0x0400U
7467 #define USART_CR2_CLKEN 0x0800U
7469 #define USART_CR2_STOP 0x3000U
7470 #define USART_CR2_STOP_0 0x1000U
7471 #define USART_CR2_STOP_1 0x2000U
7473 #define USART_CR2_LINEN 0x4000U
7475 /****************** Bit definition for USART_CR3 register *******************/
7476 #define USART_CR3_EIE 0x0001U
7477 #define USART_CR3_IREN 0x0002U
7478 #define USART_CR3_IRLP 0x0004U
7479 #define USART_CR3_HDSEL 0x0008U
7480 #define USART_CR3_NACK 0x0010U
7481 #define USART_CR3_SCEN 0x0020U
7482 #define USART_CR3_DMAR 0x0040U
7483 #define USART_CR3_DMAT 0x0080U
7484 #define USART_CR3_RTSE 0x0100U
7485 #define USART_CR3_CTSE 0x0200U
7486 #define USART_CR3_CTSIE 0x0400U
7487 #define USART_CR3_ONEBIT 0x0800U
7489 /****************** Bit definition for USART_GTPR register ******************/
7490 #define USART_GTPR_PSC 0x00FFU
7491 #define USART_GTPR_PSC_0 0x0001U
7492 #define USART_GTPR_PSC_1 0x0002U
7493 #define USART_GTPR_PSC_2 0x0004U
7494 #define USART_GTPR_PSC_3 0x0008U
7495 #define USART_GTPR_PSC_4 0x0010U
7496 #define USART_GTPR_PSC_5 0x0020U
7497 #define USART_GTPR_PSC_6 0x0040U
7498 #define USART_GTPR_PSC_7 0x0080U
7500 #define USART_GTPR_GT 0xFF00U
7502 /******************************************************************************/
7503 /* */
7504 /* Window WATCHDOG */
7505 /* */
7506 /******************************************************************************/
7507 /******************* Bit definition for WWDG_CR register ********************/
7508 #define WWDG_CR_T 0x7FU
7509 #define WWDG_CR_T_0 0x01U
7510 #define WWDG_CR_T_1 0x02U
7511 #define WWDG_CR_T_2 0x04U
7512 #define WWDG_CR_T_3 0x08U
7513 #define WWDG_CR_T_4 0x10U
7514 #define WWDG_CR_T_5 0x20U
7515 #define WWDG_CR_T_6 0x40U
7516 /* Legacy defines */
7517 #define WWDG_CR_T0 WWDG_CR_T_0
7518 #define WWDG_CR_T1 WWDG_CR_T_1
7519 #define WWDG_CR_T2 WWDG_CR_T_2
7520 #define WWDG_CR_T3 WWDG_CR_T_3
7521 #define WWDG_CR_T4 WWDG_CR_T_4
7522 #define WWDG_CR_T5 WWDG_CR_T_5
7523 #define WWDG_CR_T6 WWDG_CR_T_6
7524 
7525 #define WWDG_CR_WDGA 0x80U
7527 /******************* Bit definition for WWDG_CFR register *******************/
7528 #define WWDG_CFR_W 0x007FU
7529 #define WWDG_CFR_W_0 0x0001U
7530 #define WWDG_CFR_W_1 0x0002U
7531 #define WWDG_CFR_W_2 0x0004U
7532 #define WWDG_CFR_W_3 0x0008U
7533 #define WWDG_CFR_W_4 0x0010U
7534 #define WWDG_CFR_W_5 0x0020U
7535 #define WWDG_CFR_W_6 0x0040U
7536 /* Legacy defines */
7537 #define WWDG_CFR_W0 WWDG_CFR_W_0
7538 #define WWDG_CFR_W1 WWDG_CFR_W_1
7539 #define WWDG_CFR_W2 WWDG_CFR_W_2
7540 #define WWDG_CFR_W3 WWDG_CFR_W_3
7541 #define WWDG_CFR_W4 WWDG_CFR_W_4
7542 #define WWDG_CFR_W5 WWDG_CFR_W_5
7543 #define WWDG_CFR_W6 WWDG_CFR_W_6
7544 
7545 #define WWDG_CFR_WDGTB 0x0180U
7546 #define WWDG_CFR_WDGTB_0 0x0080U
7547 #define WWDG_CFR_WDGTB_1 0x0100U
7548 /* Legacy defines */
7549 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
7550 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
7551 
7552 #define WWDG_CFR_EWI 0x0200U
7554 /******************* Bit definition for WWDG_SR register ********************/
7555 #define WWDG_SR_EWIF 0x01U
7558 /******************************************************************************/
7559 /* */
7560 /* DBG */
7561 /* */
7562 /******************************************************************************/
7563 /******************** Bit definition for DBGMCU_IDCODE register *************/
7564 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
7565 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
7566 
7567 /******************** Bit definition for DBGMCU_CR register *****************/
7568 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
7569 #define DBGMCU_CR_DBG_STOP 0x00000002U
7570 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
7571 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
7572 
7573 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
7574 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
7575 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
7577 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
7578 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
7579 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
7580 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
7581 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
7582 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
7583 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
7584 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
7585 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
7586 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
7587 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
7588 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
7589 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
7590 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
7591 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
7592 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
7593 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
7594 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
7595 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
7596 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
7597 
7598 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
7599 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
7600 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
7601 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
7602 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
7603 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
7604 
7605 /******************************************************************************/
7606 /* */
7607 /* Ethernet MAC Registers bits definitions */
7608 /* */
7609 /******************************************************************************/
7610 /* Bit definition for Ethernet MAC Control Register register */
7611 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
7612 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
7613 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
7614 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
7615  #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
7616  #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
7617  #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
7618  #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
7619  #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
7620  #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
7621  #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
7622 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
7623 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
7624 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
7625 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
7626 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
7627 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
7628 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
7629 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
7630 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7631  a transmission attempt during retries after a collision: 0 =< r <2^k */
7632  #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
7633  #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
7634  #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
7635  #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
7636 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
7637 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
7638 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
7639 
7640 /* Bit definition for Ethernet MAC Frame Filter Register */
7641 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
7642 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
7643 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
7644 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
7645 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
7646  #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
7647  #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
7648  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
7649 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
7650 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
7651 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
7652 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
7653 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
7654 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
7655 
7656 /* Bit definition for Ethernet MAC Hash Table High Register */
7657 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
7658 
7659 /* Bit definition for Ethernet MAC Hash Table Low Register */
7660 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
7661 
7662 /* Bit definition for Ethernet MAC MII Address Register */
7663 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
7664 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
7665 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
7666  #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
7667  #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
7668  #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7669  #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7670  #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
7671 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
7672 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
7673 
7674 /* Bit definition for Ethernet MAC MII Data Register */
7675 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
7676 
7677 /* Bit definition for Ethernet MAC Flow Control Register */
7678 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
7679 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
7680 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
7681  #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
7682  #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
7683  #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
7684  #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
7685 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
7686 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
7687 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
7688 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
7689 
7690 /* Bit definition for Ethernet MAC VLAN Tag Register */
7691 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
7692 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
7693 
7694 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7695 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
7696 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7697  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7698 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7699  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7700  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7701  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7702  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7703  RSVD - Filter1 Command - RSVD - Filter0 Command
7704  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7705  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7706  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7707 
7708 /* Bit definition for Ethernet MAC PMT Control and Status Register */
7709 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
7710 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
7711 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
7712 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
7713 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
7714 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
7715 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
7716 
7717 /* Bit definition for Ethernet MAC Status Register */
7718 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
7719 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
7720 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
7721 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
7722 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
7723 
7724 /* Bit definition for Ethernet MAC Interrupt Mask Register */
7725 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
7726 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
7727 
7728 /* Bit definition for Ethernet MAC Address0 High Register */
7729 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
7730 
7731 /* Bit definition for Ethernet MAC Address0 Low Register */
7732 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
7733 
7734 /* Bit definition for Ethernet MAC Address1 High Register */
7735 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
7736 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
7737 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7738  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7739  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7740  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7741  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7742  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7743  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
7744 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
7745 
7746 /* Bit definition for Ethernet MAC Address1 Low Register */
7747 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
7748 
7749 /* Bit definition for Ethernet MAC Address2 High Register */
7750 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
7751 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
7752 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
7753  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7754  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7755  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7756  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7757  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7758  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7759 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
7760 
7761 /* Bit definition for Ethernet MAC Address2 Low Register */
7762 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
7763 
7764 /* Bit definition for Ethernet MAC Address3 High Register */
7765 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
7766 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
7767 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
7768  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7769  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7770  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7771  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7772  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7773  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7774 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
7775 
7776 /* Bit definition for Ethernet MAC Address3 Low Register */
7777 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
7778 
7779 /******************************************************************************/
7780 /* Ethernet MMC Registers bits definition */
7781 /******************************************************************************/
7782 
7783 /* Bit definition for Ethernet MMC Contol Register */
7784 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
7785 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
7786 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
7787 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
7788 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
7789 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
7790 
7791 /* Bit definition for Ethernet MMC Receive Interrupt Register */
7792 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
7793 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
7794 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
7795 
7796 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
7797 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
7798 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
7799 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
7800 
7801 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
7802 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
7803 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
7804 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
7805 
7806 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
7807 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
7808 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
7809 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
7810 
7811 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
7812 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
7813 
7814 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
7815 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
7816 
7817 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
7818 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
7819 
7820 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
7821 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
7822 
7823 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
7824 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
7825 
7826 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
7827 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
7828 
7829 /******************************************************************************/
7830 /* Ethernet PTP Registers bits definition */
7831 /******************************************************************************/
7832 
7833 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
7834 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
7835 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
7836 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
7837 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
7838 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
7839 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
7840 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
7841 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
7842 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
7843 
7844 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
7845 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
7846 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
7847 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
7848 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
7849 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
7850 
7851 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
7852 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
7853 
7854 /* Bit definition for Ethernet PTP Time Stamp High Register */
7855 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
7856 
7857 /* Bit definition for Ethernet PTP Time Stamp Low Register */
7858 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
7859 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
7860 
7861 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
7862 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
7863 
7864 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7865 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
7866 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
7867 
7868 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
7869 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
7870 
7871 /* Bit definition for Ethernet PTP Target Time High Register */
7872 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
7873 
7874 /* Bit definition for Ethernet PTP Target Time Low Register */
7875 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
7876 
7877 /* Bit definition for Ethernet PTP Time Stamp Status Register */
7878 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
7879 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
7880 
7881 /******************************************************************************/
7882 /* Ethernet DMA Registers bits definition */
7883 /******************************************************************************/
7884 
7885 /* Bit definition for Ethernet DMA Bus Mode Register */
7886 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
7887 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
7888 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
7889 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
7890  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7891  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7892  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7893  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7894  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7895  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7896  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7897  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7898  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7899  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7900  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7901  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7902 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
7903 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
7904  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
7905  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
7906  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
7907  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
7908 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
7909  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7910  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7911  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7912  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7913  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7914  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7915  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7916  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7917  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7918  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7919  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7920  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7921 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
7922 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
7923 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
7924 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
7925 
7926 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7927 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
7928 
7929 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
7930 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
7931 
7932 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7933 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
7934 
7935 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7936 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
7937 
7938 /* Bit definition for Ethernet DMA Status Register */
7939 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
7940 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
7941 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
7942 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
7943  /* combination with EBS[2:0] for GetFlagStatus function */
7944  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
7945  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
7946  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
7947 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
7948  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
7949  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
7950  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
7951  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
7952  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
7953  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
7954 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
7955  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
7956  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
7957  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
7958  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
7959  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
7960  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
7961 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
7962 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
7963 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
7964 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
7965 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
7966 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
7967 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
7968 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
7969 #define ETH_DMASR_RS 0x00000040U /* Receive status */
7970 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
7971 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
7972 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
7973 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
7974 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
7975 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
7976 
7977 /* Bit definition for Ethernet DMA Operation Mode Register */
7978 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
7979 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
7980 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
7981 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
7982 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
7983 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
7984  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7985  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7986  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7987  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7988  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7989  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7990  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7991  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7992 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
7993 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
7994 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
7995 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
7996  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
7997  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
7998  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
7999  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
8000 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
8001 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
8002 
8003 /* Bit definition for Ethernet DMA Interrupt Enable Register */
8004 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
8005 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
8006 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
8007 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
8008 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
8009 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
8010 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
8011 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
8012 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
8013 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
8014 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
8015 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
8016 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
8017 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
8018 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
8019 
8020 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8021 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
8022 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
8023 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
8024 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
8025 
8026 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8027 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
8028 
8029 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8030 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
8031 
8032 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8033 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
8034 
8035 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8036 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
8037 
8038 /******************************************************************************/
8039 /* */
8040 /* USB_OTG */
8041 /* */
8042 /******************************************************************************/
8043 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
8044 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
8045 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
8046 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
8047 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
8048 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
8049 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
8050 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
8051 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
8052 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
8053 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
8055 /******************** Bit definition forUSB_OTG_HCFG register ********************/
8056 
8057 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
8058 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
8059 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
8060 #define USB_OTG_HCFG_FSLSS 0x00000004U
8062 /******************** Bit definition forUSB_OTG_DCFG register ********************/
8063 
8064 #define USB_OTG_DCFG_DSPD 0x00000003U
8065 #define USB_OTG_DCFG_DSPD_0 0x00000001U
8066 #define USB_OTG_DCFG_DSPD_1 0x00000002U
8067 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
8069 #define USB_OTG_DCFG_DAD 0x000007F0U
8070 #define USB_OTG_DCFG_DAD_0 0x00000010U
8071 #define USB_OTG_DCFG_DAD_1 0x00000020U
8072 #define USB_OTG_DCFG_DAD_2 0x00000040U
8073 #define USB_OTG_DCFG_DAD_3 0x00000080U
8074 #define USB_OTG_DCFG_DAD_4 0x00000100U
8075 #define USB_OTG_DCFG_DAD_5 0x00000200U
8076 #define USB_OTG_DCFG_DAD_6 0x00000400U
8078 #define USB_OTG_DCFG_PFIVL 0x00001800U
8079 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
8080 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
8082 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
8083 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
8084 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
8086 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
8087 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
8088 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
8089 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
8091 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
8092 #define USB_OTG_GOTGINT_SEDET 0x00000004U
8093 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
8094 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
8095 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
8096 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
8097 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
8099 /******************** Bit definition forUSB_OTG_DCTL register ********************/
8100 #define USB_OTG_DCTL_RWUSIG 0x00000001U
8101 #define USB_OTG_DCTL_SDIS 0x00000002U
8102 #define USB_OTG_DCTL_GINSTS 0x00000004U
8103 #define USB_OTG_DCTL_GONSTS 0x00000008U
8105 #define USB_OTG_DCTL_TCTL 0x00000070U
8106 #define USB_OTG_DCTL_TCTL_0 0x00000010U
8107 #define USB_OTG_DCTL_TCTL_1 0x00000020U
8108 #define USB_OTG_DCTL_TCTL_2 0x00000040U
8109 #define USB_OTG_DCTL_SGINAK 0x00000080U
8110 #define USB_OTG_DCTL_CGINAK 0x00000100U
8111 #define USB_OTG_DCTL_SGONAK 0x00000200U
8112 #define USB_OTG_DCTL_CGONAK 0x00000400U
8113 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
8115 /******************** Bit definition forUSB_OTG_HFIR register ********************/
8116 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
8118 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
8119 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
8120 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
8122 /******************** Bit definition forUSB_OTG_DSTS register ********************/
8123 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
8125 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
8126 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
8127 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
8128 #define USB_OTG_DSTS_EERR 0x00000008U
8129 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
8131 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
8132 #define USB_OTG_GAHBCFG_GINT 0x00000001U
8134 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
8135 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
8136 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
8137 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
8138 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
8139 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
8140 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
8141 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
8143 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
8144 
8145 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
8146 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
8147 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
8148 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
8149 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
8150 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
8151 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
8153 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
8154 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
8155 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
8156 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
8157 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
8158 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
8159 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
8160 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
8161 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
8162 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
8163 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
8164 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
8165 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
8166 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
8167 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
8168 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
8169 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
8170 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
8172 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
8173 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
8174 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
8175 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
8176 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
8177 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
8179 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
8180 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
8181 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
8182 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
8183 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
8184 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
8185 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
8186 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
8188 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
8189 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
8190 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
8191 #define USB_OTG_DIEPMSK_TOM 0x00000008U
8192 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
8193 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
8194 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
8195 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
8196 #define USB_OTG_DIEPMSK_BIM 0x00000200U
8198 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
8199 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
8201 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
8202 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
8203 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
8204 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
8205 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
8206 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
8207 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
8208 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
8209 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
8211 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
8212 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
8213 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
8214 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
8215 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
8216 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
8217 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
8218 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
8219 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
8221 /******************** Bit definition forUSB_OTG_HAINT register ********************/
8222 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
8224 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
8225 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
8226 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
8227 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
8228 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
8229 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
8230 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
8231 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
8233 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
8234 #define USB_OTG_GINTSTS_CMOD 0x00000001U
8235 #define USB_OTG_GINTSTS_MMIS 0x00000002U
8236 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
8237 #define USB_OTG_GINTSTS_SOF 0x00000008U
8238 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
8239 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
8240 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
8241 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
8242 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
8243 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
8244 #define USB_OTG_GINTSTS_USBRST 0x00001000U
8245 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
8246 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
8247 #define USB_OTG_GINTSTS_EOPF 0x00008000U
8248 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
8249 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
8250 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
8251 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
8252 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
8253 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
8254 #define USB_OTG_GINTSTS_HCINT 0x02000000U
8255 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
8256 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
8257 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
8258 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
8259 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
8261 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
8262 #define USB_OTG_GINTMSK_MMISM 0x00000002U
8263 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
8264 #define USB_OTG_GINTMSK_SOFM 0x00000008U
8265 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
8266 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
8267 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
8268 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
8269 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
8270 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
8271 #define USB_OTG_GINTMSK_USBRST 0x00001000U
8272 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
8273 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
8274 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
8275 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
8276 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
8277 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
8278 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
8279 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
8280 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
8281 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
8282 #define USB_OTG_GINTMSK_HCIM 0x02000000U
8283 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
8284 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
8285 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
8286 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
8287 #define USB_OTG_GINTMSK_WUIM 0x80000000U
8289 /******************** Bit definition forUSB_OTG_DAINT register ********************/
8290 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
8291 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
8293 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
8294 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
8296 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8297 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
8298 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
8299 #define USB_OTG_GRXSTSP_DPID 0x00018000U
8300 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
8302 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
8303 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
8304 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
8306 /******************** Bit definition for OTG register ********************/
8307 
8308 #define USB_OTG_CHNUM 0x0000000FU
8309 #define USB_OTG_CHNUM_0 0x00000001U
8310 #define USB_OTG_CHNUM_1 0x00000002U
8311 #define USB_OTG_CHNUM_2 0x00000004U
8312 #define USB_OTG_CHNUM_3 0x00000008U
8313 #define USB_OTG_BCNT 0x00007FF0U
8315 #define USB_OTG_DPID 0x00018000U
8316 #define USB_OTG_DPID_0 0x00008000U
8317 #define USB_OTG_DPID_1 0x00010000U
8319 #define USB_OTG_PKTSTS 0x001E0000U
8320 #define USB_OTG_PKTSTS_0 0x00020000U
8321 #define USB_OTG_PKTSTS_1 0x00040000U
8322 #define USB_OTG_PKTSTS_2 0x00080000U
8323 #define USB_OTG_PKTSTS_3 0x00100000U
8325 #define USB_OTG_EPNUM 0x0000000FU
8326 #define USB_OTG_EPNUM_0 0x00000001U
8327 #define USB_OTG_EPNUM_1 0x00000002U
8328 #define USB_OTG_EPNUM_2 0x00000004U
8329 #define USB_OTG_EPNUM_3 0x00000008U
8331 #define USB_OTG_FRMNUM 0x01E00000U
8332 #define USB_OTG_FRMNUM_0 0x00200000U
8333 #define USB_OTG_FRMNUM_1 0x00400000U
8334 #define USB_OTG_FRMNUM_2 0x00800000U
8335 #define USB_OTG_FRMNUM_3 0x01000000U
8337 /******************** Bit definition for OTG register ********************/
8338 
8339 #define USB_OTG_CHNUM 0x0000000FU
8340 #define USB_OTG_CHNUM_0 0x00000001U
8341 #define USB_OTG_CHNUM_1 0x00000002U
8342 #define USB_OTG_CHNUM_2 0x00000004U
8343 #define USB_OTG_CHNUM_3 0x00000008U
8344 #define USB_OTG_BCNT 0x00007FF0U
8346 #define USB_OTG_DPID 0x00018000U
8347 #define USB_OTG_DPID_0 0x00008000U
8348 #define USB_OTG_DPID_1 0x00010000U
8350 #define USB_OTG_PKTSTS 0x001E0000U
8351 #define USB_OTG_PKTSTS_0 0x00020000U
8352 #define USB_OTG_PKTSTS_1 0x00040000U
8353 #define USB_OTG_PKTSTS_2 0x00080000U
8354 #define USB_OTG_PKTSTS_3 0x00100000U
8356 #define USB_OTG_EPNUM 0x0000000FU
8357 #define USB_OTG_EPNUM_0 0x00000001U
8358 #define USB_OTG_EPNUM_1 0x00000002U
8359 #define USB_OTG_EPNUM_2 0x00000004U
8360 #define USB_OTG_EPNUM_3 0x00000008U
8362 #define USB_OTG_FRMNUM 0x01E00000U
8363 #define USB_OTG_FRMNUM_0 0x00200000U
8364 #define USB_OTG_FRMNUM_1 0x00400000U
8365 #define USB_OTG_FRMNUM_2 0x00800000U
8366 #define USB_OTG_FRMNUM_3 0x01000000U
8368 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
8369 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
8371 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
8372 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
8374 /******************** Bit definition for OTG register ********************/
8375 #define USB_OTG_NPTXFSA 0x0000FFFFU
8376 #define USB_OTG_NPTXFD 0xFFFF0000U
8377 #define USB_OTG_TX0FSA 0x0000FFFFU
8378 #define USB_OTG_TX0FD 0xFFFF0000U
8380 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
8381 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
8383 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
8384 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
8386 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
8387 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
8388 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
8389 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
8390 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
8391 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
8392 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
8393 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
8394 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
8396 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
8397 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
8398 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
8399 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
8400 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
8401 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
8402 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
8403 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
8405 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
8406 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
8407 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
8409 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
8410 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
8411 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
8412 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
8413 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
8414 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
8415 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
8416 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
8417 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
8418 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
8419 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
8421 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
8422 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
8423 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
8424 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
8425 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
8426 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
8427 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
8428 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
8429 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
8430 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
8431 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
8433 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
8434 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
8436 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
8437 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
8438 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
8440 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
8441 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
8442 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
8443 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
8444 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
8445 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
8446 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
8448 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
8449 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
8450 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
8452 /******************** Bit definition forUSB_OTG_CID register ********************/
8453 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
8455 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
8456 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
8457 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
8458 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
8459 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
8460 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
8461 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
8462 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
8463 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
8464 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
8466 /******************** Bit definition forUSB_OTG_HPRT register ********************/
8467 #define USB_OTG_HPRT_PCSTS 0x00000001U
8468 #define USB_OTG_HPRT_PCDET 0x00000002U
8469 #define USB_OTG_HPRT_PENA 0x00000004U
8470 #define USB_OTG_HPRT_PENCHNG 0x00000008U
8471 #define USB_OTG_HPRT_POCA 0x00000010U
8472 #define USB_OTG_HPRT_POCCHNG 0x00000020U
8473 #define USB_OTG_HPRT_PRES 0x00000040U
8474 #define USB_OTG_HPRT_PSUSP 0x00000080U
8475 #define USB_OTG_HPRT_PRST 0x00000100U
8477 #define USB_OTG_HPRT_PLSTS 0x00000C00U
8478 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
8479 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
8480 #define USB_OTG_HPRT_PPWR 0x00001000U
8482 #define USB_OTG_HPRT_PTCTL 0x0001E000U
8483 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
8484 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
8485 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
8486 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
8488 #define USB_OTG_HPRT_PSPD 0x00060000U
8489 #define USB_OTG_HPRT_PSPD_0 0x00020000U
8490 #define USB_OTG_HPRT_PSPD_1 0x00040000U
8492 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
8493 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
8494 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
8495 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
8496 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
8497 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
8498 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
8499 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
8500 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
8501 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
8502 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
8503 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
8505 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
8506 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
8507 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
8509 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
8510 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
8511 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
8512 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
8513 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
8515 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
8516 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
8517 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
8518 #define USB_OTG_DIEPCTL_STALL 0x00200000U
8520 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
8521 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
8522 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
8523 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
8524 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
8525 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
8526 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
8527 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
8528 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
8529 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
8530 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
8532 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
8533 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
8535 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
8536 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
8537 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
8538 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
8539 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
8540 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
8541 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
8543 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
8544 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
8545 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
8547 #define USB_OTG_HCCHAR_MC 0x00300000U
8548 #define USB_OTG_HCCHAR_MC_0 0x00100000U
8549 #define USB_OTG_HCCHAR_MC_1 0x00200000U
8551 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
8552 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
8553 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
8554 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
8555 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
8556 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
8557 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
8558 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
8559 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
8560 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
8561 #define USB_OTG_HCCHAR_CHENA 0x80000000U
8563 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
8564 
8565 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
8566 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
8567 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
8568 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
8569 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
8570 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
8571 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
8572 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
8574 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
8575 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
8576 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
8577 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
8578 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
8579 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
8580 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
8581 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
8583 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
8584 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
8585 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
8586 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
8587 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
8589 /******************** Bit definition forUSB_OTG_HCINT register ********************/
8590 #define USB_OTG_HCINT_XFRC 0x00000001U
8591 #define USB_OTG_HCINT_CHH 0x00000002U
8592 #define USB_OTG_HCINT_AHBERR 0x00000004U
8593 #define USB_OTG_HCINT_STALL 0x00000008U
8594 #define USB_OTG_HCINT_NAK 0x00000010U
8595 #define USB_OTG_HCINT_ACK 0x00000020U
8596 #define USB_OTG_HCINT_NYET 0x00000040U
8597 #define USB_OTG_HCINT_TXERR 0x00000080U
8598 #define USB_OTG_HCINT_BBERR 0x00000100U
8599 #define USB_OTG_HCINT_FRMOR 0x00000200U
8600 #define USB_OTG_HCINT_DTERR 0x00000400U
8602 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
8603 #define USB_OTG_DIEPINT_XFRC 0x00000001U
8604 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
8605 #define USB_OTG_DIEPINT_TOC 0x00000008U
8606 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
8607 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
8608 #define USB_OTG_DIEPINT_TXFE 0x00000080U
8609 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
8610 #define USB_OTG_DIEPINT_BNA 0x00000200U
8611 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
8612 #define USB_OTG_DIEPINT_BERR 0x00001000U
8613 #define USB_OTG_DIEPINT_NAK 0x00002000U
8615 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
8616 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
8617 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
8618 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
8619 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
8620 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
8621 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
8622 #define USB_OTG_HCINTMSK_NYET 0x00000040U
8623 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
8624 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
8625 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
8626 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
8628 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8629 
8630 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
8631 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
8632 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
8633 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
8634 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
8635 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
8636 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
8637 #define USB_OTG_HCTSIZ_DPID 0x60000000U
8638 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
8639 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
8641 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
8642 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
8644 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
8645 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
8647 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
8648 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
8650 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
8651 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
8652 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
8654 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
8655 
8656 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
8657 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
8658 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
8659 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
8660 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
8661 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
8662 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
8663 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
8664 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
8665 #define USB_OTG_DOEPCTL_STALL 0x00200000U
8666 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
8667 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
8668 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
8669 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
8671 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
8672 #define USB_OTG_DOEPINT_XFRC 0x00000001U
8673 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
8674 #define USB_OTG_DOEPINT_STUP 0x00000008U
8675 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
8676 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
8677 #define USB_OTG_DOEPINT_NYET 0x00004000U
8679 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
8680 
8681 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
8682 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
8684 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
8685 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
8686 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
8688 /******************** Bit definition for PCGCCTL register ********************/
8689 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
8690 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
8691 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
8706 /******************************* ADC Instances ********************************/
8707 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
8708  ((INSTANCE) == ADC2) || \
8709  ((INSTANCE) == ADC3))
8710 
8711 /******************************* CAN Instances ********************************/
8712 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
8713  ((INSTANCE) == CAN2))
8714 
8715 /******************************* CRC Instances ********************************/
8716 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8717 
8718 /******************************* DAC Instances ********************************/
8719 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
8720 
8721 /******************************* DCMI Instances *******************************/
8722 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
8723 
8724 /******************************* DMA2D Instances *******************************/
8725 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
8726 
8727 /******************************** DMA Instances *******************************/
8728 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
8729  ((INSTANCE) == DMA1_Stream1) || \
8730  ((INSTANCE) == DMA1_Stream2) || \
8731  ((INSTANCE) == DMA1_Stream3) || \
8732  ((INSTANCE) == DMA1_Stream4) || \
8733  ((INSTANCE) == DMA1_Stream5) || \
8734  ((INSTANCE) == DMA1_Stream6) || \
8735  ((INSTANCE) == DMA1_Stream7) || \
8736  ((INSTANCE) == DMA2_Stream0) || \
8737  ((INSTANCE) == DMA2_Stream1) || \
8738  ((INSTANCE) == DMA2_Stream2) || \
8739  ((INSTANCE) == DMA2_Stream3) || \
8740  ((INSTANCE) == DMA2_Stream4) || \
8741  ((INSTANCE) == DMA2_Stream5) || \
8742  ((INSTANCE) == DMA2_Stream6) || \
8743  ((INSTANCE) == DMA2_Stream7))
8744 
8745 /******************************* GPIO Instances *******************************/
8746 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8747  ((INSTANCE) == GPIOB) || \
8748  ((INSTANCE) == GPIOC) || \
8749  ((INSTANCE) == GPIOD) || \
8750  ((INSTANCE) == GPIOE) || \
8751  ((INSTANCE) == GPIOF) || \
8752  ((INSTANCE) == GPIOG) || \
8753  ((INSTANCE) == GPIOH) || \
8754  ((INSTANCE) == GPIOI) || \
8755  ((INSTANCE) == GPIOJ) || \
8756  ((INSTANCE) == GPIOK))
8757 
8758 /******************************** I2C Instances *******************************/
8759 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8760  ((INSTANCE) == I2C2) || \
8761  ((INSTANCE) == I2C3))
8762 
8763 /******************************** I2S Instances *******************************/
8764 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
8765  ((INSTANCE) == SPI3))
8766 
8767 /*************************** I2S Extended Instances ***************************/
8768 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
8769  ((INSTANCE) == SPI3) || \
8770  ((INSTANCE) == I2S2ext) || \
8771  ((INSTANCE) == I2S3ext))
8772 
8773 /****************************** LTDC Instances ********************************/
8774 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
8775 
8776 /******************************* RNG Instances ********************************/
8777 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
8778 
8779 /****************************** RTC Instances *********************************/
8780 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
8781 
8782 /******************************* SAI Instances ********************************/
8783 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
8784  ((PERIPH) == SAI1_Block_B))
8785 /* Legacy define */
8786 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
8787 
8788 /******************************** SPI Instances *******************************/
8789 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8790  ((INSTANCE) == SPI2) || \
8791  ((INSTANCE) == SPI3) || \
8792  ((INSTANCE) == SPI4) || \
8793  ((INSTANCE) == SPI5) || \
8794  ((INSTANCE) == SPI6))
8795 
8796 /*************************** SPI Extended Instances ***************************/
8797 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
8798  ((INSTANCE) == SPI2) || \
8799  ((INSTANCE) == SPI3) || \
8800  ((INSTANCE) == SPI4) || \
8801  ((INSTANCE) == SPI5) || \
8802  ((INSTANCE) == SPI6) || \
8803  ((INSTANCE) == I2S2ext) || \
8804  ((INSTANCE) == I2S3ext))
8805 
8806 /****************** TIM Instances : All supported instances *******************/
8807 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8808  ((INSTANCE) == TIM2) || \
8809  ((INSTANCE) == TIM3) || \
8810  ((INSTANCE) == TIM4) || \
8811  ((INSTANCE) == TIM5) || \
8812  ((INSTANCE) == TIM6) || \
8813  ((INSTANCE) == TIM7) || \
8814  ((INSTANCE) == TIM8) || \
8815  ((INSTANCE) == TIM9) || \
8816  ((INSTANCE) == TIM10) || \
8817  ((INSTANCE) == TIM11) || \
8818  ((INSTANCE) == TIM12) || \
8819  ((INSTANCE) == TIM13) || \
8820  ((INSTANCE) == TIM14))
8821 
8822 /************* TIM Instances : at least 1 capture/compare channel *************/
8823 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8824  ((INSTANCE) == TIM2) || \
8825  ((INSTANCE) == TIM3) || \
8826  ((INSTANCE) == TIM4) || \
8827  ((INSTANCE) == TIM5) || \
8828  ((INSTANCE) == TIM8) || \
8829  ((INSTANCE) == TIM9) || \
8830  ((INSTANCE) == TIM10) || \
8831  ((INSTANCE) == TIM11) || \
8832  ((INSTANCE) == TIM12) || \
8833  ((INSTANCE) == TIM13) || \
8834  ((INSTANCE) == TIM14))
8835 
8836 /************ TIM Instances : at least 2 capture/compare channels *************/
8837 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8838  ((INSTANCE) == TIM2) || \
8839  ((INSTANCE) == TIM3) || \
8840  ((INSTANCE) == TIM4) || \
8841  ((INSTANCE) == TIM5) || \
8842  ((INSTANCE) == TIM8) || \
8843  ((INSTANCE) == TIM9) || \
8844  ((INSTANCE) == TIM12))
8845 
8846 /************ TIM Instances : at least 3 capture/compare channels *************/
8847 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8848  ((INSTANCE) == TIM2) || \
8849  ((INSTANCE) == TIM3) || \
8850  ((INSTANCE) == TIM4) || \
8851  ((INSTANCE) == TIM5) || \
8852  ((INSTANCE) == TIM8))
8853 
8854 /************ TIM Instances : at least 4 capture/compare channels *************/
8855 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8856  ((INSTANCE) == TIM2) || \
8857  ((INSTANCE) == TIM3) || \
8858  ((INSTANCE) == TIM4) || \
8859  ((INSTANCE) == TIM5) || \
8860  ((INSTANCE) == TIM8))
8861 
8862 /******************** TIM Instances : Advanced-control timers *****************/
8863 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8864  ((INSTANCE) == TIM8))
8865 
8866 /******************* TIM Instances : Timer input XOR function *****************/
8867 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8868  ((INSTANCE) == TIM2) || \
8869  ((INSTANCE) == TIM3) || \
8870  ((INSTANCE) == TIM4) || \
8871  ((INSTANCE) == TIM5) || \
8872  ((INSTANCE) == TIM8))
8873 
8874 /****************** TIM Instances : DMA requests generation (UDE) *************/
8875 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8876  ((INSTANCE) == TIM2) || \
8877  ((INSTANCE) == TIM3) || \
8878  ((INSTANCE) == TIM4) || \
8879  ((INSTANCE) == TIM5) || \
8880  ((INSTANCE) == TIM6) || \
8881  ((INSTANCE) == TIM7) || \
8882  ((INSTANCE) == TIM8))
8883 
8884 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8885 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8886  ((INSTANCE) == TIM2) || \
8887  ((INSTANCE) == TIM3) || \
8888  ((INSTANCE) == TIM4) || \
8889  ((INSTANCE) == TIM5) || \
8890  ((INSTANCE) == TIM8))
8891 
8892 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8893 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8894  ((INSTANCE) == TIM2) || \
8895  ((INSTANCE) == TIM3) || \
8896  ((INSTANCE) == TIM4) || \
8897  ((INSTANCE) == TIM5) || \
8898  ((INSTANCE) == TIM8))
8899 
8900 /******************** TIM Instances : DMA burst feature ***********************/
8901 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8902  ((INSTANCE) == TIM2) || \
8903  ((INSTANCE) == TIM3) || \
8904  ((INSTANCE) == TIM4) || \
8905  ((INSTANCE) == TIM5) || \
8906  ((INSTANCE) == TIM8))
8907 
8908 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8909 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8910  ((INSTANCE) == TIM2) || \
8911  ((INSTANCE) == TIM3) || \
8912  ((INSTANCE) == TIM4) || \
8913  ((INSTANCE) == TIM5) || \
8914  ((INSTANCE) == TIM6) || \
8915  ((INSTANCE) == TIM7) || \
8916  ((INSTANCE) == TIM8) || \
8917  ((INSTANCE) == TIM9) || \
8918  ((INSTANCE) == TIM12))
8919 
8920 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8921 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8922  ((INSTANCE) == TIM2) || \
8923  ((INSTANCE) == TIM3) || \
8924  ((INSTANCE) == TIM4) || \
8925  ((INSTANCE) == TIM5) || \
8926  ((INSTANCE) == TIM8) || \
8927  ((INSTANCE) == TIM9) || \
8928  ((INSTANCE) == TIM12))
8929 
8930 /********************** TIM Instances : 32 bit Counter ************************/
8931 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
8932  ((INSTANCE) == TIM5))
8933 
8934 /***************** TIM Instances : external trigger input availabe ************/
8935 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8936  ((INSTANCE) == TIM2) || \
8937  ((INSTANCE) == TIM3) || \
8938  ((INSTANCE) == TIM4) || \
8939  ((INSTANCE) == TIM5) || \
8940  ((INSTANCE) == TIM8))
8941 
8942 /****************** TIM Instances : remapping capability **********************/
8943 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8944  ((INSTANCE) == TIM5) || \
8945  ((INSTANCE) == TIM11))
8946 
8947 /******************* TIM Instances : output(s) available **********************/
8948 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8949  ((((INSTANCE) == TIM1) && \
8950  (((CHANNEL) == TIM_CHANNEL_1) || \
8951  ((CHANNEL) == TIM_CHANNEL_2) || \
8952  ((CHANNEL) == TIM_CHANNEL_3) || \
8953  ((CHANNEL) == TIM_CHANNEL_4))) \
8954  || \
8955  (((INSTANCE) == TIM2) && \
8956  (((CHANNEL) == TIM_CHANNEL_1) || \
8957  ((CHANNEL) == TIM_CHANNEL_2) || \
8958  ((CHANNEL) == TIM_CHANNEL_3) || \
8959  ((CHANNEL) == TIM_CHANNEL_4))) \
8960  || \
8961  (((INSTANCE) == TIM3) && \
8962  (((CHANNEL) == TIM_CHANNEL_1) || \
8963  ((CHANNEL) == TIM_CHANNEL_2) || \
8964  ((CHANNEL) == TIM_CHANNEL_3) || \
8965  ((CHANNEL) == TIM_CHANNEL_4))) \
8966  || \
8967  (((INSTANCE) == TIM4) && \
8968  (((CHANNEL) == TIM_CHANNEL_1) || \
8969  ((CHANNEL) == TIM_CHANNEL_2) || \
8970  ((CHANNEL) == TIM_CHANNEL_3) || \
8971  ((CHANNEL) == TIM_CHANNEL_4))) \
8972  || \
8973  (((INSTANCE) == TIM5) && \
8974  (((CHANNEL) == TIM_CHANNEL_1) || \
8975  ((CHANNEL) == TIM_CHANNEL_2) || \
8976  ((CHANNEL) == TIM_CHANNEL_3) || \
8977  ((CHANNEL) == TIM_CHANNEL_4))) \
8978  || \
8979  (((INSTANCE) == TIM8) && \
8980  (((CHANNEL) == TIM_CHANNEL_1) || \
8981  ((CHANNEL) == TIM_CHANNEL_2) || \
8982  ((CHANNEL) == TIM_CHANNEL_3) || \
8983  ((CHANNEL) == TIM_CHANNEL_4))) \
8984  || \
8985  (((INSTANCE) == TIM9) && \
8986  (((CHANNEL) == TIM_CHANNEL_1) || \
8987  ((CHANNEL) == TIM_CHANNEL_2))) \
8988  || \
8989  (((INSTANCE) == TIM10) && \
8990  (((CHANNEL) == TIM_CHANNEL_1))) \
8991  || \
8992  (((INSTANCE) == TIM11) && \
8993  (((CHANNEL) == TIM_CHANNEL_1))) \
8994  || \
8995  (((INSTANCE) == TIM12) && \
8996  (((CHANNEL) == TIM_CHANNEL_1) || \
8997  ((CHANNEL) == TIM_CHANNEL_2))) \
8998  || \
8999  (((INSTANCE) == TIM13) && \
9000  (((CHANNEL) == TIM_CHANNEL_1))) \
9001  || \
9002  (((INSTANCE) == TIM14) && \
9003  (((CHANNEL) == TIM_CHANNEL_1))))
9004 
9005 /************ TIM Instances : complementary output(s) available ***************/
9006 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
9007  ((((INSTANCE) == TIM1) && \
9008  (((CHANNEL) == TIM_CHANNEL_1) || \
9009  ((CHANNEL) == TIM_CHANNEL_2) || \
9010  ((CHANNEL) == TIM_CHANNEL_3))) \
9011  || \
9012  (((INSTANCE) == TIM8) && \
9013  (((CHANNEL) == TIM_CHANNEL_1) || \
9014  ((CHANNEL) == TIM_CHANNEL_2) || \
9015  ((CHANNEL) == TIM_CHANNEL_3))))
9016 
9017 /******************** USART Instances : Synchronous mode **********************/
9018 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9019  ((INSTANCE) == USART2) || \
9020  ((INSTANCE) == USART3) || \
9021  ((INSTANCE) == USART6))
9022 
9023 /******************** UART Instances : Asynchronous mode **********************/
9024 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9025  ((INSTANCE) == USART2) || \
9026  ((INSTANCE) == USART3) || \
9027  ((INSTANCE) == UART4) || \
9028  ((INSTANCE) == UART5) || \
9029  ((INSTANCE) == USART6) || \
9030  ((INSTANCE) == UART7) || \
9031  ((INSTANCE) == UART8))
9032 
9033 /****************** UART Instances : Hardware Flow control ********************/
9034 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9035  ((INSTANCE) == USART2) || \
9036  ((INSTANCE) == USART3) || \
9037  ((INSTANCE) == USART6))
9038 
9039 /********************* UART Instances : Smard card mode ***********************/
9040 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9041  ((INSTANCE) == USART2) || \
9042  ((INSTANCE) == USART3) || \
9043  ((INSTANCE) == USART6))
9044 
9045 /*********************** UART Instances : IRDA mode ***************************/
9046 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9047  ((INSTANCE) == USART2) || \
9048  ((INSTANCE) == USART3) || \
9049  ((INSTANCE) == UART4) || \
9050  ((INSTANCE) == UART5) || \
9051  ((INSTANCE) == USART6) || \
9052  ((INSTANCE) == UART7) || \
9053  ((INSTANCE) == UART8))
9054 
9055 /*********************** PCD Instances ****************************************/
9056 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
9057  ((INSTANCE) == USB_OTG_HS))
9058 
9059 /*********************** HCD Instances ****************************************/
9060 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
9061  ((INSTANCE) == USB_OTG_HS))
9062 
9063 
9064 /****************************** IWDG Instances ********************************/
9065 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
9066 
9067 /****************************** WWDG Instances ********************************/
9068 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
9069 
9070 /****************************** SDIO Instances ********************************/
9071 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
9072 
9073 /****************************** USB Exported Constants ************************/
9074 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
9075 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
9076 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
9077 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
9078 
9079 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
9080 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
9081 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
9082 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
9083 
9084 /******************************************************************************/
9085 /* For a painless codes migration between the STM32F4xx device product */
9086 /* lines, the aliases defined below are put in place to overcome the */
9087 /* differences in the interrupt handlers and IRQn definitions. */
9088 /* No need to update developed interrupt code when moving across */
9089 /* product lines within the same STM32F4 Family */
9090 /******************************************************************************/
9091 
9092 /* Aliases for __IRQn */
9093 #define FSMC_IRQn FMC_IRQn
9094 
9095 /* Aliases for __IRQHandler */
9096 #define FSMC_IRQHandler FMC_IRQHandler
9097 
9110 #ifdef __cplusplus
9111 }
9112 #endif /* __cplusplus */
9113 
9114 #endif /* __STM32F429xx_H */
9115 
9116 
9117 
9118 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f429xx.h:653
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
LTDC_TypeDef::CPSR
__IO uint32_t CPSR
Definition: stm32f429xx.h:670
SAI1_IRQn
Definition: stm32f429xx.h:182
TAMP_STAMP_IRQn
Definition: stm32f429xx.h:98
LTDC_TypeDef::SSCR
__IO uint32_t SSCR
Definition: stm32f429xx.h:656
TIM2_IRQn
Definition: stm32f429xx.h:124
UART4_IRQn
Definition: stm32f429xx.h:148
LTDC_Layer_TypeDef::CFBLR
__IO uint32_t CFBLR
Definition: stm32f429xx.h:690
UART5_IRQn
Definition: stm32f429xx.h:149
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f429xx.h:122
EXTI2_IRQn
Definition: stm32f429xx.h:104
EXTI4_IRQn
Definition: stm32f429xx.h:106
USART1_IRQn
Definition: stm32f429xx.h:133
LTDC_Layer_TypeDef::WHPCR
__IO uint32_t WHPCR
Definition: stm32f429xx.h:681
LTDC_Layer_TypeDef::DCCR
__IO uint32_t DCCR
Definition: stm32f429xx.h:686
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
LTDC_Layer_TypeDef::CFBAR
__IO uint32_t CFBAR
Definition: stm32f429xx.h:689
ETH_WKUP_IRQn
Definition: stm32f429xx.h:158
DMA2D_IRQn
Definition: stm32f429xx.h:185
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f429xx.h:141
TIM4_IRQn
Definition: stm32f429xx.h:126
RTC_Alarm_IRQn
Definition: stm32f429xx.h:137
CAN2_SCE_IRQn
Definition: stm32f429xx.h:162
PendSV_IRQn
Definition: stm32f429xx.h:93
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f429xx.h:99
CAN1_RX1_IRQn
Definition: stm32f429xx.h:117
TIM6_DAC_IRQn
Definition: stm32f429xx.h:150
LTDC_IRQn
Definition: stm32f429xx.h:183
CAN1_TX_IRQn
Definition: stm32f429xx.h:115
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f429xx.h:131
LTDC_Layer_TypeDef::BFCR
__IO uint32_t BFCR
Definition: stm32f429xx.h:687
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
LTDC_Layer_TypeDef::CR
__IO uint32_t CR
Definition: stm32f429xx.h:680
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f427xx.h:534
OTG_FS_WKUP_IRQn
Definition: stm32f429xx.h:138
DMA_TypeDef
Definition: stm32f401xc.h:243
ETH_IRQn
Definition: stm32f429xx.h:157
LTDC_TypeDef::LIPCR
__IO uint32_t LIPCR
Definition: stm32f429xx.h:669
DMA1_Stream2_IRQn
Definition: stm32f429xx.h:109
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f429xx.h:132
FMC_Bank2_3_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32f427xx.h:543
LTDC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f429xx.h:667
LTDC_TypeDef::BPCR
__IO uint32_t BPCR
Definition: stm32f429xx.h:657
__I
#define __I
Definition: core_cm0.h:210
LTDC_TypeDef::SRCR
__IO uint32_t SRCR
Definition: stm32f429xx.h:662
DMA2_Stream5_IRQn
Definition: stm32f429xx.h:164
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f429xx.h:678
ADC_IRQn
Definition: stm32f429xx.h:114
CAN1_RX0_IRQn
Definition: stm32f429xx.h:116
RCC_IRQn
Definition: stm32f429xx.h:101
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f429xx.h:92
LTDC_Layer_TypeDef::CKCR
__IO uint32_t CKCR
Definition: stm32f429xx.h:683
DMA2_Stream3_IRQn
Definition: stm32f429xx.h:155
NonMaskableInt_IRQn
Definition: stm32f429xx.h:87
UART8_IRQn
Definition: stm32f429xx.h:178
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f429xx.h:84
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f429xx.h:140
DMA1_Stream1_IRQn
Definition: stm32f429xx.h:108
DMA2_Stream7_IRQn
Definition: stm32f429xx.h:166
DMA2_Stream6_IRQn
Definition: stm32f429xx.h:165
BusFault_IRQn
Definition: stm32f429xx.h:89
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
LTDC_TypeDef::IER
__IO uint32_t IER
Definition: stm32f429xx.h:666
I2C3_ER_IRQn
Definition: stm32f429xx.h:169
CAN2_RX0_IRQn
Definition: stm32f429xx.h:160
USART6_IRQn
Definition: stm32f429xx.h:167
PVD_IRQn
Definition: stm32f429xx.h:97
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f427xx.h:391
FMC_Bank4_TypeDef
Flexible Memory Controller Bank4.
Definition: stm32f427xx.h:565
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
LTDC_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32f429xx.h:660
LTDC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f429xx.h:668
DMA1_Stream4_IRQn
Definition: stm32f429xx.h:111
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f427xx.h:750
DMA1_Stream0_IRQn
Definition: stm32f429xx.h:107
OTG_HS_IRQn
Definition: stm32f429xx.h:173
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f429xx.h:179
TIM8_CC_IRQn
Definition: stm32f429xx.h:142
DMA1_Stream3_IRQn
Definition: stm32f429xx.h:110
FPU_IRQn
Definition: stm32f429xx.h:176
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:386
OTG_FS_IRQn
Definition: stm32f429xx.h:163
DMA2_Stream2_IRQn
Definition: stm32f429xx.h:154
OTG_HS_EP1_OUT_IRQn
Definition: stm32f429xx.h:170
OTG_HS_EP1_IN_IRQn
Definition: stm32f429xx.h:171
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f429xx.h:145
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f429xx.h:168
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f429xx.h:134
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
LTDC_ER_IRQn
Definition: stm32f429xx.h:184
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f429xx.h:151
I2C2_EV_IRQn
Definition: stm32f429xx.h:129
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f429xx.h:125
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f429xx.h:103
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f429xx.h:91
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
LTDC_Layer_TypeDef::WVPCR
__IO uint32_t WVPCR
Definition: stm32f429xx.h:682
TIM1_CC_IRQn
Definition: stm32f429xx.h:123
TIM8_BRK_TIM12_IRQn
Definition: stm32f429xx.h:139
LTDC_Layer_TypeDef::CACR
__IO uint32_t CACR
Definition: stm32f429xx.h:685
HASH_RNG_IRQn
Definition: stm32f429xx.h:175
FLASH_IRQn
Definition: stm32f429xx.h:100
DMA1_Stream5_IRQn
Definition: stm32f429xx.h:112
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f429xx.h:94
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f427xx.h:525
SPI6_IRQn
Definition: stm32f429xx.h:181
TIM1_UP_TIM10_IRQn
Definition: stm32f429xx.h:121
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f429xx.h:130
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:344
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f427xx.h:578
UsageFault_IRQn
Definition: stm32f429xx.h:90
FMC_IRQn
Definition: stm32f429xx.h:144
SPI3_IRQn
Definition: stm32f429xx.h:147
DMA2_Stream1_IRQn
Definition: stm32f429xx.h:153
EXTI9_5_IRQn
Definition: stm32f429xx.h:119
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f429xx.h:127
LTDC_TypeDef::BCCR
__IO uint32_t BCCR
Definition: stm32f429xx.h:664
DMA1_Stream6_IRQn
Definition: stm32f429xx.h:113
OTG_HS_WKUP_IRQn
Definition: stm32f429xx.h:172
I2C1_ER_IRQn
Definition: stm32f429xx.h:128
LTDC_Layer_TypeDef::PFCR
__IO uint32_t PFCR
Definition: stm32f429xx.h:684
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
LTDC_TypeDef::AWCR
__IO uint32_t AWCR
Definition: stm32f429xx.h:658
LTDC_Layer_TypeDef::CLUTWR
__IO uint32_t CLUTWR
Definition: stm32f429xx.h:693
UART7_IRQn
Definition: stm32f429xx.h:177
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
SAI_Block_TypeDef
Definition: stm32f427xx.h:755
CAN2_RX1_IRQn
Definition: stm32f429xx.h:161
DMA2_Stream4_IRQn
Definition: stm32f429xx.h:156
WWDG_IRQn
Definition: stm32f429xx.h:96
DMA1_Stream7_IRQn
Definition: stm32f429xx.h:143
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
SPI5_IRQn
Definition: stm32f429xx.h:180
LTDC_Layer_TypeDef::CFBLNR
__IO uint32_t CFBLNR
Definition: stm32f429xx.h:691
EXTI15_10_IRQn
Definition: stm32f429xx.h:136
CAN1_SCE_IRQn
Definition: stm32f429xx.h:118
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f429xx.h:102
DMA2_Stream0_IRQn
Definition: stm32f429xx.h:152
TIM1_BRK_TIM9_IRQn
Definition: stm32f429xx.h:120
CAN2_TX_IRQn
Definition: stm32f429xx.h:159
TIM5_IRQn
Definition: stm32f429xx.h:146
LTDC_TypeDef::TWCR
__IO uint32_t TWCR
Definition: stm32f429xx.h:659
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f429xx.h:105
USART3_IRQn
Definition: stm32f429xx.h:135
DCMI_IRQn
Definition: stm32f429xx.h:174
MemoryManagement_IRQn
Definition: stm32f429xx.h:88
LTDC_TypeDef::CDSR
__IO uint32_t CDSR
Definition: stm32f429xx.h:671