STM CMSIS
stm32f437xx.h
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1 
52 #ifndef __STM32F437xx_H
53 #define __STM32F437xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
66 #define __CM4_REV 0x0001U
67 #define __MPU_PRESENT 1U
68 #define __NVIC_PRIO_BITS 4U
69 #define __Vendor_SysTickConfig 0U
70 #define __FPU_PRESENT 1U
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87  NonMaskableInt_IRQn = -14,
88  MemoryManagement_IRQn = -12,
89  BusFault_IRQn = -11,
90  UsageFault_IRQn = -10,
91  SVCall_IRQn = -5,
92  DebugMonitor_IRQn = -4,
93  PendSV_IRQn = -2,
94  SysTick_IRQn = -1,
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96  WWDG_IRQn = 0,
97  PVD_IRQn = 1,
98  TAMP_STAMP_IRQn = 2,
99  RTC_WKUP_IRQn = 3,
100  FLASH_IRQn = 4,
101  RCC_IRQn = 5,
102  EXTI0_IRQn = 6,
103  EXTI1_IRQn = 7,
104  EXTI2_IRQn = 8,
105  EXTI3_IRQn = 9,
106  EXTI4_IRQn = 10,
107  DMA1_Stream0_IRQn = 11,
108  DMA1_Stream1_IRQn = 12,
109  DMA1_Stream2_IRQn = 13,
110  DMA1_Stream3_IRQn = 14,
111  DMA1_Stream4_IRQn = 15,
112  DMA1_Stream5_IRQn = 16,
113  DMA1_Stream6_IRQn = 17,
114  ADC_IRQn = 18,
115  CAN1_TX_IRQn = 19,
116  CAN1_RX0_IRQn = 20,
117  CAN1_RX1_IRQn = 21,
118  CAN1_SCE_IRQn = 22,
119  EXTI9_5_IRQn = 23,
120  TIM1_BRK_TIM9_IRQn = 24,
121  TIM1_UP_TIM10_IRQn = 25,
122  TIM1_TRG_COM_TIM11_IRQn = 26,
123  TIM1_CC_IRQn = 27,
124  TIM2_IRQn = 28,
125  TIM3_IRQn = 29,
126  TIM4_IRQn = 30,
127  I2C1_EV_IRQn = 31,
128  I2C1_ER_IRQn = 32,
129  I2C2_EV_IRQn = 33,
130  I2C2_ER_IRQn = 34,
131  SPI1_IRQn = 35,
132  SPI2_IRQn = 36,
133  USART1_IRQn = 37,
134  USART2_IRQn = 38,
135  USART3_IRQn = 39,
136  EXTI15_10_IRQn = 40,
137  RTC_Alarm_IRQn = 41,
138  OTG_FS_WKUP_IRQn = 42,
139  TIM8_BRK_TIM12_IRQn = 43,
140  TIM8_UP_TIM13_IRQn = 44,
141  TIM8_TRG_COM_TIM14_IRQn = 45,
142  TIM8_CC_IRQn = 46,
143  DMA1_Stream7_IRQn = 47,
144  FMC_IRQn = 48,
145  SDIO_IRQn = 49,
146  TIM5_IRQn = 50,
147  SPI3_IRQn = 51,
148  UART4_IRQn = 52,
149  UART5_IRQn = 53,
150  TIM6_DAC_IRQn = 54,
151  TIM7_IRQn = 55,
152  DMA2_Stream0_IRQn = 56,
153  DMA2_Stream1_IRQn = 57,
154  DMA2_Stream2_IRQn = 58,
155  DMA2_Stream3_IRQn = 59,
156  DMA2_Stream4_IRQn = 60,
157  ETH_IRQn = 61,
158  ETH_WKUP_IRQn = 62,
159  CAN2_TX_IRQn = 63,
160  CAN2_RX0_IRQn = 64,
161  CAN2_RX1_IRQn = 65,
162  CAN2_SCE_IRQn = 66,
163  OTG_FS_IRQn = 67,
164  DMA2_Stream5_IRQn = 68,
165  DMA2_Stream6_IRQn = 69,
166  DMA2_Stream7_IRQn = 70,
167  USART6_IRQn = 71,
168  I2C3_EV_IRQn = 72,
169  I2C3_ER_IRQn = 73,
170  OTG_HS_EP1_OUT_IRQn = 74,
171  OTG_HS_EP1_IN_IRQn = 75,
172  OTG_HS_WKUP_IRQn = 76,
173  OTG_HS_IRQn = 77,
174  DCMI_IRQn = 78,
175  CRYP_IRQn = 79,
176  HASH_RNG_IRQn = 80,
177  FPU_IRQn = 81,
178  UART7_IRQn = 82,
179  UART8_IRQn = 83,
180  SPI4_IRQn = 84,
181  SPI5_IRQn = 85,
182  SPI6_IRQn = 86,
183  SAI1_IRQn = 87,
184  DMA2D_IRQn = 90
185 } IRQn_Type;
186 
191 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
192 #include "system_stm32f4xx.h"
193 #include <stdint.h>
194 
203 typedef struct
204 {
205  __IO uint32_t SR;
206  __IO uint32_t CR1;
207  __IO uint32_t CR2;
208  __IO uint32_t SMPR1;
209  __IO uint32_t SMPR2;
210  __IO uint32_t JOFR1;
211  __IO uint32_t JOFR2;
212  __IO uint32_t JOFR3;
213  __IO uint32_t JOFR4;
214  __IO uint32_t HTR;
215  __IO uint32_t LTR;
216  __IO uint32_t SQR1;
217  __IO uint32_t SQR2;
218  __IO uint32_t SQR3;
219  __IO uint32_t JSQR;
220  __IO uint32_t JDR1;
221  __IO uint32_t JDR2;
222  __IO uint32_t JDR3;
223  __IO uint32_t JDR4;
224  __IO uint32_t DR;
225 } ADC_TypeDef;
226 
227 typedef struct
228 {
229  __IO uint32_t CSR;
230  __IO uint32_t CCR;
231  __IO uint32_t CDR;
233 } ADC_Common_TypeDef;
234 
235 
240 typedef struct
241 {
242  __IO uint32_t TIR;
243  __IO uint32_t TDTR;
244  __IO uint32_t TDLR;
245  __IO uint32_t TDHR;
246 } CAN_TxMailBox_TypeDef;
247 
252 typedef struct
253 {
254  __IO uint32_t RIR;
255  __IO uint32_t RDTR;
256  __IO uint32_t RDLR;
257  __IO uint32_t RDHR;
258 } CAN_FIFOMailBox_TypeDef;
259 
264 typedef struct
265 {
266  __IO uint32_t FR1;
267  __IO uint32_t FR2;
268 } CAN_FilterRegister_TypeDef;
269 
274 typedef struct
275 {
276  __IO uint32_t MCR;
277  __IO uint32_t MSR;
278  __IO uint32_t TSR;
279  __IO uint32_t RF0R;
280  __IO uint32_t RF1R;
281  __IO uint32_t IER;
282  __IO uint32_t ESR;
283  __IO uint32_t BTR;
284  uint32_t RESERVED0[88];
285  CAN_TxMailBox_TypeDef sTxMailBox[3];
286  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
287  uint32_t RESERVED1[12];
288  __IO uint32_t FMR;
289  __IO uint32_t FM1R;
290  uint32_t RESERVED2;
291  __IO uint32_t FS1R;
292  uint32_t RESERVED3;
293  __IO uint32_t FFA1R;
294  uint32_t RESERVED4;
295  __IO uint32_t FA1R;
296  uint32_t RESERVED5[8];
297  CAN_FilterRegister_TypeDef sFilterRegister[28];
298 } CAN_TypeDef;
299 
304 typedef struct
305 {
306  __IO uint32_t DR;
307  __IO uint8_t IDR;
308  uint8_t RESERVED0;
309  uint16_t RESERVED1;
310  __IO uint32_t CR;
311 } CRC_TypeDef;
312 
317 typedef struct
318 {
319  __IO uint32_t CR;
320  __IO uint32_t SWTRIGR;
321  __IO uint32_t DHR12R1;
322  __IO uint32_t DHR12L1;
323  __IO uint32_t DHR8R1;
324  __IO uint32_t DHR12R2;
325  __IO uint32_t DHR12L2;
326  __IO uint32_t DHR8R2;
327  __IO uint32_t DHR12RD;
328  __IO uint32_t DHR12LD;
329  __IO uint32_t DHR8RD;
330  __IO uint32_t DOR1;
331  __IO uint32_t DOR2;
332  __IO uint32_t SR;
333 } DAC_TypeDef;
334 
339 typedef struct
340 {
341  __IO uint32_t IDCODE;
342  __IO uint32_t CR;
343  __IO uint32_t APB1FZ;
344  __IO uint32_t APB2FZ;
345 }DBGMCU_TypeDef;
346 
351 typedef struct
352 {
353  __IO uint32_t CR;
354  __IO uint32_t SR;
355  __IO uint32_t RISR;
356  __IO uint32_t IER;
357  __IO uint32_t MISR;
358  __IO uint32_t ICR;
359  __IO uint32_t ESCR;
360  __IO uint32_t ESUR;
361  __IO uint32_t CWSTRTR;
362  __IO uint32_t CWSIZER;
363  __IO uint32_t DR;
364 } DCMI_TypeDef;
365 
370 typedef struct
371 {
372  __IO uint32_t CR;
373  __IO uint32_t NDTR;
374  __IO uint32_t PAR;
375  __IO uint32_t M0AR;
376  __IO uint32_t M1AR;
377  __IO uint32_t FCR;
378 } DMA_Stream_TypeDef;
379 
380 typedef struct
381 {
382  __IO uint32_t LISR;
383  __IO uint32_t HISR;
384  __IO uint32_t LIFCR;
385  __IO uint32_t HIFCR;
386 } DMA_TypeDef;
387 
392 typedef struct
393 {
394  __IO uint32_t CR;
395  __IO uint32_t ISR;
396  __IO uint32_t IFCR;
397  __IO uint32_t FGMAR;
398  __IO uint32_t FGOR;
399  __IO uint32_t BGMAR;
400  __IO uint32_t BGOR;
401  __IO uint32_t FGPFCCR;
402  __IO uint32_t FGCOLR;
403  __IO uint32_t BGPFCCR;
404  __IO uint32_t BGCOLR;
405  __IO uint32_t FGCMAR;
406  __IO uint32_t BGCMAR;
407  __IO uint32_t OPFCCR;
408  __IO uint32_t OCOLR;
409  __IO uint32_t OMAR;
410  __IO uint32_t OOR;
411  __IO uint32_t NLR;
412  __IO uint32_t LWR;
413  __IO uint32_t AMTCR;
414  uint32_t RESERVED[236];
415  __IO uint32_t FGCLUT[256];
416  __IO uint32_t BGCLUT[256];
417 } DMA2D_TypeDef;
418 
423 typedef struct
424 {
425  __IO uint32_t MACCR;
426  __IO uint32_t MACFFR;
427  __IO uint32_t MACHTHR;
428  __IO uint32_t MACHTLR;
429  __IO uint32_t MACMIIAR;
430  __IO uint32_t MACMIIDR;
431  __IO uint32_t MACFCR;
432  __IO uint32_t MACVLANTR; /* 8 */
433  uint32_t RESERVED0[2];
434  __IO uint32_t MACRWUFFR; /* 11 */
435  __IO uint32_t MACPMTCSR;
436  uint32_t RESERVED1[2];
437  __IO uint32_t MACSR; /* 15 */
438  __IO uint32_t MACIMR;
439  __IO uint32_t MACA0HR;
440  __IO uint32_t MACA0LR;
441  __IO uint32_t MACA1HR;
442  __IO uint32_t MACA1LR;
443  __IO uint32_t MACA2HR;
444  __IO uint32_t MACA2LR;
445  __IO uint32_t MACA3HR;
446  __IO uint32_t MACA3LR; /* 24 */
447  uint32_t RESERVED2[40];
448  __IO uint32_t MMCCR; /* 65 */
449  __IO uint32_t MMCRIR;
450  __IO uint32_t MMCTIR;
451  __IO uint32_t MMCRIMR;
452  __IO uint32_t MMCTIMR; /* 69 */
453  uint32_t RESERVED3[14];
454  __IO uint32_t MMCTGFSCCR; /* 84 */
455  __IO uint32_t MMCTGFMSCCR;
456  uint32_t RESERVED4[5];
457  __IO uint32_t MMCTGFCR;
458  uint32_t RESERVED5[10];
459  __IO uint32_t MMCRFCECR;
460  __IO uint32_t MMCRFAECR;
461  uint32_t RESERVED6[10];
462  __IO uint32_t MMCRGUFCR;
463  uint32_t RESERVED7[334];
464  __IO uint32_t PTPTSCR;
465  __IO uint32_t PTPSSIR;
466  __IO uint32_t PTPTSHR;
467  __IO uint32_t PTPTSLR;
468  __IO uint32_t PTPTSHUR;
469  __IO uint32_t PTPTSLUR;
470  __IO uint32_t PTPTSAR;
471  __IO uint32_t PTPTTHR;
472  __IO uint32_t PTPTTLR;
473  __IO uint32_t RESERVED8;
474  __IO uint32_t PTPTSSR;
475  uint32_t RESERVED9[565];
476  __IO uint32_t DMABMR;
477  __IO uint32_t DMATPDR;
478  __IO uint32_t DMARPDR;
479  __IO uint32_t DMARDLAR;
480  __IO uint32_t DMATDLAR;
481  __IO uint32_t DMASR;
482  __IO uint32_t DMAOMR;
483  __IO uint32_t DMAIER;
484  __IO uint32_t DMAMFBOCR;
485  __IO uint32_t DMARSWTR;
486  uint32_t RESERVED10[8];
487  __IO uint32_t DMACHTDR;
488  __IO uint32_t DMACHRDR;
489  __IO uint32_t DMACHTBAR;
490  __IO uint32_t DMACHRBAR;
491 } ETH_TypeDef;
492 
497 typedef struct
498 {
499  __IO uint32_t IMR;
500  __IO uint32_t EMR;
501  __IO uint32_t RTSR;
502  __IO uint32_t FTSR;
503  __IO uint32_t SWIER;
504  __IO uint32_t PR;
505 } EXTI_TypeDef;
506 
511 typedef struct
512 {
513  __IO uint32_t ACR;
514  __IO uint32_t KEYR;
515  __IO uint32_t OPTKEYR;
516  __IO uint32_t SR;
517  __IO uint32_t CR;
518  __IO uint32_t OPTCR;
519  __IO uint32_t OPTCR1;
520 } FLASH_TypeDef;
521 
526 typedef struct
527 {
528  __IO uint32_t BTCR[8];
529 } FMC_Bank1_TypeDef;
530 
535 typedef struct
536 {
537  __IO uint32_t BWTR[7];
538 } FMC_Bank1E_TypeDef;
539 
544 typedef struct
545 {
546  __IO uint32_t PCR2;
547  __IO uint32_t SR2;
548  __IO uint32_t PMEM2;
549  __IO uint32_t PATT2;
550  uint32_t RESERVED0;
551  __IO uint32_t ECCR2;
552  uint32_t RESERVED1;
553  uint32_t RESERVED2;
554  __IO uint32_t PCR3;
555  __IO uint32_t SR3;
556  __IO uint32_t PMEM3;
557  __IO uint32_t PATT3;
558  uint32_t RESERVED3;
559  __IO uint32_t ECCR3;
560 } FMC_Bank2_3_TypeDef;
561 
566 typedef struct
567 {
568  __IO uint32_t PCR4;
569  __IO uint32_t SR4;
570  __IO uint32_t PMEM4;
571  __IO uint32_t PATT4;
572  __IO uint32_t PIO4;
573 } FMC_Bank4_TypeDef;
574 
579 typedef struct
580 {
581  __IO uint32_t SDCR[2];
582  __IO uint32_t SDTR[2];
583  __IO uint32_t SDCMR;
584  __IO uint32_t SDRTR;
585  __IO uint32_t SDSR;
586 } FMC_Bank5_6_TypeDef;
587 
592 typedef struct
593 {
594  __IO uint32_t MODER;
595  __IO uint32_t OTYPER;
596  __IO uint32_t OSPEEDR;
597  __IO uint32_t PUPDR;
598  __IO uint32_t IDR;
599  __IO uint32_t ODR;
600  __IO uint32_t BSRR;
601  __IO uint32_t LCKR;
602  __IO uint32_t AFR[2];
603 } GPIO_TypeDef;
604 
609 typedef struct
610 {
611  __IO uint32_t MEMRMP;
612  __IO uint32_t PMC;
613  __IO uint32_t EXTICR[4];
614  uint32_t RESERVED[2];
615  __IO uint32_t CMPCR;
616 } SYSCFG_TypeDef;
617 
622 typedef struct
623 {
624  __IO uint32_t CR1;
625  __IO uint32_t CR2;
626  __IO uint32_t OAR1;
627  __IO uint32_t OAR2;
628  __IO uint32_t DR;
629  __IO uint32_t SR1;
630  __IO uint32_t SR2;
631  __IO uint32_t CCR;
632  __IO uint32_t TRISE;
633  __IO uint32_t FLTR;
634 } I2C_TypeDef;
635 
640 typedef struct
641 {
642  __IO uint32_t KR;
643  __IO uint32_t PR;
644  __IO uint32_t RLR;
645  __IO uint32_t SR;
646 } IWDG_TypeDef;
647 
648 
653 typedef struct
654 {
655  __IO uint32_t CR;
656  __IO uint32_t CSR;
657 } PWR_TypeDef;
658 
663 typedef struct
664 {
665  __IO uint32_t CR;
666  __IO uint32_t PLLCFGR;
667  __IO uint32_t CFGR;
668  __IO uint32_t CIR;
669  __IO uint32_t AHB1RSTR;
670  __IO uint32_t AHB2RSTR;
671  __IO uint32_t AHB3RSTR;
672  uint32_t RESERVED0;
673  __IO uint32_t APB1RSTR;
674  __IO uint32_t APB2RSTR;
675  uint32_t RESERVED1[2];
676  __IO uint32_t AHB1ENR;
677  __IO uint32_t AHB2ENR;
678  __IO uint32_t AHB3ENR;
679  uint32_t RESERVED2;
680  __IO uint32_t APB1ENR;
681  __IO uint32_t APB2ENR;
682  uint32_t RESERVED3[2];
683  __IO uint32_t AHB1LPENR;
684  __IO uint32_t AHB2LPENR;
685  __IO uint32_t AHB3LPENR;
686  uint32_t RESERVED4;
687  __IO uint32_t APB1LPENR;
688  __IO uint32_t APB2LPENR;
689  uint32_t RESERVED5[2];
690  __IO uint32_t BDCR;
691  __IO uint32_t CSR;
692  uint32_t RESERVED6[2];
693  __IO uint32_t SSCGR;
694  __IO uint32_t PLLI2SCFGR;
695  __IO uint32_t PLLSAICFGR;
696  __IO uint32_t DCKCFGR;
698 } RCC_TypeDef;
699 
704 typedef struct
705 {
706  __IO uint32_t TR;
707  __IO uint32_t DR;
708  __IO uint32_t CR;
709  __IO uint32_t ISR;
710  __IO uint32_t PRER;
711  __IO uint32_t WUTR;
712  __IO uint32_t CALIBR;
713  __IO uint32_t ALRMAR;
714  __IO uint32_t ALRMBR;
715  __IO uint32_t WPR;
716  __IO uint32_t SSR;
717  __IO uint32_t SHIFTR;
718  __IO uint32_t TSTR;
719  __IO uint32_t TSDR;
720  __IO uint32_t TSSSR;
721  __IO uint32_t CALR;
722  __IO uint32_t TAFCR;
723  __IO uint32_t ALRMASSR;
724  __IO uint32_t ALRMBSSR;
725  uint32_t RESERVED7;
726  __IO uint32_t BKP0R;
727  __IO uint32_t BKP1R;
728  __IO uint32_t BKP2R;
729  __IO uint32_t BKP3R;
730  __IO uint32_t BKP4R;
731  __IO uint32_t BKP5R;
732  __IO uint32_t BKP6R;
733  __IO uint32_t BKP7R;
734  __IO uint32_t BKP8R;
735  __IO uint32_t BKP9R;
736  __IO uint32_t BKP10R;
737  __IO uint32_t BKP11R;
738  __IO uint32_t BKP12R;
739  __IO uint32_t BKP13R;
740  __IO uint32_t BKP14R;
741  __IO uint32_t BKP15R;
742  __IO uint32_t BKP16R;
743  __IO uint32_t BKP17R;
744  __IO uint32_t BKP18R;
745  __IO uint32_t BKP19R;
746 } RTC_TypeDef;
747 
752 typedef struct
753 {
754  __IO uint32_t GCR;
755 } SAI_TypeDef;
756 
757 typedef struct
758 {
759  __IO uint32_t CR1;
760  __IO uint32_t CR2;
761  __IO uint32_t FRCR;
762  __IO uint32_t SLOTR;
763  __IO uint32_t IMR;
764  __IO uint32_t SR;
765  __IO uint32_t CLRFR;
766  __IO uint32_t DR;
767 } SAI_Block_TypeDef;
768 
773 typedef struct
774 {
775  __IO uint32_t POWER;
776  __IO uint32_t CLKCR;
777  __IO uint32_t ARG;
778  __IO uint32_t CMD;
779  __I uint32_t RESPCMD;
780  __I uint32_t RESP1;
781  __I uint32_t RESP2;
782  __I uint32_t RESP3;
783  __I uint32_t RESP4;
784  __IO uint32_t DTIMER;
785  __IO uint32_t DLEN;
786  __IO uint32_t DCTRL;
787  __I uint32_t DCOUNT;
788  __I uint32_t STA;
789  __IO uint32_t ICR;
790  __IO uint32_t MASK;
791  uint32_t RESERVED0[2];
792  __I uint32_t FIFOCNT;
793  uint32_t RESERVED1[13];
794  __IO uint32_t FIFO;
795 } SDIO_TypeDef;
796 
801 typedef struct
802 {
803  __IO uint32_t CR1;
804  __IO uint32_t CR2;
805  __IO uint32_t SR;
806  __IO uint32_t DR;
807  __IO uint32_t CRCPR;
808  __IO uint32_t RXCRCR;
809  __IO uint32_t TXCRCR;
810  __IO uint32_t I2SCFGR;
811  __IO uint32_t I2SPR;
812 } SPI_TypeDef;
813 
818 typedef struct
819 {
820  __IO uint32_t CR1;
821  __IO uint32_t CR2;
822  __IO uint32_t SMCR;
823  __IO uint32_t DIER;
824  __IO uint32_t SR;
825  __IO uint32_t EGR;
826  __IO uint32_t CCMR1;
827  __IO uint32_t CCMR2;
828  __IO uint32_t CCER;
829  __IO uint32_t CNT;
830  __IO uint32_t PSC;
831  __IO uint32_t ARR;
832  __IO uint32_t RCR;
833  __IO uint32_t CCR1;
834  __IO uint32_t CCR2;
835  __IO uint32_t CCR3;
836  __IO uint32_t CCR4;
837  __IO uint32_t BDTR;
838  __IO uint32_t DCR;
839  __IO uint32_t DMAR;
840  __IO uint32_t OR;
841 } TIM_TypeDef;
842 
847 typedef struct
848 {
849  __IO uint32_t SR;
850  __IO uint32_t DR;
851  __IO uint32_t BRR;
852  __IO uint32_t CR1;
853  __IO uint32_t CR2;
854  __IO uint32_t CR3;
855  __IO uint32_t GTPR;
856 } USART_TypeDef;
857 
862 typedef struct
863 {
864  __IO uint32_t CR;
865  __IO uint32_t CFR;
866  __IO uint32_t SR;
867 } WWDG_TypeDef;
868 
873 typedef struct
874 {
875  __IO uint32_t CR;
876  __IO uint32_t SR;
877  __IO uint32_t DR;
878  __IO uint32_t DOUT;
879  __IO uint32_t DMACR;
880  __IO uint32_t IMSCR;
881  __IO uint32_t RISR;
882  __IO uint32_t MISR;
883  __IO uint32_t K0LR;
884  __IO uint32_t K0RR;
885  __IO uint32_t K1LR;
886  __IO uint32_t K1RR;
887  __IO uint32_t K2LR;
888  __IO uint32_t K2RR;
889  __IO uint32_t K3LR;
890  __IO uint32_t K3RR;
891  __IO uint32_t IV0LR;
892  __IO uint32_t IV0RR;
893  __IO uint32_t IV1LR;
894  __IO uint32_t IV1RR;
895  __IO uint32_t CSGCMCCM0R;
896  __IO uint32_t CSGCMCCM1R;
897  __IO uint32_t CSGCMCCM2R;
898  __IO uint32_t CSGCMCCM3R;
899  __IO uint32_t CSGCMCCM4R;
900  __IO uint32_t CSGCMCCM5R;
901  __IO uint32_t CSGCMCCM6R;
902  __IO uint32_t CSGCMCCM7R;
903  __IO uint32_t CSGCM0R;
904  __IO uint32_t CSGCM1R;
905  __IO uint32_t CSGCM2R;
906  __IO uint32_t CSGCM3R;
907  __IO uint32_t CSGCM4R;
908  __IO uint32_t CSGCM5R;
909  __IO uint32_t CSGCM6R;
910  __IO uint32_t CSGCM7R;
911 } CRYP_TypeDef;
912 
917 typedef struct
918 {
919  __IO uint32_t CR;
920  __IO uint32_t DIN;
921  __IO uint32_t STR;
922  __IO uint32_t HR[5];
923  __IO uint32_t IMR;
924  __IO uint32_t SR;
925  uint32_t RESERVED[52];
926  __IO uint32_t CSR[54];
927 } HASH_TypeDef;
928 
933 typedef struct
934 {
935  __IO uint32_t HR[8];
936 } HASH_DIGEST_TypeDef;
937 
942 typedef struct
943 {
944  __IO uint32_t CR;
945  __IO uint32_t SR;
946  __IO uint32_t DR;
947 } RNG_TypeDef;
948 
949 
953 typedef struct
954 {
955  __IO uint32_t GOTGCTL;
956  __IO uint32_t GOTGINT;
957  __IO uint32_t GAHBCFG;
958  __IO uint32_t GUSBCFG;
959  __IO uint32_t GRSTCTL;
960  __IO uint32_t GINTSTS;
961  __IO uint32_t GINTMSK;
962  __IO uint32_t GRXSTSR;
963  __IO uint32_t GRXSTSP;
964  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
965  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
966  __IO uint32_t HNPTXSTS;
967  uint32_t Reserved30[2]; /* Reserved 030h*/
968  __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
969  __IO uint32_t CID; /* User ID Register 03Ch*/
970  uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
971  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
972  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
973 }
974 USB_OTG_GlobalTypeDef;
975 
976 
980 typedef struct
981 {
982  __IO uint32_t DCFG; /* dev Configuration Register 800h*/
983  __IO uint32_t DCTL; /* dev Control Register 804h*/
984  __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
985  uint32_t Reserved0C; /* Reserved 80Ch*/
986  __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
987  __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
988  __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
989  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
990  uint32_t Reserved20; /* Reserved 820h*/
991  uint32_t Reserved9; /* Reserved 824h*/
992  __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
993  __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
994  __IO uint32_t DTHRCTL; /* dev thr 830h*/
995  __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
996  __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
997  __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
998  uint32_t Reserved40; /* dedicated EP mask 840h*/
999  __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
1000  uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
1001  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
1002 }
1003 USB_OTG_DeviceTypeDef;
1004 
1005 
1009 typedef struct
1010 {
1011  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1012  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
1013  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
1014  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
1015  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
1016  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
1017  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1018  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1019 }
1020 USB_OTG_INEndpointTypeDef;
1021 
1022 
1026 typedef struct
1027 {
1028  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1029  uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1030  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1031  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1032  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1033  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1034  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1035 }
1036 USB_OTG_OUTEndpointTypeDef;
1037 
1038 
1042 typedef struct
1043 {
1044  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1045  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1046  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1047  uint32_t Reserved40C; /* Reserved 40Ch*/
1048  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1049  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1050  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1051 }
1052 USB_OTG_HostTypeDef;
1053 
1057 typedef struct
1058 {
1059  __IO uint32_t HCCHAR;
1060  __IO uint32_t HCSPLT;
1061  __IO uint32_t HCINT;
1062  __IO uint32_t HCINTMSK;
1063  __IO uint32_t HCTSIZ;
1064  __IO uint32_t HCDMA;
1065  uint32_t Reserved[2];
1066 }
1067 USB_OTG_HostChannelTypeDef;
1075 #define FLASH_BASE 0x08000000U
1076 #define CCMDATARAM_BASE 0x10000000U
1077 #define SRAM1_BASE 0x20000000U
1078 #define SRAM2_BASE 0x2001C000U
1079 #define SRAM3_BASE 0x20020000U
1080 #define PERIPH_BASE 0x40000000U
1081 #define BKPSRAM_BASE 0x40024000U
1082 #define FMC_R_BASE 0xA0000000U
1083 #define SRAM1_BB_BASE 0x22000000U
1084 #define SRAM2_BB_BASE 0x22380000U
1085 #define SRAM3_BB_BASE 0x22400000U
1086 #define PERIPH_BB_BASE 0x42000000U
1087 #define BKPSRAM_BB_BASE 0x42480000U
1088 #define FLASH_END 0x081FFFFFU
1089 #define CCMDATARAM_END 0x1000FFFFU
1091 /* Legacy defines */
1092 #define SRAM_BASE SRAM1_BASE
1093 #define SRAM_BB_BASE SRAM1_BB_BASE
1094 
1095 
1097 #define APB1PERIPH_BASE PERIPH_BASE
1098 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1099 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1100 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1101 
1103 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1104 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1105 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1106 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1107 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1108 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1109 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1110 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1111 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1112 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1113 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1114 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1115 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1116 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1117 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1118 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1119 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1120 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1121 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1122 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1123 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1124 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1125 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1126 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1127 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1128 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1129 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1130 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1131 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1132 
1134 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1135 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1136 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1137 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1138 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1139 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1140 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1141 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1142 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1143 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1144 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1145 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1146 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1147 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1148 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1149 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1150 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1151 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1152 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1153 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1154 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1155 
1157 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1158 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1159 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1160 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1161 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1162 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1163 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1164 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1165 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1166 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1167 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1168 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1169 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1170 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1171 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1172 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1173 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1174 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1175 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1176 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1177 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1178 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1179 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1180 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1181 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1182 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1183 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1184 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1185 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1186 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1187 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1188 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1189 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1190 #define ETH_MAC_BASE (ETH_BASE)
1191 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1192 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1193 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1194 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1195 
1197 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1198 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1199 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1200 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1201 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1202 
1204 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1205 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1206 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
1207 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
1208 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1209 
1210 /* Debug MCU registers base address */
1211 #define DBGMCU_BASE 0xE0042000U
1212 
1214 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1215 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1216 
1217 #define USB_OTG_GLOBAL_BASE 0x000U
1218 #define USB_OTG_DEVICE_BASE 0x800U
1219 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1220 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1221 #define USB_OTG_EP_REG_SIZE 0x20U
1222 #define USB_OTG_HOST_BASE 0x400U
1223 #define USB_OTG_HOST_PORT_BASE 0x440U
1224 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1225 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1226 #define USB_OTG_PCGCCTL_BASE 0xE00U
1227 #define USB_OTG_FIFO_BASE 0x1000U
1228 #define USB_OTG_FIFO_SIZE 0x1000U
1229 
1237 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1238 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1239 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1240 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1241 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1242 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1243 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1244 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1245 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1246 #define RTC ((RTC_TypeDef *) RTC_BASE)
1247 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1248 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1249 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1250 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1251 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1252 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1253 #define USART2 ((USART_TypeDef *) USART2_BASE)
1254 #define USART3 ((USART_TypeDef *) USART3_BASE)
1255 #define UART4 ((USART_TypeDef *) UART4_BASE)
1256 #define UART5 ((USART_TypeDef *) UART5_BASE)
1257 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1258 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1259 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1260 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1261 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1262 #define PWR ((PWR_TypeDef *) PWR_BASE)
1263 #define DAC ((DAC_TypeDef *) DAC_BASE)
1264 #define UART7 ((USART_TypeDef *) UART7_BASE)
1265 #define UART8 ((USART_TypeDef *) UART8_BASE)
1266 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1267 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1268 #define USART1 ((USART_TypeDef *) USART1_BASE)
1269 #define USART6 ((USART_TypeDef *) USART6_BASE)
1270 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1271 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1272 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1273 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1274 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1275 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1276 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1277 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1278 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1279 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1280 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1281 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1282 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1283 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1284 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1285 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1286 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1287 
1288 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1289 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1290 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1291 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1292 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1293 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1294 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1295 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1296 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1297 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1298 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1299 #define CRC ((CRC_TypeDef *) CRC_BASE)
1300 #define RCC ((RCC_TypeDef *) RCC_BASE)
1301 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1302 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1303 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1304 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1305 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1306 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1307 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1308 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1309 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1310 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1311 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1312 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1313 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1314 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1315 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1316 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1317 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1318 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1319 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1320 #define ETH ((ETH_TypeDef *) ETH_BASE)
1321 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1322 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1323 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1324 #define HASH ((HASH_TypeDef *) HASH_BASE)
1325 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1326 #define RNG ((RNG_TypeDef *) RNG_BASE)
1327 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1328 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1329 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1330 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1331 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1332 
1333 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1334 
1335 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1336 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1337 
1350 /******************************************************************************/
1351 /* Peripheral Registers_Bits_Definition */
1352 /******************************************************************************/
1353 
1354 /******************************************************************************/
1355 /* */
1356 /* Analog to Digital Converter */
1357 /* */
1358 /******************************************************************************/
1359 /******************** Bit definition for ADC_SR register ********************/
1360 #define ADC_SR_AWD 0x00000001U
1361 #define ADC_SR_EOC 0x00000002U
1362 #define ADC_SR_JEOC 0x00000004U
1363 #define ADC_SR_JSTRT 0x00000008U
1364 #define ADC_SR_STRT 0x00000010U
1365 #define ADC_SR_OVR 0x00000020U
1367 /******************* Bit definition for ADC_CR1 register ********************/
1368 #define ADC_CR1_AWDCH 0x0000001FU
1369 #define ADC_CR1_AWDCH_0 0x00000001U
1370 #define ADC_CR1_AWDCH_1 0x00000002U
1371 #define ADC_CR1_AWDCH_2 0x00000004U
1372 #define ADC_CR1_AWDCH_3 0x00000008U
1373 #define ADC_CR1_AWDCH_4 0x00000010U
1374 #define ADC_CR1_EOCIE 0x00000020U
1375 #define ADC_CR1_AWDIE 0x00000040U
1376 #define ADC_CR1_JEOCIE 0x00000080U
1377 #define ADC_CR1_SCAN 0x00000100U
1378 #define ADC_CR1_AWDSGL 0x00000200U
1379 #define ADC_CR1_JAUTO 0x00000400U
1380 #define ADC_CR1_DISCEN 0x00000800U
1381 #define ADC_CR1_JDISCEN 0x00001000U
1382 #define ADC_CR1_DISCNUM 0x0000E000U
1383 #define ADC_CR1_DISCNUM_0 0x00002000U
1384 #define ADC_CR1_DISCNUM_1 0x00004000U
1385 #define ADC_CR1_DISCNUM_2 0x00008000U
1386 #define ADC_CR1_JAWDEN 0x00400000U
1387 #define ADC_CR1_AWDEN 0x00800000U
1388 #define ADC_CR1_RES 0x03000000U
1389 #define ADC_CR1_RES_0 0x01000000U
1390 #define ADC_CR1_RES_1 0x02000000U
1391 #define ADC_CR1_OVRIE 0x04000000U
1393 /******************* Bit definition for ADC_CR2 register ********************/
1394 #define ADC_CR2_ADON 0x00000001U
1395 #define ADC_CR2_CONT 0x00000002U
1396 #define ADC_CR2_DMA 0x00000100U
1397 #define ADC_CR2_DDS 0x00000200U
1398 #define ADC_CR2_EOCS 0x00000400U
1399 #define ADC_CR2_ALIGN 0x00000800U
1400 #define ADC_CR2_JEXTSEL 0x000F0000U
1401 #define ADC_CR2_JEXTSEL_0 0x00010000U
1402 #define ADC_CR2_JEXTSEL_1 0x00020000U
1403 #define ADC_CR2_JEXTSEL_2 0x00040000U
1404 #define ADC_CR2_JEXTSEL_3 0x00080000U
1405 #define ADC_CR2_JEXTEN 0x00300000U
1406 #define ADC_CR2_JEXTEN_0 0x00100000U
1407 #define ADC_CR2_JEXTEN_1 0x00200000U
1408 #define ADC_CR2_JSWSTART 0x00400000U
1409 #define ADC_CR2_EXTSEL 0x0F000000U
1410 #define ADC_CR2_EXTSEL_0 0x01000000U
1411 #define ADC_CR2_EXTSEL_1 0x02000000U
1412 #define ADC_CR2_EXTSEL_2 0x04000000U
1413 #define ADC_CR2_EXTSEL_3 0x08000000U
1414 #define ADC_CR2_EXTEN 0x30000000U
1415 #define ADC_CR2_EXTEN_0 0x10000000U
1416 #define ADC_CR2_EXTEN_1 0x20000000U
1417 #define ADC_CR2_SWSTART 0x40000000U
1419 /****************** Bit definition for ADC_SMPR1 register *******************/
1420 #define ADC_SMPR1_SMP10 0x00000007U
1421 #define ADC_SMPR1_SMP10_0 0x00000001U
1422 #define ADC_SMPR1_SMP10_1 0x00000002U
1423 #define ADC_SMPR1_SMP10_2 0x00000004U
1424 #define ADC_SMPR1_SMP11 0x00000038U
1425 #define ADC_SMPR1_SMP11_0 0x00000008U
1426 #define ADC_SMPR1_SMP11_1 0x00000010U
1427 #define ADC_SMPR1_SMP11_2 0x00000020U
1428 #define ADC_SMPR1_SMP12 0x000001C0U
1429 #define ADC_SMPR1_SMP12_0 0x00000040U
1430 #define ADC_SMPR1_SMP12_1 0x00000080U
1431 #define ADC_SMPR1_SMP12_2 0x00000100U
1432 #define ADC_SMPR1_SMP13 0x00000E00U
1433 #define ADC_SMPR1_SMP13_0 0x00000200U
1434 #define ADC_SMPR1_SMP13_1 0x00000400U
1435 #define ADC_SMPR1_SMP13_2 0x00000800U
1436 #define ADC_SMPR1_SMP14 0x00007000U
1437 #define ADC_SMPR1_SMP14_0 0x00001000U
1438 #define ADC_SMPR1_SMP14_1 0x00002000U
1439 #define ADC_SMPR1_SMP14_2 0x00004000U
1440 #define ADC_SMPR1_SMP15 0x00038000U
1441 #define ADC_SMPR1_SMP15_0 0x00008000U
1442 #define ADC_SMPR1_SMP15_1 0x00010000U
1443 #define ADC_SMPR1_SMP15_2 0x00020000U
1444 #define ADC_SMPR1_SMP16 0x001C0000U
1445 #define ADC_SMPR1_SMP16_0 0x00040000U
1446 #define ADC_SMPR1_SMP16_1 0x00080000U
1447 #define ADC_SMPR1_SMP16_2 0x00100000U
1448 #define ADC_SMPR1_SMP17 0x00E00000U
1449 #define ADC_SMPR1_SMP17_0 0x00200000U
1450 #define ADC_SMPR1_SMP17_1 0x00400000U
1451 #define ADC_SMPR1_SMP17_2 0x00800000U
1452 #define ADC_SMPR1_SMP18 0x07000000U
1453 #define ADC_SMPR1_SMP18_0 0x01000000U
1454 #define ADC_SMPR1_SMP18_1 0x02000000U
1455 #define ADC_SMPR1_SMP18_2 0x04000000U
1457 /****************** Bit definition for ADC_SMPR2 register *******************/
1458 #define ADC_SMPR2_SMP0 0x00000007U
1459 #define ADC_SMPR2_SMP0_0 0x00000001U
1460 #define ADC_SMPR2_SMP0_1 0x00000002U
1461 #define ADC_SMPR2_SMP0_2 0x00000004U
1462 #define ADC_SMPR2_SMP1 0x00000038U
1463 #define ADC_SMPR2_SMP1_0 0x00000008U
1464 #define ADC_SMPR2_SMP1_1 0x00000010U
1465 #define ADC_SMPR2_SMP1_2 0x00000020U
1466 #define ADC_SMPR2_SMP2 0x000001C0U
1467 #define ADC_SMPR2_SMP2_0 0x00000040U
1468 #define ADC_SMPR2_SMP2_1 0x00000080U
1469 #define ADC_SMPR2_SMP2_2 0x00000100U
1470 #define ADC_SMPR2_SMP3 0x00000E00U
1471 #define ADC_SMPR2_SMP3_0 0x00000200U
1472 #define ADC_SMPR2_SMP3_1 0x00000400U
1473 #define ADC_SMPR2_SMP3_2 0x00000800U
1474 #define ADC_SMPR2_SMP4 0x00007000U
1475 #define ADC_SMPR2_SMP4_0 0x00001000U
1476 #define ADC_SMPR2_SMP4_1 0x00002000U
1477 #define ADC_SMPR2_SMP4_2 0x00004000U
1478 #define ADC_SMPR2_SMP5 0x00038000U
1479 #define ADC_SMPR2_SMP5_0 0x00008000U
1480 #define ADC_SMPR2_SMP5_1 0x00010000U
1481 #define ADC_SMPR2_SMP5_2 0x00020000U
1482 #define ADC_SMPR2_SMP6 0x001C0000U
1483 #define ADC_SMPR2_SMP6_0 0x00040000U
1484 #define ADC_SMPR2_SMP6_1 0x00080000U
1485 #define ADC_SMPR2_SMP6_2 0x00100000U
1486 #define ADC_SMPR2_SMP7 0x00E00000U
1487 #define ADC_SMPR2_SMP7_0 0x00200000U
1488 #define ADC_SMPR2_SMP7_1 0x00400000U
1489 #define ADC_SMPR2_SMP7_2 0x00800000U
1490 #define ADC_SMPR2_SMP8 0x07000000U
1491 #define ADC_SMPR2_SMP8_0 0x01000000U
1492 #define ADC_SMPR2_SMP8_1 0x02000000U
1493 #define ADC_SMPR2_SMP8_2 0x04000000U
1494 #define ADC_SMPR2_SMP9 0x38000000U
1495 #define ADC_SMPR2_SMP9_0 0x08000000U
1496 #define ADC_SMPR2_SMP9_1 0x10000000U
1497 #define ADC_SMPR2_SMP9_2 0x20000000U
1499 /****************** Bit definition for ADC_JOFR1 register *******************/
1500 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1502 /****************** Bit definition for ADC_JOFR2 register *******************/
1503 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1505 /****************** Bit definition for ADC_JOFR3 register *******************/
1506 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1508 /****************** Bit definition for ADC_JOFR4 register *******************/
1509 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1511 /******************* Bit definition for ADC_HTR register ********************/
1512 #define ADC_HTR_HT 0x0FFFU
1514 /******************* Bit definition for ADC_LTR register ********************/
1515 #define ADC_LTR_LT 0x0FFFU
1517 /******************* Bit definition for ADC_SQR1 register *******************/
1518 #define ADC_SQR1_SQ13 0x0000001FU
1519 #define ADC_SQR1_SQ13_0 0x00000001U
1520 #define ADC_SQR1_SQ13_1 0x00000002U
1521 #define ADC_SQR1_SQ13_2 0x00000004U
1522 #define ADC_SQR1_SQ13_3 0x00000008U
1523 #define ADC_SQR1_SQ13_4 0x00000010U
1524 #define ADC_SQR1_SQ14 0x000003E0U
1525 #define ADC_SQR1_SQ14_0 0x00000020U
1526 #define ADC_SQR1_SQ14_1 0x00000040U
1527 #define ADC_SQR1_SQ14_2 0x00000080U
1528 #define ADC_SQR1_SQ14_3 0x00000100U
1529 #define ADC_SQR1_SQ14_4 0x00000200U
1530 #define ADC_SQR1_SQ15 0x00007C00U
1531 #define ADC_SQR1_SQ15_0 0x00000400U
1532 #define ADC_SQR1_SQ15_1 0x00000800U
1533 #define ADC_SQR1_SQ15_2 0x00001000U
1534 #define ADC_SQR1_SQ15_3 0x00002000U
1535 #define ADC_SQR1_SQ15_4 0x00004000U
1536 #define ADC_SQR1_SQ16 0x000F8000U
1537 #define ADC_SQR1_SQ16_0 0x00008000U
1538 #define ADC_SQR1_SQ16_1 0x00010000U
1539 #define ADC_SQR1_SQ16_2 0x00020000U
1540 #define ADC_SQR1_SQ16_3 0x00040000U
1541 #define ADC_SQR1_SQ16_4 0x00080000U
1542 #define ADC_SQR1_L 0x00F00000U
1543 #define ADC_SQR1_L_0 0x00100000U
1544 #define ADC_SQR1_L_1 0x00200000U
1545 #define ADC_SQR1_L_2 0x00400000U
1546 #define ADC_SQR1_L_3 0x00800000U
1548 /******************* Bit definition for ADC_SQR2 register *******************/
1549 #define ADC_SQR2_SQ7 0x0000001FU
1550 #define ADC_SQR2_SQ7_0 0x00000001U
1551 #define ADC_SQR2_SQ7_1 0x00000002U
1552 #define ADC_SQR2_SQ7_2 0x00000004U
1553 #define ADC_SQR2_SQ7_3 0x00000008U
1554 #define ADC_SQR2_SQ7_4 0x00000010U
1555 #define ADC_SQR2_SQ8 0x000003E0U
1556 #define ADC_SQR2_SQ8_0 0x00000020U
1557 #define ADC_SQR2_SQ8_1 0x00000040U
1558 #define ADC_SQR2_SQ8_2 0x00000080U
1559 #define ADC_SQR2_SQ8_3 0x00000100U
1560 #define ADC_SQR2_SQ8_4 0x00000200U
1561 #define ADC_SQR2_SQ9 0x00007C00U
1562 #define ADC_SQR2_SQ9_0 0x00000400U
1563 #define ADC_SQR2_SQ9_1 0x00000800U
1564 #define ADC_SQR2_SQ9_2 0x00001000U
1565 #define ADC_SQR2_SQ9_3 0x00002000U
1566 #define ADC_SQR2_SQ9_4 0x00004000U
1567 #define ADC_SQR2_SQ10 0x000F8000U
1568 #define ADC_SQR2_SQ10_0 0x00008000U
1569 #define ADC_SQR2_SQ10_1 0x00010000U
1570 #define ADC_SQR2_SQ10_2 0x00020000U
1571 #define ADC_SQR2_SQ10_3 0x00040000U
1572 #define ADC_SQR2_SQ10_4 0x00080000U
1573 #define ADC_SQR2_SQ11 0x01F00000U
1574 #define ADC_SQR2_SQ11_0 0x00100000U
1575 #define ADC_SQR2_SQ11_1 0x00200000U
1576 #define ADC_SQR2_SQ11_2 0x00400000U
1577 #define ADC_SQR2_SQ11_3 0x00800000U
1578 #define ADC_SQR2_SQ11_4 0x01000000U
1579 #define ADC_SQR2_SQ12 0x3E000000U
1580 #define ADC_SQR2_SQ12_0 0x02000000U
1581 #define ADC_SQR2_SQ12_1 0x04000000U
1582 #define ADC_SQR2_SQ12_2 0x08000000U
1583 #define ADC_SQR2_SQ12_3 0x10000000U
1584 #define ADC_SQR2_SQ12_4 0x20000000U
1586 /******************* Bit definition for ADC_SQR3 register *******************/
1587 #define ADC_SQR3_SQ1 0x0000001FU
1588 #define ADC_SQR3_SQ1_0 0x00000001U
1589 #define ADC_SQR3_SQ1_1 0x00000002U
1590 #define ADC_SQR3_SQ1_2 0x00000004U
1591 #define ADC_SQR3_SQ1_3 0x00000008U
1592 #define ADC_SQR3_SQ1_4 0x00000010U
1593 #define ADC_SQR3_SQ2 0x000003E0U
1594 #define ADC_SQR3_SQ2_0 0x00000020U
1595 #define ADC_SQR3_SQ2_1 0x00000040U
1596 #define ADC_SQR3_SQ2_2 0x00000080U
1597 #define ADC_SQR3_SQ2_3 0x00000100U
1598 #define ADC_SQR3_SQ2_4 0x00000200U
1599 #define ADC_SQR3_SQ3 0x00007C00U
1600 #define ADC_SQR3_SQ3_0 0x00000400U
1601 #define ADC_SQR3_SQ3_1 0x00000800U
1602 #define ADC_SQR3_SQ3_2 0x00001000U
1603 #define ADC_SQR3_SQ3_3 0x00002000U
1604 #define ADC_SQR3_SQ3_4 0x00004000U
1605 #define ADC_SQR3_SQ4 0x000F8000U
1606 #define ADC_SQR3_SQ4_0 0x00008000U
1607 #define ADC_SQR3_SQ4_1 0x00010000U
1608 #define ADC_SQR3_SQ4_2 0x00020000U
1609 #define ADC_SQR3_SQ4_3 0x00040000U
1610 #define ADC_SQR3_SQ4_4 0x00080000U
1611 #define ADC_SQR3_SQ5 0x01F00000U
1612 #define ADC_SQR3_SQ5_0 0x00100000U
1613 #define ADC_SQR3_SQ5_1 0x00200000U
1614 #define ADC_SQR3_SQ5_2 0x00400000U
1615 #define ADC_SQR3_SQ5_3 0x00800000U
1616 #define ADC_SQR3_SQ5_4 0x01000000U
1617 #define ADC_SQR3_SQ6 0x3E000000U
1618 #define ADC_SQR3_SQ6_0 0x02000000U
1619 #define ADC_SQR3_SQ6_1 0x04000000U
1620 #define ADC_SQR3_SQ6_2 0x08000000U
1621 #define ADC_SQR3_SQ6_3 0x10000000U
1622 #define ADC_SQR3_SQ6_4 0x20000000U
1624 /******************* Bit definition for ADC_JSQR register *******************/
1625 #define ADC_JSQR_JSQ1 0x0000001FU
1626 #define ADC_JSQR_JSQ1_0 0x00000001U
1627 #define ADC_JSQR_JSQ1_1 0x00000002U
1628 #define ADC_JSQR_JSQ1_2 0x00000004U
1629 #define ADC_JSQR_JSQ1_3 0x00000008U
1630 #define ADC_JSQR_JSQ1_4 0x00000010U
1631 #define ADC_JSQR_JSQ2 0x000003E0U
1632 #define ADC_JSQR_JSQ2_0 0x00000020U
1633 #define ADC_JSQR_JSQ2_1 0x00000040U
1634 #define ADC_JSQR_JSQ2_2 0x00000080U
1635 #define ADC_JSQR_JSQ2_3 0x00000100U
1636 #define ADC_JSQR_JSQ2_4 0x00000200U
1637 #define ADC_JSQR_JSQ3 0x00007C00U
1638 #define ADC_JSQR_JSQ3_0 0x00000400U
1639 #define ADC_JSQR_JSQ3_1 0x00000800U
1640 #define ADC_JSQR_JSQ3_2 0x00001000U
1641 #define ADC_JSQR_JSQ3_3 0x00002000U
1642 #define ADC_JSQR_JSQ3_4 0x00004000U
1643 #define ADC_JSQR_JSQ4 0x000F8000U
1644 #define ADC_JSQR_JSQ4_0 0x00008000U
1645 #define ADC_JSQR_JSQ4_1 0x00010000U
1646 #define ADC_JSQR_JSQ4_2 0x00020000U
1647 #define ADC_JSQR_JSQ4_3 0x00040000U
1648 #define ADC_JSQR_JSQ4_4 0x00080000U
1649 #define ADC_JSQR_JL 0x00300000U
1650 #define ADC_JSQR_JL_0 0x00100000U
1651 #define ADC_JSQR_JL_1 0x00200000U
1653 /******************* Bit definition for ADC_JDR1 register *******************/
1654 #define ADC_JDR1_JDATA 0xFFFFU
1656 /******************* Bit definition for ADC_JDR2 register *******************/
1657 #define ADC_JDR2_JDATA 0xFFFFU
1659 /******************* Bit definition for ADC_JDR3 register *******************/
1660 #define ADC_JDR3_JDATA 0xFFFFU
1662 /******************* Bit definition for ADC_JDR4 register *******************/
1663 #define ADC_JDR4_JDATA 0xFFFFU
1665 /******************** Bit definition for ADC_DR register ********************/
1666 #define ADC_DR_DATA 0x0000FFFFU
1667 #define ADC_DR_ADC2DATA 0xFFFF0000U
1669 /******************* Bit definition for ADC_CSR register ********************/
1670 #define ADC_CSR_AWD1 0x00000001U
1671 #define ADC_CSR_EOC1 0x00000002U
1672 #define ADC_CSR_JEOC1 0x00000004U
1673 #define ADC_CSR_JSTRT1 0x00000008U
1674 #define ADC_CSR_STRT1 0x00000010U
1675 #define ADC_CSR_OVR1 0x00000020U
1676 #define ADC_CSR_AWD2 0x00000100U
1677 #define ADC_CSR_EOC2 0x00000200U
1678 #define ADC_CSR_JEOC2 0x00000400U
1679 #define ADC_CSR_JSTRT2 0x00000800U
1680 #define ADC_CSR_STRT2 0x00001000U
1681 #define ADC_CSR_OVR2 0x00002000U
1682 #define ADC_CSR_AWD3 0x00010000U
1683 #define ADC_CSR_EOC3 0x00020000U
1684 #define ADC_CSR_JEOC3 0x00040000U
1685 #define ADC_CSR_JSTRT3 0x00080000U
1686 #define ADC_CSR_STRT3 0x00100000U
1687 #define ADC_CSR_OVR3 0x00200000U
1689 /* Legacy defines */
1690 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1691 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1692 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1693 
1694 /******************* Bit definition for ADC_CCR register ********************/
1695 #define ADC_CCR_MULTI 0x0000001FU
1696 #define ADC_CCR_MULTI_0 0x00000001U
1697 #define ADC_CCR_MULTI_1 0x00000002U
1698 #define ADC_CCR_MULTI_2 0x00000004U
1699 #define ADC_CCR_MULTI_3 0x00000008U
1700 #define ADC_CCR_MULTI_4 0x00000010U
1701 #define ADC_CCR_DELAY 0x00000F00U
1702 #define ADC_CCR_DELAY_0 0x00000100U
1703 #define ADC_CCR_DELAY_1 0x00000200U
1704 #define ADC_CCR_DELAY_2 0x00000400U
1705 #define ADC_CCR_DELAY_3 0x00000800U
1706 #define ADC_CCR_DDS 0x00002000U
1707 #define ADC_CCR_DMA 0x0000C000U
1708 #define ADC_CCR_DMA_0 0x00004000U
1709 #define ADC_CCR_DMA_1 0x00008000U
1710 #define ADC_CCR_ADCPRE 0x00030000U
1711 #define ADC_CCR_ADCPRE_0 0x00010000U
1712 #define ADC_CCR_ADCPRE_1 0x00020000U
1713 #define ADC_CCR_VBATE 0x00400000U
1714 #define ADC_CCR_TSVREFE 0x00800000U
1716 /******************* Bit definition for ADC_CDR register ********************/
1717 #define ADC_CDR_DATA1 0x0000FFFFU
1718 #define ADC_CDR_DATA2 0xFFFF0000U
1720 /******************************************************************************/
1721 /* */
1722 /* Controller Area Network */
1723 /* */
1724 /******************************************************************************/
1726 /******************* Bit definition for CAN_MCR register ********************/
1727 #define CAN_MCR_INRQ 0x00000001U
1728 #define CAN_MCR_SLEEP 0x00000002U
1729 #define CAN_MCR_TXFP 0x00000004U
1730 #define CAN_MCR_RFLM 0x00000008U
1731 #define CAN_MCR_NART 0x00000010U
1732 #define CAN_MCR_AWUM 0x00000020U
1733 #define CAN_MCR_ABOM 0x00000040U
1734 #define CAN_MCR_TTCM 0x00000080U
1735 #define CAN_MCR_RESET 0x00008000U
1736 #define CAN_MCR_DBF 0x00010000U
1737 /******************* Bit definition for CAN_MSR register ********************/
1738 #define CAN_MSR_INAK 0x0001U
1739 #define CAN_MSR_SLAK 0x0002U
1740 #define CAN_MSR_ERRI 0x0004U
1741 #define CAN_MSR_WKUI 0x0008U
1742 #define CAN_MSR_SLAKI 0x0010U
1743 #define CAN_MSR_TXM 0x0100U
1744 #define CAN_MSR_RXM 0x0200U
1745 #define CAN_MSR_SAMP 0x0400U
1746 #define CAN_MSR_RX 0x0800U
1748 /******************* Bit definition for CAN_TSR register ********************/
1749 #define CAN_TSR_RQCP0 0x00000001U
1750 #define CAN_TSR_TXOK0 0x00000002U
1751 #define CAN_TSR_ALST0 0x00000004U
1752 #define CAN_TSR_TERR0 0x00000008U
1753 #define CAN_TSR_ABRQ0 0x00000080U
1754 #define CAN_TSR_RQCP1 0x00000100U
1755 #define CAN_TSR_TXOK1 0x00000200U
1756 #define CAN_TSR_ALST1 0x00000400U
1757 #define CAN_TSR_TERR1 0x00000800U
1758 #define CAN_TSR_ABRQ1 0x00008000U
1759 #define CAN_TSR_RQCP2 0x00010000U
1760 #define CAN_TSR_TXOK2 0x00020000U
1761 #define CAN_TSR_ALST2 0x00040000U
1762 #define CAN_TSR_TERR2 0x00080000U
1763 #define CAN_TSR_ABRQ2 0x00800000U
1764 #define CAN_TSR_CODE 0x03000000U
1766 #define CAN_TSR_TME 0x1C000000U
1767 #define CAN_TSR_TME0 0x04000000U
1768 #define CAN_TSR_TME1 0x08000000U
1769 #define CAN_TSR_TME2 0x10000000U
1771 #define CAN_TSR_LOW 0xE0000000U
1772 #define CAN_TSR_LOW0 0x20000000U
1773 #define CAN_TSR_LOW1 0x40000000U
1774 #define CAN_TSR_LOW2 0x80000000U
1776 /******************* Bit definition for CAN_RF0R register *******************/
1777 #define CAN_RF0R_FMP0 0x03U
1778 #define CAN_RF0R_FULL0 0x08U
1779 #define CAN_RF0R_FOVR0 0x10U
1780 #define CAN_RF0R_RFOM0 0x20U
1782 /******************* Bit definition for CAN_RF1R register *******************/
1783 #define CAN_RF1R_FMP1 0x03U
1784 #define CAN_RF1R_FULL1 0x08U
1785 #define CAN_RF1R_FOVR1 0x10U
1786 #define CAN_RF1R_RFOM1 0x20U
1788 /******************** Bit definition for CAN_IER register *******************/
1789 #define CAN_IER_TMEIE 0x00000001U
1790 #define CAN_IER_FMPIE0 0x00000002U
1791 #define CAN_IER_FFIE0 0x00000004U
1792 #define CAN_IER_FOVIE0 0x00000008U
1793 #define CAN_IER_FMPIE1 0x00000010U
1794 #define CAN_IER_FFIE1 0x00000020U
1795 #define CAN_IER_FOVIE1 0x00000040U
1796 #define CAN_IER_EWGIE 0x00000100U
1797 #define CAN_IER_EPVIE 0x00000200U
1798 #define CAN_IER_BOFIE 0x00000400U
1799 #define CAN_IER_LECIE 0x00000800U
1800 #define CAN_IER_ERRIE 0x00008000U
1801 #define CAN_IER_WKUIE 0x00010000U
1802 #define CAN_IER_SLKIE 0x00020000U
1803 #define CAN_IER_EWGIE 0x00000100U
1804 #define CAN_IER_EPVIE 0x00000200U
1805 #define CAN_IER_BOFIE 0x00000400U
1806 #define CAN_IER_LECIE 0x00000800U
1807 #define CAN_IER_ERRIE 0x00008000U
1810 /******************** Bit definition for CAN_ESR register *******************/
1811 #define CAN_ESR_EWGF 0x00000001U
1812 #define CAN_ESR_EPVF 0x00000002U
1813 #define CAN_ESR_BOFF 0x00000004U
1815 #define CAN_ESR_LEC 0x00000070U
1816 #define CAN_ESR_LEC_0 0x00000010U
1817 #define CAN_ESR_LEC_1 0x00000020U
1818 #define CAN_ESR_LEC_2 0x00000040U
1820 #define CAN_ESR_TEC 0x00FF0000U
1821 #define CAN_ESR_REC 0xFF000000U
1823 /******************* Bit definition for CAN_BTR register ********************/
1824 #define CAN_BTR_BRP 0x000003FFU
1825 #define CAN_BTR_TS1 0x000F0000U
1826 #define CAN_BTR_TS1_0 0x00010000U
1827 #define CAN_BTR_TS1_1 0x00020000U
1828 #define CAN_BTR_TS1_2 0x00040000U
1829 #define CAN_BTR_TS1_3 0x00080000U
1830 #define CAN_BTR_TS2 0x00700000U
1831 #define CAN_BTR_TS2_0 0x00100000U
1832 #define CAN_BTR_TS2_1 0x00200000U
1833 #define CAN_BTR_TS2_2 0x00400000U
1834 #define CAN_BTR_SJW 0x03000000U
1835 #define CAN_BTR_SJW_0 0x01000000U
1836 #define CAN_BTR_SJW_1 0x02000000U
1837 #define CAN_BTR_LBKM 0x40000000U
1838 #define CAN_BTR_SILM 0x80000000U
1842 /****************** Bit definition for CAN_TI0R register ********************/
1843 #define CAN_TI0R_TXRQ 0x00000001U
1844 #define CAN_TI0R_RTR 0x00000002U
1845 #define CAN_TI0R_IDE 0x00000004U
1846 #define CAN_TI0R_EXID 0x001FFFF8U
1847 #define CAN_TI0R_STID 0xFFE00000U
1849 /****************** Bit definition for CAN_TDT0R register *******************/
1850 #define CAN_TDT0R_DLC 0x0000000FU
1851 #define CAN_TDT0R_TGT 0x00000100U
1852 #define CAN_TDT0R_TIME 0xFFFF0000U
1854 /****************** Bit definition for CAN_TDL0R register *******************/
1855 #define CAN_TDL0R_DATA0 0x000000FFU
1856 #define CAN_TDL0R_DATA1 0x0000FF00U
1857 #define CAN_TDL0R_DATA2 0x00FF0000U
1858 #define CAN_TDL0R_DATA3 0xFF000000U
1860 /****************** Bit definition for CAN_TDH0R register *******************/
1861 #define CAN_TDH0R_DATA4 0x000000FFU
1862 #define CAN_TDH0R_DATA5 0x0000FF00U
1863 #define CAN_TDH0R_DATA6 0x00FF0000U
1864 #define CAN_TDH0R_DATA7 0xFF000000U
1866 /******************* Bit definition for CAN_TI1R register *******************/
1867 #define CAN_TI1R_TXRQ 0x00000001U
1868 #define CAN_TI1R_RTR 0x00000002U
1869 #define CAN_TI1R_IDE 0x00000004U
1870 #define CAN_TI1R_EXID 0x001FFFF8U
1871 #define CAN_TI1R_STID 0xFFE00000U
1873 /******************* Bit definition for CAN_TDT1R register ******************/
1874 #define CAN_TDT1R_DLC 0x0000000FU
1875 #define CAN_TDT1R_TGT 0x00000100U
1876 #define CAN_TDT1R_TIME 0xFFFF0000U
1878 /******************* Bit definition for CAN_TDL1R register ******************/
1879 #define CAN_TDL1R_DATA0 0x000000FFU
1880 #define CAN_TDL1R_DATA1 0x0000FF00U
1881 #define CAN_TDL1R_DATA2 0x00FF0000U
1882 #define CAN_TDL1R_DATA3 0xFF000000U
1884 /******************* Bit definition for CAN_TDH1R register ******************/
1885 #define CAN_TDH1R_DATA4 0x000000FFU
1886 #define CAN_TDH1R_DATA5 0x0000FF00U
1887 #define CAN_TDH1R_DATA6 0x00FF0000U
1888 #define CAN_TDH1R_DATA7 0xFF000000U
1890 /******************* Bit definition for CAN_TI2R register *******************/
1891 #define CAN_TI2R_TXRQ 0x00000001U
1892 #define CAN_TI2R_RTR 0x00000002U
1893 #define CAN_TI2R_IDE 0x00000004U
1894 #define CAN_TI2R_EXID 0x001FFFF8U
1895 #define CAN_TI2R_STID 0xFFE00000U
1897 /******************* Bit definition for CAN_TDT2R register ******************/
1898 #define CAN_TDT2R_DLC 0x0000000FU
1899 #define CAN_TDT2R_TGT 0x00000100U
1900 #define CAN_TDT2R_TIME 0xFFFF0000U
1902 /******************* Bit definition for CAN_TDL2R register ******************/
1903 #define CAN_TDL2R_DATA0 0x000000FFU
1904 #define CAN_TDL2R_DATA1 0x0000FF00U
1905 #define CAN_TDL2R_DATA2 0x00FF0000U
1906 #define CAN_TDL2R_DATA3 0xFF000000U
1908 /******************* Bit definition for CAN_TDH2R register ******************/
1909 #define CAN_TDH2R_DATA4 0x000000FFU
1910 #define CAN_TDH2R_DATA5 0x0000FF00U
1911 #define CAN_TDH2R_DATA6 0x00FF0000U
1912 #define CAN_TDH2R_DATA7 0xFF000000U
1914 /******************* Bit definition for CAN_RI0R register *******************/
1915 #define CAN_RI0R_RTR 0x00000002U
1916 #define CAN_RI0R_IDE 0x00000004U
1917 #define CAN_RI0R_EXID 0x001FFFF8U
1918 #define CAN_RI0R_STID 0xFFE00000U
1920 /******************* Bit definition for CAN_RDT0R register ******************/
1921 #define CAN_RDT0R_DLC 0x0000000FU
1922 #define CAN_RDT0R_FMI 0x0000FF00U
1923 #define CAN_RDT0R_TIME 0xFFFF0000U
1925 /******************* Bit definition for CAN_RDL0R register ******************/
1926 #define CAN_RDL0R_DATA0 0x000000FFU
1927 #define CAN_RDL0R_DATA1 0x0000FF00U
1928 #define CAN_RDL0R_DATA2 0x00FF0000U
1929 #define CAN_RDL0R_DATA3 0xFF000000U
1931 /******************* Bit definition for CAN_RDH0R register ******************/
1932 #define CAN_RDH0R_DATA4 0x000000FFU
1933 #define CAN_RDH0R_DATA5 0x0000FF00U
1934 #define CAN_RDH0R_DATA6 0x00FF0000U
1935 #define CAN_RDH0R_DATA7 0xFF000000U
1937 /******************* Bit definition for CAN_RI1R register *******************/
1938 #define CAN_RI1R_RTR 0x00000002U
1939 #define CAN_RI1R_IDE 0x00000004U
1940 #define CAN_RI1R_EXID 0x001FFFF8U
1941 #define CAN_RI1R_STID 0xFFE00000U
1943 /******************* Bit definition for CAN_RDT1R register ******************/
1944 #define CAN_RDT1R_DLC 0x0000000FU
1945 #define CAN_RDT1R_FMI 0x0000FF00U
1946 #define CAN_RDT1R_TIME 0xFFFF0000U
1948 /******************* Bit definition for CAN_RDL1R register ******************/
1949 #define CAN_RDL1R_DATA0 0x000000FFU
1950 #define CAN_RDL1R_DATA1 0x0000FF00U
1951 #define CAN_RDL1R_DATA2 0x00FF0000U
1952 #define CAN_RDL1R_DATA3 0xFF000000U
1954 /******************* Bit definition for CAN_RDH1R register ******************/
1955 #define CAN_RDH1R_DATA4 0x000000FFU
1956 #define CAN_RDH1R_DATA5 0x0000FF00U
1957 #define CAN_RDH1R_DATA6 0x00FF0000U
1958 #define CAN_RDH1R_DATA7 0xFF000000U
1961 /******************* Bit definition for CAN_FMR register ********************/
1962 #define CAN_FMR_FINIT 0x01U
1963 #define CAN_FMR_CAN2SB 0x00003F00U
1965 /******************* Bit definition for CAN_FM1R register *******************/
1966 #define CAN_FM1R_FBM 0x0FFFFFFFU
1967 #define CAN_FM1R_FBM0 0x00000001U
1968 #define CAN_FM1R_FBM1 0x00000002U
1969 #define CAN_FM1R_FBM2 0x00000004U
1970 #define CAN_FM1R_FBM3 0x00000008U
1971 #define CAN_FM1R_FBM4 0x00000010U
1972 #define CAN_FM1R_FBM5 0x00000020U
1973 #define CAN_FM1R_FBM6 0x00000040U
1974 #define CAN_FM1R_FBM7 0x00000080U
1975 #define CAN_FM1R_FBM8 0x00000100U
1976 #define CAN_FM1R_FBM9 0x00000200U
1977 #define CAN_FM1R_FBM10 0x00000400U
1978 #define CAN_FM1R_FBM11 0x00000800U
1979 #define CAN_FM1R_FBM12 0x00001000U
1980 #define CAN_FM1R_FBM13 0x00002000U
1981 #define CAN_FM1R_FBM14 0x00004000U
1982 #define CAN_FM1R_FBM15 0x00008000U
1983 #define CAN_FM1R_FBM16 0x00010000U
1984 #define CAN_FM1R_FBM17 0x00020000U
1985 #define CAN_FM1R_FBM18 0x00040000U
1986 #define CAN_FM1R_FBM19 0x00080000U
1987 #define CAN_FM1R_FBM20 0x00100000U
1988 #define CAN_FM1R_FBM21 0x00200000U
1989 #define CAN_FM1R_FBM22 0x00400000U
1990 #define CAN_FM1R_FBM23 0x00800000U
1991 #define CAN_FM1R_FBM24 0x01000000U
1992 #define CAN_FM1R_FBM25 0x02000000U
1993 #define CAN_FM1R_FBM26 0x04000000U
1994 #define CAN_FM1R_FBM27 0x08000000U
1996 /******************* Bit definition for CAN_FS1R register *******************/
1997 #define CAN_FS1R_FSC 0x0FFFFFFFU
1998 #define CAN_FS1R_FSC0 0x00000001U
1999 #define CAN_FS1R_FSC1 0x00000002U
2000 #define CAN_FS1R_FSC2 0x00000004U
2001 #define CAN_FS1R_FSC3 0x00000008U
2002 #define CAN_FS1R_FSC4 0x00000010U
2003 #define CAN_FS1R_FSC5 0x00000020U
2004 #define CAN_FS1R_FSC6 0x00000040U
2005 #define CAN_FS1R_FSC7 0x00000080U
2006 #define CAN_FS1R_FSC8 0x00000100U
2007 #define CAN_FS1R_FSC9 0x00000200U
2008 #define CAN_FS1R_FSC10 0x00000400U
2009 #define CAN_FS1R_FSC11 0x00000800U
2010 #define CAN_FS1R_FSC12 0x00001000U
2011 #define CAN_FS1R_FSC13 0x00002000U
2012 #define CAN_FS1R_FSC14 0x00004000U
2013 #define CAN_FS1R_FSC15 0x00008000U
2014 #define CAN_FS1R_FSC16 0x00010000U
2015 #define CAN_FS1R_FSC17 0x00020000U
2016 #define CAN_FS1R_FSC18 0x00040000U
2017 #define CAN_FS1R_FSC19 0x00080000U
2018 #define CAN_FS1R_FSC20 0x00100000U
2019 #define CAN_FS1R_FSC21 0x00200000U
2020 #define CAN_FS1R_FSC22 0x00400000U
2021 #define CAN_FS1R_FSC23 0x00800000U
2022 #define CAN_FS1R_FSC24 0x01000000U
2023 #define CAN_FS1R_FSC25 0x02000000U
2024 #define CAN_FS1R_FSC26 0x04000000U
2025 #define CAN_FS1R_FSC27 0x08000000U
2027 /****************** Bit definition for CAN_FFA1R register *******************/
2028 #define CAN_FFA1R_FFA 0x0FFFFFFFU
2029 #define CAN_FFA1R_FFA0 0x00000001U
2030 #define CAN_FFA1R_FFA1 0x00000002U
2031 #define CAN_FFA1R_FFA2 0x00000004U
2032 #define CAN_FFA1R_FFA3 0x00000008U
2033 #define CAN_FFA1R_FFA4 0x00000010U
2034 #define CAN_FFA1R_FFA5 0x00000020U
2035 #define CAN_FFA1R_FFA6 0x00000040U
2036 #define CAN_FFA1R_FFA7 0x00000080U
2037 #define CAN_FFA1R_FFA8 0x00000100U
2038 #define CAN_FFA1R_FFA9 0x00000200U
2039 #define CAN_FFA1R_FFA10 0x00000400U
2040 #define CAN_FFA1R_FFA11 0x00000800U
2041 #define CAN_FFA1R_FFA12 0x00001000U
2042 #define CAN_FFA1R_FFA13 0x00002000U
2043 #define CAN_FFA1R_FFA14 0x00004000U
2044 #define CAN_FFA1R_FFA15 0x00008000U
2045 #define CAN_FFA1R_FFA16 0x00010000U
2046 #define CAN_FFA1R_FFA17 0x00020000U
2047 #define CAN_FFA1R_FFA18 0x00040000U
2048 #define CAN_FFA1R_FFA19 0x00080000U
2049 #define CAN_FFA1R_FFA20 0x00100000U
2050 #define CAN_FFA1R_FFA21 0x00200000U
2051 #define CAN_FFA1R_FFA22 0x00400000U
2052 #define CAN_FFA1R_FFA23 0x00800000U
2053 #define CAN_FFA1R_FFA24 0x01000000U
2054 #define CAN_FFA1R_FFA25 0x02000000U
2055 #define CAN_FFA1R_FFA26 0x04000000U
2056 #define CAN_FFA1R_FFA27 0x08000000U
2058 /******************* Bit definition for CAN_FA1R register *******************/
2059 #define CAN_FA1R_FACT 0x0FFFFFFFU
2060 #define CAN_FA1R_FACT0 0x00000001U
2061 #define CAN_FA1R_FACT1 0x00000002U
2062 #define CAN_FA1R_FACT2 0x00000004U
2063 #define CAN_FA1R_FACT3 0x00000008U
2064 #define CAN_FA1R_FACT4 0x00000010U
2065 #define CAN_FA1R_FACT5 0x00000020U
2066 #define CAN_FA1R_FACT6 0x00000040U
2067 #define CAN_FA1R_FACT7 0x00000080U
2068 #define CAN_FA1R_FACT8 0x00000100U
2069 #define CAN_FA1R_FACT9 0x00000200U
2070 #define CAN_FA1R_FACT10 0x00000400U
2071 #define CAN_FA1R_FACT11 0x00000800U
2072 #define CAN_FA1R_FACT12 0x00001000U
2073 #define CAN_FA1R_FACT13 0x00002000U
2074 #define CAN_FA1R_FACT14 0x00004000U
2075 #define CAN_FA1R_FACT15 0x00008000U
2076 #define CAN_FA1R_FACT16 0x00010000U
2077 #define CAN_FA1R_FACT17 0x00020000U
2078 #define CAN_FA1R_FACT18 0x00040000U
2079 #define CAN_FA1R_FACT19 0x00080000U
2080 #define CAN_FA1R_FACT20 0x00100000U
2081 #define CAN_FA1R_FACT21 0x00200000U
2082 #define CAN_FA1R_FACT22 0x00400000U
2083 #define CAN_FA1R_FACT23 0x00800000U
2084 #define CAN_FA1R_FACT24 0x01000000U
2085 #define CAN_FA1R_FACT25 0x02000000U
2086 #define CAN_FA1R_FACT26 0x04000000U
2087 #define CAN_FA1R_FACT27 0x08000000U
2089 /******************* Bit definition for CAN_F0R1 register *******************/
2090 #define CAN_F0R1_FB0 0x00000001U
2091 #define CAN_F0R1_FB1 0x00000002U
2092 #define CAN_F0R1_FB2 0x00000004U
2093 #define CAN_F0R1_FB3 0x00000008U
2094 #define CAN_F0R1_FB4 0x00000010U
2095 #define CAN_F0R1_FB5 0x00000020U
2096 #define CAN_F0R1_FB6 0x00000040U
2097 #define CAN_F0R1_FB7 0x00000080U
2098 #define CAN_F0R1_FB8 0x00000100U
2099 #define CAN_F0R1_FB9 0x00000200U
2100 #define CAN_F0R1_FB10 0x00000400U
2101 #define CAN_F0R1_FB11 0x00000800U
2102 #define CAN_F0R1_FB12 0x00001000U
2103 #define CAN_F0R1_FB13 0x00002000U
2104 #define CAN_F0R1_FB14 0x00004000U
2105 #define CAN_F0R1_FB15 0x00008000U
2106 #define CAN_F0R1_FB16 0x00010000U
2107 #define CAN_F0R1_FB17 0x00020000U
2108 #define CAN_F0R1_FB18 0x00040000U
2109 #define CAN_F0R1_FB19 0x00080000U
2110 #define CAN_F0R1_FB20 0x00100000U
2111 #define CAN_F0R1_FB21 0x00200000U
2112 #define CAN_F0R1_FB22 0x00400000U
2113 #define CAN_F0R1_FB23 0x00800000U
2114 #define CAN_F0R1_FB24 0x01000000U
2115 #define CAN_F0R1_FB25 0x02000000U
2116 #define CAN_F0R1_FB26 0x04000000U
2117 #define CAN_F0R1_FB27 0x08000000U
2118 #define CAN_F0R1_FB28 0x10000000U
2119 #define CAN_F0R1_FB29 0x20000000U
2120 #define CAN_F0R1_FB30 0x40000000U
2121 #define CAN_F0R1_FB31 0x80000000U
2123 /******************* Bit definition for CAN_F1R1 register *******************/
2124 #define CAN_F1R1_FB0 0x00000001U
2125 #define CAN_F1R1_FB1 0x00000002U
2126 #define CAN_F1R1_FB2 0x00000004U
2127 #define CAN_F1R1_FB3 0x00000008U
2128 #define CAN_F1R1_FB4 0x00000010U
2129 #define CAN_F1R1_FB5 0x00000020U
2130 #define CAN_F1R1_FB6 0x00000040U
2131 #define CAN_F1R1_FB7 0x00000080U
2132 #define CAN_F1R1_FB8 0x00000100U
2133 #define CAN_F1R1_FB9 0x00000200U
2134 #define CAN_F1R1_FB10 0x00000400U
2135 #define CAN_F1R1_FB11 0x00000800U
2136 #define CAN_F1R1_FB12 0x00001000U
2137 #define CAN_F1R1_FB13 0x00002000U
2138 #define CAN_F1R1_FB14 0x00004000U
2139 #define CAN_F1R1_FB15 0x00008000U
2140 #define CAN_F1R1_FB16 0x00010000U
2141 #define CAN_F1R1_FB17 0x00020000U
2142 #define CAN_F1R1_FB18 0x00040000U
2143 #define CAN_F1R1_FB19 0x00080000U
2144 #define CAN_F1R1_FB20 0x00100000U
2145 #define CAN_F1R1_FB21 0x00200000U
2146 #define CAN_F1R1_FB22 0x00400000U
2147 #define CAN_F1R1_FB23 0x00800000U
2148 #define CAN_F1R1_FB24 0x01000000U
2149 #define CAN_F1R1_FB25 0x02000000U
2150 #define CAN_F1R1_FB26 0x04000000U
2151 #define CAN_F1R1_FB27 0x08000000U
2152 #define CAN_F1R1_FB28 0x10000000U
2153 #define CAN_F1R1_FB29 0x20000000U
2154 #define CAN_F1R1_FB30 0x40000000U
2155 #define CAN_F1R1_FB31 0x80000000U
2157 /******************* Bit definition for CAN_F2R1 register *******************/
2158 #define CAN_F2R1_FB0 0x00000001U
2159 #define CAN_F2R1_FB1 0x00000002U
2160 #define CAN_F2R1_FB2 0x00000004U
2161 #define CAN_F2R1_FB3 0x00000008U
2162 #define CAN_F2R1_FB4 0x00000010U
2163 #define CAN_F2R1_FB5 0x00000020U
2164 #define CAN_F2R1_FB6 0x00000040U
2165 #define CAN_F2R1_FB7 0x00000080U
2166 #define CAN_F2R1_FB8 0x00000100U
2167 #define CAN_F2R1_FB9 0x00000200U
2168 #define CAN_F2R1_FB10 0x00000400U
2169 #define CAN_F2R1_FB11 0x00000800U
2170 #define CAN_F2R1_FB12 0x00001000U
2171 #define CAN_F2R1_FB13 0x00002000U
2172 #define CAN_F2R1_FB14 0x00004000U
2173 #define CAN_F2R1_FB15 0x00008000U
2174 #define CAN_F2R1_FB16 0x00010000U
2175 #define CAN_F2R1_FB17 0x00020000U
2176 #define CAN_F2R1_FB18 0x00040000U
2177 #define CAN_F2R1_FB19 0x00080000U
2178 #define CAN_F2R1_FB20 0x00100000U
2179 #define CAN_F2R1_FB21 0x00200000U
2180 #define CAN_F2R1_FB22 0x00400000U
2181 #define CAN_F2R1_FB23 0x00800000U
2182 #define CAN_F2R1_FB24 0x01000000U
2183 #define CAN_F2R1_FB25 0x02000000U
2184 #define CAN_F2R1_FB26 0x04000000U
2185 #define CAN_F2R1_FB27 0x08000000U
2186 #define CAN_F2R1_FB28 0x10000000U
2187 #define CAN_F2R1_FB29 0x20000000U
2188 #define CAN_F2R1_FB30 0x40000000U
2189 #define CAN_F2R1_FB31 0x80000000U
2191 /******************* Bit definition for CAN_F3R1 register *******************/
2192 #define CAN_F3R1_FB0 0x00000001U
2193 #define CAN_F3R1_FB1 0x00000002U
2194 #define CAN_F3R1_FB2 0x00000004U
2195 #define CAN_F3R1_FB3 0x00000008U
2196 #define CAN_F3R1_FB4 0x00000010U
2197 #define CAN_F3R1_FB5 0x00000020U
2198 #define CAN_F3R1_FB6 0x00000040U
2199 #define CAN_F3R1_FB7 0x00000080U
2200 #define CAN_F3R1_FB8 0x00000100U
2201 #define CAN_F3R1_FB9 0x00000200U
2202 #define CAN_F3R1_FB10 0x00000400U
2203 #define CAN_F3R1_FB11 0x00000800U
2204 #define CAN_F3R1_FB12 0x00001000U
2205 #define CAN_F3R1_FB13 0x00002000U
2206 #define CAN_F3R1_FB14 0x00004000U
2207 #define CAN_F3R1_FB15 0x00008000U
2208 #define CAN_F3R1_FB16 0x00010000U
2209 #define CAN_F3R1_FB17 0x00020000U
2210 #define CAN_F3R1_FB18 0x00040000U
2211 #define CAN_F3R1_FB19 0x00080000U
2212 #define CAN_F3R1_FB20 0x00100000U
2213 #define CAN_F3R1_FB21 0x00200000U
2214 #define CAN_F3R1_FB22 0x00400000U
2215 #define CAN_F3R1_FB23 0x00800000U
2216 #define CAN_F3R1_FB24 0x01000000U
2217 #define CAN_F3R1_FB25 0x02000000U
2218 #define CAN_F3R1_FB26 0x04000000U
2219 #define CAN_F3R1_FB27 0x08000000U
2220 #define CAN_F3R1_FB28 0x10000000U
2221 #define CAN_F3R1_FB29 0x20000000U
2222 #define CAN_F3R1_FB30 0x40000000U
2223 #define CAN_F3R1_FB31 0x80000000U
2225 /******************* Bit definition for CAN_F4R1 register *******************/
2226 #define CAN_F4R1_FB0 0x00000001U
2227 #define CAN_F4R1_FB1 0x00000002U
2228 #define CAN_F4R1_FB2 0x00000004U
2229 #define CAN_F4R1_FB3 0x00000008U
2230 #define CAN_F4R1_FB4 0x00000010U
2231 #define CAN_F4R1_FB5 0x00000020U
2232 #define CAN_F4R1_FB6 0x00000040U
2233 #define CAN_F4R1_FB7 0x00000080U
2234 #define CAN_F4R1_FB8 0x00000100U
2235 #define CAN_F4R1_FB9 0x00000200U
2236 #define CAN_F4R1_FB10 0x00000400U
2237 #define CAN_F4R1_FB11 0x00000800U
2238 #define CAN_F4R1_FB12 0x00001000U
2239 #define CAN_F4R1_FB13 0x00002000U
2240 #define CAN_F4R1_FB14 0x00004000U
2241 #define CAN_F4R1_FB15 0x00008000U
2242 #define CAN_F4R1_FB16 0x00010000U
2243 #define CAN_F4R1_FB17 0x00020000U
2244 #define CAN_F4R1_FB18 0x00040000U
2245 #define CAN_F4R1_FB19 0x00080000U
2246 #define CAN_F4R1_FB20 0x00100000U
2247 #define CAN_F4R1_FB21 0x00200000U
2248 #define CAN_F4R1_FB22 0x00400000U
2249 #define CAN_F4R1_FB23 0x00800000U
2250 #define CAN_F4R1_FB24 0x01000000U
2251 #define CAN_F4R1_FB25 0x02000000U
2252 #define CAN_F4R1_FB26 0x04000000U
2253 #define CAN_F4R1_FB27 0x08000000U
2254 #define CAN_F4R1_FB28 0x10000000U
2255 #define CAN_F4R1_FB29 0x20000000U
2256 #define CAN_F4R1_FB30 0x40000000U
2257 #define CAN_F4R1_FB31 0x80000000U
2259 /******************* Bit definition for CAN_F5R1 register *******************/
2260 #define CAN_F5R1_FB0 0x00000001U
2261 #define CAN_F5R1_FB1 0x00000002U
2262 #define CAN_F5R1_FB2 0x00000004U
2263 #define CAN_F5R1_FB3 0x00000008U
2264 #define CAN_F5R1_FB4 0x00000010U
2265 #define CAN_F5R1_FB5 0x00000020U
2266 #define CAN_F5R1_FB6 0x00000040U
2267 #define CAN_F5R1_FB7 0x00000080U
2268 #define CAN_F5R1_FB8 0x00000100U
2269 #define CAN_F5R1_FB9 0x00000200U
2270 #define CAN_F5R1_FB10 0x00000400U
2271 #define CAN_F5R1_FB11 0x00000800U
2272 #define CAN_F5R1_FB12 0x00001000U
2273 #define CAN_F5R1_FB13 0x00002000U
2274 #define CAN_F5R1_FB14 0x00004000U
2275 #define CAN_F5R1_FB15 0x00008000U
2276 #define CAN_F5R1_FB16 0x00010000U
2277 #define CAN_F5R1_FB17 0x00020000U
2278 #define CAN_F5R1_FB18 0x00040000U
2279 #define CAN_F5R1_FB19 0x00080000U
2280 #define CAN_F5R1_FB20 0x00100000U
2281 #define CAN_F5R1_FB21 0x00200000U
2282 #define CAN_F5R1_FB22 0x00400000U
2283 #define CAN_F5R1_FB23 0x00800000U
2284 #define CAN_F5R1_FB24 0x01000000U
2285 #define CAN_F5R1_FB25 0x02000000U
2286 #define CAN_F5R1_FB26 0x04000000U
2287 #define CAN_F5R1_FB27 0x08000000U
2288 #define CAN_F5R1_FB28 0x10000000U
2289 #define CAN_F5R1_FB29 0x20000000U
2290 #define CAN_F5R1_FB30 0x40000000U
2291 #define CAN_F5R1_FB31 0x80000000U
2293 /******************* Bit definition for CAN_F6R1 register *******************/
2294 #define CAN_F6R1_FB0 0x00000001U
2295 #define CAN_F6R1_FB1 0x00000002U
2296 #define CAN_F6R1_FB2 0x00000004U
2297 #define CAN_F6R1_FB3 0x00000008U
2298 #define CAN_F6R1_FB4 0x00000010U
2299 #define CAN_F6R1_FB5 0x00000020U
2300 #define CAN_F6R1_FB6 0x00000040U
2301 #define CAN_F6R1_FB7 0x00000080U
2302 #define CAN_F6R1_FB8 0x00000100U
2303 #define CAN_F6R1_FB9 0x00000200U
2304 #define CAN_F6R1_FB10 0x00000400U
2305 #define CAN_F6R1_FB11 0x00000800U
2306 #define CAN_F6R1_FB12 0x00001000U
2307 #define CAN_F6R1_FB13 0x00002000U
2308 #define CAN_F6R1_FB14 0x00004000U
2309 #define CAN_F6R1_FB15 0x00008000U
2310 #define CAN_F6R1_FB16 0x00010000U
2311 #define CAN_F6R1_FB17 0x00020000U
2312 #define CAN_F6R1_FB18 0x00040000U
2313 #define CAN_F6R1_FB19 0x00080000U
2314 #define CAN_F6R1_FB20 0x00100000U
2315 #define CAN_F6R1_FB21 0x00200000U
2316 #define CAN_F6R1_FB22 0x00400000U
2317 #define CAN_F6R1_FB23 0x00800000U
2318 #define CAN_F6R1_FB24 0x01000000U
2319 #define CAN_F6R1_FB25 0x02000000U
2320 #define CAN_F6R1_FB26 0x04000000U
2321 #define CAN_F6R1_FB27 0x08000000U
2322 #define CAN_F6R1_FB28 0x10000000U
2323 #define CAN_F6R1_FB29 0x20000000U
2324 #define CAN_F6R1_FB30 0x40000000U
2325 #define CAN_F6R1_FB31 0x80000000U
2327 /******************* Bit definition for CAN_F7R1 register *******************/
2328 #define CAN_F7R1_FB0 0x00000001U
2329 #define CAN_F7R1_FB1 0x00000002U
2330 #define CAN_F7R1_FB2 0x00000004U
2331 #define CAN_F7R1_FB3 0x00000008U
2332 #define CAN_F7R1_FB4 0x00000010U
2333 #define CAN_F7R1_FB5 0x00000020U
2334 #define CAN_F7R1_FB6 0x00000040U
2335 #define CAN_F7R1_FB7 0x00000080U
2336 #define CAN_F7R1_FB8 0x00000100U
2337 #define CAN_F7R1_FB9 0x00000200U
2338 #define CAN_F7R1_FB10 0x00000400U
2339 #define CAN_F7R1_FB11 0x00000800U
2340 #define CAN_F7R1_FB12 0x00001000U
2341 #define CAN_F7R1_FB13 0x00002000U
2342 #define CAN_F7R1_FB14 0x00004000U
2343 #define CAN_F7R1_FB15 0x00008000U
2344 #define CAN_F7R1_FB16 0x00010000U
2345 #define CAN_F7R1_FB17 0x00020000U
2346 #define CAN_F7R1_FB18 0x00040000U
2347 #define CAN_F7R1_FB19 0x00080000U
2348 #define CAN_F7R1_FB20 0x00100000U
2349 #define CAN_F7R1_FB21 0x00200000U
2350 #define CAN_F7R1_FB22 0x00400000U
2351 #define CAN_F7R1_FB23 0x00800000U
2352 #define CAN_F7R1_FB24 0x01000000U
2353 #define CAN_F7R1_FB25 0x02000000U
2354 #define CAN_F7R1_FB26 0x04000000U
2355 #define CAN_F7R1_FB27 0x08000000U
2356 #define CAN_F7R1_FB28 0x10000000U
2357 #define CAN_F7R1_FB29 0x20000000U
2358 #define CAN_F7R1_FB30 0x40000000U
2359 #define CAN_F7R1_FB31 0x80000000U
2361 /******************* Bit definition for CAN_F8R1 register *******************/
2362 #define CAN_F8R1_FB0 0x00000001U
2363 #define CAN_F8R1_FB1 0x00000002U
2364 #define CAN_F8R1_FB2 0x00000004U
2365 #define CAN_F8R1_FB3 0x00000008U
2366 #define CAN_F8R1_FB4 0x00000010U
2367 #define CAN_F8R1_FB5 0x00000020U
2368 #define CAN_F8R1_FB6 0x00000040U
2369 #define CAN_F8R1_FB7 0x00000080U
2370 #define CAN_F8R1_FB8 0x00000100U
2371 #define CAN_F8R1_FB9 0x00000200U
2372 #define CAN_F8R1_FB10 0x00000400U
2373 #define CAN_F8R1_FB11 0x00000800U
2374 #define CAN_F8R1_FB12 0x00001000U
2375 #define CAN_F8R1_FB13 0x00002000U
2376 #define CAN_F8R1_FB14 0x00004000U
2377 #define CAN_F8R1_FB15 0x00008000U
2378 #define CAN_F8R1_FB16 0x00010000U
2379 #define CAN_F8R1_FB17 0x00020000U
2380 #define CAN_F8R1_FB18 0x00040000U
2381 #define CAN_F8R1_FB19 0x00080000U
2382 #define CAN_F8R1_FB20 0x00100000U
2383 #define CAN_F8R1_FB21 0x00200000U
2384 #define CAN_F8R1_FB22 0x00400000U
2385 #define CAN_F8R1_FB23 0x00800000U
2386 #define CAN_F8R1_FB24 0x01000000U
2387 #define CAN_F8R1_FB25 0x02000000U
2388 #define CAN_F8R1_FB26 0x04000000U
2389 #define CAN_F8R1_FB27 0x08000000U
2390 #define CAN_F8R1_FB28 0x10000000U
2391 #define CAN_F8R1_FB29 0x20000000U
2392 #define CAN_F8R1_FB30 0x40000000U
2393 #define CAN_F8R1_FB31 0x80000000U
2395 /******************* Bit definition for CAN_F9R1 register *******************/
2396 #define CAN_F9R1_FB0 0x00000001U
2397 #define CAN_F9R1_FB1 0x00000002U
2398 #define CAN_F9R1_FB2 0x00000004U
2399 #define CAN_F9R1_FB3 0x00000008U
2400 #define CAN_F9R1_FB4 0x00000010U
2401 #define CAN_F9R1_FB5 0x00000020U
2402 #define CAN_F9R1_FB6 0x00000040U
2403 #define CAN_F9R1_FB7 0x00000080U
2404 #define CAN_F9R1_FB8 0x00000100U
2405 #define CAN_F9R1_FB9 0x00000200U
2406 #define CAN_F9R1_FB10 0x00000400U
2407 #define CAN_F9R1_FB11 0x00000800U
2408 #define CAN_F9R1_FB12 0x00001000U
2409 #define CAN_F9R1_FB13 0x00002000U
2410 #define CAN_F9R1_FB14 0x00004000U
2411 #define CAN_F9R1_FB15 0x00008000U
2412 #define CAN_F9R1_FB16 0x00010000U
2413 #define CAN_F9R1_FB17 0x00020000U
2414 #define CAN_F9R1_FB18 0x00040000U
2415 #define CAN_F9R1_FB19 0x00080000U
2416 #define CAN_F9R1_FB20 0x00100000U
2417 #define CAN_F9R1_FB21 0x00200000U
2418 #define CAN_F9R1_FB22 0x00400000U
2419 #define CAN_F9R1_FB23 0x00800000U
2420 #define CAN_F9R1_FB24 0x01000000U
2421 #define CAN_F9R1_FB25 0x02000000U
2422 #define CAN_F9R1_FB26 0x04000000U
2423 #define CAN_F9R1_FB27 0x08000000U
2424 #define CAN_F9R1_FB28 0x10000000U
2425 #define CAN_F9R1_FB29 0x20000000U
2426 #define CAN_F9R1_FB30 0x40000000U
2427 #define CAN_F9R1_FB31 0x80000000U
2429 /******************* Bit definition for CAN_F10R1 register ******************/
2430 #define CAN_F10R1_FB0 0x00000001U
2431 #define CAN_F10R1_FB1 0x00000002U
2432 #define CAN_F10R1_FB2 0x00000004U
2433 #define CAN_F10R1_FB3 0x00000008U
2434 #define CAN_F10R1_FB4 0x00000010U
2435 #define CAN_F10R1_FB5 0x00000020U
2436 #define CAN_F10R1_FB6 0x00000040U
2437 #define CAN_F10R1_FB7 0x00000080U
2438 #define CAN_F10R1_FB8 0x00000100U
2439 #define CAN_F10R1_FB9 0x00000200U
2440 #define CAN_F10R1_FB10 0x00000400U
2441 #define CAN_F10R1_FB11 0x00000800U
2442 #define CAN_F10R1_FB12 0x00001000U
2443 #define CAN_F10R1_FB13 0x00002000U
2444 #define CAN_F10R1_FB14 0x00004000U
2445 #define CAN_F10R1_FB15 0x00008000U
2446 #define CAN_F10R1_FB16 0x00010000U
2447 #define CAN_F10R1_FB17 0x00020000U
2448 #define CAN_F10R1_FB18 0x00040000U
2449 #define CAN_F10R1_FB19 0x00080000U
2450 #define CAN_F10R1_FB20 0x00100000U
2451 #define CAN_F10R1_FB21 0x00200000U
2452 #define CAN_F10R1_FB22 0x00400000U
2453 #define CAN_F10R1_FB23 0x00800000U
2454 #define CAN_F10R1_FB24 0x01000000U
2455 #define CAN_F10R1_FB25 0x02000000U
2456 #define CAN_F10R1_FB26 0x04000000U
2457 #define CAN_F10R1_FB27 0x08000000U
2458 #define CAN_F10R1_FB28 0x10000000U
2459 #define CAN_F10R1_FB29 0x20000000U
2460 #define CAN_F10R1_FB30 0x40000000U
2461 #define CAN_F10R1_FB31 0x80000000U
2463 /******************* Bit definition for CAN_F11R1 register ******************/
2464 #define CAN_F11R1_FB0 0x00000001U
2465 #define CAN_F11R1_FB1 0x00000002U
2466 #define CAN_F11R1_FB2 0x00000004U
2467 #define CAN_F11R1_FB3 0x00000008U
2468 #define CAN_F11R1_FB4 0x00000010U
2469 #define CAN_F11R1_FB5 0x00000020U
2470 #define CAN_F11R1_FB6 0x00000040U
2471 #define CAN_F11R1_FB7 0x00000080U
2472 #define CAN_F11R1_FB8 0x00000100U
2473 #define CAN_F11R1_FB9 0x00000200U
2474 #define CAN_F11R1_FB10 0x00000400U
2475 #define CAN_F11R1_FB11 0x00000800U
2476 #define CAN_F11R1_FB12 0x00001000U
2477 #define CAN_F11R1_FB13 0x00002000U
2478 #define CAN_F11R1_FB14 0x00004000U
2479 #define CAN_F11R1_FB15 0x00008000U
2480 #define CAN_F11R1_FB16 0x00010000U
2481 #define CAN_F11R1_FB17 0x00020000U
2482 #define CAN_F11R1_FB18 0x00040000U
2483 #define CAN_F11R1_FB19 0x00080000U
2484 #define CAN_F11R1_FB20 0x00100000U
2485 #define CAN_F11R1_FB21 0x00200000U
2486 #define CAN_F11R1_FB22 0x00400000U
2487 #define CAN_F11R1_FB23 0x00800000U
2488 #define CAN_F11R1_FB24 0x01000000U
2489 #define CAN_F11R1_FB25 0x02000000U
2490 #define CAN_F11R1_FB26 0x04000000U
2491 #define CAN_F11R1_FB27 0x08000000U
2492 #define CAN_F11R1_FB28 0x10000000U
2493 #define CAN_F11R1_FB29 0x20000000U
2494 #define CAN_F11R1_FB30 0x40000000U
2495 #define CAN_F11R1_FB31 0x80000000U
2497 /******************* Bit definition for CAN_F12R1 register ******************/
2498 #define CAN_F12R1_FB0 0x00000001U
2499 #define CAN_F12R1_FB1 0x00000002U
2500 #define CAN_F12R1_FB2 0x00000004U
2501 #define CAN_F12R1_FB3 0x00000008U
2502 #define CAN_F12R1_FB4 0x00000010U
2503 #define CAN_F12R1_FB5 0x00000020U
2504 #define CAN_F12R1_FB6 0x00000040U
2505 #define CAN_F12R1_FB7 0x00000080U
2506 #define CAN_F12R1_FB8 0x00000100U
2507 #define CAN_F12R1_FB9 0x00000200U
2508 #define CAN_F12R1_FB10 0x00000400U
2509 #define CAN_F12R1_FB11 0x00000800U
2510 #define CAN_F12R1_FB12 0x00001000U
2511 #define CAN_F12R1_FB13 0x00002000U
2512 #define CAN_F12R1_FB14 0x00004000U
2513 #define CAN_F12R1_FB15 0x00008000U
2514 #define CAN_F12R1_FB16 0x00010000U
2515 #define CAN_F12R1_FB17 0x00020000U
2516 #define CAN_F12R1_FB18 0x00040000U
2517 #define CAN_F12R1_FB19 0x00080000U
2518 #define CAN_F12R1_FB20 0x00100000U
2519 #define CAN_F12R1_FB21 0x00200000U
2520 #define CAN_F12R1_FB22 0x00400000U
2521 #define CAN_F12R1_FB23 0x00800000U
2522 #define CAN_F12R1_FB24 0x01000000U
2523 #define CAN_F12R1_FB25 0x02000000U
2524 #define CAN_F12R1_FB26 0x04000000U
2525 #define CAN_F12R1_FB27 0x08000000U
2526 #define CAN_F12R1_FB28 0x10000000U
2527 #define CAN_F12R1_FB29 0x20000000U
2528 #define CAN_F12R1_FB30 0x40000000U
2529 #define CAN_F12R1_FB31 0x80000000U
2531 /******************* Bit definition for CAN_F13R1 register ******************/
2532 #define CAN_F13R1_FB0 0x00000001U
2533 #define CAN_F13R1_FB1 0x00000002U
2534 #define CAN_F13R1_FB2 0x00000004U
2535 #define CAN_F13R1_FB3 0x00000008U
2536 #define CAN_F13R1_FB4 0x00000010U
2537 #define CAN_F13R1_FB5 0x00000020U
2538 #define CAN_F13R1_FB6 0x00000040U
2539 #define CAN_F13R1_FB7 0x00000080U
2540 #define CAN_F13R1_FB8 0x00000100U
2541 #define CAN_F13R1_FB9 0x00000200U
2542 #define CAN_F13R1_FB10 0x00000400U
2543 #define CAN_F13R1_FB11 0x00000800U
2544 #define CAN_F13R1_FB12 0x00001000U
2545 #define CAN_F13R1_FB13 0x00002000U
2546 #define CAN_F13R1_FB14 0x00004000U
2547 #define CAN_F13R1_FB15 0x00008000U
2548 #define CAN_F13R1_FB16 0x00010000U
2549 #define CAN_F13R1_FB17 0x00020000U
2550 #define CAN_F13R1_FB18 0x00040000U
2551 #define CAN_F13R1_FB19 0x00080000U
2552 #define CAN_F13R1_FB20 0x00100000U
2553 #define CAN_F13R1_FB21 0x00200000U
2554 #define CAN_F13R1_FB22 0x00400000U
2555 #define CAN_F13R1_FB23 0x00800000U
2556 #define CAN_F13R1_FB24 0x01000000U
2557 #define CAN_F13R1_FB25 0x02000000U
2558 #define CAN_F13R1_FB26 0x04000000U
2559 #define CAN_F13R1_FB27 0x08000000U
2560 #define CAN_F13R1_FB28 0x10000000U
2561 #define CAN_F13R1_FB29 0x20000000U
2562 #define CAN_F13R1_FB30 0x40000000U
2563 #define CAN_F13R1_FB31 0x80000000U
2565 /******************* Bit definition for CAN_F0R2 register *******************/
2566 #define CAN_F0R2_FB0 0x00000001U
2567 #define CAN_F0R2_FB1 0x00000002U
2568 #define CAN_F0R2_FB2 0x00000004U
2569 #define CAN_F0R2_FB3 0x00000008U
2570 #define CAN_F0R2_FB4 0x00000010U
2571 #define CAN_F0R2_FB5 0x00000020U
2572 #define CAN_F0R2_FB6 0x00000040U
2573 #define CAN_F0R2_FB7 0x00000080U
2574 #define CAN_F0R2_FB8 0x00000100U
2575 #define CAN_F0R2_FB9 0x00000200U
2576 #define CAN_F0R2_FB10 0x00000400U
2577 #define CAN_F0R2_FB11 0x00000800U
2578 #define CAN_F0R2_FB12 0x00001000U
2579 #define CAN_F0R2_FB13 0x00002000U
2580 #define CAN_F0R2_FB14 0x00004000U
2581 #define CAN_F0R2_FB15 0x00008000U
2582 #define CAN_F0R2_FB16 0x00010000U
2583 #define CAN_F0R2_FB17 0x00020000U
2584 #define CAN_F0R2_FB18 0x00040000U
2585 #define CAN_F0R2_FB19 0x00080000U
2586 #define CAN_F0R2_FB20 0x00100000U
2587 #define CAN_F0R2_FB21 0x00200000U
2588 #define CAN_F0R2_FB22 0x00400000U
2589 #define CAN_F0R2_FB23 0x00800000U
2590 #define CAN_F0R2_FB24 0x01000000U
2591 #define CAN_F0R2_FB25 0x02000000U
2592 #define CAN_F0R2_FB26 0x04000000U
2593 #define CAN_F0R2_FB27 0x08000000U
2594 #define CAN_F0R2_FB28 0x10000000U
2595 #define CAN_F0R2_FB29 0x20000000U
2596 #define CAN_F0R2_FB30 0x40000000U
2597 #define CAN_F0R2_FB31 0x80000000U
2599 /******************* Bit definition for CAN_F1R2 register *******************/
2600 #define CAN_F1R2_FB0 0x00000001U
2601 #define CAN_F1R2_FB1 0x00000002U
2602 #define CAN_F1R2_FB2 0x00000004U
2603 #define CAN_F1R2_FB3 0x00000008U
2604 #define CAN_F1R2_FB4 0x00000010U
2605 #define CAN_F1R2_FB5 0x00000020U
2606 #define CAN_F1R2_FB6 0x00000040U
2607 #define CAN_F1R2_FB7 0x00000080U
2608 #define CAN_F1R2_FB8 0x00000100U
2609 #define CAN_F1R2_FB9 0x00000200U
2610 #define CAN_F1R2_FB10 0x00000400U
2611 #define CAN_F1R2_FB11 0x00000800U
2612 #define CAN_F1R2_FB12 0x00001000U
2613 #define CAN_F1R2_FB13 0x00002000U
2614 #define CAN_F1R2_FB14 0x00004000U
2615 #define CAN_F1R2_FB15 0x00008000U
2616 #define CAN_F1R2_FB16 0x00010000U
2617 #define CAN_F1R2_FB17 0x00020000U
2618 #define CAN_F1R2_FB18 0x00040000U
2619 #define CAN_F1R2_FB19 0x00080000U
2620 #define CAN_F1R2_FB20 0x00100000U
2621 #define CAN_F1R2_FB21 0x00200000U
2622 #define CAN_F1R2_FB22 0x00400000U
2623 #define CAN_F1R2_FB23 0x00800000U
2624 #define CAN_F1R2_FB24 0x01000000U
2625 #define CAN_F1R2_FB25 0x02000000U
2626 #define CAN_F1R2_FB26 0x04000000U
2627 #define CAN_F1R2_FB27 0x08000000U
2628 #define CAN_F1R2_FB28 0x10000000U
2629 #define CAN_F1R2_FB29 0x20000000U
2630 #define CAN_F1R2_FB30 0x40000000U
2631 #define CAN_F1R2_FB31 0x80000000U
2633 /******************* Bit definition for CAN_F2R2 register *******************/
2634 #define CAN_F2R2_FB0 0x00000001U
2635 #define CAN_F2R2_FB1 0x00000002U
2636 #define CAN_F2R2_FB2 0x00000004U
2637 #define CAN_F2R2_FB3 0x00000008U
2638 #define CAN_F2R2_FB4 0x00000010U
2639 #define CAN_F2R2_FB5 0x00000020U
2640 #define CAN_F2R2_FB6 0x00000040U
2641 #define CAN_F2R2_FB7 0x00000080U
2642 #define CAN_F2R2_FB8 0x00000100U
2643 #define CAN_F2R2_FB9 0x00000200U
2644 #define CAN_F2R2_FB10 0x00000400U
2645 #define CAN_F2R2_FB11 0x00000800U
2646 #define CAN_F2R2_FB12 0x00001000U
2647 #define CAN_F2R2_FB13 0x00002000U
2648 #define CAN_F2R2_FB14 0x00004000U
2649 #define CAN_F2R2_FB15 0x00008000U
2650 #define CAN_F2R2_FB16 0x00010000U
2651 #define CAN_F2R2_FB17 0x00020000U
2652 #define CAN_F2R2_FB18 0x00040000U
2653 #define CAN_F2R2_FB19 0x00080000U
2654 #define CAN_F2R2_FB20 0x00100000U
2655 #define CAN_F2R2_FB21 0x00200000U
2656 #define CAN_F2R2_FB22 0x00400000U
2657 #define CAN_F2R2_FB23 0x00800000U
2658 #define CAN_F2R2_FB24 0x01000000U
2659 #define CAN_F2R2_FB25 0x02000000U
2660 #define CAN_F2R2_FB26 0x04000000U
2661 #define CAN_F2R2_FB27 0x08000000U
2662 #define CAN_F2R2_FB28 0x10000000U
2663 #define CAN_F2R2_FB29 0x20000000U
2664 #define CAN_F2R2_FB30 0x40000000U
2665 #define CAN_F2R2_FB31 0x80000000U
2667 /******************* Bit definition for CAN_F3R2 register *******************/
2668 #define CAN_F3R2_FB0 0x00000001U
2669 #define CAN_F3R2_FB1 0x00000002U
2670 #define CAN_F3R2_FB2 0x00000004U
2671 #define CAN_F3R2_FB3 0x00000008U
2672 #define CAN_F3R2_FB4 0x00000010U
2673 #define CAN_F3R2_FB5 0x00000020U
2674 #define CAN_F3R2_FB6 0x00000040U
2675 #define CAN_F3R2_FB7 0x00000080U
2676 #define CAN_F3R2_FB8 0x00000100U
2677 #define CAN_F3R2_FB9 0x00000200U
2678 #define CAN_F3R2_FB10 0x00000400U
2679 #define CAN_F3R2_FB11 0x00000800U
2680 #define CAN_F3R2_FB12 0x00001000U
2681 #define CAN_F3R2_FB13 0x00002000U
2682 #define CAN_F3R2_FB14 0x00004000U
2683 #define CAN_F3R2_FB15 0x00008000U
2684 #define CAN_F3R2_FB16 0x00010000U
2685 #define CAN_F3R2_FB17 0x00020000U
2686 #define CAN_F3R2_FB18 0x00040000U
2687 #define CAN_F3R2_FB19 0x00080000U
2688 #define CAN_F3R2_FB20 0x00100000U
2689 #define CAN_F3R2_FB21 0x00200000U
2690 #define CAN_F3R2_FB22 0x00400000U
2691 #define CAN_F3R2_FB23 0x00800000U
2692 #define CAN_F3R2_FB24 0x01000000U
2693 #define CAN_F3R2_FB25 0x02000000U
2694 #define CAN_F3R2_FB26 0x04000000U
2695 #define CAN_F3R2_FB27 0x08000000U
2696 #define CAN_F3R2_FB28 0x10000000U
2697 #define CAN_F3R2_FB29 0x20000000U
2698 #define CAN_F3R2_FB30 0x40000000U
2699 #define CAN_F3R2_FB31 0x80000000U
2701 /******************* Bit definition for CAN_F4R2 register *******************/
2702 #define CAN_F4R2_FB0 0x00000001U
2703 #define CAN_F4R2_FB1 0x00000002U
2704 #define CAN_F4R2_FB2 0x00000004U
2705 #define CAN_F4R2_FB3 0x00000008U
2706 #define CAN_F4R2_FB4 0x00000010U
2707 #define CAN_F4R2_FB5 0x00000020U
2708 #define CAN_F4R2_FB6 0x00000040U
2709 #define CAN_F4R2_FB7 0x00000080U
2710 #define CAN_F4R2_FB8 0x00000100U
2711 #define CAN_F4R2_FB9 0x00000200U
2712 #define CAN_F4R2_FB10 0x00000400U
2713 #define CAN_F4R2_FB11 0x00000800U
2714 #define CAN_F4R2_FB12 0x00001000U
2715 #define CAN_F4R2_FB13 0x00002000U
2716 #define CAN_F4R2_FB14 0x00004000U
2717 #define CAN_F4R2_FB15 0x00008000U
2718 #define CAN_F4R2_FB16 0x00010000U
2719 #define CAN_F4R2_FB17 0x00020000U
2720 #define CAN_F4R2_FB18 0x00040000U
2721 #define CAN_F4R2_FB19 0x00080000U
2722 #define CAN_F4R2_FB20 0x00100000U
2723 #define CAN_F4R2_FB21 0x00200000U
2724 #define CAN_F4R2_FB22 0x00400000U
2725 #define CAN_F4R2_FB23 0x00800000U
2726 #define CAN_F4R2_FB24 0x01000000U
2727 #define CAN_F4R2_FB25 0x02000000U
2728 #define CAN_F4R2_FB26 0x04000000U
2729 #define CAN_F4R2_FB27 0x08000000U
2730 #define CAN_F4R2_FB28 0x10000000U
2731 #define CAN_F4R2_FB29 0x20000000U
2732 #define CAN_F4R2_FB30 0x40000000U
2733 #define CAN_F4R2_FB31 0x80000000U
2735 /******************* Bit definition for CAN_F5R2 register *******************/
2736 #define CAN_F5R2_FB0 0x00000001U
2737 #define CAN_F5R2_FB1 0x00000002U
2738 #define CAN_F5R2_FB2 0x00000004U
2739 #define CAN_F5R2_FB3 0x00000008U
2740 #define CAN_F5R2_FB4 0x00000010U
2741 #define CAN_F5R2_FB5 0x00000020U
2742 #define CAN_F5R2_FB6 0x00000040U
2743 #define CAN_F5R2_FB7 0x00000080U
2744 #define CAN_F5R2_FB8 0x00000100U
2745 #define CAN_F5R2_FB9 0x00000200U
2746 #define CAN_F5R2_FB10 0x00000400U
2747 #define CAN_F5R2_FB11 0x00000800U
2748 #define CAN_F5R2_FB12 0x00001000U
2749 #define CAN_F5R2_FB13 0x00002000U
2750 #define CAN_F5R2_FB14 0x00004000U
2751 #define CAN_F5R2_FB15 0x00008000U
2752 #define CAN_F5R2_FB16 0x00010000U
2753 #define CAN_F5R2_FB17 0x00020000U
2754 #define CAN_F5R2_FB18 0x00040000U
2755 #define CAN_F5R2_FB19 0x00080000U
2756 #define CAN_F5R2_FB20 0x00100000U
2757 #define CAN_F5R2_FB21 0x00200000U
2758 #define CAN_F5R2_FB22 0x00400000U
2759 #define CAN_F5R2_FB23 0x00800000U
2760 #define CAN_F5R2_FB24 0x01000000U
2761 #define CAN_F5R2_FB25 0x02000000U
2762 #define CAN_F5R2_FB26 0x04000000U
2763 #define CAN_F5R2_FB27 0x08000000U
2764 #define CAN_F5R2_FB28 0x10000000U
2765 #define CAN_F5R2_FB29 0x20000000U
2766 #define CAN_F5R2_FB30 0x40000000U
2767 #define CAN_F5R2_FB31 0x80000000U
2769 /******************* Bit definition for CAN_F6R2 register *******************/
2770 #define CAN_F6R2_FB0 0x00000001U
2771 #define CAN_F6R2_FB1 0x00000002U
2772 #define CAN_F6R2_FB2 0x00000004U
2773 #define CAN_F6R2_FB3 0x00000008U
2774 #define CAN_F6R2_FB4 0x00000010U
2775 #define CAN_F6R2_FB5 0x00000020U
2776 #define CAN_F6R2_FB6 0x00000040U
2777 #define CAN_F6R2_FB7 0x00000080U
2778 #define CAN_F6R2_FB8 0x00000100U
2779 #define CAN_F6R2_FB9 0x00000200U
2780 #define CAN_F6R2_FB10 0x00000400U
2781 #define CAN_F6R2_FB11 0x00000800U
2782 #define CAN_F6R2_FB12 0x00001000U
2783 #define CAN_F6R2_FB13 0x00002000U
2784 #define CAN_F6R2_FB14 0x00004000U
2785 #define CAN_F6R2_FB15 0x00008000U
2786 #define CAN_F6R2_FB16 0x00010000U
2787 #define CAN_F6R2_FB17 0x00020000U
2788 #define CAN_F6R2_FB18 0x00040000U
2789 #define CAN_F6R2_FB19 0x00080000U
2790 #define CAN_F6R2_FB20 0x00100000U
2791 #define CAN_F6R2_FB21 0x00200000U
2792 #define CAN_F6R2_FB22 0x00400000U
2793 #define CAN_F6R2_FB23 0x00800000U
2794 #define CAN_F6R2_FB24 0x01000000U
2795 #define CAN_F6R2_FB25 0x02000000U
2796 #define CAN_F6R2_FB26 0x04000000U
2797 #define CAN_F6R2_FB27 0x08000000U
2798 #define CAN_F6R2_FB28 0x10000000U
2799 #define CAN_F6R2_FB29 0x20000000U
2800 #define CAN_F6R2_FB30 0x40000000U
2801 #define CAN_F6R2_FB31 0x80000000U
2803 /******************* Bit definition for CAN_F7R2 register *******************/
2804 #define CAN_F7R2_FB0 0x00000001U
2805 #define CAN_F7R2_FB1 0x00000002U
2806 #define CAN_F7R2_FB2 0x00000004U
2807 #define CAN_F7R2_FB3 0x00000008U
2808 #define CAN_F7R2_FB4 0x00000010U
2809 #define CAN_F7R2_FB5 0x00000020U
2810 #define CAN_F7R2_FB6 0x00000040U
2811 #define CAN_F7R2_FB7 0x00000080U
2812 #define CAN_F7R2_FB8 0x00000100U
2813 #define CAN_F7R2_FB9 0x00000200U
2814 #define CAN_F7R2_FB10 0x00000400U
2815 #define CAN_F7R2_FB11 0x00000800U
2816 #define CAN_F7R2_FB12 0x00001000U
2817 #define CAN_F7R2_FB13 0x00002000U
2818 #define CAN_F7R2_FB14 0x00004000U
2819 #define CAN_F7R2_FB15 0x00008000U
2820 #define CAN_F7R2_FB16 0x00010000U
2821 #define CAN_F7R2_FB17 0x00020000U
2822 #define CAN_F7R2_FB18 0x00040000U
2823 #define CAN_F7R2_FB19 0x00080000U
2824 #define CAN_F7R2_FB20 0x00100000U
2825 #define CAN_F7R2_FB21 0x00200000U
2826 #define CAN_F7R2_FB22 0x00400000U
2827 #define CAN_F7R2_FB23 0x00800000U
2828 #define CAN_F7R2_FB24 0x01000000U
2829 #define CAN_F7R2_FB25 0x02000000U
2830 #define CAN_F7R2_FB26 0x04000000U
2831 #define CAN_F7R2_FB27 0x08000000U
2832 #define CAN_F7R2_FB28 0x10000000U
2833 #define CAN_F7R2_FB29 0x20000000U
2834 #define CAN_F7R2_FB30 0x40000000U
2835 #define CAN_F7R2_FB31 0x80000000U
2837 /******************* Bit definition for CAN_F8R2 register *******************/
2838 #define CAN_F8R2_FB0 0x00000001U
2839 #define CAN_F8R2_FB1 0x00000002U
2840 #define CAN_F8R2_FB2 0x00000004U
2841 #define CAN_F8R2_FB3 0x00000008U
2842 #define CAN_F8R2_FB4 0x00000010U
2843 #define CAN_F8R2_FB5 0x00000020U
2844 #define CAN_F8R2_FB6 0x00000040U
2845 #define CAN_F8R2_FB7 0x00000080U
2846 #define CAN_F8R2_FB8 0x00000100U
2847 #define CAN_F8R2_FB9 0x00000200U
2848 #define CAN_F8R2_FB10 0x00000400U
2849 #define CAN_F8R2_FB11 0x00000800U
2850 #define CAN_F8R2_FB12 0x00001000U
2851 #define CAN_F8R2_FB13 0x00002000U
2852 #define CAN_F8R2_FB14 0x00004000U
2853 #define CAN_F8R2_FB15 0x00008000U
2854 #define CAN_F8R2_FB16 0x00010000U
2855 #define CAN_F8R2_FB17 0x00020000U
2856 #define CAN_F8R2_FB18 0x00040000U
2857 #define CAN_F8R2_FB19 0x00080000U
2858 #define CAN_F8R2_FB20 0x00100000U
2859 #define CAN_F8R2_FB21 0x00200000U
2860 #define CAN_F8R2_FB22 0x00400000U
2861 #define CAN_F8R2_FB23 0x00800000U
2862 #define CAN_F8R2_FB24 0x01000000U
2863 #define CAN_F8R2_FB25 0x02000000U
2864 #define CAN_F8R2_FB26 0x04000000U
2865 #define CAN_F8R2_FB27 0x08000000U
2866 #define CAN_F8R2_FB28 0x10000000U
2867 #define CAN_F8R2_FB29 0x20000000U
2868 #define CAN_F8R2_FB30 0x40000000U
2869 #define CAN_F8R2_FB31 0x80000000U
2871 /******************* Bit definition for CAN_F9R2 register *******************/
2872 #define CAN_F9R2_FB0 0x00000001U
2873 #define CAN_F9R2_FB1 0x00000002U
2874 #define CAN_F9R2_FB2 0x00000004U
2875 #define CAN_F9R2_FB3 0x00000008U
2876 #define CAN_F9R2_FB4 0x00000010U
2877 #define CAN_F9R2_FB5 0x00000020U
2878 #define CAN_F9R2_FB6 0x00000040U
2879 #define CAN_F9R2_FB7 0x00000080U
2880 #define CAN_F9R2_FB8 0x00000100U
2881 #define CAN_F9R2_FB9 0x00000200U
2882 #define CAN_F9R2_FB10 0x00000400U
2883 #define CAN_F9R2_FB11 0x00000800U
2884 #define CAN_F9R2_FB12 0x00001000U
2885 #define CAN_F9R2_FB13 0x00002000U
2886 #define CAN_F9R2_FB14 0x00004000U
2887 #define CAN_F9R2_FB15 0x00008000U
2888 #define CAN_F9R2_FB16 0x00010000U
2889 #define CAN_F9R2_FB17 0x00020000U
2890 #define CAN_F9R2_FB18 0x00040000U
2891 #define CAN_F9R2_FB19 0x00080000U
2892 #define CAN_F9R2_FB20 0x00100000U
2893 #define CAN_F9R2_FB21 0x00200000U
2894 #define CAN_F9R2_FB22 0x00400000U
2895 #define CAN_F9R2_FB23 0x00800000U
2896 #define CAN_F9R2_FB24 0x01000000U
2897 #define CAN_F9R2_FB25 0x02000000U
2898 #define CAN_F9R2_FB26 0x04000000U
2899 #define CAN_F9R2_FB27 0x08000000U
2900 #define CAN_F9R2_FB28 0x10000000U
2901 #define CAN_F9R2_FB29 0x20000000U
2902 #define CAN_F9R2_FB30 0x40000000U
2903 #define CAN_F9R2_FB31 0x80000000U
2905 /******************* Bit definition for CAN_F10R2 register ******************/
2906 #define CAN_F10R2_FB0 0x00000001U
2907 #define CAN_F10R2_FB1 0x00000002U
2908 #define CAN_F10R2_FB2 0x00000004U
2909 #define CAN_F10R2_FB3 0x00000008U
2910 #define CAN_F10R2_FB4 0x00000010U
2911 #define CAN_F10R2_FB5 0x00000020U
2912 #define CAN_F10R2_FB6 0x00000040U
2913 #define CAN_F10R2_FB7 0x00000080U
2914 #define CAN_F10R2_FB8 0x00000100U
2915 #define CAN_F10R2_FB9 0x00000200U
2916 #define CAN_F10R2_FB10 0x00000400U
2917 #define CAN_F10R2_FB11 0x00000800U
2918 #define CAN_F10R2_FB12 0x00001000U
2919 #define CAN_F10R2_FB13 0x00002000U
2920 #define CAN_F10R2_FB14 0x00004000U
2921 #define CAN_F10R2_FB15 0x00008000U
2922 #define CAN_F10R2_FB16 0x00010000U
2923 #define CAN_F10R2_FB17 0x00020000U
2924 #define CAN_F10R2_FB18 0x00040000U
2925 #define CAN_F10R2_FB19 0x00080000U
2926 #define CAN_F10R2_FB20 0x00100000U
2927 #define CAN_F10R2_FB21 0x00200000U
2928 #define CAN_F10R2_FB22 0x00400000U
2929 #define CAN_F10R2_FB23 0x00800000U
2930 #define CAN_F10R2_FB24 0x01000000U
2931 #define CAN_F10R2_FB25 0x02000000U
2932 #define CAN_F10R2_FB26 0x04000000U
2933 #define CAN_F10R2_FB27 0x08000000U
2934 #define CAN_F10R2_FB28 0x10000000U
2935 #define CAN_F10R2_FB29 0x20000000U
2936 #define CAN_F10R2_FB30 0x40000000U
2937 #define CAN_F10R2_FB31 0x80000000U
2939 /******************* Bit definition for CAN_F11R2 register ******************/
2940 #define CAN_F11R2_FB0 0x00000001U
2941 #define CAN_F11R2_FB1 0x00000002U
2942 #define CAN_F11R2_FB2 0x00000004U
2943 #define CAN_F11R2_FB3 0x00000008U
2944 #define CAN_F11R2_FB4 0x00000010U
2945 #define CAN_F11R2_FB5 0x00000020U
2946 #define CAN_F11R2_FB6 0x00000040U
2947 #define CAN_F11R2_FB7 0x00000080U
2948 #define CAN_F11R2_FB8 0x00000100U
2949 #define CAN_F11R2_FB9 0x00000200U
2950 #define CAN_F11R2_FB10 0x00000400U
2951 #define CAN_F11R2_FB11 0x00000800U
2952 #define CAN_F11R2_FB12 0x00001000U
2953 #define CAN_F11R2_FB13 0x00002000U
2954 #define CAN_F11R2_FB14 0x00004000U
2955 #define CAN_F11R2_FB15 0x00008000U
2956 #define CAN_F11R2_FB16 0x00010000U
2957 #define CAN_F11R2_FB17 0x00020000U
2958 #define CAN_F11R2_FB18 0x00040000U
2959 #define CAN_F11R2_FB19 0x00080000U
2960 #define CAN_F11R2_FB20 0x00100000U
2961 #define CAN_F11R2_FB21 0x00200000U
2962 #define CAN_F11R2_FB22 0x00400000U
2963 #define CAN_F11R2_FB23 0x00800000U
2964 #define CAN_F11R2_FB24 0x01000000U
2965 #define CAN_F11R2_FB25 0x02000000U
2966 #define CAN_F11R2_FB26 0x04000000U
2967 #define CAN_F11R2_FB27 0x08000000U
2968 #define CAN_F11R2_FB28 0x10000000U
2969 #define CAN_F11R2_FB29 0x20000000U
2970 #define CAN_F11R2_FB30 0x40000000U
2971 #define CAN_F11R2_FB31 0x80000000U
2973 /******************* Bit definition for CAN_F12R2 register ******************/
2974 #define CAN_F12R2_FB0 0x00000001U
2975 #define CAN_F12R2_FB1 0x00000002U
2976 #define CAN_F12R2_FB2 0x00000004U
2977 #define CAN_F12R2_FB3 0x00000008U
2978 #define CAN_F12R2_FB4 0x00000010U
2979 #define CAN_F12R2_FB5 0x00000020U
2980 #define CAN_F12R2_FB6 0x00000040U
2981 #define CAN_F12R2_FB7 0x00000080U
2982 #define CAN_F12R2_FB8 0x00000100U
2983 #define CAN_F12R2_FB9 0x00000200U
2984 #define CAN_F12R2_FB10 0x00000400U
2985 #define CAN_F12R2_FB11 0x00000800U
2986 #define CAN_F12R2_FB12 0x00001000U
2987 #define CAN_F12R2_FB13 0x00002000U
2988 #define CAN_F12R2_FB14 0x00004000U
2989 #define CAN_F12R2_FB15 0x00008000U
2990 #define CAN_F12R2_FB16 0x00010000U
2991 #define CAN_F12R2_FB17 0x00020000U
2992 #define CAN_F12R2_FB18 0x00040000U
2993 #define CAN_F12R2_FB19 0x00080000U
2994 #define CAN_F12R2_FB20 0x00100000U
2995 #define CAN_F12R2_FB21 0x00200000U
2996 #define CAN_F12R2_FB22 0x00400000U
2997 #define CAN_F12R2_FB23 0x00800000U
2998 #define CAN_F12R2_FB24 0x01000000U
2999 #define CAN_F12R2_FB25 0x02000000U
3000 #define CAN_F12R2_FB26 0x04000000U
3001 #define CAN_F12R2_FB27 0x08000000U
3002 #define CAN_F12R2_FB28 0x10000000U
3003 #define CAN_F12R2_FB29 0x20000000U
3004 #define CAN_F12R2_FB30 0x40000000U
3005 #define CAN_F12R2_FB31 0x80000000U
3007 /******************* Bit definition for CAN_F13R2 register ******************/
3008 #define CAN_F13R2_FB0 0x00000001U
3009 #define CAN_F13R2_FB1 0x00000002U
3010 #define CAN_F13R2_FB2 0x00000004U
3011 #define CAN_F13R2_FB3 0x00000008U
3012 #define CAN_F13R2_FB4 0x00000010U
3013 #define CAN_F13R2_FB5 0x00000020U
3014 #define CAN_F13R2_FB6 0x00000040U
3015 #define CAN_F13R2_FB7 0x00000080U
3016 #define CAN_F13R2_FB8 0x00000100U
3017 #define CAN_F13R2_FB9 0x00000200U
3018 #define CAN_F13R2_FB10 0x00000400U
3019 #define CAN_F13R2_FB11 0x00000800U
3020 #define CAN_F13R2_FB12 0x00001000U
3021 #define CAN_F13R2_FB13 0x00002000U
3022 #define CAN_F13R2_FB14 0x00004000U
3023 #define CAN_F13R2_FB15 0x00008000U
3024 #define CAN_F13R2_FB16 0x00010000U
3025 #define CAN_F13R2_FB17 0x00020000U
3026 #define CAN_F13R2_FB18 0x00040000U
3027 #define CAN_F13R2_FB19 0x00080000U
3028 #define CAN_F13R2_FB20 0x00100000U
3029 #define CAN_F13R2_FB21 0x00200000U
3030 #define CAN_F13R2_FB22 0x00400000U
3031 #define CAN_F13R2_FB23 0x00800000U
3032 #define CAN_F13R2_FB24 0x01000000U
3033 #define CAN_F13R2_FB25 0x02000000U
3034 #define CAN_F13R2_FB26 0x04000000U
3035 #define CAN_F13R2_FB27 0x08000000U
3036 #define CAN_F13R2_FB28 0x10000000U
3037 #define CAN_F13R2_FB29 0x20000000U
3038 #define CAN_F13R2_FB30 0x40000000U
3039 #define CAN_F13R2_FB31 0x80000000U
3041 /******************************************************************************/
3042 /* */
3043 /* CRC calculation unit */
3044 /* */
3045 /******************************************************************************/
3046 /******************* Bit definition for CRC_DR register *********************/
3047 #define CRC_DR_DR 0xFFFFFFFFU
3050 /******************* Bit definition for CRC_IDR register ********************/
3051 #define CRC_IDR_IDR 0xFFU
3054 /******************** Bit definition for CRC_CR register ********************/
3055 #define CRC_CR_RESET 0x01U
3057 /******************************************************************************/
3058 /* */
3059 /* Crypto Processor */
3060 /* */
3061 /******************************************************************************/
3062 /******************* Bits definition for CRYP_CR register ********************/
3063 #define CRYP_CR_ALGODIR 0x00000004U
3064 
3065 #define CRYP_CR_ALGOMODE 0x00080038U
3066 #define CRYP_CR_ALGOMODE_0 0x00000008U
3067 #define CRYP_CR_ALGOMODE_1 0x00000010U
3068 #define CRYP_CR_ALGOMODE_2 0x00000020U
3069 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
3070 #define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
3071 #define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
3072 #define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
3073 #define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
3074 #define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
3075 #define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
3076 #define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
3077 
3078 #define CRYP_CR_DATATYPE 0x000000C0U
3079 #define CRYP_CR_DATATYPE_0 0x00000040U
3080 #define CRYP_CR_DATATYPE_1 0x00000080U
3081 #define CRYP_CR_KEYSIZE 0x00000300U
3082 #define CRYP_CR_KEYSIZE_0 0x00000100U
3083 #define CRYP_CR_KEYSIZE_1 0x00000200U
3084 #define CRYP_CR_FFLUSH 0x00004000U
3085 #define CRYP_CR_CRYPEN 0x00008000U
3086 
3087 #define CRYP_CR_GCM_CCMPH 0x00030000U
3088 #define CRYP_CR_GCM_CCMPH_0 0x00010000U
3089 #define CRYP_CR_GCM_CCMPH_1 0x00020000U
3090 #define CRYP_CR_ALGOMODE_3 0x00080000U
3091 
3092 /****************** Bits definition for CRYP_SR register *********************/
3093 #define CRYP_SR_IFEM 0x00000001U
3094 #define CRYP_SR_IFNF 0x00000002U
3095 #define CRYP_SR_OFNE 0x00000004U
3096 #define CRYP_SR_OFFU 0x00000008U
3097 #define CRYP_SR_BUSY 0x00000010U
3098 /****************** Bits definition for CRYP_DMACR register ******************/
3099 #define CRYP_DMACR_DIEN 0x00000001U
3100 #define CRYP_DMACR_DOEN 0x00000002U
3101 /***************** Bits definition for CRYP_IMSCR register ******************/
3102 #define CRYP_IMSCR_INIM 0x00000001U
3103 #define CRYP_IMSCR_OUTIM 0x00000002U
3104 /****************** Bits definition for CRYP_RISR register *******************/
3105 #define CRYP_RISR_OUTRIS 0x00000001U
3106 #define CRYP_RISR_INRIS 0x00000002U
3107 /****************** Bits definition for CRYP_MISR register *******************/
3108 #define CRYP_MISR_INMIS 0x00000001U
3109 #define CRYP_MISR_OUTMIS 0x00000002U
3110 
3111 /******************************************************************************/
3112 /* */
3113 /* Digital to Analog Converter */
3114 /* */
3115 /******************************************************************************/
3116 /******************** Bit definition for DAC_CR register ********************/
3117 #define DAC_CR_EN1 0x00000001U
3118 #define DAC_CR_BOFF1 0x00000002U
3119 #define DAC_CR_TEN1 0x00000004U
3121 #define DAC_CR_TSEL1 0x00000038U
3122 #define DAC_CR_TSEL1_0 0x00000008U
3123 #define DAC_CR_TSEL1_1 0x00000010U
3124 #define DAC_CR_TSEL1_2 0x00000020U
3126 #define DAC_CR_WAVE1 0x000000C0U
3127 #define DAC_CR_WAVE1_0 0x00000040U
3128 #define DAC_CR_WAVE1_1 0x00000080U
3130 #define DAC_CR_MAMP1 0x00000F00U
3131 #define DAC_CR_MAMP1_0 0x00000100U
3132 #define DAC_CR_MAMP1_1 0x00000200U
3133 #define DAC_CR_MAMP1_2 0x00000400U
3134 #define DAC_CR_MAMP1_3 0x00000800U
3136 #define DAC_CR_DMAEN1 0x00001000U
3137 #define DAC_CR_DMAUDRIE1 0x00002000U
3138 #define DAC_CR_EN2 0x00010000U
3139 #define DAC_CR_BOFF2 0x00020000U
3140 #define DAC_CR_TEN2 0x00040000U
3142 #define DAC_CR_TSEL2 0x00380000U
3143 #define DAC_CR_TSEL2_0 0x00080000U
3144 #define DAC_CR_TSEL2_1 0x00100000U
3145 #define DAC_CR_TSEL2_2 0x00200000U
3147 #define DAC_CR_WAVE2 0x00C00000U
3148 #define DAC_CR_WAVE2_0 0x00400000U
3149 #define DAC_CR_WAVE2_1 0x00800000U
3151 #define DAC_CR_MAMP2 0x0F000000U
3152 #define DAC_CR_MAMP2_0 0x01000000U
3153 #define DAC_CR_MAMP2_1 0x02000000U
3154 #define DAC_CR_MAMP2_2 0x04000000U
3155 #define DAC_CR_MAMP2_3 0x08000000U
3157 #define DAC_CR_DMAEN2 0x10000000U
3158 #define DAC_CR_DMAUDRIE2 0x20000000U
3160 /***************** Bit definition for DAC_SWTRIGR register ******************/
3161 #define DAC_SWTRIGR_SWTRIG1 0x01U
3162 #define DAC_SWTRIGR_SWTRIG2 0x02U
3164 /***************** Bit definition for DAC_DHR12R1 register ******************/
3165 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3167 /***************** Bit definition for DAC_DHR12L1 register ******************/
3168 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3170 /****************** Bit definition for DAC_DHR8R1 register ******************/
3171 #define DAC_DHR8R1_DACC1DHR 0xFFU
3173 /***************** Bit definition for DAC_DHR12R2 register ******************/
3174 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3176 /***************** Bit definition for DAC_DHR12L2 register ******************/
3177 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3179 /****************** Bit definition for DAC_DHR8R2 register ******************/
3180 #define DAC_DHR8R2_DACC2DHR 0xFFU
3182 /***************** Bit definition for DAC_DHR12RD register ******************/
3183 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3184 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3186 /***************** Bit definition for DAC_DHR12LD register ******************/
3187 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3188 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3190 /****************** Bit definition for DAC_DHR8RD register ******************/
3191 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3192 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3194 /******************* Bit definition for DAC_DOR1 register *******************/
3195 #define DAC_DOR1_DACC1DOR 0x0FFFU
3197 /******************* Bit definition for DAC_DOR2 register *******************/
3198 #define DAC_DOR2_DACC2DOR 0x0FFFU
3200 /******************** Bit definition for DAC_SR register ********************/
3201 #define DAC_SR_DMAUDR1 0x00002000U
3202 #define DAC_SR_DMAUDR2 0x20000000U
3204 /******************************************************************************/
3205 /* */
3206 /* Debug MCU */
3207 /* */
3208 /******************************************************************************/
3209 
3210 /******************************************************************************/
3211 /* */
3212 /* DCMI */
3213 /* */
3214 /******************************************************************************/
3215 /******************** Bits definition for DCMI_CR register ******************/
3216 #define DCMI_CR_CAPTURE 0x00000001U
3217 #define DCMI_CR_CM 0x00000002U
3218 #define DCMI_CR_CROP 0x00000004U
3219 #define DCMI_CR_JPEG 0x00000008U
3220 #define DCMI_CR_ESS 0x00000010U
3221 #define DCMI_CR_PCKPOL 0x00000020U
3222 #define DCMI_CR_HSPOL 0x00000040U
3223 #define DCMI_CR_VSPOL 0x00000080U
3224 #define DCMI_CR_FCRC_0 0x00000100U
3225 #define DCMI_CR_FCRC_1 0x00000200U
3226 #define DCMI_CR_EDM_0 0x00000400U
3227 #define DCMI_CR_EDM_1 0x00000800U
3228 #define DCMI_CR_CRE 0x00001000U
3229 #define DCMI_CR_ENABLE 0x00004000U
3230 
3231 /******************** Bits definition for DCMI_SR register ******************/
3232 #define DCMI_SR_HSYNC 0x00000001U
3233 #define DCMI_SR_VSYNC 0x00000002U
3234 #define DCMI_SR_FNE 0x00000004U
3235 
3236 /******************** Bits definition for DCMI_RIS register *****************/
3237 #define DCMI_RIS_FRAME_RIS 0x00000001U
3238 #define DCMI_RIS_OVR_RIS 0x00000002U
3239 #define DCMI_RIS_ERR_RIS 0x00000004U
3240 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3241 #define DCMI_RIS_LINE_RIS 0x00000010U
3242 /* Legacy defines */
3243 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3244 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
3245 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3246 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3247 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3248 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3249 
3250 /******************** Bits definition for DCMI_IER register *****************/
3251 #define DCMI_IER_FRAME_IE 0x00000001U
3252 #define DCMI_IER_OVR_IE 0x00000002U
3253 #define DCMI_IER_ERR_IE 0x00000004U
3254 #define DCMI_IER_VSYNC_IE 0x00000008U
3255 #define DCMI_IER_LINE_IE 0x00000010U
3256 /* Legacy defines */
3257 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3258 
3259 /******************** Bits definition for DCMI_MIS register *****************/
3260 #define DCMI_MIS_FRAME_MIS 0x00000001U
3261 #define DCMI_MIS_OVR_MIS 0x00000002U
3262 #define DCMI_MIS_ERR_MIS 0x00000004U
3263 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3264 #define DCMI_MIS_LINE_MIS 0x00000010U
3265 
3266 /* Legacy defines */
3267 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3268 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3269 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3270 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3271 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3272 
3273 /******************** Bits definition for DCMI_ICR register *****************/
3274 #define DCMI_ICR_FRAME_ISC 0x00000001U
3275 #define DCMI_ICR_OVR_ISC 0x00000002U
3276 #define DCMI_ICR_ERR_ISC 0x00000004U
3277 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3278 #define DCMI_ICR_LINE_ISC 0x00000010U
3279 
3280 /* Legacy defines */
3281 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3282 
3283 /******************** Bits definition for DCMI_ESCR register ******************/
3284 #define DCMI_ESCR_FSC 0x000000FFU
3285 #define DCMI_ESCR_LSC 0x0000FF00U
3286 #define DCMI_ESCR_LEC 0x00FF0000U
3287 #define DCMI_ESCR_FEC 0xFF000000U
3288 
3289 /******************** Bits definition for DCMI_ESUR register ******************/
3290 #define DCMI_ESUR_FSU 0x000000FFU
3291 #define DCMI_ESUR_LSU 0x0000FF00U
3292 #define DCMI_ESUR_LEU 0x00FF0000U
3293 #define DCMI_ESUR_FEU 0xFF000000U
3294 
3295 /******************** Bits definition for DCMI_CWSTRT register ******************/
3296 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3297 #define DCMI_CWSTRT_VST 0x1FFF0000U
3298 
3299 /******************** Bits definition for DCMI_CWSIZE register ******************/
3300 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3301 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3302 
3303 /******************** Bits definition for DCMI_DR register ******************/
3304 #define DCMI_DR_BYTE0 0x000000FFU
3305 #define DCMI_DR_BYTE1 0x0000FF00U
3306 #define DCMI_DR_BYTE2 0x00FF0000U
3307 #define DCMI_DR_BYTE3 0xFF000000U
3308 
3309 /******************************************************************************/
3310 /* */
3311 /* DMA Controller */
3312 /* */
3313 /******************************************************************************/
3314 /******************** Bits definition for DMA_SxCR register *****************/
3315 #define DMA_SxCR_CHSEL 0x0E000000U
3316 #define DMA_SxCR_CHSEL_0 0x02000000U
3317 #define DMA_SxCR_CHSEL_1 0x04000000U
3318 #define DMA_SxCR_CHSEL_2 0x08000000U
3319 #define DMA_SxCR_MBURST 0x01800000U
3320 #define DMA_SxCR_MBURST_0 0x00800000U
3321 #define DMA_SxCR_MBURST_1 0x01000000U
3322 #define DMA_SxCR_PBURST 0x00600000U
3323 #define DMA_SxCR_PBURST_0 0x00200000U
3324 #define DMA_SxCR_PBURST_1 0x00400000U
3325 #define DMA_SxCR_CT 0x00080000U
3326 #define DMA_SxCR_DBM 0x00040000U
3327 #define DMA_SxCR_PL 0x00030000U
3328 #define DMA_SxCR_PL_0 0x00010000U
3329 #define DMA_SxCR_PL_1 0x00020000U
3330 #define DMA_SxCR_PINCOS 0x00008000U
3331 #define DMA_SxCR_MSIZE 0x00006000U
3332 #define DMA_SxCR_MSIZE_0 0x00002000U
3333 #define DMA_SxCR_MSIZE_1 0x00004000U
3334 #define DMA_SxCR_PSIZE 0x00001800U
3335 #define DMA_SxCR_PSIZE_0 0x00000800U
3336 #define DMA_SxCR_PSIZE_1 0x00001000U
3337 #define DMA_SxCR_MINC 0x00000400U
3338 #define DMA_SxCR_PINC 0x00000200U
3339 #define DMA_SxCR_CIRC 0x00000100U
3340 #define DMA_SxCR_DIR 0x000000C0U
3341 #define DMA_SxCR_DIR_0 0x00000040U
3342 #define DMA_SxCR_DIR_1 0x00000080U
3343 #define DMA_SxCR_PFCTRL 0x00000020U
3344 #define DMA_SxCR_TCIE 0x00000010U
3345 #define DMA_SxCR_HTIE 0x00000008U
3346 #define DMA_SxCR_TEIE 0x00000004U
3347 #define DMA_SxCR_DMEIE 0x00000002U
3348 #define DMA_SxCR_EN 0x00000001U
3349 
3350 /* Legacy defines */
3351 #define DMA_SxCR_ACK 0x00100000U
3352 
3353 /******************** Bits definition for DMA_SxCNDTR register **************/
3354 #define DMA_SxNDT 0x0000FFFFU
3355 #define DMA_SxNDT_0 0x00000001U
3356 #define DMA_SxNDT_1 0x00000002U
3357 #define DMA_SxNDT_2 0x00000004U
3358 #define DMA_SxNDT_3 0x00000008U
3359 #define DMA_SxNDT_4 0x00000010U
3360 #define DMA_SxNDT_5 0x00000020U
3361 #define DMA_SxNDT_6 0x00000040U
3362 #define DMA_SxNDT_7 0x00000080U
3363 #define DMA_SxNDT_8 0x00000100U
3364 #define DMA_SxNDT_9 0x00000200U
3365 #define DMA_SxNDT_10 0x00000400U
3366 #define DMA_SxNDT_11 0x00000800U
3367 #define DMA_SxNDT_12 0x00001000U
3368 #define DMA_SxNDT_13 0x00002000U
3369 #define DMA_SxNDT_14 0x00004000U
3370 #define DMA_SxNDT_15 0x00008000U
3371 
3372 /******************** Bits definition for DMA_SxFCR register ****************/
3373 #define DMA_SxFCR_FEIE 0x00000080U
3374 #define DMA_SxFCR_FS 0x00000038U
3375 #define DMA_SxFCR_FS_0 0x00000008U
3376 #define DMA_SxFCR_FS_1 0x00000010U
3377 #define DMA_SxFCR_FS_2 0x00000020U
3378 #define DMA_SxFCR_DMDIS 0x00000004U
3379 #define DMA_SxFCR_FTH 0x00000003U
3380 #define DMA_SxFCR_FTH_0 0x00000001U
3381 #define DMA_SxFCR_FTH_1 0x00000002U
3382 
3383 /******************** Bits definition for DMA_LISR register *****************/
3384 #define DMA_LISR_TCIF3 0x08000000U
3385 #define DMA_LISR_HTIF3 0x04000000U
3386 #define DMA_LISR_TEIF3 0x02000000U
3387 #define DMA_LISR_DMEIF3 0x01000000U
3388 #define DMA_LISR_FEIF3 0x00400000U
3389 #define DMA_LISR_TCIF2 0x00200000U
3390 #define DMA_LISR_HTIF2 0x00100000U
3391 #define DMA_LISR_TEIF2 0x00080000U
3392 #define DMA_LISR_DMEIF2 0x00040000U
3393 #define DMA_LISR_FEIF2 0x00010000U
3394 #define DMA_LISR_TCIF1 0x00000800U
3395 #define DMA_LISR_HTIF1 0x00000400U
3396 #define DMA_LISR_TEIF1 0x00000200U
3397 #define DMA_LISR_DMEIF1 0x00000100U
3398 #define DMA_LISR_FEIF1 0x00000040U
3399 #define DMA_LISR_TCIF0 0x00000020U
3400 #define DMA_LISR_HTIF0 0x00000010U
3401 #define DMA_LISR_TEIF0 0x00000008U
3402 #define DMA_LISR_DMEIF0 0x00000004U
3403 #define DMA_LISR_FEIF0 0x00000001U
3404 
3405 /******************** Bits definition for DMA_HISR register *****************/
3406 #define DMA_HISR_TCIF7 0x08000000U
3407 #define DMA_HISR_HTIF7 0x04000000U
3408 #define DMA_HISR_TEIF7 0x02000000U
3409 #define DMA_HISR_DMEIF7 0x01000000U
3410 #define DMA_HISR_FEIF7 0x00400000U
3411 #define DMA_HISR_TCIF6 0x00200000U
3412 #define DMA_HISR_HTIF6 0x00100000U
3413 #define DMA_HISR_TEIF6 0x00080000U
3414 #define DMA_HISR_DMEIF6 0x00040000U
3415 #define DMA_HISR_FEIF6 0x00010000U
3416 #define DMA_HISR_TCIF5 0x00000800U
3417 #define DMA_HISR_HTIF5 0x00000400U
3418 #define DMA_HISR_TEIF5 0x00000200U
3419 #define DMA_HISR_DMEIF5 0x00000100U
3420 #define DMA_HISR_FEIF5 0x00000040U
3421 #define DMA_HISR_TCIF4 0x00000020U
3422 #define DMA_HISR_HTIF4 0x00000010U
3423 #define DMA_HISR_TEIF4 0x00000008U
3424 #define DMA_HISR_DMEIF4 0x00000004U
3425 #define DMA_HISR_FEIF4 0x00000001U
3426 
3427 /******************** Bits definition for DMA_LIFCR register ****************/
3428 #define DMA_LIFCR_CTCIF3 0x08000000U
3429 #define DMA_LIFCR_CHTIF3 0x04000000U
3430 #define DMA_LIFCR_CTEIF3 0x02000000U
3431 #define DMA_LIFCR_CDMEIF3 0x01000000U
3432 #define DMA_LIFCR_CFEIF3 0x00400000U
3433 #define DMA_LIFCR_CTCIF2 0x00200000U
3434 #define DMA_LIFCR_CHTIF2 0x00100000U
3435 #define DMA_LIFCR_CTEIF2 0x00080000U
3436 #define DMA_LIFCR_CDMEIF2 0x00040000U
3437 #define DMA_LIFCR_CFEIF2 0x00010000U
3438 #define DMA_LIFCR_CTCIF1 0x00000800U
3439 #define DMA_LIFCR_CHTIF1 0x00000400U
3440 #define DMA_LIFCR_CTEIF1 0x00000200U
3441 #define DMA_LIFCR_CDMEIF1 0x00000100U
3442 #define DMA_LIFCR_CFEIF1 0x00000040U
3443 #define DMA_LIFCR_CTCIF0 0x00000020U
3444 #define DMA_LIFCR_CHTIF0 0x00000010U
3445 #define DMA_LIFCR_CTEIF0 0x00000008U
3446 #define DMA_LIFCR_CDMEIF0 0x00000004U
3447 #define DMA_LIFCR_CFEIF0 0x00000001U
3448 
3449 /******************** Bits definition for DMA_HIFCR register ****************/
3450 #define DMA_HIFCR_CTCIF7 0x08000000U
3451 #define DMA_HIFCR_CHTIF7 0x04000000U
3452 #define DMA_HIFCR_CTEIF7 0x02000000U
3453 #define DMA_HIFCR_CDMEIF7 0x01000000U
3454 #define DMA_HIFCR_CFEIF7 0x00400000U
3455 #define DMA_HIFCR_CTCIF6 0x00200000U
3456 #define DMA_HIFCR_CHTIF6 0x00100000U
3457 #define DMA_HIFCR_CTEIF6 0x00080000U
3458 #define DMA_HIFCR_CDMEIF6 0x00040000U
3459 #define DMA_HIFCR_CFEIF6 0x00010000U
3460 #define DMA_HIFCR_CTCIF5 0x00000800U
3461 #define DMA_HIFCR_CHTIF5 0x00000400U
3462 #define DMA_HIFCR_CTEIF5 0x00000200U
3463 #define DMA_HIFCR_CDMEIF5 0x00000100U
3464 #define DMA_HIFCR_CFEIF5 0x00000040U
3465 #define DMA_HIFCR_CTCIF4 0x00000020U
3466 #define DMA_HIFCR_CHTIF4 0x00000010U
3467 #define DMA_HIFCR_CTEIF4 0x00000008U
3468 #define DMA_HIFCR_CDMEIF4 0x00000004U
3469 #define DMA_HIFCR_CFEIF4 0x00000001U
3470 
3471 
3472 /******************************************************************************/
3473 /* */
3474 /* AHB Master DMA2D Controller (DMA2D) */
3475 /* */
3476 /******************************************************************************/
3477 
3478 /******************** Bit definition for DMA2D_CR register ******************/
3479 
3480 #define DMA2D_CR_START 0x00000001U
3481 #define DMA2D_CR_SUSP 0x00000002U
3482 #define DMA2D_CR_ABORT 0x00000004U
3483 #define DMA2D_CR_TEIE 0x00000100U
3484 #define DMA2D_CR_TCIE 0x00000200U
3485 #define DMA2D_CR_TWIE 0x00000400U
3486 #define DMA2D_CR_CAEIE 0x00000800U
3487 #define DMA2D_CR_CTCIE 0x00001000U
3488 #define DMA2D_CR_CEIE 0x00002000U
3489 #define DMA2D_CR_MODE 0x00030000U
3490 #define DMA2D_CR_MODE_0 0x00010000U
3491 #define DMA2D_CR_MODE_1 0x00020000U
3493 /******************** Bit definition for DMA2D_ISR register *****************/
3494 
3495 #define DMA2D_ISR_TEIF 0x00000001U
3496 #define DMA2D_ISR_TCIF 0x00000002U
3497 #define DMA2D_ISR_TWIF 0x00000004U
3498 #define DMA2D_ISR_CAEIF 0x00000008U
3499 #define DMA2D_ISR_CTCIF 0x00000010U
3500 #define DMA2D_ISR_CEIF 0x00000020U
3502 /******************** Bit definition for DMA2D_IFCR register ****************/
3503 
3504 #define DMA2D_IFCR_CTEIF 0x00000001U
3505 #define DMA2D_IFCR_CTCIF 0x00000002U
3506 #define DMA2D_IFCR_CTWIF 0x00000004U
3507 #define DMA2D_IFCR_CAECIF 0x00000008U
3508 #define DMA2D_IFCR_CCTCIF 0x00000010U
3509 #define DMA2D_IFCR_CCEIF 0x00000020U
3511 /* Legacy defines */
3512 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3513 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3514 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3515 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3516 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3517 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3519 /******************** Bit definition for DMA2D_FGMAR register ***************/
3520 
3521 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3523 /******************** Bit definition for DMA2D_FGOR register ****************/
3524 
3525 #define DMA2D_FGOR_LO 0x00003FFFU
3527 /******************** Bit definition for DMA2D_BGMAR register ***************/
3528 
3529 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3531 /******************** Bit definition for DMA2D_BGOR register ****************/
3532 
3533 #define DMA2D_BGOR_LO 0x00003FFFU
3535 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3536 
3537 #define DMA2D_FGPFCCR_CM 0x0000000FU
3538 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3539 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3540 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3541 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3542 #define DMA2D_FGPFCCR_CCM 0x00000010U
3543 #define DMA2D_FGPFCCR_START 0x00000020U
3544 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3545 #define DMA2D_FGPFCCR_AM 0x00030000U
3546 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3547 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3548 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3550 /******************** Bit definition for DMA2D_FGCOLR register **************/
3551 
3552 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3553 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3554 #define DMA2D_FGCOLR_RED 0x00FF0000U
3556 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3557 
3558 #define DMA2D_BGPFCCR_CM 0x0000000FU
3559 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3560 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3561 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3562 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3563 #define DMA2D_BGPFCCR_CCM 0x00000010U
3564 #define DMA2D_BGPFCCR_START 0x00000020U
3565 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3566 #define DMA2D_BGPFCCR_AM 0x00030000U
3567 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3568 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3569 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3571 /******************** Bit definition for DMA2D_BGCOLR register **************/
3572 
3573 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3574 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3575 #define DMA2D_BGCOLR_RED 0x00FF0000U
3577 /******************** Bit definition for DMA2D_FGCMAR register **************/
3578 
3579 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3581 /******************** Bit definition for DMA2D_BGCMAR register **************/
3582 
3583 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3585 /******************** Bit definition for DMA2D_OPFCCR register **************/
3586 
3587 #define DMA2D_OPFCCR_CM 0x00000007U
3588 #define DMA2D_OPFCCR_CM_0 0x00000001U
3589 #define DMA2D_OPFCCR_CM_1 0x00000002U
3590 #define DMA2D_OPFCCR_CM_2 0x00000004U
3592 /******************** Bit definition for DMA2D_OCOLR register ***************/
3593 
3596 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3597 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3598 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3599 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3602 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3603 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3604 #define DMA2D_OCOLR_RED_2 0x0000F800U
3607 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3608 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3609 #define DMA2D_OCOLR_RED_3 0x00007C00U
3610 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3613 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3614 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3615 #define DMA2D_OCOLR_RED_4 0x00000F00U
3616 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3618 /******************** Bit definition for DMA2D_OMAR register ****************/
3619 
3620 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3622 /******************** Bit definition for DMA2D_OOR register *****************/
3623 
3624 #define DMA2D_OOR_LO 0x00003FFFU
3626 /******************** Bit definition for DMA2D_NLR register *****************/
3627 
3628 #define DMA2D_NLR_NL 0x0000FFFFU
3629 #define DMA2D_NLR_PL 0x3FFF0000U
3631 /******************** Bit definition for DMA2D_LWR register *****************/
3632 
3633 #define DMA2D_LWR_LW 0x0000FFFFU
3635 /******************** Bit definition for DMA2D_AMTCR register ***************/
3636 
3637 #define DMA2D_AMTCR_EN 0x00000001U
3638 #define DMA2D_AMTCR_DT 0x0000FF00U
3640 /******************** Bit definition for DMA2D_FGCLUT register **************/
3641 
3642 /******************** Bit definition for DMA2D_BGCLUT register **************/
3643 
3644 
3645 
3646 /******************************************************************************/
3647 /* */
3648 /* External Interrupt/Event Controller */
3649 /* */
3650 /******************************************************************************/
3651 /******************* Bit definition for EXTI_IMR register *******************/
3652 #define EXTI_IMR_MR0 0x00000001U
3653 #define EXTI_IMR_MR1 0x00000002U
3654 #define EXTI_IMR_MR2 0x00000004U
3655 #define EXTI_IMR_MR3 0x00000008U
3656 #define EXTI_IMR_MR4 0x00000010U
3657 #define EXTI_IMR_MR5 0x00000020U
3658 #define EXTI_IMR_MR6 0x00000040U
3659 #define EXTI_IMR_MR7 0x00000080U
3660 #define EXTI_IMR_MR8 0x00000100U
3661 #define EXTI_IMR_MR9 0x00000200U
3662 #define EXTI_IMR_MR10 0x00000400U
3663 #define EXTI_IMR_MR11 0x00000800U
3664 #define EXTI_IMR_MR12 0x00001000U
3665 #define EXTI_IMR_MR13 0x00002000U
3666 #define EXTI_IMR_MR14 0x00004000U
3667 #define EXTI_IMR_MR15 0x00008000U
3668 #define EXTI_IMR_MR16 0x00010000U
3669 #define EXTI_IMR_MR17 0x00020000U
3670 #define EXTI_IMR_MR18 0x00040000U
3671 #define EXTI_IMR_MR19 0x00080000U
3672 #define EXTI_IMR_MR20 0x00100000U
3673 #define EXTI_IMR_MR21 0x00200000U
3674 #define EXTI_IMR_MR22 0x00400000U
3676 /******************* Bit definition for EXTI_EMR register *******************/
3677 #define EXTI_EMR_MR0 0x00000001U
3678 #define EXTI_EMR_MR1 0x00000002U
3679 #define EXTI_EMR_MR2 0x00000004U
3680 #define EXTI_EMR_MR3 0x00000008U
3681 #define EXTI_EMR_MR4 0x00000010U
3682 #define EXTI_EMR_MR5 0x00000020U
3683 #define EXTI_EMR_MR6 0x00000040U
3684 #define EXTI_EMR_MR7 0x00000080U
3685 #define EXTI_EMR_MR8 0x00000100U
3686 #define EXTI_EMR_MR9 0x00000200U
3687 #define EXTI_EMR_MR10 0x00000400U
3688 #define EXTI_EMR_MR11 0x00000800U
3689 #define EXTI_EMR_MR12 0x00001000U
3690 #define EXTI_EMR_MR13 0x00002000U
3691 #define EXTI_EMR_MR14 0x00004000U
3692 #define EXTI_EMR_MR15 0x00008000U
3693 #define EXTI_EMR_MR16 0x00010000U
3694 #define EXTI_EMR_MR17 0x00020000U
3695 #define EXTI_EMR_MR18 0x00040000U
3696 #define EXTI_EMR_MR19 0x00080000U
3697 #define EXTI_EMR_MR20 0x00100000U
3698 #define EXTI_EMR_MR21 0x00200000U
3699 #define EXTI_EMR_MR22 0x00400000U
3701 /****************** Bit definition for EXTI_RTSR register *******************/
3702 #define EXTI_RTSR_TR0 0x00000001U
3703 #define EXTI_RTSR_TR1 0x00000002U
3704 #define EXTI_RTSR_TR2 0x00000004U
3705 #define EXTI_RTSR_TR3 0x00000008U
3706 #define EXTI_RTSR_TR4 0x00000010U
3707 #define EXTI_RTSR_TR5 0x00000020U
3708 #define EXTI_RTSR_TR6 0x00000040U
3709 #define EXTI_RTSR_TR7 0x00000080U
3710 #define EXTI_RTSR_TR8 0x00000100U
3711 #define EXTI_RTSR_TR9 0x00000200U
3712 #define EXTI_RTSR_TR10 0x00000400U
3713 #define EXTI_RTSR_TR11 0x00000800U
3714 #define EXTI_RTSR_TR12 0x00001000U
3715 #define EXTI_RTSR_TR13 0x00002000U
3716 #define EXTI_RTSR_TR14 0x00004000U
3717 #define EXTI_RTSR_TR15 0x00008000U
3718 #define EXTI_RTSR_TR16 0x00010000U
3719 #define EXTI_RTSR_TR17 0x00020000U
3720 #define EXTI_RTSR_TR18 0x00040000U
3721 #define EXTI_RTSR_TR19 0x00080000U
3722 #define EXTI_RTSR_TR20 0x00100000U
3723 #define EXTI_RTSR_TR21 0x00200000U
3724 #define EXTI_RTSR_TR22 0x00400000U
3726 /****************** Bit definition for EXTI_FTSR register *******************/
3727 #define EXTI_FTSR_TR0 0x00000001U
3728 #define EXTI_FTSR_TR1 0x00000002U
3729 #define EXTI_FTSR_TR2 0x00000004U
3730 #define EXTI_FTSR_TR3 0x00000008U
3731 #define EXTI_FTSR_TR4 0x00000010U
3732 #define EXTI_FTSR_TR5 0x00000020U
3733 #define EXTI_FTSR_TR6 0x00000040U
3734 #define EXTI_FTSR_TR7 0x00000080U
3735 #define EXTI_FTSR_TR8 0x00000100U
3736 #define EXTI_FTSR_TR9 0x00000200U
3737 #define EXTI_FTSR_TR10 0x00000400U
3738 #define EXTI_FTSR_TR11 0x00000800U
3739 #define EXTI_FTSR_TR12 0x00001000U
3740 #define EXTI_FTSR_TR13 0x00002000U
3741 #define EXTI_FTSR_TR14 0x00004000U
3742 #define EXTI_FTSR_TR15 0x00008000U
3743 #define EXTI_FTSR_TR16 0x00010000U
3744 #define EXTI_FTSR_TR17 0x00020000U
3745 #define EXTI_FTSR_TR18 0x00040000U
3746 #define EXTI_FTSR_TR19 0x00080000U
3747 #define EXTI_FTSR_TR20 0x00100000U
3748 #define EXTI_FTSR_TR21 0x00200000U
3749 #define EXTI_FTSR_TR22 0x00400000U
3751 /****************** Bit definition for EXTI_SWIER register ******************/
3752 #define EXTI_SWIER_SWIER0 0x00000001U
3753 #define EXTI_SWIER_SWIER1 0x00000002U
3754 #define EXTI_SWIER_SWIER2 0x00000004U
3755 #define EXTI_SWIER_SWIER3 0x00000008U
3756 #define EXTI_SWIER_SWIER4 0x00000010U
3757 #define EXTI_SWIER_SWIER5 0x00000020U
3758 #define EXTI_SWIER_SWIER6 0x00000040U
3759 #define EXTI_SWIER_SWIER7 0x00000080U
3760 #define EXTI_SWIER_SWIER8 0x00000100U
3761 #define EXTI_SWIER_SWIER9 0x00000200U
3762 #define EXTI_SWIER_SWIER10 0x00000400U
3763 #define EXTI_SWIER_SWIER11 0x00000800U
3764 #define EXTI_SWIER_SWIER12 0x00001000U
3765 #define EXTI_SWIER_SWIER13 0x00002000U
3766 #define EXTI_SWIER_SWIER14 0x00004000U
3767 #define EXTI_SWIER_SWIER15 0x00008000U
3768 #define EXTI_SWIER_SWIER16 0x00010000U
3769 #define EXTI_SWIER_SWIER17 0x00020000U
3770 #define EXTI_SWIER_SWIER18 0x00040000U
3771 #define EXTI_SWIER_SWIER19 0x00080000U
3772 #define EXTI_SWIER_SWIER20 0x00100000U
3773 #define EXTI_SWIER_SWIER21 0x00200000U
3774 #define EXTI_SWIER_SWIER22 0x00400000U
3776 /******************* Bit definition for EXTI_PR register ********************/
3777 #define EXTI_PR_PR0 0x00000001U
3778 #define EXTI_PR_PR1 0x00000002U
3779 #define EXTI_PR_PR2 0x00000004U
3780 #define EXTI_PR_PR3 0x00000008U
3781 #define EXTI_PR_PR4 0x00000010U
3782 #define EXTI_PR_PR5 0x00000020U
3783 #define EXTI_PR_PR6 0x00000040U
3784 #define EXTI_PR_PR7 0x00000080U
3785 #define EXTI_PR_PR8 0x00000100U
3786 #define EXTI_PR_PR9 0x00000200U
3787 #define EXTI_PR_PR10 0x00000400U
3788 #define EXTI_PR_PR11 0x00000800U
3789 #define EXTI_PR_PR12 0x00001000U
3790 #define EXTI_PR_PR13 0x00002000U
3791 #define EXTI_PR_PR14 0x00004000U
3792 #define EXTI_PR_PR15 0x00008000U
3793 #define EXTI_PR_PR16 0x00010000U
3794 #define EXTI_PR_PR17 0x00020000U
3795 #define EXTI_PR_PR18 0x00040000U
3796 #define EXTI_PR_PR19 0x00080000U
3797 #define EXTI_PR_PR20 0x00100000U
3798 #define EXTI_PR_PR21 0x00200000U
3799 #define EXTI_PR_PR22 0x00400000U
3801 /******************************************************************************/
3802 /* */
3803 /* FLASH */
3804 /* */
3805 /******************************************************************************/
3806 /******************* Bits definition for FLASH_ACR register *****************/
3807 #define FLASH_ACR_LATENCY 0x0000000FU
3808 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3809 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3810 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3811 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3812 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3813 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3814 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3815 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3816 #define FLASH_ACR_LATENCY_8WS 0x00000008U
3817 #define FLASH_ACR_LATENCY_9WS 0x00000009U
3818 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
3819 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
3820 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
3821 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
3822 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
3823 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
3824 #define FLASH_ACR_PRFTEN 0x00000100U
3825 #define FLASH_ACR_ICEN 0x00000200U
3826 #define FLASH_ACR_DCEN 0x00000400U
3827 #define FLASH_ACR_ICRST 0x00000800U
3828 #define FLASH_ACR_DCRST 0x00001000U
3829 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3830 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3831 
3832 /******************* Bits definition for FLASH_SR register ******************/
3833 #define FLASH_SR_EOP 0x00000001U
3834 #define FLASH_SR_SOP 0x00000002U
3835 #define FLASH_SR_WRPERR 0x00000010U
3836 #define FLASH_SR_PGAERR 0x00000020U
3837 #define FLASH_SR_PGPERR 0x00000040U
3838 #define FLASH_SR_PGSERR 0x00000080U
3839 #define FLASH_SR_BSY 0x00010000U
3840 
3841 /******************* Bits definition for FLASH_CR register ******************/
3842 #define FLASH_CR_PG 0x00000001U
3843 #define FLASH_CR_SER 0x00000002U
3844 #define FLASH_CR_MER 0x00000004U
3845 #define FLASH_CR_MER1 FLASH_CR_MER
3846 #define FLASH_CR_SNB 0x000000F8U
3847 #define FLASH_CR_SNB_0 0x00000008U
3848 #define FLASH_CR_SNB_1 0x00000010U
3849 #define FLASH_CR_SNB_2 0x00000020U
3850 #define FLASH_CR_SNB_3 0x00000040U
3851 #define FLASH_CR_SNB_4 0x00000080U
3852 #define FLASH_CR_PSIZE 0x00000300U
3853 #define FLASH_CR_PSIZE_0 0x00000100U
3854 #define FLASH_CR_PSIZE_1 0x00000200U
3855 #define FLASH_CR_MER2 0x00008000U
3856 #define FLASH_CR_STRT 0x00010000U
3857 #define FLASH_CR_EOPIE 0x01000000U
3858 #define FLASH_CR_LOCK 0x80000000U
3859 
3860 /******************* Bits definition for FLASH_OPTCR register ***************/
3861 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3862 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3863 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3864 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3865 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3866 #define FLASH_OPTCR_BFB2 0x00000010U
3867 #define FLASH_OPTCR_WDG_SW 0x00000020U
3868 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3869 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3870 #define FLASH_OPTCR_RDP 0x0000FF00U
3871 #define FLASH_OPTCR_RDP_0 0x00000100U
3872 #define FLASH_OPTCR_RDP_1 0x00000200U
3873 #define FLASH_OPTCR_RDP_2 0x00000400U
3874 #define FLASH_OPTCR_RDP_3 0x00000800U
3875 #define FLASH_OPTCR_RDP_4 0x00001000U
3876 #define FLASH_OPTCR_RDP_5 0x00002000U
3877 #define FLASH_OPTCR_RDP_6 0x00004000U
3878 #define FLASH_OPTCR_RDP_7 0x00008000U
3879 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3880 #define FLASH_OPTCR_nWRP_0 0x00010000U
3881 #define FLASH_OPTCR_nWRP_1 0x00020000U
3882 #define FLASH_OPTCR_nWRP_2 0x00040000U
3883 #define FLASH_OPTCR_nWRP_3 0x00080000U
3884 #define FLASH_OPTCR_nWRP_4 0x00100000U
3885 #define FLASH_OPTCR_nWRP_5 0x00200000U
3886 #define FLASH_OPTCR_nWRP_6 0x00400000U
3887 #define FLASH_OPTCR_nWRP_7 0x00800000U
3888 #define FLASH_OPTCR_nWRP_8 0x01000000U
3889 #define FLASH_OPTCR_nWRP_9 0x02000000U
3890 #define FLASH_OPTCR_nWRP_10 0x04000000U
3891 #define FLASH_OPTCR_nWRP_11 0x08000000U
3892 #define FLASH_OPTCR_DB1M 0x40000000U
3893 #define FLASH_OPTCR_SPRMOD 0x80000000U
3894 
3895 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3896 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3897 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3898 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3899 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3900 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3901 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3902 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3903 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3904 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3905 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3906 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3907 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3908 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3909 
3910 /******************************************************************************/
3911 /* */
3912 /* Flexible Memory Controller */
3913 /* */
3914 /******************************************************************************/
3915 /****************** Bit definition for FMC_BCR1 register *******************/
3916 #define FMC_BCR1_MBKEN 0x00000001U
3917 #define FMC_BCR1_MUXEN 0x00000002U
3919 #define FMC_BCR1_MTYP 0x0000000CU
3920 #define FMC_BCR1_MTYP_0 0x00000004U
3921 #define FMC_BCR1_MTYP_1 0x00000008U
3923 #define FMC_BCR1_MWID 0x00000030U
3924 #define FMC_BCR1_MWID_0 0x00000010U
3925 #define FMC_BCR1_MWID_1 0x00000020U
3927 #define FMC_BCR1_FACCEN 0x00000040U
3928 #define FMC_BCR1_BURSTEN 0x00000100U
3929 #define FMC_BCR1_WAITPOL 0x00000200U
3930 #define FMC_BCR1_WRAPMOD 0x00000400U
3931 #define FMC_BCR1_WAITCFG 0x00000800U
3932 #define FMC_BCR1_WREN 0x00001000U
3933 #define FMC_BCR1_WAITEN 0x00002000U
3934 #define FMC_BCR1_EXTMOD 0x00004000U
3935 #define FMC_BCR1_ASYNCWAIT 0x00008000U
3936 #define FMC_BCR1_CPSIZE 0x00070000U
3937 #define FMC_BCR1_CPSIZE_0 0x00010000U
3938 #define FMC_BCR1_CPSIZE_1 0x00020000U
3939 #define FMC_BCR1_CPSIZE_2 0x00040000U
3940 #define FMC_BCR1_CBURSTRW 0x00080000U
3941 #define FMC_BCR1_CCLKEN 0x00100000U
3943 /****************** Bit definition for FMC_BCR2 register *******************/
3944 #define FMC_BCR2_MBKEN 0x00000001U
3945 #define FMC_BCR2_MUXEN 0x00000002U
3947 #define FMC_BCR2_MTYP 0x0000000CU
3948 #define FMC_BCR2_MTYP_0 0x00000004U
3949 #define FMC_BCR2_MTYP_1 0x00000008U
3951 #define FMC_BCR2_MWID 0x00000030U
3952 #define FMC_BCR2_MWID_0 0x00000010U
3953 #define FMC_BCR2_MWID_1 0x00000020U
3955 #define FMC_BCR2_FACCEN 0x00000040U
3956 #define FMC_BCR2_BURSTEN 0x00000100U
3957 #define FMC_BCR2_WAITPOL 0x00000200U
3958 #define FMC_BCR2_WRAPMOD 0x00000400U
3959 #define FMC_BCR2_WAITCFG 0x00000800U
3960 #define FMC_BCR2_WREN 0x00001000U
3961 #define FMC_BCR2_WAITEN 0x00002000U
3962 #define FMC_BCR2_EXTMOD 0x00004000U
3963 #define FMC_BCR2_ASYNCWAIT 0x00008000U
3964 #define FMC_BCR2_CPSIZE 0x00070000U
3965 #define FMC_BCR2_CPSIZE_0 0x00010000U
3966 #define FMC_BCR2_CPSIZE_1 0x00020000U
3967 #define FMC_BCR2_CPSIZE_2 0x00040000U
3968 #define FMC_BCR2_CBURSTRW 0x00080000U
3970 /****************** Bit definition for FMC_BCR3 register *******************/
3971 #define FMC_BCR3_MBKEN 0x00000001U
3972 #define FMC_BCR3_MUXEN 0x00000002U
3974 #define FMC_BCR3_MTYP 0x0000000CU
3975 #define FMC_BCR3_MTYP_0 0x00000004U
3976 #define FMC_BCR3_MTYP_1 0x00000008U
3978 #define FMC_BCR3_MWID 0x00000030U
3979 #define FMC_BCR3_MWID_0 0x00000010U
3980 #define FMC_BCR3_MWID_1 0x00000020U
3982 #define FMC_BCR3_FACCEN 0x00000040U
3983 #define FMC_BCR3_BURSTEN 0x00000100U
3984 #define FMC_BCR3_WAITPOL 0x00000200U
3985 #define FMC_BCR3_WRAPMOD 0x00000400U
3986 #define FMC_BCR3_WAITCFG 0x00000800U
3987 #define FMC_BCR3_WREN 0x00001000U
3988 #define FMC_BCR3_WAITEN 0x00002000U
3989 #define FMC_BCR3_EXTMOD 0x00004000U
3990 #define FMC_BCR3_ASYNCWAIT 0x00008000U
3991 #define FMC_BCR3_CPSIZE 0x00070000U
3992 #define FMC_BCR3_CPSIZE_0 0x00010000U
3993 #define FMC_BCR3_CPSIZE_1 0x00020000U
3994 #define FMC_BCR3_CPSIZE_2 0x00040000U
3995 #define FMC_BCR3_CBURSTRW 0x00080000U
3997 /****************** Bit definition for FMC_BCR4 register *******************/
3998 #define FMC_BCR4_MBKEN 0x00000001U
3999 #define FMC_BCR4_MUXEN 0x00000002U
4001 #define FMC_BCR4_MTYP 0x0000000CU
4002 #define FMC_BCR4_MTYP_0 0x00000004U
4003 #define FMC_BCR4_MTYP_1 0x00000008U
4005 #define FMC_BCR4_MWID 0x00000030U
4006 #define FMC_BCR4_MWID_0 0x00000010U
4007 #define FMC_BCR4_MWID_1 0x00000020U
4009 #define FMC_BCR4_FACCEN 0x00000040U
4010 #define FMC_BCR4_BURSTEN 0x00000100U
4011 #define FMC_BCR4_WAITPOL 0x00000200U
4012 #define FMC_BCR4_WRAPMOD 0x00000400U
4013 #define FMC_BCR4_WAITCFG 0x00000800U
4014 #define FMC_BCR4_WREN 0x00001000U
4015 #define FMC_BCR4_WAITEN 0x00002000U
4016 #define FMC_BCR4_EXTMOD 0x00004000U
4017 #define FMC_BCR4_ASYNCWAIT 0x00008000U
4018 #define FMC_BCR4_CPSIZE 0x00070000U
4019 #define FMC_BCR4_CPSIZE_0 0x00010000U
4020 #define FMC_BCR4_CPSIZE_1 0x00020000U
4021 #define FMC_BCR4_CPSIZE_2 0x00040000U
4022 #define FMC_BCR4_CBURSTRW 0x00080000U
4024 /****************** Bit definition for FMC_BTR1 register ******************/
4025 #define FMC_BTR1_ADDSET 0x0000000FU
4026 #define FMC_BTR1_ADDSET_0 0x00000001U
4027 #define FMC_BTR1_ADDSET_1 0x00000002U
4028 #define FMC_BTR1_ADDSET_2 0x00000004U
4029 #define FMC_BTR1_ADDSET_3 0x00000008U
4031 #define FMC_BTR1_ADDHLD 0x000000F0U
4032 #define FMC_BTR1_ADDHLD_0 0x00000010U
4033 #define FMC_BTR1_ADDHLD_1 0x00000020U
4034 #define FMC_BTR1_ADDHLD_2 0x00000040U
4035 #define FMC_BTR1_ADDHLD_3 0x00000080U
4037 #define FMC_BTR1_DATAST 0x0000FF00U
4038 #define FMC_BTR1_DATAST_0 0x00000100U
4039 #define FMC_BTR1_DATAST_1 0x00000200U
4040 #define FMC_BTR1_DATAST_2 0x00000400U
4041 #define FMC_BTR1_DATAST_3 0x00000800U
4042 #define FMC_BTR1_DATAST_4 0x00001000U
4043 #define FMC_BTR1_DATAST_5 0x00002000U
4044 #define FMC_BTR1_DATAST_6 0x00004000U
4045 #define FMC_BTR1_DATAST_7 0x00008000U
4047 #define FMC_BTR1_BUSTURN 0x000F0000U
4048 #define FMC_BTR1_BUSTURN_0 0x00010000U
4049 #define FMC_BTR1_BUSTURN_1 0x00020000U
4050 #define FMC_BTR1_BUSTURN_2 0x00040000U
4051 #define FMC_BTR1_BUSTURN_3 0x00080000U
4053 #define FMC_BTR1_CLKDIV 0x00F00000U
4054 #define FMC_BTR1_CLKDIV_0 0x00100000U
4055 #define FMC_BTR1_CLKDIV_1 0x00200000U
4056 #define FMC_BTR1_CLKDIV_2 0x00400000U
4057 #define FMC_BTR1_CLKDIV_3 0x00800000U
4059 #define FMC_BTR1_DATLAT 0x0F000000U
4060 #define FMC_BTR1_DATLAT_0 0x01000000U
4061 #define FMC_BTR1_DATLAT_1 0x02000000U
4062 #define FMC_BTR1_DATLAT_2 0x04000000U
4063 #define FMC_BTR1_DATLAT_3 0x08000000U
4065 #define FMC_BTR1_ACCMOD 0x30000000U
4066 #define FMC_BTR1_ACCMOD_0 0x10000000U
4067 #define FMC_BTR1_ACCMOD_1 0x20000000U
4069 /****************** Bit definition for FMC_BTR2 register *******************/
4070 #define FMC_BTR2_ADDSET 0x0000000FU
4071 #define FMC_BTR2_ADDSET_0 0x00000001U
4072 #define FMC_BTR2_ADDSET_1 0x00000002U
4073 #define FMC_BTR2_ADDSET_2 0x00000004U
4074 #define FMC_BTR2_ADDSET_3 0x00000008U
4076 #define FMC_BTR2_ADDHLD 0x000000F0U
4077 #define FMC_BTR2_ADDHLD_0 0x00000010U
4078 #define FMC_BTR2_ADDHLD_1 0x00000020U
4079 #define FMC_BTR2_ADDHLD_2 0x00000040U
4080 #define FMC_BTR2_ADDHLD_3 0x00000080U
4082 #define FMC_BTR2_DATAST 0x0000FF00U
4083 #define FMC_BTR2_DATAST_0 0x00000100U
4084 #define FMC_BTR2_DATAST_1 0x00000200U
4085 #define FMC_BTR2_DATAST_2 0x00000400U
4086 #define FMC_BTR2_DATAST_3 0x00000800U
4087 #define FMC_BTR2_DATAST_4 0x00001000U
4088 #define FMC_BTR2_DATAST_5 0x00002000U
4089 #define FMC_BTR2_DATAST_6 0x00004000U
4090 #define FMC_BTR2_DATAST_7 0x00008000U
4092 #define FMC_BTR2_BUSTURN 0x000F0000U
4093 #define FMC_BTR2_BUSTURN_0 0x00010000U
4094 #define FMC_BTR2_BUSTURN_1 0x00020000U
4095 #define FMC_BTR2_BUSTURN_2 0x00040000U
4096 #define FMC_BTR2_BUSTURN_3 0x00080000U
4098 #define FMC_BTR2_CLKDIV 0x00F00000U
4099 #define FMC_BTR2_CLKDIV_0 0x00100000U
4100 #define FMC_BTR2_CLKDIV_1 0x00200000U
4101 #define FMC_BTR2_CLKDIV_2 0x00400000U
4102 #define FMC_BTR2_CLKDIV_3 0x00800000U
4104 #define FMC_BTR2_DATLAT 0x0F000000U
4105 #define FMC_BTR2_DATLAT_0 0x01000000U
4106 #define FMC_BTR2_DATLAT_1 0x02000000U
4107 #define FMC_BTR2_DATLAT_2 0x04000000U
4108 #define FMC_BTR2_DATLAT_3 0x08000000U
4110 #define FMC_BTR2_ACCMOD 0x30000000U
4111 #define FMC_BTR2_ACCMOD_0 0x10000000U
4112 #define FMC_BTR2_ACCMOD_1 0x20000000U
4114 /******************* Bit definition for FMC_BTR3 register *******************/
4115 #define FMC_BTR3_ADDSET 0x0000000FU
4116 #define FMC_BTR3_ADDSET_0 0x00000001U
4117 #define FMC_BTR3_ADDSET_1 0x00000002U
4118 #define FMC_BTR3_ADDSET_2 0x00000004U
4119 #define FMC_BTR3_ADDSET_3 0x00000008U
4121 #define FMC_BTR3_ADDHLD 0x000000F0U
4122 #define FMC_BTR3_ADDHLD_0 0x00000010U
4123 #define FMC_BTR3_ADDHLD_1 0x00000020U
4124 #define FMC_BTR3_ADDHLD_2 0x00000040U
4125 #define FMC_BTR3_ADDHLD_3 0x00000080U
4127 #define FMC_BTR3_DATAST 0x0000FF00U
4128 #define FMC_BTR3_DATAST_0 0x00000100U
4129 #define FMC_BTR3_DATAST_1 0x00000200U
4130 #define FMC_BTR3_DATAST_2 0x00000400U
4131 #define FMC_BTR3_DATAST_3 0x00000800U
4132 #define FMC_BTR3_DATAST_4 0x00001000U
4133 #define FMC_BTR3_DATAST_5 0x00002000U
4134 #define FMC_BTR3_DATAST_6 0x00004000U
4135 #define FMC_BTR3_DATAST_7 0x00008000U
4137 #define FMC_BTR3_BUSTURN 0x000F0000U
4138 #define FMC_BTR3_BUSTURN_0 0x00010000U
4139 #define FMC_BTR3_BUSTURN_1 0x00020000U
4140 #define FMC_BTR3_BUSTURN_2 0x00040000U
4141 #define FMC_BTR3_BUSTURN_3 0x00080000U
4143 #define FMC_BTR3_CLKDIV 0x00F00000U
4144 #define FMC_BTR3_CLKDIV_0 0x00100000U
4145 #define FMC_BTR3_CLKDIV_1 0x00200000U
4146 #define FMC_BTR3_CLKDIV_2 0x00400000U
4147 #define FMC_BTR3_CLKDIV_3 0x00800000U
4149 #define FMC_BTR3_DATLAT 0x0F000000U
4150 #define FMC_BTR3_DATLAT_0 0x01000000U
4151 #define FMC_BTR3_DATLAT_1 0x02000000U
4152 #define FMC_BTR3_DATLAT_2 0x04000000U
4153 #define FMC_BTR3_DATLAT_3 0x08000000U
4155 #define FMC_BTR3_ACCMOD 0x30000000U
4156 #define FMC_BTR3_ACCMOD_0 0x10000000U
4157 #define FMC_BTR3_ACCMOD_1 0x20000000U
4159 /****************** Bit definition for FMC_BTR4 register *******************/
4160 #define FMC_BTR4_ADDSET 0x0000000FU
4161 #define FMC_BTR4_ADDSET_0 0x00000001U
4162 #define FMC_BTR4_ADDSET_1 0x00000002U
4163 #define FMC_BTR4_ADDSET_2 0x00000004U
4164 #define FMC_BTR4_ADDSET_3 0x00000008U
4166 #define FMC_BTR4_ADDHLD 0x000000F0U
4167 #define FMC_BTR4_ADDHLD_0 0x00000010U
4168 #define FMC_BTR4_ADDHLD_1 0x00000020U
4169 #define FMC_BTR4_ADDHLD_2 0x00000040U
4170 #define FMC_BTR4_ADDHLD_3 0x00000080U
4172 #define FMC_BTR4_DATAST 0x0000FF00U
4173 #define FMC_BTR4_DATAST_0 0x00000100U
4174 #define FMC_BTR4_DATAST_1 0x00000200U
4175 #define FMC_BTR4_DATAST_2 0x00000400U
4176 #define FMC_BTR4_DATAST_3 0x00000800U
4177 #define FMC_BTR4_DATAST_4 0x00001000U
4178 #define FMC_BTR4_DATAST_5 0x00002000U
4179 #define FMC_BTR4_DATAST_6 0x00004000U
4180 #define FMC_BTR4_DATAST_7 0x00008000U
4182 #define FMC_BTR4_BUSTURN 0x000F0000U
4183 #define FMC_BTR4_BUSTURN_0 0x00010000U
4184 #define FMC_BTR4_BUSTURN_1 0x00020000U
4185 #define FMC_BTR4_BUSTURN_2 0x00040000U
4186 #define FMC_BTR4_BUSTURN_3 0x00080000U
4188 #define FMC_BTR4_CLKDIV 0x00F00000U
4189 #define FMC_BTR4_CLKDIV_0 0x00100000U
4190 #define FMC_BTR4_CLKDIV_1 0x00200000U
4191 #define FMC_BTR4_CLKDIV_2 0x00400000U
4192 #define FMC_BTR4_CLKDIV_3 0x00800000U
4194 #define FMC_BTR4_DATLAT 0x0F000000U
4195 #define FMC_BTR4_DATLAT_0 0x01000000U
4196 #define FMC_BTR4_DATLAT_1 0x02000000U
4197 #define FMC_BTR4_DATLAT_2 0x04000000U
4198 #define FMC_BTR4_DATLAT_3 0x08000000U
4200 #define FMC_BTR4_ACCMOD 0x30000000U
4201 #define FMC_BTR4_ACCMOD_0 0x10000000U
4202 #define FMC_BTR4_ACCMOD_1 0x20000000U
4204 /****************** Bit definition for FMC_BWTR1 register ******************/
4205 #define FMC_BWTR1_ADDSET 0x0000000FU
4206 #define FMC_BWTR1_ADDSET_0 0x00000001U
4207 #define FMC_BWTR1_ADDSET_1 0x00000002U
4208 #define FMC_BWTR1_ADDSET_2 0x00000004U
4209 #define FMC_BWTR1_ADDSET_3 0x00000008U
4211 #define FMC_BWTR1_ADDHLD 0x000000F0U
4212 #define FMC_BWTR1_ADDHLD_0 0x00000010U
4213 #define FMC_BWTR1_ADDHLD_1 0x00000020U
4214 #define FMC_BWTR1_ADDHLD_2 0x00000040U
4215 #define FMC_BWTR1_ADDHLD_3 0x00000080U
4217 #define FMC_BWTR1_DATAST 0x0000FF00U
4218 #define FMC_BWTR1_DATAST_0 0x00000100U
4219 #define FMC_BWTR1_DATAST_1 0x00000200U
4220 #define FMC_BWTR1_DATAST_2 0x00000400U
4221 #define FMC_BWTR1_DATAST_3 0x00000800U
4222 #define FMC_BWTR1_DATAST_4 0x00001000U
4223 #define FMC_BWTR1_DATAST_5 0x00002000U
4224 #define FMC_BWTR1_DATAST_6 0x00004000U
4225 #define FMC_BWTR1_DATAST_7 0x00008000U
4227 #define FMC_BWTR1_BUSTURN 0x000F0000U
4228 #define FMC_BWTR1_BUSTURN_0 0x00010000U
4229 #define FMC_BWTR1_BUSTURN_1 0x00020000U
4230 #define FMC_BWTR1_BUSTURN_2 0x00040000U
4231 #define FMC_BWTR1_BUSTURN_3 0x00080000U
4233 #define FMC_BWTR1_ACCMOD 0x30000000U
4234 #define FMC_BWTR1_ACCMOD_0 0x10000000U
4235 #define FMC_BWTR1_ACCMOD_1 0x20000000U
4237 /****************** Bit definition for FMC_BWTR2 register ******************/
4238 #define FMC_BWTR2_ADDSET 0x0000000FU
4239 #define FMC_BWTR2_ADDSET_0 0x00000001U
4240 #define FMC_BWTR2_ADDSET_1 0x00000002U
4241 #define FMC_BWTR2_ADDSET_2 0x00000004U
4242 #define FMC_BWTR2_ADDSET_3 0x00000008U
4244 #define FMC_BWTR2_ADDHLD 0x000000F0U
4245 #define FMC_BWTR2_ADDHLD_0 0x00000010U
4246 #define FMC_BWTR2_ADDHLD_1 0x00000020U
4247 #define FMC_BWTR2_ADDHLD_2 0x00000040U
4248 #define FMC_BWTR2_ADDHLD_3 0x00000080U
4250 #define FMC_BWTR2_DATAST 0x0000FF00U
4251 #define FMC_BWTR2_DATAST_0 0x00000100U
4252 #define FMC_BWTR2_DATAST_1 0x00000200U
4253 #define FMC_BWTR2_DATAST_2 0x00000400U
4254 #define FMC_BWTR2_DATAST_3 0x00000800U
4255 #define FMC_BWTR2_DATAST_4 0x00001000U
4256 #define FMC_BWTR2_DATAST_5 0x00002000U
4257 #define FMC_BWTR2_DATAST_6 0x00004000U
4258 #define FMC_BWTR2_DATAST_7 0x00008000U
4260 #define FMC_BWTR2_BUSTURN 0x000F0000U
4261 #define FMC_BWTR2_BUSTURN_0 0x00010000U
4262 #define FMC_BWTR2_BUSTURN_1 0x00020000U
4263 #define FMC_BWTR2_BUSTURN_2 0x00040000U
4264 #define FMC_BWTR2_BUSTURN_3 0x00080000U
4266 #define FMC_BWTR2_ACCMOD 0x30000000U
4267 #define FMC_BWTR2_ACCMOD_0 0x10000000U
4268 #define FMC_BWTR2_ACCMOD_1 0x20000000U
4270 /****************** Bit definition for FMC_BWTR3 register ******************/
4271 #define FMC_BWTR3_ADDSET 0x0000000FU
4272 #define FMC_BWTR3_ADDSET_0 0x00000001U
4273 #define FMC_BWTR3_ADDSET_1 0x00000002U
4274 #define FMC_BWTR3_ADDSET_2 0x00000004U
4275 #define FMC_BWTR3_ADDSET_3 0x00000008U
4277 #define FMC_BWTR3_ADDHLD 0x000000F0U
4278 #define FMC_BWTR3_ADDHLD_0 0x00000010U
4279 #define FMC_BWTR3_ADDHLD_1 0x00000020U
4280 #define FMC_BWTR3_ADDHLD_2 0x00000040U
4281 #define FMC_BWTR3_ADDHLD_3 0x00000080U
4283 #define FMC_BWTR3_DATAST 0x0000FF00U
4284 #define FMC_BWTR3_DATAST_0 0x00000100U
4285 #define FMC_BWTR3_DATAST_1 0x00000200U
4286 #define FMC_BWTR3_DATAST_2 0x00000400U
4287 #define FMC_BWTR3_DATAST_3 0x00000800U
4288 #define FMC_BWTR3_DATAST_4 0x00001000U
4289 #define FMC_BWTR3_DATAST_5 0x00002000U
4290 #define FMC_BWTR3_DATAST_6 0x00004000U
4291 #define FMC_BWTR3_DATAST_7 0x00008000U
4293 #define FMC_BWTR3_BUSTURN 0x000F0000U
4294 #define FMC_BWTR3_BUSTURN_0 0x00010000U
4295 #define FMC_BWTR3_BUSTURN_1 0x00020000U
4296 #define FMC_BWTR3_BUSTURN_2 0x00040000U
4297 #define FMC_BWTR3_BUSTURN_3 0x00080000U
4299 #define FMC_BWTR3_ACCMOD 0x30000000U
4300 #define FMC_BWTR3_ACCMOD_0 0x10000000U
4301 #define FMC_BWTR3_ACCMOD_1 0x20000000U
4303 /****************** Bit definition for FMC_BWTR4 register ******************/
4304 #define FMC_BWTR4_ADDSET 0x0000000FU
4305 #define FMC_BWTR4_ADDSET_0 0x00000001U
4306 #define FMC_BWTR4_ADDSET_1 0x00000002U
4307 #define FMC_BWTR4_ADDSET_2 0x00000004U
4308 #define FMC_BWTR4_ADDSET_3 0x00000008U
4310 #define FMC_BWTR4_ADDHLD 0x000000F0U
4311 #define FMC_BWTR4_ADDHLD_0 0x00000010U
4312 #define FMC_BWTR4_ADDHLD_1 0x00000020U
4313 #define FMC_BWTR4_ADDHLD_2 0x00000040U
4314 #define FMC_BWTR4_ADDHLD_3 0x00000080U
4316 #define FMC_BWTR4_DATAST 0x0000FF00U
4317 #define FMC_BWTR4_DATAST_0 0x00000100U
4318 #define FMC_BWTR4_DATAST_1 0x00000200U
4319 #define FMC_BWTR4_DATAST_2 0x00000400U
4320 #define FMC_BWTR4_DATAST_3 0x00000800U
4321 #define FMC_BWTR4_DATAST_4 0x00001000U
4322 #define FMC_BWTR4_DATAST_5 0x00002000U
4323 #define FMC_BWTR4_DATAST_6 0x00004000U
4324 #define FMC_BWTR4_DATAST_7 0x00008000U
4326 #define FMC_BWTR4_BUSTURN 0x000F0000U
4327 #define FMC_BWTR4_BUSTURN_0 0x00010000U
4328 #define FMC_BWTR4_BUSTURN_1 0x00020000U
4329 #define FMC_BWTR4_BUSTURN_2 0x00040000U
4330 #define FMC_BWTR4_BUSTURN_3 0x00080000U
4332 #define FMC_BWTR4_ACCMOD 0x30000000U
4333 #define FMC_BWTR4_ACCMOD_0 0x10000000U
4334 #define FMC_BWTR4_ACCMOD_1 0x20000000U
4336 /****************** Bit definition for FMC_PCR2 register *******************/
4337 #define FMC_PCR2_PWAITEN 0x00000002U
4338 #define FMC_PCR2_PBKEN 0x00000004U
4339 #define FMC_PCR2_PTYP 0x00000008U
4341 #define FMC_PCR2_PWID 0x00000030U
4342 #define FMC_PCR2_PWID_0 0x00000010U
4343 #define FMC_PCR2_PWID_1 0x00000020U
4345 #define FMC_PCR2_ECCEN 0x00000040U
4347 #define FMC_PCR2_TCLR 0x00001E00U
4348 #define FMC_PCR2_TCLR_0 0x00000200U
4349 #define FMC_PCR2_TCLR_1 0x00000400U
4350 #define FMC_PCR2_TCLR_2 0x00000800U
4351 #define FMC_PCR2_TCLR_3 0x00001000U
4353 #define FMC_PCR2_TAR 0x0001E000U
4354 #define FMC_PCR2_TAR_0 0x00002000U
4355 #define FMC_PCR2_TAR_1 0x00004000U
4356 #define FMC_PCR2_TAR_2 0x00008000U
4357 #define FMC_PCR2_TAR_3 0x00010000U
4359 #define FMC_PCR2_ECCPS 0x000E0000U
4360 #define FMC_PCR2_ECCPS_0 0x00020000U
4361 #define FMC_PCR2_ECCPS_1 0x00040000U
4362 #define FMC_PCR2_ECCPS_2 0x00080000U
4364 /****************** Bit definition for FMC_PCR3 register *******************/
4365 #define FMC_PCR3_PWAITEN 0x00000002U
4366 #define FMC_PCR3_PBKEN 0x00000004U
4367 #define FMC_PCR3_PTYP 0x00000008U
4369 #define FMC_PCR3_PWID 0x00000030U
4370 #define FMC_PCR3_PWID_0 0x00000010U
4371 #define FMC_PCR3_PWID_1 0x00000020U
4373 #define FMC_PCR3_ECCEN 0x00000040U
4375 #define FMC_PCR3_TCLR 0x00001E00U
4376 #define FMC_PCR3_TCLR_0 0x00000200U
4377 #define FMC_PCR3_TCLR_1 0x00000400U
4378 #define FMC_PCR3_TCLR_2 0x00000800U
4379 #define FMC_PCR3_TCLR_3 0x00001000U
4381 #define FMC_PCR3_TAR 0x0001E000U
4382 #define FMC_PCR3_TAR_0 0x00002000U
4383 #define FMC_PCR3_TAR_1 0x00004000U
4384 #define FMC_PCR3_TAR_2 0x00008000U
4385 #define FMC_PCR3_TAR_3 0x00010000U
4387 #define FMC_PCR3_ECCPS 0x000E0000U
4388 #define FMC_PCR3_ECCPS_0 0x00020000U
4389 #define FMC_PCR3_ECCPS_1 0x00040000U
4390 #define FMC_PCR3_ECCPS_2 0x00080000U
4392 /****************** Bit definition for FMC_PCR4 register *******************/
4393 #define FMC_PCR4_PWAITEN 0x00000002U
4394 #define FMC_PCR4_PBKEN 0x00000004U
4395 #define FMC_PCR4_PTYP 0x00000008U
4397 #define FMC_PCR4_PWID 0x00000030U
4398 #define FMC_PCR4_PWID_0 0x00000010U
4399 #define FMC_PCR4_PWID_1 0x00000020U
4401 #define FMC_PCR4_ECCEN 0x00000040U
4403 #define FMC_PCR4_TCLR 0x00001E00U
4404 #define FMC_PCR4_TCLR_0 0x00000200U
4405 #define FMC_PCR4_TCLR_1 0x00000400U
4406 #define FMC_PCR4_TCLR_2 0x00000800U
4407 #define FMC_PCR4_TCLR_3 0x00001000U
4409 #define FMC_PCR4_TAR 0x0001E000U
4410 #define FMC_PCR4_TAR_0 0x00002000U
4411 #define FMC_PCR4_TAR_1 0x00004000U
4412 #define FMC_PCR4_TAR_2 0x00008000U
4413 #define FMC_PCR4_TAR_3 0x00010000U
4415 #define FMC_PCR4_ECCPS 0x000E0000U
4416 #define FMC_PCR4_ECCPS_0 0x00020000U
4417 #define FMC_PCR4_ECCPS_1 0x00040000U
4418 #define FMC_PCR4_ECCPS_2 0x00080000U
4420 /******************* Bit definition for FMC_SR2 register *******************/
4421 #define FMC_SR2_IRS 0x01U
4422 #define FMC_SR2_ILS 0x02U
4423 #define FMC_SR2_IFS 0x04U
4424 #define FMC_SR2_IREN 0x08U
4425 #define FMC_SR2_ILEN 0x10U
4426 #define FMC_SR2_IFEN 0x20U
4427 #define FMC_SR2_FEMPT 0x40U
4429 /******************* Bit definition for FMC_SR3 register *******************/
4430 #define FMC_SR3_IRS 0x01U
4431 #define FMC_SR3_ILS 0x02U
4432 #define FMC_SR3_IFS 0x04U
4433 #define FMC_SR3_IREN 0x08U
4434 #define FMC_SR3_ILEN 0x10U
4435 #define FMC_SR3_IFEN 0x20U
4436 #define FMC_SR3_FEMPT 0x40U
4438 /******************* Bit definition for FMC_SR4 register *******************/
4439 #define FMC_SR4_IRS 0x01U
4440 #define FMC_SR4_ILS 0x02U
4441 #define FMC_SR4_IFS 0x04U
4442 #define FMC_SR4_IREN 0x08U
4443 #define FMC_SR4_ILEN 0x10U
4444 #define FMC_SR4_IFEN 0x20U
4445 #define FMC_SR4_FEMPT 0x40U
4447 /****************** Bit definition for FMC_PMEM2 register ******************/
4448 #define FMC_PMEM2_MEMSET2 0x000000FFU
4449 #define FMC_PMEM2_MEMSET2_0 0x00000001U
4450 #define FMC_PMEM2_MEMSET2_1 0x00000002U
4451 #define FMC_PMEM2_MEMSET2_2 0x00000004U
4452 #define FMC_PMEM2_MEMSET2_3 0x00000008U
4453 #define FMC_PMEM2_MEMSET2_4 0x00000010U
4454 #define FMC_PMEM2_MEMSET2_5 0x00000020U
4455 #define FMC_PMEM2_MEMSET2_6 0x00000040U
4456 #define FMC_PMEM2_MEMSET2_7 0x00000080U
4458 #define FMC_PMEM2_MEMWAIT2 0x0000FF00U
4459 #define FMC_PMEM2_MEMWAIT2_0 0x00000100U
4460 #define FMC_PMEM2_MEMWAIT2_1 0x00000200U
4461 #define FMC_PMEM2_MEMWAIT2_2 0x00000400U
4462 #define FMC_PMEM2_MEMWAIT2_3 0x00000800U
4463 #define FMC_PMEM2_MEMWAIT2_4 0x00001000U
4464 #define FMC_PMEM2_MEMWAIT2_5 0x00002000U
4465 #define FMC_PMEM2_MEMWAIT2_6 0x00004000U
4466 #define FMC_PMEM2_MEMWAIT2_7 0x00008000U
4468 #define FMC_PMEM2_MEMHOLD2 0x00FF0000U
4469 #define FMC_PMEM2_MEMHOLD2_0 0x00010000U
4470 #define FMC_PMEM2_MEMHOLD2_1 0x00020000U
4471 #define FMC_PMEM2_MEMHOLD2_2 0x00040000U
4472 #define FMC_PMEM2_MEMHOLD2_3 0x00080000U
4473 #define FMC_PMEM2_MEMHOLD2_4 0x00100000U
4474 #define FMC_PMEM2_MEMHOLD2_5 0x00200000U
4475 #define FMC_PMEM2_MEMHOLD2_6 0x00400000U
4476 #define FMC_PMEM2_MEMHOLD2_7 0x00800000U
4478 #define FMC_PMEM2_MEMHIZ2 0xFF000000U
4479 #define FMC_PMEM2_MEMHIZ2_0 0x01000000U
4480 #define FMC_PMEM2_MEMHIZ2_1 0x02000000U
4481 #define FMC_PMEM2_MEMHIZ2_2 0x04000000U
4482 #define FMC_PMEM2_MEMHIZ2_3 0x08000000U
4483 #define FMC_PMEM2_MEMHIZ2_4 0x10000000U
4484 #define FMC_PMEM2_MEMHIZ2_5 0x20000000U
4485 #define FMC_PMEM2_MEMHIZ2_6 0x40000000U
4486 #define FMC_PMEM2_MEMHIZ2_7 0x80000000U
4488 /****************** Bit definition for FMC_PMEM3 register ******************/
4489 #define FMC_PMEM3_MEMSET3 0x000000FFU
4490 #define FMC_PMEM3_MEMSET3_0 0x00000001U
4491 #define FMC_PMEM3_MEMSET3_1 0x00000002U
4492 #define FMC_PMEM3_MEMSET3_2 0x00000004U
4493 #define FMC_PMEM3_MEMSET3_3 0x00000008U
4494 #define FMC_PMEM3_MEMSET3_4 0x00000010U
4495 #define FMC_PMEM3_MEMSET3_5 0x00000020U
4496 #define FMC_PMEM3_MEMSET3_6 0x00000040U
4497 #define FMC_PMEM3_MEMSET3_7 0x00000080U
4499 #define FMC_PMEM3_MEMWAIT3 0x0000FF00U
4500 #define FMC_PMEM3_MEMWAIT3_0 0x00000100U
4501 #define FMC_PMEM3_MEMWAIT3_1 0x00000200U
4502 #define FMC_PMEM3_MEMWAIT3_2 0x00000400U
4503 #define FMC_PMEM3_MEMWAIT3_3 0x00000800U
4504 #define FMC_PMEM3_MEMWAIT3_4 0x00001000U
4505 #define FMC_PMEM3_MEMWAIT3_5 0x00002000U
4506 #define FMC_PMEM3_MEMWAIT3_6 0x00004000U
4507 #define FMC_PMEM3_MEMWAIT3_7 0x00008000U
4509 #define FMC_PMEM3_MEMHOLD3 0x00FF0000U
4510 #define FMC_PMEM3_MEMHOLD3_0 0x00010000U
4511 #define FMC_PMEM3_MEMHOLD3_1 0x00020000U
4512 #define FMC_PMEM3_MEMHOLD3_2 0x00040000U
4513 #define FMC_PMEM3_MEMHOLD3_3 0x00080000U
4514 #define FMC_PMEM3_MEMHOLD3_4 0x00100000U
4515 #define FMC_PMEM3_MEMHOLD3_5 0x00200000U
4516 #define FMC_PMEM3_MEMHOLD3_6 0x00400000U
4517 #define FMC_PMEM3_MEMHOLD3_7 0x00800000U
4519 #define FMC_PMEM3_MEMHIZ3 0xFF000000U
4520 #define FMC_PMEM3_MEMHIZ3_0 0x01000000U
4521 #define FMC_PMEM3_MEMHIZ3_1 0x02000000U
4522 #define FMC_PMEM3_MEMHIZ3_2 0x04000000U
4523 #define FMC_PMEM3_MEMHIZ3_3 0x08000000U
4524 #define FMC_PMEM3_MEMHIZ3_4 0x10000000U
4525 #define FMC_PMEM3_MEMHIZ3_5 0x20000000U
4526 #define FMC_PMEM3_MEMHIZ3_6 0x40000000U
4527 #define FMC_PMEM3_MEMHIZ3_7 0x80000000U
4529 /****************** Bit definition for FMC_PMEM4 register ******************/
4530 #define FMC_PMEM4_MEMSET4 0x000000FFU
4531 #define FMC_PMEM4_MEMSET4_0 0x00000001U
4532 #define FMC_PMEM4_MEMSET4_1 0x00000002U
4533 #define FMC_PMEM4_MEMSET4_2 0x00000004U
4534 #define FMC_PMEM4_MEMSET4_3 0x00000008U
4535 #define FMC_PMEM4_MEMSET4_4 0x00000010U
4536 #define FMC_PMEM4_MEMSET4_5 0x00000020U
4537 #define FMC_PMEM4_MEMSET4_6 0x00000040U
4538 #define FMC_PMEM4_MEMSET4_7 0x00000080U
4540 #define FMC_PMEM4_MEMWAIT4 0x0000FF00U
4541 #define FMC_PMEM4_MEMWAIT4_0 0x00000100U
4542 #define FMC_PMEM4_MEMWAIT4_1 0x00000200U
4543 #define FMC_PMEM4_MEMWAIT4_2 0x00000400U
4544 #define FMC_PMEM4_MEMWAIT4_3 0x00000800U
4545 #define FMC_PMEM4_MEMWAIT4_4 0x00001000U
4546 #define FMC_PMEM4_MEMWAIT4_5 0x00002000U
4547 #define FMC_PMEM4_MEMWAIT4_6 0x00004000U
4548 #define FMC_PMEM4_MEMWAIT4_7 0x00008000U
4550 #define FMC_PMEM4_MEMHOLD4 0x00FF0000U
4551 #define FMC_PMEM4_MEMHOLD4_0 0x00010000U
4552 #define FMC_PMEM4_MEMHOLD4_1 0x00020000U
4553 #define FMC_PMEM4_MEMHOLD4_2 0x00040000U
4554 #define FMC_PMEM4_MEMHOLD4_3 0x00080000U
4555 #define FMC_PMEM4_MEMHOLD4_4 0x00100000U
4556 #define FMC_PMEM4_MEMHOLD4_5 0x00200000U
4557 #define FMC_PMEM4_MEMHOLD4_6 0x00400000U
4558 #define FMC_PMEM4_MEMHOLD4_7 0x00800000U
4560 #define FMC_PMEM4_MEMHIZ4 0xFF000000U
4561 #define FMC_PMEM4_MEMHIZ4_0 0x01000000U
4562 #define FMC_PMEM4_MEMHIZ4_1 0x02000000U
4563 #define FMC_PMEM4_MEMHIZ4_2 0x04000000U
4564 #define FMC_PMEM4_MEMHIZ4_3 0x08000000U
4565 #define FMC_PMEM4_MEMHIZ4_4 0x10000000U
4566 #define FMC_PMEM4_MEMHIZ4_5 0x20000000U
4567 #define FMC_PMEM4_MEMHIZ4_6 0x40000000U
4568 #define FMC_PMEM4_MEMHIZ4_7 0x80000000U
4570 /****************** Bit definition for FMC_PATT2 register ******************/
4571 #define FMC_PATT2_ATTSET2 0x000000FFU
4572 #define FMC_PATT2_ATTSET2_0 0x00000001U
4573 #define FMC_PATT2_ATTSET2_1 0x00000002U
4574 #define FMC_PATT2_ATTSET2_2 0x00000004U
4575 #define FMC_PATT2_ATTSET2_3 0x00000008U
4576 #define FMC_PATT2_ATTSET2_4 0x00000010U
4577 #define FMC_PATT2_ATTSET2_5 0x00000020U
4578 #define FMC_PATT2_ATTSET2_6 0x00000040U
4579 #define FMC_PATT2_ATTSET2_7 0x00000080U
4581 #define FMC_PATT2_ATTWAIT2 0x0000FF00U
4582 #define FMC_PATT2_ATTWAIT2_0 0x00000100U
4583 #define FMC_PATT2_ATTWAIT2_1 0x00000200U
4584 #define FMC_PATT2_ATTWAIT2_2 0x00000400U
4585 #define FMC_PATT2_ATTWAIT2_3 0x00000800U
4586 #define FMC_PATT2_ATTWAIT2_4 0x00001000U
4587 #define FMC_PATT2_ATTWAIT2_5 0x00002000U
4588 #define FMC_PATT2_ATTWAIT2_6 0x00004000U
4589 #define FMC_PATT2_ATTWAIT2_7 0x00008000U
4591 #define FMC_PATT2_ATTHOLD2 0x00FF0000U
4592 #define FMC_PATT2_ATTHOLD2_0 0x00010000U
4593 #define FMC_PATT2_ATTHOLD2_1 0x00020000U
4594 #define FMC_PATT2_ATTHOLD2_2 0x00040000U
4595 #define FMC_PATT2_ATTHOLD2_3 0x00080000U
4596 #define FMC_PATT2_ATTHOLD2_4 0x00100000U
4597 #define FMC_PATT2_ATTHOLD2_5 0x00200000U
4598 #define FMC_PATT2_ATTHOLD2_6 0x00400000U
4599 #define FMC_PATT2_ATTHOLD2_7 0x00800000U
4601 #define FMC_PATT2_ATTHIZ2 0xFF000000U
4602 #define FMC_PATT2_ATTHIZ2_0 0x01000000U
4603 #define FMC_PATT2_ATTHIZ2_1 0x02000000U
4604 #define FMC_PATT2_ATTHIZ2_2 0x04000000U
4605 #define FMC_PATT2_ATTHIZ2_3 0x08000000U
4606 #define FMC_PATT2_ATTHIZ2_4 0x10000000U
4607 #define FMC_PATT2_ATTHIZ2_5 0x20000000U
4608 #define FMC_PATT2_ATTHIZ2_6 0x40000000U
4609 #define FMC_PATT2_ATTHIZ2_7 0x80000000U
4611 /****************** Bit definition for FMC_PATT3 register ******************/
4612 #define FMC_PATT3_ATTSET3 0x000000FFU
4613 #define FMC_PATT3_ATTSET3_0 0x00000001U
4614 #define FMC_PATT3_ATTSET3_1 0x00000002U
4615 #define FMC_PATT3_ATTSET3_2 0x00000004U
4616 #define FMC_PATT3_ATTSET3_3 0x00000008U
4617 #define FMC_PATT3_ATTSET3_4 0x00000010U
4618 #define FMC_PATT3_ATTSET3_5 0x00000020U
4619 #define FMC_PATT3_ATTSET3_6 0x00000040U
4620 #define FMC_PATT3_ATTSET3_7 0x00000080U
4622 #define FMC_PATT3_ATTWAIT3 0x0000FF00U
4623 #define FMC_PATT3_ATTWAIT3_0 0x00000100U
4624 #define FMC_PATT3_ATTWAIT3_1 0x00000200U
4625 #define FMC_PATT3_ATTWAIT3_2 0x00000400U
4626 #define FMC_PATT3_ATTWAIT3_3 0x00000800U
4627 #define FMC_PATT3_ATTWAIT3_4 0x00001000U
4628 #define FMC_PATT3_ATTWAIT3_5 0x00002000U
4629 #define FMC_PATT3_ATTWAIT3_6 0x00004000U
4630 #define FMC_PATT3_ATTWAIT3_7 0x00008000U
4632 #define FMC_PATT3_ATTHOLD3 0x00FF0000U
4633 #define FMC_PATT3_ATTHOLD3_0 0x00010000U
4634 #define FMC_PATT3_ATTHOLD3_1 0x00020000U
4635 #define FMC_PATT3_ATTHOLD3_2 0x00040000U
4636 #define FMC_PATT3_ATTHOLD3_3 0x00080000U
4637 #define FMC_PATT3_ATTHOLD3_4 0x00100000U
4638 #define FMC_PATT3_ATTHOLD3_5 0x00200000U
4639 #define FMC_PATT3_ATTHOLD3_6 0x00400000U
4640 #define FMC_PATT3_ATTHOLD3_7 0x00800000U
4642 #define FMC_PATT3_ATTHIZ3 0xFF000000U
4643 #define FMC_PATT3_ATTHIZ3_0 0x01000000U
4644 #define FMC_PATT3_ATTHIZ3_1 0x02000000U
4645 #define FMC_PATT3_ATTHIZ3_2 0x04000000U
4646 #define FMC_PATT3_ATTHIZ3_3 0x08000000U
4647 #define FMC_PATT3_ATTHIZ3_4 0x10000000U
4648 #define FMC_PATT3_ATTHIZ3_5 0x20000000U
4649 #define FMC_PATT3_ATTHIZ3_6 0x40000000U
4650 #define FMC_PATT3_ATTHIZ3_7 0x80000000U
4652 /****************** Bit definition for FMC_PATT4 register ******************/
4653 #define FMC_PATT4_ATTSET4 0x000000FFU
4654 #define FMC_PATT4_ATTSET4_0 0x00000001U
4655 #define FMC_PATT4_ATTSET4_1 0x00000002U
4656 #define FMC_PATT4_ATTSET4_2 0x00000004U
4657 #define FMC_PATT4_ATTSET4_3 0x00000008U
4658 #define FMC_PATT4_ATTSET4_4 0x00000010U
4659 #define FMC_PATT4_ATTSET4_5 0x00000020U
4660 #define FMC_PATT4_ATTSET4_6 0x00000040U
4661 #define FMC_PATT4_ATTSET4_7 0x00000080U
4663 #define FMC_PATT4_ATTWAIT4 0x0000FF00U
4664 #define FMC_PATT4_ATTWAIT4_0 0x00000100U
4665 #define FMC_PATT4_ATTWAIT4_1 0x00000200U
4666 #define FMC_PATT4_ATTWAIT4_2 0x00000400U
4667 #define FMC_PATT4_ATTWAIT4_3 0x00000800U
4668 #define FMC_PATT4_ATTWAIT4_4 0x00001000U
4669 #define FMC_PATT4_ATTWAIT4_5 0x00002000U
4670 #define FMC_PATT4_ATTWAIT4_6 0x00004000U
4671 #define FMC_PATT4_ATTWAIT4_7 0x00008000U
4673 #define FMC_PATT4_ATTHOLD4 0x00FF0000U
4674 #define FMC_PATT4_ATTHOLD4_0 0x00010000U
4675 #define FMC_PATT4_ATTHOLD4_1 0x00020000U
4676 #define FMC_PATT4_ATTHOLD4_2 0x00040000U
4677 #define FMC_PATT4_ATTHOLD4_3 0x00080000U
4678 #define FMC_PATT4_ATTHOLD4_4 0x00100000U
4679 #define FMC_PATT4_ATTHOLD4_5 0x00200000U
4680 #define FMC_PATT4_ATTHOLD4_6 0x00400000U
4681 #define FMC_PATT4_ATTHOLD4_7 0x00800000U
4683 #define FMC_PATT4_ATTHIZ4 0xFF000000U
4684 #define FMC_PATT4_ATTHIZ4_0 0x01000000U
4685 #define FMC_PATT4_ATTHIZ4_1 0x02000000U
4686 #define FMC_PATT4_ATTHIZ4_2 0x04000000U
4687 #define FMC_PATT4_ATTHIZ4_3 0x08000000U
4688 #define FMC_PATT4_ATTHIZ4_4 0x10000000U
4689 #define FMC_PATT4_ATTHIZ4_5 0x20000000U
4690 #define FMC_PATT4_ATTHIZ4_6 0x40000000U
4691 #define FMC_PATT4_ATTHIZ4_7 0x80000000U
4693 /****************** Bit definition for FMC_PIO4 register *******************/
4694 #define FMC_PIO4_IOSET4 0x000000FFU
4695 #define FMC_PIO4_IOSET4_0 0x00000001U
4696 #define FMC_PIO4_IOSET4_1 0x00000002U
4697 #define FMC_PIO4_IOSET4_2 0x00000004U
4698 #define FMC_PIO4_IOSET4_3 0x00000008U
4699 #define FMC_PIO4_IOSET4_4 0x00000010U
4700 #define FMC_PIO4_IOSET4_5 0x00000020U
4701 #define FMC_PIO4_IOSET4_6 0x00000040U
4702 #define FMC_PIO4_IOSET4_7 0x00000080U
4704 #define FMC_PIO4_IOWAIT4 0x0000FF00U
4705 #define FMC_PIO4_IOWAIT4_0 0x00000100U
4706 #define FMC_PIO4_IOWAIT4_1 0x00000200U
4707 #define FMC_PIO4_IOWAIT4_2 0x00000400U
4708 #define FMC_PIO4_IOWAIT4_3 0x00000800U
4709 #define FMC_PIO4_IOWAIT4_4 0x00001000U
4710 #define FMC_PIO4_IOWAIT4_5 0x00002000U
4711 #define FMC_PIO4_IOWAIT4_6 0x00004000U
4712 #define FMC_PIO4_IOWAIT4_7 0x00008000U
4714 #define FMC_PIO4_IOHOLD4 0x00FF0000U
4715 #define FMC_PIO4_IOHOLD4_0 0x00010000U
4716 #define FMC_PIO4_IOHOLD4_1 0x00020000U
4717 #define FMC_PIO4_IOHOLD4_2 0x00040000U
4718 #define FMC_PIO4_IOHOLD4_3 0x00080000U
4719 #define FMC_PIO4_IOHOLD4_4 0x00100000U
4720 #define FMC_PIO4_IOHOLD4_5 0x00200000U
4721 #define FMC_PIO4_IOHOLD4_6 0x00400000U
4722 #define FMC_PIO4_IOHOLD4_7 0x00800000U
4724 #define FMC_PIO4_IOHIZ4 0xFF000000U
4725 #define FMC_PIO4_IOHIZ4_0 0x01000000U
4726 #define FMC_PIO4_IOHIZ4_1 0x02000000U
4727 #define FMC_PIO4_IOHIZ4_2 0x04000000U
4728 #define FMC_PIO4_IOHIZ4_3 0x08000000U
4729 #define FMC_PIO4_IOHIZ4_4 0x10000000U
4730 #define FMC_PIO4_IOHIZ4_5 0x20000000U
4731 #define FMC_PIO4_IOHIZ4_6 0x40000000U
4732 #define FMC_PIO4_IOHIZ4_7 0x80000000U
4734 /****************** Bit definition for FMC_ECCR2 register ******************/
4735 #define FMC_ECCR2_ECC2 0xFFFFFFFFU
4737 /****************** Bit definition for FMC_ECCR3 register ******************/
4738 #define FMC_ECCR3_ECC3 0xFFFFFFFFU
4740 /****************** Bit definition for FMC_SDCR1 register ******************/
4741 #define FMC_SDCR1_NC 0x00000003U
4742 #define FMC_SDCR1_NC_0 0x00000001U
4743 #define FMC_SDCR1_NC_1 0x00000002U
4745 #define FMC_SDCR1_NR 0x0000000CU
4746 #define FMC_SDCR1_NR_0 0x00000004U
4747 #define FMC_SDCR1_NR_1 0x00000008U
4749 #define FMC_SDCR1_MWID 0x00000030U
4750 #define FMC_SDCR1_MWID_0 0x00000010U
4751 #define FMC_SDCR1_MWID_1 0x00000020U
4753 #define FMC_SDCR1_NB 0x00000040U
4755 #define FMC_SDCR1_CAS 0x00000180U
4756 #define FMC_SDCR1_CAS_0 0x00000080U
4757 #define FMC_SDCR1_CAS_1 0x00000100U
4759 #define FMC_SDCR1_WP 0x00000200U
4761 #define FMC_SDCR1_SDCLK 0x00000C00U
4762 #define FMC_SDCR1_SDCLK_0 0x00000400U
4763 #define FMC_SDCR1_SDCLK_1 0x00000800U
4765 #define FMC_SDCR1_RBURST 0x00001000U
4767 #define FMC_SDCR1_RPIPE 0x00006000U
4768 #define FMC_SDCR1_RPIPE_0 0x00002000U
4769 #define FMC_SDCR1_RPIPE_1 0x00004000U
4771 /****************** Bit definition for FMC_SDCR2 register ******************/
4772 #define FMC_SDCR2_NC 0x00000003U
4773 #define FMC_SDCR2_NC_0 0x00000001U
4774 #define FMC_SDCR2_NC_1 0x00000002U
4776 #define FMC_SDCR2_NR 0x0000000CU
4777 #define FMC_SDCR2_NR_0 0x00000004U
4778 #define FMC_SDCR2_NR_1 0x00000008U
4780 #define FMC_SDCR2_MWID 0x00000030U
4781 #define FMC_SDCR2_MWID_0 0x00000010U
4782 #define FMC_SDCR2_MWID_1 0x00000020U
4784 #define FMC_SDCR2_NB 0x00000040U
4786 #define FMC_SDCR2_CAS 0x00000180U
4787 #define FMC_SDCR2_CAS_0 0x00000080U
4788 #define FMC_SDCR2_CAS_1 0x00000100U
4790 #define FMC_SDCR2_WP 0x00000200U
4792 #define FMC_SDCR2_SDCLK 0x00000C00U
4793 #define FMC_SDCR2_SDCLK_0 0x00000400U
4794 #define FMC_SDCR2_SDCLK_1 0x00000800U
4796 #define FMC_SDCR2_RBURST 0x00001000U
4798 #define FMC_SDCR2_RPIPE 0x00006000U
4799 #define FMC_SDCR2_RPIPE_0 0x00002000U
4800 #define FMC_SDCR2_RPIPE_1 0x00004000U
4802 /****************** Bit definition for FMC_SDTR1 register ******************/
4803 #define FMC_SDTR1_TMRD 0x0000000FU
4804 #define FMC_SDTR1_TMRD_0 0x00000001U
4805 #define FMC_SDTR1_TMRD_1 0x00000002U
4806 #define FMC_SDTR1_TMRD_2 0x00000004U
4807 #define FMC_SDTR1_TMRD_3 0x00000008U
4809 #define FMC_SDTR1_TXSR 0x000000F0U
4810 #define FMC_SDTR1_TXSR_0 0x00000010U
4811 #define FMC_SDTR1_TXSR_1 0x00000020U
4812 #define FMC_SDTR1_TXSR_2 0x00000040U
4813 #define FMC_SDTR1_TXSR_3 0x00000080U
4815 #define FMC_SDTR1_TRAS 0x00000F00U
4816 #define FMC_SDTR1_TRAS_0 0x00000100U
4817 #define FMC_SDTR1_TRAS_1 0x00000200U
4818 #define FMC_SDTR1_TRAS_2 0x00000400U
4819 #define FMC_SDTR1_TRAS_3 0x00000800U
4821 #define FMC_SDTR1_TRC 0x0000F000U
4822 #define FMC_SDTR1_TRC_0 0x00001000U
4823 #define FMC_SDTR1_TRC_1 0x00002000U
4824 #define FMC_SDTR1_TRC_2 0x00004000U
4826 #define FMC_SDTR1_TWR 0x000F0000U
4827 #define FMC_SDTR1_TWR_0 0x00010000U
4828 #define FMC_SDTR1_TWR_1 0x00020000U
4829 #define FMC_SDTR1_TWR_2 0x00040000U
4831 #define FMC_SDTR1_TRP 0x00F00000U
4832 #define FMC_SDTR1_TRP_0 0x00100000U
4833 #define FMC_SDTR1_TRP_1 0x00200000U
4834 #define FMC_SDTR1_TRP_2 0x00400000U
4836 #define FMC_SDTR1_TRCD 0x0F000000U
4837 #define FMC_SDTR1_TRCD_0 0x01000000U
4838 #define FMC_SDTR1_TRCD_1 0x02000000U
4839 #define FMC_SDTR1_TRCD_2 0x04000000U
4841 /****************** Bit definition for FMC_SDTR2 register ******************/
4842 #define FMC_SDTR2_TMRD 0x0000000FU
4843 #define FMC_SDTR2_TMRD_0 0x00000001U
4844 #define FMC_SDTR2_TMRD_1 0x00000002U
4845 #define FMC_SDTR2_TMRD_2 0x00000004U
4846 #define FMC_SDTR2_TMRD_3 0x00000008U
4848 #define FMC_SDTR2_TXSR 0x000000F0U
4849 #define FMC_SDTR2_TXSR_0 0x00000010U
4850 #define FMC_SDTR2_TXSR_1 0x00000020U
4851 #define FMC_SDTR2_TXSR_2 0x00000040U
4852 #define FMC_SDTR2_TXSR_3 0x00000080U
4854 #define FMC_SDTR2_TRAS 0x00000F00U
4855 #define FMC_SDTR2_TRAS_0 0x00000100U
4856 #define FMC_SDTR2_TRAS_1 0x00000200U
4857 #define FMC_SDTR2_TRAS_2 0x00000400U
4858 #define FMC_SDTR2_TRAS_3 0x00000800U
4860 #define FMC_SDTR2_TRC 0x0000F000U
4861 #define FMC_SDTR2_TRC_0 0x00001000U
4862 #define FMC_SDTR2_TRC_1 0x00002000U
4863 #define FMC_SDTR2_TRC_2 0x00004000U
4865 #define FMC_SDTR2_TWR 0x000F0000U
4866 #define FMC_SDTR2_TWR_0 0x00010000U
4867 #define FMC_SDTR2_TWR_1 0x00020000U
4868 #define FMC_SDTR2_TWR_2 0x00040000U
4870 #define FMC_SDTR2_TRP 0x00F00000U
4871 #define FMC_SDTR2_TRP_0 0x00100000U
4872 #define FMC_SDTR2_TRP_1 0x00200000U
4873 #define FMC_SDTR2_TRP_2 0x00400000U
4875 #define FMC_SDTR2_TRCD 0x0F000000U
4876 #define FMC_SDTR2_TRCD_0 0x01000000U
4877 #define FMC_SDTR2_TRCD_1 0x02000000U
4878 #define FMC_SDTR2_TRCD_2 0x04000000U
4880 /****************** Bit definition for FMC_SDCMR register ******************/
4881 #define FMC_SDCMR_MODE 0x00000007U
4882 #define FMC_SDCMR_MODE_0 0x00000001U
4883 #define FMC_SDCMR_MODE_1 0x00000002U
4884 #define FMC_SDCMR_MODE_2 0x00000004U
4886 #define FMC_SDCMR_CTB2 0x00000008U
4888 #define FMC_SDCMR_CTB1 0x00000010U
4890 #define FMC_SDCMR_NRFS 0x000001E0U
4891 #define FMC_SDCMR_NRFS_0 0x00000020U
4892 #define FMC_SDCMR_NRFS_1 0x00000040U
4893 #define FMC_SDCMR_NRFS_2 0x00000080U
4894 #define FMC_SDCMR_NRFS_3 0x00000100U
4896 #define FMC_SDCMR_MRD 0x003FFE00U
4898 /****************** Bit definition for FMC_SDRTR register ******************/
4899 #define FMC_SDRTR_CRE 0x00000001U
4901 #define FMC_SDRTR_COUNT 0x00003FFEU
4903 #define FMC_SDRTR_REIE 0x00004000U
4905 /****************** Bit definition for FMC_SDSR register ******************/
4906 #define FMC_SDSR_RE 0x00000001U
4908 #define FMC_SDSR_MODES1 0x00000006U
4909 #define FMC_SDSR_MODES1_0 0x00000002U
4910 #define FMC_SDSR_MODES1_1 0x00000004U
4912 #define FMC_SDSR_MODES2 0x00000018U
4913 #define FMC_SDSR_MODES2_0 0x00000008U
4914 #define FMC_SDSR_MODES2_1 0x00000010U
4915 #define FMC_SDSR_BUSY 0x00000020U
4919 /******************************************************************************/
4920 /* */
4921 /* General Purpose I/O */
4922 /* */
4923 /******************************************************************************/
4924 /****************** Bits definition for GPIO_MODER register *****************/
4925 #define GPIO_MODER_MODER0 0x00000003U
4926 #define GPIO_MODER_MODER0_0 0x00000001U
4927 #define GPIO_MODER_MODER0_1 0x00000002U
4928 
4929 #define GPIO_MODER_MODER1 0x0000000CU
4930 #define GPIO_MODER_MODER1_0 0x00000004U
4931 #define GPIO_MODER_MODER1_1 0x00000008U
4932 
4933 #define GPIO_MODER_MODER2 0x00000030U
4934 #define GPIO_MODER_MODER2_0 0x00000010U
4935 #define GPIO_MODER_MODER2_1 0x00000020U
4936 
4937 #define GPIO_MODER_MODER3 0x000000C0U
4938 #define GPIO_MODER_MODER3_0 0x00000040U
4939 #define GPIO_MODER_MODER3_1 0x00000080U
4940 
4941 #define GPIO_MODER_MODER4 0x00000300U
4942 #define GPIO_MODER_MODER4_0 0x00000100U
4943 #define GPIO_MODER_MODER4_1 0x00000200U
4944 
4945 #define GPIO_MODER_MODER5 0x00000C00U
4946 #define GPIO_MODER_MODER5_0 0x00000400U
4947 #define GPIO_MODER_MODER5_1 0x00000800U
4948 
4949 #define GPIO_MODER_MODER6 0x00003000U
4950 #define GPIO_MODER_MODER6_0 0x00001000U
4951 #define GPIO_MODER_MODER6_1 0x00002000U
4952 
4953 #define GPIO_MODER_MODER7 0x0000C000U
4954 #define GPIO_MODER_MODER7_0 0x00004000U
4955 #define GPIO_MODER_MODER7_1 0x00008000U
4956 
4957 #define GPIO_MODER_MODER8 0x00030000U
4958 #define GPIO_MODER_MODER8_0 0x00010000U
4959 #define GPIO_MODER_MODER8_1 0x00020000U
4960 
4961 #define GPIO_MODER_MODER9 0x000C0000U
4962 #define GPIO_MODER_MODER9_0 0x00040000U
4963 #define GPIO_MODER_MODER9_1 0x00080000U
4964 
4965 #define GPIO_MODER_MODER10 0x00300000U
4966 #define GPIO_MODER_MODER10_0 0x00100000U
4967 #define GPIO_MODER_MODER10_1 0x00200000U
4968 
4969 #define GPIO_MODER_MODER11 0x00C00000U
4970 #define GPIO_MODER_MODER11_0 0x00400000U
4971 #define GPIO_MODER_MODER11_1 0x00800000U
4972 
4973 #define GPIO_MODER_MODER12 0x03000000U
4974 #define GPIO_MODER_MODER12_0 0x01000000U
4975 #define GPIO_MODER_MODER12_1 0x02000000U
4976 
4977 #define GPIO_MODER_MODER13 0x0C000000U
4978 #define GPIO_MODER_MODER13_0 0x04000000U
4979 #define GPIO_MODER_MODER13_1 0x08000000U
4980 
4981 #define GPIO_MODER_MODER14 0x30000000U
4982 #define GPIO_MODER_MODER14_0 0x10000000U
4983 #define GPIO_MODER_MODER14_1 0x20000000U
4984 
4985 #define GPIO_MODER_MODER15 0xC0000000U
4986 #define GPIO_MODER_MODER15_0 0x40000000U
4987 #define GPIO_MODER_MODER15_1 0x80000000U
4988 
4989 /****************** Bits definition for GPIO_OTYPER register ****************/
4990 #define GPIO_OTYPER_OT_0 0x00000001U
4991 #define GPIO_OTYPER_OT_1 0x00000002U
4992 #define GPIO_OTYPER_OT_2 0x00000004U
4993 #define GPIO_OTYPER_OT_3 0x00000008U
4994 #define GPIO_OTYPER_OT_4 0x00000010U
4995 #define GPIO_OTYPER_OT_5 0x00000020U
4996 #define GPIO_OTYPER_OT_6 0x00000040U
4997 #define GPIO_OTYPER_OT_7 0x00000080U
4998 #define GPIO_OTYPER_OT_8 0x00000100U
4999 #define GPIO_OTYPER_OT_9 0x00000200U
5000 #define GPIO_OTYPER_OT_10 0x00000400U
5001 #define GPIO_OTYPER_OT_11 0x00000800U
5002 #define GPIO_OTYPER_OT_12 0x00001000U
5003 #define GPIO_OTYPER_OT_13 0x00002000U
5004 #define GPIO_OTYPER_OT_14 0x00004000U
5005 #define GPIO_OTYPER_OT_15 0x00008000U
5006 
5007 /****************** Bits definition for GPIO_OSPEEDR register ***************/
5008 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
5009 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
5010 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
5011 
5012 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
5013 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
5014 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
5015 
5016 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
5017 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
5018 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
5019 
5020 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
5021 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
5022 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
5023 
5024 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
5025 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
5026 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
5027 
5028 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
5029 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
5030 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
5031 
5032 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
5033 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
5034 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
5035 
5036 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
5037 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
5038 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
5039 
5040 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
5041 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
5042 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
5043 
5044 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
5045 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
5046 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
5047 
5048 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
5049 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
5050 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
5051 
5052 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
5053 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
5054 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
5055 
5056 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
5057 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
5058 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
5059 
5060 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
5061 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
5062 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
5063 
5064 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
5065 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
5066 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
5067 
5068 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
5069 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
5070 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
5071 
5072 /****************** Bits definition for GPIO_PUPDR register *****************/
5073 #define GPIO_PUPDR_PUPDR0 0x00000003U
5074 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
5075 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
5076 
5077 #define GPIO_PUPDR_PUPDR1 0x0000000CU
5078 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
5079 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
5080 
5081 #define GPIO_PUPDR_PUPDR2 0x00000030U
5082 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
5083 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
5084 
5085 #define GPIO_PUPDR_PUPDR3 0x000000C0U
5086 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
5087 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
5088 
5089 #define GPIO_PUPDR_PUPDR4 0x00000300U
5090 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
5091 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
5092 
5093 #define GPIO_PUPDR_PUPDR5 0x00000C00U
5094 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
5095 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
5096 
5097 #define GPIO_PUPDR_PUPDR6 0x00003000U
5098 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
5099 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
5100 
5101 #define GPIO_PUPDR_PUPDR7 0x0000C000U
5102 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
5103 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
5104 
5105 #define GPIO_PUPDR_PUPDR8 0x00030000U
5106 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
5107 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
5108 
5109 #define GPIO_PUPDR_PUPDR9 0x000C0000U
5110 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
5111 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
5112 
5113 #define GPIO_PUPDR_PUPDR10 0x00300000U
5114 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
5115 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
5116 
5117 #define GPIO_PUPDR_PUPDR11 0x00C00000U
5118 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
5119 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
5120 
5121 #define GPIO_PUPDR_PUPDR12 0x03000000U
5122 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
5123 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
5124 
5125 #define GPIO_PUPDR_PUPDR13 0x0C000000U
5126 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
5127 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
5128 
5129 #define GPIO_PUPDR_PUPDR14 0x30000000U
5130 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
5131 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
5132 
5133 #define GPIO_PUPDR_PUPDR15 0xC0000000U
5134 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
5135 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
5136 
5137 /****************** Bits definition for GPIO_IDR register *******************/
5138 #define GPIO_IDR_IDR_0 0x00000001U
5139 #define GPIO_IDR_IDR_1 0x00000002U
5140 #define GPIO_IDR_IDR_2 0x00000004U
5141 #define GPIO_IDR_IDR_3 0x00000008U
5142 #define GPIO_IDR_IDR_4 0x00000010U
5143 #define GPIO_IDR_IDR_5 0x00000020U
5144 #define GPIO_IDR_IDR_6 0x00000040U
5145 #define GPIO_IDR_IDR_7 0x00000080U
5146 #define GPIO_IDR_IDR_8 0x00000100U
5147 #define GPIO_IDR_IDR_9 0x00000200U
5148 #define GPIO_IDR_IDR_10 0x00000400U
5149 #define GPIO_IDR_IDR_11 0x00000800U
5150 #define GPIO_IDR_IDR_12 0x00001000U
5151 #define GPIO_IDR_IDR_13 0x00002000U
5152 #define GPIO_IDR_IDR_14 0x00004000U
5153 #define GPIO_IDR_IDR_15 0x00008000U
5154 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5155 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
5156 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
5157 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
5158 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
5159 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
5160 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
5161 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
5162 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
5163 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
5164 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
5165 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
5166 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
5167 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
5168 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
5169 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
5170 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
5171 
5172 /****************** Bits definition for GPIO_ODR register *******************/
5173 #define GPIO_ODR_ODR_0 0x00000001U
5174 #define GPIO_ODR_ODR_1 0x00000002U
5175 #define GPIO_ODR_ODR_2 0x00000004U
5176 #define GPIO_ODR_ODR_3 0x00000008U
5177 #define GPIO_ODR_ODR_4 0x00000010U
5178 #define GPIO_ODR_ODR_5 0x00000020U
5179 #define GPIO_ODR_ODR_6 0x00000040U
5180 #define GPIO_ODR_ODR_7 0x00000080U
5181 #define GPIO_ODR_ODR_8 0x00000100U
5182 #define GPIO_ODR_ODR_9 0x00000200U
5183 #define GPIO_ODR_ODR_10 0x00000400U
5184 #define GPIO_ODR_ODR_11 0x00000800U
5185 #define GPIO_ODR_ODR_12 0x00001000U
5186 #define GPIO_ODR_ODR_13 0x00002000U
5187 #define GPIO_ODR_ODR_14 0x00004000U
5188 #define GPIO_ODR_ODR_15 0x00008000U
5189 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
5190 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
5191 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
5192 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
5193 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
5194 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
5195 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
5196 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
5197 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
5198 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
5199 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
5200 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
5201 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
5202 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
5203 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
5204 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
5205 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
5206 
5207 /****************** Bits definition for GPIO_BSRR register ******************/
5208 #define GPIO_BSRR_BS_0 0x00000001U
5209 #define GPIO_BSRR_BS_1 0x00000002U
5210 #define GPIO_BSRR_BS_2 0x00000004U
5211 #define GPIO_BSRR_BS_3 0x00000008U
5212 #define GPIO_BSRR_BS_4 0x00000010U
5213 #define GPIO_BSRR_BS_5 0x00000020U
5214 #define GPIO_BSRR_BS_6 0x00000040U
5215 #define GPIO_BSRR_BS_7 0x00000080U
5216 #define GPIO_BSRR_BS_8 0x00000100U
5217 #define GPIO_BSRR_BS_9 0x00000200U
5218 #define GPIO_BSRR_BS_10 0x00000400U
5219 #define GPIO_BSRR_BS_11 0x00000800U
5220 #define GPIO_BSRR_BS_12 0x00001000U
5221 #define GPIO_BSRR_BS_13 0x00002000U
5222 #define GPIO_BSRR_BS_14 0x00004000U
5223 #define GPIO_BSRR_BS_15 0x00008000U
5224 #define GPIO_BSRR_BR_0 0x00010000U
5225 #define GPIO_BSRR_BR_1 0x00020000U
5226 #define GPIO_BSRR_BR_2 0x00040000U
5227 #define GPIO_BSRR_BR_3 0x00080000U
5228 #define GPIO_BSRR_BR_4 0x00100000U
5229 #define GPIO_BSRR_BR_5 0x00200000U
5230 #define GPIO_BSRR_BR_6 0x00400000U
5231 #define GPIO_BSRR_BR_7 0x00800000U
5232 #define GPIO_BSRR_BR_8 0x01000000U
5233 #define GPIO_BSRR_BR_9 0x02000000U
5234 #define GPIO_BSRR_BR_10 0x04000000U
5235 #define GPIO_BSRR_BR_11 0x08000000U
5236 #define GPIO_BSRR_BR_12 0x10000000U
5237 #define GPIO_BSRR_BR_13 0x20000000U
5238 #define GPIO_BSRR_BR_14 0x40000000U
5239 #define GPIO_BSRR_BR_15 0x80000000U
5240 
5241 /****************** Bit definition for GPIO_LCKR register *********************/
5242 #define GPIO_LCKR_LCK0 0x00000001U
5243 #define GPIO_LCKR_LCK1 0x00000002U
5244 #define GPIO_LCKR_LCK2 0x00000004U
5245 #define GPIO_LCKR_LCK3 0x00000008U
5246 #define GPIO_LCKR_LCK4 0x00000010U
5247 #define GPIO_LCKR_LCK5 0x00000020U
5248 #define GPIO_LCKR_LCK6 0x00000040U
5249 #define GPIO_LCKR_LCK7 0x00000080U
5250 #define GPIO_LCKR_LCK8 0x00000100U
5251 #define GPIO_LCKR_LCK9 0x00000200U
5252 #define GPIO_LCKR_LCK10 0x00000400U
5253 #define GPIO_LCKR_LCK11 0x00000800U
5254 #define GPIO_LCKR_LCK12 0x00001000U
5255 #define GPIO_LCKR_LCK13 0x00002000U
5256 #define GPIO_LCKR_LCK14 0x00004000U
5257 #define GPIO_LCKR_LCK15 0x00008000U
5258 #define GPIO_LCKR_LCKK 0x00010000U
5259 
5260 /******************************************************************************/
5261 /* */
5262 /* HASH */
5263 /* */
5264 /******************************************************************************/
5265 /****************** Bits definition for HASH_CR register ********************/
5266 #define HASH_CR_INIT 0x00000004U
5267 #define HASH_CR_DMAE 0x00000008U
5268 #define HASH_CR_DATATYPE 0x00000030U
5269 #define HASH_CR_DATATYPE_0 0x00000010U
5270 #define HASH_CR_DATATYPE_1 0x00000020U
5271 #define HASH_CR_MODE 0x00000040U
5272 #define HASH_CR_ALGO 0x00040080U
5273 #define HASH_CR_ALGO_0 0x00000080U
5274 #define HASH_CR_ALGO_1 0x00040000U
5275 #define HASH_CR_NBW 0x00000F00U
5276 #define HASH_CR_NBW_0 0x00000100U
5277 #define HASH_CR_NBW_1 0x00000200U
5278 #define HASH_CR_NBW_2 0x00000400U
5279 #define HASH_CR_NBW_3 0x00000800U
5280 #define HASH_CR_DINNE 0x00001000U
5281 #define HASH_CR_MDMAT 0x00002000U
5282 #define HASH_CR_LKEY 0x00010000U
5283 
5284 /****************** Bits definition for HASH_STR register *******************/
5285 #define HASH_STR_NBLW 0x0000001FU
5286 #define HASH_STR_NBLW_0 0x00000001U
5287 #define HASH_STR_NBLW_1 0x00000002U
5288 #define HASH_STR_NBLW_2 0x00000004U
5289 #define HASH_STR_NBLW_3 0x00000008U
5290 #define HASH_STR_NBLW_4 0x00000010U
5291 #define HASH_STR_DCAL 0x00000100U
5292 /* Aliases for HASH_STR register */
5293 #define HASH_STR_NBW HASH_STR_NBLW
5294 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
5295 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
5296 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
5297 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
5298 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
5299 
5300 /****************** Bits definition for HASH_IMR register *******************/
5301 #define HASH_IMR_DINIE 0x00000001U
5302 #define HASH_IMR_DCIE 0x00000002U
5303 /* Aliases for HASH_IMR register */
5304 #define HASH_IMR_DINIM HASH_IMR_DINIE
5305 #define HASH_IMR_DCIM HASH_IMR_DCIE
5306 
5307 /****************** Bits definition for HASH_SR register ********************/
5308 #define HASH_SR_DINIS 0x00000001U
5309 #define HASH_SR_DCIS 0x00000002U
5310 #define HASH_SR_DMAS 0x00000004U
5311 #define HASH_SR_BUSY 0x00000008U
5312 
5313 /******************************************************************************/
5314 /* */
5315 /* Inter-integrated Circuit Interface */
5316 /* */
5317 /******************************************************************************/
5318 /******************* Bit definition for I2C_CR1 register ********************/
5319 #define I2C_CR1_PE 0x00000001U
5320 #define I2C_CR1_SMBUS 0x00000002U
5321 #define I2C_CR1_SMBTYPE 0x00000008U
5322 #define I2C_CR1_ENARP 0x00000010U
5323 #define I2C_CR1_ENPEC 0x00000020U
5324 #define I2C_CR1_ENGC 0x00000040U
5325 #define I2C_CR1_NOSTRETCH 0x00000080U
5326 #define I2C_CR1_START 0x00000100U
5327 #define I2C_CR1_STOP 0x00000200U
5328 #define I2C_CR1_ACK 0x00000400U
5329 #define I2C_CR1_POS 0x00000800U
5330 #define I2C_CR1_PEC 0x00001000U
5331 #define I2C_CR1_ALERT 0x00002000U
5332 #define I2C_CR1_SWRST 0x00008000U
5334 /******************* Bit definition for I2C_CR2 register ********************/
5335 #define I2C_CR2_FREQ 0x0000003FU
5336 #define I2C_CR2_FREQ_0 0x00000001U
5337 #define I2C_CR2_FREQ_1 0x00000002U
5338 #define I2C_CR2_FREQ_2 0x00000004U
5339 #define I2C_CR2_FREQ_3 0x00000008U
5340 #define I2C_CR2_FREQ_4 0x00000010U
5341 #define I2C_CR2_FREQ_5 0x00000020U
5343 #define I2C_CR2_ITERREN 0x00000100U
5344 #define I2C_CR2_ITEVTEN 0x00000200U
5345 #define I2C_CR2_ITBUFEN 0x00000400U
5346 #define I2C_CR2_DMAEN 0x00000800U
5347 #define I2C_CR2_LAST 0x00001000U
5349 /******************* Bit definition for I2C_OAR1 register *******************/
5350 #define I2C_OAR1_ADD1_7 0x000000FEU
5351 #define I2C_OAR1_ADD8_9 0x00000300U
5353 #define I2C_OAR1_ADD0 0x00000001U
5354 #define I2C_OAR1_ADD1 0x00000002U
5355 #define I2C_OAR1_ADD2 0x00000004U
5356 #define I2C_OAR1_ADD3 0x00000008U
5357 #define I2C_OAR1_ADD4 0x00000010U
5358 #define I2C_OAR1_ADD5 0x00000020U
5359 #define I2C_OAR1_ADD6 0x00000040U
5360 #define I2C_OAR1_ADD7 0x00000080U
5361 #define I2C_OAR1_ADD8 0x00000100U
5362 #define I2C_OAR1_ADD9 0x00000200U
5364 #define I2C_OAR1_ADDMODE 0x00008000U
5366 /******************* Bit definition for I2C_OAR2 register *******************/
5367 #define I2C_OAR2_ENDUAL 0x00000001U
5368 #define I2C_OAR2_ADD2 0x000000FEU
5370 /******************** Bit definition for I2C_DR register ********************/
5371 #define I2C_DR_DR 0x000000FFU
5373 /******************* Bit definition for I2C_SR1 register ********************/
5374 #define I2C_SR1_SB 0x00000001U
5375 #define I2C_SR1_ADDR 0x00000002U
5376 #define I2C_SR1_BTF 0x00000004U
5377 #define I2C_SR1_ADD10 0x00000008U
5378 #define I2C_SR1_STOPF 0x00000010U
5379 #define I2C_SR1_RXNE 0x00000040U
5380 #define I2C_SR1_TXE 0x00000080U
5381 #define I2C_SR1_BERR 0x00000100U
5382 #define I2C_SR1_ARLO 0x00000200U
5383 #define I2C_SR1_AF 0x00000400U
5384 #define I2C_SR1_OVR 0x00000800U
5385 #define I2C_SR1_PECERR 0x00001000U
5386 #define I2C_SR1_TIMEOUT 0x00004000U
5387 #define I2C_SR1_SMBALERT 0x00008000U
5389 /******************* Bit definition for I2C_SR2 register ********************/
5390 #define I2C_SR2_MSL 0x00000001U
5391 #define I2C_SR2_BUSY 0x00000002U
5392 #define I2C_SR2_TRA 0x00000004U
5393 #define I2C_SR2_GENCALL 0x00000010U
5394 #define I2C_SR2_SMBDEFAULT 0x00000020U
5395 #define I2C_SR2_SMBHOST 0x00000040U
5396 #define I2C_SR2_DUALF 0x00000080U
5397 #define I2C_SR2_PEC 0x0000FF00U
5399 /******************* Bit definition for I2C_CCR register ********************/
5400 #define I2C_CCR_CCR 0x00000FFFU
5401 #define I2C_CCR_DUTY 0x00004000U
5402 #define I2C_CCR_FS 0x00008000U
5404 /****************** Bit definition for I2C_TRISE register *******************/
5405 #define I2C_TRISE_TRISE 0x0000003FU
5407 /****************** Bit definition for I2C_FLTR register *******************/
5408 #define I2C_FLTR_DNF 0x0000000FU
5409 #define I2C_FLTR_ANOFF 0x00000010U
5411 /******************************************************************************/
5412 /* */
5413 /* Independent WATCHDOG */
5414 /* */
5415 /******************************************************************************/
5416 /******************* Bit definition for IWDG_KR register ********************/
5417 #define IWDG_KR_KEY 0xFFFFU
5419 /******************* Bit definition for IWDG_PR register ********************/
5420 #define IWDG_PR_PR 0x07U
5421 #define IWDG_PR_PR_0 0x01U
5422 #define IWDG_PR_PR_1 0x02U
5423 #define IWDG_PR_PR_2 0x04U
5425 /******************* Bit definition for IWDG_RLR register *******************/
5426 #define IWDG_RLR_RL 0x0FFFU
5428 /******************* Bit definition for IWDG_SR register ********************/
5429 #define IWDG_SR_PVU 0x01U
5430 #define IWDG_SR_RVU 0x02U
5432 /******************************************************************************/
5433 /* */
5434 /* Power Control */
5435 /* */
5436 /******************************************************************************/
5437 /******************** Bit definition for PWR_CR register ********************/
5438 #define PWR_CR_LPDS 0x00000001U
5439 #define PWR_CR_PDDS 0x00000002U
5440 #define PWR_CR_CWUF 0x00000004U
5441 #define PWR_CR_CSBF 0x00000008U
5442 #define PWR_CR_PVDE 0x00000010U
5444 #define PWR_CR_PLS 0x000000E0U
5445 #define PWR_CR_PLS_0 0x00000020U
5446 #define PWR_CR_PLS_1 0x00000040U
5447 #define PWR_CR_PLS_2 0x00000080U
5450 #define PWR_CR_PLS_LEV0 0x00000000U
5451 #define PWR_CR_PLS_LEV1 0x00000020U
5452 #define PWR_CR_PLS_LEV2 0x00000040U
5453 #define PWR_CR_PLS_LEV3 0x00000060U
5454 #define PWR_CR_PLS_LEV4 0x00000080U
5455 #define PWR_CR_PLS_LEV5 0x000000A0U
5456 #define PWR_CR_PLS_LEV6 0x000000C0U
5457 #define PWR_CR_PLS_LEV7 0x000000E0U
5458 #define PWR_CR_DBP 0x00000100U
5459 #define PWR_CR_FPDS 0x00000200U
5460 #define PWR_CR_LPLVDS 0x00000400U
5461 #define PWR_CR_MRLVDS 0x00000800U
5462 #define PWR_CR_ADCDC1 0x00002000U
5463 #define PWR_CR_VOS 0x0000C000U
5464 #define PWR_CR_VOS_0 0x00004000U
5465 #define PWR_CR_VOS_1 0x00008000U
5466 #define PWR_CR_ODEN 0x00010000U
5467 #define PWR_CR_ODSWEN 0x00020000U
5468 #define PWR_CR_UDEN 0x000C0000U
5469 #define PWR_CR_UDEN_0 0x00040000U
5470 #define PWR_CR_UDEN_1 0x00080000U
5472 /* Legacy define */
5473 #define PWR_CR_PMODE PWR_CR_VOS
5474 #define PWR_CR_LPUDS PWR_CR_LPLVDS
5475 #define PWR_CR_MRUDS PWR_CR_MRLVDS
5477 /******************* Bit definition for PWR_CSR register ********************/
5478 #define PWR_CSR_WUF 0x00000001U
5479 #define PWR_CSR_SBF 0x00000002U
5480 #define PWR_CSR_PVDO 0x00000004U
5481 #define PWR_CSR_BRR 0x00000008U
5482 #define PWR_CSR_EWUP 0x00000100U
5483 #define PWR_CSR_BRE 0x00000200U
5484 #define PWR_CSR_VOSRDY 0x00004000U
5485 #define PWR_CSR_ODRDY 0x00010000U
5486 #define PWR_CSR_ODSWRDY 0x00020000U
5487 #define PWR_CSR_UDSWRDY 0x000C0000U
5489 /* Legacy define */
5490 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
5491 
5492 /******************************************************************************/
5493 /* */
5494 /* Reset and Clock Control */
5495 /* */
5496 /******************************************************************************/
5497 /******************** Bit definition for RCC_CR register ********************/
5498 #define RCC_CR_HSION 0x00000001U
5499 #define RCC_CR_HSIRDY 0x00000002U
5500 
5501 #define RCC_CR_HSITRIM 0x000000F8U
5502 #define RCC_CR_HSITRIM_0 0x00000008U
5503 #define RCC_CR_HSITRIM_1 0x00000010U
5504 #define RCC_CR_HSITRIM_2 0x00000020U
5505 #define RCC_CR_HSITRIM_3 0x00000040U
5506 #define RCC_CR_HSITRIM_4 0x00000080U
5508 #define RCC_CR_HSICAL 0x0000FF00U
5509 #define RCC_CR_HSICAL_0 0x00000100U
5510 #define RCC_CR_HSICAL_1 0x00000200U
5511 #define RCC_CR_HSICAL_2 0x00000400U
5512 #define RCC_CR_HSICAL_3 0x00000800U
5513 #define RCC_CR_HSICAL_4 0x00001000U
5514 #define RCC_CR_HSICAL_5 0x00002000U
5515 #define RCC_CR_HSICAL_6 0x00004000U
5516 #define RCC_CR_HSICAL_7 0x00008000U
5518 #define RCC_CR_HSEON 0x00010000U
5519 #define RCC_CR_HSERDY 0x00020000U
5520 #define RCC_CR_HSEBYP 0x00040000U
5521 #define RCC_CR_CSSON 0x00080000U
5522 #define RCC_CR_PLLON 0x01000000U
5523 #define RCC_CR_PLLRDY 0x02000000U
5524 #define RCC_CR_PLLI2SON 0x04000000U
5525 #define RCC_CR_PLLI2SRDY 0x08000000U
5526 #define RCC_CR_PLLSAION 0x10000000U
5527 #define RCC_CR_PLLSAIRDY 0x20000000U
5528 
5529 /******************** Bit definition for RCC_PLLCFGR register ***************/
5530 #define RCC_PLLCFGR_PLLM 0x0000003FU
5531 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5532 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5533 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5534 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5535 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5536 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5537 
5538 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5539 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5540 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5541 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5542 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5543 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5544 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5545 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5546 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5547 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5548 
5549 #define RCC_PLLCFGR_PLLP 0x00030000U
5550 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5551 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5552 
5553 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5554 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5555 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5556 
5557 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5558 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5559 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5560 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5561 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5562 
5563 /******************** Bit definition for RCC_CFGR register ******************/
5565 #define RCC_CFGR_SW 0x00000003U
5566 #define RCC_CFGR_SW_0 0x00000001U
5567 #define RCC_CFGR_SW_1 0x00000002U
5569 #define RCC_CFGR_SW_HSI 0x00000000U
5570 #define RCC_CFGR_SW_HSE 0x00000001U
5571 #define RCC_CFGR_SW_PLL 0x00000002U
5574 #define RCC_CFGR_SWS 0x0000000CU
5575 #define RCC_CFGR_SWS_0 0x00000004U
5576 #define RCC_CFGR_SWS_1 0x00000008U
5578 #define RCC_CFGR_SWS_HSI 0x00000000U
5579 #define RCC_CFGR_SWS_HSE 0x00000004U
5580 #define RCC_CFGR_SWS_PLL 0x00000008U
5583 #define RCC_CFGR_HPRE 0x000000F0U
5584 #define RCC_CFGR_HPRE_0 0x00000010U
5585 #define RCC_CFGR_HPRE_1 0x00000020U
5586 #define RCC_CFGR_HPRE_2 0x00000040U
5587 #define RCC_CFGR_HPRE_3 0x00000080U
5589 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5590 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5591 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5592 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5593 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5594 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5595 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5596 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5597 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5600 #define RCC_CFGR_PPRE1 0x00001C00U
5601 #define RCC_CFGR_PPRE1_0 0x00000400U
5602 #define RCC_CFGR_PPRE1_1 0x00000800U
5603 #define RCC_CFGR_PPRE1_2 0x00001000U
5605 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5606 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5607 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5608 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5609 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5612 #define RCC_CFGR_PPRE2 0x0000E000U
5613 #define RCC_CFGR_PPRE2_0 0x00002000U
5614 #define RCC_CFGR_PPRE2_1 0x00004000U
5615 #define RCC_CFGR_PPRE2_2 0x00008000U
5617 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5618 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5619 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5620 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5621 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5624 #define RCC_CFGR_RTCPRE 0x001F0000U
5625 #define RCC_CFGR_RTCPRE_0 0x00010000U
5626 #define RCC_CFGR_RTCPRE_1 0x00020000U
5627 #define RCC_CFGR_RTCPRE_2 0x00040000U
5628 #define RCC_CFGR_RTCPRE_3 0x00080000U
5629 #define RCC_CFGR_RTCPRE_4 0x00100000U
5630 
5632 #define RCC_CFGR_MCO1 0x00600000U
5633 #define RCC_CFGR_MCO1_0 0x00200000U
5634 #define RCC_CFGR_MCO1_1 0x00400000U
5635 
5636 #define RCC_CFGR_I2SSRC 0x00800000U
5637 
5638 #define RCC_CFGR_MCO1PRE 0x07000000U
5639 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5640 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5641 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5642 
5643 #define RCC_CFGR_MCO2PRE 0x38000000U
5644 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5645 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5646 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5647 
5648 #define RCC_CFGR_MCO2 0xC0000000U
5649 #define RCC_CFGR_MCO2_0 0x40000000U
5650 #define RCC_CFGR_MCO2_1 0x80000000U
5651 
5652 /******************** Bit definition for RCC_CIR register *******************/
5653 #define RCC_CIR_LSIRDYF 0x00000001U
5654 #define RCC_CIR_LSERDYF 0x00000002U
5655 #define RCC_CIR_HSIRDYF 0x00000004U
5656 #define RCC_CIR_HSERDYF 0x00000008U
5657 #define RCC_CIR_PLLRDYF 0x00000010U
5658 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5659 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5660 #define RCC_CIR_CSSF 0x00000080U
5661 #define RCC_CIR_LSIRDYIE 0x00000100U
5662 #define RCC_CIR_LSERDYIE 0x00000200U
5663 #define RCC_CIR_HSIRDYIE 0x00000400U
5664 #define RCC_CIR_HSERDYIE 0x00000800U
5665 #define RCC_CIR_PLLRDYIE 0x00001000U
5666 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5667 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5668 #define RCC_CIR_LSIRDYC 0x00010000U
5669 #define RCC_CIR_LSERDYC 0x00020000U
5670 #define RCC_CIR_HSIRDYC 0x00040000U
5671 #define RCC_CIR_HSERDYC 0x00080000U
5672 #define RCC_CIR_PLLRDYC 0x00100000U
5673 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5674 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5675 #define RCC_CIR_CSSC 0x00800000U
5676 
5677 /******************** Bit definition for RCC_AHB1RSTR register **************/
5678 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5679 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5680 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5681 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5682 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5683 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5684 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5685 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5686 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
5687 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
5688 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
5689 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5690 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5691 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5692 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
5693 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
5694 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5695 
5696 /******************** Bit definition for RCC_AHB2RSTR register **************/
5697 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5698 #define RCC_AHB2RSTR_CRYPRST 0x00000010U
5699 #define RCC_AHB2RSTR_HASHRST 0x00000020U
5700  /* maintained for legacy purpose */
5701  #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
5702 #define RCC_AHB2RSTR_RNGRST 0x00000040U
5703 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5704 
5705 /******************** Bit definition for RCC_AHB3RSTR register **************/
5706 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5707 
5708 /******************** Bit definition for RCC_APB1RSTR register **************/
5709 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5710 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5711 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5712 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5713 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5714 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5715 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5716 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5717 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5718 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5719 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5720 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5721 #define RCC_APB1RSTR_USART2RST 0x00020000U
5722 #define RCC_APB1RSTR_USART3RST 0x00040000U
5723 #define RCC_APB1RSTR_UART4RST 0x00080000U
5724 #define RCC_APB1RSTR_UART5RST 0x00100000U
5725 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5726 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5727 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5728 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5729 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5730 #define RCC_APB1RSTR_PWRRST 0x10000000U
5731 #define RCC_APB1RSTR_DACRST 0x20000000U
5732 #define RCC_APB1RSTR_UART7RST 0x40000000U
5733 #define RCC_APB1RSTR_UART8RST 0x80000000U
5734 
5735 /******************** Bit definition for RCC_APB2RSTR register **************/
5736 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5737 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5738 #define RCC_APB2RSTR_USART1RST 0x00000010U
5739 #define RCC_APB2RSTR_USART6RST 0x00000020U
5740 #define RCC_APB2RSTR_ADCRST 0x00000100U
5741 #define RCC_APB2RSTR_SDIORST 0x00000800U
5742 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5743 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5744 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5745 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5746 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5747 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5748 #define RCC_APB2RSTR_SPI5RST 0x00100000U
5749 #define RCC_APB2RSTR_SPI6RST 0x00200000U
5750 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5751 
5752 /* Old SPI1RST bit definition, maintained for legacy purpose */
5753 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5754 
5755 /******************** Bit definition for RCC_AHB1ENR register ***************/
5756 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5757 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5758 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5759 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5760 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5761 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5762 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5763 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5764 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
5765 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
5766 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
5767 
5768 #define RCC_AHB1ENR_CRCEN 0x00001000U
5769 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5770 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
5771 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5772 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5773 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
5774 
5775 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
5776 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
5777 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
5778 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
5779 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5780 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5781 
5782 /******************** Bit definition for RCC_AHB2ENR register ***************/
5783 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5784 #define RCC_AHB2ENR_CRYPEN 0x00000010U
5785 #define RCC_AHB2ENR_HASHEN 0x00000020U
5786 #define RCC_AHB2ENR_RNGEN 0x00000040U
5787 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5788 
5789 /******************** Bit definition for RCC_AHB3ENR register ***************/
5790 #define RCC_AHB3ENR_FMCEN 0x00000001U
5791 
5792 /******************** Bit definition for RCC_APB1ENR register ***************/
5793 #define RCC_APB1ENR_TIM2EN 0x00000001U
5794 #define RCC_APB1ENR_TIM3EN 0x00000002U
5795 #define RCC_APB1ENR_TIM4EN 0x00000004U
5796 #define RCC_APB1ENR_TIM5EN 0x00000008U
5797 #define RCC_APB1ENR_TIM6EN 0x00000010U
5798 #define RCC_APB1ENR_TIM7EN 0x00000020U
5799 #define RCC_APB1ENR_TIM12EN 0x00000040U
5800 #define RCC_APB1ENR_TIM13EN 0x00000080U
5801 #define RCC_APB1ENR_TIM14EN 0x00000100U
5802 #define RCC_APB1ENR_WWDGEN 0x00000800U
5803 #define RCC_APB1ENR_SPI2EN 0x00004000U
5804 #define RCC_APB1ENR_SPI3EN 0x00008000U
5805 #define RCC_APB1ENR_USART2EN 0x00020000U
5806 #define RCC_APB1ENR_USART3EN 0x00040000U
5807 #define RCC_APB1ENR_UART4EN 0x00080000U
5808 #define RCC_APB1ENR_UART5EN 0x00100000U
5809 #define RCC_APB1ENR_I2C1EN 0x00200000U
5810 #define RCC_APB1ENR_I2C2EN 0x00400000U
5811 #define RCC_APB1ENR_I2C3EN 0x00800000U
5812 #define RCC_APB1ENR_CAN1EN 0x02000000U
5813 #define RCC_APB1ENR_CAN2EN 0x04000000U
5814 #define RCC_APB1ENR_PWREN 0x10000000U
5815 #define RCC_APB1ENR_DACEN 0x20000000U
5816 #define RCC_APB1ENR_UART7EN 0x40000000U
5817 #define RCC_APB1ENR_UART8EN 0x80000000U
5818 
5819 /******************** Bit definition for RCC_APB2ENR register ***************/
5820 #define RCC_APB2ENR_TIM1EN 0x00000001U
5821 #define RCC_APB2ENR_TIM8EN 0x00000002U
5822 #define RCC_APB2ENR_USART1EN 0x00000010U
5823 #define RCC_APB2ENR_USART6EN 0x00000020U
5824 #define RCC_APB2ENR_ADC1EN 0x00000100U
5825 #define RCC_APB2ENR_ADC2EN 0x00000200U
5826 #define RCC_APB2ENR_ADC3EN 0x00000400U
5827 #define RCC_APB2ENR_SDIOEN 0x00000800U
5828 #define RCC_APB2ENR_SPI1EN 0x00001000U
5829 #define RCC_APB2ENR_SPI4EN 0x00002000U
5830 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5831 #define RCC_APB2ENR_TIM9EN 0x00010000U
5832 #define RCC_APB2ENR_TIM10EN 0x00020000U
5833 #define RCC_APB2ENR_TIM11EN 0x00040000U
5834 #define RCC_APB2ENR_SPI5EN 0x00100000U
5835 #define RCC_APB2ENR_SPI6EN 0x00200000U
5836 #define RCC_APB2ENR_SAI1EN 0x00400000U
5837 
5838 /******************** Bit definition for RCC_AHB1LPENR register *************/
5839 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5840 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5841 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5842 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5843 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5844 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5845 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5846 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5847 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5848 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
5849 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
5850 
5851 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5852 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5853 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5854 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5855 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5856 #define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
5857 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5858 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5859 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
5860 
5861 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
5862 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
5863 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
5864 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
5865 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5866 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5867 
5868 /******************** Bit definition for RCC_AHB2LPENR register *************/
5869 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5870 #define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
5871 #define RCC_AHB2LPENR_HASHLPEN 0x00000020U
5872 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
5873 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5874 
5875 /******************** Bit definition for RCC_AHB3LPENR register *************/
5876 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
5877 
5878 /******************** Bit definition for RCC_APB1LPENR register *************/
5879 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5880 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5881 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5882 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5883 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5884 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5885 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5886 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5887 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5888 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5889 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5890 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5891 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5892 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5893 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5894 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5895 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5896 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5897 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5898 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5899 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5900 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5901 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5902 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
5903 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
5904 
5905 /******************** Bit definition for RCC_APB2LPENR register *************/
5906 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5907 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5908 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5909 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5910 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5911 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5912 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5913 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
5914 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5915 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
5916 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5917 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5918 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5919 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5920 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
5921 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
5922 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
5923 
5924 /******************** Bit definition for RCC_BDCR register ******************/
5925 #define RCC_BDCR_LSEON 0x00000001U
5926 #define RCC_BDCR_LSERDY 0x00000002U
5927 #define RCC_BDCR_LSEBYP 0x00000004U
5928 
5929 #define RCC_BDCR_RTCSEL 0x00000300U
5930 #define RCC_BDCR_RTCSEL_0 0x00000100U
5931 #define RCC_BDCR_RTCSEL_1 0x00000200U
5932 
5933 #define RCC_BDCR_RTCEN 0x00008000U
5934 #define RCC_BDCR_BDRST 0x00010000U
5935 
5936 /******************** Bit definition for RCC_CSR register *******************/
5937 #define RCC_CSR_LSION 0x00000001U
5938 #define RCC_CSR_LSIRDY 0x00000002U
5939 #define RCC_CSR_RMVF 0x01000000U
5940 #define RCC_CSR_BORRSTF 0x02000000U
5941 #define RCC_CSR_PADRSTF 0x04000000U
5942 #define RCC_CSR_PORRSTF 0x08000000U
5943 #define RCC_CSR_SFTRSTF 0x10000000U
5944 #define RCC_CSR_WDGRSTF 0x20000000U
5945 #define RCC_CSR_WWDGRSTF 0x40000000U
5946 #define RCC_CSR_LPWRRSTF 0x80000000U
5947 
5948 /******************** Bit definition for RCC_SSCGR register *****************/
5949 #define RCC_SSCGR_MODPER 0x00001FFFU
5950 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5951 #define RCC_SSCGR_SPREADSEL 0x40000000U
5952 #define RCC_SSCGR_SSCGEN 0x80000000U
5953 
5954 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5955 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5956 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5957 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5958 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5959 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5960 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5961 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5962 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5963 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5964 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5965 
5966 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
5967 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
5968 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
5969 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
5970 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
5971 
5972 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5973 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5974 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5975 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5976 
5977 
5978 /******************** Bit definition for RCC_PLLSAICFGR register ************/
5979 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
5980 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
5981 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
5982 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
5983 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
5984 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
5985 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
5986 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
5987 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
5988 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
5989 
5990 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
5991 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
5992 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
5993 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
5994 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
5995 
5996 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
5997 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
5998 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
5999 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
6000 
6001 /******************** Bit definition for RCC_DCKCFGR register ***************/
6002 #define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
6003 #define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
6004 #define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
6005 #define RCC_DCKCFGR_SAI1ASRC 0x00300000U
6006 #define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
6007 #define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
6008 #define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
6009 #define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
6010 #define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
6011 #define RCC_DCKCFGR_TIMPRE 0x01000000U
6012 
6013 
6014 /******************************************************************************/
6015 /* */
6016 /* RNG */
6017 /* */
6018 /******************************************************************************/
6019 /******************** Bits definition for RNG_CR register *******************/
6020 #define RNG_CR_RNGEN 0x00000004U
6021 #define RNG_CR_IE 0x00000008U
6022 
6023 /******************** Bits definition for RNG_SR register *******************/
6024 #define RNG_SR_DRDY 0x00000001U
6025 #define RNG_SR_CECS 0x00000002U
6026 #define RNG_SR_SECS 0x00000004U
6027 #define RNG_SR_CEIS 0x00000020U
6028 #define RNG_SR_SEIS 0x00000040U
6029 
6030 /******************************************************************************/
6031 /* */
6032 /* Real-Time Clock (RTC) */
6033 /* */
6034 /******************************************************************************/
6035 /******************** Bits definition for RTC_TR register *******************/
6036 #define RTC_TR_PM 0x00400000U
6037 #define RTC_TR_HT 0x00300000U
6038 #define RTC_TR_HT_0 0x00100000U
6039 #define RTC_TR_HT_1 0x00200000U
6040 #define RTC_TR_HU 0x000F0000U
6041 #define RTC_TR_HU_0 0x00010000U
6042 #define RTC_TR_HU_1 0x00020000U
6043 #define RTC_TR_HU_2 0x00040000U
6044 #define RTC_TR_HU_3 0x00080000U
6045 #define RTC_TR_MNT 0x00007000U
6046 #define RTC_TR_MNT_0 0x00001000U
6047 #define RTC_TR_MNT_1 0x00002000U
6048 #define RTC_TR_MNT_2 0x00004000U
6049 #define RTC_TR_MNU 0x00000F00U
6050 #define RTC_TR_MNU_0 0x00000100U
6051 #define RTC_TR_MNU_1 0x00000200U
6052 #define RTC_TR_MNU_2 0x00000400U
6053 #define RTC_TR_MNU_3 0x00000800U
6054 #define RTC_TR_ST 0x00000070U
6055 #define RTC_TR_ST_0 0x00000010U
6056 #define RTC_TR_ST_1 0x00000020U
6057 #define RTC_TR_ST_2 0x00000040U
6058 #define RTC_TR_SU 0x0000000FU
6059 #define RTC_TR_SU_0 0x00000001U
6060 #define RTC_TR_SU_1 0x00000002U
6061 #define RTC_TR_SU_2 0x00000004U
6062 #define RTC_TR_SU_3 0x00000008U
6063 
6064 /******************** Bits definition for RTC_DR register *******************/
6065 #define RTC_DR_YT 0x00F00000U
6066 #define RTC_DR_YT_0 0x00100000U
6067 #define RTC_DR_YT_1 0x00200000U
6068 #define RTC_DR_YT_2 0x00400000U
6069 #define RTC_DR_YT_3 0x00800000U
6070 #define RTC_DR_YU 0x000F0000U
6071 #define RTC_DR_YU_0 0x00010000U
6072 #define RTC_DR_YU_1 0x00020000U
6073 #define RTC_DR_YU_2 0x00040000U
6074 #define RTC_DR_YU_3 0x00080000U
6075 #define RTC_DR_WDU 0x0000E000U
6076 #define RTC_DR_WDU_0 0x00002000U
6077 #define RTC_DR_WDU_1 0x00004000U
6078 #define RTC_DR_WDU_2 0x00008000U
6079 #define RTC_DR_MT 0x00001000U
6080 #define RTC_DR_MU 0x00000F00U
6081 #define RTC_DR_MU_0 0x00000100U
6082 #define RTC_DR_MU_1 0x00000200U
6083 #define RTC_DR_MU_2 0x00000400U
6084 #define RTC_DR_MU_3 0x00000800U
6085 #define RTC_DR_DT 0x00000030U
6086 #define RTC_DR_DT_0 0x00000010U
6087 #define RTC_DR_DT_1 0x00000020U
6088 #define RTC_DR_DU 0x0000000FU
6089 #define RTC_DR_DU_0 0x00000001U
6090 #define RTC_DR_DU_1 0x00000002U
6091 #define RTC_DR_DU_2 0x00000004U
6092 #define RTC_DR_DU_3 0x00000008U
6093 
6094 /******************** Bits definition for RTC_CR register *******************/
6095 #define RTC_CR_COE 0x00800000U
6096 #define RTC_CR_OSEL 0x00600000U
6097 #define RTC_CR_OSEL_0 0x00200000U
6098 #define RTC_CR_OSEL_1 0x00400000U
6099 #define RTC_CR_POL 0x00100000U
6100 #define RTC_CR_COSEL 0x00080000U
6101 #define RTC_CR_BCK 0x00040000U
6102 #define RTC_CR_SUB1H 0x00020000U
6103 #define RTC_CR_ADD1H 0x00010000U
6104 #define RTC_CR_TSIE 0x00008000U
6105 #define RTC_CR_WUTIE 0x00004000U
6106 #define RTC_CR_ALRBIE 0x00002000U
6107 #define RTC_CR_ALRAIE 0x00001000U
6108 #define RTC_CR_TSE 0x00000800U
6109 #define RTC_CR_WUTE 0x00000400U
6110 #define RTC_CR_ALRBE 0x00000200U
6111 #define RTC_CR_ALRAE 0x00000100U
6112 #define RTC_CR_DCE 0x00000080U
6113 #define RTC_CR_FMT 0x00000040U
6114 #define RTC_CR_BYPSHAD 0x00000020U
6115 #define RTC_CR_REFCKON 0x00000010U
6116 #define RTC_CR_TSEDGE 0x00000008U
6117 #define RTC_CR_WUCKSEL 0x00000007U
6118 #define RTC_CR_WUCKSEL_0 0x00000001U
6119 #define RTC_CR_WUCKSEL_1 0x00000002U
6120 #define RTC_CR_WUCKSEL_2 0x00000004U
6121 
6122 /******************** Bits definition for RTC_ISR register ******************/
6123 #define RTC_ISR_RECALPF 0x00010000U
6124 #define RTC_ISR_TAMP1F 0x00002000U
6125 #define RTC_ISR_TAMP2F 0x00004000U
6126 #define RTC_ISR_TSOVF 0x00001000U
6127 #define RTC_ISR_TSF 0x00000800U
6128 #define RTC_ISR_WUTF 0x00000400U
6129 #define RTC_ISR_ALRBF 0x00000200U
6130 #define RTC_ISR_ALRAF 0x00000100U
6131 #define RTC_ISR_INIT 0x00000080U
6132 #define RTC_ISR_INITF 0x00000040U
6133 #define RTC_ISR_RSF 0x00000020U
6134 #define RTC_ISR_INITS 0x00000010U
6135 #define RTC_ISR_SHPF 0x00000008U
6136 #define RTC_ISR_WUTWF 0x00000004U
6137 #define RTC_ISR_ALRBWF 0x00000002U
6138 #define RTC_ISR_ALRAWF 0x00000001U
6139 
6140 /******************** Bits definition for RTC_PRER register *****************/
6141 #define RTC_PRER_PREDIV_A 0x007F0000U
6142 #define RTC_PRER_PREDIV_S 0x00007FFFU
6143 
6144 /******************** Bits definition for RTC_WUTR register *****************/
6145 #define RTC_WUTR_WUT 0x0000FFFFU
6146 
6147 /******************** Bits definition for RTC_CALIBR register ***************/
6148 #define RTC_CALIBR_DCS 0x00000080U
6149 #define RTC_CALIBR_DC 0x0000001FU
6150 
6151 /******************** Bits definition for RTC_ALRMAR register ***************/
6152 #define RTC_ALRMAR_MSK4 0x80000000U
6153 #define RTC_ALRMAR_WDSEL 0x40000000U
6154 #define RTC_ALRMAR_DT 0x30000000U
6155 #define RTC_ALRMAR_DT_0 0x10000000U
6156 #define RTC_ALRMAR_DT_1 0x20000000U
6157 #define RTC_ALRMAR_DU 0x0F000000U
6158 #define RTC_ALRMAR_DU_0 0x01000000U
6159 #define RTC_ALRMAR_DU_1 0x02000000U
6160 #define RTC_ALRMAR_DU_2 0x04000000U
6161 #define RTC_ALRMAR_DU_3 0x08000000U
6162 #define RTC_ALRMAR_MSK3 0x00800000U
6163 #define RTC_ALRMAR_PM 0x00400000U
6164 #define RTC_ALRMAR_HT 0x00300000U
6165 #define RTC_ALRMAR_HT_0 0x00100000U
6166 #define RTC_ALRMAR_HT_1 0x00200000U
6167 #define RTC_ALRMAR_HU 0x000F0000U
6168 #define RTC_ALRMAR_HU_0 0x00010000U
6169 #define RTC_ALRMAR_HU_1 0x00020000U
6170 #define RTC_ALRMAR_HU_2 0x00040000U
6171 #define RTC_ALRMAR_HU_3 0x00080000U
6172 #define RTC_ALRMAR_MSK2 0x00008000U
6173 #define RTC_ALRMAR_MNT 0x00007000U
6174 #define RTC_ALRMAR_MNT_0 0x00001000U
6175 #define RTC_ALRMAR_MNT_1 0x00002000U
6176 #define RTC_ALRMAR_MNT_2 0x00004000U
6177 #define RTC_ALRMAR_MNU 0x00000F00U
6178 #define RTC_ALRMAR_MNU_0 0x00000100U
6179 #define RTC_ALRMAR_MNU_1 0x00000200U
6180 #define RTC_ALRMAR_MNU_2 0x00000400U
6181 #define RTC_ALRMAR_MNU_3 0x00000800U
6182 #define RTC_ALRMAR_MSK1 0x00000080U
6183 #define RTC_ALRMAR_ST 0x00000070U
6184 #define RTC_ALRMAR_ST_0 0x00000010U
6185 #define RTC_ALRMAR_ST_1 0x00000020U
6186 #define RTC_ALRMAR_ST_2 0x00000040U
6187 #define RTC_ALRMAR_SU 0x0000000FU
6188 #define RTC_ALRMAR_SU_0 0x00000001U
6189 #define RTC_ALRMAR_SU_1 0x00000002U
6190 #define RTC_ALRMAR_SU_2 0x00000004U
6191 #define RTC_ALRMAR_SU_3 0x00000008U
6192 
6193 /******************** Bits definition for RTC_ALRMBR register ***************/
6194 #define RTC_ALRMBR_MSK4 0x80000000U
6195 #define RTC_ALRMBR_WDSEL 0x40000000U
6196 #define RTC_ALRMBR_DT 0x30000000U
6197 #define RTC_ALRMBR_DT_0 0x10000000U
6198 #define RTC_ALRMBR_DT_1 0x20000000U
6199 #define RTC_ALRMBR_DU 0x0F000000U
6200 #define RTC_ALRMBR_DU_0 0x01000000U
6201 #define RTC_ALRMBR_DU_1 0x02000000U
6202 #define RTC_ALRMBR_DU_2 0x04000000U
6203 #define RTC_ALRMBR_DU_3 0x08000000U
6204 #define RTC_ALRMBR_MSK3 0x00800000U
6205 #define RTC_ALRMBR_PM 0x00400000U
6206 #define RTC_ALRMBR_HT 0x00300000U
6207 #define RTC_ALRMBR_HT_0 0x00100000U
6208 #define RTC_ALRMBR_HT_1 0x00200000U
6209 #define RTC_ALRMBR_HU 0x000F0000U
6210 #define RTC_ALRMBR_HU_0 0x00010000U
6211 #define RTC_ALRMBR_HU_1 0x00020000U
6212 #define RTC_ALRMBR_HU_2 0x00040000U
6213 #define RTC_ALRMBR_HU_3 0x00080000U
6214 #define RTC_ALRMBR_MSK2 0x00008000U
6215 #define RTC_ALRMBR_MNT 0x00007000U
6216 #define RTC_ALRMBR_MNT_0 0x00001000U
6217 #define RTC_ALRMBR_MNT_1 0x00002000U
6218 #define RTC_ALRMBR_MNT_2 0x00004000U
6219 #define RTC_ALRMBR_MNU 0x00000F00U
6220 #define RTC_ALRMBR_MNU_0 0x00000100U
6221 #define RTC_ALRMBR_MNU_1 0x00000200U
6222 #define RTC_ALRMBR_MNU_2 0x00000400U
6223 #define RTC_ALRMBR_MNU_3 0x00000800U
6224 #define RTC_ALRMBR_MSK1 0x00000080U
6225 #define RTC_ALRMBR_ST 0x00000070U
6226 #define RTC_ALRMBR_ST_0 0x00000010U
6227 #define RTC_ALRMBR_ST_1 0x00000020U
6228 #define RTC_ALRMBR_ST_2 0x00000040U
6229 #define RTC_ALRMBR_SU 0x0000000FU
6230 #define RTC_ALRMBR_SU_0 0x00000001U
6231 #define RTC_ALRMBR_SU_1 0x00000002U
6232 #define RTC_ALRMBR_SU_2 0x00000004U
6233 #define RTC_ALRMBR_SU_3 0x00000008U
6234 
6235 /******************** Bits definition for RTC_WPR register ******************/
6236 #define RTC_WPR_KEY 0x000000FFU
6237 
6238 /******************** Bits definition for RTC_SSR register ******************/
6239 #define RTC_SSR_SS 0x0000FFFFU
6240 
6241 /******************** Bits definition for RTC_SHIFTR register ***************/
6242 #define RTC_SHIFTR_SUBFS 0x00007FFFU
6243 #define RTC_SHIFTR_ADD1S 0x80000000U
6244 
6245 /******************** Bits definition for RTC_TSTR register *****************/
6246 #define RTC_TSTR_PM 0x00400000U
6247 #define RTC_TSTR_HT 0x00300000U
6248 #define RTC_TSTR_HT_0 0x00100000U
6249 #define RTC_TSTR_HT_1 0x00200000U
6250 #define RTC_TSTR_HU 0x000F0000U
6251 #define RTC_TSTR_HU_0 0x00010000U
6252 #define RTC_TSTR_HU_1 0x00020000U
6253 #define RTC_TSTR_HU_2 0x00040000U
6254 #define RTC_TSTR_HU_3 0x00080000U
6255 #define RTC_TSTR_MNT 0x00007000U
6256 #define RTC_TSTR_MNT_0 0x00001000U
6257 #define RTC_TSTR_MNT_1 0x00002000U
6258 #define RTC_TSTR_MNT_2 0x00004000U
6259 #define RTC_TSTR_MNU 0x00000F00U
6260 #define RTC_TSTR_MNU_0 0x00000100U
6261 #define RTC_TSTR_MNU_1 0x00000200U
6262 #define RTC_TSTR_MNU_2 0x00000400U
6263 #define RTC_TSTR_MNU_3 0x00000800U
6264 #define RTC_TSTR_ST 0x00000070U
6265 #define RTC_TSTR_ST_0 0x00000010U
6266 #define RTC_TSTR_ST_1 0x00000020U
6267 #define RTC_TSTR_ST_2 0x00000040U
6268 #define RTC_TSTR_SU 0x0000000FU
6269 #define RTC_TSTR_SU_0 0x00000001U
6270 #define RTC_TSTR_SU_1 0x00000002U
6271 #define RTC_TSTR_SU_2 0x00000004U
6272 #define RTC_TSTR_SU_3 0x00000008U
6273 
6274 /******************** Bits definition for RTC_TSDR register *****************/
6275 #define RTC_TSDR_WDU 0x0000E000U
6276 #define RTC_TSDR_WDU_0 0x00002000U
6277 #define RTC_TSDR_WDU_1 0x00004000U
6278 #define RTC_TSDR_WDU_2 0x00008000U
6279 #define RTC_TSDR_MT 0x00001000U
6280 #define RTC_TSDR_MU 0x00000F00U
6281 #define RTC_TSDR_MU_0 0x00000100U
6282 #define RTC_TSDR_MU_1 0x00000200U
6283 #define RTC_TSDR_MU_2 0x00000400U
6284 #define RTC_TSDR_MU_3 0x00000800U
6285 #define RTC_TSDR_DT 0x00000030U
6286 #define RTC_TSDR_DT_0 0x00000010U
6287 #define RTC_TSDR_DT_1 0x00000020U
6288 #define RTC_TSDR_DU 0x0000000FU
6289 #define RTC_TSDR_DU_0 0x00000001U
6290 #define RTC_TSDR_DU_1 0x00000002U
6291 #define RTC_TSDR_DU_2 0x00000004U
6292 #define RTC_TSDR_DU_3 0x00000008U
6293 
6294 /******************** Bits definition for RTC_TSSSR register ****************/
6295 #define RTC_TSSSR_SS 0x0000FFFFU
6296 
6297 /******************** Bits definition for RTC_CAL register *****************/
6298 #define RTC_CALR_CALP 0x00008000U
6299 #define RTC_CALR_CALW8 0x00004000U
6300 #define RTC_CALR_CALW16 0x00002000U
6301 #define RTC_CALR_CALM 0x000001FFU
6302 #define RTC_CALR_CALM_0 0x00000001U
6303 #define RTC_CALR_CALM_1 0x00000002U
6304 #define RTC_CALR_CALM_2 0x00000004U
6305 #define RTC_CALR_CALM_3 0x00000008U
6306 #define RTC_CALR_CALM_4 0x00000010U
6307 #define RTC_CALR_CALM_5 0x00000020U
6308 #define RTC_CALR_CALM_6 0x00000040U
6309 #define RTC_CALR_CALM_7 0x00000080U
6310 #define RTC_CALR_CALM_8 0x00000100U
6311 
6312 /******************** Bits definition for RTC_TAFCR register ****************/
6313 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
6314 #define RTC_TAFCR_TSINSEL 0x00020000U
6315 #define RTC_TAFCR_TAMPINSEL 0x00010000U
6316 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
6317 #define RTC_TAFCR_TAMPPRCH 0x00006000U
6318 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
6319 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
6320 #define RTC_TAFCR_TAMPFLT 0x00001800U
6321 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
6322 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
6323 #define RTC_TAFCR_TAMPFREQ 0x00000700U
6324 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
6325 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
6326 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
6327 #define RTC_TAFCR_TAMPTS 0x00000080U
6328 #define RTC_TAFCR_TAMP2TRG 0x00000010U
6329 #define RTC_TAFCR_TAMP2E 0x00000008U
6330 #define RTC_TAFCR_TAMPIE 0x00000004U
6331 #define RTC_TAFCR_TAMP1TRG 0x00000002U
6332 #define RTC_TAFCR_TAMP1E 0x00000001U
6333 
6334 /******************** Bits definition for RTC_ALRMASSR register *************/
6335 #define RTC_ALRMASSR_MASKSS 0x0F000000U
6336 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
6337 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
6338 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
6339 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
6340 #define RTC_ALRMASSR_SS 0x00007FFFU
6341 
6342 /******************** Bits definition for RTC_ALRMBSSR register *************/
6343 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
6344 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
6345 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
6346 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
6347 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
6348 #define RTC_ALRMBSSR_SS 0x00007FFFU
6349 
6350 /******************** Bits definition for RTC_BKP0R register ****************/
6351 #define RTC_BKP0R 0xFFFFFFFFU
6352 
6353 /******************** Bits definition for RTC_BKP1R register ****************/
6354 #define RTC_BKP1R 0xFFFFFFFFU
6355 
6356 /******************** Bits definition for RTC_BKP2R register ****************/
6357 #define RTC_BKP2R 0xFFFFFFFFU
6358 
6359 /******************** Bits definition for RTC_BKP3R register ****************/
6360 #define RTC_BKP3R 0xFFFFFFFFU
6361 
6362 /******************** Bits definition for RTC_BKP4R register ****************/
6363 #define RTC_BKP4R 0xFFFFFFFFU
6364 
6365 /******************** Bits definition for RTC_BKP5R register ****************/
6366 #define RTC_BKP5R 0xFFFFFFFFU
6367 
6368 /******************** Bits definition for RTC_BKP6R register ****************/
6369 #define RTC_BKP6R 0xFFFFFFFFU
6370 
6371 /******************** Bits definition for RTC_BKP7R register ****************/
6372 #define RTC_BKP7R 0xFFFFFFFFU
6373 
6374 /******************** Bits definition for RTC_BKP8R register ****************/
6375 #define RTC_BKP8R 0xFFFFFFFFU
6376 
6377 /******************** Bits definition for RTC_BKP9R register ****************/
6378 #define RTC_BKP9R 0xFFFFFFFFU
6379 
6380 /******************** Bits definition for RTC_BKP10R register ***************/
6381 #define RTC_BKP10R 0xFFFFFFFFU
6382 
6383 /******************** Bits definition for RTC_BKP11R register ***************/
6384 #define RTC_BKP11R 0xFFFFFFFFU
6385 
6386 /******************** Bits definition for RTC_BKP12R register ***************/
6387 #define RTC_BKP12R 0xFFFFFFFFU
6388 
6389 /******************** Bits definition for RTC_BKP13R register ***************/
6390 #define RTC_BKP13R 0xFFFFFFFFU
6391 
6392 /******************** Bits definition for RTC_BKP14R register ***************/
6393 #define RTC_BKP14R 0xFFFFFFFFU
6394 
6395 /******************** Bits definition for RTC_BKP15R register ***************/
6396 #define RTC_BKP15R 0xFFFFFFFFU
6397 
6398 /******************** Bits definition for RTC_BKP16R register ***************/
6399 #define RTC_BKP16R 0xFFFFFFFFU
6400 
6401 /******************** Bits definition for RTC_BKP17R register ***************/
6402 #define RTC_BKP17R 0xFFFFFFFFU
6403 
6404 /******************** Bits definition for RTC_BKP18R register ***************/
6405 #define RTC_BKP18R 0xFFFFFFFFU
6406 
6407 /******************** Bits definition for RTC_BKP19R register ***************/
6408 #define RTC_BKP19R 0xFFFFFFFFU
6409 
6410 /******************************************************************************/
6411 /* */
6412 /* Serial Audio Interface */
6413 /* */
6414 /******************************************************************************/
6415 /******************** Bit definition for SAI_GCR register *******************/
6416 #define SAI_GCR_SYNCIN 0x00000003U
6417 #define SAI_GCR_SYNCIN_0 0x00000001U
6418 #define SAI_GCR_SYNCIN_1 0x00000002U
6420 #define SAI_GCR_SYNCOUT 0x00000030U
6421 #define SAI_GCR_SYNCOUT_0 0x00000010U
6422 #define SAI_GCR_SYNCOUT_1 0x00000020U
6424 /******************* Bit definition for SAI_xCR1 register *******************/
6425 #define SAI_xCR1_MODE 0x00000003U
6426 #define SAI_xCR1_MODE_0 0x00000001U
6427 #define SAI_xCR1_MODE_1 0x00000002U
6429 #define SAI_xCR1_PRTCFG 0x0000000CU
6430 #define SAI_xCR1_PRTCFG_0 0x00000004U
6431 #define SAI_xCR1_PRTCFG_1 0x00000008U
6433 #define SAI_xCR1_DS 0x000000E0U
6434 #define SAI_xCR1_DS_0 0x00000020U
6435 #define SAI_xCR1_DS_1 0x00000040U
6436 #define SAI_xCR1_DS_2 0x00000080U
6438 #define SAI_xCR1_LSBFIRST 0x00000100U
6439 #define SAI_xCR1_CKSTR 0x00000200U
6441 #define SAI_xCR1_SYNCEN 0x00000C00U
6442 #define SAI_xCR1_SYNCEN_0 0x00000400U
6443 #define SAI_xCR1_SYNCEN_1 0x00000800U
6445 #define SAI_xCR1_MONO 0x00001000U
6446 #define SAI_xCR1_OUTDRIV 0x00002000U
6447 #define SAI_xCR1_SAIEN 0x00010000U
6448 #define SAI_xCR1_DMAEN 0x00020000U
6449 #define SAI_xCR1_NODIV 0x00080000U
6451 #define SAI_xCR1_MCKDIV 0x00F00000U
6452 #define SAI_xCR1_MCKDIV_0 0x00100000U
6453 #define SAI_xCR1_MCKDIV_1 0x00200000U
6454 #define SAI_xCR1_MCKDIV_2 0x00400000U
6455 #define SAI_xCR1_MCKDIV_3 0x00800000U
6457 /******************* Bit definition for SAI_xCR2 register *******************/
6458 #define SAI_xCR2_FTH 0x00000007U
6459 #define SAI_xCR2_FTH_0 0x00000001U
6460 #define SAI_xCR2_FTH_1 0x00000002U
6461 #define SAI_xCR2_FTH_2 0x00000004U
6463 #define SAI_xCR2_FFLUSH 0x00000008U
6464 #define SAI_xCR2_TRIS 0x00000010U
6465 #define SAI_xCR2_MUTE 0x00000020U
6466 #define SAI_xCR2_MUTEVAL 0x00000040U
6468 #define SAI_xCR2_MUTECNT 0x00001F80U
6469 #define SAI_xCR2_MUTECNT_0 0x00000080U
6470 #define SAI_xCR2_MUTECNT_1 0x00000100U
6471 #define SAI_xCR2_MUTECNT_2 0x00000200U
6472 #define SAI_xCR2_MUTECNT_3 0x00000400U
6473 #define SAI_xCR2_MUTECNT_4 0x00000800U
6474 #define SAI_xCR2_MUTECNT_5 0x00001000U
6476 #define SAI_xCR2_CPL 0x00002000U
6478 #define SAI_xCR2_COMP 0x0000C000U
6479 #define SAI_xCR2_COMP_0 0x00004000U
6480 #define SAI_xCR2_COMP_1 0x00008000U
6482 /****************** Bit definition for SAI_xFRCR register *******************/
6483 #define SAI_xFRCR_FRL 0x000000FFU
6484 #define SAI_xFRCR_FRL_0 0x00000001U
6485 #define SAI_xFRCR_FRL_1 0x00000002U
6486 #define SAI_xFRCR_FRL_2 0x00000004U
6487 #define SAI_xFRCR_FRL_3 0x00000008U
6488 #define SAI_xFRCR_FRL_4 0x00000010U
6489 #define SAI_xFRCR_FRL_5 0x00000020U
6490 #define SAI_xFRCR_FRL_6 0x00000040U
6491 #define SAI_xFRCR_FRL_7 0x00000080U
6493 #define SAI_xFRCR_FSALL 0x00007F00U
6494 #define SAI_xFRCR_FSALL_0 0x00000100U
6495 #define SAI_xFRCR_FSALL_1 0x00000200U
6496 #define SAI_xFRCR_FSALL_2 0x00000400U
6497 #define SAI_xFRCR_FSALL_3 0x00000800U
6498 #define SAI_xFRCR_FSALL_4 0x00001000U
6499 #define SAI_xFRCR_FSALL_5 0x00002000U
6500 #define SAI_xFRCR_FSALL_6 0x00004000U
6502 #define SAI_xFRCR_FSDEF 0x00010000U
6503 #define SAI_xFRCR_FSPOL 0x00020000U
6504 #define SAI_xFRCR_FSOFF 0x00040000U
6505 /* Legacy defines */
6506 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6507 
6508 /****************** Bit definition for SAI_xSLOTR register *******************/
6509 #define SAI_xSLOTR_FBOFF 0x0000001FU
6510 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6511 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6512 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6513 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6514 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6516 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6517 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6518 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6520 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6521 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6522 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6523 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6524 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6526 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6528 /******************* Bit definition for SAI_xIMR register *******************/
6529 #define SAI_xIMR_OVRUDRIE 0x00000001U
6530 #define SAI_xIMR_MUTEDETIE 0x00000002U
6531 #define SAI_xIMR_WCKCFGIE 0x00000004U
6532 #define SAI_xIMR_FREQIE 0x00000008U
6533 #define SAI_xIMR_CNRDYIE 0x00000010U
6534 #define SAI_xIMR_AFSDETIE 0x00000020U
6535 #define SAI_xIMR_LFSDETIE 0x00000040U
6537 /******************** Bit definition for SAI_xSR register *******************/
6538 #define SAI_xSR_OVRUDR 0x00000001U
6539 #define SAI_xSR_MUTEDET 0x00000002U
6540 #define SAI_xSR_WCKCFG 0x00000004U
6541 #define SAI_xSR_FREQ 0x00000008U
6542 #define SAI_xSR_CNRDY 0x00000010U
6543 #define SAI_xSR_AFSDET 0x00000020U
6544 #define SAI_xSR_LFSDET 0x00000040U
6546 #define SAI_xSR_FLVL 0x00070000U
6547 #define SAI_xSR_FLVL_0 0x00010000U
6548 #define SAI_xSR_FLVL_1 0x00020000U
6549 #define SAI_xSR_FLVL_2 0x00040000U
6551 /****************** Bit definition for SAI_xCLRFR register ******************/
6552 #define SAI_xCLRFR_COVRUDR 0x00000001U
6553 #define SAI_xCLRFR_CMUTEDET 0x00000002U
6554 #define SAI_xCLRFR_CWCKCFG 0x00000004U
6555 #define SAI_xCLRFR_CFREQ 0x00000008U
6556 #define SAI_xCLRFR_CCNRDY 0x00000010U
6557 #define SAI_xCLRFR_CAFSDET 0x00000020U
6558 #define SAI_xCLRFR_CLFSDET 0x00000040U
6560 /****************** Bit definition for SAI_xDR register ******************/
6561 #define SAI_xDR_DATA 0xFFFFFFFFU
6562 
6563 
6564 /******************************************************************************/
6565 /* */
6566 /* SD host Interface */
6567 /* */
6568 /******************************************************************************/
6569 /****************** Bit definition for SDIO_POWER register ******************/
6570 #define SDIO_POWER_PWRCTRL 0x03U
6571 #define SDIO_POWER_PWRCTRL_0 0x01U
6572 #define SDIO_POWER_PWRCTRL_1 0x02U
6574 /****************** Bit definition for SDIO_CLKCR register ******************/
6575 #define SDIO_CLKCR_CLKDIV 0x00FFU
6576 #define SDIO_CLKCR_CLKEN 0x0100U
6577 #define SDIO_CLKCR_PWRSAV 0x0200U
6578 #define SDIO_CLKCR_BYPASS 0x0400U
6580 #define SDIO_CLKCR_WIDBUS 0x1800U
6581 #define SDIO_CLKCR_WIDBUS_0 0x0800U
6582 #define SDIO_CLKCR_WIDBUS_1 0x1000U
6584 #define SDIO_CLKCR_NEGEDGE 0x2000U
6585 #define SDIO_CLKCR_HWFC_EN 0x4000U
6587 /******************* Bit definition for SDIO_ARG register *******************/
6588 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
6590 /******************* Bit definition for SDIO_CMD register *******************/
6591 #define SDIO_CMD_CMDINDEX 0x003FU
6593 #define SDIO_CMD_WAITRESP 0x00C0U
6594 #define SDIO_CMD_WAITRESP_0 0x0040U
6595 #define SDIO_CMD_WAITRESP_1 0x0080U
6597 #define SDIO_CMD_WAITINT 0x0100U
6598 #define SDIO_CMD_WAITPEND 0x0200U
6599 #define SDIO_CMD_CPSMEN 0x0400U
6600 #define SDIO_CMD_SDIOSUSPEND 0x0800U
6601 #define SDIO_CMD_ENCMDCOMPL 0x1000U
6602 #define SDIO_CMD_NIEN 0x2000U
6603 #define SDIO_CMD_CEATACMD 0x4000U
6605 /***************** Bit definition for SDIO_RESPCMD register *****************/
6606 #define SDIO_RESPCMD_RESPCMD 0x3FU
6608 /****************** Bit definition for SDIO_RESP0 register ******************/
6609 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
6611 /****************** Bit definition for SDIO_RESP1 register ******************/
6612 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
6614 /****************** Bit definition for SDIO_RESP2 register ******************/
6615 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
6617 /****************** Bit definition for SDIO_RESP3 register ******************/
6618 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
6620 /****************** Bit definition for SDIO_RESP4 register ******************/
6621 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
6623 /****************** Bit definition for SDIO_DTIMER register *****************/
6624 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
6626 /****************** Bit definition for SDIO_DLEN register *******************/
6627 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
6629 /****************** Bit definition for SDIO_DCTRL register ******************/
6630 #define SDIO_DCTRL_DTEN 0x0001U
6631 #define SDIO_DCTRL_DTDIR 0x0002U
6632 #define SDIO_DCTRL_DTMODE 0x0004U
6633 #define SDIO_DCTRL_DMAEN 0x0008U
6635 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
6636 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
6637 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
6638 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
6639 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
6641 #define SDIO_DCTRL_RWSTART 0x0100U
6642 #define SDIO_DCTRL_RWSTOP 0x0200U
6643 #define SDIO_DCTRL_RWMOD 0x0400U
6644 #define SDIO_DCTRL_SDIOEN 0x0800U
6646 /****************** Bit definition for SDIO_DCOUNT register *****************/
6647 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
6649 /****************** Bit definition for SDIO_STA register ********************/
6650 #define SDIO_STA_CCRCFAIL 0x00000001U
6651 #define SDIO_STA_DCRCFAIL 0x00000002U
6652 #define SDIO_STA_CTIMEOUT 0x00000004U
6653 #define SDIO_STA_DTIMEOUT 0x00000008U
6654 #define SDIO_STA_TXUNDERR 0x00000010U
6655 #define SDIO_STA_RXOVERR 0x00000020U
6656 #define SDIO_STA_CMDREND 0x00000040U
6657 #define SDIO_STA_CMDSENT 0x00000080U
6658 #define SDIO_STA_DATAEND 0x00000100U
6659 #define SDIO_STA_STBITERR 0x00000200U
6660 #define SDIO_STA_DBCKEND 0x00000400U
6661 #define SDIO_STA_CMDACT 0x00000800U
6662 #define SDIO_STA_TXACT 0x00001000U
6663 #define SDIO_STA_RXACT 0x00002000U
6664 #define SDIO_STA_TXFIFOHE 0x00004000U
6665 #define SDIO_STA_RXFIFOHF 0x00008000U
6666 #define SDIO_STA_TXFIFOF 0x00010000U
6667 #define SDIO_STA_RXFIFOF 0x00020000U
6668 #define SDIO_STA_TXFIFOE 0x00040000U
6669 #define SDIO_STA_RXFIFOE 0x00080000U
6670 #define SDIO_STA_TXDAVL 0x00100000U
6671 #define SDIO_STA_RXDAVL 0x00200000U
6672 #define SDIO_STA_SDIOIT 0x00400000U
6673 #define SDIO_STA_CEATAEND 0x00800000U
6675 /******************* Bit definition for SDIO_ICR register *******************/
6676 #define SDIO_ICR_CCRCFAILC 0x00000001U
6677 #define SDIO_ICR_DCRCFAILC 0x00000002U
6678 #define SDIO_ICR_CTIMEOUTC 0x00000004U
6679 #define SDIO_ICR_DTIMEOUTC 0x00000008U
6680 #define SDIO_ICR_TXUNDERRC 0x00000010U
6681 #define SDIO_ICR_RXOVERRC 0x00000020U
6682 #define SDIO_ICR_CMDRENDC 0x00000040U
6683 #define SDIO_ICR_CMDSENTC 0x00000080U
6684 #define SDIO_ICR_DATAENDC 0x00000100U
6685 #define SDIO_ICR_STBITERRC 0x00000200U
6686 #define SDIO_ICR_DBCKENDC 0x00000400U
6687 #define SDIO_ICR_SDIOITC 0x00400000U
6688 #define SDIO_ICR_CEATAENDC 0x00800000U
6690 /****************** Bit definition for SDIO_MASK register *******************/
6691 #define SDIO_MASK_CCRCFAILIE 0x00000001U
6692 #define SDIO_MASK_DCRCFAILIE 0x00000002U
6693 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
6694 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
6695 #define SDIO_MASK_TXUNDERRIE 0x00000010U
6696 #define SDIO_MASK_RXOVERRIE 0x00000020U
6697 #define SDIO_MASK_CMDRENDIE 0x00000040U
6698 #define SDIO_MASK_CMDSENTIE 0x00000080U
6699 #define SDIO_MASK_DATAENDIE 0x00000100U
6700 #define SDIO_MASK_STBITERRIE 0x00000200U
6701 #define SDIO_MASK_DBCKENDIE 0x00000400U
6702 #define SDIO_MASK_CMDACTIE 0x00000800U
6703 #define SDIO_MASK_TXACTIE 0x00001000U
6704 #define SDIO_MASK_RXACTIE 0x00002000U
6705 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
6706 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
6707 #define SDIO_MASK_TXFIFOFIE 0x00010000U
6708 #define SDIO_MASK_RXFIFOFIE 0x00020000U
6709 #define SDIO_MASK_TXFIFOEIE 0x00040000U
6710 #define SDIO_MASK_RXFIFOEIE 0x00080000U
6711 #define SDIO_MASK_TXDAVLIE 0x00100000U
6712 #define SDIO_MASK_RXDAVLIE 0x00200000U
6713 #define SDIO_MASK_SDIOITIE 0x00400000U
6714 #define SDIO_MASK_CEATAENDIE 0x00800000U
6716 /***************** Bit definition for SDIO_FIFOCNT register *****************/
6717 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6719 /****************** Bit definition for SDIO_FIFO register *******************/
6720 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
6722 /******************************************************************************/
6723 /* */
6724 /* Serial Peripheral Interface */
6725 /* */
6726 /******************************************************************************/
6727 /******************* Bit definition for SPI_CR1 register ********************/
6728 #define SPI_CR1_CPHA 0x00000001U
6729 #define SPI_CR1_CPOL 0x00000002U
6730 #define SPI_CR1_MSTR 0x00000004U
6732 #define SPI_CR1_BR 0x00000038U
6733 #define SPI_CR1_BR_0 0x00000008U
6734 #define SPI_CR1_BR_1 0x00000010U
6735 #define SPI_CR1_BR_2 0x00000020U
6737 #define SPI_CR1_SPE 0x00000040U
6738 #define SPI_CR1_LSBFIRST 0x00000080U
6739 #define SPI_CR1_SSI 0x00000100U
6740 #define SPI_CR1_SSM 0x00000200U
6741 #define SPI_CR1_RXONLY 0x00000400U
6742 #define SPI_CR1_DFF 0x00000800U
6743 #define SPI_CR1_CRCNEXT 0x00001000U
6744 #define SPI_CR1_CRCEN 0x00002000U
6745 #define SPI_CR1_BIDIOE 0x00004000U
6746 #define SPI_CR1_BIDIMODE 0x00008000U
6748 /******************* Bit definition for SPI_CR2 register ********************/
6749 #define SPI_CR2_RXDMAEN 0x00000001U
6750 #define SPI_CR2_TXDMAEN 0x00000002U
6751 #define SPI_CR2_SSOE 0x00000004U
6752 #define SPI_CR2_FRF 0x00000010U
6753 #define SPI_CR2_ERRIE 0x00000020U
6754 #define SPI_CR2_RXNEIE 0x00000040U
6755 #define SPI_CR2_TXEIE 0x00000080U
6757 /******************** Bit definition for SPI_SR register ********************/
6758 #define SPI_SR_RXNE 0x00000001U
6759 #define SPI_SR_TXE 0x00000002U
6760 #define SPI_SR_CHSIDE 0x00000004U
6761 #define SPI_SR_UDR 0x00000008U
6762 #define SPI_SR_CRCERR 0x00000010U
6763 #define SPI_SR_MODF 0x00000020U
6764 #define SPI_SR_OVR 0x00000040U
6765 #define SPI_SR_BSY 0x00000080U
6766 #define SPI_SR_FRE 0x00000100U
6768 /******************** Bit definition for SPI_DR register ********************/
6769 #define SPI_DR_DR 0x0000FFFFU
6771 /******************* Bit definition for SPI_CRCPR register ******************/
6772 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
6774 /****************** Bit definition for SPI_RXCRCR register ******************/
6775 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
6777 /****************** Bit definition for SPI_TXCRCR register ******************/
6778 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
6780 /****************** Bit definition for SPI_I2SCFGR register *****************/
6781 #define SPI_I2SCFGR_CHLEN 0x00000001U
6783 #define SPI_I2SCFGR_DATLEN 0x00000006U
6784 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
6785 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
6787 #define SPI_I2SCFGR_CKPOL 0x00000008U
6789 #define SPI_I2SCFGR_I2SSTD 0x00000030U
6790 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
6791 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
6793 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
6795 #define SPI_I2SCFGR_I2SCFG 0x00000300U
6796 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
6797 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
6799 #define SPI_I2SCFGR_I2SE 0x00000400U
6800 #define SPI_I2SCFGR_I2SMOD 0x00000800U
6802 /****************** Bit definition for SPI_I2SPR register *******************/
6803 #define SPI_I2SPR_I2SDIV 0x000000FFU
6804 #define SPI_I2SPR_ODD 0x00000100U
6805 #define SPI_I2SPR_MCKOE 0x00000200U
6807 /******************************************************************************/
6808 /* */
6809 /* SYSCFG */
6810 /* */
6811 /******************************************************************************/
6812 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6813 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
6814 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
6815 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
6816 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
6817 
6818 #define SYSCFG_MEMRMP_UFB_MODE 0x00000100U
6819 #define SYSCFG_SWP_FMC 0x00000C00U
6821 /****************** Bit definition for SYSCFG_PMC register ******************/
6822 #define SYSCFG_PMC_ADCxDC2 0x00070000U
6823 #define SYSCFG_PMC_ADC1DC2 0x00010000U
6824 #define SYSCFG_PMC_ADC2DC2 0x00020000U
6825 #define SYSCFG_PMC_ADC3DC2 0x00040000U
6827 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
6828 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
6829 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
6830 
6831 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6832 #define SYSCFG_EXTICR1_EXTI0 0x000FU
6833 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
6834 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
6835 #define SYSCFG_EXTICR1_EXTI3 0xF000U
6839 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
6840 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
6841 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
6842 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
6843 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
6844 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
6845 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
6846 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
6847 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
6848 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
6849 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
6854 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
6855 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
6856 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
6857 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
6858 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
6859 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
6860 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
6861 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
6862 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
6863 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
6864 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
6870 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
6871 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
6872 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
6873 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
6874 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
6875 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
6876 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
6877 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
6878 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
6879 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
6880 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
6886 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
6887 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
6888 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
6889 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
6890 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
6891 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
6892 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
6893 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
6894 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
6895 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
6896 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
6899 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6900 #define SYSCFG_EXTICR2_EXTI4 0x000FU
6901 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
6902 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
6903 #define SYSCFG_EXTICR2_EXTI7 0xF000U
6907 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
6908 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
6909 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
6910 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
6911 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
6912 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
6913 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
6914 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
6915 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
6916 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
6917 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
6922 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
6923 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
6924 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
6925 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
6926 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
6927 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
6928 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
6929 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
6930 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
6931 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
6932 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
6937 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
6938 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
6939 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
6940 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
6941 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
6942 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
6943 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
6944 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
6945 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
6946 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
6947 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
6953 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
6954 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
6955 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
6956 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
6957 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
6958 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
6959 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
6960 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
6961 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
6962 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
6963 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
6965 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6966 #define SYSCFG_EXTICR3_EXTI8 0x000FU
6967 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
6968 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
6969 #define SYSCFG_EXTICR3_EXTI11 0xF000U
6974 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
6975 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
6976 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
6977 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
6978 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
6979 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
6980 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
6981 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
6982 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
6983 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
6988 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
6989 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
6990 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
6991 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
6992 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
6993 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
6994 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
6995 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
6996 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
6997 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
7003 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
7004 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
7005 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
7006 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
7007 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
7008 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
7009 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
7010 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
7011 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
7012 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
7018 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
7019 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
7020 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
7021 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
7022 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
7023 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
7024 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
7025 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
7026 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
7027 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
7030 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7031 #define SYSCFG_EXTICR4_EXTI12 0x000FU
7032 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
7033 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
7034 #define SYSCFG_EXTICR4_EXTI15 0xF000U
7038 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
7039 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
7040 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
7041 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
7042 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
7043 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
7044 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
7045 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
7046 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
7047 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
7053 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
7054 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
7055 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
7056 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
7057 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
7058 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
7059 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
7060 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
7061 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
7062 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
7068 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
7069 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
7070 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
7071 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
7072 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
7073 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
7074 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
7075 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
7076 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
7077 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
7083 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
7084 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
7085 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
7086 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
7087 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
7088 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
7089 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
7090 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
7091 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
7092 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
7094 /****************** Bit definition for SYSCFG_CMPCR register ****************/
7095 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
7096 #define SYSCFG_CMPCR_READY 0x00000100U
7098 /******************************************************************************/
7099 /* */
7100 /* TIM */
7101 /* */
7102 /******************************************************************************/
7103 /******************* Bit definition for TIM_CR1 register ********************/
7104 #define TIM_CR1_CEN 0x0001U
7105 #define TIM_CR1_UDIS 0x0002U
7106 #define TIM_CR1_URS 0x0004U
7107 #define TIM_CR1_OPM 0x0008U
7108 #define TIM_CR1_DIR 0x0010U
7110 #define TIM_CR1_CMS 0x0060U
7111 #define TIM_CR1_CMS_0 0x0020U
7112 #define TIM_CR1_CMS_1 0x0040U
7114 #define TIM_CR1_ARPE 0x0080U
7116 #define TIM_CR1_CKD 0x0300U
7117 #define TIM_CR1_CKD_0 0x0100U
7118 #define TIM_CR1_CKD_1 0x0200U
7120 /******************* Bit definition for TIM_CR2 register ********************/
7121 #define TIM_CR2_CCPC 0x0001U
7122 #define TIM_CR2_CCUS 0x0004U
7123 #define TIM_CR2_CCDS 0x0008U
7125 #define TIM_CR2_MMS 0x0070U
7126 #define TIM_CR2_MMS_0 0x0010U
7127 #define TIM_CR2_MMS_1 0x0020U
7128 #define TIM_CR2_MMS_2 0x0040U
7130 #define TIM_CR2_TI1S 0x0080U
7131 #define TIM_CR2_OIS1 0x0100U
7132 #define TIM_CR2_OIS1N 0x0200U
7133 #define TIM_CR2_OIS2 0x0400U
7134 #define TIM_CR2_OIS2N 0x0800U
7135 #define TIM_CR2_OIS3 0x1000U
7136 #define TIM_CR2_OIS3N 0x2000U
7137 #define TIM_CR2_OIS4 0x4000U
7139 /******************* Bit definition for TIM_SMCR register *******************/
7140 #define TIM_SMCR_SMS 0x0007U
7141 #define TIM_SMCR_SMS_0 0x0001U
7142 #define TIM_SMCR_SMS_1 0x0002U
7143 #define TIM_SMCR_SMS_2 0x0004U
7145 #define TIM_SMCR_TS 0x0070U
7146 #define TIM_SMCR_TS_0 0x0010U
7147 #define TIM_SMCR_TS_1 0x0020U
7148 #define TIM_SMCR_TS_2 0x0040U
7150 #define TIM_SMCR_MSM 0x0080U
7152 #define TIM_SMCR_ETF 0x0F00U
7153 #define TIM_SMCR_ETF_0 0x0100U
7154 #define TIM_SMCR_ETF_1 0x0200U
7155 #define TIM_SMCR_ETF_2 0x0400U
7156 #define TIM_SMCR_ETF_3 0x0800U
7158 #define TIM_SMCR_ETPS 0x3000U
7159 #define TIM_SMCR_ETPS_0 0x1000U
7160 #define TIM_SMCR_ETPS_1 0x2000U
7162 #define TIM_SMCR_ECE 0x4000U
7163 #define TIM_SMCR_ETP 0x8000U
7165 /******************* Bit definition for TIM_DIER register *******************/
7166 #define TIM_DIER_UIE 0x0001U
7167 #define TIM_DIER_CC1IE 0x0002U
7168 #define TIM_DIER_CC2IE 0x0004U
7169 #define TIM_DIER_CC3IE 0x0008U
7170 #define TIM_DIER_CC4IE 0x0010U
7171 #define TIM_DIER_COMIE 0x0020U
7172 #define TIM_DIER_TIE 0x0040U
7173 #define TIM_DIER_BIE 0x0080U
7174 #define TIM_DIER_UDE 0x0100U
7175 #define TIM_DIER_CC1DE 0x0200U
7176 #define TIM_DIER_CC2DE 0x0400U
7177 #define TIM_DIER_CC3DE 0x0800U
7178 #define TIM_DIER_CC4DE 0x1000U
7179 #define TIM_DIER_COMDE 0x2000U
7180 #define TIM_DIER_TDE 0x4000U
7182 /******************** Bit definition for TIM_SR register ********************/
7183 #define TIM_SR_UIF 0x0001U
7184 #define TIM_SR_CC1IF 0x0002U
7185 #define TIM_SR_CC2IF 0x0004U
7186 #define TIM_SR_CC3IF 0x0008U
7187 #define TIM_SR_CC4IF 0x0010U
7188 #define TIM_SR_COMIF 0x0020U
7189 #define TIM_SR_TIF 0x0040U
7190 #define TIM_SR_BIF 0x0080U
7191 #define TIM_SR_CC1OF 0x0200U
7192 #define TIM_SR_CC2OF 0x0400U
7193 #define TIM_SR_CC3OF 0x0800U
7194 #define TIM_SR_CC4OF 0x1000U
7196 /******************* Bit definition for TIM_EGR register ********************/
7197 #define TIM_EGR_UG 0x01U
7198 #define TIM_EGR_CC1G 0x02U
7199 #define TIM_EGR_CC2G 0x04U
7200 #define TIM_EGR_CC3G 0x08U
7201 #define TIM_EGR_CC4G 0x10U
7202 #define TIM_EGR_COMG 0x20U
7203 #define TIM_EGR_TG 0x40U
7204 #define TIM_EGR_BG 0x80U
7206 /****************** Bit definition for TIM_CCMR1 register *******************/
7207 #define TIM_CCMR1_CC1S 0x0003U
7208 #define TIM_CCMR1_CC1S_0 0x0001U
7209 #define TIM_CCMR1_CC1S_1 0x0002U
7211 #define TIM_CCMR1_OC1FE 0x0004U
7212 #define TIM_CCMR1_OC1PE 0x0008U
7214 #define TIM_CCMR1_OC1M 0x0070U
7215 #define TIM_CCMR1_OC1M_0 0x0010U
7216 #define TIM_CCMR1_OC1M_1 0x0020U
7217 #define TIM_CCMR1_OC1M_2 0x0040U
7219 #define TIM_CCMR1_OC1CE 0x0080U
7221 #define TIM_CCMR1_CC2S 0x0300U
7222 #define TIM_CCMR1_CC2S_0 0x0100U
7223 #define TIM_CCMR1_CC2S_1 0x0200U
7225 #define TIM_CCMR1_OC2FE 0x0400U
7226 #define TIM_CCMR1_OC2PE 0x0800U
7228 #define TIM_CCMR1_OC2M 0x7000U
7229 #define TIM_CCMR1_OC2M_0 0x1000U
7230 #define TIM_CCMR1_OC2M_1 0x2000U
7231 #define TIM_CCMR1_OC2M_2 0x4000U
7233 #define TIM_CCMR1_OC2CE 0x8000U
7235 /*----------------------------------------------------------------------------*/
7236 
7237 #define TIM_CCMR1_IC1PSC 0x000CU
7238 #define TIM_CCMR1_IC1PSC_0 0x0004U
7239 #define TIM_CCMR1_IC1PSC_1 0x0008U
7241 #define TIM_CCMR1_IC1F 0x00F0U
7242 #define TIM_CCMR1_IC1F_0 0x0010U
7243 #define TIM_CCMR1_IC1F_1 0x0020U
7244 #define TIM_CCMR1_IC1F_2 0x0040U
7245 #define TIM_CCMR1_IC1F_3 0x0080U
7247 #define TIM_CCMR1_IC2PSC 0x0C00U
7248 #define TIM_CCMR1_IC2PSC_0 0x0400U
7249 #define TIM_CCMR1_IC2PSC_1 0x0800U
7251 #define TIM_CCMR1_IC2F 0xF000U
7252 #define TIM_CCMR1_IC2F_0 0x1000U
7253 #define TIM_CCMR1_IC2F_1 0x2000U
7254 #define TIM_CCMR1_IC2F_2 0x4000U
7255 #define TIM_CCMR1_IC2F_3 0x8000U
7257 /****************** Bit definition for TIM_CCMR2 register *******************/
7258 #define TIM_CCMR2_CC3S 0x0003U
7259 #define TIM_CCMR2_CC3S_0 0x0001U
7260 #define TIM_CCMR2_CC3S_1 0x0002U
7262 #define TIM_CCMR2_OC3FE 0x0004U
7263 #define TIM_CCMR2_OC3PE 0x0008U
7265 #define TIM_CCMR2_OC3M 0x0070U
7266 #define TIM_CCMR2_OC3M_0 0x0010U
7267 #define TIM_CCMR2_OC3M_1 0x0020U
7268 #define TIM_CCMR2_OC3M_2 0x0040U
7270 #define TIM_CCMR2_OC3CE 0x0080U
7272 #define TIM_CCMR2_CC4S 0x0300U
7273 #define TIM_CCMR2_CC4S_0 0x0100U
7274 #define TIM_CCMR2_CC4S_1 0x0200U
7276 #define TIM_CCMR2_OC4FE 0x0400U
7277 #define TIM_CCMR2_OC4PE 0x0800U
7279 #define TIM_CCMR2_OC4M 0x7000U
7280 #define TIM_CCMR2_OC4M_0 0x1000U
7281 #define TIM_CCMR2_OC4M_1 0x2000U
7282 #define TIM_CCMR2_OC4M_2 0x4000U
7284 #define TIM_CCMR2_OC4CE 0x8000U
7286 /*----------------------------------------------------------------------------*/
7287 
7288 #define TIM_CCMR2_IC3PSC 0x000CU
7289 #define TIM_CCMR2_IC3PSC_0 0x0004U
7290 #define TIM_CCMR2_IC3PSC_1 0x0008U
7292 #define TIM_CCMR2_IC3F 0x00F0U
7293 #define TIM_CCMR2_IC3F_0 0x0010U
7294 #define TIM_CCMR2_IC3F_1 0x0020U
7295 #define TIM_CCMR2_IC3F_2 0x0040U
7296 #define TIM_CCMR2_IC3F_3 0x0080U
7298 #define TIM_CCMR2_IC4PSC 0x0C00U
7299 #define TIM_CCMR2_IC4PSC_0 0x0400U
7300 #define TIM_CCMR2_IC4PSC_1 0x0800U
7302 #define TIM_CCMR2_IC4F 0xF000U
7303 #define TIM_CCMR2_IC4F_0 0x1000U
7304 #define TIM_CCMR2_IC4F_1 0x2000U
7305 #define TIM_CCMR2_IC4F_2 0x4000U
7306 #define TIM_CCMR2_IC4F_3 0x8000U
7308 /******************* Bit definition for TIM_CCER register *******************/
7309 #define TIM_CCER_CC1E 0x0001U
7310 #define TIM_CCER_CC1P 0x0002U
7311 #define TIM_CCER_CC1NE 0x0004U
7312 #define TIM_CCER_CC1NP 0x0008U
7313 #define TIM_CCER_CC2E 0x0010U
7314 #define TIM_CCER_CC2P 0x0020U
7315 #define TIM_CCER_CC2NE 0x0040U
7316 #define TIM_CCER_CC2NP 0x0080U
7317 #define TIM_CCER_CC3E 0x0100U
7318 #define TIM_CCER_CC3P 0x0200U
7319 #define TIM_CCER_CC3NE 0x0400U
7320 #define TIM_CCER_CC3NP 0x0800U
7321 #define TIM_CCER_CC4E 0x1000U
7322 #define TIM_CCER_CC4P 0x2000U
7323 #define TIM_CCER_CC4NP 0x8000U
7325 /******************* Bit definition for TIM_CNT register ********************/
7326 #define TIM_CNT_CNT 0xFFFFU
7328 /******************* Bit definition for TIM_PSC register ********************/
7329 #define TIM_PSC_PSC 0xFFFFU
7331 /******************* Bit definition for TIM_ARR register ********************/
7332 #define TIM_ARR_ARR 0xFFFFU
7334 /******************* Bit definition for TIM_RCR register ********************/
7335 #define TIM_RCR_REP 0xFFU
7337 /******************* Bit definition for TIM_CCR1 register *******************/
7338 #define TIM_CCR1_CCR1 0xFFFFU
7340 /******************* Bit definition for TIM_CCR2 register *******************/
7341 #define TIM_CCR2_CCR2 0xFFFFU
7343 /******************* Bit definition for TIM_CCR3 register *******************/
7344 #define TIM_CCR3_CCR3 0xFFFFU
7346 /******************* Bit definition for TIM_CCR4 register *******************/
7347 #define TIM_CCR4_CCR4 0xFFFFU
7349 /******************* Bit definition for TIM_BDTR register *******************/
7350 #define TIM_BDTR_DTG 0x00FFU
7351 #define TIM_BDTR_DTG_0 0x0001U
7352 #define TIM_BDTR_DTG_1 0x0002U
7353 #define TIM_BDTR_DTG_2 0x0004U
7354 #define TIM_BDTR_DTG_3 0x0008U
7355 #define TIM_BDTR_DTG_4 0x0010U
7356 #define TIM_BDTR_DTG_5 0x0020U
7357 #define TIM_BDTR_DTG_6 0x0040U
7358 #define TIM_BDTR_DTG_7 0x0080U
7360 #define TIM_BDTR_LOCK 0x0300U
7361 #define TIM_BDTR_LOCK_0 0x0100U
7362 #define TIM_BDTR_LOCK_1 0x0200U
7364 #define TIM_BDTR_OSSI 0x0400U
7365 #define TIM_BDTR_OSSR 0x0800U
7366 #define TIM_BDTR_BKE 0x1000U
7367 #define TIM_BDTR_BKP 0x2000U
7368 #define TIM_BDTR_AOE 0x4000U
7369 #define TIM_BDTR_MOE 0x8000U
7371 /******************* Bit definition for TIM_DCR register ********************/
7372 #define TIM_DCR_DBA 0x001FU
7373 #define TIM_DCR_DBA_0 0x0001U
7374 #define TIM_DCR_DBA_1 0x0002U
7375 #define TIM_DCR_DBA_2 0x0004U
7376 #define TIM_DCR_DBA_3 0x0008U
7377 #define TIM_DCR_DBA_4 0x0010U
7379 #define TIM_DCR_DBL 0x1F00U
7380 #define TIM_DCR_DBL_0 0x0100U
7381 #define TIM_DCR_DBL_1 0x0200U
7382 #define TIM_DCR_DBL_2 0x0400U
7383 #define TIM_DCR_DBL_3 0x0800U
7384 #define TIM_DCR_DBL_4 0x1000U
7386 /******************* Bit definition for TIM_DMAR register *******************/
7387 #define TIM_DMAR_DMAB 0xFFFFU
7389 /******************* Bit definition for TIM_OR register *********************/
7390 #define TIM_OR_TI4_RMP 0x00C0U
7391 #define TIM_OR_TI4_RMP_0 0x0040U
7392 #define TIM_OR_TI4_RMP_1 0x0080U
7393 #define TIM_OR_ITR1_RMP 0x0C00U
7394 #define TIM_OR_ITR1_RMP_0 0x0400U
7395 #define TIM_OR_ITR1_RMP_1 0x0800U
7398 /******************************************************************************/
7399 /* */
7400 /* Universal Synchronous Asynchronous Receiver Transmitter */
7401 /* */
7402 /******************************************************************************/
7403 /******************* Bit definition for USART_SR register *******************/
7404 #define USART_SR_PE 0x0001U
7405 #define USART_SR_FE 0x0002U
7406 #define USART_SR_NE 0x0004U
7407 #define USART_SR_ORE 0x0008U
7408 #define USART_SR_IDLE 0x0010U
7409 #define USART_SR_RXNE 0x0020U
7410 #define USART_SR_TC 0x0040U
7411 #define USART_SR_TXE 0x0080U
7412 #define USART_SR_LBD 0x0100U
7413 #define USART_SR_CTS 0x0200U
7415 /******************* Bit definition for USART_DR register *******************/
7416 #define USART_DR_DR 0x01FFU
7418 /****************** Bit definition for USART_BRR register *******************/
7419 #define USART_BRR_DIV_Fraction 0x000FU
7420 #define USART_BRR_DIV_Mantissa 0xFFF0U
7422 /****************** Bit definition for USART_CR1 register *******************/
7423 #define USART_CR1_SBK 0x0001U
7424 #define USART_CR1_RWU 0x0002U
7425 #define USART_CR1_RE 0x0004U
7426 #define USART_CR1_TE 0x0008U
7427 #define USART_CR1_IDLEIE 0x0010U
7428 #define USART_CR1_RXNEIE 0x0020U
7429 #define USART_CR1_TCIE 0x0040U
7430 #define USART_CR1_TXEIE 0x0080U
7431 #define USART_CR1_PEIE 0x0100U
7432 #define USART_CR1_PS 0x0200U
7433 #define USART_CR1_PCE 0x0400U
7434 #define USART_CR1_WAKE 0x0800U
7435 #define USART_CR1_M 0x1000U
7436 #define USART_CR1_UE 0x2000U
7437 #define USART_CR1_OVER8 0x8000U
7439 /****************** Bit definition for USART_CR2 register *******************/
7440 #define USART_CR2_ADD 0x000FU
7441 #define USART_CR2_LBDL 0x0020U
7442 #define USART_CR2_LBDIE 0x0040U
7443 #define USART_CR2_LBCL 0x0100U
7444 #define USART_CR2_CPHA 0x0200U
7445 #define USART_CR2_CPOL 0x0400U
7446 #define USART_CR2_CLKEN 0x0800U
7448 #define USART_CR2_STOP 0x3000U
7449 #define USART_CR2_STOP_0 0x1000U
7450 #define USART_CR2_STOP_1 0x2000U
7452 #define USART_CR2_LINEN 0x4000U
7454 /****************** Bit definition for USART_CR3 register *******************/
7455 #define USART_CR3_EIE 0x0001U
7456 #define USART_CR3_IREN 0x0002U
7457 #define USART_CR3_IRLP 0x0004U
7458 #define USART_CR3_HDSEL 0x0008U
7459 #define USART_CR3_NACK 0x0010U
7460 #define USART_CR3_SCEN 0x0020U
7461 #define USART_CR3_DMAR 0x0040U
7462 #define USART_CR3_DMAT 0x0080U
7463 #define USART_CR3_RTSE 0x0100U
7464 #define USART_CR3_CTSE 0x0200U
7465 #define USART_CR3_CTSIE 0x0400U
7466 #define USART_CR3_ONEBIT 0x0800U
7468 /****************** Bit definition for USART_GTPR register ******************/
7469 #define USART_GTPR_PSC 0x00FFU
7470 #define USART_GTPR_PSC_0 0x0001U
7471 #define USART_GTPR_PSC_1 0x0002U
7472 #define USART_GTPR_PSC_2 0x0004U
7473 #define USART_GTPR_PSC_3 0x0008U
7474 #define USART_GTPR_PSC_4 0x0010U
7475 #define USART_GTPR_PSC_5 0x0020U
7476 #define USART_GTPR_PSC_6 0x0040U
7477 #define USART_GTPR_PSC_7 0x0080U
7479 #define USART_GTPR_GT 0xFF00U
7481 /******************************************************************************/
7482 /* */
7483 /* Window WATCHDOG */
7484 /* */
7485 /******************************************************************************/
7486 /******************* Bit definition for WWDG_CR register ********************/
7487 #define WWDG_CR_T 0x7FU
7488 #define WWDG_CR_T_0 0x01U
7489 #define WWDG_CR_T_1 0x02U
7490 #define WWDG_CR_T_2 0x04U
7491 #define WWDG_CR_T_3 0x08U
7492 #define WWDG_CR_T_4 0x10U
7493 #define WWDG_CR_T_5 0x20U
7494 #define WWDG_CR_T_6 0x40U
7495 /* Legacy defines */
7496 #define WWDG_CR_T0 WWDG_CR_T_0
7497 #define WWDG_CR_T1 WWDG_CR_T_1
7498 #define WWDG_CR_T2 WWDG_CR_T_2
7499 #define WWDG_CR_T3 WWDG_CR_T_3
7500 #define WWDG_CR_T4 WWDG_CR_T_4
7501 #define WWDG_CR_T5 WWDG_CR_T_5
7502 #define WWDG_CR_T6 WWDG_CR_T_6
7503 
7504 #define WWDG_CR_WDGA 0x80U
7506 /******************* Bit definition for WWDG_CFR register *******************/
7507 #define WWDG_CFR_W 0x007FU
7508 #define WWDG_CFR_W_0 0x0001U
7509 #define WWDG_CFR_W_1 0x0002U
7510 #define WWDG_CFR_W_2 0x0004U
7511 #define WWDG_CFR_W_3 0x0008U
7512 #define WWDG_CFR_W_4 0x0010U
7513 #define WWDG_CFR_W_5 0x0020U
7514 #define WWDG_CFR_W_6 0x0040U
7515 /* Legacy defines */
7516 #define WWDG_CFR_W0 WWDG_CFR_W_0
7517 #define WWDG_CFR_W1 WWDG_CFR_W_1
7518 #define WWDG_CFR_W2 WWDG_CFR_W_2
7519 #define WWDG_CFR_W3 WWDG_CFR_W_3
7520 #define WWDG_CFR_W4 WWDG_CFR_W_4
7521 #define WWDG_CFR_W5 WWDG_CFR_W_5
7522 #define WWDG_CFR_W6 WWDG_CFR_W_6
7523 
7524 #define WWDG_CFR_WDGTB 0x0180U
7525 #define WWDG_CFR_WDGTB_0 0x0080U
7526 #define WWDG_CFR_WDGTB_1 0x0100U
7527 /* Legacy defines */
7528 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
7529 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
7530 
7531 #define WWDG_CFR_EWI 0x0200U
7533 /******************* Bit definition for WWDG_SR register ********************/
7534 #define WWDG_SR_EWIF 0x01U
7537 /******************************************************************************/
7538 /* */
7539 /* DBG */
7540 /* */
7541 /******************************************************************************/
7542 /******************** Bit definition for DBGMCU_IDCODE register *************/
7543 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
7544 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
7545 
7546 /******************** Bit definition for DBGMCU_CR register *****************/
7547 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
7548 #define DBGMCU_CR_DBG_STOP 0x00000002U
7549 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
7550 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
7551 
7552 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
7553 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
7554 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
7556 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
7557 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
7558 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
7559 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
7560 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
7561 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
7562 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
7563 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
7564 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
7565 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
7566 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
7567 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
7568 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
7569 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
7570 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
7571 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
7572 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
7573 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
7574 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
7575 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
7576 
7577 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
7578 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
7579 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
7580 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
7581 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
7582 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
7583 
7584 /******************************************************************************/
7585 /* */
7586 /* Ethernet MAC Registers bits definitions */
7587 /* */
7588 /******************************************************************************/
7589 /* Bit definition for Ethernet MAC Control Register register */
7590 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
7591 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
7592 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
7593 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
7594  #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
7595  #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
7596  #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
7597  #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
7598  #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
7599  #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
7600  #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
7601 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
7602 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
7603 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
7604 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
7605 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
7606 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
7607 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
7608 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
7609 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7610  a transmission attempt during retries after a collision: 0 =< r <2^k */
7611  #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
7612  #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
7613  #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
7614  #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
7615 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
7616 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
7617 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
7618 
7619 /* Bit definition for Ethernet MAC Frame Filter Register */
7620 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
7621 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
7622 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
7623 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
7624 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
7625  #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
7626  #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
7627  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
7628 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
7629 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
7630 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
7631 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
7632 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
7633 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
7634 
7635 /* Bit definition for Ethernet MAC Hash Table High Register */
7636 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
7637 
7638 /* Bit definition for Ethernet MAC Hash Table Low Register */
7639 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
7640 
7641 /* Bit definition for Ethernet MAC MII Address Register */
7642 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
7643 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
7644 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
7645  #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
7646  #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
7647  #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7648  #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7649  #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
7650 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
7651 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
7652 
7653 /* Bit definition for Ethernet MAC MII Data Register */
7654 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
7655 
7656 /* Bit definition for Ethernet MAC Flow Control Register */
7657 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
7658 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
7659 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
7660  #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
7661  #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
7662  #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
7663  #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
7664 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
7665 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
7666 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
7667 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
7668 
7669 /* Bit definition for Ethernet MAC VLAN Tag Register */
7670 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
7671 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
7672 
7673 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7674 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
7675 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7676  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7677 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7678  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7679  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7680  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7681  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7682  RSVD - Filter1 Command - RSVD - Filter0 Command
7683  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7684  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7685  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7686 
7687 /* Bit definition for Ethernet MAC PMT Control and Status Register */
7688 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
7689 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
7690 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
7691 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
7692 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
7693 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
7694 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
7695 
7696 /* Bit definition for Ethernet MAC Status Register */
7697 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
7698 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
7699 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
7700 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
7701 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
7702 
7703 /* Bit definition for Ethernet MAC Interrupt Mask Register */
7704 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
7705 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
7706 
7707 /* Bit definition for Ethernet MAC Address0 High Register */
7708 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
7709 
7710 /* Bit definition for Ethernet MAC Address0 Low Register */
7711 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
7712 
7713 /* Bit definition for Ethernet MAC Address1 High Register */
7714 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
7715 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
7716 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7717  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7718  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7719  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7720  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7721  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7722  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
7723 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
7724 
7725 /* Bit definition for Ethernet MAC Address1 Low Register */
7726 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
7727 
7728 /* Bit definition for Ethernet MAC Address2 High Register */
7729 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
7730 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
7731 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
7732  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7733  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7734  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7735  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7736  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7737  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7738 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
7739 
7740 /* Bit definition for Ethernet MAC Address2 Low Register */
7741 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
7742 
7743 /* Bit definition for Ethernet MAC Address3 High Register */
7744 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
7745 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
7746 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
7747  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
7748  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
7749  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
7750  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
7751  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
7752  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
7753 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
7754 
7755 /* Bit definition for Ethernet MAC Address3 Low Register */
7756 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
7757 
7758 /******************************************************************************/
7759 /* Ethernet MMC Registers bits definition */
7760 /******************************************************************************/
7761 
7762 /* Bit definition for Ethernet MMC Contol Register */
7763 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
7764 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
7765 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
7766 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
7767 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
7768 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
7769 
7770 /* Bit definition for Ethernet MMC Receive Interrupt Register */
7771 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
7772 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
7773 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
7774 
7775 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
7776 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
7777 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
7778 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
7779 
7780 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
7781 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
7782 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
7783 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
7784 
7785 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
7786 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
7787 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
7788 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
7789 
7790 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
7791 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
7792 
7793 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
7794 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
7795 
7796 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
7797 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
7798 
7799 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
7800 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
7801 
7802 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
7803 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
7804 
7805 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
7806 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
7807 
7808 /******************************************************************************/
7809 /* Ethernet PTP Registers bits definition */
7810 /******************************************************************************/
7811 
7812 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
7813 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
7814 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
7815 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
7816 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
7817 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
7818 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
7819 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
7820 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
7821 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
7822 
7823 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
7824 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
7825 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
7826 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
7827 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
7828 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
7829 
7830 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
7831 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
7832 
7833 /* Bit definition for Ethernet PTP Time Stamp High Register */
7834 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
7835 
7836 /* Bit definition for Ethernet PTP Time Stamp Low Register */
7837 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
7838 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
7839 
7840 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
7841 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
7842 
7843 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7844 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
7845 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
7846 
7847 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
7848 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
7849 
7850 /* Bit definition for Ethernet PTP Target Time High Register */
7851 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
7852 
7853 /* Bit definition for Ethernet PTP Target Time Low Register */
7854 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
7855 
7856 /* Bit definition for Ethernet PTP Time Stamp Status Register */
7857 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
7858 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
7859 
7860 /******************************************************************************/
7861 /* Ethernet DMA Registers bits definition */
7862 /******************************************************************************/
7863 
7864 /* Bit definition for Ethernet DMA Bus Mode Register */
7865 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
7866 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
7867 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
7868 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
7869  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7870  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7871  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7872  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7873  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7874  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7875  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7876  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7877  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7878  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7879  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7880  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7881 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
7882 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
7883  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
7884  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
7885  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
7886  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
7887 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
7888  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7889  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7890  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7891  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7892  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7893  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7894  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7895  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7896  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7897  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7898  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7899  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7900 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
7901 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
7902 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
7903 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
7904 
7905 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7906 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
7907 
7908 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
7909 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
7910 
7911 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7912 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
7913 
7914 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7915 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
7916 
7917 /* Bit definition for Ethernet DMA Status Register */
7918 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
7919 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
7920 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
7921 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
7922  /* combination with EBS[2:0] for GetFlagStatus function */
7923  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
7924  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
7925  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
7926 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
7927  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
7928  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
7929  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
7930  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
7931  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
7932  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
7933 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
7934  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
7935  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
7936  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
7937  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
7938  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
7939  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
7940 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
7941 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
7942 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
7943 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
7944 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
7945 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
7946 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
7947 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
7948 #define ETH_DMASR_RS 0x00000040U /* Receive status */
7949 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
7950 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
7951 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
7952 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
7953 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
7954 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
7955 
7956 /* Bit definition for Ethernet DMA Operation Mode Register */
7957 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
7958 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
7959 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
7960 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
7961 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
7962 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
7963  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7964  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7965  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7966  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7967  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7968  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7969  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7970  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7971 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
7972 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
7973 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
7974 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
7975  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
7976  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
7977  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
7978  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
7979 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
7980 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
7981 
7982 /* Bit definition for Ethernet DMA Interrupt Enable Register */
7983 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
7984 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
7985 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
7986 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
7987 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
7988 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
7989 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
7990 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
7991 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
7992 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
7993 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
7994 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
7995 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
7996 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
7997 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
7998 
7999 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8000 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
8001 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
8002 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
8003 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
8004 
8005 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8006 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
8007 
8008 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8009 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
8010 
8011 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8012 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
8013 
8014 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8015 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
8016 
8017 /******************************************************************************/
8018 /* */
8019 /* USB_OTG */
8020 /* */
8021 /******************************************************************************/
8022 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
8023 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
8024 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
8025 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
8026 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
8027 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
8028 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
8029 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
8030 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
8031 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
8032 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U
8034 /******************** Bit definition forUSB_OTG_HCFG register ********************/
8035 
8036 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
8037 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
8038 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
8039 #define USB_OTG_HCFG_FSLSS 0x00000004U
8041 /******************** Bit definition forUSB_OTG_DCFG register ********************/
8042 
8043 #define USB_OTG_DCFG_DSPD 0x00000003U
8044 #define USB_OTG_DCFG_DSPD_0 0x00000001U
8045 #define USB_OTG_DCFG_DSPD_1 0x00000002U
8046 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
8048 #define USB_OTG_DCFG_DAD 0x000007F0U
8049 #define USB_OTG_DCFG_DAD_0 0x00000010U
8050 #define USB_OTG_DCFG_DAD_1 0x00000020U
8051 #define USB_OTG_DCFG_DAD_2 0x00000040U
8052 #define USB_OTG_DCFG_DAD_3 0x00000080U
8053 #define USB_OTG_DCFG_DAD_4 0x00000100U
8054 #define USB_OTG_DCFG_DAD_5 0x00000200U
8055 #define USB_OTG_DCFG_DAD_6 0x00000400U
8057 #define USB_OTG_DCFG_PFIVL 0x00001800U
8058 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
8059 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
8061 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
8062 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
8063 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
8065 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
8066 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
8067 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
8068 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
8070 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
8071 #define USB_OTG_GOTGINT_SEDET 0x00000004U
8072 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
8073 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
8074 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
8075 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
8076 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
8078 /******************** Bit definition forUSB_OTG_DCTL register ********************/
8079 #define USB_OTG_DCTL_RWUSIG 0x00000001U
8080 #define USB_OTG_DCTL_SDIS 0x00000002U
8081 #define USB_OTG_DCTL_GINSTS 0x00000004U
8082 #define USB_OTG_DCTL_GONSTS 0x00000008U
8084 #define USB_OTG_DCTL_TCTL 0x00000070U
8085 #define USB_OTG_DCTL_TCTL_0 0x00000010U
8086 #define USB_OTG_DCTL_TCTL_1 0x00000020U
8087 #define USB_OTG_DCTL_TCTL_2 0x00000040U
8088 #define USB_OTG_DCTL_SGINAK 0x00000080U
8089 #define USB_OTG_DCTL_CGINAK 0x00000100U
8090 #define USB_OTG_DCTL_SGONAK 0x00000200U
8091 #define USB_OTG_DCTL_CGONAK 0x00000400U
8092 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
8094 /******************** Bit definition forUSB_OTG_HFIR register ********************/
8095 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
8097 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
8098 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
8099 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
8101 /******************** Bit definition forUSB_OTG_DSTS register ********************/
8102 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
8104 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
8105 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
8106 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
8107 #define USB_OTG_DSTS_EERR 0x00000008U
8108 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
8110 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
8111 #define USB_OTG_GAHBCFG_GINT 0x00000001U
8113 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
8114 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
8115 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
8116 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
8117 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
8118 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
8119 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
8120 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
8122 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
8123 
8124 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
8125 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
8126 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
8127 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
8128 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
8129 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
8130 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
8132 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
8133 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
8134 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
8135 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
8136 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
8137 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
8138 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
8139 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
8140 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
8141 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
8142 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
8143 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
8144 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
8145 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
8146 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
8147 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
8148 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
8149 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
8151 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
8152 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
8153 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
8154 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
8155 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
8156 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
8158 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
8159 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
8160 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
8161 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
8162 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
8163 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
8164 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
8165 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
8167 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
8168 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
8169 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
8170 #define USB_OTG_DIEPMSK_TOM 0x00000008U
8171 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
8172 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
8173 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
8174 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
8175 #define USB_OTG_DIEPMSK_BIM 0x00000200U
8177 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
8178 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
8180 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
8181 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
8182 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
8183 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
8184 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
8185 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
8186 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
8187 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
8188 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
8190 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
8191 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
8192 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
8193 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
8194 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
8195 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
8196 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
8197 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
8198 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
8200 /******************** Bit definition forUSB_OTG_HAINT register ********************/
8201 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
8203 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
8204 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
8205 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
8206 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
8207 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
8208 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
8209 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
8210 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
8212 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
8213 #define USB_OTG_GINTSTS_CMOD 0x00000001U
8214 #define USB_OTG_GINTSTS_MMIS 0x00000002U
8215 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
8216 #define USB_OTG_GINTSTS_SOF 0x00000008U
8217 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
8218 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
8219 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
8220 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
8221 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
8222 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
8223 #define USB_OTG_GINTSTS_USBRST 0x00001000U
8224 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
8225 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
8226 #define USB_OTG_GINTSTS_EOPF 0x00008000U
8227 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
8228 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
8229 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
8230 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
8231 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
8232 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
8233 #define USB_OTG_GINTSTS_HCINT 0x02000000U
8234 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
8235 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
8236 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
8237 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
8238 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
8240 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
8241 #define USB_OTG_GINTMSK_MMISM 0x00000002U
8242 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
8243 #define USB_OTG_GINTMSK_SOFM 0x00000008U
8244 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
8245 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
8246 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
8247 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
8248 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
8249 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
8250 #define USB_OTG_GINTMSK_USBRST 0x00001000U
8251 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
8252 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
8253 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
8254 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
8255 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
8256 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
8257 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
8258 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
8259 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
8260 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
8261 #define USB_OTG_GINTMSK_HCIM 0x02000000U
8262 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
8263 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
8264 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
8265 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
8266 #define USB_OTG_GINTMSK_WUIM 0x80000000U
8268 /******************** Bit definition forUSB_OTG_DAINT register ********************/
8269 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
8270 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
8272 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
8273 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
8275 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8276 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
8277 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
8278 #define USB_OTG_GRXSTSP_DPID 0x00018000U
8279 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
8281 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
8282 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
8283 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
8285 /******************** Bit definition for OTG register ********************/
8286 
8287 #define USB_OTG_CHNUM 0x0000000FU
8288 #define USB_OTG_CHNUM_0 0x00000001U
8289 #define USB_OTG_CHNUM_1 0x00000002U
8290 #define USB_OTG_CHNUM_2 0x00000004U
8291 #define USB_OTG_CHNUM_3 0x00000008U
8292 #define USB_OTG_BCNT 0x00007FF0U
8294 #define USB_OTG_DPID 0x00018000U
8295 #define USB_OTG_DPID_0 0x00008000U
8296 #define USB_OTG_DPID_1 0x00010000U
8298 #define USB_OTG_PKTSTS 0x001E0000U
8299 #define USB_OTG_PKTSTS_0 0x00020000U
8300 #define USB_OTG_PKTSTS_1 0x00040000U
8301 #define USB_OTG_PKTSTS_2 0x00080000U
8302 #define USB_OTG_PKTSTS_3 0x00100000U
8304 #define USB_OTG_EPNUM 0x0000000FU
8305 #define USB_OTG_EPNUM_0 0x00000001U
8306 #define USB_OTG_EPNUM_1 0x00000002U
8307 #define USB_OTG_EPNUM_2 0x00000004U
8308 #define USB_OTG_EPNUM_3 0x00000008U
8310 #define USB_OTG_FRMNUM 0x01E00000U
8311 #define USB_OTG_FRMNUM_0 0x00200000U
8312 #define USB_OTG_FRMNUM_1 0x00400000U
8313 #define USB_OTG_FRMNUM_2 0x00800000U
8314 #define USB_OTG_FRMNUM_3 0x01000000U
8316 /******************** Bit definition for OTG register ********************/
8317 
8318 #define USB_OTG_CHNUM 0x0000000FU
8319 #define USB_OTG_CHNUM_0 0x00000001U
8320 #define USB_OTG_CHNUM_1 0x00000002U
8321 #define USB_OTG_CHNUM_2 0x00000004U
8322 #define USB_OTG_CHNUM_3 0x00000008U
8323 #define USB_OTG_BCNT 0x00007FF0U
8325 #define USB_OTG_DPID 0x00018000U
8326 #define USB_OTG_DPID_0 0x00008000U
8327 #define USB_OTG_DPID_1 0x00010000U
8329 #define USB_OTG_PKTSTS 0x001E0000U
8330 #define USB_OTG_PKTSTS_0 0x00020000U
8331 #define USB_OTG_PKTSTS_1 0x00040000U
8332 #define USB_OTG_PKTSTS_2 0x00080000U
8333 #define USB_OTG_PKTSTS_3 0x00100000U
8335 #define USB_OTG_EPNUM 0x0000000FU
8336 #define USB_OTG_EPNUM_0 0x00000001U
8337 #define USB_OTG_EPNUM_1 0x00000002U
8338 #define USB_OTG_EPNUM_2 0x00000004U
8339 #define USB_OTG_EPNUM_3 0x00000008U
8341 #define USB_OTG_FRMNUM 0x01E00000U
8342 #define USB_OTG_FRMNUM_0 0x00200000U
8343 #define USB_OTG_FRMNUM_1 0x00400000U
8344 #define USB_OTG_FRMNUM_2 0x00800000U
8345 #define USB_OTG_FRMNUM_3 0x01000000U
8347 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
8348 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
8350 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
8351 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
8353 /******************** Bit definition for OTG register ********************/
8354 #define USB_OTG_NPTXFSA 0x0000FFFFU
8355 #define USB_OTG_NPTXFD 0xFFFF0000U
8356 #define USB_OTG_TX0FSA 0x0000FFFFU
8357 #define USB_OTG_TX0FD 0xFFFF0000U
8359 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
8360 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
8362 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
8363 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
8365 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
8366 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
8367 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
8368 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
8369 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
8370 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
8371 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
8372 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
8373 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
8375 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
8376 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
8377 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
8378 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
8379 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
8380 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
8381 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
8382 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
8384 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
8385 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
8386 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
8388 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
8389 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
8390 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
8391 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
8392 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
8393 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
8394 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
8395 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
8396 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
8397 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
8398 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
8400 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
8401 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
8402 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
8403 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
8404 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
8405 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
8406 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
8407 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
8408 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
8409 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
8410 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
8412 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
8413 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
8415 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
8416 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
8417 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
8419 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
8420 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
8421 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U
8422 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U
8423 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U
8424 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U
8425 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U
8427 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
8428 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
8429 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
8431 /******************** Bit definition forUSB_OTG_CID register ********************/
8432 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
8434 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
8435 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
8436 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
8437 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
8438 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
8439 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
8440 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
8441 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
8442 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
8443 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
8445 /******************** Bit definition forUSB_OTG_HPRT register ********************/
8446 #define USB_OTG_HPRT_PCSTS 0x00000001U
8447 #define USB_OTG_HPRT_PCDET 0x00000002U
8448 #define USB_OTG_HPRT_PENA 0x00000004U
8449 #define USB_OTG_HPRT_PENCHNG 0x00000008U
8450 #define USB_OTG_HPRT_POCA 0x00000010U
8451 #define USB_OTG_HPRT_POCCHNG 0x00000020U
8452 #define USB_OTG_HPRT_PRES 0x00000040U
8453 #define USB_OTG_HPRT_PSUSP 0x00000080U
8454 #define USB_OTG_HPRT_PRST 0x00000100U
8456 #define USB_OTG_HPRT_PLSTS 0x00000C00U
8457 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
8458 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
8459 #define USB_OTG_HPRT_PPWR 0x00001000U
8461 #define USB_OTG_HPRT_PTCTL 0x0001E000U
8462 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
8463 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
8464 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
8465 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
8467 #define USB_OTG_HPRT_PSPD 0x00060000U
8468 #define USB_OTG_HPRT_PSPD_0 0x00020000U
8469 #define USB_OTG_HPRT_PSPD_1 0x00040000U
8471 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
8472 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
8473 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
8474 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
8475 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
8476 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
8477 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
8478 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
8479 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
8480 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
8481 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
8482 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
8484 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
8485 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
8486 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
8488 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
8489 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
8490 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
8491 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
8492 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
8494 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
8495 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
8496 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
8497 #define USB_OTG_DIEPCTL_STALL 0x00200000U
8499 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
8500 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
8501 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
8502 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
8503 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
8504 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
8505 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
8506 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
8507 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
8508 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
8509 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
8511 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
8512 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
8514 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
8515 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
8516 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
8517 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
8518 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
8519 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
8520 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
8522 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
8523 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
8524 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
8526 #define USB_OTG_HCCHAR_MC 0x00300000U
8527 #define USB_OTG_HCCHAR_MC_0 0x00100000U
8528 #define USB_OTG_HCCHAR_MC_1 0x00200000U
8530 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
8531 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
8532 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
8533 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
8534 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
8535 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
8536 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
8537 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
8538 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
8539 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
8540 #define USB_OTG_HCCHAR_CHENA 0x80000000U
8542 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
8543 
8544 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
8545 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
8546 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
8547 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
8548 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
8549 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
8550 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
8551 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
8553 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
8554 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
8555 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
8556 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
8557 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
8558 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
8559 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
8560 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
8562 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
8563 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
8564 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
8565 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
8566 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
8568 /******************** Bit definition forUSB_OTG_HCINT register ********************/
8569 #define USB_OTG_HCINT_XFRC 0x00000001U
8570 #define USB_OTG_HCINT_CHH 0x00000002U
8571 #define USB_OTG_HCINT_AHBERR 0x00000004U
8572 #define USB_OTG_HCINT_STALL 0x00000008U
8573 #define USB_OTG_HCINT_NAK 0x00000010U
8574 #define USB_OTG_HCINT_ACK 0x00000020U
8575 #define USB_OTG_HCINT_NYET 0x00000040U
8576 #define USB_OTG_HCINT_TXERR 0x00000080U
8577 #define USB_OTG_HCINT_BBERR 0x00000100U
8578 #define USB_OTG_HCINT_FRMOR 0x00000200U
8579 #define USB_OTG_HCINT_DTERR 0x00000400U
8581 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
8582 #define USB_OTG_DIEPINT_XFRC 0x00000001U
8583 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
8584 #define USB_OTG_DIEPINT_TOC 0x00000008U
8585 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
8586 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
8587 #define USB_OTG_DIEPINT_TXFE 0x00000080U
8588 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
8589 #define USB_OTG_DIEPINT_BNA 0x00000200U
8590 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
8591 #define USB_OTG_DIEPINT_BERR 0x00001000U
8592 #define USB_OTG_DIEPINT_NAK 0x00002000U
8594 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
8595 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
8596 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
8597 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
8598 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
8599 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
8600 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
8601 #define USB_OTG_HCINTMSK_NYET 0x00000040U
8602 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
8603 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
8604 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
8605 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
8607 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8608 
8609 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
8610 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
8611 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
8612 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
8613 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
8614 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
8615 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
8616 #define USB_OTG_HCTSIZ_DPID 0x60000000U
8617 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
8618 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
8620 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
8621 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
8623 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
8624 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
8626 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
8627 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
8629 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
8630 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
8631 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
8633 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
8634 
8635 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
8636 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
8637 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
8638 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
8639 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
8640 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
8641 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
8642 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
8643 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
8644 #define USB_OTG_DOEPCTL_STALL 0x00200000U
8645 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
8646 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
8647 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
8648 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
8650 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
8651 #define USB_OTG_DOEPINT_XFRC 0x00000001U
8652 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
8653 #define USB_OTG_DOEPINT_STUP 0x00000008U
8654 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
8655 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
8656 #define USB_OTG_DOEPINT_NYET 0x00004000U
8658 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
8659 
8660 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
8661 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
8663 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
8664 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
8665 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
8667 /******************** Bit definition for PCGCCTL register ********************/
8668 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
8669 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
8670 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
8685 /******************************* ADC Instances ********************************/
8686 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
8687  ((INSTANCE) == ADC2) || \
8688  ((INSTANCE) == ADC3))
8689 
8690 /******************************* CAN Instances ********************************/
8691 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
8692  ((INSTANCE) == CAN2))
8693 
8694 /******************************* CRC Instances ********************************/
8695 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8696 
8697 /******************************* DAC Instances ********************************/
8698 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
8699 
8700 /******************************* DCMI Instances *******************************/
8701 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
8702 
8703 /******************************* DMA2D Instances *******************************/
8704 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
8705 
8706 /******************************** DMA Instances *******************************/
8707 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
8708  ((INSTANCE) == DMA1_Stream1) || \
8709  ((INSTANCE) == DMA1_Stream2) || \
8710  ((INSTANCE) == DMA1_Stream3) || \
8711  ((INSTANCE) == DMA1_Stream4) || \
8712  ((INSTANCE) == DMA1_Stream5) || \
8713  ((INSTANCE) == DMA1_Stream6) || \
8714  ((INSTANCE) == DMA1_Stream7) || \
8715  ((INSTANCE) == DMA2_Stream0) || \
8716  ((INSTANCE) == DMA2_Stream1) || \
8717  ((INSTANCE) == DMA2_Stream2) || \
8718  ((INSTANCE) == DMA2_Stream3) || \
8719  ((INSTANCE) == DMA2_Stream4) || \
8720  ((INSTANCE) == DMA2_Stream5) || \
8721  ((INSTANCE) == DMA2_Stream6) || \
8722  ((INSTANCE) == DMA2_Stream7))
8723 
8724 /******************************* GPIO Instances *******************************/
8725 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8726  ((INSTANCE) == GPIOB) || \
8727  ((INSTANCE) == GPIOC) || \
8728  ((INSTANCE) == GPIOD) || \
8729  ((INSTANCE) == GPIOE) || \
8730  ((INSTANCE) == GPIOF) || \
8731  ((INSTANCE) == GPIOG) || \
8732  ((INSTANCE) == GPIOH) || \
8733  ((INSTANCE) == GPIOI) || \
8734  ((INSTANCE) == GPIOJ) || \
8735  ((INSTANCE) == GPIOK))
8736 
8737 /******************************** I2C Instances *******************************/
8738 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8739  ((INSTANCE) == I2C2) || \
8740  ((INSTANCE) == I2C3))
8741 
8742 /******************************** I2S Instances *******************************/
8743 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
8744  ((INSTANCE) == SPI3))
8745 
8746 /*************************** I2S Extended Instances ***************************/
8747 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
8748  ((INSTANCE) == SPI3) || \
8749  ((INSTANCE) == I2S2ext) || \
8750  ((INSTANCE) == I2S3ext))
8751 
8752 /******************************* RNG Instances ********************************/
8753 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
8754 
8755 /****************************** RTC Instances *********************************/
8756 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
8757 
8758 /******************************* SAI Instances ********************************/
8759 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
8760  ((PERIPH) == SAI1_Block_B))
8761 /* Legacy define */
8762 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
8763 
8764 /******************************** SPI Instances *******************************/
8765 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8766  ((INSTANCE) == SPI2) || \
8767  ((INSTANCE) == SPI3) || \
8768  ((INSTANCE) == SPI4) || \
8769  ((INSTANCE) == SPI5) || \
8770  ((INSTANCE) == SPI6))
8771 
8772 /*************************** SPI Extended Instances ***************************/
8773 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
8774  ((INSTANCE) == SPI2) || \
8775  ((INSTANCE) == SPI3) || \
8776  ((INSTANCE) == SPI4) || \
8777  ((INSTANCE) == SPI5) || \
8778  ((INSTANCE) == SPI6) || \
8779  ((INSTANCE) == I2S2ext) || \
8780  ((INSTANCE) == I2S3ext))
8781 
8782 /****************** TIM Instances : All supported instances *******************/
8783 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8784  ((INSTANCE) == TIM2) || \
8785  ((INSTANCE) == TIM3) || \
8786  ((INSTANCE) == TIM4) || \
8787  ((INSTANCE) == TIM5) || \
8788  ((INSTANCE) == TIM6) || \
8789  ((INSTANCE) == TIM7) || \
8790  ((INSTANCE) == TIM8) || \
8791  ((INSTANCE) == TIM9) || \
8792  ((INSTANCE) == TIM10) || \
8793  ((INSTANCE) == TIM11) || \
8794  ((INSTANCE) == TIM12) || \
8795  ((INSTANCE) == TIM13) || \
8796  ((INSTANCE) == TIM14))
8797 
8798 /************* TIM Instances : at least 1 capture/compare channel *************/
8799 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8800  ((INSTANCE) == TIM2) || \
8801  ((INSTANCE) == TIM3) || \
8802  ((INSTANCE) == TIM4) || \
8803  ((INSTANCE) == TIM5) || \
8804  ((INSTANCE) == TIM8) || \
8805  ((INSTANCE) == TIM9) || \
8806  ((INSTANCE) == TIM10) || \
8807  ((INSTANCE) == TIM11) || \
8808  ((INSTANCE) == TIM12) || \
8809  ((INSTANCE) == TIM13) || \
8810  ((INSTANCE) == TIM14))
8811 
8812 /************ TIM Instances : at least 2 capture/compare channels *************/
8813 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8814  ((INSTANCE) == TIM2) || \
8815  ((INSTANCE) == TIM3) || \
8816  ((INSTANCE) == TIM4) || \
8817  ((INSTANCE) == TIM5) || \
8818  ((INSTANCE) == TIM8) || \
8819  ((INSTANCE) == TIM9) || \
8820  ((INSTANCE) == TIM12))
8821 
8822 /************ TIM Instances : at least 3 capture/compare channels *************/
8823 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8824  ((INSTANCE) == TIM2) || \
8825  ((INSTANCE) == TIM3) || \
8826  ((INSTANCE) == TIM4) || \
8827  ((INSTANCE) == TIM5) || \
8828  ((INSTANCE) == TIM8))
8829 
8830 /************ TIM Instances : at least 4 capture/compare channels *************/
8831 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8832  ((INSTANCE) == TIM2) || \
8833  ((INSTANCE) == TIM3) || \
8834  ((INSTANCE) == TIM4) || \
8835  ((INSTANCE) == TIM5) || \
8836  ((INSTANCE) == TIM8))
8837 
8838 /******************** TIM Instances : Advanced-control timers *****************/
8839 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8840  ((INSTANCE) == TIM8))
8841 
8842 /******************* TIM Instances : Timer input XOR function *****************/
8843 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8844  ((INSTANCE) == TIM2) || \
8845  ((INSTANCE) == TIM3) || \
8846  ((INSTANCE) == TIM4) || \
8847  ((INSTANCE) == TIM5) || \
8848  ((INSTANCE) == TIM8))
8849 
8850 /****************** TIM Instances : DMA requests generation (UDE) *************/
8851 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8852  ((INSTANCE) == TIM2) || \
8853  ((INSTANCE) == TIM3) || \
8854  ((INSTANCE) == TIM4) || \
8855  ((INSTANCE) == TIM5) || \
8856  ((INSTANCE) == TIM6) || \
8857  ((INSTANCE) == TIM7) || \
8858  ((INSTANCE) == TIM8))
8859 
8860 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8861 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8862  ((INSTANCE) == TIM2) || \
8863  ((INSTANCE) == TIM3) || \
8864  ((INSTANCE) == TIM4) || \
8865  ((INSTANCE) == TIM5) || \
8866  ((INSTANCE) == TIM8))
8867 
8868 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8869 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8870  ((INSTANCE) == TIM2) || \
8871  ((INSTANCE) == TIM3) || \
8872  ((INSTANCE) == TIM4) || \
8873  ((INSTANCE) == TIM5) || \
8874  ((INSTANCE) == TIM8))
8875 
8876 /******************** TIM Instances : DMA burst feature ***********************/
8877 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8878  ((INSTANCE) == TIM2) || \
8879  ((INSTANCE) == TIM3) || \
8880  ((INSTANCE) == TIM4) || \
8881  ((INSTANCE) == TIM5) || \
8882  ((INSTANCE) == TIM8))
8883 
8884 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8885 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8886  ((INSTANCE) == TIM2) || \
8887  ((INSTANCE) == TIM3) || \
8888  ((INSTANCE) == TIM4) || \
8889  ((INSTANCE) == TIM5) || \
8890  ((INSTANCE) == TIM6) || \
8891  ((INSTANCE) == TIM7) || \
8892  ((INSTANCE) == TIM8) || \
8893  ((INSTANCE) == TIM9) || \
8894  ((INSTANCE) == TIM12))
8895 
8896 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8897 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8898  ((INSTANCE) == TIM2) || \
8899  ((INSTANCE) == TIM3) || \
8900  ((INSTANCE) == TIM4) || \
8901  ((INSTANCE) == TIM5) || \
8902  ((INSTANCE) == TIM8) || \
8903  ((INSTANCE) == TIM9) || \
8904  ((INSTANCE) == TIM12))
8905 
8906 /********************** TIM Instances : 32 bit Counter ************************/
8907 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
8908  ((INSTANCE) == TIM5))
8909 
8910 /***************** TIM Instances : external trigger input availabe ************/
8911 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8912  ((INSTANCE) == TIM2) || \
8913  ((INSTANCE) == TIM3) || \
8914  ((INSTANCE) == TIM4) || \
8915  ((INSTANCE) == TIM5) || \
8916  ((INSTANCE) == TIM8))
8917 
8918 /****************** TIM Instances : remapping capability **********************/
8919 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8920  ((INSTANCE) == TIM5) || \
8921  ((INSTANCE) == TIM11))
8922 
8923 /******************* TIM Instances : output(s) available **********************/
8924 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8925  ((((INSTANCE) == TIM1) && \
8926  (((CHANNEL) == TIM_CHANNEL_1) || \
8927  ((CHANNEL) == TIM_CHANNEL_2) || \
8928  ((CHANNEL) == TIM_CHANNEL_3) || \
8929  ((CHANNEL) == TIM_CHANNEL_4))) \
8930  || \
8931  (((INSTANCE) == TIM2) && \
8932  (((CHANNEL) == TIM_CHANNEL_1) || \
8933  ((CHANNEL) == TIM_CHANNEL_2) || \
8934  ((CHANNEL) == TIM_CHANNEL_3) || \
8935  ((CHANNEL) == TIM_CHANNEL_4))) \
8936  || \
8937  (((INSTANCE) == TIM3) && \
8938  (((CHANNEL) == TIM_CHANNEL_1) || \
8939  ((CHANNEL) == TIM_CHANNEL_2) || \
8940  ((CHANNEL) == TIM_CHANNEL_3) || \
8941  ((CHANNEL) == TIM_CHANNEL_4))) \
8942  || \
8943  (((INSTANCE) == TIM4) && \
8944  (((CHANNEL) == TIM_CHANNEL_1) || \
8945  ((CHANNEL) == TIM_CHANNEL_2) || \
8946  ((CHANNEL) == TIM_CHANNEL_3) || \
8947  ((CHANNEL) == TIM_CHANNEL_4))) \
8948  || \
8949  (((INSTANCE) == TIM5) && \
8950  (((CHANNEL) == TIM_CHANNEL_1) || \
8951  ((CHANNEL) == TIM_CHANNEL_2) || \
8952  ((CHANNEL) == TIM_CHANNEL_3) || \
8953  ((CHANNEL) == TIM_CHANNEL_4))) \
8954  || \
8955  (((INSTANCE) == TIM8) && \
8956  (((CHANNEL) == TIM_CHANNEL_1) || \
8957  ((CHANNEL) == TIM_CHANNEL_2) || \
8958  ((CHANNEL) == TIM_CHANNEL_3) || \
8959  ((CHANNEL) == TIM_CHANNEL_4))) \
8960  || \
8961  (((INSTANCE) == TIM9) && \
8962  (((CHANNEL) == TIM_CHANNEL_1) || \
8963  ((CHANNEL) == TIM_CHANNEL_2))) \
8964  || \
8965  (((INSTANCE) == TIM10) && \
8966  (((CHANNEL) == TIM_CHANNEL_1))) \
8967  || \
8968  (((INSTANCE) == TIM11) && \
8969  (((CHANNEL) == TIM_CHANNEL_1))) \
8970  || \
8971  (((INSTANCE) == TIM12) && \
8972  (((CHANNEL) == TIM_CHANNEL_1) || \
8973  ((CHANNEL) == TIM_CHANNEL_2))) \
8974  || \
8975  (((INSTANCE) == TIM13) && \
8976  (((CHANNEL) == TIM_CHANNEL_1))) \
8977  || \
8978  (((INSTANCE) == TIM14) && \
8979  (((CHANNEL) == TIM_CHANNEL_1))))
8980 
8981 /************ TIM Instances : complementary output(s) available ***************/
8982 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8983  ((((INSTANCE) == TIM1) && \
8984  (((CHANNEL) == TIM_CHANNEL_1) || \
8985  ((CHANNEL) == TIM_CHANNEL_2) || \
8986  ((CHANNEL) == TIM_CHANNEL_3))) \
8987  || \
8988  (((INSTANCE) == TIM8) && \
8989  (((CHANNEL) == TIM_CHANNEL_1) || \
8990  ((CHANNEL) == TIM_CHANNEL_2) || \
8991  ((CHANNEL) == TIM_CHANNEL_3))))
8992 
8993 /******************** USART Instances : Synchronous mode **********************/
8994 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8995  ((INSTANCE) == USART2) || \
8996  ((INSTANCE) == USART3) || \
8997  ((INSTANCE) == USART6))
8998 
8999 /******************** UART Instances : Asynchronous mode **********************/
9000 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9001  ((INSTANCE) == USART2) || \
9002  ((INSTANCE) == USART3) || \
9003  ((INSTANCE) == UART4) || \
9004  ((INSTANCE) == UART5) || \
9005  ((INSTANCE) == USART6) || \
9006  ((INSTANCE) == UART7) || \
9007  ((INSTANCE) == UART8))
9008 
9009 /****************** UART Instances : Hardware Flow control ********************/
9010 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9011  ((INSTANCE) == USART2) || \
9012  ((INSTANCE) == USART3) || \
9013  ((INSTANCE) == USART6))
9014 
9015 /********************* UART Instances : Smard card mode ***********************/
9016 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9017  ((INSTANCE) == USART2) || \
9018  ((INSTANCE) == USART3) || \
9019  ((INSTANCE) == USART6))
9020 
9021 /*********************** UART Instances : IRDA mode ***************************/
9022 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9023  ((INSTANCE) == USART2) || \
9024  ((INSTANCE) == USART3) || \
9025  ((INSTANCE) == UART4) || \
9026  ((INSTANCE) == UART5) || \
9027  ((INSTANCE) == USART6) || \
9028  ((INSTANCE) == UART7) || \
9029  ((INSTANCE) == UART8))
9030 
9031 /*********************** PCD Instances ****************************************/
9032 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
9033  ((INSTANCE) == USB_OTG_HS))
9034 
9035 /*********************** HCD Instances ****************************************/
9036 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
9037  ((INSTANCE) == USB_OTG_HS))
9038 
9039 /****************************** IWDG Instances ********************************/
9040 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
9041 
9042 /****************************** WWDG Instances ********************************/
9043 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
9044 
9045 /****************************** SDIO Instances ********************************/
9046 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
9047 
9048 /****************************** USB Exported Constants ************************/
9049 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
9050 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
9051 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
9052 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
9053 
9054 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
9055 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
9056 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
9057 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
9058 
9059 /******************************************************************************/
9060 /* For a painless codes migration between the STM32F4xx device product */
9061 /* lines, the aliases defined below are put in place to overcome the */
9062 /* differences in the interrupt handlers and IRQn definitions. */
9063 /* No need to update developed interrupt code when moving across */
9064 /* product lines within the same STM32F4 Family */
9065 /******************************************************************************/
9066 
9067 /* Aliases for __IRQn */
9068 #define FSMC_IRQn FMC_IRQn
9069 
9070 /* Aliases for __IRQHandler */
9071 #define FSMC_IRQHandler FMC_IRQHandler
9072 
9085 #ifdef __cplusplus
9086 }
9087 #endif /* __cplusplus */
9088 
9089 #endif /* __STM32F437xx_H */
9090 
9091 
9092 
9093 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
SAI1_IRQn
Definition: stm32f437xx.h:183
TAMP_STAMP_IRQn
Definition: stm32f437xx.h:98
TIM2_IRQn
Definition: stm32f437xx.h:124
UART4_IRQn
Definition: stm32f437xx.h:148
UART5_IRQn
Definition: stm32f437xx.h:149
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f437xx.h:122
EXTI2_IRQn
Definition: stm32f437xx.h:104
EXTI4_IRQn
Definition: stm32f437xx.h:106
USART1_IRQn
Definition: stm32f437xx.h:133
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
ETH_WKUP_IRQn
Definition: stm32f437xx.h:158
DMA2D_IRQn
Definition: stm32f437xx.h:184
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f437xx.h:141
TIM4_IRQn
Definition: stm32f437xx.h:126
RTC_Alarm_IRQn
Definition: stm32f437xx.h:137
CAN2_SCE_IRQn
Definition: stm32f437xx.h:162
CRYP_IRQn
Definition: stm32f437xx.h:175
PendSV_IRQn
Definition: stm32f437xx.h:93
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f437xx.h:99
CAN1_RX1_IRQn
Definition: stm32f437xx.h:117
TIM6_DAC_IRQn
Definition: stm32f437xx.h:150
CAN1_TX_IRQn
Definition: stm32f437xx.h:115
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f437xx.h:131
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f427xx.h:534
OTG_FS_WKUP_IRQn
Definition: stm32f437xx.h:138
DMA_TypeDef
Definition: stm32f401xc.h:243
ETH_IRQn
Definition: stm32f437xx.h:157
DMA1_Stream2_IRQn
Definition: stm32f437xx.h:109
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f437xx.h:132
FMC_Bank2_3_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32f427xx.h:543
__I
#define __I
Definition: core_cm0.h:210
DMA2_Stream5_IRQn
Definition: stm32f437xx.h:164
ADC_IRQn
Definition: stm32f437xx.h:114
CAN1_RX0_IRQn
Definition: stm32f437xx.h:116
RCC_IRQn
Definition: stm32f437xx.h:101
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32f415xx.h:768
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f437xx.h:92
DMA2_Stream3_IRQn
Definition: stm32f437xx.h:155
NonMaskableInt_IRQn
Definition: stm32f437xx.h:87
UART8_IRQn
Definition: stm32f437xx.h:179
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f437xx.h:84
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f437xx.h:140
DMA1_Stream1_IRQn
Definition: stm32f437xx.h:108
DMA2_Stream7_IRQn
Definition: stm32f437xx.h:166
DMA2_Stream6_IRQn
Definition: stm32f437xx.h:165
BusFault_IRQn
Definition: stm32f437xx.h:89
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
I2C3_ER_IRQn
Definition: stm32f437xx.h:169
CAN2_RX0_IRQn
Definition: stm32f437xx.h:160
USART6_IRQn
Definition: stm32f437xx.h:167
PVD_IRQn
Definition: stm32f437xx.h:97
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f427xx.h:391
FMC_Bank4_TypeDef
Flexible Memory Controller Bank4.
Definition: stm32f427xx.h:565
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f437xx.h:111
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f427xx.h:750
DMA1_Stream0_IRQn
Definition: stm32f437xx.h:107
OTG_HS_IRQn
Definition: stm32f437xx.h:173
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f437xx.h:180
TIM8_CC_IRQn
Definition: stm32f437xx.h:142
DMA1_Stream3_IRQn
Definition: stm32f437xx.h:110
FPU_IRQn
Definition: stm32f437xx.h:177
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:386
OTG_FS_IRQn
Definition: stm32f437xx.h:163
DMA2_Stream2_IRQn
Definition: stm32f437xx.h:154
OTG_HS_EP1_OUT_IRQn
Definition: stm32f437xx.h:170
OTG_HS_EP1_IN_IRQn
Definition: stm32f437xx.h:171
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f437xx.h:145
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f437xx.h:168
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f437xx.h:134
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f437xx.h:151
I2C2_EV_IRQn
Definition: stm32f437xx.h:129
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f437xx.h:125
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f437xx.h:103
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f437xx.h:91
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f437xx.h:123
TIM8_BRK_TIM12_IRQn
Definition: stm32f437xx.h:139
HASH_RNG_IRQn
Definition: stm32f437xx.h:176
FLASH_IRQn
Definition: stm32f437xx.h:100
DMA1_Stream5_IRQn
Definition: stm32f437xx.h:112
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f437xx.h:94
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f427xx.h:525
SPI6_IRQn
Definition: stm32f437xx.h:182
TIM1_UP_TIM10_IRQn
Definition: stm32f437xx.h:121
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f437xx.h:130
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:344
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f427xx.h:578
UsageFault_IRQn
Definition: stm32f437xx.h:90
FMC_IRQn
Definition: stm32f437xx.h:144
SPI3_IRQn
Definition: stm32f437xx.h:147
DMA2_Stream1_IRQn
Definition: stm32f437xx.h:153
EXTI9_5_IRQn
Definition: stm32f437xx.h:119
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f437xx.h:127
DMA1_Stream6_IRQn
Definition: stm32f437xx.h:113
OTG_HS_WKUP_IRQn
Definition: stm32f437xx.h:172
I2C1_ER_IRQn
Definition: stm32f437xx.h:128
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
HASH_TypeDef
HASH.
Definition: stm32f415xx.h:752
UART7_IRQn
Definition: stm32f437xx.h:178
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
SAI_Block_TypeDef
Definition: stm32f427xx.h:755
CAN2_RX1_IRQn
Definition: stm32f437xx.h:161
DMA2_Stream4_IRQn
Definition: stm32f437xx.h:156
WWDG_IRQn
Definition: stm32f437xx.h:96
CRYP_TypeDef
Crypto Processor.
Definition: stm32f415xx.h:708
DMA1_Stream7_IRQn
Definition: stm32f437xx.h:143
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
SPI5_IRQn
Definition: stm32f437xx.h:181
EXTI15_10_IRQn
Definition: stm32f437xx.h:136
CAN1_SCE_IRQn
Definition: stm32f437xx.h:118
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f437xx.h:102
DMA2_Stream0_IRQn
Definition: stm32f437xx.h:152
TIM1_BRK_TIM9_IRQn
Definition: stm32f437xx.h:120
CAN2_TX_IRQn
Definition: stm32f437xx.h:159
TIM5_IRQn
Definition: stm32f437xx.h:146
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f437xx.h:105
USART3_IRQn
Definition: stm32f437xx.h:135
DCMI_IRQn
Definition: stm32f437xx.h:174
MemoryManagement_IRQn
Definition: stm32f437xx.h:88