STM CMSIS
stm32f446xx.h
Go to the documentation of this file.
1 
52 #ifndef __STM32F446xx_H
53 #define __STM32F446xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
66 #define __CM4_REV 0x0001U
67 #define __MPU_PRESENT 1U
68 #define __NVIC_PRIO_BITS 4U
69 #define __Vendor_SysTickConfig 0U
70 #define __FPU_PRESENT 1U
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87  NonMaskableInt_IRQn = -14,
88  MemoryManagement_IRQn = -12,
89  BusFault_IRQn = -11,
90  UsageFault_IRQn = -10,
91  SVCall_IRQn = -5,
92  DebugMonitor_IRQn = -4,
93  PendSV_IRQn = -2,
94  SysTick_IRQn = -1,
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96  WWDG_IRQn = 0,
97  PVD_IRQn = 1,
98  TAMP_STAMP_IRQn = 2,
99  RTC_WKUP_IRQn = 3,
100  FLASH_IRQn = 4,
101  RCC_IRQn = 5,
102  EXTI0_IRQn = 6,
103  EXTI1_IRQn = 7,
104  EXTI2_IRQn = 8,
105  EXTI3_IRQn = 9,
106  EXTI4_IRQn = 10,
107  DMA1_Stream0_IRQn = 11,
108  DMA1_Stream1_IRQn = 12,
109  DMA1_Stream2_IRQn = 13,
110  DMA1_Stream3_IRQn = 14,
111  DMA1_Stream4_IRQn = 15,
112  DMA1_Stream5_IRQn = 16,
113  DMA1_Stream6_IRQn = 17,
114  ADC_IRQn = 18,
115  CAN1_TX_IRQn = 19,
116  CAN1_RX0_IRQn = 20,
117  CAN1_RX1_IRQn = 21,
118  CAN1_SCE_IRQn = 22,
119  EXTI9_5_IRQn = 23,
120  TIM1_BRK_TIM9_IRQn = 24,
121  TIM1_UP_TIM10_IRQn = 25,
122  TIM1_TRG_COM_TIM11_IRQn = 26,
123  TIM1_CC_IRQn = 27,
124  TIM2_IRQn = 28,
125  TIM3_IRQn = 29,
126  TIM4_IRQn = 30,
127  I2C1_EV_IRQn = 31,
128  I2C1_ER_IRQn = 32,
129  I2C2_EV_IRQn = 33,
130  I2C2_ER_IRQn = 34,
131  SPI1_IRQn = 35,
132  SPI2_IRQn = 36,
133  USART1_IRQn = 37,
134  USART2_IRQn = 38,
135  USART3_IRQn = 39,
136  EXTI15_10_IRQn = 40,
137  RTC_Alarm_IRQn = 41,
138  OTG_FS_WKUP_IRQn = 42,
139  TIM8_BRK_TIM12_IRQn = 43,
140  TIM8_UP_TIM13_IRQn = 44,
141  TIM8_TRG_COM_TIM14_IRQn = 45,
142  TIM8_CC_IRQn = 46,
143  DMA1_Stream7_IRQn = 47,
144  FMC_IRQn = 48,
145  SDIO_IRQn = 49,
146  TIM5_IRQn = 50,
147  SPI3_IRQn = 51,
148  UART4_IRQn = 52,
149  UART5_IRQn = 53,
150  TIM6_DAC_IRQn = 54,
151  TIM7_IRQn = 55,
152  DMA2_Stream0_IRQn = 56,
153  DMA2_Stream1_IRQn = 57,
154  DMA2_Stream2_IRQn = 58,
155  DMA2_Stream3_IRQn = 59,
156  DMA2_Stream4_IRQn = 60,
157  CAN2_TX_IRQn = 63,
158  CAN2_RX0_IRQn = 64,
159  CAN2_RX1_IRQn = 65,
160  CAN2_SCE_IRQn = 66,
161  OTG_FS_IRQn = 67,
162  DMA2_Stream5_IRQn = 68,
163  DMA2_Stream6_IRQn = 69,
164  DMA2_Stream7_IRQn = 70,
165  USART6_IRQn = 71,
166  I2C3_EV_IRQn = 72,
167  I2C3_ER_IRQn = 73,
168  OTG_HS_EP1_OUT_IRQn = 74,
169  OTG_HS_EP1_IN_IRQn = 75,
170  OTG_HS_WKUP_IRQn = 76,
171  OTG_HS_IRQn = 77,
172  DCMI_IRQn = 78,
173  FPU_IRQn = 81,
174  SPI4_IRQn = 84,
175  SAI1_IRQn = 87,
176  SAI2_IRQn = 91,
177  QUADSPI_IRQn = 92,
178  CEC_IRQn = 93,
179  SPDIF_RX_IRQn = 94,
180  FMPI2C1_EV_IRQn = 95,
181  FMPI2C1_ER_IRQn = 96
182 } IRQn_Type;
183 
188 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
189 #include "system_stm32f4xx.h"
190 #include <stdint.h>
191 
200 typedef struct
201 {
202  __IO uint32_t SR;
203  __IO uint32_t CR1;
204  __IO uint32_t CR2;
205  __IO uint32_t SMPR1;
206  __IO uint32_t SMPR2;
207  __IO uint32_t JOFR1;
208  __IO uint32_t JOFR2;
209  __IO uint32_t JOFR3;
210  __IO uint32_t JOFR4;
211  __IO uint32_t HTR;
212  __IO uint32_t LTR;
213  __IO uint32_t SQR1;
214  __IO uint32_t SQR2;
215  __IO uint32_t SQR3;
216  __IO uint32_t JSQR;
217  __IO uint32_t JDR1;
218  __IO uint32_t JDR2;
219  __IO uint32_t JDR3;
220  __IO uint32_t JDR4;
221  __IO uint32_t DR;
222 } ADC_TypeDef;
223 
224 typedef struct
225 {
226  __IO uint32_t CSR;
227  __IO uint32_t CCR;
228  __IO uint32_t CDR;
230 } ADC_Common_TypeDef;
231 
232 
237 typedef struct
238 {
239  __IO uint32_t TIR;
240  __IO uint32_t TDTR;
241  __IO uint32_t TDLR;
242  __IO uint32_t TDHR;
243 } CAN_TxMailBox_TypeDef;
244 
249 typedef struct
250 {
251  __IO uint32_t RIR;
252  __IO uint32_t RDTR;
253  __IO uint32_t RDLR;
254  __IO uint32_t RDHR;
255 } CAN_FIFOMailBox_TypeDef;
256 
261 typedef struct
262 {
263  __IO uint32_t FR1;
264  __IO uint32_t FR2;
265 } CAN_FilterRegister_TypeDef;
266 
271 typedef struct
272 {
273  __IO uint32_t MCR;
274  __IO uint32_t MSR;
275  __IO uint32_t TSR;
276  __IO uint32_t RF0R;
277  __IO uint32_t RF1R;
278  __IO uint32_t IER;
279  __IO uint32_t ESR;
280  __IO uint32_t BTR;
281  uint32_t RESERVED0[88];
282  CAN_TxMailBox_TypeDef sTxMailBox[3];
283  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
284  uint32_t RESERVED1[12];
285  __IO uint32_t FMR;
286  __IO uint32_t FM1R;
287  uint32_t RESERVED2;
288  __IO uint32_t FS1R;
289  uint32_t RESERVED3;
290  __IO uint32_t FFA1R;
291  uint32_t RESERVED4;
292  __IO uint32_t FA1R;
293  uint32_t RESERVED5[8];
294  CAN_FilterRegister_TypeDef sFilterRegister[28];
295 } CAN_TypeDef;
296 
301 typedef struct
302 {
303  __IO uint32_t CR;
304  __IO uint32_t CFGR;
305  __IO uint32_t TXDR;
306  __IO uint32_t RXDR;
307  __IO uint32_t ISR;
308  __IO uint32_t IER;
309 }CEC_TypeDef;
310 
315 typedef struct
316 {
317  __IO uint32_t DR;
318  __IO uint8_t IDR;
319  uint8_t RESERVED0;
320  uint16_t RESERVED1;
321  __IO uint32_t CR;
322 } CRC_TypeDef;
323 
328 typedef struct
329 {
330  __IO uint32_t CR;
331  __IO uint32_t SWTRIGR;
332  __IO uint32_t DHR12R1;
333  __IO uint32_t DHR12L1;
334  __IO uint32_t DHR8R1;
335  __IO uint32_t DHR12R2;
336  __IO uint32_t DHR12L2;
337  __IO uint32_t DHR8R2;
338  __IO uint32_t DHR12RD;
339  __IO uint32_t DHR12LD;
340  __IO uint32_t DHR8RD;
341  __IO uint32_t DOR1;
342  __IO uint32_t DOR2;
343  __IO uint32_t SR;
344 } DAC_TypeDef;
345 
350 typedef struct
351 {
352  __IO uint32_t IDCODE;
353  __IO uint32_t CR;
354  __IO uint32_t APB1FZ;
355  __IO uint32_t APB2FZ;
356 }DBGMCU_TypeDef;
357 
362 typedef struct
363 {
364  __IO uint32_t CR;
365  __IO uint32_t SR;
366  __IO uint32_t RISR;
367  __IO uint32_t IER;
368  __IO uint32_t MISR;
369  __IO uint32_t ICR;
370  __IO uint32_t ESCR;
371  __IO uint32_t ESUR;
372  __IO uint32_t CWSTRTR;
373  __IO uint32_t CWSIZER;
374  __IO uint32_t DR;
375 } DCMI_TypeDef;
376 
381 typedef struct
382 {
383  __IO uint32_t CR;
384  __IO uint32_t NDTR;
385  __IO uint32_t PAR;
386  __IO uint32_t M0AR;
387  __IO uint32_t M1AR;
388  __IO uint32_t FCR;
389 } DMA_Stream_TypeDef;
390 
391 typedef struct
392 {
393  __IO uint32_t LISR;
394  __IO uint32_t HISR;
395  __IO uint32_t LIFCR;
396  __IO uint32_t HIFCR;
397 } DMA_TypeDef;
398 
399 
404 typedef struct
405 {
406  __IO uint32_t IMR;
407  __IO uint32_t EMR;
408  __IO uint32_t RTSR;
409  __IO uint32_t FTSR;
410  __IO uint32_t SWIER;
411  __IO uint32_t PR;
412 } EXTI_TypeDef;
413 
418 typedef struct
419 {
420  __IO uint32_t ACR;
421  __IO uint32_t KEYR;
422  __IO uint32_t OPTKEYR;
423  __IO uint32_t SR;
424  __IO uint32_t CR;
425  __IO uint32_t OPTCR;
426  __IO uint32_t OPTCR1;
427 } FLASH_TypeDef;
428 
433 typedef struct
434 {
435  __IO uint32_t BTCR[8];
436 } FMC_Bank1_TypeDef;
437 
442 typedef struct
443 {
444  __IO uint32_t BWTR[7];
445 } FMC_Bank1E_TypeDef;
446 
451 typedef struct
452 {
453  __IO uint32_t PCR;
454  __IO uint32_t SR;
455  __IO uint32_t PMEM;
456  __IO uint32_t PATT;
457  uint32_t RESERVED;
458  __IO uint32_t ECCR;
459 } FMC_Bank3_TypeDef;
460 
465 typedef struct
466 {
467  __IO uint32_t SDCR[2];
468  __IO uint32_t SDTR[2];
469  __IO uint32_t SDCMR;
470  __IO uint32_t SDRTR;
471  __IO uint32_t SDSR;
472 } FMC_Bank5_6_TypeDef;
473 
478 typedef struct
479 {
480  __IO uint32_t MODER;
481  __IO uint32_t OTYPER;
482  __IO uint32_t OSPEEDR;
483  __IO uint32_t PUPDR;
484  __IO uint32_t IDR;
485  __IO uint32_t ODR;
486  __IO uint32_t BSRR;
487  __IO uint32_t LCKR;
488  __IO uint32_t AFR[2];
489 } GPIO_TypeDef;
490 
495 typedef struct
496 {
497  __IO uint32_t MEMRMP;
498  __IO uint32_t PMC;
499  __IO uint32_t EXTICR[4];
500  uint32_t RESERVED[2];
501  __IO uint32_t CMPCR;
502  uint32_t RESERVED1[2];
503  __IO uint32_t CFGR;
504 } SYSCFG_TypeDef;
505 
510 typedef struct
511 {
512  __IO uint32_t CR1;
513  __IO uint32_t CR2;
514  __IO uint32_t OAR1;
515  __IO uint32_t OAR2;
516  __IO uint32_t DR;
517  __IO uint32_t SR1;
518  __IO uint32_t SR2;
519  __IO uint32_t CCR;
520  __IO uint32_t TRISE;
521  __IO uint32_t FLTR;
522 } I2C_TypeDef;
523 
528 typedef struct
529 {
530  __IO uint32_t CR1;
531  __IO uint32_t CR2;
532  __IO uint32_t OAR1;
533  __IO uint32_t OAR2;
534  __IO uint32_t TIMINGR;
535  __IO uint32_t TIMEOUTR;
536  __IO uint32_t ISR;
537  __IO uint32_t ICR;
538  __IO uint32_t PECR;
539  __IO uint32_t RXDR;
540  __IO uint32_t TXDR;
541 } FMPI2C_TypeDef;
542 
547 typedef struct
548 {
549  __IO uint32_t KR;
550  __IO uint32_t PR;
551  __IO uint32_t RLR;
552  __IO uint32_t SR;
553 } IWDG_TypeDef;
554 
559 typedef struct
560 {
561  __IO uint32_t CR;
562  __IO uint32_t CSR;
563 } PWR_TypeDef;
564 
569 typedef struct
570 {
571  __IO uint32_t CR;
572  __IO uint32_t PLLCFGR;
573  __IO uint32_t CFGR;
574  __IO uint32_t CIR;
575  __IO uint32_t AHB1RSTR;
576  __IO uint32_t AHB2RSTR;
577  __IO uint32_t AHB3RSTR;
578  uint32_t RESERVED0;
579  __IO uint32_t APB1RSTR;
580  __IO uint32_t APB2RSTR;
581  uint32_t RESERVED1[2];
582  __IO uint32_t AHB1ENR;
583  __IO uint32_t AHB2ENR;
584  __IO uint32_t AHB3ENR;
585  uint32_t RESERVED2;
586  __IO uint32_t APB1ENR;
587  __IO uint32_t APB2ENR;
588  uint32_t RESERVED3[2];
589  __IO uint32_t AHB1LPENR;
590  __IO uint32_t AHB2LPENR;
591  __IO uint32_t AHB3LPENR;
592  uint32_t RESERVED4;
593  __IO uint32_t APB1LPENR;
594  __IO uint32_t APB2LPENR;
595  uint32_t RESERVED5[2];
596  __IO uint32_t BDCR;
597  __IO uint32_t CSR;
598  uint32_t RESERVED6[2];
599  __IO uint32_t SSCGR;
600  __IO uint32_t PLLI2SCFGR;
601  __IO uint32_t PLLSAICFGR;
602  __IO uint32_t DCKCFGR;
603  __IO uint32_t CKGATENR;
604  __IO uint32_t DCKCFGR2;
605 } RCC_TypeDef;
606 
611 typedef struct
612 {
613  __IO uint32_t TR;
614  __IO uint32_t DR;
615  __IO uint32_t CR;
616  __IO uint32_t ISR;
617  __IO uint32_t PRER;
618  __IO uint32_t WUTR;
619  __IO uint32_t CALIBR;
620  __IO uint32_t ALRMAR;
621  __IO uint32_t ALRMBR;
622  __IO uint32_t WPR;
623  __IO uint32_t SSR;
624  __IO uint32_t SHIFTR;
625  __IO uint32_t TSTR;
626  __IO uint32_t TSDR;
627  __IO uint32_t TSSSR;
628  __IO uint32_t CALR;
629  __IO uint32_t TAFCR;
630  __IO uint32_t ALRMASSR;
631  __IO uint32_t ALRMBSSR;
632  uint32_t RESERVED7;
633  __IO uint32_t BKP0R;
634  __IO uint32_t BKP1R;
635  __IO uint32_t BKP2R;
636  __IO uint32_t BKP3R;
637  __IO uint32_t BKP4R;
638  __IO uint32_t BKP5R;
639  __IO uint32_t BKP6R;
640  __IO uint32_t BKP7R;
641  __IO uint32_t BKP8R;
642  __IO uint32_t BKP9R;
643  __IO uint32_t BKP10R;
644  __IO uint32_t BKP11R;
645  __IO uint32_t BKP12R;
646  __IO uint32_t BKP13R;
647  __IO uint32_t BKP14R;
648  __IO uint32_t BKP15R;
649  __IO uint32_t BKP16R;
650  __IO uint32_t BKP17R;
651  __IO uint32_t BKP18R;
652  __IO uint32_t BKP19R;
653 } RTC_TypeDef;
654 
659 typedef struct
660 {
661  __IO uint32_t GCR;
662 } SAI_TypeDef;
663 
664 typedef struct
665 {
666  __IO uint32_t CR1;
667  __IO uint32_t CR2;
668  __IO uint32_t FRCR;
669  __IO uint32_t SLOTR;
670  __IO uint32_t IMR;
671  __IO uint32_t SR;
672  __IO uint32_t CLRFR;
673  __IO uint32_t DR;
674 } SAI_Block_TypeDef;
675 
680 typedef struct
681 {
682  __IO uint32_t POWER;
683  __IO uint32_t CLKCR;
684  __IO uint32_t ARG;
685  __IO uint32_t CMD;
686  __I uint32_t RESPCMD;
687  __I uint32_t RESP1;
688  __I uint32_t RESP2;
689  __I uint32_t RESP3;
690  __I uint32_t RESP4;
691  __IO uint32_t DTIMER;
692  __IO uint32_t DLEN;
693  __IO uint32_t DCTRL;
694  __I uint32_t DCOUNT;
695  __I uint32_t STA;
696  __IO uint32_t ICR;
697  __IO uint32_t MASK;
698  uint32_t RESERVED0[2];
699  __I uint32_t FIFOCNT;
700  uint32_t RESERVED1[13];
701  __IO uint32_t FIFO;
702 } SDIO_TypeDef;
703 
708 typedef struct
709 {
710  __IO uint32_t CR1;
711  __IO uint32_t CR2;
712  __IO uint32_t SR;
713  __IO uint32_t DR;
714  __IO uint32_t CRCPR;
715  __IO uint32_t RXCRCR;
716  __IO uint32_t TXCRCR;
717  __IO uint32_t I2SCFGR;
718  __IO uint32_t I2SPR;
719 } SPI_TypeDef;
720 
725 typedef struct
726 {
727  __IO uint32_t CR;
728  __IO uint32_t DCR;
729  __IO uint32_t SR;
730  __IO uint32_t FCR;
731  __IO uint32_t DLR;
732  __IO uint32_t CCR;
733  __IO uint32_t AR;
734  __IO uint32_t ABR;
735  __IO uint32_t DR;
736  __IO uint32_t PSMKR;
737  __IO uint32_t PSMAR;
738  __IO uint32_t PIR;
739  __IO uint32_t LPTR;
740 } QUADSPI_TypeDef;
741 
746 typedef struct
747 {
748  __IO uint32_t CR;
749  __IO uint16_t IMR;
750  uint16_t RESERVED0;
751  __IO uint32_t SR;
752  __IO uint16_t IFCR;
753  uint16_t RESERVED1;
754  __IO uint32_t DR;
755  __IO uint32_t CSR;
756  __IO uint32_t DIR;
757  uint16_t RESERVED2;
758 } SPDIFRX_TypeDef;
759 
764 typedef struct
765 {
766  __IO uint32_t CR1;
767  __IO uint32_t CR2;
768  __IO uint32_t SMCR;
769  __IO uint32_t DIER;
770  __IO uint32_t SR;
771  __IO uint32_t EGR;
772  __IO uint32_t CCMR1;
773  __IO uint32_t CCMR2;
774  __IO uint32_t CCER;
775  __IO uint32_t CNT;
776  __IO uint32_t PSC;
777  __IO uint32_t ARR;
778  __IO uint32_t RCR;
779  __IO uint32_t CCR1;
780  __IO uint32_t CCR2;
781  __IO uint32_t CCR3;
782  __IO uint32_t CCR4;
783  __IO uint32_t BDTR;
784  __IO uint32_t DCR;
785  __IO uint32_t DMAR;
786  __IO uint32_t OR;
787 } TIM_TypeDef;
788 
793 typedef struct
794 {
795  __IO uint32_t SR;
796  __IO uint32_t DR;
797  __IO uint32_t BRR;
798  __IO uint32_t CR1;
799  __IO uint32_t CR2;
800  __IO uint32_t CR3;
801  __IO uint32_t GTPR;
802 } USART_TypeDef;
803 
808 typedef struct
809 {
810  __IO uint32_t CR;
811  __IO uint32_t CFR;
812  __IO uint32_t SR;
813 } WWDG_TypeDef;
814 
818 typedef struct
819 {
820  __IO uint32_t GOTGCTL;
821  __IO uint32_t GOTGINT;
822  __IO uint32_t GAHBCFG;
823  __IO uint32_t GUSBCFG;
824  __IO uint32_t GRSTCTL;
825  __IO uint32_t GINTSTS;
826  __IO uint32_t GINTMSK;
827  __IO uint32_t GRXSTSR;
828  __IO uint32_t GRXSTSP;
829  __IO uint32_t GRXFSIZ;
830  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
831  __IO uint32_t HNPTXSTS;
832  uint32_t Reserved30[2];
833  __IO uint32_t GCCFG;
834  __IO uint32_t CID;
835  uint32_t Reserved5[3];
836  __IO uint32_t GHWCFG3;
837  uint32_t Reserved6;
838  __IO uint32_t GLPMCFG;
839  uint32_t Reserved;
840  __IO uint32_t GDFIFOCFG;
841  uint32_t Reserved43[40];
842  __IO uint32_t HPTXFSIZ;
843  __IO uint32_t DIEPTXF[0x0F];
844 } USB_OTG_GlobalTypeDef;
845 
849 typedef struct
850 {
851  __IO uint32_t DCFG;
852  __IO uint32_t DCTL;
853  __IO uint32_t DSTS;
854  uint32_t Reserved0C;
855  __IO uint32_t DIEPMSK;
856  __IO uint32_t DOEPMSK;
857  __IO uint32_t DAINT;
858  __IO uint32_t DAINTMSK;
859  uint32_t Reserved20;
860  uint32_t Reserved9;
861  __IO uint32_t DVBUSDIS;
862  __IO uint32_t DVBUSPULSE;
863  __IO uint32_t DTHRCTL;
864  __IO uint32_t DIEPEMPMSK;
865  __IO uint32_t DEACHINT;
866  __IO uint32_t DEACHMSK;
867  uint32_t Reserved40;
868  __IO uint32_t DINEP1MSK;
869  uint32_t Reserved44[15];
870  __IO uint32_t DOUTEP1MSK;
871 } USB_OTG_DeviceTypeDef;
872 
876 typedef struct
877 {
878  __IO uint32_t DIEPCTL;
879  uint32_t Reserved04;
880  __IO uint32_t DIEPINT;
881  uint32_t Reserved0C;
882  __IO uint32_t DIEPTSIZ;
883  __IO uint32_t DIEPDMA;
884  __IO uint32_t DTXFSTS;
885  uint32_t Reserved18;
886 } USB_OTG_INEndpointTypeDef;
887 
891 typedef struct
892 {
893  __IO uint32_t DOEPCTL;
894  uint32_t Reserved04;
895  __IO uint32_t DOEPINT;
896  uint32_t Reserved0C;
897  __IO uint32_t DOEPTSIZ;
898  __IO uint32_t DOEPDMA;
899  uint32_t Reserved18[2];
900 } USB_OTG_OUTEndpointTypeDef;
901 
905 typedef struct
906 {
907  __IO uint32_t HCFG;
908  __IO uint32_t HFIR;
909  __IO uint32_t HFNUM;
910  uint32_t Reserved40C;
911  __IO uint32_t HPTXSTS;
912  __IO uint32_t HAINT;
913  __IO uint32_t HAINTMSK;
914 } USB_OTG_HostTypeDef;
915 
919 typedef struct
920 {
921  __IO uint32_t HCCHAR;
922  __IO uint32_t HCSPLT;
923  __IO uint32_t HCINT;
924  __IO uint32_t HCINTMSK;
925  __IO uint32_t HCTSIZ;
926  __IO uint32_t HCDMA;
927  uint32_t Reserved[2];
928 } USB_OTG_HostChannelTypeDef;
929 
937 #define FLASH_BASE 0x08000000U
938 #define SRAM1_BASE 0x20000000U
939 #define SRAM2_BASE 0x2001C000U
940 #define PERIPH_BASE 0x40000000U
941 #define BKPSRAM_BASE 0x40024000U
942 #define FMC_R_BASE 0xA0000000U
943 #define QSPI_R_BASE 0xA0001000U
945 #define SRAM1_BB_BASE 0x22000000U
946 #define SRAM2_BB_BASE 0x22380000U
947 #define PERIPH_BB_BASE 0x42000000U
948 #define BKPSRAM_BB_BASE 0x42480000U
949 #define FLASH_END 0x0807FFFFU
951 /* Legacy defines */
952 #define SRAM_BASE SRAM1_BASE
953 #define SRAM_BB_BASE SRAM1_BB_BASE
954 
955 
957 #define APB1PERIPH_BASE PERIPH_BASE
958 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
959 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
960 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
961 
963 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
964 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
965 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
966 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
967 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
968 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
969 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
970 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
971 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
972 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
973 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
974 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
975 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
976 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
977 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
978 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
979 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
980 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
981 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
982 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
983 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
984 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
985 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
986 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
987 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
988 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
989 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
990 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
991 
993 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
994 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
995 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
996 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
997 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
998 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
999 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1000 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1001 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1002 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1003 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1004 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1005 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1006 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1007 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1008 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1009 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1010 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1011 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1012 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1013 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1014 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1015 
1017 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1018 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1019 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1020 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1021 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1022 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1023 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1024 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1025 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1026 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1027 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1028 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1029 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1030 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1031 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1032 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1033 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1034 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1035 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1036 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1037 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1038 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1039 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1040 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1041 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1042 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1043 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1044 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1045 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1046 
1048 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1049 
1051 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1052 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1053 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1054 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1055 
1057 #define DBGMCU_BASE 0xE0042000U
1058 
1060 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1061 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1062 
1063 #define USB_OTG_GLOBAL_BASE 0x000U
1064 #define USB_OTG_DEVICE_BASE 0x800U
1065 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1066 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1067 #define USB_OTG_EP_REG_SIZE 0x20U
1068 #define USB_OTG_HOST_BASE 0x400U
1069 #define USB_OTG_HOST_PORT_BASE 0x440U
1070 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1071 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1072 #define USB_OTG_PCGCCTL_BASE 0xE00U
1073 #define USB_OTG_FIFO_BASE 0x1000U
1074 #define USB_OTG_FIFO_SIZE 0x1000U
1075 
1083 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1084 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1085 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1086 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1087 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1088 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1089 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1090 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1091 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1092 #define RTC ((RTC_TypeDef *) RTC_BASE)
1093 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1094 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1095 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1096 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1097 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1098 #define USART2 ((USART_TypeDef *) USART2_BASE)
1099 #define USART3 ((USART_TypeDef *) USART3_BASE)
1100 #define UART4 ((USART_TypeDef *) UART4_BASE)
1101 #define UART5 ((USART_TypeDef *) UART5_BASE)
1102 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1103 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1104 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1105 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1106 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1107 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1108 #define CEC ((CEC_TypeDef *) CEC_BASE)
1109 #define PWR ((PWR_TypeDef *) PWR_BASE)
1110 #define DAC ((DAC_TypeDef *) DAC_BASE)
1111 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1112 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1113 #define USART1 ((USART_TypeDef *) USART1_BASE)
1114 #define USART6 ((USART_TypeDef *) USART6_BASE)
1115 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1116 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1117 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1118 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1119 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1120 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1121 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1122 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1123 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1124 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1125 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1126 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1127 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1128 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1129 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1130 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1131 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1132 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1133 
1134 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1135 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1136 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1137 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1138 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1139 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1140 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1141 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1142 #define CRC ((CRC_TypeDef *) CRC_BASE)
1143 #define RCC ((RCC_TypeDef *) RCC_BASE)
1144 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1145 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1146 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1147 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1148 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1149 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1150 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1151 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1152 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1153 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1154 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1155 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1156 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1157 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1158 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1159 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1160 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1161 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1162 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1163 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1164 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1165 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1166 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1167 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1168 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1169 
1170 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1171 
1172 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1173 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1174 
1187 /******************************************************************************/
1188 /* Peripheral Registers_Bits_Definition */
1189 /******************************************************************************/
1190 
1191 /******************************************************************************/
1192 /* */
1193 /* Analog to Digital Converter */
1194 /* */
1195 /******************************************************************************/
1196 /******************** Bit definition for ADC_SR register ********************/
1197 #define ADC_SR_AWD 0x00000001U
1198 #define ADC_SR_EOC 0x00000002U
1199 #define ADC_SR_JEOC 0x00000004U
1200 #define ADC_SR_JSTRT 0x00000008U
1201 #define ADC_SR_STRT 0x00000010U
1202 #define ADC_SR_OVR 0x00000020U
1204 /******************* Bit definition for ADC_CR1 register ********************/
1205 #define ADC_CR1_AWDCH 0x0000001FU
1206 #define ADC_CR1_AWDCH_0 0x00000001U
1207 #define ADC_CR1_AWDCH_1 0x00000002U
1208 #define ADC_CR1_AWDCH_2 0x00000004U
1209 #define ADC_CR1_AWDCH_3 0x00000008U
1210 #define ADC_CR1_AWDCH_4 0x00000010U
1211 #define ADC_CR1_EOCIE 0x00000020U
1212 #define ADC_CR1_AWDIE 0x00000040U
1213 #define ADC_CR1_JEOCIE 0x00000080U
1214 #define ADC_CR1_SCAN 0x00000100U
1215 #define ADC_CR1_AWDSGL 0x00000200U
1216 #define ADC_CR1_JAUTO 0x00000400U
1217 #define ADC_CR1_DISCEN 0x00000800U
1218 #define ADC_CR1_JDISCEN 0x00001000U
1219 #define ADC_CR1_DISCNUM 0x0000E000U
1220 #define ADC_CR1_DISCNUM_0 0x00002000U
1221 #define ADC_CR1_DISCNUM_1 0x00004000U
1222 #define ADC_CR1_DISCNUM_2 0x00008000U
1223 #define ADC_CR1_JAWDEN 0x00400000U
1224 #define ADC_CR1_AWDEN 0x00800000U
1225 #define ADC_CR1_RES 0x03000000U
1226 #define ADC_CR1_RES_0 0x01000000U
1227 #define ADC_CR1_RES_1 0x02000000U
1228 #define ADC_CR1_OVRIE 0x04000000U
1230 /******************* Bit definition for ADC_CR2 register ********************/
1231 #define ADC_CR2_ADON 0x00000001U
1232 #define ADC_CR2_CONT 0x00000002U
1233 #define ADC_CR2_DMA 0x00000100U
1234 #define ADC_CR2_DDS 0x00000200U
1235 #define ADC_CR2_EOCS 0x00000400U
1236 #define ADC_CR2_ALIGN 0x00000800U
1237 #define ADC_CR2_JEXTSEL 0x000F0000U
1238 #define ADC_CR2_JEXTSEL_0 0x00010000U
1239 #define ADC_CR2_JEXTSEL_1 0x00020000U
1240 #define ADC_CR2_JEXTSEL_2 0x00040000U
1241 #define ADC_CR2_JEXTSEL_3 0x00080000U
1242 #define ADC_CR2_JEXTEN 0x00300000U
1243 #define ADC_CR2_JEXTEN_0 0x00100000U
1244 #define ADC_CR2_JEXTEN_1 0x00200000U
1245 #define ADC_CR2_JSWSTART 0x00400000U
1246 #define ADC_CR2_EXTSEL 0x0F000000U
1247 #define ADC_CR2_EXTSEL_0 0x01000000U
1248 #define ADC_CR2_EXTSEL_1 0x02000000U
1249 #define ADC_CR2_EXTSEL_2 0x04000000U
1250 #define ADC_CR2_EXTSEL_3 0x08000000U
1251 #define ADC_CR2_EXTEN 0x30000000U
1252 #define ADC_CR2_EXTEN_0 0x10000000U
1253 #define ADC_CR2_EXTEN_1 0x20000000U
1254 #define ADC_CR2_SWSTART 0x40000000U
1256 /****************** Bit definition for ADC_SMPR1 register *******************/
1257 #define ADC_SMPR1_SMP10 0x00000007U
1258 #define ADC_SMPR1_SMP10_0 0x00000001U
1259 #define ADC_SMPR1_SMP10_1 0x00000002U
1260 #define ADC_SMPR1_SMP10_2 0x00000004U
1261 #define ADC_SMPR1_SMP11 0x00000038U
1262 #define ADC_SMPR1_SMP11_0 0x00000008U
1263 #define ADC_SMPR1_SMP11_1 0x00000010U
1264 #define ADC_SMPR1_SMP11_2 0x00000020U
1265 #define ADC_SMPR1_SMP12 0x000001C0U
1266 #define ADC_SMPR1_SMP12_0 0x00000040U
1267 #define ADC_SMPR1_SMP12_1 0x00000080U
1268 #define ADC_SMPR1_SMP12_2 0x00000100U
1269 #define ADC_SMPR1_SMP13 0x00000E00U
1270 #define ADC_SMPR1_SMP13_0 0x00000200U
1271 #define ADC_SMPR1_SMP13_1 0x00000400U
1272 #define ADC_SMPR1_SMP13_2 0x00000800U
1273 #define ADC_SMPR1_SMP14 0x00007000U
1274 #define ADC_SMPR1_SMP14_0 0x00001000U
1275 #define ADC_SMPR1_SMP14_1 0x00002000U
1276 #define ADC_SMPR1_SMP14_2 0x00004000U
1277 #define ADC_SMPR1_SMP15 0x00038000U
1278 #define ADC_SMPR1_SMP15_0 0x00008000U
1279 #define ADC_SMPR1_SMP15_1 0x00010000U
1280 #define ADC_SMPR1_SMP15_2 0x00020000U
1281 #define ADC_SMPR1_SMP16 0x001C0000U
1282 #define ADC_SMPR1_SMP16_0 0x00040000U
1283 #define ADC_SMPR1_SMP16_1 0x00080000U
1284 #define ADC_SMPR1_SMP16_2 0x00100000U
1285 #define ADC_SMPR1_SMP17 0x00E00000U
1286 #define ADC_SMPR1_SMP17_0 0x00200000U
1287 #define ADC_SMPR1_SMP17_1 0x00400000U
1288 #define ADC_SMPR1_SMP17_2 0x00800000U
1289 #define ADC_SMPR1_SMP18 0x07000000U
1290 #define ADC_SMPR1_SMP18_0 0x01000000U
1291 #define ADC_SMPR1_SMP18_1 0x02000000U
1292 #define ADC_SMPR1_SMP18_2 0x04000000U
1294 /****************** Bit definition for ADC_SMPR2 register *******************/
1295 #define ADC_SMPR2_SMP0 0x00000007U
1296 #define ADC_SMPR2_SMP0_0 0x00000001U
1297 #define ADC_SMPR2_SMP0_1 0x00000002U
1298 #define ADC_SMPR2_SMP0_2 0x00000004U
1299 #define ADC_SMPR2_SMP1 0x00000038U
1300 #define ADC_SMPR2_SMP1_0 0x00000008U
1301 #define ADC_SMPR2_SMP1_1 0x00000010U
1302 #define ADC_SMPR2_SMP1_2 0x00000020U
1303 #define ADC_SMPR2_SMP2 0x000001C0U
1304 #define ADC_SMPR2_SMP2_0 0x00000040U
1305 #define ADC_SMPR2_SMP2_1 0x00000080U
1306 #define ADC_SMPR2_SMP2_2 0x00000100U
1307 #define ADC_SMPR2_SMP3 0x00000E00U
1308 #define ADC_SMPR2_SMP3_0 0x00000200U
1309 #define ADC_SMPR2_SMP3_1 0x00000400U
1310 #define ADC_SMPR2_SMP3_2 0x00000800U
1311 #define ADC_SMPR2_SMP4 0x00007000U
1312 #define ADC_SMPR2_SMP4_0 0x00001000U
1313 #define ADC_SMPR2_SMP4_1 0x00002000U
1314 #define ADC_SMPR2_SMP4_2 0x00004000U
1315 #define ADC_SMPR2_SMP5 0x00038000U
1316 #define ADC_SMPR2_SMP5_0 0x00008000U
1317 #define ADC_SMPR2_SMP5_1 0x00010000U
1318 #define ADC_SMPR2_SMP5_2 0x00020000U
1319 #define ADC_SMPR2_SMP6 0x001C0000U
1320 #define ADC_SMPR2_SMP6_0 0x00040000U
1321 #define ADC_SMPR2_SMP6_1 0x00080000U
1322 #define ADC_SMPR2_SMP6_2 0x00100000U
1323 #define ADC_SMPR2_SMP7 0x00E00000U
1324 #define ADC_SMPR2_SMP7_0 0x00200000U
1325 #define ADC_SMPR2_SMP7_1 0x00400000U
1326 #define ADC_SMPR2_SMP7_2 0x00800000U
1327 #define ADC_SMPR2_SMP8 0x07000000U
1328 #define ADC_SMPR2_SMP8_0 0x01000000U
1329 #define ADC_SMPR2_SMP8_1 0x02000000U
1330 #define ADC_SMPR2_SMP8_2 0x04000000U
1331 #define ADC_SMPR2_SMP9 0x38000000U
1332 #define ADC_SMPR2_SMP9_0 0x08000000U
1333 #define ADC_SMPR2_SMP9_1 0x10000000U
1334 #define ADC_SMPR2_SMP9_2 0x20000000U
1336 /****************** Bit definition for ADC_JOFR1 register *******************/
1337 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1339 /****************** Bit definition for ADC_JOFR2 register *******************/
1340 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1342 /****************** Bit definition for ADC_JOFR3 register *******************/
1343 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1345 /****************** Bit definition for ADC_JOFR4 register *******************/
1346 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1348 /******************* Bit definition for ADC_HTR register ********************/
1349 #define ADC_HTR_HT 0x0FFFU
1351 /******************* Bit definition for ADC_LTR register ********************/
1352 #define ADC_LTR_LT 0x0FFFU
1354 /******************* Bit definition for ADC_SQR1 register *******************/
1355 #define ADC_SQR1_SQ13 0x0000001FU
1356 #define ADC_SQR1_SQ13_0 0x00000001U
1357 #define ADC_SQR1_SQ13_1 0x00000002U
1358 #define ADC_SQR1_SQ13_2 0x00000004U
1359 #define ADC_SQR1_SQ13_3 0x00000008U
1360 #define ADC_SQR1_SQ13_4 0x00000010U
1361 #define ADC_SQR1_SQ14 0x000003E0U
1362 #define ADC_SQR1_SQ14_0 0x00000020U
1363 #define ADC_SQR1_SQ14_1 0x00000040U
1364 #define ADC_SQR1_SQ14_2 0x00000080U
1365 #define ADC_SQR1_SQ14_3 0x00000100U
1366 #define ADC_SQR1_SQ14_4 0x00000200U
1367 #define ADC_SQR1_SQ15 0x00007C00U
1368 #define ADC_SQR1_SQ15_0 0x00000400U
1369 #define ADC_SQR1_SQ15_1 0x00000800U
1370 #define ADC_SQR1_SQ15_2 0x00001000U
1371 #define ADC_SQR1_SQ15_3 0x00002000U
1372 #define ADC_SQR1_SQ15_4 0x00004000U
1373 #define ADC_SQR1_SQ16 0x000F8000U
1374 #define ADC_SQR1_SQ16_0 0x00008000U
1375 #define ADC_SQR1_SQ16_1 0x00010000U
1376 #define ADC_SQR1_SQ16_2 0x00020000U
1377 #define ADC_SQR1_SQ16_3 0x00040000U
1378 #define ADC_SQR1_SQ16_4 0x00080000U
1379 #define ADC_SQR1_L 0x00F00000U
1380 #define ADC_SQR1_L_0 0x00100000U
1381 #define ADC_SQR1_L_1 0x00200000U
1382 #define ADC_SQR1_L_2 0x00400000U
1383 #define ADC_SQR1_L_3 0x00800000U
1385 /******************* Bit definition for ADC_SQR2 register *******************/
1386 #define ADC_SQR2_SQ7 0x0000001FU
1387 #define ADC_SQR2_SQ7_0 0x00000001U
1388 #define ADC_SQR2_SQ7_1 0x00000002U
1389 #define ADC_SQR2_SQ7_2 0x00000004U
1390 #define ADC_SQR2_SQ7_3 0x00000008U
1391 #define ADC_SQR2_SQ7_4 0x00000010U
1392 #define ADC_SQR2_SQ8 0x000003E0U
1393 #define ADC_SQR2_SQ8_0 0x00000020U
1394 #define ADC_SQR2_SQ8_1 0x00000040U
1395 #define ADC_SQR2_SQ8_2 0x00000080U
1396 #define ADC_SQR2_SQ8_3 0x00000100U
1397 #define ADC_SQR2_SQ8_4 0x00000200U
1398 #define ADC_SQR2_SQ9 0x00007C00U
1399 #define ADC_SQR2_SQ9_0 0x00000400U
1400 #define ADC_SQR2_SQ9_1 0x00000800U
1401 #define ADC_SQR2_SQ9_2 0x00001000U
1402 #define ADC_SQR2_SQ9_3 0x00002000U
1403 #define ADC_SQR2_SQ9_4 0x00004000U
1404 #define ADC_SQR2_SQ10 0x000F8000U
1405 #define ADC_SQR2_SQ10_0 0x00008000U
1406 #define ADC_SQR2_SQ10_1 0x00010000U
1407 #define ADC_SQR2_SQ10_2 0x00020000U
1408 #define ADC_SQR2_SQ10_3 0x00040000U
1409 #define ADC_SQR2_SQ10_4 0x00080000U
1410 #define ADC_SQR2_SQ11 0x01F00000U
1411 #define ADC_SQR2_SQ11_0 0x00100000U
1412 #define ADC_SQR2_SQ11_1 0x00200000U
1413 #define ADC_SQR2_SQ11_2 0x00400000U
1414 #define ADC_SQR2_SQ11_3 0x00800000U
1415 #define ADC_SQR2_SQ11_4 0x01000000U
1416 #define ADC_SQR2_SQ12 0x3E000000U
1417 #define ADC_SQR2_SQ12_0 0x02000000U
1418 #define ADC_SQR2_SQ12_1 0x04000000U
1419 #define ADC_SQR2_SQ12_2 0x08000000U
1420 #define ADC_SQR2_SQ12_3 0x10000000U
1421 #define ADC_SQR2_SQ12_4 0x20000000U
1423 /******************* Bit definition for ADC_SQR3 register *******************/
1424 #define ADC_SQR3_SQ1 0x0000001FU
1425 #define ADC_SQR3_SQ1_0 0x00000001U
1426 #define ADC_SQR3_SQ1_1 0x00000002U
1427 #define ADC_SQR3_SQ1_2 0x00000004U
1428 #define ADC_SQR3_SQ1_3 0x00000008U
1429 #define ADC_SQR3_SQ1_4 0x00000010U
1430 #define ADC_SQR3_SQ2 0x000003E0U
1431 #define ADC_SQR3_SQ2_0 0x00000020U
1432 #define ADC_SQR3_SQ2_1 0x00000040U
1433 #define ADC_SQR3_SQ2_2 0x00000080U
1434 #define ADC_SQR3_SQ2_3 0x00000100U
1435 #define ADC_SQR3_SQ2_4 0x00000200U
1436 #define ADC_SQR3_SQ3 0x00007C00U
1437 #define ADC_SQR3_SQ3_0 0x00000400U
1438 #define ADC_SQR3_SQ3_1 0x00000800U
1439 #define ADC_SQR3_SQ3_2 0x00001000U
1440 #define ADC_SQR3_SQ3_3 0x00002000U
1441 #define ADC_SQR3_SQ3_4 0x00004000U
1442 #define ADC_SQR3_SQ4 0x000F8000U
1443 #define ADC_SQR3_SQ4_0 0x00008000U
1444 #define ADC_SQR3_SQ4_1 0x00010000U
1445 #define ADC_SQR3_SQ4_2 0x00020000U
1446 #define ADC_SQR3_SQ4_3 0x00040000U
1447 #define ADC_SQR3_SQ4_4 0x00080000U
1448 #define ADC_SQR3_SQ5 0x01F00000U
1449 #define ADC_SQR3_SQ5_0 0x00100000U
1450 #define ADC_SQR3_SQ5_1 0x00200000U
1451 #define ADC_SQR3_SQ5_2 0x00400000U
1452 #define ADC_SQR3_SQ5_3 0x00800000U
1453 #define ADC_SQR3_SQ5_4 0x01000000U
1454 #define ADC_SQR3_SQ6 0x3E000000U
1455 #define ADC_SQR3_SQ6_0 0x02000000U
1456 #define ADC_SQR3_SQ6_1 0x04000000U
1457 #define ADC_SQR3_SQ6_2 0x08000000U
1458 #define ADC_SQR3_SQ6_3 0x10000000U
1459 #define ADC_SQR3_SQ6_4 0x20000000U
1461 /******************* Bit definition for ADC_JSQR register *******************/
1462 #define ADC_JSQR_JSQ1 0x0000001FU
1463 #define ADC_JSQR_JSQ1_0 0x00000001U
1464 #define ADC_JSQR_JSQ1_1 0x00000002U
1465 #define ADC_JSQR_JSQ1_2 0x00000004U
1466 #define ADC_JSQR_JSQ1_3 0x00000008U
1467 #define ADC_JSQR_JSQ1_4 0x00000010U
1468 #define ADC_JSQR_JSQ2 0x000003E0U
1469 #define ADC_JSQR_JSQ2_0 0x00000020U
1470 #define ADC_JSQR_JSQ2_1 0x00000040U
1471 #define ADC_JSQR_JSQ2_2 0x00000080U
1472 #define ADC_JSQR_JSQ2_3 0x00000100U
1473 #define ADC_JSQR_JSQ2_4 0x00000200U
1474 #define ADC_JSQR_JSQ3 0x00007C00U
1475 #define ADC_JSQR_JSQ3_0 0x00000400U
1476 #define ADC_JSQR_JSQ3_1 0x00000800U
1477 #define ADC_JSQR_JSQ3_2 0x00001000U
1478 #define ADC_JSQR_JSQ3_3 0x00002000U
1479 #define ADC_JSQR_JSQ3_4 0x00004000U
1480 #define ADC_JSQR_JSQ4 0x000F8000U
1481 #define ADC_JSQR_JSQ4_0 0x00008000U
1482 #define ADC_JSQR_JSQ4_1 0x00010000U
1483 #define ADC_JSQR_JSQ4_2 0x00020000U
1484 #define ADC_JSQR_JSQ4_3 0x00040000U
1485 #define ADC_JSQR_JSQ4_4 0x00080000U
1486 #define ADC_JSQR_JL 0x00300000U
1487 #define ADC_JSQR_JL_0 0x00100000U
1488 #define ADC_JSQR_JL_1 0x00200000U
1490 /******************* Bit definition for ADC_JDR1 register *******************/
1491 #define ADC_JDR1_JDATA 0xFFFFU
1493 /******************* Bit definition for ADC_JDR2 register *******************/
1494 #define ADC_JDR2_JDATA 0xFFFFU
1496 /******************* Bit definition for ADC_JDR3 register *******************/
1497 #define ADC_JDR3_JDATA 0xFFFFU
1499 /******************* Bit definition for ADC_JDR4 register *******************/
1500 #define ADC_JDR4_JDATA 0xFFFFU
1502 /******************** Bit definition for ADC_DR register ********************/
1503 #define ADC_DR_DATA 0x0000FFFFU
1504 #define ADC_DR_ADC2DATA 0xFFFF0000U
1506 /******************* Bit definition for ADC_CSR register ********************/
1507 #define ADC_CSR_AWD1 0x00000001U
1508 #define ADC_CSR_EOC1 0x00000002U
1509 #define ADC_CSR_JEOC1 0x00000004U
1510 #define ADC_CSR_JSTRT1 0x00000008U
1511 #define ADC_CSR_STRT1 0x00000010U
1512 #define ADC_CSR_OVR1 0x00000020U
1513 #define ADC_CSR_AWD2 0x00000100U
1514 #define ADC_CSR_EOC2 0x00000200U
1515 #define ADC_CSR_JEOC2 0x00000400U
1516 #define ADC_CSR_JSTRT2 0x00000800U
1517 #define ADC_CSR_STRT2 0x00001000U
1518 #define ADC_CSR_OVR2 0x00002000U
1519 #define ADC_CSR_AWD3 0x00010000U
1520 #define ADC_CSR_EOC3 0x00020000U
1521 #define ADC_CSR_JEOC3 0x00040000U
1522 #define ADC_CSR_JSTRT3 0x00080000U
1523 #define ADC_CSR_STRT3 0x00100000U
1524 #define ADC_CSR_OVR3 0x00200000U
1526 /* Legacy defines */
1527 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1528 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1529 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1530 
1531 /******************* Bit definition for ADC_CCR register ********************/
1532 #define ADC_CCR_MULTI 0x0000001FU
1533 #define ADC_CCR_MULTI_0 0x00000001U
1534 #define ADC_CCR_MULTI_1 0x00000002U
1535 #define ADC_CCR_MULTI_2 0x00000004U
1536 #define ADC_CCR_MULTI_3 0x00000008U
1537 #define ADC_CCR_MULTI_4 0x00000010U
1538 #define ADC_CCR_DELAY 0x00000F00U
1539 #define ADC_CCR_DELAY_0 0x00000100U
1540 #define ADC_CCR_DELAY_1 0x00000200U
1541 #define ADC_CCR_DELAY_2 0x00000400U
1542 #define ADC_CCR_DELAY_3 0x00000800U
1543 #define ADC_CCR_DDS 0x00002000U
1544 #define ADC_CCR_DMA 0x0000C000U
1545 #define ADC_CCR_DMA_0 0x00004000U
1546 #define ADC_CCR_DMA_1 0x00008000U
1547 #define ADC_CCR_ADCPRE 0x00030000U
1548 #define ADC_CCR_ADCPRE_0 0x00010000U
1549 #define ADC_CCR_ADCPRE_1 0x00020000U
1550 #define ADC_CCR_VBATE 0x00400000U
1551 #define ADC_CCR_TSVREFE 0x00800000U
1553 /******************* Bit definition for ADC_CDR register ********************/
1554 #define ADC_CDR_DATA1 0x0000FFFFU
1555 #define ADC_CDR_DATA2 0xFFFF0000U
1557 /******************************************************************************/
1558 /* */
1559 /* Controller Area Network */
1560 /* */
1561 /******************************************************************************/
1563 /******************* Bit definition for CAN_MCR register ********************/
1564 #define CAN_MCR_INRQ 0x00000001U
1565 #define CAN_MCR_SLEEP 0x00000002U
1566 #define CAN_MCR_TXFP 0x00000004U
1567 #define CAN_MCR_RFLM 0x00000008U
1568 #define CAN_MCR_NART 0x00000010U
1569 #define CAN_MCR_AWUM 0x00000020U
1570 #define CAN_MCR_ABOM 0x00000040U
1571 #define CAN_MCR_TTCM 0x00000080U
1572 #define CAN_MCR_RESET 0x00008000U
1573 #define CAN_MCR_DBF 0x00010000U
1574 /******************* Bit definition for CAN_MSR register ********************/
1575 #define CAN_MSR_INAK 0x0001U
1576 #define CAN_MSR_SLAK 0x0002U
1577 #define CAN_MSR_ERRI 0x0004U
1578 #define CAN_MSR_WKUI 0x0008U
1579 #define CAN_MSR_SLAKI 0x0010U
1580 #define CAN_MSR_TXM 0x0100U
1581 #define CAN_MSR_RXM 0x0200U
1582 #define CAN_MSR_SAMP 0x0400U
1583 #define CAN_MSR_RX 0x0800U
1585 /******************* Bit definition for CAN_TSR register ********************/
1586 #define CAN_TSR_RQCP0 0x00000001U
1587 #define CAN_TSR_TXOK0 0x00000002U
1588 #define CAN_TSR_ALST0 0x00000004U
1589 #define CAN_TSR_TERR0 0x00000008U
1590 #define CAN_TSR_ABRQ0 0x00000080U
1591 #define CAN_TSR_RQCP1 0x00000100U
1592 #define CAN_TSR_TXOK1 0x00000200U
1593 #define CAN_TSR_ALST1 0x00000400U
1594 #define CAN_TSR_TERR1 0x00000800U
1595 #define CAN_TSR_ABRQ1 0x00008000U
1596 #define CAN_TSR_RQCP2 0x00010000U
1597 #define CAN_TSR_TXOK2 0x00020000U
1598 #define CAN_TSR_ALST2 0x00040000U
1599 #define CAN_TSR_TERR2 0x00080000U
1600 #define CAN_TSR_ABRQ2 0x00800000U
1601 #define CAN_TSR_CODE 0x03000000U
1603 #define CAN_TSR_TME 0x1C000000U
1604 #define CAN_TSR_TME0 0x04000000U
1605 #define CAN_TSR_TME1 0x08000000U
1606 #define CAN_TSR_TME2 0x10000000U
1608 #define CAN_TSR_LOW 0xE0000000U
1609 #define CAN_TSR_LOW0 0x20000000U
1610 #define CAN_TSR_LOW1 0x40000000U
1611 #define CAN_TSR_LOW2 0x80000000U
1613 /******************* Bit definition for CAN_RF0R register *******************/
1614 #define CAN_RF0R_FMP0 0x03U
1615 #define CAN_RF0R_FULL0 0x08U
1616 #define CAN_RF0R_FOVR0 0x10U
1617 #define CAN_RF0R_RFOM0 0x20U
1619 /******************* Bit definition for CAN_RF1R register *******************/
1620 #define CAN_RF1R_FMP1 0x03U
1621 #define CAN_RF1R_FULL1 0x08U
1622 #define CAN_RF1R_FOVR1 0x10U
1623 #define CAN_RF1R_RFOM1 0x20U
1625 /******************** Bit definition for CAN_IER register *******************/
1626 #define CAN_IER_TMEIE 0x00000001U
1627 #define CAN_IER_FMPIE0 0x00000002U
1628 #define CAN_IER_FFIE0 0x00000004U
1629 #define CAN_IER_FOVIE0 0x00000008U
1630 #define CAN_IER_FMPIE1 0x00000010U
1631 #define CAN_IER_FFIE1 0x00000020U
1632 #define CAN_IER_FOVIE1 0x00000040U
1633 #define CAN_IER_EWGIE 0x00000100U
1634 #define CAN_IER_EPVIE 0x00000200U
1635 #define CAN_IER_BOFIE 0x00000400U
1636 #define CAN_IER_LECIE 0x00000800U
1637 #define CAN_IER_ERRIE 0x00008000U
1638 #define CAN_IER_WKUIE 0x00010000U
1639 #define CAN_IER_SLKIE 0x00020000U
1640 #define CAN_IER_EWGIE 0x00000100U
1641 #define CAN_IER_EPVIE 0x00000200U
1642 #define CAN_IER_BOFIE 0x00000400U
1643 #define CAN_IER_LECIE 0x00000800U
1644 #define CAN_IER_ERRIE 0x00008000U
1647 /******************** Bit definition for CAN_ESR register *******************/
1648 #define CAN_ESR_EWGF 0x00000001U
1649 #define CAN_ESR_EPVF 0x00000002U
1650 #define CAN_ESR_BOFF 0x00000004U
1652 #define CAN_ESR_LEC 0x00000070U
1653 #define CAN_ESR_LEC_0 0x00000010U
1654 #define CAN_ESR_LEC_1 0x00000020U
1655 #define CAN_ESR_LEC_2 0x00000040U
1657 #define CAN_ESR_TEC 0x00FF0000U
1658 #define CAN_ESR_REC 0xFF000000U
1660 /******************* Bit definition for CAN_BTR register ********************/
1661 #define CAN_BTR_BRP 0x000003FFU
1662 #define CAN_BTR_TS1 0x000F0000U
1663 #define CAN_BTR_TS1_0 0x00010000U
1664 #define CAN_BTR_TS1_1 0x00020000U
1665 #define CAN_BTR_TS1_2 0x00040000U
1666 #define CAN_BTR_TS1_3 0x00080000U
1667 #define CAN_BTR_TS2 0x00700000U
1668 #define CAN_BTR_TS2_0 0x00100000U
1669 #define CAN_BTR_TS2_1 0x00200000U
1670 #define CAN_BTR_TS2_2 0x00400000U
1671 #define CAN_BTR_SJW 0x03000000U
1672 #define CAN_BTR_SJW_0 0x01000000U
1673 #define CAN_BTR_SJW_1 0x02000000U
1674 #define CAN_BTR_LBKM 0x40000000U
1675 #define CAN_BTR_SILM 0x80000000U
1679 /****************** Bit definition for CAN_TI0R register ********************/
1680 #define CAN_TI0R_TXRQ 0x00000001U
1681 #define CAN_TI0R_RTR 0x00000002U
1682 #define CAN_TI0R_IDE 0x00000004U
1683 #define CAN_TI0R_EXID 0x001FFFF8U
1684 #define CAN_TI0R_STID 0xFFE00000U
1686 /****************** Bit definition for CAN_TDT0R register *******************/
1687 #define CAN_TDT0R_DLC 0x0000000FU
1688 #define CAN_TDT0R_TGT 0x00000100U
1689 #define CAN_TDT0R_TIME 0xFFFF0000U
1691 /****************** Bit definition for CAN_TDL0R register *******************/
1692 #define CAN_TDL0R_DATA0 0x000000FFU
1693 #define CAN_TDL0R_DATA1 0x0000FF00U
1694 #define CAN_TDL0R_DATA2 0x00FF0000U
1695 #define CAN_TDL0R_DATA3 0xFF000000U
1697 /****************** Bit definition for CAN_TDH0R register *******************/
1698 #define CAN_TDH0R_DATA4 0x000000FFU
1699 #define CAN_TDH0R_DATA5 0x0000FF00U
1700 #define CAN_TDH0R_DATA6 0x00FF0000U
1701 #define CAN_TDH0R_DATA7 0xFF000000U
1703 /******************* Bit definition for CAN_TI1R register *******************/
1704 #define CAN_TI1R_TXRQ 0x00000001U
1705 #define CAN_TI1R_RTR 0x00000002U
1706 #define CAN_TI1R_IDE 0x00000004U
1707 #define CAN_TI1R_EXID 0x001FFFF8U
1708 #define CAN_TI1R_STID 0xFFE00000U
1710 /******************* Bit definition for CAN_TDT1R register ******************/
1711 #define CAN_TDT1R_DLC 0x0000000FU
1712 #define CAN_TDT1R_TGT 0x00000100U
1713 #define CAN_TDT1R_TIME 0xFFFF0000U
1715 /******************* Bit definition for CAN_TDL1R register ******************/
1716 #define CAN_TDL1R_DATA0 0x000000FFU
1717 #define CAN_TDL1R_DATA1 0x0000FF00U
1718 #define CAN_TDL1R_DATA2 0x00FF0000U
1719 #define CAN_TDL1R_DATA3 0xFF000000U
1721 /******************* Bit definition for CAN_TDH1R register ******************/
1722 #define CAN_TDH1R_DATA4 0x000000FFU
1723 #define CAN_TDH1R_DATA5 0x0000FF00U
1724 #define CAN_TDH1R_DATA6 0x00FF0000U
1725 #define CAN_TDH1R_DATA7 0xFF000000U
1727 /******************* Bit definition for CAN_TI2R register *******************/
1728 #define CAN_TI2R_TXRQ 0x00000001U
1729 #define CAN_TI2R_RTR 0x00000002U
1730 #define CAN_TI2R_IDE 0x00000004U
1731 #define CAN_TI2R_EXID 0x001FFFF8U
1732 #define CAN_TI2R_STID 0xFFE00000U
1734 /******************* Bit definition for CAN_TDT2R register ******************/
1735 #define CAN_TDT2R_DLC 0x0000000FU
1736 #define CAN_TDT2R_TGT 0x00000100U
1737 #define CAN_TDT2R_TIME 0xFFFF0000U
1739 /******************* Bit definition for CAN_TDL2R register ******************/
1740 #define CAN_TDL2R_DATA0 0x000000FFU
1741 #define CAN_TDL2R_DATA1 0x0000FF00U
1742 #define CAN_TDL2R_DATA2 0x00FF0000U
1743 #define CAN_TDL2R_DATA3 0xFF000000U
1745 /******************* Bit definition for CAN_TDH2R register ******************/
1746 #define CAN_TDH2R_DATA4 0x000000FFU
1747 #define CAN_TDH2R_DATA5 0x0000FF00U
1748 #define CAN_TDH2R_DATA6 0x00FF0000U
1749 #define CAN_TDH2R_DATA7 0xFF000000U
1751 /******************* Bit definition for CAN_RI0R register *******************/
1752 #define CAN_RI0R_RTR 0x00000002U
1753 #define CAN_RI0R_IDE 0x00000004U
1754 #define CAN_RI0R_EXID 0x001FFFF8U
1755 #define CAN_RI0R_STID 0xFFE00000U
1757 /******************* Bit definition for CAN_RDT0R register ******************/
1758 #define CAN_RDT0R_DLC 0x0000000FU
1759 #define CAN_RDT0R_FMI 0x0000FF00U
1760 #define CAN_RDT0R_TIME 0xFFFF0000U
1762 /******************* Bit definition for CAN_RDL0R register ******************/
1763 #define CAN_RDL0R_DATA0 0x000000FFU
1764 #define CAN_RDL0R_DATA1 0x0000FF00U
1765 #define CAN_RDL0R_DATA2 0x00FF0000U
1766 #define CAN_RDL0R_DATA3 0xFF000000U
1768 /******************* Bit definition for CAN_RDH0R register ******************/
1769 #define CAN_RDH0R_DATA4 0x000000FFU
1770 #define CAN_RDH0R_DATA5 0x0000FF00U
1771 #define CAN_RDH0R_DATA6 0x00FF0000U
1772 #define CAN_RDH0R_DATA7 0xFF000000U
1774 /******************* Bit definition for CAN_RI1R register *******************/
1775 #define CAN_RI1R_RTR 0x00000002U
1776 #define CAN_RI1R_IDE 0x00000004U
1777 #define CAN_RI1R_EXID 0x001FFFF8U
1778 #define CAN_RI1R_STID 0xFFE00000U
1780 /******************* Bit definition for CAN_RDT1R register ******************/
1781 #define CAN_RDT1R_DLC 0x0000000FU
1782 #define CAN_RDT1R_FMI 0x0000FF00U
1783 #define CAN_RDT1R_TIME 0xFFFF0000U
1785 /******************* Bit definition for CAN_RDL1R register ******************/
1786 #define CAN_RDL1R_DATA0 0x000000FFU
1787 #define CAN_RDL1R_DATA1 0x0000FF00U
1788 #define CAN_RDL1R_DATA2 0x00FF0000U
1789 #define CAN_RDL1R_DATA3 0xFF000000U
1791 /******************* Bit definition for CAN_RDH1R register ******************/
1792 #define CAN_RDH1R_DATA4 0x000000FFU
1793 #define CAN_RDH1R_DATA5 0x0000FF00U
1794 #define CAN_RDH1R_DATA6 0x00FF0000U
1795 #define CAN_RDH1R_DATA7 0xFF000000U
1798 /******************* Bit definition for CAN_FMR register ********************/
1799 #define CAN_FMR_FINIT 0x01U
1800 #define CAN_FMR_CAN2SB 0x00003F00U
1802 /******************* Bit definition for CAN_FM1R register *******************/
1803 #define CAN_FM1R_FBM 0x0FFFFFFFU
1804 #define CAN_FM1R_FBM0 0x00000001U
1805 #define CAN_FM1R_FBM1 0x00000002U
1806 #define CAN_FM1R_FBM2 0x00000004U
1807 #define CAN_FM1R_FBM3 0x00000008U
1808 #define CAN_FM1R_FBM4 0x00000010U
1809 #define CAN_FM1R_FBM5 0x00000020U
1810 #define CAN_FM1R_FBM6 0x00000040U
1811 #define CAN_FM1R_FBM7 0x00000080U
1812 #define CAN_FM1R_FBM8 0x00000100U
1813 #define CAN_FM1R_FBM9 0x00000200U
1814 #define CAN_FM1R_FBM10 0x00000400U
1815 #define CAN_FM1R_FBM11 0x00000800U
1816 #define CAN_FM1R_FBM12 0x00001000U
1817 #define CAN_FM1R_FBM13 0x00002000U
1818 #define CAN_FM1R_FBM14 0x00004000U
1819 #define CAN_FM1R_FBM15 0x00008000U
1820 #define CAN_FM1R_FBM16 0x00010000U
1821 #define CAN_FM1R_FBM17 0x00020000U
1822 #define CAN_FM1R_FBM18 0x00040000U
1823 #define CAN_FM1R_FBM19 0x00080000U
1824 #define CAN_FM1R_FBM20 0x00100000U
1825 #define CAN_FM1R_FBM21 0x00200000U
1826 #define CAN_FM1R_FBM22 0x00400000U
1827 #define CAN_FM1R_FBM23 0x00800000U
1828 #define CAN_FM1R_FBM24 0x01000000U
1829 #define CAN_FM1R_FBM25 0x02000000U
1830 #define CAN_FM1R_FBM26 0x04000000U
1831 #define CAN_FM1R_FBM27 0x08000000U
1833 /******************* Bit definition for CAN_FS1R register *******************/
1834 #define CAN_FS1R_FSC 0x0FFFFFFFU
1835 #define CAN_FS1R_FSC0 0x00000001U
1836 #define CAN_FS1R_FSC1 0x00000002U
1837 #define CAN_FS1R_FSC2 0x00000004U
1838 #define CAN_FS1R_FSC3 0x00000008U
1839 #define CAN_FS1R_FSC4 0x00000010U
1840 #define CAN_FS1R_FSC5 0x00000020U
1841 #define CAN_FS1R_FSC6 0x00000040U
1842 #define CAN_FS1R_FSC7 0x00000080U
1843 #define CAN_FS1R_FSC8 0x00000100U
1844 #define CAN_FS1R_FSC9 0x00000200U
1845 #define CAN_FS1R_FSC10 0x00000400U
1846 #define CAN_FS1R_FSC11 0x00000800U
1847 #define CAN_FS1R_FSC12 0x00001000U
1848 #define CAN_FS1R_FSC13 0x00002000U
1849 #define CAN_FS1R_FSC14 0x00004000U
1850 #define CAN_FS1R_FSC15 0x00008000U
1851 #define CAN_FS1R_FSC16 0x00010000U
1852 #define CAN_FS1R_FSC17 0x00020000U
1853 #define CAN_FS1R_FSC18 0x00040000U
1854 #define CAN_FS1R_FSC19 0x00080000U
1855 #define CAN_FS1R_FSC20 0x00100000U
1856 #define CAN_FS1R_FSC21 0x00200000U
1857 #define CAN_FS1R_FSC22 0x00400000U
1858 #define CAN_FS1R_FSC23 0x00800000U
1859 #define CAN_FS1R_FSC24 0x01000000U
1860 #define CAN_FS1R_FSC25 0x02000000U
1861 #define CAN_FS1R_FSC26 0x04000000U
1862 #define CAN_FS1R_FSC27 0x08000000U
1864 /****************** Bit definition for CAN_FFA1R register *******************/
1865 #define CAN_FFA1R_FFA 0x0FFFFFFFU
1866 #define CAN_FFA1R_FFA0 0x00000001U
1867 #define CAN_FFA1R_FFA1 0x00000002U
1868 #define CAN_FFA1R_FFA2 0x00000004U
1869 #define CAN_FFA1R_FFA3 0x00000008U
1870 #define CAN_FFA1R_FFA4 0x00000010U
1871 #define CAN_FFA1R_FFA5 0x00000020U
1872 #define CAN_FFA1R_FFA6 0x00000040U
1873 #define CAN_FFA1R_FFA7 0x00000080U
1874 #define CAN_FFA1R_FFA8 0x00000100U
1875 #define CAN_FFA1R_FFA9 0x00000200U
1876 #define CAN_FFA1R_FFA10 0x00000400U
1877 #define CAN_FFA1R_FFA11 0x00000800U
1878 #define CAN_FFA1R_FFA12 0x00001000U
1879 #define CAN_FFA1R_FFA13 0x00002000U
1880 #define CAN_FFA1R_FFA14 0x00004000U
1881 #define CAN_FFA1R_FFA15 0x00008000U
1882 #define CAN_FFA1R_FFA16 0x00010000U
1883 #define CAN_FFA1R_FFA17 0x00020000U
1884 #define CAN_FFA1R_FFA18 0x00040000U
1885 #define CAN_FFA1R_FFA19 0x00080000U
1886 #define CAN_FFA1R_FFA20 0x00100000U
1887 #define CAN_FFA1R_FFA21 0x00200000U
1888 #define CAN_FFA1R_FFA22 0x00400000U
1889 #define CAN_FFA1R_FFA23 0x00800000U
1890 #define CAN_FFA1R_FFA24 0x01000000U
1891 #define CAN_FFA1R_FFA25 0x02000000U
1892 #define CAN_FFA1R_FFA26 0x04000000U
1893 #define CAN_FFA1R_FFA27 0x08000000U
1895 /******************* Bit definition for CAN_FA1R register *******************/
1896 #define CAN_FA1R_FACT 0x0FFFFFFFU
1897 #define CAN_FA1R_FACT0 0x00000001U
1898 #define CAN_FA1R_FACT1 0x00000002U
1899 #define CAN_FA1R_FACT2 0x00000004U
1900 #define CAN_FA1R_FACT3 0x00000008U
1901 #define CAN_FA1R_FACT4 0x00000010U
1902 #define CAN_FA1R_FACT5 0x00000020U
1903 #define CAN_FA1R_FACT6 0x00000040U
1904 #define CAN_FA1R_FACT7 0x00000080U
1905 #define CAN_FA1R_FACT8 0x00000100U
1906 #define CAN_FA1R_FACT9 0x00000200U
1907 #define CAN_FA1R_FACT10 0x00000400U
1908 #define CAN_FA1R_FACT11 0x00000800U
1909 #define CAN_FA1R_FACT12 0x00001000U
1910 #define CAN_FA1R_FACT13 0x00002000U
1911 #define CAN_FA1R_FACT14 0x00004000U
1912 #define CAN_FA1R_FACT15 0x00008000U
1913 #define CAN_FA1R_FACT16 0x00010000U
1914 #define CAN_FA1R_FACT17 0x00020000U
1915 #define CAN_FA1R_FACT18 0x00040000U
1916 #define CAN_FA1R_FACT19 0x00080000U
1917 #define CAN_FA1R_FACT20 0x00100000U
1918 #define CAN_FA1R_FACT21 0x00200000U
1919 #define CAN_FA1R_FACT22 0x00400000U
1920 #define CAN_FA1R_FACT23 0x00800000U
1921 #define CAN_FA1R_FACT24 0x01000000U
1922 #define CAN_FA1R_FACT25 0x02000000U
1923 #define CAN_FA1R_FACT26 0x04000000U
1924 #define CAN_FA1R_FACT27 0x08000000U
1927 /******************* Bit definition for CAN_F0R1 register *******************/
1928 #define CAN_F0R1_FB0 0x00000001U
1929 #define CAN_F0R1_FB1 0x00000002U
1930 #define CAN_F0R1_FB2 0x00000004U
1931 #define CAN_F0R1_FB3 0x00000008U
1932 #define CAN_F0R1_FB4 0x00000010U
1933 #define CAN_F0R1_FB5 0x00000020U
1934 #define CAN_F0R1_FB6 0x00000040U
1935 #define CAN_F0R1_FB7 0x00000080U
1936 #define CAN_F0R1_FB8 0x00000100U
1937 #define CAN_F0R1_FB9 0x00000200U
1938 #define CAN_F0R1_FB10 0x00000400U
1939 #define CAN_F0R1_FB11 0x00000800U
1940 #define CAN_F0R1_FB12 0x00001000U
1941 #define CAN_F0R1_FB13 0x00002000U
1942 #define CAN_F0R1_FB14 0x00004000U
1943 #define CAN_F0R1_FB15 0x00008000U
1944 #define CAN_F0R1_FB16 0x00010000U
1945 #define CAN_F0R1_FB17 0x00020000U
1946 #define CAN_F0R1_FB18 0x00040000U
1947 #define CAN_F0R1_FB19 0x00080000U
1948 #define CAN_F0R1_FB20 0x00100000U
1949 #define CAN_F0R1_FB21 0x00200000U
1950 #define CAN_F0R1_FB22 0x00400000U
1951 #define CAN_F0R1_FB23 0x00800000U
1952 #define CAN_F0R1_FB24 0x01000000U
1953 #define CAN_F0R1_FB25 0x02000000U
1954 #define CAN_F0R1_FB26 0x04000000U
1955 #define CAN_F0R1_FB27 0x08000000U
1956 #define CAN_F0R1_FB28 0x10000000U
1957 #define CAN_F0R1_FB29 0x20000000U
1958 #define CAN_F0R1_FB30 0x40000000U
1959 #define CAN_F0R1_FB31 0x80000000U
1961 /******************* Bit definition for CAN_F1R1 register *******************/
1962 #define CAN_F1R1_FB0 0x00000001U
1963 #define CAN_F1R1_FB1 0x00000002U
1964 #define CAN_F1R1_FB2 0x00000004U
1965 #define CAN_F1R1_FB3 0x00000008U
1966 #define CAN_F1R1_FB4 0x00000010U
1967 #define CAN_F1R1_FB5 0x00000020U
1968 #define CAN_F1R1_FB6 0x00000040U
1969 #define CAN_F1R1_FB7 0x00000080U
1970 #define CAN_F1R1_FB8 0x00000100U
1971 #define CAN_F1R1_FB9 0x00000200U
1972 #define CAN_F1R1_FB10 0x00000400U
1973 #define CAN_F1R1_FB11 0x00000800U
1974 #define CAN_F1R1_FB12 0x00001000U
1975 #define CAN_F1R1_FB13 0x00002000U
1976 #define CAN_F1R1_FB14 0x00004000U
1977 #define CAN_F1R1_FB15 0x00008000U
1978 #define CAN_F1R1_FB16 0x00010000U
1979 #define CAN_F1R1_FB17 0x00020000U
1980 #define CAN_F1R1_FB18 0x00040000U
1981 #define CAN_F1R1_FB19 0x00080000U
1982 #define CAN_F1R1_FB20 0x00100000U
1983 #define CAN_F1R1_FB21 0x00200000U
1984 #define CAN_F1R1_FB22 0x00400000U
1985 #define CAN_F1R1_FB23 0x00800000U
1986 #define CAN_F1R1_FB24 0x01000000U
1987 #define CAN_F1R1_FB25 0x02000000U
1988 #define CAN_F1R1_FB26 0x04000000U
1989 #define CAN_F1R1_FB27 0x08000000U
1990 #define CAN_F1R1_FB28 0x10000000U
1991 #define CAN_F1R1_FB29 0x20000000U
1992 #define CAN_F1R1_FB30 0x40000000U
1993 #define CAN_F1R1_FB31 0x80000000U
1995 /******************* Bit definition for CAN_F2R1 register *******************/
1996 #define CAN_F2R1_FB0 0x00000001U
1997 #define CAN_F2R1_FB1 0x00000002U
1998 #define CAN_F2R1_FB2 0x00000004U
1999 #define CAN_F2R1_FB3 0x00000008U
2000 #define CAN_F2R1_FB4 0x00000010U
2001 #define CAN_F2R1_FB5 0x00000020U
2002 #define CAN_F2R1_FB6 0x00000040U
2003 #define CAN_F2R1_FB7 0x00000080U
2004 #define CAN_F2R1_FB8 0x00000100U
2005 #define CAN_F2R1_FB9 0x00000200U
2006 #define CAN_F2R1_FB10 0x00000400U
2007 #define CAN_F2R1_FB11 0x00000800U
2008 #define CAN_F2R1_FB12 0x00001000U
2009 #define CAN_F2R1_FB13 0x00002000U
2010 #define CAN_F2R1_FB14 0x00004000U
2011 #define CAN_F2R1_FB15 0x00008000U
2012 #define CAN_F2R1_FB16 0x00010000U
2013 #define CAN_F2R1_FB17 0x00020000U
2014 #define CAN_F2R1_FB18 0x00040000U
2015 #define CAN_F2R1_FB19 0x00080000U
2016 #define CAN_F2R1_FB20 0x00100000U
2017 #define CAN_F2R1_FB21 0x00200000U
2018 #define CAN_F2R1_FB22 0x00400000U
2019 #define CAN_F2R1_FB23 0x00800000U
2020 #define CAN_F2R1_FB24 0x01000000U
2021 #define CAN_F2R1_FB25 0x02000000U
2022 #define CAN_F2R1_FB26 0x04000000U
2023 #define CAN_F2R1_FB27 0x08000000U
2024 #define CAN_F2R1_FB28 0x10000000U
2025 #define CAN_F2R1_FB29 0x20000000U
2026 #define CAN_F2R1_FB30 0x40000000U
2027 #define CAN_F2R1_FB31 0x80000000U
2029 /******************* Bit definition for CAN_F3R1 register *******************/
2030 #define CAN_F3R1_FB0 0x00000001U
2031 #define CAN_F3R1_FB1 0x00000002U
2032 #define CAN_F3R1_FB2 0x00000004U
2033 #define CAN_F3R1_FB3 0x00000008U
2034 #define CAN_F3R1_FB4 0x00000010U
2035 #define CAN_F3R1_FB5 0x00000020U
2036 #define CAN_F3R1_FB6 0x00000040U
2037 #define CAN_F3R1_FB7 0x00000080U
2038 #define CAN_F3R1_FB8 0x00000100U
2039 #define CAN_F3R1_FB9 0x00000200U
2040 #define CAN_F3R1_FB10 0x00000400U
2041 #define CAN_F3R1_FB11 0x00000800U
2042 #define CAN_F3R1_FB12 0x00001000U
2043 #define CAN_F3R1_FB13 0x00002000U
2044 #define CAN_F3R1_FB14 0x00004000U
2045 #define CAN_F3R1_FB15 0x00008000U
2046 #define CAN_F3R1_FB16 0x00010000U
2047 #define CAN_F3R1_FB17 0x00020000U
2048 #define CAN_F3R1_FB18 0x00040000U
2049 #define CAN_F3R1_FB19 0x00080000U
2050 #define CAN_F3R1_FB20 0x00100000U
2051 #define CAN_F3R1_FB21 0x00200000U
2052 #define CAN_F3R1_FB22 0x00400000U
2053 #define CAN_F3R1_FB23 0x00800000U
2054 #define CAN_F3R1_FB24 0x01000000U
2055 #define CAN_F3R1_FB25 0x02000000U
2056 #define CAN_F3R1_FB26 0x04000000U
2057 #define CAN_F3R1_FB27 0x08000000U
2058 #define CAN_F3R1_FB28 0x10000000U
2059 #define CAN_F3R1_FB29 0x20000000U
2060 #define CAN_F3R1_FB30 0x40000000U
2061 #define CAN_F3R1_FB31 0x80000000U
2063 /******************* Bit definition for CAN_F4R1 register *******************/
2064 #define CAN_F4R1_FB0 0x00000001U
2065 #define CAN_F4R1_FB1 0x00000002U
2066 #define CAN_F4R1_FB2 0x00000004U
2067 #define CAN_F4R1_FB3 0x00000008U
2068 #define CAN_F4R1_FB4 0x00000010U
2069 #define CAN_F4R1_FB5 0x00000020U
2070 #define CAN_F4R1_FB6 0x00000040U
2071 #define CAN_F4R1_FB7 0x00000080U
2072 #define CAN_F4R1_FB8 0x00000100U
2073 #define CAN_F4R1_FB9 0x00000200U
2074 #define CAN_F4R1_FB10 0x00000400U
2075 #define CAN_F4R1_FB11 0x00000800U
2076 #define CAN_F4R1_FB12 0x00001000U
2077 #define CAN_F4R1_FB13 0x00002000U
2078 #define CAN_F4R1_FB14 0x00004000U
2079 #define CAN_F4R1_FB15 0x00008000U
2080 #define CAN_F4R1_FB16 0x00010000U
2081 #define CAN_F4R1_FB17 0x00020000U
2082 #define CAN_F4R1_FB18 0x00040000U
2083 #define CAN_F4R1_FB19 0x00080000U
2084 #define CAN_F4R1_FB20 0x00100000U
2085 #define CAN_F4R1_FB21 0x00200000U
2086 #define CAN_F4R1_FB22 0x00400000U
2087 #define CAN_F4R1_FB23 0x00800000U
2088 #define CAN_F4R1_FB24 0x01000000U
2089 #define CAN_F4R1_FB25 0x02000000U
2090 #define CAN_F4R1_FB26 0x04000000U
2091 #define CAN_F4R1_FB27 0x08000000U
2092 #define CAN_F4R1_FB28 0x10000000U
2093 #define CAN_F4R1_FB29 0x20000000U
2094 #define CAN_F4R1_FB30 0x40000000U
2095 #define CAN_F4R1_FB31 0x80000000U
2097 /******************* Bit definition for CAN_F5R1 register *******************/
2098 #define CAN_F5R1_FB0 0x00000001U
2099 #define CAN_F5R1_FB1 0x00000002U
2100 #define CAN_F5R1_FB2 0x00000004U
2101 #define CAN_F5R1_FB3 0x00000008U
2102 #define CAN_F5R1_FB4 0x00000010U
2103 #define CAN_F5R1_FB5 0x00000020U
2104 #define CAN_F5R1_FB6 0x00000040U
2105 #define CAN_F5R1_FB7 0x00000080U
2106 #define CAN_F5R1_FB8 0x00000100U
2107 #define CAN_F5R1_FB9 0x00000200U
2108 #define CAN_F5R1_FB10 0x00000400U
2109 #define CAN_F5R1_FB11 0x00000800U
2110 #define CAN_F5R1_FB12 0x00001000U
2111 #define CAN_F5R1_FB13 0x00002000U
2112 #define CAN_F5R1_FB14 0x00004000U
2113 #define CAN_F5R1_FB15 0x00008000U
2114 #define CAN_F5R1_FB16 0x00010000U
2115 #define CAN_F5R1_FB17 0x00020000U
2116 #define CAN_F5R1_FB18 0x00040000U
2117 #define CAN_F5R1_FB19 0x00080000U
2118 #define CAN_F5R1_FB20 0x00100000U
2119 #define CAN_F5R1_FB21 0x00200000U
2120 #define CAN_F5R1_FB22 0x00400000U
2121 #define CAN_F5R1_FB23 0x00800000U
2122 #define CAN_F5R1_FB24 0x01000000U
2123 #define CAN_F5R1_FB25 0x02000000U
2124 #define CAN_F5R1_FB26 0x04000000U
2125 #define CAN_F5R1_FB27 0x08000000U
2126 #define CAN_F5R1_FB28 0x10000000U
2127 #define CAN_F5R1_FB29 0x20000000U
2128 #define CAN_F5R1_FB30 0x40000000U
2129 #define CAN_F5R1_FB31 0x80000000U
2131 /******************* Bit definition for CAN_F6R1 register *******************/
2132 #define CAN_F6R1_FB0 0x00000001U
2133 #define CAN_F6R1_FB1 0x00000002U
2134 #define CAN_F6R1_FB2 0x00000004U
2135 #define CAN_F6R1_FB3 0x00000008U
2136 #define CAN_F6R1_FB4 0x00000010U
2137 #define CAN_F6R1_FB5 0x00000020U
2138 #define CAN_F6R1_FB6 0x00000040U
2139 #define CAN_F6R1_FB7 0x00000080U
2140 #define CAN_F6R1_FB8 0x00000100U
2141 #define CAN_F6R1_FB9 0x00000200U
2142 #define CAN_F6R1_FB10 0x00000400U
2143 #define CAN_F6R1_FB11 0x00000800U
2144 #define CAN_F6R1_FB12 0x00001000U
2145 #define CAN_F6R1_FB13 0x00002000U
2146 #define CAN_F6R1_FB14 0x00004000U
2147 #define CAN_F6R1_FB15 0x00008000U
2148 #define CAN_F6R1_FB16 0x00010000U
2149 #define CAN_F6R1_FB17 0x00020000U
2150 #define CAN_F6R1_FB18 0x00040000U
2151 #define CAN_F6R1_FB19 0x00080000U
2152 #define CAN_F6R1_FB20 0x00100000U
2153 #define CAN_F6R1_FB21 0x00200000U
2154 #define CAN_F6R1_FB22 0x00400000U
2155 #define CAN_F6R1_FB23 0x00800000U
2156 #define CAN_F6R1_FB24 0x01000000U
2157 #define CAN_F6R1_FB25 0x02000000U
2158 #define CAN_F6R1_FB26 0x04000000U
2159 #define CAN_F6R1_FB27 0x08000000U
2160 #define CAN_F6R1_FB28 0x10000000U
2161 #define CAN_F6R1_FB29 0x20000000U
2162 #define CAN_F6R1_FB30 0x40000000U
2163 #define CAN_F6R1_FB31 0x80000000U
2165 /******************* Bit definition for CAN_F7R1 register *******************/
2166 #define CAN_F7R1_FB0 0x00000001U
2167 #define CAN_F7R1_FB1 0x00000002U
2168 #define CAN_F7R1_FB2 0x00000004U
2169 #define CAN_F7R1_FB3 0x00000008U
2170 #define CAN_F7R1_FB4 0x00000010U
2171 #define CAN_F7R1_FB5 0x00000020U
2172 #define CAN_F7R1_FB6 0x00000040U
2173 #define CAN_F7R1_FB7 0x00000080U
2174 #define CAN_F7R1_FB8 0x00000100U
2175 #define CAN_F7R1_FB9 0x00000200U
2176 #define CAN_F7R1_FB10 0x00000400U
2177 #define CAN_F7R1_FB11 0x00000800U
2178 #define CAN_F7R1_FB12 0x00001000U
2179 #define CAN_F7R1_FB13 0x00002000U
2180 #define CAN_F7R1_FB14 0x00004000U
2181 #define CAN_F7R1_FB15 0x00008000U
2182 #define CAN_F7R1_FB16 0x00010000U
2183 #define CAN_F7R1_FB17 0x00020000U
2184 #define CAN_F7R1_FB18 0x00040000U
2185 #define CAN_F7R1_FB19 0x00080000U
2186 #define CAN_F7R1_FB20 0x00100000U
2187 #define CAN_F7R1_FB21 0x00200000U
2188 #define CAN_F7R1_FB22 0x00400000U
2189 #define CAN_F7R1_FB23 0x00800000U
2190 #define CAN_F7R1_FB24 0x01000000U
2191 #define CAN_F7R1_FB25 0x02000000U
2192 #define CAN_F7R1_FB26 0x04000000U
2193 #define CAN_F7R1_FB27 0x08000000U
2194 #define CAN_F7R1_FB28 0x10000000U
2195 #define CAN_F7R1_FB29 0x20000000U
2196 #define CAN_F7R1_FB30 0x40000000U
2197 #define CAN_F7R1_FB31 0x80000000U
2199 /******************* Bit definition for CAN_F8R1 register *******************/
2200 #define CAN_F8R1_FB0 0x00000001U
2201 #define CAN_F8R1_FB1 0x00000002U
2202 #define CAN_F8R1_FB2 0x00000004U
2203 #define CAN_F8R1_FB3 0x00000008U
2204 #define CAN_F8R1_FB4 0x00000010U
2205 #define CAN_F8R1_FB5 0x00000020U
2206 #define CAN_F8R1_FB6 0x00000040U
2207 #define CAN_F8R1_FB7 0x00000080U
2208 #define CAN_F8R1_FB8 0x00000100U
2209 #define CAN_F8R1_FB9 0x00000200U
2210 #define CAN_F8R1_FB10 0x00000400U
2211 #define CAN_F8R1_FB11 0x00000800U
2212 #define CAN_F8R1_FB12 0x00001000U
2213 #define CAN_F8R1_FB13 0x00002000U
2214 #define CAN_F8R1_FB14 0x00004000U
2215 #define CAN_F8R1_FB15 0x00008000U
2216 #define CAN_F8R1_FB16 0x00010000U
2217 #define CAN_F8R1_FB17 0x00020000U
2218 #define CAN_F8R1_FB18 0x00040000U
2219 #define CAN_F8R1_FB19 0x00080000U
2220 #define CAN_F8R1_FB20 0x00100000U
2221 #define CAN_F8R1_FB21 0x00200000U
2222 #define CAN_F8R1_FB22 0x00400000U
2223 #define CAN_F8R1_FB23 0x00800000U
2224 #define CAN_F8R1_FB24 0x01000000U
2225 #define CAN_F8R1_FB25 0x02000000U
2226 #define CAN_F8R1_FB26 0x04000000U
2227 #define CAN_F8R1_FB27 0x08000000U
2228 #define CAN_F8R1_FB28 0x10000000U
2229 #define CAN_F8R1_FB29 0x20000000U
2230 #define CAN_F8R1_FB30 0x40000000U
2231 #define CAN_F8R1_FB31 0x80000000U
2233 /******************* Bit definition for CAN_F9R1 register *******************/
2234 #define CAN_F9R1_FB0 0x00000001U
2235 #define CAN_F9R1_FB1 0x00000002U
2236 #define CAN_F9R1_FB2 0x00000004U
2237 #define CAN_F9R1_FB3 0x00000008U
2238 #define CAN_F9R1_FB4 0x00000010U
2239 #define CAN_F9R1_FB5 0x00000020U
2240 #define CAN_F9R1_FB6 0x00000040U
2241 #define CAN_F9R1_FB7 0x00000080U
2242 #define CAN_F9R1_FB8 0x00000100U
2243 #define CAN_F9R1_FB9 0x00000200U
2244 #define CAN_F9R1_FB10 0x00000400U
2245 #define CAN_F9R1_FB11 0x00000800U
2246 #define CAN_F9R1_FB12 0x00001000U
2247 #define CAN_F9R1_FB13 0x00002000U
2248 #define CAN_F9R1_FB14 0x00004000U
2249 #define CAN_F9R1_FB15 0x00008000U
2250 #define CAN_F9R1_FB16 0x00010000U
2251 #define CAN_F9R1_FB17 0x00020000U
2252 #define CAN_F9R1_FB18 0x00040000U
2253 #define CAN_F9R1_FB19 0x00080000U
2254 #define CAN_F9R1_FB20 0x00100000U
2255 #define CAN_F9R1_FB21 0x00200000U
2256 #define CAN_F9R1_FB22 0x00400000U
2257 #define CAN_F9R1_FB23 0x00800000U
2258 #define CAN_F9R1_FB24 0x01000000U
2259 #define CAN_F9R1_FB25 0x02000000U
2260 #define CAN_F9R1_FB26 0x04000000U
2261 #define CAN_F9R1_FB27 0x08000000U
2262 #define CAN_F9R1_FB28 0x10000000U
2263 #define CAN_F9R1_FB29 0x20000000U
2264 #define CAN_F9R1_FB30 0x40000000U
2265 #define CAN_F9R1_FB31 0x80000000U
2267 /******************* Bit definition for CAN_F10R1 register ******************/
2268 #define CAN_F10R1_FB0 0x00000001U
2269 #define CAN_F10R1_FB1 0x00000002U
2270 #define CAN_F10R1_FB2 0x00000004U
2271 #define CAN_F10R1_FB3 0x00000008U
2272 #define CAN_F10R1_FB4 0x00000010U
2273 #define CAN_F10R1_FB5 0x00000020U
2274 #define CAN_F10R1_FB6 0x00000040U
2275 #define CAN_F10R1_FB7 0x00000080U
2276 #define CAN_F10R1_FB8 0x00000100U
2277 #define CAN_F10R1_FB9 0x00000200U
2278 #define CAN_F10R1_FB10 0x00000400U
2279 #define CAN_F10R1_FB11 0x00000800U
2280 #define CAN_F10R1_FB12 0x00001000U
2281 #define CAN_F10R1_FB13 0x00002000U
2282 #define CAN_F10R1_FB14 0x00004000U
2283 #define CAN_F10R1_FB15 0x00008000U
2284 #define CAN_F10R1_FB16 0x00010000U
2285 #define CAN_F10R1_FB17 0x00020000U
2286 #define CAN_F10R1_FB18 0x00040000U
2287 #define CAN_F10R1_FB19 0x00080000U
2288 #define CAN_F10R1_FB20 0x00100000U
2289 #define CAN_F10R1_FB21 0x00200000U
2290 #define CAN_F10R1_FB22 0x00400000U
2291 #define CAN_F10R1_FB23 0x00800000U
2292 #define CAN_F10R1_FB24 0x01000000U
2293 #define CAN_F10R1_FB25 0x02000000U
2294 #define CAN_F10R1_FB26 0x04000000U
2295 #define CAN_F10R1_FB27 0x08000000U
2296 #define CAN_F10R1_FB28 0x10000000U
2297 #define CAN_F10R1_FB29 0x20000000U
2298 #define CAN_F10R1_FB30 0x40000000U
2299 #define CAN_F10R1_FB31 0x80000000U
2301 /******************* Bit definition for CAN_F11R1 register ******************/
2302 #define CAN_F11R1_FB0 0x00000001U
2303 #define CAN_F11R1_FB1 0x00000002U
2304 #define CAN_F11R1_FB2 0x00000004U
2305 #define CAN_F11R1_FB3 0x00000008U
2306 #define CAN_F11R1_FB4 0x00000010U
2307 #define CAN_F11R1_FB5 0x00000020U
2308 #define CAN_F11R1_FB6 0x00000040U
2309 #define CAN_F11R1_FB7 0x00000080U
2310 #define CAN_F11R1_FB8 0x00000100U
2311 #define CAN_F11R1_FB9 0x00000200U
2312 #define CAN_F11R1_FB10 0x00000400U
2313 #define CAN_F11R1_FB11 0x00000800U
2314 #define CAN_F11R1_FB12 0x00001000U
2315 #define CAN_F11R1_FB13 0x00002000U
2316 #define CAN_F11R1_FB14 0x00004000U
2317 #define CAN_F11R1_FB15 0x00008000U
2318 #define CAN_F11R1_FB16 0x00010000U
2319 #define CAN_F11R1_FB17 0x00020000U
2320 #define CAN_F11R1_FB18 0x00040000U
2321 #define CAN_F11R1_FB19 0x00080000U
2322 #define CAN_F11R1_FB20 0x00100000U
2323 #define CAN_F11R1_FB21 0x00200000U
2324 #define CAN_F11R1_FB22 0x00400000U
2325 #define CAN_F11R1_FB23 0x00800000U
2326 #define CAN_F11R1_FB24 0x01000000U
2327 #define CAN_F11R1_FB25 0x02000000U
2328 #define CAN_F11R1_FB26 0x04000000U
2329 #define CAN_F11R1_FB27 0x08000000U
2330 #define CAN_F11R1_FB28 0x10000000U
2331 #define CAN_F11R1_FB29 0x20000000U
2332 #define CAN_F11R1_FB30 0x40000000U
2333 #define CAN_F11R1_FB31 0x80000000U
2335 /******************* Bit definition for CAN_F12R1 register ******************/
2336 #define CAN_F12R1_FB0 0x00000001U
2337 #define CAN_F12R1_FB1 0x00000002U
2338 #define CAN_F12R1_FB2 0x00000004U
2339 #define CAN_F12R1_FB3 0x00000008U
2340 #define CAN_F12R1_FB4 0x00000010U
2341 #define CAN_F12R1_FB5 0x00000020U
2342 #define CAN_F12R1_FB6 0x00000040U
2343 #define CAN_F12R1_FB7 0x00000080U
2344 #define CAN_F12R1_FB8 0x00000100U
2345 #define CAN_F12R1_FB9 0x00000200U
2346 #define CAN_F12R1_FB10 0x00000400U
2347 #define CAN_F12R1_FB11 0x00000800U
2348 #define CAN_F12R1_FB12 0x00001000U
2349 #define CAN_F12R1_FB13 0x00002000U
2350 #define CAN_F12R1_FB14 0x00004000U
2351 #define CAN_F12R1_FB15 0x00008000U
2352 #define CAN_F12R1_FB16 0x00010000U
2353 #define CAN_F12R1_FB17 0x00020000U
2354 #define CAN_F12R1_FB18 0x00040000U
2355 #define CAN_F12R1_FB19 0x00080000U
2356 #define CAN_F12R1_FB20 0x00100000U
2357 #define CAN_F12R1_FB21 0x00200000U
2358 #define CAN_F12R1_FB22 0x00400000U
2359 #define CAN_F12R1_FB23 0x00800000U
2360 #define CAN_F12R1_FB24 0x01000000U
2361 #define CAN_F12R1_FB25 0x02000000U
2362 #define CAN_F12R1_FB26 0x04000000U
2363 #define CAN_F12R1_FB27 0x08000000U
2364 #define CAN_F12R1_FB28 0x10000000U
2365 #define CAN_F12R1_FB29 0x20000000U
2366 #define CAN_F12R1_FB30 0x40000000U
2367 #define CAN_F12R1_FB31 0x80000000U
2369 /******************* Bit definition for CAN_F13R1 register ******************/
2370 #define CAN_F13R1_FB0 0x00000001U
2371 #define CAN_F13R1_FB1 0x00000002U
2372 #define CAN_F13R1_FB2 0x00000004U
2373 #define CAN_F13R1_FB3 0x00000008U
2374 #define CAN_F13R1_FB4 0x00000010U
2375 #define CAN_F13R1_FB5 0x00000020U
2376 #define CAN_F13R1_FB6 0x00000040U
2377 #define CAN_F13R1_FB7 0x00000080U
2378 #define CAN_F13R1_FB8 0x00000100U
2379 #define CAN_F13R1_FB9 0x00000200U
2380 #define CAN_F13R1_FB10 0x00000400U
2381 #define CAN_F13R1_FB11 0x00000800U
2382 #define CAN_F13R1_FB12 0x00001000U
2383 #define CAN_F13R1_FB13 0x00002000U
2384 #define CAN_F13R1_FB14 0x00004000U
2385 #define CAN_F13R1_FB15 0x00008000U
2386 #define CAN_F13R1_FB16 0x00010000U
2387 #define CAN_F13R1_FB17 0x00020000U
2388 #define CAN_F13R1_FB18 0x00040000U
2389 #define CAN_F13R1_FB19 0x00080000U
2390 #define CAN_F13R1_FB20 0x00100000U
2391 #define CAN_F13R1_FB21 0x00200000U
2392 #define CAN_F13R1_FB22 0x00400000U
2393 #define CAN_F13R1_FB23 0x00800000U
2394 #define CAN_F13R1_FB24 0x01000000U
2395 #define CAN_F13R1_FB25 0x02000000U
2396 #define CAN_F13R1_FB26 0x04000000U
2397 #define CAN_F13R1_FB27 0x08000000U
2398 #define CAN_F13R1_FB28 0x10000000U
2399 #define CAN_F13R1_FB29 0x20000000U
2400 #define CAN_F13R1_FB30 0x40000000U
2401 #define CAN_F13R1_FB31 0x80000000U
2403 /******************* Bit definition for CAN_F0R2 register *******************/
2404 #define CAN_F0R2_FB0 0x00000001U
2405 #define CAN_F0R2_FB1 0x00000002U
2406 #define CAN_F0R2_FB2 0x00000004U
2407 #define CAN_F0R2_FB3 0x00000008U
2408 #define CAN_F0R2_FB4 0x00000010U
2409 #define CAN_F0R2_FB5 0x00000020U
2410 #define CAN_F0R2_FB6 0x00000040U
2411 #define CAN_F0R2_FB7 0x00000080U
2412 #define CAN_F0R2_FB8 0x00000100U
2413 #define CAN_F0R2_FB9 0x00000200U
2414 #define CAN_F0R2_FB10 0x00000400U
2415 #define CAN_F0R2_FB11 0x00000800U
2416 #define CAN_F0R2_FB12 0x00001000U
2417 #define CAN_F0R2_FB13 0x00002000U
2418 #define CAN_F0R2_FB14 0x00004000U
2419 #define CAN_F0R2_FB15 0x00008000U
2420 #define CAN_F0R2_FB16 0x00010000U
2421 #define CAN_F0R2_FB17 0x00020000U
2422 #define CAN_F0R2_FB18 0x00040000U
2423 #define CAN_F0R2_FB19 0x00080000U
2424 #define CAN_F0R2_FB20 0x00100000U
2425 #define CAN_F0R2_FB21 0x00200000U
2426 #define CAN_F0R2_FB22 0x00400000U
2427 #define CAN_F0R2_FB23 0x00800000U
2428 #define CAN_F0R2_FB24 0x01000000U
2429 #define CAN_F0R2_FB25 0x02000000U
2430 #define CAN_F0R2_FB26 0x04000000U
2431 #define CAN_F0R2_FB27 0x08000000U
2432 #define CAN_F0R2_FB28 0x10000000U
2433 #define CAN_F0R2_FB29 0x20000000U
2434 #define CAN_F0R2_FB30 0x40000000U
2435 #define CAN_F0R2_FB31 0x80000000U
2437 /******************* Bit definition for CAN_F1R2 register *******************/
2438 #define CAN_F1R2_FB0 0x00000001U
2439 #define CAN_F1R2_FB1 0x00000002U
2440 #define CAN_F1R2_FB2 0x00000004U
2441 #define CAN_F1R2_FB3 0x00000008U
2442 #define CAN_F1R2_FB4 0x00000010U
2443 #define CAN_F1R2_FB5 0x00000020U
2444 #define CAN_F1R2_FB6 0x00000040U
2445 #define CAN_F1R2_FB7 0x00000080U
2446 #define CAN_F1R2_FB8 0x00000100U
2447 #define CAN_F1R2_FB9 0x00000200U
2448 #define CAN_F1R2_FB10 0x00000400U
2449 #define CAN_F1R2_FB11 0x00000800U
2450 #define CAN_F1R2_FB12 0x00001000U
2451 #define CAN_F1R2_FB13 0x00002000U
2452 #define CAN_F1R2_FB14 0x00004000U
2453 #define CAN_F1R2_FB15 0x00008000U
2454 #define CAN_F1R2_FB16 0x00010000U
2455 #define CAN_F1R2_FB17 0x00020000U
2456 #define CAN_F1R2_FB18 0x00040000U
2457 #define CAN_F1R2_FB19 0x00080000U
2458 #define CAN_F1R2_FB20 0x00100000U
2459 #define CAN_F1R2_FB21 0x00200000U
2460 #define CAN_F1R2_FB22 0x00400000U
2461 #define CAN_F1R2_FB23 0x00800000U
2462 #define CAN_F1R2_FB24 0x01000000U
2463 #define CAN_F1R2_FB25 0x02000000U
2464 #define CAN_F1R2_FB26 0x04000000U
2465 #define CAN_F1R2_FB27 0x08000000U
2466 #define CAN_F1R2_FB28 0x10000000U
2467 #define CAN_F1R2_FB29 0x20000000U
2468 #define CAN_F1R2_FB30 0x40000000U
2469 #define CAN_F1R2_FB31 0x80000000U
2471 /******************* Bit definition for CAN_F2R2 register *******************/
2472 #define CAN_F2R2_FB0 0x00000001U
2473 #define CAN_F2R2_FB1 0x00000002U
2474 #define CAN_F2R2_FB2 0x00000004U
2475 #define CAN_F2R2_FB3 0x00000008U
2476 #define CAN_F2R2_FB4 0x00000010U
2477 #define CAN_F2R2_FB5 0x00000020U
2478 #define CAN_F2R2_FB6 0x00000040U
2479 #define CAN_F2R2_FB7 0x00000080U
2480 #define CAN_F2R2_FB8 0x00000100U
2481 #define CAN_F2R2_FB9 0x00000200U
2482 #define CAN_F2R2_FB10 0x00000400U
2483 #define CAN_F2R2_FB11 0x00000800U
2484 #define CAN_F2R2_FB12 0x00001000U
2485 #define CAN_F2R2_FB13 0x00002000U
2486 #define CAN_F2R2_FB14 0x00004000U
2487 #define CAN_F2R2_FB15 0x00008000U
2488 #define CAN_F2R2_FB16 0x00010000U
2489 #define CAN_F2R2_FB17 0x00020000U
2490 #define CAN_F2R2_FB18 0x00040000U
2491 #define CAN_F2R2_FB19 0x00080000U
2492 #define CAN_F2R2_FB20 0x00100000U
2493 #define CAN_F2R2_FB21 0x00200000U
2494 #define CAN_F2R2_FB22 0x00400000U
2495 #define CAN_F2R2_FB23 0x00800000U
2496 #define CAN_F2R2_FB24 0x01000000U
2497 #define CAN_F2R2_FB25 0x02000000U
2498 #define CAN_F2R2_FB26 0x04000000U
2499 #define CAN_F2R2_FB27 0x08000000U
2500 #define CAN_F2R2_FB28 0x10000000U
2501 #define CAN_F2R2_FB29 0x20000000U
2502 #define CAN_F2R2_FB30 0x40000000U
2503 #define CAN_F2R2_FB31 0x80000000U
2505 /******************* Bit definition for CAN_F3R2 register *******************/
2506 #define CAN_F3R2_FB0 0x00000001U
2507 #define CAN_F3R2_FB1 0x00000002U
2508 #define CAN_F3R2_FB2 0x00000004U
2509 #define CAN_F3R2_FB3 0x00000008U
2510 #define CAN_F3R2_FB4 0x00000010U
2511 #define CAN_F3R2_FB5 0x00000020U
2512 #define CAN_F3R2_FB6 0x00000040U
2513 #define CAN_F3R2_FB7 0x00000080U
2514 #define CAN_F3R2_FB8 0x00000100U
2515 #define CAN_F3R2_FB9 0x00000200U
2516 #define CAN_F3R2_FB10 0x00000400U
2517 #define CAN_F3R2_FB11 0x00000800U
2518 #define CAN_F3R2_FB12 0x00001000U
2519 #define CAN_F3R2_FB13 0x00002000U
2520 #define CAN_F3R2_FB14 0x00004000U
2521 #define CAN_F3R2_FB15 0x00008000U
2522 #define CAN_F3R2_FB16 0x00010000U
2523 #define CAN_F3R2_FB17 0x00020000U
2524 #define CAN_F3R2_FB18 0x00040000U
2525 #define CAN_F3R2_FB19 0x00080000U
2526 #define CAN_F3R2_FB20 0x00100000U
2527 #define CAN_F3R2_FB21 0x00200000U
2528 #define CAN_F3R2_FB22 0x00400000U
2529 #define CAN_F3R2_FB23 0x00800000U
2530 #define CAN_F3R2_FB24 0x01000000U
2531 #define CAN_F3R2_FB25 0x02000000U
2532 #define CAN_F3R2_FB26 0x04000000U
2533 #define CAN_F3R2_FB27 0x08000000U
2534 #define CAN_F3R2_FB28 0x10000000U
2535 #define CAN_F3R2_FB29 0x20000000U
2536 #define CAN_F3R2_FB30 0x40000000U
2537 #define CAN_F3R2_FB31 0x80000000U
2539 /******************* Bit definition for CAN_F4R2 register *******************/
2540 #define CAN_F4R2_FB0 0x00000001U
2541 #define CAN_F4R2_FB1 0x00000002U
2542 #define CAN_F4R2_FB2 0x00000004U
2543 #define CAN_F4R2_FB3 0x00000008U
2544 #define CAN_F4R2_FB4 0x00000010U
2545 #define CAN_F4R2_FB5 0x00000020U
2546 #define CAN_F4R2_FB6 0x00000040U
2547 #define CAN_F4R2_FB7 0x00000080U
2548 #define CAN_F4R2_FB8 0x00000100U
2549 #define CAN_F4R2_FB9 0x00000200U
2550 #define CAN_F4R2_FB10 0x00000400U
2551 #define CAN_F4R2_FB11 0x00000800U
2552 #define CAN_F4R2_FB12 0x00001000U
2553 #define CAN_F4R2_FB13 0x00002000U
2554 #define CAN_F4R2_FB14 0x00004000U
2555 #define CAN_F4R2_FB15 0x00008000U
2556 #define CAN_F4R2_FB16 0x00010000U
2557 #define CAN_F4R2_FB17 0x00020000U
2558 #define CAN_F4R2_FB18 0x00040000U
2559 #define CAN_F4R2_FB19 0x00080000U
2560 #define CAN_F4R2_FB20 0x00100000U
2561 #define CAN_F4R2_FB21 0x00200000U
2562 #define CAN_F4R2_FB22 0x00400000U
2563 #define CAN_F4R2_FB23 0x00800000U
2564 #define CAN_F4R2_FB24 0x01000000U
2565 #define CAN_F4R2_FB25 0x02000000U
2566 #define CAN_F4R2_FB26 0x04000000U
2567 #define CAN_F4R2_FB27 0x08000000U
2568 #define CAN_F4R2_FB28 0x10000000U
2569 #define CAN_F4R2_FB29 0x20000000U
2570 #define CAN_F4R2_FB30 0x40000000U
2571 #define CAN_F4R2_FB31 0x80000000U
2573 /******************* Bit definition for CAN_F5R2 register *******************/
2574 #define CAN_F5R2_FB0 0x00000001U
2575 #define CAN_F5R2_FB1 0x00000002U
2576 #define CAN_F5R2_FB2 0x00000004U
2577 #define CAN_F5R2_FB3 0x00000008U
2578 #define CAN_F5R2_FB4 0x00000010U
2579 #define CAN_F5R2_FB5 0x00000020U
2580 #define CAN_F5R2_FB6 0x00000040U
2581 #define CAN_F5R2_FB7 0x00000080U
2582 #define CAN_F5R2_FB8 0x00000100U
2583 #define CAN_F5R2_FB9 0x00000200U
2584 #define CAN_F5R2_FB10 0x00000400U
2585 #define CAN_F5R2_FB11 0x00000800U
2586 #define CAN_F5R2_FB12 0x00001000U
2587 #define CAN_F5R2_FB13 0x00002000U
2588 #define CAN_F5R2_FB14 0x00004000U
2589 #define CAN_F5R2_FB15 0x00008000U
2590 #define CAN_F5R2_FB16 0x00010000U
2591 #define CAN_F5R2_FB17 0x00020000U
2592 #define CAN_F5R2_FB18 0x00040000U
2593 #define CAN_F5R2_FB19 0x00080000U
2594 #define CAN_F5R2_FB20 0x00100000U
2595 #define CAN_F5R2_FB21 0x00200000U
2596 #define CAN_F5R2_FB22 0x00400000U
2597 #define CAN_F5R2_FB23 0x00800000U
2598 #define CAN_F5R2_FB24 0x01000000U
2599 #define CAN_F5R2_FB25 0x02000000U
2600 #define CAN_F5R2_FB26 0x04000000U
2601 #define CAN_F5R2_FB27 0x08000000U
2602 #define CAN_F5R2_FB28 0x10000000U
2603 #define CAN_F5R2_FB29 0x20000000U
2604 #define CAN_F5R2_FB30 0x40000000U
2605 #define CAN_F5R2_FB31 0x80000000U
2607 /******************* Bit definition for CAN_F6R2 register *******************/
2608 #define CAN_F6R2_FB0 0x00000001U
2609 #define CAN_F6R2_FB1 0x00000002U
2610 #define CAN_F6R2_FB2 0x00000004U
2611 #define CAN_F6R2_FB3 0x00000008U
2612 #define CAN_F6R2_FB4 0x00000010U
2613 #define CAN_F6R2_FB5 0x00000020U
2614 #define CAN_F6R2_FB6 0x00000040U
2615 #define CAN_F6R2_FB7 0x00000080U
2616 #define CAN_F6R2_FB8 0x00000100U
2617 #define CAN_F6R2_FB9 0x00000200U
2618 #define CAN_F6R2_FB10 0x00000400U
2619 #define CAN_F6R2_FB11 0x00000800U
2620 #define CAN_F6R2_FB12 0x00001000U
2621 #define CAN_F6R2_FB13 0x00002000U
2622 #define CAN_F6R2_FB14 0x00004000U
2623 #define CAN_F6R2_FB15 0x00008000U
2624 #define CAN_F6R2_FB16 0x00010000U
2625 #define CAN_F6R2_FB17 0x00020000U
2626 #define CAN_F6R2_FB18 0x00040000U
2627 #define CAN_F6R2_FB19 0x00080000U
2628 #define CAN_F6R2_FB20 0x00100000U
2629 #define CAN_F6R2_FB21 0x00200000U
2630 #define CAN_F6R2_FB22 0x00400000U
2631 #define CAN_F6R2_FB23 0x00800000U
2632 #define CAN_F6R2_FB24 0x01000000U
2633 #define CAN_F6R2_FB25 0x02000000U
2634 #define CAN_F6R2_FB26 0x04000000U
2635 #define CAN_F6R2_FB27 0x08000000U
2636 #define CAN_F6R2_FB28 0x10000000U
2637 #define CAN_F6R2_FB29 0x20000000U
2638 #define CAN_F6R2_FB30 0x40000000U
2639 #define CAN_F6R2_FB31 0x80000000U
2641 /******************* Bit definition for CAN_F7R2 register *******************/
2642 #define CAN_F7R2_FB0 0x00000001U
2643 #define CAN_F7R2_FB1 0x00000002U
2644 #define CAN_F7R2_FB2 0x00000004U
2645 #define CAN_F7R2_FB3 0x00000008U
2646 #define CAN_F7R2_FB4 0x00000010U
2647 #define CAN_F7R2_FB5 0x00000020U
2648 #define CAN_F7R2_FB6 0x00000040U
2649 #define CAN_F7R2_FB7 0x00000080U
2650 #define CAN_F7R2_FB8 0x00000100U
2651 #define CAN_F7R2_FB9 0x00000200U
2652 #define CAN_F7R2_FB10 0x00000400U
2653 #define CAN_F7R2_FB11 0x00000800U
2654 #define CAN_F7R2_FB12 0x00001000U
2655 #define CAN_F7R2_FB13 0x00002000U
2656 #define CAN_F7R2_FB14 0x00004000U
2657 #define CAN_F7R2_FB15 0x00008000U
2658 #define CAN_F7R2_FB16 0x00010000U
2659 #define CAN_F7R2_FB17 0x00020000U
2660 #define CAN_F7R2_FB18 0x00040000U
2661 #define CAN_F7R2_FB19 0x00080000U
2662 #define CAN_F7R2_FB20 0x00100000U
2663 #define CAN_F7R2_FB21 0x00200000U
2664 #define CAN_F7R2_FB22 0x00400000U
2665 #define CAN_F7R2_FB23 0x00800000U
2666 #define CAN_F7R2_FB24 0x01000000U
2667 #define CAN_F7R2_FB25 0x02000000U
2668 #define CAN_F7R2_FB26 0x04000000U
2669 #define CAN_F7R2_FB27 0x08000000U
2670 #define CAN_F7R2_FB28 0x10000000U
2671 #define CAN_F7R2_FB29 0x20000000U
2672 #define CAN_F7R2_FB30 0x40000000U
2673 #define CAN_F7R2_FB31 0x80000000U
2675 /******************* Bit definition for CAN_F8R2 register *******************/
2676 #define CAN_F8R2_FB0 0x00000001U
2677 #define CAN_F8R2_FB1 0x00000002U
2678 #define CAN_F8R2_FB2 0x00000004U
2679 #define CAN_F8R2_FB3 0x00000008U
2680 #define CAN_F8R2_FB4 0x00000010U
2681 #define CAN_F8R2_FB5 0x00000020U
2682 #define CAN_F8R2_FB6 0x00000040U
2683 #define CAN_F8R2_FB7 0x00000080U
2684 #define CAN_F8R2_FB8 0x00000100U
2685 #define CAN_F8R2_FB9 0x00000200U
2686 #define CAN_F8R2_FB10 0x00000400U
2687 #define CAN_F8R2_FB11 0x00000800U
2688 #define CAN_F8R2_FB12 0x00001000U
2689 #define CAN_F8R2_FB13 0x00002000U
2690 #define CAN_F8R2_FB14 0x00004000U
2691 #define CAN_F8R2_FB15 0x00008000U
2692 #define CAN_F8R2_FB16 0x00010000U
2693 #define CAN_F8R2_FB17 0x00020000U
2694 #define CAN_F8R2_FB18 0x00040000U
2695 #define CAN_F8R2_FB19 0x00080000U
2696 #define CAN_F8R2_FB20 0x00100000U
2697 #define CAN_F8R2_FB21 0x00200000U
2698 #define CAN_F8R2_FB22 0x00400000U
2699 #define CAN_F8R2_FB23 0x00800000U
2700 #define CAN_F8R2_FB24 0x01000000U
2701 #define CAN_F8R2_FB25 0x02000000U
2702 #define CAN_F8R2_FB26 0x04000000U
2703 #define CAN_F8R2_FB27 0x08000000U
2704 #define CAN_F8R2_FB28 0x10000000U
2705 #define CAN_F8R2_FB29 0x20000000U
2706 #define CAN_F8R2_FB30 0x40000000U
2707 #define CAN_F8R2_FB31 0x80000000U
2709 /******************* Bit definition for CAN_F9R2 register *******************/
2710 #define CAN_F9R2_FB0 0x00000001U
2711 #define CAN_F9R2_FB1 0x00000002U
2712 #define CAN_F9R2_FB2 0x00000004U
2713 #define CAN_F9R2_FB3 0x00000008U
2714 #define CAN_F9R2_FB4 0x00000010U
2715 #define CAN_F9R2_FB5 0x00000020U
2716 #define CAN_F9R2_FB6 0x00000040U
2717 #define CAN_F9R2_FB7 0x00000080U
2718 #define CAN_F9R2_FB8 0x00000100U
2719 #define CAN_F9R2_FB9 0x00000200U
2720 #define CAN_F9R2_FB10 0x00000400U
2721 #define CAN_F9R2_FB11 0x00000800U
2722 #define CAN_F9R2_FB12 0x00001000U
2723 #define CAN_F9R2_FB13 0x00002000U
2724 #define CAN_F9R2_FB14 0x00004000U
2725 #define CAN_F9R2_FB15 0x00008000U
2726 #define CAN_F9R2_FB16 0x00010000U
2727 #define CAN_F9R2_FB17 0x00020000U
2728 #define CAN_F9R2_FB18 0x00040000U
2729 #define CAN_F9R2_FB19 0x00080000U
2730 #define CAN_F9R2_FB20 0x00100000U
2731 #define CAN_F9R2_FB21 0x00200000U
2732 #define CAN_F9R2_FB22 0x00400000U
2733 #define CAN_F9R2_FB23 0x00800000U
2734 #define CAN_F9R2_FB24 0x01000000U
2735 #define CAN_F9R2_FB25 0x02000000U
2736 #define CAN_F9R2_FB26 0x04000000U
2737 #define CAN_F9R2_FB27 0x08000000U
2738 #define CAN_F9R2_FB28 0x10000000U
2739 #define CAN_F9R2_FB29 0x20000000U
2740 #define CAN_F9R2_FB30 0x40000000U
2741 #define CAN_F9R2_FB31 0x80000000U
2743 /******************* Bit definition for CAN_F10R2 register ******************/
2744 #define CAN_F10R2_FB0 0x00000001U
2745 #define CAN_F10R2_FB1 0x00000002U
2746 #define CAN_F10R2_FB2 0x00000004U
2747 #define CAN_F10R2_FB3 0x00000008U
2748 #define CAN_F10R2_FB4 0x00000010U
2749 #define CAN_F10R2_FB5 0x00000020U
2750 #define CAN_F10R2_FB6 0x00000040U
2751 #define CAN_F10R2_FB7 0x00000080U
2752 #define CAN_F10R2_FB8 0x00000100U
2753 #define CAN_F10R2_FB9 0x00000200U
2754 #define CAN_F10R2_FB10 0x00000400U
2755 #define CAN_F10R2_FB11 0x00000800U
2756 #define CAN_F10R2_FB12 0x00001000U
2757 #define CAN_F10R2_FB13 0x00002000U
2758 #define CAN_F10R2_FB14 0x00004000U
2759 #define CAN_F10R2_FB15 0x00008000U
2760 #define CAN_F10R2_FB16 0x00010000U
2761 #define CAN_F10R2_FB17 0x00020000U
2762 #define CAN_F10R2_FB18 0x00040000U
2763 #define CAN_F10R2_FB19 0x00080000U
2764 #define CAN_F10R2_FB20 0x00100000U
2765 #define CAN_F10R2_FB21 0x00200000U
2766 #define CAN_F10R2_FB22 0x00400000U
2767 #define CAN_F10R2_FB23 0x00800000U
2768 #define CAN_F10R2_FB24 0x01000000U
2769 #define CAN_F10R2_FB25 0x02000000U
2770 #define CAN_F10R2_FB26 0x04000000U
2771 #define CAN_F10R2_FB27 0x08000000U
2772 #define CAN_F10R2_FB28 0x10000000U
2773 #define CAN_F10R2_FB29 0x20000000U
2774 #define CAN_F10R2_FB30 0x40000000U
2775 #define CAN_F10R2_FB31 0x80000000U
2777 /******************* Bit definition for CAN_F11R2 register ******************/
2778 #define CAN_F11R2_FB0 0x00000001U
2779 #define CAN_F11R2_FB1 0x00000002U
2780 #define CAN_F11R2_FB2 0x00000004U
2781 #define CAN_F11R2_FB3 0x00000008U
2782 #define CAN_F11R2_FB4 0x00000010U
2783 #define CAN_F11R2_FB5 0x00000020U
2784 #define CAN_F11R2_FB6 0x00000040U
2785 #define CAN_F11R2_FB7 0x00000080U
2786 #define CAN_F11R2_FB8 0x00000100U
2787 #define CAN_F11R2_FB9 0x00000200U
2788 #define CAN_F11R2_FB10 0x00000400U
2789 #define CAN_F11R2_FB11 0x00000800U
2790 #define CAN_F11R2_FB12 0x00001000U
2791 #define CAN_F11R2_FB13 0x00002000U
2792 #define CAN_F11R2_FB14 0x00004000U
2793 #define CAN_F11R2_FB15 0x00008000U
2794 #define CAN_F11R2_FB16 0x00010000U
2795 #define CAN_F11R2_FB17 0x00020000U
2796 #define CAN_F11R2_FB18 0x00040000U
2797 #define CAN_F11R2_FB19 0x00080000U
2798 #define CAN_F11R2_FB20 0x00100000U
2799 #define CAN_F11R2_FB21 0x00200000U
2800 #define CAN_F11R2_FB22 0x00400000U
2801 #define CAN_F11R2_FB23 0x00800000U
2802 #define CAN_F11R2_FB24 0x01000000U
2803 #define CAN_F11R2_FB25 0x02000000U
2804 #define CAN_F11R2_FB26 0x04000000U
2805 #define CAN_F11R2_FB27 0x08000000U
2806 #define CAN_F11R2_FB28 0x10000000U
2807 #define CAN_F11R2_FB29 0x20000000U
2808 #define CAN_F11R2_FB30 0x40000000U
2809 #define CAN_F11R2_FB31 0x80000000U
2811 /******************* Bit definition for CAN_F12R2 register ******************/
2812 #define CAN_F12R2_FB0 0x00000001U
2813 #define CAN_F12R2_FB1 0x00000002U
2814 #define CAN_F12R2_FB2 0x00000004U
2815 #define CAN_F12R2_FB3 0x00000008U
2816 #define CAN_F12R2_FB4 0x00000010U
2817 #define CAN_F12R2_FB5 0x00000020U
2818 #define CAN_F12R2_FB6 0x00000040U
2819 #define CAN_F12R2_FB7 0x00000080U
2820 #define CAN_F12R2_FB8 0x00000100U
2821 #define CAN_F12R2_FB9 0x00000200U
2822 #define CAN_F12R2_FB10 0x00000400U
2823 #define CAN_F12R2_FB11 0x00000800U
2824 #define CAN_F12R2_FB12 0x00001000U
2825 #define CAN_F12R2_FB13 0x00002000U
2826 #define CAN_F12R2_FB14 0x00004000U
2827 #define CAN_F12R2_FB15 0x00008000U
2828 #define CAN_F12R2_FB16 0x00010000U
2829 #define CAN_F12R2_FB17 0x00020000U
2830 #define CAN_F12R2_FB18 0x00040000U
2831 #define CAN_F12R2_FB19 0x00080000U
2832 #define CAN_F12R2_FB20 0x00100000U
2833 #define CAN_F12R2_FB21 0x00200000U
2834 #define CAN_F12R2_FB22 0x00400000U
2835 #define CAN_F12R2_FB23 0x00800000U
2836 #define CAN_F12R2_FB24 0x01000000U
2837 #define CAN_F12R2_FB25 0x02000000U
2838 #define CAN_F12R2_FB26 0x04000000U
2839 #define CAN_F12R2_FB27 0x08000000U
2840 #define CAN_F12R2_FB28 0x10000000U
2841 #define CAN_F12R2_FB29 0x20000000U
2842 #define CAN_F12R2_FB30 0x40000000U
2843 #define CAN_F12R2_FB31 0x80000000U
2845 /******************* Bit definition for CAN_F13R2 register ******************/
2846 #define CAN_F13R2_FB0 0x00000001U
2847 #define CAN_F13R2_FB1 0x00000002U
2848 #define CAN_F13R2_FB2 0x00000004U
2849 #define CAN_F13R2_FB3 0x00000008U
2850 #define CAN_F13R2_FB4 0x00000010U
2851 #define CAN_F13R2_FB5 0x00000020U
2852 #define CAN_F13R2_FB6 0x00000040U
2853 #define CAN_F13R2_FB7 0x00000080U
2854 #define CAN_F13R2_FB8 0x00000100U
2855 #define CAN_F13R2_FB9 0x00000200U
2856 #define CAN_F13R2_FB10 0x00000400U
2857 #define CAN_F13R2_FB11 0x00000800U
2858 #define CAN_F13R2_FB12 0x00001000U
2859 #define CAN_F13R2_FB13 0x00002000U
2860 #define CAN_F13R2_FB14 0x00004000U
2861 #define CAN_F13R2_FB15 0x00008000U
2862 #define CAN_F13R2_FB16 0x00010000U
2863 #define CAN_F13R2_FB17 0x00020000U
2864 #define CAN_F13R2_FB18 0x00040000U
2865 #define CAN_F13R2_FB19 0x00080000U
2866 #define CAN_F13R2_FB20 0x00100000U
2867 #define CAN_F13R2_FB21 0x00200000U
2868 #define CAN_F13R2_FB22 0x00400000U
2869 #define CAN_F13R2_FB23 0x00800000U
2870 #define CAN_F13R2_FB24 0x01000000U
2871 #define CAN_F13R2_FB25 0x02000000U
2872 #define CAN_F13R2_FB26 0x04000000U
2873 #define CAN_F13R2_FB27 0x08000000U
2874 #define CAN_F13R2_FB28 0x10000000U
2875 #define CAN_F13R2_FB29 0x20000000U
2876 #define CAN_F13R2_FB30 0x40000000U
2877 #define CAN_F13R2_FB31 0x80000000U
2879 /******************************************************************************/
2880 /* */
2881 /* HDMI-CEC (CEC) */
2882 /* */
2883 /******************************************************************************/
2884 
2885 /******************* Bit definition for CEC_CR register *********************/
2886 #define CEC_CR_CECEN 0x00000001U
2887 #define CEC_CR_TXSOM 0x00000002U
2888 #define CEC_CR_TXEOM 0x00000004U
2890 /******************* Bit definition for CEC_CFGR register *******************/
2891 #define CEC_CFGR_SFT 0x00000007U
2892 #define CEC_CFGR_RXTOL 0x00000008U
2893 #define CEC_CFGR_BRESTP 0x00000010U
2894 #define CEC_CFGR_BREGEN 0x00000020U
2895 #define CEC_CFGR_LBPEGEN 0x00000040U
2896 #define CEC_CFGR_SFTOPT 0x00000100U
2897 #define CEC_CFGR_BRDNOGEN 0x00000080U
2898 #define CEC_CFGR_OAR 0x7FFF0000U
2899 #define CEC_CFGR_LSTN 0x80000000U
2901 /******************* Bit definition for CEC_TXDR register *******************/
2902 #define CEC_TXDR_TXD 0x000000FFU
2904 /******************* Bit definition for CEC_RXDR register *******************/
2905 #define CEC_TXDR_RXD 0x000000FFU
2907 /******************* Bit definition for CEC_ISR register ********************/
2908 #define CEC_ISR_RXBR 0x00000001U
2909 #define CEC_ISR_RXEND 0x00000002U
2910 #define CEC_ISR_RXOVR 0x00000004U
2911 #define CEC_ISR_BRE 0x00000008U
2912 #define CEC_ISR_SBPE 0x00000010U
2913 #define CEC_ISR_LBPE 0x00000020U
2914 #define CEC_ISR_RXACKE 0x00000040U
2915 #define CEC_ISR_ARBLST 0x00000080U
2916 #define CEC_ISR_TXBR 0x00000100U
2917 #define CEC_ISR_TXEND 0x00000200U
2918 #define CEC_ISR_TXUDR 0x00000400U
2919 #define CEC_ISR_TXERR 0x00000800U
2920 #define CEC_ISR_TXACKE 0x00001000U
2922 /******************* Bit definition for CEC_IER register ********************/
2923 #define CEC_IER_RXBRIE 0x00000001U
2924 #define CEC_IER_RXENDIE 0x00000002U
2925 #define CEC_IER_RXOVRIE 0x00000004U
2926 #define CEC_IER_BREIE 0x00000008U
2927 #define CEC_IER_SBPEIE 0x00000010U
2928 #define CEC_IER_LBPEIE 0x00000020U
2929 #define CEC_IER_RXACKEIE 0x00000040U
2930 #define CEC_IER_ARBLSTIE 0x00000080U
2931 #define CEC_IER_TXBRIE 0x00000100U
2932 #define CEC_IER_TXENDIE 0x00000200U
2933 #define CEC_IER_TXUDRIE 0x00000400U
2934 #define CEC_IER_TXERRIE 0x00000800U
2935 #define CEC_IER_TXACKEIE 0x00001000U
2937 /******************************************************************************/
2938 /* */
2939 /* CRC calculation unit */
2940 /* */
2941 /******************************************************************************/
2942 /******************* Bit definition for CRC_DR register *********************/
2943 #define CRC_DR_DR 0xFFFFFFFFU
2946 /******************* Bit definition for CRC_IDR register ********************/
2947 #define CRC_IDR_IDR 0xFFU
2950 /******************** Bit definition for CRC_CR register ********************/
2951 #define CRC_CR_RESET 0x01U
2953 /******************************************************************************/
2954 /* */
2955 /* Digital to Analog Converter */
2956 /* */
2957 /******************************************************************************/
2958 /******************** Bit definition for DAC_CR register ********************/
2959 #define DAC_CR_EN1 0x00000001U
2960 #define DAC_CR_BOFF1 0x00000002U
2961 #define DAC_CR_TEN1 0x00000004U
2963 #define DAC_CR_TSEL1 0x00000038U
2964 #define DAC_CR_TSEL1_0 0x00000008U
2965 #define DAC_CR_TSEL1_1 0x00000010U
2966 #define DAC_CR_TSEL1_2 0x00000020U
2968 #define DAC_CR_WAVE1 0x000000C0U
2969 #define DAC_CR_WAVE1_0 0x00000040U
2970 #define DAC_CR_WAVE1_1 0x00000080U
2972 #define DAC_CR_MAMP1 0x00000F00U
2973 #define DAC_CR_MAMP1_0 0x00000100U
2974 #define DAC_CR_MAMP1_1 0x00000200U
2975 #define DAC_CR_MAMP1_2 0x00000400U
2976 #define DAC_CR_MAMP1_3 0x00000800U
2978 #define DAC_CR_DMAEN1 0x00001000U
2979 #define DAC_CR_DMAUDRIE1 0x00002000U
2980 #define DAC_CR_EN2 0x00010000U
2981 #define DAC_CR_BOFF2 0x00020000U
2982 #define DAC_CR_TEN2 0x00040000U
2984 #define DAC_CR_TSEL2 0x00380000U
2985 #define DAC_CR_TSEL2_0 0x00080000U
2986 #define DAC_CR_TSEL2_1 0x00100000U
2987 #define DAC_CR_TSEL2_2 0x00200000U
2989 #define DAC_CR_WAVE2 0x00C00000U
2990 #define DAC_CR_WAVE2_0 0x00400000U
2991 #define DAC_CR_WAVE2_1 0x00800000U
2993 #define DAC_CR_MAMP2 0x0F000000U
2994 #define DAC_CR_MAMP2_0 0x01000000U
2995 #define DAC_CR_MAMP2_1 0x02000000U
2996 #define DAC_CR_MAMP2_2 0x04000000U
2997 #define DAC_CR_MAMP2_3 0x08000000U
2999 #define DAC_CR_DMAEN2 0x10000000U
3000 #define DAC_CR_DMAUDRIE2 0x20000000U
3002 /***************** Bit definition for DAC_SWTRIGR register ******************/
3003 #define DAC_SWTRIGR_SWTRIG1 0x01U
3004 #define DAC_SWTRIGR_SWTRIG2 0x02U
3006 /***************** Bit definition for DAC_DHR12R1 register ******************/
3007 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3009 /***************** Bit definition for DAC_DHR12L1 register ******************/
3010 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3012 /****************** Bit definition for DAC_DHR8R1 register ******************/
3013 #define DAC_DHR8R1_DACC1DHR 0xFFU
3015 /***************** Bit definition for DAC_DHR12R2 register ******************/
3016 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3018 /***************** Bit definition for DAC_DHR12L2 register ******************/
3019 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3021 /****************** Bit definition for DAC_DHR8R2 register ******************/
3022 #define DAC_DHR8R2_DACC2DHR 0xFFU
3024 /***************** Bit definition for DAC_DHR12RD register ******************/
3025 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3026 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3028 /***************** Bit definition for DAC_DHR12LD register ******************/
3029 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3030 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3032 /****************** Bit definition for DAC_DHR8RD register ******************/
3033 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3034 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3036 /******************* Bit definition for DAC_DOR1 register *******************/
3037 #define DAC_DOR1_DACC1DOR 0x0FFFU
3039 /******************* Bit definition for DAC_DOR2 register *******************/
3040 #define DAC_DOR2_DACC2DOR 0x0FFFU
3042 /******************** Bit definition for DAC_SR register ********************/
3043 #define DAC_SR_DMAUDR1 0x00002000U
3044 #define DAC_SR_DMAUDR2 0x20000000U
3046 /******************************************************************************/
3047 /* */
3048 /* Debug MCU */
3049 /* */
3050 /******************************************************************************/
3051 
3052 /******************************************************************************/
3053 /* */
3054 /* DCMI */
3055 /* */
3056 /******************************************************************************/
3057 /******************** Bits definition for DCMI_CR register ******************/
3058 #define DCMI_CR_CAPTURE 0x00000001U
3059 #define DCMI_CR_CM 0x00000002U
3060 #define DCMI_CR_CROP 0x00000004U
3061 #define DCMI_CR_JPEG 0x00000008U
3062 #define DCMI_CR_ESS 0x00000010U
3063 #define DCMI_CR_PCKPOL 0x00000020U
3064 #define DCMI_CR_HSPOL 0x00000040U
3065 #define DCMI_CR_VSPOL 0x00000080U
3066 #define DCMI_CR_FCRC_0 0x00000100U
3067 #define DCMI_CR_FCRC_1 0x00000200U
3068 #define DCMI_CR_EDM_0 0x00000400U
3069 #define DCMI_CR_EDM_1 0x00000800U
3070 #define DCMI_CR_OUTEN 0x00002000U
3071 #define DCMI_CR_ENABLE 0x00004000U
3072 #define DCMI_CR_BSM_0 0x00010000U
3073 #define DCMI_CR_BSM_1 0x00020000U
3074 #define DCMI_CR_OEBS 0x00040000U
3075 #define DCMI_CR_LSM 0x00080000U
3076 #define DCMI_CR_OELS 0x00100000U
3077 
3078 /******************** Bits definition for DCMI_SR register ******************/
3079 #define DCMI_SR_HSYNC 0x00000001U
3080 #define DCMI_SR_VSYNC 0x00000002U
3081 #define DCMI_SR_FNE 0x00000004U
3082 
3083 /******************** Bits definition for DCMI_RIS register ****************/
3084 #define DCMI_RIS_FRAME_RIS 0x00000001U
3085 #define DCMI_RIS_OVR_RIS 0x00000002U
3086 #define DCMI_RIS_ERR_RIS 0x00000004U
3087 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3088 #define DCMI_RIS_LINE_RIS 0x00000010U
3089 /* Legacy defines */
3090 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3091 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
3092 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3093 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3094 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3095 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3096 
3097 /******************** Bits definition for DCMI_IER register *****************/
3098 #define DCMI_IER_FRAME_IE 0x00000001U
3099 #define DCMI_IER_OVR_IE 0x00000002U
3100 #define DCMI_IER_ERR_IE 0x00000004U
3101 #define DCMI_IER_VSYNC_IE 0x00000008U
3102 #define DCMI_IER_LINE_IE 0x00000010U
3103 /* Legacy defines */
3104 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3105 
3106 /******************** Bits definition for DCMI_MIS register *****************/
3107 #define DCMI_MIS_FRAME_MIS 0x00000001U
3108 #define DCMI_MIS_OVR_MIS 0x00000002U
3109 #define DCMI_MIS_ERR_MIS 0x00000004U
3110 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3111 #define DCMI_MIS_LINE_MIS 0x00000010U
3112 
3113 /* Legacy defines */
3114 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3115 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3116 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3117 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3118 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3119 
3120 /******************** Bits definition for DCMI_ICR register *****************/
3121 #define DCMI_ICR_FRAME_ISC 0x00000001U
3122 #define DCMI_ICR_OVR_ISC 0x00000002U
3123 #define DCMI_ICR_ERR_ISC 0x00000004U
3124 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3125 #define DCMI_ICR_LINE_ISC 0x00000010U
3126 
3127 /* Legacy defines */
3128 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3129 
3130 /******************** Bits definition for DCMI_ESCR register ******************/
3131 #define DCMI_ESCR_FSC 0x000000FFU
3132 #define DCMI_ESCR_LSC 0x0000FF00U
3133 #define DCMI_ESCR_LEC 0x00FF0000U
3134 #define DCMI_ESCR_FEC 0xFF000000U
3135 
3136 /******************** Bits definition for DCMI_ESUR register ******************/
3137 #define DCMI_ESUR_FSU 0x000000FFU
3138 #define DCMI_ESUR_LSU 0x0000FF00U
3139 #define DCMI_ESUR_LEU 0x00FF0000U
3140 #define DCMI_ESUR_FEU 0xFF000000U
3141 
3142 /******************** Bits definition for DCMI_CWSTRT register ******************/
3143 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3144 #define DCMI_CWSTRT_VST 0x1FFF0000U
3145 
3146 /******************** Bits definition for DCMI_CWSIZE register ******************/
3147 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3148 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3149 
3150 /******************** Bits definition for DCMI_DR register ******************/
3151 #define DCMI_DR_BYTE0 0x000000FFU
3152 #define DCMI_DR_BYTE1 0x0000FF00U
3153 #define DCMI_DR_BYTE2 0x00FF0000U
3154 #define DCMI_DR_BYTE3 0xFF000000U
3155 
3156 /******************************************************************************/
3157 /* */
3158 /* DMA Controller */
3159 /* */
3160 /******************************************************************************/
3161 /******************** Bits definition for DMA_SxCR register *****************/
3162 #define DMA_SxCR_CHSEL 0x0E000000U
3163 #define DMA_SxCR_CHSEL_0 0x02000000U
3164 #define DMA_SxCR_CHSEL_1 0x04000000U
3165 #define DMA_SxCR_CHSEL_2 0x08000000U
3166 #define DMA_SxCR_MBURST 0x01800000U
3167 #define DMA_SxCR_MBURST_0 0x00800000U
3168 #define DMA_SxCR_MBURST_1 0x01000000U
3169 #define DMA_SxCR_PBURST 0x00600000U
3170 #define DMA_SxCR_PBURST_0 0x00200000U
3171 #define DMA_SxCR_PBURST_1 0x00400000U
3172 #define DMA_SxCR_CT 0x00080000U
3173 #define DMA_SxCR_DBM 0x00040000U
3174 #define DMA_SxCR_PL 0x00030000U
3175 #define DMA_SxCR_PL_0 0x00010000U
3176 #define DMA_SxCR_PL_1 0x00020000U
3177 #define DMA_SxCR_PINCOS 0x00008000U
3178 #define DMA_SxCR_MSIZE 0x00006000U
3179 #define DMA_SxCR_MSIZE_0 0x00002000U
3180 #define DMA_SxCR_MSIZE_1 0x00004000U
3181 #define DMA_SxCR_PSIZE 0x00001800U
3182 #define DMA_SxCR_PSIZE_0 0x00000800U
3183 #define DMA_SxCR_PSIZE_1 0x00001000U
3184 #define DMA_SxCR_MINC 0x00000400U
3185 #define DMA_SxCR_PINC 0x00000200U
3186 #define DMA_SxCR_CIRC 0x00000100U
3187 #define DMA_SxCR_DIR 0x000000C0U
3188 #define DMA_SxCR_DIR_0 0x00000040U
3189 #define DMA_SxCR_DIR_1 0x00000080U
3190 #define DMA_SxCR_PFCTRL 0x00000020U
3191 #define DMA_SxCR_TCIE 0x00000010U
3192 #define DMA_SxCR_HTIE 0x00000008U
3193 #define DMA_SxCR_TEIE 0x00000004U
3194 #define DMA_SxCR_DMEIE 0x00000002U
3195 #define DMA_SxCR_EN 0x00000001U
3196 
3197 /* Legacy defines */
3198 #define DMA_SxCR_ACK 0x00100000U
3199 
3200 /******************** Bits definition for DMA_SxCNDTR register **************/
3201 #define DMA_SxNDT 0x0000FFFFU
3202 #define DMA_SxNDT_0 0x00000001U
3203 #define DMA_SxNDT_1 0x00000002U
3204 #define DMA_SxNDT_2 0x00000004U
3205 #define DMA_SxNDT_3 0x00000008U
3206 #define DMA_SxNDT_4 0x00000010U
3207 #define DMA_SxNDT_5 0x00000020U
3208 #define DMA_SxNDT_6 0x00000040U
3209 #define DMA_SxNDT_7 0x00000080U
3210 #define DMA_SxNDT_8 0x00000100U
3211 #define DMA_SxNDT_9 0x00000200U
3212 #define DMA_SxNDT_10 0x00000400U
3213 #define DMA_SxNDT_11 0x00000800U
3214 #define DMA_SxNDT_12 0x00001000U
3215 #define DMA_SxNDT_13 0x00002000U
3216 #define DMA_SxNDT_14 0x00004000U
3217 #define DMA_SxNDT_15 0x00008000U
3218 
3219 /******************** Bits definition for DMA_SxFCR register ****************/
3220 #define DMA_SxFCR_FEIE 0x00000080U
3221 #define DMA_SxFCR_FS 0x00000038U
3222 #define DMA_SxFCR_FS_0 0x00000008U
3223 #define DMA_SxFCR_FS_1 0x00000010U
3224 #define DMA_SxFCR_FS_2 0x00000020U
3225 #define DMA_SxFCR_DMDIS 0x00000004U
3226 #define DMA_SxFCR_FTH 0x00000003U
3227 #define DMA_SxFCR_FTH_0 0x00000001U
3228 #define DMA_SxFCR_FTH_1 0x00000002U
3229 
3230 /******************** Bits definition for DMA_LISR register *****************/
3231 #define DMA_LISR_TCIF3 0x08000000U
3232 #define DMA_LISR_HTIF3 0x04000000U
3233 #define DMA_LISR_TEIF3 0x02000000U
3234 #define DMA_LISR_DMEIF3 0x01000000U
3235 #define DMA_LISR_FEIF3 0x00400000U
3236 #define DMA_LISR_TCIF2 0x00200000U
3237 #define DMA_LISR_HTIF2 0x00100000U
3238 #define DMA_LISR_TEIF2 0x00080000U
3239 #define DMA_LISR_DMEIF2 0x00040000U
3240 #define DMA_LISR_FEIF2 0x00010000U
3241 #define DMA_LISR_TCIF1 0x00000800U
3242 #define DMA_LISR_HTIF1 0x00000400U
3243 #define DMA_LISR_TEIF1 0x00000200U
3244 #define DMA_LISR_DMEIF1 0x00000100U
3245 #define DMA_LISR_FEIF1 0x00000040U
3246 #define DMA_LISR_TCIF0 0x00000020U
3247 #define DMA_LISR_HTIF0 0x00000010U
3248 #define DMA_LISR_TEIF0 0x00000008U
3249 #define DMA_LISR_DMEIF0 0x00000004U
3250 #define DMA_LISR_FEIF0 0x00000001U
3251 
3252 /******************** Bits definition for DMA_HISR register *****************/
3253 #define DMA_HISR_TCIF7 0x08000000U
3254 #define DMA_HISR_HTIF7 0x04000000U
3255 #define DMA_HISR_TEIF7 0x02000000U
3256 #define DMA_HISR_DMEIF7 0x01000000U
3257 #define DMA_HISR_FEIF7 0x00400000U
3258 #define DMA_HISR_TCIF6 0x00200000U
3259 #define DMA_HISR_HTIF6 0x00100000U
3260 #define DMA_HISR_TEIF6 0x00080000U
3261 #define DMA_HISR_DMEIF6 0x00040000U
3262 #define DMA_HISR_FEIF6 0x00010000U
3263 #define DMA_HISR_TCIF5 0x00000800U
3264 #define DMA_HISR_HTIF5 0x00000400U
3265 #define DMA_HISR_TEIF5 0x00000200U
3266 #define DMA_HISR_DMEIF5 0x00000100U
3267 #define DMA_HISR_FEIF5 0x00000040U
3268 #define DMA_HISR_TCIF4 0x00000020U
3269 #define DMA_HISR_HTIF4 0x00000010U
3270 #define DMA_HISR_TEIF4 0x00000008U
3271 #define DMA_HISR_DMEIF4 0x00000004U
3272 #define DMA_HISR_FEIF4 0x00000001U
3273 
3274 /******************** Bits definition for DMA_LIFCR register ****************/
3275 #define DMA_LIFCR_CTCIF3 0x08000000U
3276 #define DMA_LIFCR_CHTIF3 0x04000000U
3277 #define DMA_LIFCR_CTEIF3 0x02000000U
3278 #define DMA_LIFCR_CDMEIF3 0x01000000U
3279 #define DMA_LIFCR_CFEIF3 0x00400000U
3280 #define DMA_LIFCR_CTCIF2 0x00200000U
3281 #define DMA_LIFCR_CHTIF2 0x00100000U
3282 #define DMA_LIFCR_CTEIF2 0x00080000U
3283 #define DMA_LIFCR_CDMEIF2 0x00040000U
3284 #define DMA_LIFCR_CFEIF2 0x00010000U
3285 #define DMA_LIFCR_CTCIF1 0x00000800U
3286 #define DMA_LIFCR_CHTIF1 0x00000400U
3287 #define DMA_LIFCR_CTEIF1 0x00000200U
3288 #define DMA_LIFCR_CDMEIF1 0x00000100U
3289 #define DMA_LIFCR_CFEIF1 0x00000040U
3290 #define DMA_LIFCR_CTCIF0 0x00000020U
3291 #define DMA_LIFCR_CHTIF0 0x00000010U
3292 #define DMA_LIFCR_CTEIF0 0x00000008U
3293 #define DMA_LIFCR_CDMEIF0 0x00000004U
3294 #define DMA_LIFCR_CFEIF0 0x00000001U
3295 
3296 /******************** Bits definition for DMA_HIFCR register ****************/
3297 #define DMA_HIFCR_CTCIF7 0x08000000U
3298 #define DMA_HIFCR_CHTIF7 0x04000000U
3299 #define DMA_HIFCR_CTEIF7 0x02000000U
3300 #define DMA_HIFCR_CDMEIF7 0x01000000U
3301 #define DMA_HIFCR_CFEIF7 0x00400000U
3302 #define DMA_HIFCR_CTCIF6 0x00200000U
3303 #define DMA_HIFCR_CHTIF6 0x00100000U
3304 #define DMA_HIFCR_CTEIF6 0x00080000U
3305 #define DMA_HIFCR_CDMEIF6 0x00040000U
3306 #define DMA_HIFCR_CFEIF6 0x00010000U
3307 #define DMA_HIFCR_CTCIF5 0x00000800U
3308 #define DMA_HIFCR_CHTIF5 0x00000400U
3309 #define DMA_HIFCR_CTEIF5 0x00000200U
3310 #define DMA_HIFCR_CDMEIF5 0x00000100U
3311 #define DMA_HIFCR_CFEIF5 0x00000040U
3312 #define DMA_HIFCR_CTCIF4 0x00000020U
3313 #define DMA_HIFCR_CHTIF4 0x00000010U
3314 #define DMA_HIFCR_CTEIF4 0x00000008U
3315 #define DMA_HIFCR_CDMEIF4 0x00000004U
3316 #define DMA_HIFCR_CFEIF4 0x00000001U
3317 
3318 
3319 /******************************************************************************/
3320 /* */
3321 /* External Interrupt/Event Controller */
3322 /* */
3323 /******************************************************************************/
3324 /******************* Bit definition for EXTI_IMR register *******************/
3325 #define EXTI_IMR_MR0 0x00000001U
3326 #define EXTI_IMR_MR1 0x00000002U
3327 #define EXTI_IMR_MR2 0x00000004U
3328 #define EXTI_IMR_MR3 0x00000008U
3329 #define EXTI_IMR_MR4 0x00000010U
3330 #define EXTI_IMR_MR5 0x00000020U
3331 #define EXTI_IMR_MR6 0x00000040U
3332 #define EXTI_IMR_MR7 0x00000080U
3333 #define EXTI_IMR_MR8 0x00000100U
3334 #define EXTI_IMR_MR9 0x00000200U
3335 #define EXTI_IMR_MR10 0x00000400U
3336 #define EXTI_IMR_MR11 0x00000800U
3337 #define EXTI_IMR_MR12 0x00001000U
3338 #define EXTI_IMR_MR13 0x00002000U
3339 #define EXTI_IMR_MR14 0x00004000U
3340 #define EXTI_IMR_MR15 0x00008000U
3341 #define EXTI_IMR_MR16 0x00010000U
3342 #define EXTI_IMR_MR17 0x00020000U
3343 #define EXTI_IMR_MR18 0x00040000U
3344 #define EXTI_IMR_MR19 0x00080000U
3345 #define EXTI_IMR_MR20 0x00100000U
3346 #define EXTI_IMR_MR21 0x00200000U
3347 #define EXTI_IMR_MR22 0x00400000U
3349 /******************* Bit definition for EXTI_EMR register *******************/
3350 #define EXTI_EMR_MR0 0x00000001U
3351 #define EXTI_EMR_MR1 0x00000002U
3352 #define EXTI_EMR_MR2 0x00000004U
3353 #define EXTI_EMR_MR3 0x00000008U
3354 #define EXTI_EMR_MR4 0x00000010U
3355 #define EXTI_EMR_MR5 0x00000020U
3356 #define EXTI_EMR_MR6 0x00000040U
3357 #define EXTI_EMR_MR7 0x00000080U
3358 #define EXTI_EMR_MR8 0x00000100U
3359 #define EXTI_EMR_MR9 0x00000200U
3360 #define EXTI_EMR_MR10 0x00000400U
3361 #define EXTI_EMR_MR11 0x00000800U
3362 #define EXTI_EMR_MR12 0x00001000U
3363 #define EXTI_EMR_MR13 0x00002000U
3364 #define EXTI_EMR_MR14 0x00004000U
3365 #define EXTI_EMR_MR15 0x00008000U
3366 #define EXTI_EMR_MR16 0x00010000U
3367 #define EXTI_EMR_MR17 0x00020000U
3368 #define EXTI_EMR_MR18 0x00040000U
3369 #define EXTI_EMR_MR19 0x00080000U
3370 #define EXTI_EMR_MR20 0x00100000U
3371 #define EXTI_EMR_MR21 0x00200000U
3372 #define EXTI_EMR_MR22 0x00400000U
3374 /****************** Bit definition for EXTI_RTSR register *******************/
3375 #define EXTI_RTSR_TR0 0x00000001U
3376 #define EXTI_RTSR_TR1 0x00000002U
3377 #define EXTI_RTSR_TR2 0x00000004U
3378 #define EXTI_RTSR_TR3 0x00000008U
3379 #define EXTI_RTSR_TR4 0x00000010U
3380 #define EXTI_RTSR_TR5 0x00000020U
3381 #define EXTI_RTSR_TR6 0x00000040U
3382 #define EXTI_RTSR_TR7 0x00000080U
3383 #define EXTI_RTSR_TR8 0x00000100U
3384 #define EXTI_RTSR_TR9 0x00000200U
3385 #define EXTI_RTSR_TR10 0x00000400U
3386 #define EXTI_RTSR_TR11 0x00000800U
3387 #define EXTI_RTSR_TR12 0x00001000U
3388 #define EXTI_RTSR_TR13 0x00002000U
3389 #define EXTI_RTSR_TR14 0x00004000U
3390 #define EXTI_RTSR_TR15 0x00008000U
3391 #define EXTI_RTSR_TR16 0x00010000U
3392 #define EXTI_RTSR_TR17 0x00020000U
3393 #define EXTI_RTSR_TR18 0x00040000U
3394 #define EXTI_RTSR_TR19 0x00080000U
3395 #define EXTI_RTSR_TR20 0x00100000U
3396 #define EXTI_RTSR_TR21 0x00200000U
3397 #define EXTI_RTSR_TR22 0x00400000U
3399 /****************** Bit definition for EXTI_FTSR register *******************/
3400 #define EXTI_FTSR_TR0 0x00000001U
3401 #define EXTI_FTSR_TR1 0x00000002U
3402 #define EXTI_FTSR_TR2 0x00000004U
3403 #define EXTI_FTSR_TR3 0x00000008U
3404 #define EXTI_FTSR_TR4 0x00000010U
3405 #define EXTI_FTSR_TR5 0x00000020U
3406 #define EXTI_FTSR_TR6 0x00000040U
3407 #define EXTI_FTSR_TR7 0x00000080U
3408 #define EXTI_FTSR_TR8 0x00000100U
3409 #define EXTI_FTSR_TR9 0x00000200U
3410 #define EXTI_FTSR_TR10 0x00000400U
3411 #define EXTI_FTSR_TR11 0x00000800U
3412 #define EXTI_FTSR_TR12 0x00001000U
3413 #define EXTI_FTSR_TR13 0x00002000U
3414 #define EXTI_FTSR_TR14 0x00004000U
3415 #define EXTI_FTSR_TR15 0x00008000U
3416 #define EXTI_FTSR_TR16 0x00010000U
3417 #define EXTI_FTSR_TR17 0x00020000U
3418 #define EXTI_FTSR_TR18 0x00040000U
3419 #define EXTI_FTSR_TR19 0x00080000U
3420 #define EXTI_FTSR_TR20 0x00100000U
3421 #define EXTI_FTSR_TR21 0x00200000U
3422 #define EXTI_FTSR_TR22 0x00400000U
3424 /****************** Bit definition for EXTI_SWIER register ******************/
3425 #define EXTI_SWIER_SWIER0 0x00000001U
3426 #define EXTI_SWIER_SWIER1 0x00000002U
3427 #define EXTI_SWIER_SWIER2 0x00000004U
3428 #define EXTI_SWIER_SWIER3 0x00000008U
3429 #define EXTI_SWIER_SWIER4 0x00000010U
3430 #define EXTI_SWIER_SWIER5 0x00000020U
3431 #define EXTI_SWIER_SWIER6 0x00000040U
3432 #define EXTI_SWIER_SWIER7 0x00000080U
3433 #define EXTI_SWIER_SWIER8 0x00000100U
3434 #define EXTI_SWIER_SWIER9 0x00000200U
3435 #define EXTI_SWIER_SWIER10 0x00000400U
3436 #define EXTI_SWIER_SWIER11 0x00000800U
3437 #define EXTI_SWIER_SWIER12 0x00001000U
3438 #define EXTI_SWIER_SWIER13 0x00002000U
3439 #define EXTI_SWIER_SWIER14 0x00004000U
3440 #define EXTI_SWIER_SWIER15 0x00008000U
3441 #define EXTI_SWIER_SWIER16 0x00010000U
3442 #define EXTI_SWIER_SWIER17 0x00020000U
3443 #define EXTI_SWIER_SWIER18 0x00040000U
3444 #define EXTI_SWIER_SWIER19 0x00080000U
3445 #define EXTI_SWIER_SWIER20 0x00100000U
3446 #define EXTI_SWIER_SWIER21 0x00200000U
3447 #define EXTI_SWIER_SWIER22 0x00400000U
3449 /******************* Bit definition for EXTI_PR register ********************/
3450 #define EXTI_PR_PR0 0x00000001U
3451 #define EXTI_PR_PR1 0x00000002U
3452 #define EXTI_PR_PR2 0x00000004U
3453 #define EXTI_PR_PR3 0x00000008U
3454 #define EXTI_PR_PR4 0x00000010U
3455 #define EXTI_PR_PR5 0x00000020U
3456 #define EXTI_PR_PR6 0x00000040U
3457 #define EXTI_PR_PR7 0x00000080U
3458 #define EXTI_PR_PR8 0x00000100U
3459 #define EXTI_PR_PR9 0x00000200U
3460 #define EXTI_PR_PR10 0x00000400U
3461 #define EXTI_PR_PR11 0x00000800U
3462 #define EXTI_PR_PR12 0x00001000U
3463 #define EXTI_PR_PR13 0x00002000U
3464 #define EXTI_PR_PR14 0x00004000U
3465 #define EXTI_PR_PR15 0x00008000U
3466 #define EXTI_PR_PR16 0x00010000U
3467 #define EXTI_PR_PR17 0x00020000U
3468 #define EXTI_PR_PR18 0x00040000U
3469 #define EXTI_PR_PR19 0x00080000U
3470 #define EXTI_PR_PR20 0x00100000U
3471 #define EXTI_PR_PR21 0x00200000U
3472 #define EXTI_PR_PR22 0x00400000U
3474 /******************************************************************************/
3475 /* */
3476 /* FLASH */
3477 /* */
3478 /******************************************************************************/
3479 /******************* Bits definition for FLASH_ACR register *****************/
3480 #define FLASH_ACR_LATENCY 0x0000000FU
3481 #define FLASH_ACR_LATENCY_0WS 0x00000000U
3482 #define FLASH_ACR_LATENCY_1WS 0x00000001U
3483 #define FLASH_ACR_LATENCY_2WS 0x00000002U
3484 #define FLASH_ACR_LATENCY_3WS 0x00000003U
3485 #define FLASH_ACR_LATENCY_4WS 0x00000004U
3486 #define FLASH_ACR_LATENCY_5WS 0x00000005U
3487 #define FLASH_ACR_LATENCY_6WS 0x00000006U
3488 #define FLASH_ACR_LATENCY_7WS 0x00000007U
3489 #define FLASH_ACR_LATENCY_8WS 0x00000008U
3490 #define FLASH_ACR_LATENCY_9WS 0x00000009U
3491 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
3492 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
3493 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
3494 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
3495 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
3496 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
3497 #define FLASH_ACR_PRFTEN 0x00000100U
3498 #define FLASH_ACR_ICEN 0x00000200U
3499 #define FLASH_ACR_DCEN 0x00000400U
3500 #define FLASH_ACR_ICRST 0x00000800U
3501 #define FLASH_ACR_DCRST 0x00001000U
3502 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
3503 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
3504 
3505 /******************* Bits definition for FLASH_SR register ******************/
3506 #define FLASH_SR_EOP 0x00000001U
3507 #define FLASH_SR_SOP 0x00000002U
3508 #define FLASH_SR_WRPERR 0x00000010U
3509 #define FLASH_SR_PGAERR 0x00000020U
3510 #define FLASH_SR_PGPERR 0x00000040U
3511 #define FLASH_SR_PGSERR 0x00000080U
3512 #define FLASH_SR_BSY 0x00010000U
3513 
3514 /******************* Bits definition for FLASH_CR register ******************/
3515 #define FLASH_CR_PG 0x00000001U
3516 #define FLASH_CR_SER 0x00000002U
3517 #define FLASH_CR_MER 0x00000004U
3518 #define FLASH_CR_MER1 FLASH_CR_MER
3519 #define FLASH_CR_SNB 0x000000F8U
3520 #define FLASH_CR_SNB_0 0x00000008U
3521 #define FLASH_CR_SNB_1 0x00000010U
3522 #define FLASH_CR_SNB_2 0x00000020U
3523 #define FLASH_CR_SNB_3 0x00000040U
3524 #define FLASH_CR_SNB_4 0x00000080U
3525 #define FLASH_CR_PSIZE 0x00000300U
3526 #define FLASH_CR_PSIZE_0 0x00000100U
3527 #define FLASH_CR_PSIZE_1 0x00000200U
3528 #define FLASH_CR_MER2 0x00008000U
3529 #define FLASH_CR_STRT 0x00010000U
3530 #define FLASH_CR_EOPIE 0x01000000U
3531 #define FLASH_CR_LOCK 0x80000000U
3532 
3533 /******************* Bits definition for FLASH_OPTCR register ***************/
3534 #define FLASH_OPTCR_OPTLOCK 0x00000001U
3535 #define FLASH_OPTCR_OPTSTRT 0x00000002U
3536 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
3537 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
3538 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
3539 #define FLASH_OPTCR_BFB2 0x00000010U
3540 #define FLASH_OPTCR_WDG_SW 0x00000020U
3541 #define FLASH_OPTCR_nRST_STOP 0x00000040U
3542 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
3543 #define FLASH_OPTCR_RDP 0x0000FF00U
3544 #define FLASH_OPTCR_RDP_0 0x00000100U
3545 #define FLASH_OPTCR_RDP_1 0x00000200U
3546 #define FLASH_OPTCR_RDP_2 0x00000400U
3547 #define FLASH_OPTCR_RDP_3 0x00000800U
3548 #define FLASH_OPTCR_RDP_4 0x00001000U
3549 #define FLASH_OPTCR_RDP_5 0x00002000U
3550 #define FLASH_OPTCR_RDP_6 0x00004000U
3551 #define FLASH_OPTCR_RDP_7 0x00008000U
3552 #define FLASH_OPTCR_nWRP 0x0FFF0000U
3553 #define FLASH_OPTCR_nWRP_0 0x00010000U
3554 #define FLASH_OPTCR_nWRP_1 0x00020000U
3555 #define FLASH_OPTCR_nWRP_2 0x00040000U
3556 #define FLASH_OPTCR_nWRP_3 0x00080000U
3557 #define FLASH_OPTCR_nWRP_4 0x00100000U
3558 #define FLASH_OPTCR_nWRP_5 0x00200000U
3559 #define FLASH_OPTCR_nWRP_6 0x00400000U
3560 #define FLASH_OPTCR_nWRP_7 0x00800000U
3561 #define FLASH_OPTCR_nWRP_8 0x01000000U
3562 #define FLASH_OPTCR_nWRP_9 0x02000000U
3563 #define FLASH_OPTCR_nWRP_10 0x04000000U
3564 #define FLASH_OPTCR_nWRP_11 0x08000000U
3565 #define FLASH_OPTCR_DB1M 0x40000000U
3566 #define FLASH_OPTCR_SPRMOD 0x80000000U
3567 
3568 /****************** Bits definition for FLASH_OPTCR1 register ***************/
3569 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
3570 #define FLASH_OPTCR1_nWRP_0 0x00010000U
3571 #define FLASH_OPTCR1_nWRP_1 0x00020000U
3572 #define FLASH_OPTCR1_nWRP_2 0x00040000U
3573 #define FLASH_OPTCR1_nWRP_3 0x00080000U
3574 #define FLASH_OPTCR1_nWRP_4 0x00100000U
3575 #define FLASH_OPTCR1_nWRP_5 0x00200000U
3576 #define FLASH_OPTCR1_nWRP_6 0x00400000U
3577 #define FLASH_OPTCR1_nWRP_7 0x00800000U
3578 #define FLASH_OPTCR1_nWRP_8 0x01000000U
3579 #define FLASH_OPTCR1_nWRP_9 0x02000000U
3580 #define FLASH_OPTCR1_nWRP_10 0x04000000U
3581 #define FLASH_OPTCR1_nWRP_11 0x08000000U
3582 
3583 /******************************************************************************/
3584 /* */
3585 /* Flexible Memory Controller */
3586 /* */
3587 /******************************************************************************/
3588 /****************** Bit definition for FMC_BCR1 register *******************/
3589 #define FMC_BCR1_MBKEN 0x00000001U
3590 #define FMC_BCR1_MUXEN 0x00000002U
3592 #define FMC_BCR1_MTYP 0x0000000CU
3593 #define FMC_BCR1_MTYP_0 0x00000004U
3594 #define FMC_BCR1_MTYP_1 0x00000008U
3596 #define FMC_BCR1_MWID 0x00000030U
3597 #define FMC_BCR1_MWID_0 0x00000010U
3598 #define FMC_BCR1_MWID_1 0x00000020U
3600 #define FMC_BCR1_FACCEN 0x00000040U
3601 #define FMC_BCR1_BURSTEN 0x00000100U
3602 #define FMC_BCR1_WAITPOL 0x00000200U
3603 #define FMC_BCR1_WAITCFG 0x00000800U
3604 #define FMC_BCR1_WREN 0x00001000U
3605 #define FMC_BCR1_WAITEN 0x00002000U
3606 #define FMC_BCR1_EXTMOD 0x00004000U
3607 #define FMC_BCR1_ASYNCWAIT 0x00008000U
3608 #define FMC_BCR1_CPSIZE 0x00070000U
3609 #define FMC_BCR1_CPSIZE_0 0x00010000U
3610 #define FMC_BCR1_CPSIZE_1 0x00020000U
3611 #define FMC_BCR1_CPSIZE_2 0x00040000U
3612 #define FMC_BCR1_CBURSTRW 0x00080000U
3613 #define FMC_BCR1_CCLKEN 0x00100000U
3614 #define FMC_BCR1_WFDIS 0x00200000U
3616 /****************** Bit definition for FMC_BCR2 register *******************/
3617 #define FMC_BCR2_MBKEN 0x00000001U
3618 #define FMC_BCR2_MUXEN 0x00000002U
3620 #define FMC_BCR2_MTYP 0x0000000CU
3621 #define FMC_BCR2_MTYP_0 0x00000004U
3622 #define FMC_BCR2_MTYP_1 0x00000008U
3624 #define FMC_BCR2_MWID 0x00000030U
3625 #define FMC_BCR2_MWID_0 0x00000010U
3626 #define FMC_BCR2_MWID_1 0x00000020U
3628 #define FMC_BCR2_FACCEN 0x00000040U
3629 #define FMC_BCR2_BURSTEN 0x00000100U
3630 #define FMC_BCR2_WAITPOL 0x00000200U
3631 #define FMC_BCR2_WAITCFG 0x00000800U
3632 #define FMC_BCR2_WREN 0x00001000U
3633 #define FMC_BCR2_WAITEN 0x00002000U
3634 #define FMC_BCR2_EXTMOD 0x00004000U
3635 #define FMC_BCR2_ASYNCWAIT 0x00008000U
3636 #define FMC_BCR2_CBURSTRW 0x00080000U
3638 /****************** Bit definition for FMC_BCR3 register *******************/
3639 #define FMC_BCR3_MBKEN 0x00000001U
3640 #define FMC_BCR3_MUXEN 0x00000002U
3642 #define FMC_BCR3_MTYP 0x0000000CU
3643 #define FMC_BCR3_MTYP_0 0x00000004U
3644 #define FMC_BCR3_MTYP_1 0x00000008U
3646 #define FMC_BCR3_MWID 0x00000030U
3647 #define FMC_BCR3_MWID_0 0x00000010U
3648 #define FMC_BCR3_MWID_1 0x00000020U
3650 #define FMC_BCR3_FACCEN 0x00000040U
3651 #define FMC_BCR3_BURSTEN 0x00000100U
3652 #define FMC_BCR3_WAITPOL 0x00000200U
3653 #define FMC_BCR3_WAITCFG 0x00000800U
3654 #define FMC_BCR3_WREN 0x00001000U
3655 #define FMC_BCR3_WAITEN 0x00002000U
3656 #define FMC_BCR3_EXTMOD 0x00004000U
3657 #define FMC_BCR3_ASYNCWAIT 0x00008000U
3658 #define FMC_BCR3_CBURSTRW 0x00080000U
3660 /****************** Bit definition for FMC_BCR4 register *******************/
3661 #define FMC_BCR4_MBKEN 0x00000001U
3662 #define FMC_BCR4_MUXEN 0x00000002U
3664 #define FMC_BCR4_MTYP 0x0000000CU
3665 #define FMC_BCR4_MTYP_0 0x00000004U
3666 #define FMC_BCR4_MTYP_1 0x00000008U
3668 #define FMC_BCR4_MWID 0x00000030U
3669 #define FMC_BCR4_MWID_0 0x00000010U
3670 #define FMC_BCR4_MWID_1 0x00000020U
3672 #define FMC_BCR4_FACCEN 0x00000040U
3673 #define FMC_BCR4_BURSTEN 0x00000100U
3674 #define FMC_BCR4_WAITPOL 0x00000200U
3675 #define FMC_BCR4_WAITCFG 0x00000800U
3676 #define FMC_BCR4_WREN 0x00001000U
3677 #define FMC_BCR4_WAITEN 0x00002000U
3678 #define FMC_BCR4_EXTMOD 0x00004000U
3679 #define FMC_BCR4_ASYNCWAIT 0x00008000U
3680 #define FMC_BCR4_CBURSTRW 0x00080000U
3682 /****************** Bit definition for FMC_BTR1 register ******************/
3683 #define FMC_BTR1_ADDSET 0x0000000FU
3684 #define FMC_BTR1_ADDSET_0 0x00000001U
3685 #define FMC_BTR1_ADDSET_1 0x00000002U
3686 #define FMC_BTR1_ADDSET_2 0x00000004U
3687 #define FMC_BTR1_ADDSET_3 0x00000008U
3689 #define FMC_BTR1_ADDHLD 0x000000F0U
3690 #define FMC_BTR1_ADDHLD_0 0x00000010U
3691 #define FMC_BTR1_ADDHLD_1 0x00000020U
3692 #define FMC_BTR1_ADDHLD_2 0x00000040U
3693 #define FMC_BTR1_ADDHLD_3 0x00000080U
3695 #define FMC_BTR1_DATAST 0x0000FF00U
3696 #define FMC_BTR1_DATAST_0 0x00000100U
3697 #define FMC_BTR1_DATAST_1 0x00000200U
3698 #define FMC_BTR1_DATAST_2 0x00000400U
3699 #define FMC_BTR1_DATAST_3 0x00000800U
3700 #define FMC_BTR1_DATAST_4 0x00001000U
3701 #define FMC_BTR1_DATAST_5 0x00002000U
3702 #define FMC_BTR1_DATAST_6 0x00004000U
3703 #define FMC_BTR1_DATAST_7 0x00008000U
3705 #define FMC_BTR1_BUSTURN 0x000F0000U
3706 #define FMC_BTR1_BUSTURN_0 0x00010000U
3707 #define FMC_BTR1_BUSTURN_1 0x00020000U
3708 #define FMC_BTR1_BUSTURN_2 0x00040000U
3709 #define FMC_BTR1_BUSTURN_3 0x00080000U
3711 #define FMC_BTR1_CLKDIV 0x00F00000U
3712 #define FMC_BTR1_CLKDIV_0 0x00100000U
3713 #define FMC_BTR1_CLKDIV_1 0x00200000U
3714 #define FMC_BTR1_CLKDIV_2 0x00400000U
3715 #define FMC_BTR1_CLKDIV_3 0x00800000U
3717 #define FMC_BTR1_DATLAT 0x0F000000U
3718 #define FMC_BTR1_DATLAT_0 0x01000000U
3719 #define FMC_BTR1_DATLAT_1 0x02000000U
3720 #define FMC_BTR1_DATLAT_2 0x04000000U
3721 #define FMC_BTR1_DATLAT_3 0x08000000U
3723 #define FMC_BTR1_ACCMOD 0x30000000U
3724 #define FMC_BTR1_ACCMOD_0 0x10000000U
3725 #define FMC_BTR1_ACCMOD_1 0x20000000U
3727 /****************** Bit definition for FMC_BTR2 register *******************/
3728 #define FMC_BTR2_ADDSET 0x0000000FU
3729 #define FMC_BTR2_ADDSET_0 0x00000001U
3730 #define FMC_BTR2_ADDSET_1 0x00000002U
3731 #define FMC_BTR2_ADDSET_2 0x00000004U
3732 #define FMC_BTR2_ADDSET_3 0x00000008U
3734 #define FMC_BTR2_ADDHLD 0x000000F0U
3735 #define FMC_BTR2_ADDHLD_0 0x00000010U
3736 #define FMC_BTR2_ADDHLD_1 0x00000020U
3737 #define FMC_BTR2_ADDHLD_2 0x00000040U
3738 #define FMC_BTR2_ADDHLD_3 0x00000080U
3740 #define FMC_BTR2_DATAST 0x0000FF00U
3741 #define FMC_BTR2_DATAST_0 0x00000100U
3742 #define FMC_BTR2_DATAST_1 0x00000200U
3743 #define FMC_BTR2_DATAST_2 0x00000400U
3744 #define FMC_BTR2_DATAST_3 0x00000800U
3745 #define FMC_BTR2_DATAST_4 0x00001000U
3746 #define FMC_BTR2_DATAST_5 0x00002000U
3747 #define FMC_BTR2_DATAST_6 0x00004000U
3748 #define FMC_BTR2_DATAST_7 0x00008000U
3750 #define FMC_BTR2_BUSTURN 0x000F0000U
3751 #define FMC_BTR2_BUSTURN_0 0x00010000U
3752 #define FMC_BTR2_BUSTURN_1 0x00020000U
3753 #define FMC_BTR2_BUSTURN_2 0x00040000U
3754 #define FMC_BTR2_BUSTURN_3 0x00080000U
3756 #define FMC_BTR2_CLKDIV 0x00F00000U
3757 #define FMC_BTR2_CLKDIV_0 0x00100000U
3758 #define FMC_BTR2_CLKDIV_1 0x00200000U
3759 #define FMC_BTR2_CLKDIV_2 0x00400000U
3760 #define FMC_BTR2_CLKDIV_3 0x00800000U
3762 #define FMC_BTR2_DATLAT 0x0F000000U
3763 #define FMC_BTR2_DATLAT_0 0x01000000U
3764 #define FMC_BTR2_DATLAT_1 0x02000000U
3765 #define FMC_BTR2_DATLAT_2 0x04000000U
3766 #define FMC_BTR2_DATLAT_3 0x08000000U
3768 #define FMC_BTR2_ACCMOD 0x30000000U
3769 #define FMC_BTR2_ACCMOD_0 0x10000000U
3770 #define FMC_BTR2_ACCMOD_1 0x20000000U
3772 /******************* Bit definition for FMC_BTR3 register *******************/
3773 #define FMC_BTR3_ADDSET 0x0000000FU
3774 #define FMC_BTR3_ADDSET_0 0x00000001U
3775 #define FMC_BTR3_ADDSET_1 0x00000002U
3776 #define FMC_BTR3_ADDSET_2 0x00000004U
3777 #define FMC_BTR3_ADDSET_3 0x00000008U
3779 #define FMC_BTR3_ADDHLD 0x000000F0U
3780 #define FMC_BTR3_ADDHLD_0 0x00000010U
3781 #define FMC_BTR3_ADDHLD_1 0x00000020U
3782 #define FMC_BTR3_ADDHLD_2 0x00000040U
3783 #define FMC_BTR3_ADDHLD_3 0x00000080U
3785 #define FMC_BTR3_DATAST 0x0000FF00U
3786 #define FMC_BTR3_DATAST_0 0x00000100U
3787 #define FMC_BTR3_DATAST_1 0x00000200U
3788 #define FMC_BTR3_DATAST_2 0x00000400U
3789 #define FMC_BTR3_DATAST_3 0x00000800U
3790 #define FMC_BTR3_DATAST_4 0x00001000U
3791 #define FMC_BTR3_DATAST_5 0x00002000U
3792 #define FMC_BTR3_DATAST_6 0x00004000U
3793 #define FMC_BTR3_DATAST_7 0x00008000U
3795 #define FMC_BTR3_BUSTURN 0x000F0000U
3796 #define FMC_BTR3_BUSTURN_0 0x00010000U
3797 #define FMC_BTR3_BUSTURN_1 0x00020000U
3798 #define FMC_BTR3_BUSTURN_2 0x00040000U
3799 #define FMC_BTR3_BUSTURN_3 0x00080000U
3801 #define FMC_BTR3_CLKDIV 0x00F00000U
3802 #define FMC_BTR3_CLKDIV_0 0x00100000U
3803 #define FMC_BTR3_CLKDIV_1 0x00200000U
3804 #define FMC_BTR3_CLKDIV_2 0x00400000U
3805 #define FMC_BTR3_CLKDIV_3 0x00800000U
3807 #define FMC_BTR3_DATLAT 0x0F000000U
3808 #define FMC_BTR3_DATLAT_0 0x01000000U
3809 #define FMC_BTR3_DATLAT_1 0x02000000U
3810 #define FMC_BTR3_DATLAT_2 0x04000000U
3811 #define FMC_BTR3_DATLAT_3 0x08000000U
3813 #define FMC_BTR3_ACCMOD 0x30000000U
3814 #define FMC_BTR3_ACCMOD_0 0x10000000U
3815 #define FMC_BTR3_ACCMOD_1 0x20000000U
3817 /****************** Bit definition for FMC_BTR4 register *******************/
3818 #define FMC_BTR4_ADDSET 0x0000000FU
3819 #define FMC_BTR4_ADDSET_0 0x00000001U
3820 #define FMC_BTR4_ADDSET_1 0x00000002U
3821 #define FMC_BTR4_ADDSET_2 0x00000004U
3822 #define FMC_BTR4_ADDSET_3 0x00000008U
3824 #define FMC_BTR4_ADDHLD 0x000000F0U
3825 #define FMC_BTR4_ADDHLD_0 0x00000010U
3826 #define FMC_BTR4_ADDHLD_1 0x00000020U
3827 #define FMC_BTR4_ADDHLD_2 0x00000040U
3828 #define FMC_BTR4_ADDHLD_3 0x00000080U
3830 #define FMC_BTR4_DATAST 0x0000FF00U
3831 #define FMC_BTR4_DATAST_0 0x00000100U
3832 #define FMC_BTR4_DATAST_1 0x00000200U
3833 #define FMC_BTR4_DATAST_2 0x00000400U
3834 #define FMC_BTR4_DATAST_3 0x00000800U
3835 #define FMC_BTR4_DATAST_4 0x00001000U
3836 #define FMC_BTR4_DATAST_5 0x00002000U
3837 #define FMC_BTR4_DATAST_6 0x00004000U
3838 #define FMC_BTR4_DATAST_7 0x00008000U
3840 #define FMC_BTR4_BUSTURN 0x000F0000U
3841 #define FMC_BTR4_BUSTURN_0 0x00010000U
3842 #define FMC_BTR4_BUSTURN_1 0x00020000U
3843 #define FMC_BTR4_BUSTURN_2 0x00040000U
3844 #define FMC_BTR4_BUSTURN_3 0x00080000U
3846 #define FMC_BTR4_CLKDIV 0x00F00000U
3847 #define FMC_BTR4_CLKDIV_0 0x00100000U
3848 #define FMC_BTR4_CLKDIV_1 0x00200000U
3849 #define FMC_BTR4_CLKDIV_2 0x00400000U
3850 #define FMC_BTR4_CLKDIV_3 0x00800000U
3852 #define FMC_BTR4_DATLAT 0x0F000000U
3853 #define FMC_BTR4_DATLAT_0 0x01000000U
3854 #define FMC_BTR4_DATLAT_1 0x02000000U
3855 #define FMC_BTR4_DATLAT_2 0x04000000U
3856 #define FMC_BTR4_DATLAT_3 0x08000000U
3858 #define FMC_BTR4_ACCMOD 0x30000000U
3859 #define FMC_BTR4_ACCMOD_0 0x10000000U
3860 #define FMC_BTR4_ACCMOD_1 0x20000000U
3862 /****************** Bit definition for FMC_BWTR1 register ******************/
3863 #define FMC_BWTR1_ADDSET 0x0000000FU
3864 #define FMC_BWTR1_ADDSET_0 0x00000001U
3865 #define FMC_BWTR1_ADDSET_1 0x00000002U
3866 #define FMC_BWTR1_ADDSET_2 0x00000004U
3867 #define FMC_BWTR1_ADDSET_3 0x00000008U
3869 #define FMC_BWTR1_ADDHLD 0x000000F0U
3870 #define FMC_BWTR1_ADDHLD_0 0x00000010U
3871 #define FMC_BWTR1_ADDHLD_1 0x00000020U
3872 #define FMC_BWTR1_ADDHLD_2 0x00000040U
3873 #define FMC_BWTR1_ADDHLD_3 0x00000080U
3875 #define FMC_BWTR1_DATAST 0x0000FF00U
3876 #define FMC_BWTR1_DATAST_0 0x00000100U
3877 #define FMC_BWTR1_DATAST_1 0x00000200U
3878 #define FMC_BWTR1_DATAST_2 0x00000400U
3879 #define FMC_BWTR1_DATAST_3 0x00000800U
3880 #define FMC_BWTR1_DATAST_4 0x00001000U
3881 #define FMC_BWTR1_DATAST_5 0x00002000U
3882 #define FMC_BWTR1_DATAST_6 0x00004000U
3883 #define FMC_BWTR1_DATAST_7 0x00008000U
3885 #define FMC_BWTR1_BUSTURN 0x000F0000U
3886 #define FMC_BWTR1_BUSTURN_0 0x00010000U
3887 #define FMC_BWTR1_BUSTURN_1 0x00020000U
3888 #define FMC_BWTR1_BUSTURN_2 0x00040000U
3889 #define FMC_BWTR1_BUSTURN_3 0x00080000U
3891 #define FMC_BWTR1_ACCMOD 0x30000000U
3892 #define FMC_BWTR1_ACCMOD_0 0x10000000U
3893 #define FMC_BWTR1_ACCMOD_1 0x20000000U
3895 /****************** Bit definition for FMC_BWTR2 register ******************/
3896 #define FMC_BWTR2_ADDSET 0x0000000FU
3897 #define FMC_BWTR2_ADDSET_0 0x00000001U
3898 #define FMC_BWTR2_ADDSET_1 0x00000002U
3899 #define FMC_BWTR2_ADDSET_2 0x00000004U
3900 #define FMC_BWTR2_ADDSET_3 0x00000008U
3902 #define FMC_BWTR2_ADDHLD 0x000000F0U
3903 #define FMC_BWTR2_ADDHLD_0 0x00000010U
3904 #define FMC_BWTR2_ADDHLD_1 0x00000020U
3905 #define FMC_BWTR2_ADDHLD_2 0x00000040U
3906 #define FMC_BWTR2_ADDHLD_3 0x00000080U
3908 #define FMC_BWTR2_DATAST 0x0000FF00U
3909 #define FMC_BWTR2_DATAST_0 0x00000100U
3910 #define FMC_BWTR2_DATAST_1 0x00000200U
3911 #define FMC_BWTR2_DATAST_2 0x00000400U
3912 #define FMC_BWTR2_DATAST_3 0x00000800U
3913 #define FMC_BWTR2_DATAST_4 0x00001000U
3914 #define FMC_BWTR2_DATAST_5 0x00002000U
3915 #define FMC_BWTR2_DATAST_6 0x00004000U
3916 #define FMC_BWTR2_DATAST_7 0x00008000U
3918 #define FMC_BWTR2_BUSTURN 0x000F0000U
3919 #define FMC_BWTR2_BUSTURN_0 0x00010000U
3920 #define FMC_BWTR2_BUSTURN_1 0x00020000U
3921 #define FMC_BWTR2_BUSTURN_2 0x00040000U
3922 #define FMC_BWTR2_BUSTURN_3 0x00080000U
3924 #define FMC_BWTR2_ACCMOD 0x30000000U
3925 #define FMC_BWTR2_ACCMOD_0 0x10000000U
3926 #define FMC_BWTR2_ACCMOD_1 0x20000000U
3928 /****************** Bit definition for FMC_BWTR3 register ******************/
3929 #define FMC_BWTR3_ADDSET 0x0000000FU
3930 #define FMC_BWTR3_ADDSET_0 0x00000001U
3931 #define FMC_BWTR3_ADDSET_1 0x00000002U
3932 #define FMC_BWTR3_ADDSET_2 0x00000004U
3933 #define FMC_BWTR3_ADDSET_3 0x00000008U
3935 #define FMC_BWTR3_ADDHLD 0x000000F0U
3936 #define FMC_BWTR3_ADDHLD_0 0x00000010U
3937 #define FMC_BWTR3_ADDHLD_1 0x00000020U
3938 #define FMC_BWTR3_ADDHLD_2 0x00000040U
3939 #define FMC_BWTR3_ADDHLD_3 0x00000080U
3941 #define FMC_BWTR3_DATAST 0x0000FF00U
3942 #define FMC_BWTR3_DATAST_0 0x00000100U
3943 #define FMC_BWTR3_DATAST_1 0x00000200U
3944 #define FMC_BWTR3_DATAST_2 0x00000400U
3945 #define FMC_BWTR3_DATAST_3 0x00000800U
3946 #define FMC_BWTR3_DATAST_4 0x00001000U
3947 #define FMC_BWTR3_DATAST_5 0x00002000U
3948 #define FMC_BWTR3_DATAST_6 0x00004000U
3949 #define FMC_BWTR3_DATAST_7 0x00008000U
3951 #define FMC_BWTR3_BUSTURN 0x000F0000U
3952 #define FMC_BWTR3_BUSTURN_0 0x00010000U
3953 #define FMC_BWTR3_BUSTURN_1 0x00020000U
3954 #define FMC_BWTR3_BUSTURN_2 0x00040000U
3955 #define FMC_BWTR3_BUSTURN_3 0x00080000U
3957 #define FMC_BWTR3_ACCMOD 0x30000000U
3958 #define FMC_BWTR3_ACCMOD_0 0x10000000U
3959 #define FMC_BWTR3_ACCMOD_1 0x20000000U
3961 /****************** Bit definition for FMC_BWTR4 register ******************/
3962 #define FMC_BWTR4_ADDSET 0x0000000FU
3963 #define FMC_BWTR4_ADDSET_0 0x00000001U
3964 #define FMC_BWTR4_ADDSET_1 0x00000002U
3965 #define FMC_BWTR4_ADDSET_2 0x00000004U
3966 #define FMC_BWTR4_ADDSET_3 0x00000008U
3968 #define FMC_BWTR4_ADDHLD 0x000000F0U
3969 #define FMC_BWTR4_ADDHLD_0 0x00000010U
3970 #define FMC_BWTR4_ADDHLD_1 0x00000020U
3971 #define FMC_BWTR4_ADDHLD_2 0x00000040U
3972 #define FMC_BWTR4_ADDHLD_3 0x00000080U
3974 #define FMC_BWTR4_DATAST 0x0000FF00U
3975 #define FMC_BWTR4_DATAST_0 0x00000100U
3976 #define FMC_BWTR4_DATAST_1 0x00000200U
3977 #define FMC_BWTR4_DATAST_2 0x00000400U
3978 #define FMC_BWTR4_DATAST_3 0x00000800U
3979 #define FMC_BWTR4_DATAST_4 0x00001000U
3980 #define FMC_BWTR4_DATAST_5 0x00002000U
3981 #define FMC_BWTR4_DATAST_6 0x00004000U
3982 #define FMC_BWTR4_DATAST_7 0x00008000U
3984 #define FMC_BWTR4_BUSTURN 0x000F0000U
3985 #define FMC_BWTR4_BUSTURN_0 0x00010000U
3986 #define FMC_BWTR4_BUSTURN_1 0x00020000U
3987 #define FMC_BWTR4_BUSTURN_2 0x00040000U
3988 #define FMC_BWTR4_BUSTURN_3 0x00080000U
3990 #define FMC_BWTR4_ACCMOD 0x30000000U
3991 #define FMC_BWTR4_ACCMOD_0 0x10000000U
3992 #define FMC_BWTR4_ACCMOD_1 0x20000000U
3994 /****************** Bit definition for FMC_PCR register *******************/
3995 #define FMC_PCR_PWAITEN 0x00000002U
3996 #define FMC_PCR_PBKEN 0x00000004U
3997 #define FMC_PCR_PTYP 0x00000008U
3999 #define FMC_PCR_PWID 0x00000030U
4000 #define FMC_PCR_PWID_0 0x00000010U
4001 #define FMC_PCR_PWID_1 0x00000020U
4003 #define FMC_PCR_ECCEN 0x00000040U
4005 #define FMC_PCR_TCLR 0x00001E00U
4006 #define FMC_PCR_TCLR_0 0x00000200U
4007 #define FMC_PCR_TCLR_1 0x00000400U
4008 #define FMC_PCR_TCLR_2 0x00000800U
4009 #define FMC_PCR_TCLR_3 0x00001000U
4011 #define FMC_PCR_TAR 0x0001E000U
4012 #define FMC_PCR_TAR_0 0x00002000U
4013 #define FMC_PCR_TAR_1 0x00004000U
4014 #define FMC_PCR_TAR_2 0x00008000U
4015 #define FMC_PCR_TAR_3 0x00010000U
4017 #define FMC_PCR_ECCPS 0x000E0000U
4018 #define FMC_PCR_ECCPS_0 0x00020000U
4019 #define FMC_PCR_ECCPS_1 0x00040000U
4020 #define FMC_PCR_ECCPS_2 0x00080000U
4022 /******************* Bit definition for FMC_SR register *******************/
4023 #define FMC_SR_IRS 0x01U
4024 #define FMC_SR_ILS 0x02U
4025 #define FMC_SR_IFS 0x04U
4026 #define FMC_SR_IREN 0x08U
4027 #define FMC_SR_ILEN 0x10U
4028 #define FMC_SR_IFEN 0x20U
4029 #define FMC_SR_FEMPT 0x40U
4031 /****************** Bit definition for FMC_PMEM register ******************/
4032 #define FMC_PMEM_MEMSET2 0x000000FFU
4033 #define FMC_PMEM_MEMSET2_0 0x00000001U
4034 #define FMC_PMEM_MEMSET2_1 0x00000002U
4035 #define FMC_PMEM_MEMSET2_2 0x00000004U
4036 #define FMC_PMEM_MEMSET2_3 0x00000008U
4037 #define FMC_PMEM_MEMSET2_4 0x00000010U
4038 #define FMC_PMEM_MEMSET2_5 0x00000020U
4039 #define FMC_PMEM_MEMSET2_6 0x00000040U
4040 #define FMC_PMEM_MEMSET2_7 0x00000080U
4042 #define FMC_PMEM_MEMWAIT2 0x0000FF00U
4043 #define FMC_PMEM_MEMWAIT2_0 0x00000100U
4044 #define FMC_PMEM_MEMWAIT2_1 0x00000200U
4045 #define FMC_PMEM_MEMWAIT2_2 0x00000400U
4046 #define FMC_PMEM_MEMWAIT2_3 0x00000800U
4047 #define FMC_PMEM_MEMWAIT2_4 0x00001000U
4048 #define FMC_PMEM_MEMWAIT2_5 0x00002000U
4049 #define FMC_PMEM_MEMWAIT2_6 0x00004000U
4050 #define FMC_PMEM_MEMWAIT2_7 0x00008000U
4052 #define FMC_PMEM_MEMHOLD2 0x00FF0000U
4053 #define FMC_PMEM_MEMHOLD2_0 0x00010000U
4054 #define FMC_PMEM_MEMHOLD2_1 0x00020000U
4055 #define FMC_PMEM_MEMHOLD2_2 0x00040000U
4056 #define FMC_PMEM_MEMHOLD2_3 0x00080000U
4057 #define FMC_PMEM_MEMHOLD2_4 0x00100000U
4058 #define FMC_PMEM_MEMHOLD2_5 0x00200000U
4059 #define FMC_PMEM_MEMHOLD2_6 0x00400000U
4060 #define FMC_PMEM_MEMHOLD2_7 0x00800000U
4062 #define FMC_PMEM_MEMHIZ2 0xFF000000U
4063 #define FMC_PMEM_MEMHIZ2_0 0x01000000U
4064 #define FMC_PMEM_MEMHIZ2_1 0x02000000U
4065 #define FMC_PMEM_MEMHIZ2_2 0x04000000U
4066 #define FMC_PMEM_MEMHIZ2_3 0x08000000U
4067 #define FMC_PMEM_MEMHIZ2_4 0x10000000U
4068 #define FMC_PMEM_MEMHIZ2_5 0x20000000U
4069 #define FMC_PMEM_MEMHIZ2_6 0x40000000U
4070 #define FMC_PMEM_MEMHIZ2_7 0x80000000U
4072 /****************** Bit definition for FMC_PATT register ******************/
4073 #define FMC_PATT_ATTSET2 0x000000FFU
4074 #define FMC_PATT_ATTSET2_0 0x00000001U
4075 #define FMC_PATT_ATTSET2_1 0x00000002U
4076 #define FMC_PATT_ATTSET2_2 0x00000004U
4077 #define FMC_PATT_ATTSET2_3 0x00000008U
4078 #define FMC_PATT_ATTSET2_4 0x00000010U
4079 #define FMC_PATT_ATTSET2_5 0x00000020U
4080 #define FMC_PATT_ATTSET2_6 0x00000040U
4081 #define FMC_PATT_ATTSET2_7 0x00000080U
4083 #define FMC_PATT_ATTWAIT2 0x0000FF00U
4084 #define FMC_PATT_ATTWAIT2_0 0x00000100U
4085 #define FMC_PATT_ATTWAIT2_1 0x00000200U
4086 #define FMC_PATT_ATTWAIT2_2 0x00000400U
4087 #define FMC_PATT_ATTWAIT2_3 0x00000800U
4088 #define FMC_PATT_ATTWAIT2_4 0x00001000U
4089 #define FMC_PATT_ATTWAIT2_5 0x00002000U
4090 #define FMC_PATT_ATTWAIT2_6 0x00004000U
4091 #define FMC_PATT_ATTWAIT2_7 0x00008000U
4093 #define FMC_PATT_ATTHOLD2 0x00FF0000U
4094 #define FMC_PATT_ATTHOLD2_0 0x00010000U
4095 #define FMC_PATT_ATTHOLD2_1 0x00020000U
4096 #define FMC_PATT_ATTHOLD2_2 0x00040000U
4097 #define FMC_PATT_ATTHOLD2_3 0x00080000U
4098 #define FMC_PATT_ATTHOLD2_4 0x00100000U
4099 #define FMC_PATT_ATTHOLD2_5 0x00200000U
4100 #define FMC_PATT_ATTHOLD2_6 0x00400000U
4101 #define FMC_PATT_ATTHOLD2_7 0x00800000U
4103 #define FMC_PATT_ATTHIZ2 0xFF000000U
4104 #define FMC_PATT_ATTHIZ2_0 0x01000000U
4105 #define FMC_PATT_ATTHIZ2_1 0x02000000U
4106 #define FMC_PATT_ATTHIZ2_2 0x04000000U
4107 #define FMC_PATT_ATTHIZ2_3 0x08000000U
4108 #define FMC_PATT_ATTHIZ2_4 0x10000000U
4109 #define FMC_PATT_ATTHIZ2_5 0x20000000U
4110 #define FMC_PATT_ATTHIZ2_6 0x40000000U
4111 #define FMC_PATT_ATTHIZ2_7 0x80000000U
4113 /****************** Bit definition for FMC_ECCR register ******************/
4114 #define FMC_ECCR_ECC2 0xFFFFFFFFU
4116 /****************** Bit definition for FMC_SDCR1 register ******************/
4117 #define FMC_SDCR1_NC 0x00000003U
4118 #define FMC_SDCR1_NC_0 0x00000001U
4119 #define FMC_SDCR1_NC_1 0x00000002U
4121 #define FMC_SDCR1_NR 0x0000000CU
4122 #define FMC_SDCR1_NR_0 0x00000004U
4123 #define FMC_SDCR1_NR_1 0x00000008U
4125 #define FMC_SDCR1_MWID 0x00000030U
4126 #define FMC_SDCR1_MWID_0 0x00000010U
4127 #define FMC_SDCR1_MWID_1 0x00000020U
4129 #define FMC_SDCR1_NB 0x00000040U
4131 #define FMC_SDCR1_CAS 0x00000180U
4132 #define FMC_SDCR1_CAS_0 0x00000080U
4133 #define FMC_SDCR1_CAS_1 0x00000100U
4135 #define FMC_SDCR1_WP 0x00000200U
4137 #define FMC_SDCR1_SDCLK 0x00000C00U
4138 #define FMC_SDCR1_SDCLK_0 0x00000400U
4139 #define FMC_SDCR1_SDCLK_1 0x00000800U
4141 #define FMC_SDCR1_RBURST 0x00001000U
4143 #define FMC_SDCR1_RPIPE 0x00006000U
4144 #define FMC_SDCR1_RPIPE_0 0x00002000U
4145 #define FMC_SDCR1_RPIPE_1 0x00004000U
4147 /****************** Bit definition for FMC_SDCR2 register ******************/
4148 #define FMC_SDCR2_NC 0x00000003U
4149 #define FMC_SDCR2_NC_0 0x00000001U
4150 #define FMC_SDCR2_NC_1 0x00000002U
4152 #define FMC_SDCR2_NR 0x0000000CU
4153 #define FMC_SDCR2_NR_0 0x00000004U
4154 #define FMC_SDCR2_NR_1 0x00000008U
4156 #define FMC_SDCR2_MWID 0x00000030U
4157 #define FMC_SDCR2_MWID_0 0x00000010U
4158 #define FMC_SDCR2_MWID_1 0x00000020U
4160 #define FMC_SDCR2_NB 0x00000040U
4162 #define FMC_SDCR2_CAS 0x00000180U
4163 #define FMC_SDCR2_CAS_0 0x00000080U
4164 #define FMC_SDCR2_CAS_1 0x00000100U
4166 #define FMC_SDCR2_WP 0x00000200U
4168 #define FMC_SDCR2_SDCLK 0x00000C00U
4169 #define FMC_SDCR2_SDCLK_0 0x00000400U
4170 #define FMC_SDCR2_SDCLK_1 0x00000800U
4172 #define FMC_SDCR2_RBURST 0x00001000U
4174 #define FMC_SDCR2_RPIPE 0x00006000U
4175 #define FMC_SDCR2_RPIPE_0 0x00002000U
4176 #define FMC_SDCR2_RPIPE_1 0x00004000U
4178 /****************** Bit definition for FMC_SDTR1 register ******************/
4179 #define FMC_SDTR1_TMRD 0x0000000FU
4180 #define FMC_SDTR1_TMRD_0 0x00000001U
4181 #define FMC_SDTR1_TMRD_1 0x00000002U
4182 #define FMC_SDTR1_TMRD_2 0x00000004U
4183 #define FMC_SDTR1_TMRD_3 0x00000008U
4185 #define FMC_SDTR1_TXSR 0x000000F0U
4186 #define FMC_SDTR1_TXSR_0 0x00000010U
4187 #define FMC_SDTR1_TXSR_1 0x00000020U
4188 #define FMC_SDTR1_TXSR_2 0x00000040U
4189 #define FMC_SDTR1_TXSR_3 0x00000080U
4191 #define FMC_SDTR1_TRAS 0x00000F00U
4192 #define FMC_SDTR1_TRAS_0 0x00000100U
4193 #define FMC_SDTR1_TRAS_1 0x00000200U
4194 #define FMC_SDTR1_TRAS_2 0x00000400U
4195 #define FMC_SDTR1_TRAS_3 0x00000800U
4197 #define FMC_SDTR1_TRC 0x0000F000U
4198 #define FMC_SDTR1_TRC_0 0x00001000U
4199 #define FMC_SDTR1_TRC_1 0x00002000U
4200 #define FMC_SDTR1_TRC_2 0x00004000U
4202 #define FMC_SDTR1_TWR 0x000F0000U
4203 #define FMC_SDTR1_TWR_0 0x00010000U
4204 #define FMC_SDTR1_TWR_1 0x00020000U
4205 #define FMC_SDTR1_TWR_2 0x00040000U
4207 #define FMC_SDTR1_TRP 0x00F00000U
4208 #define FMC_SDTR1_TRP_0 0x00100000U
4209 #define FMC_SDTR1_TRP_1 0x00200000U
4210 #define FMC_SDTR1_TRP_2 0x00400000U
4212 #define FMC_SDTR1_TRCD 0x0F000000U
4213 #define FMC_SDTR1_TRCD_0 0x01000000U
4214 #define FMC_SDTR1_TRCD_1 0x02000000U
4215 #define FMC_SDTR1_TRCD_2 0x04000000U
4217 /****************** Bit definition for FMC_SDTR2 register ******************/
4218 #define FMC_SDTR2_TMRD 0x0000000FU
4219 #define FMC_SDTR2_TMRD_0 0x00000001U
4220 #define FMC_SDTR2_TMRD_1 0x00000002U
4221 #define FMC_SDTR2_TMRD_2 0x00000004U
4222 #define FMC_SDTR2_TMRD_3 0x00000008U
4224 #define FMC_SDTR2_TXSR 0x000000F0U
4225 #define FMC_SDTR2_TXSR_0 0x00000010U
4226 #define FMC_SDTR2_TXSR_1 0x00000020U
4227 #define FMC_SDTR2_TXSR_2 0x00000040U
4228 #define FMC_SDTR2_TXSR_3 0x00000080U
4230 #define FMC_SDTR2_TRAS 0x00000F00U
4231 #define FMC_SDTR2_TRAS_0 0x00000100U
4232 #define FMC_SDTR2_TRAS_1 0x00000200U
4233 #define FMC_SDTR2_TRAS_2 0x00000400U
4234 #define FMC_SDTR2_TRAS_3 0x00000800U
4236 #define FMC_SDTR2_TRC 0x0000F000U
4237 #define FMC_SDTR2_TRC_0 0x00001000U
4238 #define FMC_SDTR2_TRC_1 0x00002000U
4239 #define FMC_SDTR2_TRC_2 0x00004000U
4241 #define FMC_SDTR2_TWR 0x000F0000U
4242 #define FMC_SDTR2_TWR_0 0x00010000U
4243 #define FMC_SDTR2_TWR_1 0x00020000U
4244 #define FMC_SDTR2_TWR_2 0x00040000U
4246 #define FMC_SDTR2_TRP 0x00F00000U
4247 #define FMC_SDTR2_TRP_0 0x00100000U
4248 #define FMC_SDTR2_TRP_1 0x00200000U
4249 #define FMC_SDTR2_TRP_2 0x00400000U
4251 #define FMC_SDTR2_TRCD 0x0F000000U
4252 #define FMC_SDTR2_TRCD_0 0x01000000U
4253 #define FMC_SDTR2_TRCD_1 0x02000000U
4254 #define FMC_SDTR2_TRCD_2 0x04000000U
4256 /****************** Bit definition for FMC_SDCMR register ******************/
4257 #define FMC_SDCMR_MODE 0x00000007U
4258 #define FMC_SDCMR_MODE_0 0x00000001U
4259 #define FMC_SDCMR_MODE_1 0x00000002U
4260 #define FMC_SDCMR_MODE_2 0x00000004U
4262 #define FMC_SDCMR_CTB2 0x00000008U
4264 #define FMC_SDCMR_CTB1 0x00000010U
4266 #define FMC_SDCMR_NRFS 0x000001E0U
4267 #define FMC_SDCMR_NRFS_0 0x00000020U
4268 #define FMC_SDCMR_NRFS_1 0x00000040U
4269 #define FMC_SDCMR_NRFS_2 0x00000080U
4270 #define FMC_SDCMR_NRFS_3 0x00000100U
4272 #define FMC_SDCMR_MRD 0x003FFE00U
4274 /****************** Bit definition for FMC_SDRTR register ******************/
4275 #define FMC_SDRTR_CRE 0x00000001U
4277 #define FMC_SDRTR_COUNT 0x00003FFEU
4279 #define FMC_SDRTR_REIE 0x00004000U
4281 /****************** Bit definition for FMC_SDSR register ******************/
4282 #define FMC_SDSR_RE 0x00000001U
4284 #define FMC_SDSR_MODES1 0x00000006U
4285 #define FMC_SDSR_MODES1_0 0x00000002U
4286 #define FMC_SDSR_MODES1_1 0x00000004U
4288 #define FMC_SDSR_MODES2 0x00000018U
4289 #define FMC_SDSR_MODES2_0 0x00000008U
4290 #define FMC_SDSR_MODES2_1 0x00000010U
4291 #define FMC_SDSR_BUSY 0x00000020U
4293 /******************************************************************************/
4294 /* */
4295 /* General Purpose I/O */
4296 /* */
4297 /******************************************************************************/
4298 /****************** Bits definition for GPIO_MODER register *****************/
4299 #define GPIO_MODER_MODER0 0x00000003U
4300 #define GPIO_MODER_MODER0_0 0x00000001U
4301 #define GPIO_MODER_MODER0_1 0x00000002U
4302 
4303 #define GPIO_MODER_MODER1 0x0000000CU
4304 #define GPIO_MODER_MODER1_0 0x00000004U
4305 #define GPIO_MODER_MODER1_1 0x00000008U
4306 
4307 #define GPIO_MODER_MODER2 0x00000030U
4308 #define GPIO_MODER_MODER2_0 0x00000010U
4309 #define GPIO_MODER_MODER2_1 0x00000020U
4310 
4311 #define GPIO_MODER_MODER3 0x000000C0U
4312 #define GPIO_MODER_MODER3_0 0x00000040U
4313 #define GPIO_MODER_MODER3_1 0x00000080U
4314 
4315 #define GPIO_MODER_MODER4 0x00000300U
4316 #define GPIO_MODER_MODER4_0 0x00000100U
4317 #define GPIO_MODER_MODER4_1 0x00000200U
4318 
4319 #define GPIO_MODER_MODER5 0x00000C00U
4320 #define GPIO_MODER_MODER5_0 0x00000400U
4321 #define GPIO_MODER_MODER5_1 0x00000800U
4322 
4323 #define GPIO_MODER_MODER6 0x00003000U
4324 #define GPIO_MODER_MODER6_0 0x00001000U
4325 #define GPIO_MODER_MODER6_1 0x00002000U
4326 
4327 #define GPIO_MODER_MODER7 0x0000C000U
4328 #define GPIO_MODER_MODER7_0 0x00004000U
4329 #define GPIO_MODER_MODER7_1 0x00008000U
4330 
4331 #define GPIO_MODER_MODER8 0x00030000U
4332 #define GPIO_MODER_MODER8_0 0x00010000U
4333 #define GPIO_MODER_MODER8_1 0x00020000U
4334 
4335 #define GPIO_MODER_MODER9 0x000C0000U
4336 #define GPIO_MODER_MODER9_0 0x00040000U
4337 #define GPIO_MODER_MODER9_1 0x00080000U
4338 
4339 #define GPIO_MODER_MODER10 0x00300000U
4340 #define GPIO_MODER_MODER10_0 0x00100000U
4341 #define GPIO_MODER_MODER10_1 0x00200000U
4342 
4343 #define GPIO_MODER_MODER11 0x00C00000U
4344 #define GPIO_MODER_MODER11_0 0x00400000U
4345 #define GPIO_MODER_MODER11_1 0x00800000U
4346 
4347 #define GPIO_MODER_MODER12 0x03000000U
4348 #define GPIO_MODER_MODER12_0 0x01000000U
4349 #define GPIO_MODER_MODER12_1 0x02000000U
4350 
4351 #define GPIO_MODER_MODER13 0x0C000000U
4352 #define GPIO_MODER_MODER13_0 0x04000000U
4353 #define GPIO_MODER_MODER13_1 0x08000000U
4354 
4355 #define GPIO_MODER_MODER14 0x30000000U
4356 #define GPIO_MODER_MODER14_0 0x10000000U
4357 #define GPIO_MODER_MODER14_1 0x20000000U
4358 
4359 #define GPIO_MODER_MODER15 0xC0000000U
4360 #define GPIO_MODER_MODER15_0 0x40000000U
4361 #define GPIO_MODER_MODER15_1 0x80000000U
4362 
4363 /****************** Bits definition for GPIO_OTYPER register ****************/
4364 #define GPIO_OTYPER_OT_0 0x00000001U
4365 #define GPIO_OTYPER_OT_1 0x00000002U
4366 #define GPIO_OTYPER_OT_2 0x00000004U
4367 #define GPIO_OTYPER_OT_3 0x00000008U
4368 #define GPIO_OTYPER_OT_4 0x00000010U
4369 #define GPIO_OTYPER_OT_5 0x00000020U
4370 #define GPIO_OTYPER_OT_6 0x00000040U
4371 #define GPIO_OTYPER_OT_7 0x00000080U
4372 #define GPIO_OTYPER_OT_8 0x00000100U
4373 #define GPIO_OTYPER_OT_9 0x00000200U
4374 #define GPIO_OTYPER_OT_10 0x00000400U
4375 #define GPIO_OTYPER_OT_11 0x00000800U
4376 #define GPIO_OTYPER_OT_12 0x00001000U
4377 #define GPIO_OTYPER_OT_13 0x00002000U
4378 #define GPIO_OTYPER_OT_14 0x00004000U
4379 #define GPIO_OTYPER_OT_15 0x00008000U
4380 
4381 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4382 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
4383 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
4384 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
4385 
4386 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
4387 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
4388 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
4389 
4390 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
4391 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
4392 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
4393 
4394 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
4395 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
4396 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
4397 
4398 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
4399 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
4400 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
4401 
4402 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
4403 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
4404 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
4405 
4406 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
4407 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
4408 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
4409 
4410 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
4411 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
4412 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
4413 
4414 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
4415 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
4416 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
4417 
4418 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
4419 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
4420 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
4421 
4422 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
4423 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
4424 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
4425 
4426 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
4427 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
4428 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
4429 
4430 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
4431 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
4432 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
4433 
4434 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
4435 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
4436 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
4437 
4438 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
4439 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
4440 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
4441 
4442 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
4443 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
4444 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
4445 
4446 /****************** Bits definition for GPIO_PUPDR register *****************/
4447 #define GPIO_PUPDR_PUPDR0 0x00000003U
4448 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
4449 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
4450 
4451 #define GPIO_PUPDR_PUPDR1 0x0000000CU
4452 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
4453 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
4454 
4455 #define GPIO_PUPDR_PUPDR2 0x00000030U
4456 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
4457 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
4458 
4459 #define GPIO_PUPDR_PUPDR3 0x000000C0U
4460 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
4461 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
4462 
4463 #define GPIO_PUPDR_PUPDR4 0x00000300U
4464 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
4465 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
4466 
4467 #define GPIO_PUPDR_PUPDR5 0x00000C00U
4468 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
4469 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
4470 
4471 #define GPIO_PUPDR_PUPDR6 0x00003000U
4472 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
4473 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
4474 
4475 #define GPIO_PUPDR_PUPDR7 0x0000C000U
4476 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
4477 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
4478 
4479 #define GPIO_PUPDR_PUPDR8 0x00030000U
4480 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
4481 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
4482 
4483 #define GPIO_PUPDR_PUPDR9 0x000C0000U
4484 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
4485 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
4486 
4487 #define GPIO_PUPDR_PUPDR10 0x00300000U
4488 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
4489 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
4490 
4491 #define GPIO_PUPDR_PUPDR11 0x00C00000U
4492 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
4493 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
4494 
4495 #define GPIO_PUPDR_PUPDR12 0x03000000U
4496 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
4497 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
4498 
4499 #define GPIO_PUPDR_PUPDR13 0x0C000000U
4500 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
4501 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
4502 
4503 #define GPIO_PUPDR_PUPDR14 0x30000000U
4504 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
4505 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
4506 
4507 #define GPIO_PUPDR_PUPDR15 0xC0000000U
4508 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
4509 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
4510 
4511 /****************** Bits definition for GPIO_IDR register *******************/
4512 #define GPIO_IDR_IDR_0 0x00000001U
4513 #define GPIO_IDR_IDR_1 0x00000002U
4514 #define GPIO_IDR_IDR_2 0x00000004U
4515 #define GPIO_IDR_IDR_3 0x00000008U
4516 #define GPIO_IDR_IDR_4 0x00000010U
4517 #define GPIO_IDR_IDR_5 0x00000020U
4518 #define GPIO_IDR_IDR_6 0x00000040U
4519 #define GPIO_IDR_IDR_7 0x00000080U
4520 #define GPIO_IDR_IDR_8 0x00000100U
4521 #define GPIO_IDR_IDR_9 0x00000200U
4522 #define GPIO_IDR_IDR_10 0x00000400U
4523 #define GPIO_IDR_IDR_11 0x00000800U
4524 #define GPIO_IDR_IDR_12 0x00001000U
4525 #define GPIO_IDR_IDR_13 0x00002000U
4526 #define GPIO_IDR_IDR_14 0x00004000U
4527 #define GPIO_IDR_IDR_15 0x00008000U
4528 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4529 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4530 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4531 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4532 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4533 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4534 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4535 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4536 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4537 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4538 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4539 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4540 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4541 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4542 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4543 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4544 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4545 
4546 /****************** Bits definition for GPIO_ODR register *******************/
4547 #define GPIO_ODR_ODR_0 0x00000001U
4548 #define GPIO_ODR_ODR_1 0x00000002U
4549 #define GPIO_ODR_ODR_2 0x00000004U
4550 #define GPIO_ODR_ODR_3 0x00000008U
4551 #define GPIO_ODR_ODR_4 0x00000010U
4552 #define GPIO_ODR_ODR_5 0x00000020U
4553 #define GPIO_ODR_ODR_6 0x00000040U
4554 #define GPIO_ODR_ODR_7 0x00000080U
4555 #define GPIO_ODR_ODR_8 0x00000100U
4556 #define GPIO_ODR_ODR_9 0x00000200U
4557 #define GPIO_ODR_ODR_10 0x00000400U
4558 #define GPIO_ODR_ODR_11 0x00000800U
4559 #define GPIO_ODR_ODR_12 0x00001000U
4560 #define GPIO_ODR_ODR_13 0x00002000U
4561 #define GPIO_ODR_ODR_14 0x00004000U
4562 #define GPIO_ODR_ODR_15 0x00008000U
4563 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4564 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4565 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4566 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4567 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4568 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4569 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4570 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4571 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4572 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4573 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4574 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4575 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4576 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4577 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4578 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4579 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4580 
4581 /****************** Bits definition for GPIO_BSRR register ******************/
4582 #define GPIO_BSRR_BS_0 0x00000001U
4583 #define GPIO_BSRR_BS_1 0x00000002U
4584 #define GPIO_BSRR_BS_2 0x00000004U
4585 #define GPIO_BSRR_BS_3 0x00000008U
4586 #define GPIO_BSRR_BS_4 0x00000010U
4587 #define GPIO_BSRR_BS_5 0x00000020U
4588 #define GPIO_BSRR_BS_6 0x00000040U
4589 #define GPIO_BSRR_BS_7 0x00000080U
4590 #define GPIO_BSRR_BS_8 0x00000100U
4591 #define GPIO_BSRR_BS_9 0x00000200U
4592 #define GPIO_BSRR_BS_10 0x00000400U
4593 #define GPIO_BSRR_BS_11 0x00000800U
4594 #define GPIO_BSRR_BS_12 0x00001000U
4595 #define GPIO_BSRR_BS_13 0x00002000U
4596 #define GPIO_BSRR_BS_14 0x00004000U
4597 #define GPIO_BSRR_BS_15 0x00008000U
4598 #define GPIO_BSRR_BR_0 0x00010000U
4599 #define GPIO_BSRR_BR_1 0x00020000U
4600 #define GPIO_BSRR_BR_2 0x00040000U
4601 #define GPIO_BSRR_BR_3 0x00080000U
4602 #define GPIO_BSRR_BR_4 0x00100000U
4603 #define GPIO_BSRR_BR_5 0x00200000U
4604 #define GPIO_BSRR_BR_6 0x00400000U
4605 #define GPIO_BSRR_BR_7 0x00800000U
4606 #define GPIO_BSRR_BR_8 0x01000000U
4607 #define GPIO_BSRR_BR_9 0x02000000U
4608 #define GPIO_BSRR_BR_10 0x04000000U
4609 #define GPIO_BSRR_BR_11 0x08000000U
4610 #define GPIO_BSRR_BR_12 0x10000000U
4611 #define GPIO_BSRR_BR_13 0x20000000U
4612 #define GPIO_BSRR_BR_14 0x40000000U
4613 #define GPIO_BSRR_BR_15 0x80000000U
4614 
4615 /****************** Bit definition for GPIO_LCKR register *********************/
4616 #define GPIO_LCKR_LCK0 0x00000001U
4617 #define GPIO_LCKR_LCK1 0x00000002U
4618 #define GPIO_LCKR_LCK2 0x00000004U
4619 #define GPIO_LCKR_LCK3 0x00000008U
4620 #define GPIO_LCKR_LCK4 0x00000010U
4621 #define GPIO_LCKR_LCK5 0x00000020U
4622 #define GPIO_LCKR_LCK6 0x00000040U
4623 #define GPIO_LCKR_LCK7 0x00000080U
4624 #define GPIO_LCKR_LCK8 0x00000100U
4625 #define GPIO_LCKR_LCK9 0x00000200U
4626 #define GPIO_LCKR_LCK10 0x00000400U
4627 #define GPIO_LCKR_LCK11 0x00000800U
4628 #define GPIO_LCKR_LCK12 0x00001000U
4629 #define GPIO_LCKR_LCK13 0x00002000U
4630 #define GPIO_LCKR_LCK14 0x00004000U
4631 #define GPIO_LCKR_LCK15 0x00008000U
4632 #define GPIO_LCKR_LCKK 0x00010000U
4633 
4634 /******************************************************************************/
4635 /* */
4636 /* Inter-integrated Circuit Interface */
4637 /* */
4638 /******************************************************************************/
4639 /******************* Bit definition for I2C_CR1 register ********************/
4640 #define I2C_CR1_PE 0x00000001U
4641 #define I2C_CR1_SMBUS 0x00000002U
4642 #define I2C_CR1_SMBTYPE 0x00000008U
4643 #define I2C_CR1_ENARP 0x00000010U
4644 #define I2C_CR1_ENPEC 0x00000020U
4645 #define I2C_CR1_ENGC 0x00000040U
4646 #define I2C_CR1_NOSTRETCH 0x00000080U
4647 #define I2C_CR1_START 0x00000100U
4648 #define I2C_CR1_STOP 0x00000200U
4649 #define I2C_CR1_ACK 0x00000400U
4650 #define I2C_CR1_POS 0x00000800U
4651 #define I2C_CR1_PEC 0x00001000U
4652 #define I2C_CR1_ALERT 0x00002000U
4653 #define I2C_CR1_SWRST 0x00008000U
4655 /******************* Bit definition for I2C_CR2 register ********************/
4656 #define I2C_CR2_FREQ 0x0000003FU
4657 #define I2C_CR2_FREQ_0 0x00000001U
4658 #define I2C_CR2_FREQ_1 0x00000002U
4659 #define I2C_CR2_FREQ_2 0x00000004U
4660 #define I2C_CR2_FREQ_3 0x00000008U
4661 #define I2C_CR2_FREQ_4 0x00000010U
4662 #define I2C_CR2_FREQ_5 0x00000020U
4664 #define I2C_CR2_ITERREN 0x00000100U
4665 #define I2C_CR2_ITEVTEN 0x00000200U
4666 #define I2C_CR2_ITBUFEN 0x00000400U
4667 #define I2C_CR2_DMAEN 0x00000800U
4668 #define I2C_CR2_LAST 0x00001000U
4670 /******************* Bit definition for I2C_OAR1 register *******************/
4671 #define I2C_OAR1_ADD1_7 0x000000FEU
4672 #define I2C_OAR1_ADD8_9 0x00000300U
4674 #define I2C_OAR1_ADD0 0x00000001U
4675 #define I2C_OAR1_ADD1 0x00000002U
4676 #define I2C_OAR1_ADD2 0x00000004U
4677 #define I2C_OAR1_ADD3 0x00000008U
4678 #define I2C_OAR1_ADD4 0x00000010U
4679 #define I2C_OAR1_ADD5 0x00000020U
4680 #define I2C_OAR1_ADD6 0x00000040U
4681 #define I2C_OAR1_ADD7 0x00000080U
4682 #define I2C_OAR1_ADD8 0x00000100U
4683 #define I2C_OAR1_ADD9 0x00000200U
4685 #define I2C_OAR1_ADDMODE 0x00008000U
4687 /******************* Bit definition for I2C_OAR2 register *******************/
4688 #define I2C_OAR2_ENDUAL 0x00000001U
4689 #define I2C_OAR2_ADD2 0x000000FEU
4691 /******************** Bit definition for I2C_DR register ********************/
4692 #define I2C_DR_DR 0x000000FFU
4694 /******************* Bit definition for I2C_SR1 register ********************/
4695 #define I2C_SR1_SB 0x00000001U
4696 #define I2C_SR1_ADDR 0x00000002U
4697 #define I2C_SR1_BTF 0x00000004U
4698 #define I2C_SR1_ADD10 0x00000008U
4699 #define I2C_SR1_STOPF 0x00000010U
4700 #define I2C_SR1_RXNE 0x00000040U
4701 #define I2C_SR1_TXE 0x00000080U
4702 #define I2C_SR1_BERR 0x00000100U
4703 #define I2C_SR1_ARLO 0x00000200U
4704 #define I2C_SR1_AF 0x00000400U
4705 #define I2C_SR1_OVR 0x00000800U
4706 #define I2C_SR1_PECERR 0x00001000U
4707 #define I2C_SR1_TIMEOUT 0x00004000U
4708 #define I2C_SR1_SMBALERT 0x00008000U
4710 /******************* Bit definition for I2C_SR2 register ********************/
4711 #define I2C_SR2_MSL 0x00000001U
4712 #define I2C_SR2_BUSY 0x00000002U
4713 #define I2C_SR2_TRA 0x00000004U
4714 #define I2C_SR2_GENCALL 0x00000010U
4715 #define I2C_SR2_SMBDEFAULT 0x00000020U
4716 #define I2C_SR2_SMBHOST 0x00000040U
4717 #define I2C_SR2_DUALF 0x00000080U
4718 #define I2C_SR2_PEC 0x0000FF00U
4720 /******************* Bit definition for I2C_CCR register ********************/
4721 #define I2C_CCR_CCR 0x00000FFFU
4722 #define I2C_CCR_DUTY 0x00004000U
4723 #define I2C_CCR_FS 0x00008000U
4725 /****************** Bit definition for I2C_TRISE register *******************/
4726 #define I2C_TRISE_TRISE 0x0000003FU
4728 /****************** Bit definition for I2C_FLTR register *******************/
4729 #define I2C_FLTR_DNF 0x0000000FU
4730 #define I2C_FLTR_ANOFF 0x00000010U
4732 /******************************************************************************/
4733 /* */
4734 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
4735 /* */
4736 /******************************************************************************/
4737 /******************* Bit definition for I2C_CR1 register *******************/
4738 #define FMPI2C_CR1_PE 0x00000001U
4739 #define FMPI2C_CR1_TXIE 0x00000002U
4740 #define FMPI2C_CR1_RXIE 0x00000004U
4741 #define FMPI2C_CR1_ADDRIE 0x00000008U
4742 #define FMPI2C_CR1_NACKIE 0x00000010U
4743 #define FMPI2C_CR1_STOPIE 0x00000020U
4744 #define FMPI2C_CR1_TCIE 0x00000040U
4745 #define FMPI2C_CR1_ERRIE 0x00000080U
4746 #define FMPI2C_CR1_DFN 0x00000F00U
4747 #define FMPI2C_CR1_ANFOFF 0x00001000U
4748 #define FMPI2C_CR1_TXDMAEN 0x00004000U
4749 #define FMPI2C_CR1_RXDMAEN 0x00008000U
4750 #define FMPI2C_CR1_SBC 0x00010000U
4751 #define FMPI2C_CR1_NOSTRETCH 0x00020000U
4752 #define FMPI2C_CR1_GCEN 0x00080000U
4753 #define FMPI2C_CR1_SMBHEN 0x00100000U
4754 #define FMPI2C_CR1_SMBDEN 0x00200000U
4755 #define FMPI2C_CR1_ALERTEN 0x00400000U
4756 #define FMPI2C_CR1_PECEN 0x00800000U
4758 /****************** Bit definition for I2C_CR2 register ********************/
4759 #define FMPI2C_CR2_SADD 0x000003FFU
4760 #define FMPI2C_CR2_RD_WRN 0x00000400U
4761 #define FMPI2C_CR2_ADD10 0x00000800U
4762 #define FMPI2C_CR2_HEAD10R 0x00001000U
4763 #define FMPI2C_CR2_START 0x00002000U
4764 #define FMPI2C_CR2_STOP 0x00004000U
4765 #define FMPI2C_CR2_NACK 0x00008000U
4766 #define FMPI2C_CR2_NBYTES 0x00FF0000U
4767 #define FMPI2C_CR2_RELOAD 0x01000000U
4768 #define FMPI2C_CR2_AUTOEND 0x02000000U
4769 #define FMPI2C_CR2_PECBYTE 0x04000000U
4771 /******************* Bit definition for I2C_OAR1 register ******************/
4772 #define FMPI2C_OAR1_OA1 0x000003FFU
4773 #define FMPI2C_OAR1_OA1MODE 0x00000400U
4774 #define FMPI2C_OAR1_OA1EN 0x00008000U
4776 /******************* Bit definition for I2C_OAR2 register ******************/
4777 #define FMPI2C_OAR2_OA2 0x000000FEU
4778 #define FMPI2C_OAR2_OA2MSK 0x00000700U
4779 #define FMPI2C_OAR2_OA2EN 0x00008000U
4781 /******************* Bit definition for I2C_TIMINGR register *******************/
4782 #define FMPI2C_TIMINGR_SCLL 0x000000FFU
4783 #define FMPI2C_TIMINGR_SCLH 0x0000FF00U
4784 #define FMPI2C_TIMINGR_SDADEL 0x000F0000U
4785 #define FMPI2C_TIMINGR_SCLDEL 0x00F00000U
4786 #define FMPI2C_TIMINGR_PRESC 0xF0000000U
4788 /******************* Bit definition for I2C_TIMEOUTR register *******************/
4789 #define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU
4790 #define FMPI2C_TIMEOUTR_TIDLE 0x00001000U
4791 #define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U
4792 #define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U
4793 #define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U
4795 /****************** Bit definition for I2C_ISR register *********************/
4796 #define FMPI2C_ISR_TXE 0x00000001U
4797 #define FMPI2C_ISR_TXIS 0x00000002U
4798 #define FMPI2C_ISR_RXNE 0x00000004U
4799 #define FMPI2C_ISR_ADDR 0x00000008U
4800 #define FMPI2C_ISR_NACKF 0x00000010U
4801 #define FMPI2C_ISR_STOPF 0x00000020U
4802 #define FMPI2C_ISR_TC 0x00000040U
4803 #define FMPI2C_ISR_TCR 0x00000080U
4804 #define FMPI2C_ISR_BERR 0x00000100U
4805 #define FMPI2C_ISR_ARLO 0x00000200U
4806 #define FMPI2C_ISR_OVR 0x00000400U
4807 #define FMPI2C_ISR_PECERR 0x00000800U
4808 #define FMPI2C_ISR_TIMEOUT 0x00001000U
4809 #define FMPI2C_ISR_ALERT 0x00002000U
4810 #define FMPI2C_ISR_BUSY 0x00008000U
4811 #define FMPI2C_ISR_DIR 0x00010000U
4812 #define FMPI2C_ISR_ADDCODE 0x00FE0000U
4814 /****************** Bit definition for I2C_ICR register *********************/
4815 #define FMPI2C_ICR_ADDRCF 0x00000008U
4816 #define FMPI2C_ICR_NACKCF 0x00000010U
4817 #define FMPI2C_ICR_STOPCF 0x00000020U
4818 #define FMPI2C_ICR_BERRCF 0x00000100U
4819 #define FMPI2C_ICR_ARLOCF 0x00000200U
4820 #define FMPI2C_ICR_OVRCF 0x00000400U
4821 #define FMPI2C_ICR_PECCF 0x00000800U
4822 #define FMPI2C_ICR_TIMOUTCF 0x00001000U
4823 #define FMPI2C_ICR_ALERTCF 0x00002000U
4825 /****************** Bit definition for I2C_PECR register *********************/
4826 #define FMPI2C_PECR_PEC 0x000000FFU
4828 /****************** Bit definition for I2C_RXDR register *********************/
4829 #define FMPI2C_RXDR_RXDATA 0x000000FFU
4831 /****************** Bit definition for I2C_TXDR register *********************/
4832 #define FMPI2C_TXDR_TXDATA 0x000000FFU
4834 /******************************************************************************/
4835 /* */
4836 /* Independent WATCHDOG */
4837 /* */
4838 /******************************************************************************/
4839 /******************* Bit definition for IWDG_KR register ********************/
4840 #define IWDG_KR_KEY 0xFFFFU
4842 /******************* Bit definition for IWDG_PR register ********************/
4843 #define IWDG_PR_PR 0x07U
4844 #define IWDG_PR_PR_0 0x01U
4845 #define IWDG_PR_PR_1 0x02U
4846 #define IWDG_PR_PR_2 0x04U
4848 /******************* Bit definition for IWDG_RLR register *******************/
4849 #define IWDG_RLR_RL 0x0FFFU
4851 /******************* Bit definition for IWDG_SR register ********************/
4852 #define IWDG_SR_PVU 0x01U
4853 #define IWDG_SR_RVU 0x02U
4856 /******************************************************************************/
4857 /* */
4858 /* Power Control */
4859 /* */
4860 /******************************************************************************/
4861 /******************** Bit definition for PWR_CR register ********************/
4862 #define PWR_CR_LPDS 0x00000001U
4863 #define PWR_CR_PDDS 0x00000002U
4864 #define PWR_CR_CWUF 0x00000004U
4865 #define PWR_CR_CSBF 0x00000008U
4866 #define PWR_CR_PVDE 0x00000010U
4868 #define PWR_CR_PLS 0x000000E0U
4869 #define PWR_CR_PLS_0 0x00000020U
4870 #define PWR_CR_PLS_1 0x00000040U
4871 #define PWR_CR_PLS_2 0x00000080U
4874 #define PWR_CR_PLS_LEV0 0x00000000U
4875 #define PWR_CR_PLS_LEV1 0x00000020U
4876 #define PWR_CR_PLS_LEV2 0x00000040U
4877 #define PWR_CR_PLS_LEV3 0x00000060U
4878 #define PWR_CR_PLS_LEV4 0x00000080U
4879 #define PWR_CR_PLS_LEV5 0x000000A0U
4880 #define PWR_CR_PLS_LEV6 0x000000C0U
4881 #define PWR_CR_PLS_LEV7 0x000000E0U
4882 #define PWR_CR_DBP 0x00000100U
4883 #define PWR_CR_FPDS 0x00000200U
4884 #define PWR_CR_LPLVDS 0x00000400U
4885 #define PWR_CR_MRLVDS 0x00000800U
4886 #define PWR_CR_ADCDC1 0x00002000U
4887 #define PWR_CR_VOS 0x0000C000U
4888 #define PWR_CR_VOS_0 0x00004000U
4889 #define PWR_CR_VOS_1 0x00008000U
4890 #define PWR_CR_ODEN 0x00010000U
4891 #define PWR_CR_ODSWEN 0x00020000U
4892 #define PWR_CR_UDEN 0x000C0000U
4893 #define PWR_CR_UDEN_0 0x00040000U
4894 #define PWR_CR_UDEN_1 0x00080000U
4895 #define PWR_CR_FMSSR 0x00100000U
4896 #define PWR_CR_FISSR 0x00200000U
4898 /* Legacy define */
4899 #define PWR_CR_PMODE PWR_CR_VOS
4900 #define PWR_CR_LPUDS PWR_CR_LPLVDS
4901 #define PWR_CR_MRUDS PWR_CR_MRLVDS
4903 /******************* Bit definition for PWR_CSR register ********************/
4904 #define PWR_CSR_WUF 0x00000001U
4905 #define PWR_CSR_SBF 0x00000002U
4906 #define PWR_CSR_PVDO 0x00000004U
4907 #define PWR_CSR_BRR 0x00000008U
4908 #define PWR_CSR_EWUP2 0x00000080U
4909 #define PWR_CSR_EWUP1 0x00000100U
4910 #define PWR_CSR_BRE 0x00000200U
4911 #define PWR_CSR_VOSRDY 0x00004000U
4912 #define PWR_CSR_ODRDY 0x00010000U
4913 #define PWR_CSR_ODSWRDY 0x00020000U
4914 #define PWR_CSR_UDSWRDY 0x000C0000U
4916 /* Legacy define */
4917 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
4918 
4919 /******************************************************************************/
4920 /* */
4921 /* QUADSPI */
4922 /* */
4923 /******************************************************************************/
4924 /***************** Bit definition for QUADSPI_CR register *******************/
4925 #define QUADSPI_CR_EN 0x00000001U
4926 #define QUADSPI_CR_ABORT 0x00000002U
4927 #define QUADSPI_CR_DMAEN 0x00000004U
4928 #define QUADSPI_CR_TCEN 0x00000008U
4929 #define QUADSPI_CR_SSHIFT 0x00000010U
4930 #define QUADSPI_CR_DFM 0x00000040U
4931 #define QUADSPI_CR_FSEL 0x00000080U
4932 #define QUADSPI_CR_FTHRES 0x00001F00U
4933 #define QUADSPI_CR_FTHRES_0 0x00000100U
4934 #define QUADSPI_CR_FTHRES_1 0x00000200U
4935 #define QUADSPI_CR_FTHRES_2 0x00000400U
4936 #define QUADSPI_CR_FTHRES_3 0x00000800U
4937 #define QUADSPI_CR_FTHRES_4 0x00001000U
4938 #define QUADSPI_CR_TEIE 0x00010000U
4939 #define QUADSPI_CR_TCIE 0x00020000U
4940 #define QUADSPI_CR_FTIE 0x00040000U
4941 #define QUADSPI_CR_SMIE 0x00080000U
4942 #define QUADSPI_CR_TOIE 0x00100000U
4943 #define QUADSPI_CR_APMS 0x00400000U
4944 #define QUADSPI_CR_PMM 0x00800000U
4945 #define QUADSPI_CR_PRESCALER 0xFF000000U
4946 #define QUADSPI_CR_PRESCALER_0 0x01000000U
4947 #define QUADSPI_CR_PRESCALER_1 0x02000000U
4948 #define QUADSPI_CR_PRESCALER_2 0x04000000U
4949 #define QUADSPI_CR_PRESCALER_3 0x08000000U
4950 #define QUADSPI_CR_PRESCALER_4 0x10000000U
4951 #define QUADSPI_CR_PRESCALER_5 0x20000000U
4952 #define QUADSPI_CR_PRESCALER_6 0x40000000U
4953 #define QUADSPI_CR_PRESCALER_7 0x80000000U
4955 /***************** Bit definition for QUADSPI_DCR register ******************/
4956 #define QUADSPI_DCR_CKMODE 0x00000001U
4957 #define QUADSPI_DCR_CSHT 0x00000700U
4958 #define QUADSPI_DCR_CSHT_0 0x00000100U
4959 #define QUADSPI_DCR_CSHT_1 0x00000200U
4960 #define QUADSPI_DCR_CSHT_2 0x00000400U
4961 #define QUADSPI_DCR_FSIZE 0x001F0000U
4962 #define QUADSPI_DCR_FSIZE_0 0x00010000U
4963 #define QUADSPI_DCR_FSIZE_1 0x00020000U
4964 #define QUADSPI_DCR_FSIZE_2 0x00040000U
4965 #define QUADSPI_DCR_FSIZE_3 0x00080000U
4966 #define QUADSPI_DCR_FSIZE_4 0x00100000U
4968 /****************** Bit definition for QUADSPI_SR register *******************/
4969 #define QUADSPI_SR_TEF 0x00000001U
4970 #define QUADSPI_SR_TCF 0x00000002U
4971 #define QUADSPI_SR_FTF 0x00000004U
4972 #define QUADSPI_SR_SMF 0x00000008U
4973 #define QUADSPI_SR_TOF 0x00000010U
4974 #define QUADSPI_SR_BUSY 0x00000020U
4975 #define QUADSPI_SR_FLEVEL 0x00003F00U
4976 #define QUADSPI_SR_FLEVEL_0 0x00000100U
4977 #define QUADSPI_SR_FLEVEL_1 0x00000200U
4978 #define QUADSPI_SR_FLEVEL_2 0x00000400U
4979 #define QUADSPI_SR_FLEVEL_3 0x00000800U
4980 #define QUADSPI_SR_FLEVEL_4 0x00001000U
4981 #define QUADSPI_SR_FLEVEL_5 0x00002000U
4983 /****************** Bit definition for QUADSPI_FCR register ******************/
4984 #define QUADSPI_FCR_CTEF 0x00000001U
4985 #define QUADSPI_FCR_CTCF 0x00000002U
4986 #define QUADSPI_FCR_CSMF 0x00000008U
4987 #define QUADSPI_FCR_CTOF 0x00000010U
4989 /****************** Bit definition for QUADSPI_DLR register ******************/
4990 #define QUADSPI_DLR_DL 0xFFFFFFFFU
4992 /****************** Bit definition for QUADSPI_CCR register ******************/
4993 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
4994 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
4995 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
4996 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
4997 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
4998 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
4999 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
5000 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
5001 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
5002 #define QUADSPI_CCR_IMODE 0x00000300U
5003 #define QUADSPI_CCR_IMODE_0 0x00000100U
5004 #define QUADSPI_CCR_IMODE_1 0x00000200U
5005 #define QUADSPI_CCR_ADMODE 0x00000C00U
5006 #define QUADSPI_CCR_ADMODE_0 0x00000400U
5007 #define QUADSPI_CCR_ADMODE_1 0x00000800U
5008 #define QUADSPI_CCR_ADSIZE 0x00003000U
5009 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
5010 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
5011 #define QUADSPI_CCR_ABMODE 0x0000C000U
5012 #define QUADSPI_CCR_ABMODE_0 0x00004000U
5013 #define QUADSPI_CCR_ABMODE_1 0x00008000U
5014 #define QUADSPI_CCR_ABSIZE 0x00030000U
5015 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
5016 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
5017 #define QUADSPI_CCR_DCYC 0x007C0000U
5018 #define QUADSPI_CCR_DCYC_0 0x00040000U
5019 #define QUADSPI_CCR_DCYC_1 0x00080000U
5020 #define QUADSPI_CCR_DCYC_2 0x00100000U
5021 #define QUADSPI_CCR_DCYC_3 0x00200000U
5022 #define QUADSPI_CCR_DCYC_4 0x00400000U
5023 #define QUADSPI_CCR_DMODE 0x03000000U
5024 #define QUADSPI_CCR_DMODE_0 0x01000000U
5025 #define QUADSPI_CCR_DMODE_1 0x02000000U
5026 #define QUADSPI_CCR_FMODE 0x0C000000U
5027 #define QUADSPI_CCR_FMODE_0 0x04000000U
5028 #define QUADSPI_CCR_FMODE_1 0x08000000U
5029 #define QUADSPI_CCR_SIOO 0x10000000U
5030 #define QUADSPI_CCR_DHHC 0x40000000U
5031 #define QUADSPI_CCR_DDRM 0x80000000U
5032 /****************** Bit definition for QUADSPI_AR register *******************/
5033 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
5035 /****************** Bit definition for QUADSPI_ABR register ******************/
5036 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
5038 /****************** Bit definition for QUADSPI_DR register *******************/
5039 #define QUADSPI_DR_DATA 0xFFFFFFFFU
5041 /****************** Bit definition for QUADSPI_PSMKR register ****************/
5042 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
5044 /****************** Bit definition for QUADSPI_PSMAR register ****************/
5045 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
5047 /****************** Bit definition for QUADSPI_PIR register *****************/
5048 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
5050 /****************** Bit definition for QUADSPI_LPTR register *****************/
5051 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
5053 /******************************************************************************/
5054 /* */
5055 /* Reset and Clock Control */
5056 /* */
5057 /******************************************************************************/
5058 /******************** Bit definition for RCC_CR register ********************/
5059 #define RCC_CR_HSION 0x00000001U
5060 #define RCC_CR_HSIRDY 0x00000002U
5061 
5062 #define RCC_CR_HSITRIM 0x000000F8U
5063 #define RCC_CR_HSITRIM_0 0x00000008U
5064 #define RCC_CR_HSITRIM_1 0x00000010U
5065 #define RCC_CR_HSITRIM_2 0x00000020U
5066 #define RCC_CR_HSITRIM_3 0x00000040U
5067 #define RCC_CR_HSITRIM_4 0x00000080U
5069 #define RCC_CR_HSICAL 0x0000FF00U
5070 #define RCC_CR_HSICAL_0 0x00000100U
5071 #define RCC_CR_HSICAL_1 0x00000200U
5072 #define RCC_CR_HSICAL_2 0x00000400U
5073 #define RCC_CR_HSICAL_3 0x00000800U
5074 #define RCC_CR_HSICAL_4 0x00001000U
5075 #define RCC_CR_HSICAL_5 0x00002000U
5076 #define RCC_CR_HSICAL_6 0x00004000U
5077 #define RCC_CR_HSICAL_7 0x00008000U
5079 #define RCC_CR_HSEON 0x00010000U
5080 #define RCC_CR_HSERDY 0x00020000U
5081 #define RCC_CR_HSEBYP 0x00040000U
5082 #define RCC_CR_CSSON 0x00080000U
5083 #define RCC_CR_PLLON 0x01000000U
5084 #define RCC_CR_PLLRDY 0x02000000U
5085 #define RCC_CR_PLLI2SON 0x04000000U
5086 #define RCC_CR_PLLI2SRDY 0x08000000U
5087 #define RCC_CR_PLLSAION 0x10000000U
5088 #define RCC_CR_PLLSAIRDY 0x20000000U
5089 
5090 /******************** Bit definition for RCC_PLLCFGR register ***************/
5091 #define RCC_PLLCFGR_PLLM 0x0000003FU
5092 #define RCC_PLLCFGR_PLLM_0 0x00000001U
5093 #define RCC_PLLCFGR_PLLM_1 0x00000002U
5094 #define RCC_PLLCFGR_PLLM_2 0x00000004U
5095 #define RCC_PLLCFGR_PLLM_3 0x00000008U
5096 #define RCC_PLLCFGR_PLLM_4 0x00000010U
5097 #define RCC_PLLCFGR_PLLM_5 0x00000020U
5098 
5099 #define RCC_PLLCFGR_PLLN 0x00007FC0U
5100 #define RCC_PLLCFGR_PLLN_0 0x00000040U
5101 #define RCC_PLLCFGR_PLLN_1 0x00000080U
5102 #define RCC_PLLCFGR_PLLN_2 0x00000100U
5103 #define RCC_PLLCFGR_PLLN_3 0x00000200U
5104 #define RCC_PLLCFGR_PLLN_4 0x00000400U
5105 #define RCC_PLLCFGR_PLLN_5 0x00000800U
5106 #define RCC_PLLCFGR_PLLN_6 0x00001000U
5107 #define RCC_PLLCFGR_PLLN_7 0x00002000U
5108 #define RCC_PLLCFGR_PLLN_8 0x00004000U
5109 
5110 #define RCC_PLLCFGR_PLLP 0x00030000U
5111 #define RCC_PLLCFGR_PLLP_0 0x00010000U
5112 #define RCC_PLLCFGR_PLLP_1 0x00020000U
5113 
5114 #define RCC_PLLCFGR_PLLSRC 0x00400000U
5115 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
5116 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
5117 
5118 #define RCC_PLLCFGR_PLLQ 0x0F000000U
5119 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
5120 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
5121 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
5122 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
5123 
5124 #define RCC_PLLCFGR_PLLR 0x70000000U
5125 #define RCC_PLLCFGR_PLLR_0 0x10000000U
5126 #define RCC_PLLCFGR_PLLR_1 0x20000000U
5127 #define RCC_PLLCFGR_PLLR_2 0x40000000U
5128 
5129 
5130 /******************** Bit definition for RCC_CFGR register ******************/
5132 #define RCC_CFGR_SW 0x00000003U
5133 #define RCC_CFGR_SW_0 0x00000001U
5134 #define RCC_CFGR_SW_1 0x00000002U
5136 #define RCC_CFGR_SW_HSI 0x00000000U
5137 #define RCC_CFGR_SW_HSE 0x00000001U
5138 #define RCC_CFGR_SW_PLL 0x00000002U
5139 #define RCC_CFGR_SW_PLLR 0x00000003U
5142 #define RCC_CFGR_SWS 0x0000000CU
5143 #define RCC_CFGR_SWS_0 0x00000004U
5144 #define RCC_CFGR_SWS_1 0x00000008U
5146 #define RCC_CFGR_SWS_HSI 0x00000000U
5147 #define RCC_CFGR_SWS_HSE 0x00000004U
5148 #define RCC_CFGR_SWS_PLL 0x00000008U
5149 #define RCC_CFGR_SWS_PLLR 0x0000000CU
5152 #define RCC_CFGR_HPRE 0x000000F0U
5153 #define RCC_CFGR_HPRE_0 0x00000010U
5154 #define RCC_CFGR_HPRE_1 0x00000020U
5155 #define RCC_CFGR_HPRE_2 0x00000040U
5156 #define RCC_CFGR_HPRE_3 0x00000080U
5158 #define RCC_CFGR_HPRE_DIV1 0x00000000U
5159 #define RCC_CFGR_HPRE_DIV2 0x00000080U
5160 #define RCC_CFGR_HPRE_DIV4 0x00000090U
5161 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
5162 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
5163 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
5164 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
5165 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
5166 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
5169 #define RCC_CFGR_PPRE1 0x00001C00U
5170 #define RCC_CFGR_PPRE1_0 0x00000400U
5171 #define RCC_CFGR_PPRE1_1 0x00000800U
5172 #define RCC_CFGR_PPRE1_2 0x00001000U
5174 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
5175 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
5176 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
5177 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
5178 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
5181 #define RCC_CFGR_PPRE2 0x0000E000U
5182 #define RCC_CFGR_PPRE2_0 0x00002000U
5183 #define RCC_CFGR_PPRE2_1 0x00004000U
5184 #define RCC_CFGR_PPRE2_2 0x00008000U
5186 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
5187 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
5188 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
5189 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
5190 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
5193 #define RCC_CFGR_RTCPRE 0x001F0000U
5194 #define RCC_CFGR_RTCPRE_0 0x00010000U
5195 #define RCC_CFGR_RTCPRE_1 0x00020000U
5196 #define RCC_CFGR_RTCPRE_2 0x00040000U
5197 #define RCC_CFGR_RTCPRE_3 0x00080000U
5198 #define RCC_CFGR_RTCPRE_4 0x00100000U
5199 
5201 #define RCC_CFGR_MCO1 0x00600000U
5202 #define RCC_CFGR_MCO1_0 0x00200000U
5203 #define RCC_CFGR_MCO1_1 0x00400000U
5204 
5205 #define RCC_CFGR_I2SSRC 0x00800000U
5206 
5207 #define RCC_CFGR_MCO1PRE 0x07000000U
5208 #define RCC_CFGR_MCO1PRE_0 0x01000000U
5209 #define RCC_CFGR_MCO1PRE_1 0x02000000U
5210 #define RCC_CFGR_MCO1PRE_2 0x04000000U
5211 
5212 #define RCC_CFGR_MCO2PRE 0x38000000U
5213 #define RCC_CFGR_MCO2PRE_0 0x08000000U
5214 #define RCC_CFGR_MCO2PRE_1 0x10000000U
5215 #define RCC_CFGR_MCO2PRE_2 0x20000000U
5216 
5217 #define RCC_CFGR_MCO2 0xC0000000U
5218 #define RCC_CFGR_MCO2_0 0x40000000U
5219 #define RCC_CFGR_MCO2_1 0x80000000U
5220 
5221 /******************** Bit definition for RCC_CIR register *******************/
5222 #define RCC_CIR_LSIRDYF 0x00000001U
5223 #define RCC_CIR_LSERDYF 0x00000002U
5224 #define RCC_CIR_HSIRDYF 0x00000004U
5225 #define RCC_CIR_HSERDYF 0x00000008U
5226 #define RCC_CIR_PLLRDYF 0x00000010U
5227 #define RCC_CIR_PLLI2SRDYF 0x00000020U
5228 #define RCC_CIR_PLLSAIRDYF 0x00000040U
5229 #define RCC_CIR_CSSF 0x00000080U
5230 #define RCC_CIR_LSIRDYIE 0x00000100U
5231 #define RCC_CIR_LSERDYIE 0x00000200U
5232 #define RCC_CIR_HSIRDYIE 0x00000400U
5233 #define RCC_CIR_HSERDYIE 0x00000800U
5234 #define RCC_CIR_PLLRDYIE 0x00001000U
5235 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
5236 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
5237 #define RCC_CIR_LSIRDYC 0x00010000U
5238 #define RCC_CIR_LSERDYC 0x00020000U
5239 #define RCC_CIR_HSIRDYC 0x00040000U
5240 #define RCC_CIR_HSERDYC 0x00080000U
5241 #define RCC_CIR_PLLRDYC 0x00100000U
5242 #define RCC_CIR_PLLI2SRDYC 0x00200000U
5243 #define RCC_CIR_PLLSAIRDYC 0x00400000U
5244 #define RCC_CIR_CSSC 0x00800000U
5245 
5246 /******************** Bit definition for RCC_AHB1RSTR register **************/
5247 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
5248 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
5249 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
5250 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
5251 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
5252 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
5253 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
5254 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
5255 #define RCC_AHB1RSTR_CRCRST 0x00001000U
5256 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
5257 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
5258 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
5259 
5260 /******************** Bit definition for RCC_AHB2RSTR register **************/
5261 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
5262 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
5263 
5264 /******************** Bit definition for RCC_AHB3RSTR register **************/
5265 #define RCC_AHB3RSTR_FMCRST 0x00000001U
5266 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
5267 
5268 /******************** Bit definition for RCC_APB1RSTR register **************/
5269 #define RCC_APB1RSTR_TIM2RST 0x00000001U
5270 #define RCC_APB1RSTR_TIM3RST 0x00000002U
5271 #define RCC_APB1RSTR_TIM4RST 0x00000004U
5272 #define RCC_APB1RSTR_TIM5RST 0x00000008U
5273 #define RCC_APB1RSTR_TIM6RST 0x00000010U
5274 #define RCC_APB1RSTR_TIM7RST 0x00000020U
5275 #define RCC_APB1RSTR_TIM12RST 0x00000040U
5276 #define RCC_APB1RSTR_TIM13RST 0x00000080U
5277 #define RCC_APB1RSTR_TIM14RST 0x00000100U
5278 #define RCC_APB1RSTR_WWDGRST 0x00000800U
5279 #define RCC_APB1RSTR_SPI2RST 0x00004000U
5280 #define RCC_APB1RSTR_SPI3RST 0x00008000U
5281 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
5282 #define RCC_APB1RSTR_USART2RST 0x00020000U
5283 #define RCC_APB1RSTR_USART3RST 0x00040000U
5284 #define RCC_APB1RSTR_UART4RST 0x00080000U
5285 #define RCC_APB1RSTR_UART5RST 0x00100000U
5286 #define RCC_APB1RSTR_I2C1RST 0x00200000U
5287 #define RCC_APB1RSTR_I2C2RST 0x00400000U
5288 #define RCC_APB1RSTR_I2C3RST 0x00800000U
5289 #define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
5290 #define RCC_APB1RSTR_CAN1RST 0x02000000U
5291 #define RCC_APB1RSTR_CAN2RST 0x04000000U
5292 #define RCC_APB1RSTR_CECRST 0x08000000U
5293 #define RCC_APB1RSTR_PWRRST 0x10000000U
5294 #define RCC_APB1RSTR_DACRST 0x20000000U
5295 
5296 /******************** Bit definition for RCC_APB2RSTR register **************/
5297 #define RCC_APB2RSTR_TIM1RST 0x00000001U
5298 #define RCC_APB2RSTR_TIM8RST 0x00000002U
5299 #define RCC_APB2RSTR_USART1RST 0x00000010U
5300 #define RCC_APB2RSTR_USART6RST 0x00000020U
5301 #define RCC_APB2RSTR_ADCRST 0x00000100U
5302 #define RCC_APB2RSTR_SDIORST 0x00000800U
5303 #define RCC_APB2RSTR_SPI1RST 0x00001000U
5304 #define RCC_APB2RSTR_SPI4RST 0x00002000U
5305 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
5306 #define RCC_APB2RSTR_TIM9RST 0x00010000U
5307 #define RCC_APB2RSTR_TIM10RST 0x00020000U
5308 #define RCC_APB2RSTR_TIM11RST 0x00040000U
5309 #define RCC_APB2RSTR_SAI1RST 0x00400000U
5310 #define RCC_APB2RSTR_SAI2RST 0x00800000U
5311 
5312 /* Old SPI1RST bit definition, maintained for legacy purpose */
5313 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5314 
5315 /******************** Bit definition for RCC_AHB1ENR register ***************/
5316 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
5317 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
5318 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
5319 #define RCC_AHB1ENR_GPIODEN 0x00000008U
5320 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
5321 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
5322 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
5323 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
5324 
5325 #define RCC_AHB1ENR_CRCEN 0x00001000U
5326 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
5327 #define RCC_AHB1ENR_DMA1EN 0x00200000U
5328 #define RCC_AHB1ENR_DMA2EN 0x00400000U
5329 
5330 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
5331 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
5332 
5333 /******************** Bit definition for RCC_AHB2ENR register ***************/
5334 #define RCC_AHB2ENR_DCMIEN 0x00000001U
5335 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
5336 
5337 /******************** Bit definition for RCC_AHB3ENR register ***************/
5338 #define RCC_AHB3ENR_FMCEN 0x00000001U
5339 #define RCC_AHB3ENR_QSPIEN 0x00000002U
5340 
5341 /******************** Bit definition for RCC_APB1ENR register ***************/
5342 #define RCC_APB1ENR_TIM2EN 0x00000001U
5343 #define RCC_APB1ENR_TIM3EN 0x00000002U
5344 #define RCC_APB1ENR_TIM4EN 0x00000004U
5345 #define RCC_APB1ENR_TIM5EN 0x00000008U
5346 #define RCC_APB1ENR_TIM6EN 0x00000010U
5347 #define RCC_APB1ENR_TIM7EN 0x00000020U
5348 #define RCC_APB1ENR_TIM12EN 0x00000040U
5349 #define RCC_APB1ENR_TIM13EN 0x00000080U
5350 #define RCC_APB1ENR_TIM14EN 0x00000100U
5351 #define RCC_APB1ENR_WWDGEN 0x00000800U
5352 #define RCC_APB1ENR_SPI2EN 0x00004000U
5353 #define RCC_APB1ENR_SPI3EN 0x00008000U
5354 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
5355 #define RCC_APB1ENR_USART2EN 0x00020000U
5356 #define RCC_APB1ENR_USART3EN 0x00040000U
5357 #define RCC_APB1ENR_UART4EN 0x00080000U
5358 #define RCC_APB1ENR_UART5EN 0x00100000U
5359 #define RCC_APB1ENR_I2C1EN 0x00200000U
5360 #define RCC_APB1ENR_I2C2EN 0x00400000U
5361 #define RCC_APB1ENR_I2C3EN 0x00800000U
5362 #define RCC_APB1ENR_FMPI2C1EN 0x01000000U
5363 #define RCC_APB1ENR_CAN1EN 0x02000000U
5364 #define RCC_APB1ENR_CAN2EN 0x04000000U
5365 #define RCC_APB1ENR_CECEN 0x08000000U
5366 #define RCC_APB1ENR_PWREN 0x10000000U
5367 #define RCC_APB1ENR_DACEN 0x20000000U
5368 
5369 /******************** Bit definition for RCC_APB2ENR register ***************/
5370 #define RCC_APB2ENR_TIM1EN 0x00000001U
5371 #define RCC_APB2ENR_TIM8EN 0x00000002U
5372 #define RCC_APB2ENR_USART1EN 0x00000010U
5373 #define RCC_APB2ENR_USART6EN 0x00000020U
5374 #define RCC_APB2ENR_ADC1EN 0x00000100U
5375 #define RCC_APB2ENR_ADC2EN 0x00000200U
5376 #define RCC_APB2ENR_ADC3EN 0x00000400U
5377 #define RCC_APB2ENR_SDIOEN 0x00000800U
5378 #define RCC_APB2ENR_SPI1EN 0x00001000U
5379 #define RCC_APB2ENR_SPI4EN 0x00002000U
5380 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
5381 #define RCC_APB2ENR_TIM9EN 0x00010000U
5382 #define RCC_APB2ENR_TIM10EN 0x00020000U
5383 #define RCC_APB2ENR_TIM11EN 0x00040000U
5384 #define RCC_APB2ENR_SAI1EN 0x00400000U
5385 #define RCC_APB2ENR_SAI2EN 0x00800000U
5386 
5387 /******************** Bit definition for RCC_AHB1LPENR register *************/
5388 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
5389 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
5390 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
5391 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
5392 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
5393 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
5394 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
5395 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
5396 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
5397 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
5398 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
5399 
5400 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
5401 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
5402 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
5403 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
5404 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
5405 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
5406 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
5407 
5408 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
5409 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
5410 
5411 /******************** Bit definition for RCC_AHB2LPENR register *************/
5412 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
5413 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
5414 
5415 /******************** Bit definition for RCC_AHB3LPENR register *************/
5416 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
5417 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
5418 
5419 /******************** Bit definition for RCC_APB1LPENR register *************/
5420 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
5421 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
5422 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
5423 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
5424 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
5425 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
5426 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
5427 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
5428 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
5429 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
5430 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
5431 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
5432 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
5433 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
5434 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
5435 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
5436 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
5437 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
5438 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
5439 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
5440 #define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
5441 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
5442 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
5443 #define RCC_APB1LPENR_CECLPEN 0x08000000U
5444 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
5445 #define RCC_APB1LPENR_DACLPEN 0x20000000U
5446 
5447 /******************** Bit definition for RCC_APB2LPENR register *************/
5448 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
5449 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
5450 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
5451 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
5452 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
5453 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
5454 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
5455 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
5456 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
5457 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
5458 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
5459 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
5460 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
5461 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
5462 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
5463 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
5464 
5465 /******************** Bit definition for RCC_BDCR register ******************/
5466 #define RCC_BDCR_LSEON 0x00000001U
5467 #define RCC_BDCR_LSERDY 0x00000002U
5468 #define RCC_BDCR_LSEBYP 0x00000004U
5469 #define RCC_BDCR_LSEMOD 0x00000008U
5470 
5471 #define RCC_BDCR_RTCSEL 0x00000300U
5472 #define RCC_BDCR_RTCSEL_0 0x00000100U
5473 #define RCC_BDCR_RTCSEL_1 0x00000200U
5474 
5475 #define RCC_BDCR_RTCEN 0x00008000U
5476 #define RCC_BDCR_BDRST 0x00010000U
5477 
5478 /******************** Bit definition for RCC_CSR register *******************/
5479 #define RCC_CSR_LSION 0x00000001U
5480 #define RCC_CSR_LSIRDY 0x00000002U
5481 #define RCC_CSR_RMVF 0x01000000U
5482 #define RCC_CSR_BORRSTF 0x02000000U
5483 #define RCC_CSR_PADRSTF 0x04000000U
5484 #define RCC_CSR_PORRSTF 0x08000000U
5485 #define RCC_CSR_SFTRSTF 0x10000000U
5486 #define RCC_CSR_WDGRSTF 0x20000000U
5487 #define RCC_CSR_WWDGRSTF 0x40000000U
5488 #define RCC_CSR_LPWRRSTF 0x80000000U
5489 
5490 /******************** Bit definition for RCC_SSCGR register *****************/
5491 #define RCC_SSCGR_MODPER 0x00001FFFU
5492 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
5493 #define RCC_SSCGR_SPREADSEL 0x40000000U
5494 #define RCC_SSCGR_SSCGEN 0x80000000U
5495 
5496 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5497 #define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
5498 #define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
5499 #define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
5500 #define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
5501 #define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
5502 #define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
5503 #define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
5504 
5505 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
5506 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
5507 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
5508 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
5509 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
5510 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
5511 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
5512 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
5513 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
5514 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
5515 
5516 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
5517 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
5518 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
5519 
5520 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
5521 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
5522 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
5523 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
5524 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
5525 
5526 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
5527 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
5528 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
5529 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
5530 
5531 
5532 /******************** Bit definition for RCC_PLLSAICFGR register ************/
5533 #define RCC_PLLSAICFGR_PLLSAIM 0x0000003FU
5534 #define RCC_PLLSAICFGR_PLLSAIM_0 0x00000001U
5535 #define RCC_PLLSAICFGR_PLLSAIM_1 0x00000002U
5536 #define RCC_PLLSAICFGR_PLLSAIM_2 0x00000004U
5537 #define RCC_PLLSAICFGR_PLLSAIM_3 0x00000008U
5538 #define RCC_PLLSAICFGR_PLLSAIM_4 0x00000010U
5539 #define RCC_PLLSAICFGR_PLLSAIM_5 0x00000020U
5540 
5541 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
5542 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
5543 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
5544 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
5545 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
5546 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
5547 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
5548 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
5549 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
5550 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
5551 
5552 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
5553 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
5554 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
5555 
5556 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
5557 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
5558 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
5559 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
5560 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
5561 
5562 /******************** Bit definition for RCC_DCKCFGR register ***************/
5563 #define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
5564 #define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
5565 #define RCC_DCKCFGR_SAI1SRC 0x00300000U
5566 #define RCC_DCKCFGR_SAI1SRC_0 0x00100000U
5567 #define RCC_DCKCFGR_SAI1SRC_1 0x00200000U
5568 #define RCC_DCKCFGR_SAI2SRC 0x00C00000U
5569 #define RCC_DCKCFGR_SAI2SRC_0 0x00400000U
5570 #define RCC_DCKCFGR_SAI2SRC_1 0x00800000U
5571 #define RCC_DCKCFGR_TIMPRE 0x01000000U
5572 #define RCC_DCKCFGR_I2S1SRC 0x06000000U
5573 #define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
5574 #define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
5575 #define RCC_DCKCFGR_I2S2SRC 0x18000000U
5576 #define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
5577 #define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
5578 
5579 /******************** Bit definition for RCC_CKGATENR register ***************/
5580 #define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
5581 #define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
5582 #define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
5583 #define RCC_CKGATENR_SPARE_CKEN 0x00000008U
5584 #define RCC_CKGATENR_SRAM_CKEN 0x00000010U
5585 #define RCC_CKGATENR_FLITF_CKEN 0x00000020U
5586 #define RCC_CKGATENR_RCC_CKEN 0x00000040U
5587 
5588 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
5589 #define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
5590 #define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
5591 #define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
5592 #define RCC_DCKCFGR2_CECSEL 0x04000000U
5593 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
5594 #define RCC_DCKCFGR2_SDIOSEL 0x10000000U
5595 #define RCC_DCKCFGR2_SPDIFRXSEL 0x20000000U
5596 
5597 /******************************************************************************/
5598 /* */
5599 /* Real-Time Clock (RTC) */
5600 /* */
5601 /******************************************************************************/
5602 /******************** Bits definition for RTC_TR register *******************/
5603 #define RTC_TR_PM 0x00400000U
5604 #define RTC_TR_HT 0x00300000U
5605 #define RTC_TR_HT_0 0x00100000U
5606 #define RTC_TR_HT_1 0x00200000U
5607 #define RTC_TR_HU 0x000F0000U
5608 #define RTC_TR_HU_0 0x00010000U
5609 #define RTC_TR_HU_1 0x00020000U
5610 #define RTC_TR_HU_2 0x00040000U
5611 #define RTC_TR_HU_3 0x00080000U
5612 #define RTC_TR_MNT 0x00007000U
5613 #define RTC_TR_MNT_0 0x00001000U
5614 #define RTC_TR_MNT_1 0x00002000U
5615 #define RTC_TR_MNT_2 0x00004000U
5616 #define RTC_TR_MNU 0x00000F00U
5617 #define RTC_TR_MNU_0 0x00000100U
5618 #define RTC_TR_MNU_1 0x00000200U
5619 #define RTC_TR_MNU_2 0x00000400U
5620 #define RTC_TR_MNU_3 0x00000800U
5621 #define RTC_TR_ST 0x00000070U
5622 #define RTC_TR_ST_0 0x00000010U
5623 #define RTC_TR_ST_1 0x00000020U
5624 #define RTC_TR_ST_2 0x00000040U
5625 #define RTC_TR_SU 0x0000000FU
5626 #define RTC_TR_SU_0 0x00000001U
5627 #define RTC_TR_SU_1 0x00000002U
5628 #define RTC_TR_SU_2 0x00000004U
5629 #define RTC_TR_SU_3 0x00000008U
5630 
5631 /******************** Bits definition for RTC_DR register *******************/
5632 #define RTC_DR_YT 0x00F00000U
5633 #define RTC_DR_YT_0 0x00100000U
5634 #define RTC_DR_YT_1 0x00200000U
5635 #define RTC_DR_YT_2 0x00400000U
5636 #define RTC_DR_YT_3 0x00800000U
5637 #define RTC_DR_YU 0x000F0000U
5638 #define RTC_DR_YU_0 0x00010000U
5639 #define RTC_DR_YU_1 0x00020000U
5640 #define RTC_DR_YU_2 0x00040000U
5641 #define RTC_DR_YU_3 0x00080000U
5642 #define RTC_DR_WDU 0x0000E000U
5643 #define RTC_DR_WDU_0 0x00002000U
5644 #define RTC_DR_WDU_1 0x00004000U
5645 #define RTC_DR_WDU_2 0x00008000U
5646 #define RTC_DR_MT 0x00001000U
5647 #define RTC_DR_MU 0x00000F00U
5648 #define RTC_DR_MU_0 0x00000100U
5649 #define RTC_DR_MU_1 0x00000200U
5650 #define RTC_DR_MU_2 0x00000400U
5651 #define RTC_DR_MU_3 0x00000800U
5652 #define RTC_DR_DT 0x00000030U
5653 #define RTC_DR_DT_0 0x00000010U
5654 #define RTC_DR_DT_1 0x00000020U
5655 #define RTC_DR_DU 0x0000000FU
5656 #define RTC_DR_DU_0 0x00000001U
5657 #define RTC_DR_DU_1 0x00000002U
5658 #define RTC_DR_DU_2 0x00000004U
5659 #define RTC_DR_DU_3 0x00000008U
5660 
5661 /******************** Bits definition for RTC_CR register *******************/
5662 #define RTC_CR_COE 0x00800000U
5663 #define RTC_CR_OSEL 0x00600000U
5664 #define RTC_CR_OSEL_0 0x00200000U
5665 #define RTC_CR_OSEL_1 0x00400000U
5666 #define RTC_CR_POL 0x00100000U
5667 #define RTC_CR_COSEL 0x00080000U
5668 #define RTC_CR_BCK 0x00040000U
5669 #define RTC_CR_SUB1H 0x00020000U
5670 #define RTC_CR_ADD1H 0x00010000U
5671 #define RTC_CR_TSIE 0x00008000U
5672 #define RTC_CR_WUTIE 0x00004000U
5673 #define RTC_CR_ALRBIE 0x00002000U
5674 #define RTC_CR_ALRAIE 0x00001000U
5675 #define RTC_CR_TSE 0x00000800U
5676 #define RTC_CR_WUTE 0x00000400U
5677 #define RTC_CR_ALRBE 0x00000200U
5678 #define RTC_CR_ALRAE 0x00000100U
5679 #define RTC_CR_DCE 0x00000080U
5680 #define RTC_CR_FMT 0x00000040U
5681 #define RTC_CR_BYPSHAD 0x00000020U
5682 #define RTC_CR_REFCKON 0x00000010U
5683 #define RTC_CR_TSEDGE 0x00000008U
5684 #define RTC_CR_WUCKSEL 0x00000007U
5685 #define RTC_CR_WUCKSEL_0 0x00000001U
5686 #define RTC_CR_WUCKSEL_1 0x00000002U
5687 #define RTC_CR_WUCKSEL_2 0x00000004U
5688 
5689 /******************** Bits definition for RTC_ISR register ******************/
5690 #define RTC_ISR_RECALPF 0x00010000U
5691 #define RTC_ISR_TAMP1F 0x00002000U
5692 #define RTC_ISR_TAMP2F 0x00004000U
5693 #define RTC_ISR_TSOVF 0x00001000U
5694 #define RTC_ISR_TSF 0x00000800U
5695 #define RTC_ISR_WUTF 0x00000400U
5696 #define RTC_ISR_ALRBF 0x00000200U
5697 #define RTC_ISR_ALRAF 0x00000100U
5698 #define RTC_ISR_INIT 0x00000080U
5699 #define RTC_ISR_INITF 0x00000040U
5700 #define RTC_ISR_RSF 0x00000020U
5701 #define RTC_ISR_INITS 0x00000010U
5702 #define RTC_ISR_SHPF 0x00000008U
5703 #define RTC_ISR_WUTWF 0x00000004U
5704 #define RTC_ISR_ALRBWF 0x00000002U
5705 #define RTC_ISR_ALRAWF 0x00000001U
5706 
5707 /******************** Bits definition for RTC_PRER register *****************/
5708 #define RTC_PRER_PREDIV_A 0x007F0000U
5709 #define RTC_PRER_PREDIV_S 0x00007FFFU
5710 
5711 /******************** Bits definition for RTC_WUTR register *****************/
5712 #define RTC_WUTR_WUT 0x0000FFFFU
5713 
5714 /******************** Bits definition for RTC_CALIBR register ***************/
5715 #define RTC_CALIBR_DCS 0x00000080U
5716 #define RTC_CALIBR_DC 0x0000001FU
5717 
5718 /******************** Bits definition for RTC_ALRMAR register ***************/
5719 #define RTC_ALRMAR_MSK4 0x80000000U
5720 #define RTC_ALRMAR_WDSEL 0x40000000U
5721 #define RTC_ALRMAR_DT 0x30000000U
5722 #define RTC_ALRMAR_DT_0 0x10000000U
5723 #define RTC_ALRMAR_DT_1 0x20000000U
5724 #define RTC_ALRMAR_DU 0x0F000000U
5725 #define RTC_ALRMAR_DU_0 0x01000000U
5726 #define RTC_ALRMAR_DU_1 0x02000000U
5727 #define RTC_ALRMAR_DU_2 0x04000000U
5728 #define RTC_ALRMAR_DU_3 0x08000000U
5729 #define RTC_ALRMAR_MSK3 0x00800000U
5730 #define RTC_ALRMAR_PM 0x00400000U
5731 #define RTC_ALRMAR_HT 0x00300000U
5732 #define RTC_ALRMAR_HT_0 0x00100000U
5733 #define RTC_ALRMAR_HT_1 0x00200000U
5734 #define RTC_ALRMAR_HU 0x000F0000U
5735 #define RTC_ALRMAR_HU_0 0x00010000U
5736 #define RTC_ALRMAR_HU_1 0x00020000U
5737 #define RTC_ALRMAR_HU_2 0x00040000U
5738 #define RTC_ALRMAR_HU_3 0x00080000U
5739 #define RTC_ALRMAR_MSK2 0x00008000U
5740 #define RTC_ALRMAR_MNT 0x00007000U
5741 #define RTC_ALRMAR_MNT_0 0x00001000U
5742 #define RTC_ALRMAR_MNT_1 0x00002000U
5743 #define RTC_ALRMAR_MNT_2 0x00004000U
5744 #define RTC_ALRMAR_MNU 0x00000F00U
5745 #define RTC_ALRMAR_MNU_0 0x00000100U
5746 #define RTC_ALRMAR_MNU_1 0x00000200U
5747 #define RTC_ALRMAR_MNU_2 0x00000400U
5748 #define RTC_ALRMAR_MNU_3 0x00000800U
5749 #define RTC_ALRMAR_MSK1 0x00000080U
5750 #define RTC_ALRMAR_ST 0x00000070U
5751 #define RTC_ALRMAR_ST_0 0x00000010U
5752 #define RTC_ALRMAR_ST_1 0x00000020U
5753 #define RTC_ALRMAR_ST_2 0x00000040U
5754 #define RTC_ALRMAR_SU 0x0000000FU
5755 #define RTC_ALRMAR_SU_0 0x00000001U
5756 #define RTC_ALRMAR_SU_1 0x00000002U
5757 #define RTC_ALRMAR_SU_2 0x00000004U
5758 #define RTC_ALRMAR_SU_3 0x00000008U
5759 
5760 /******************** Bits definition for RTC_ALRMBR register ***************/
5761 #define RTC_ALRMBR_MSK4 0x80000000U
5762 #define RTC_ALRMBR_WDSEL 0x40000000U
5763 #define RTC_ALRMBR_DT 0x30000000U
5764 #define RTC_ALRMBR_DT_0 0x10000000U
5765 #define RTC_ALRMBR_DT_1 0x20000000U
5766 #define RTC_ALRMBR_DU 0x0F000000U
5767 #define RTC_ALRMBR_DU_0 0x01000000U
5768 #define RTC_ALRMBR_DU_1 0x02000000U
5769 #define RTC_ALRMBR_DU_2 0x04000000U
5770 #define RTC_ALRMBR_DU_3 0x08000000U
5771 #define RTC_ALRMBR_MSK3 0x00800000U
5772 #define RTC_ALRMBR_PM 0x00400000U
5773 #define RTC_ALRMBR_HT 0x00300000U
5774 #define RTC_ALRMBR_HT_0 0x00100000U
5775 #define RTC_ALRMBR_HT_1 0x00200000U
5776 #define RTC_ALRMBR_HU 0x000F0000U
5777 #define RTC_ALRMBR_HU_0 0x00010000U
5778 #define RTC_ALRMBR_HU_1 0x00020000U
5779 #define RTC_ALRMBR_HU_2 0x00040000U
5780 #define RTC_ALRMBR_HU_3 0x00080000U
5781 #define RTC_ALRMBR_MSK2 0x00008000U
5782 #define RTC_ALRMBR_MNT 0x00007000U
5783 #define RTC_ALRMBR_MNT_0 0x00001000U
5784 #define RTC_ALRMBR_MNT_1 0x00002000U
5785 #define RTC_ALRMBR_MNT_2 0x00004000U
5786 #define RTC_ALRMBR_MNU 0x00000F00U
5787 #define RTC_ALRMBR_MNU_0 0x00000100U
5788 #define RTC_ALRMBR_MNU_1 0x00000200U
5789 #define RTC_ALRMBR_MNU_2 0x00000400U
5790 #define RTC_ALRMBR_MNU_3 0x00000800U
5791 #define RTC_ALRMBR_MSK1 0x00000080U
5792 #define RTC_ALRMBR_ST 0x00000070U
5793 #define RTC_ALRMBR_ST_0 0x00000010U
5794 #define RTC_ALRMBR_ST_1 0x00000020U
5795 #define RTC_ALRMBR_ST_2 0x00000040U
5796 #define RTC_ALRMBR_SU 0x0000000FU
5797 #define RTC_ALRMBR_SU_0 0x00000001U
5798 #define RTC_ALRMBR_SU_1 0x00000002U
5799 #define RTC_ALRMBR_SU_2 0x00000004U
5800 #define RTC_ALRMBR_SU_3 0x00000008U
5801 
5802 /******************** Bits definition for RTC_WPR register ******************/
5803 #define RTC_WPR_KEY 0x000000FFU
5804 
5805 /******************** Bits definition for RTC_SSR register ******************/
5806 #define RTC_SSR_SS 0x0000FFFFU
5807 
5808 /******************** Bits definition for RTC_SHIFTR register ***************/
5809 #define RTC_SHIFTR_SUBFS 0x00007FFFU
5810 #define RTC_SHIFTR_ADD1S 0x80000000U
5811 
5812 /******************** Bits definition for RTC_TSTR register *****************/
5813 #define RTC_TSTR_PM 0x00400000U
5814 #define RTC_TSTR_HT 0x00300000U
5815 #define RTC_TSTR_HT_0 0x00100000U
5816 #define RTC_TSTR_HT_1 0x00200000U
5817 #define RTC_TSTR_HU 0x000F0000U
5818 #define RTC_TSTR_HU_0 0x00010000U
5819 #define RTC_TSTR_HU_1 0x00020000U
5820 #define RTC_TSTR_HU_2 0x00040000U
5821 #define RTC_TSTR_HU_3 0x00080000U
5822 #define RTC_TSTR_MNT 0x00007000U
5823 #define RTC_TSTR_MNT_0 0x00001000U
5824 #define RTC_TSTR_MNT_1 0x00002000U
5825 #define RTC_TSTR_MNT_2 0x00004000U
5826 #define RTC_TSTR_MNU 0x00000F00U
5827 #define RTC_TSTR_MNU_0 0x00000100U
5828 #define RTC_TSTR_MNU_1 0x00000200U
5829 #define RTC_TSTR_MNU_2 0x00000400U
5830 #define RTC_TSTR_MNU_3 0x00000800U
5831 #define RTC_TSTR_ST 0x00000070U
5832 #define RTC_TSTR_ST_0 0x00000010U
5833 #define RTC_TSTR_ST_1 0x00000020U
5834 #define RTC_TSTR_ST_2 0x00000040U
5835 #define RTC_TSTR_SU 0x0000000FU
5836 #define RTC_TSTR_SU_0 0x00000001U
5837 #define RTC_TSTR_SU_1 0x00000002U
5838 #define RTC_TSTR_SU_2 0x00000004U
5839 #define RTC_TSTR_SU_3 0x00000008U
5840 
5841 /******************** Bits definition for RTC_TSDR register *****************/
5842 #define RTC_TSDR_WDU 0x0000E000U
5843 #define RTC_TSDR_WDU_0 0x00002000U
5844 #define RTC_TSDR_WDU_1 0x00004000U
5845 #define RTC_TSDR_WDU_2 0x00008000U
5846 #define RTC_TSDR_MT 0x00001000U
5847 #define RTC_TSDR_MU 0x00000F00U
5848 #define RTC_TSDR_MU_0 0x00000100U
5849 #define RTC_TSDR_MU_1 0x00000200U
5850 #define RTC_TSDR_MU_2 0x00000400U
5851 #define RTC_TSDR_MU_3 0x00000800U
5852 #define RTC_TSDR_DT 0x00000030U
5853 #define RTC_TSDR_DT_0 0x00000010U
5854 #define RTC_TSDR_DT_1 0x00000020U
5855 #define RTC_TSDR_DU 0x0000000FU
5856 #define RTC_TSDR_DU_0 0x00000001U
5857 #define RTC_TSDR_DU_1 0x00000002U
5858 #define RTC_TSDR_DU_2 0x00000004U
5859 #define RTC_TSDR_DU_3 0x00000008U
5860 
5861 /******************** Bits definition for RTC_TSSSR register ****************/
5862 #define RTC_TSSSR_SS 0x0000FFFFU
5863 
5864 /******************** Bits definition for RTC_CAL register *****************/
5865 #define RTC_CALR_CALP 0x00008000U
5866 #define RTC_CALR_CALW8 0x00004000U
5867 #define RTC_CALR_CALW16 0x00002000U
5868 #define RTC_CALR_CALM 0x000001FFU
5869 #define RTC_CALR_CALM_0 0x00000001U
5870 #define RTC_CALR_CALM_1 0x00000002U
5871 #define RTC_CALR_CALM_2 0x00000004U
5872 #define RTC_CALR_CALM_3 0x00000008U
5873 #define RTC_CALR_CALM_4 0x00000010U
5874 #define RTC_CALR_CALM_5 0x00000020U
5875 #define RTC_CALR_CALM_6 0x00000040U
5876 #define RTC_CALR_CALM_7 0x00000080U
5877 #define RTC_CALR_CALM_8 0x00000100U
5878 
5879 /******************** Bits definition for RTC_TAFCR register ****************/
5880 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
5881 #define RTC_TAFCR_TSINSEL 0x00020000U
5882 #define RTC_TAFCR_TAMPINSEL 0x00010000U
5883 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
5884 #define RTC_TAFCR_TAMPPRCH 0x00006000U
5885 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
5886 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
5887 #define RTC_TAFCR_TAMPFLT 0x00001800U
5888 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
5889 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
5890 #define RTC_TAFCR_TAMPFREQ 0x00000700U
5891 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
5892 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
5893 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
5894 #define RTC_TAFCR_TAMPTS 0x00000080U
5895 #define RTC_TAFCR_TAMP2TRG 0x00000010U
5896 #define RTC_TAFCR_TAMP2E 0x00000008U
5897 #define RTC_TAFCR_TAMPIE 0x00000004U
5898 #define RTC_TAFCR_TAMP1TRG 0x00000002U
5899 #define RTC_TAFCR_TAMP1E 0x00000001U
5900 
5901 /******************** Bits definition for RTC_ALRMASSR register *************/
5902 #define RTC_ALRMASSR_MASKSS 0x0F000000U
5903 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
5904 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
5905 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
5906 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
5907 #define RTC_ALRMASSR_SS 0x00007FFFU
5908 
5909 /******************** Bits definition for RTC_ALRMBSSR register *************/
5910 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
5911 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
5912 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
5913 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
5914 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
5915 #define RTC_ALRMBSSR_SS 0x00007FFFU
5916 
5917 /******************** Bits definition for RTC_BKP0R register ****************/
5918 #define RTC_BKP0R 0xFFFFFFFFU
5919 
5920 /******************** Bits definition for RTC_BKP1R register ****************/
5921 #define RTC_BKP1R 0xFFFFFFFFU
5922 
5923 /******************** Bits definition for RTC_BKP2R register ****************/
5924 #define RTC_BKP2R 0xFFFFFFFFU
5925 
5926 /******************** Bits definition for RTC_BKP3R register ****************/
5927 #define RTC_BKP3R 0xFFFFFFFFU
5928 
5929 /******************** Bits definition for RTC_BKP4R register ****************/
5930 #define RTC_BKP4R 0xFFFFFFFFU
5931 
5932 /******************** Bits definition for RTC_BKP5R register ****************/
5933 #define RTC_BKP5R 0xFFFFFFFFU
5934 
5935 /******************** Bits definition for RTC_BKP6R register ****************/
5936 #define RTC_BKP6R 0xFFFFFFFFU
5937 
5938 /******************** Bits definition for RTC_BKP7R register ****************/
5939 #define RTC_BKP7R 0xFFFFFFFFU
5940 
5941 /******************** Bits definition for RTC_BKP8R register ****************/
5942 #define RTC_BKP8R 0xFFFFFFFFU
5943 
5944 /******************** Bits definition for RTC_BKP9R register ****************/
5945 #define RTC_BKP9R 0xFFFFFFFFU
5946 
5947 /******************** Bits definition for RTC_BKP10R register ***************/
5948 #define RTC_BKP10R 0xFFFFFFFFU
5949 
5950 /******************** Bits definition for RTC_BKP11R register ***************/
5951 #define RTC_BKP11R 0xFFFFFFFFU
5952 
5953 /******************** Bits definition for RTC_BKP12R register ***************/
5954 #define RTC_BKP12R 0xFFFFFFFFU
5955 
5956 /******************** Bits definition for RTC_BKP13R register ***************/
5957 #define RTC_BKP13R 0xFFFFFFFFU
5958 
5959 /******************** Bits definition for RTC_BKP14R register ***************/
5960 #define RTC_BKP14R 0xFFFFFFFFU
5961 
5962 /******************** Bits definition for RTC_BKP15R register ***************/
5963 #define RTC_BKP15R 0xFFFFFFFFU
5964 
5965 /******************** Bits definition for RTC_BKP16R register ***************/
5966 #define RTC_BKP16R 0xFFFFFFFFU
5967 
5968 /******************** Bits definition for RTC_BKP17R register ***************/
5969 #define RTC_BKP17R 0xFFFFFFFFU
5970 
5971 /******************** Bits definition for RTC_BKP18R register ***************/
5972 #define RTC_BKP18R 0xFFFFFFFFU
5973 
5974 /******************** Bits definition for RTC_BKP19R register ***************/
5975 #define RTC_BKP19R 0xFFFFFFFFU
5976 
5977 /******************************************************************************/
5978 /* */
5979 /* Serial Audio Interface */
5980 /* */
5981 /******************************************************************************/
5982 /******************** Bit definition for SAI_GCR register *******************/
5983 #define SAI_GCR_SYNCIN 0x00000003U
5984 #define SAI_GCR_SYNCIN_0 0x00000001U
5985 #define SAI_GCR_SYNCIN_1 0x00000002U
5987 #define SAI_GCR_SYNCOUT 0x00000030U
5988 #define SAI_GCR_SYNCOUT_0 0x00000010U
5989 #define SAI_GCR_SYNCOUT_1 0x00000020U
5991 /******************* Bit definition for SAI_xCR1 register *******************/
5992 #define SAI_xCR1_MODE 0x00000003U
5993 #define SAI_xCR1_MODE_0 0x00000001U
5994 #define SAI_xCR1_MODE_1 0x00000002U
5996 #define SAI_xCR1_PRTCFG 0x0000000CU
5997 #define SAI_xCR1_PRTCFG_0 0x00000004U
5998 #define SAI_xCR1_PRTCFG_1 0x00000008U
6000 #define SAI_xCR1_DS 0x000000E0U
6001 #define SAI_xCR1_DS_0 0x00000020U
6002 #define SAI_xCR1_DS_1 0x00000040U
6003 #define SAI_xCR1_DS_2 0x00000080U
6005 #define SAI_xCR1_LSBFIRST 0x00000100U
6006 #define SAI_xCR1_CKSTR 0x00000200U
6008 #define SAI_xCR1_SYNCEN 0x00000C00U
6009 #define SAI_xCR1_SYNCEN_0 0x00000400U
6010 #define SAI_xCR1_SYNCEN_1 0x00000800U
6012 #define SAI_xCR1_MONO 0x00001000U
6013 #define SAI_xCR1_OUTDRIV 0x00002000U
6014 #define SAI_xCR1_SAIEN 0x00010000U
6015 #define SAI_xCR1_DMAEN 0x00020000U
6016 #define SAI_xCR1_NODIV 0x00080000U
6018 #define SAI_xCR1_MCKDIV 0x00F00000U
6019 #define SAI_xCR1_MCKDIV_0 0x00100000U
6020 #define SAI_xCR1_MCKDIV_1 0x00200000U
6021 #define SAI_xCR1_MCKDIV_2 0x00400000U
6022 #define SAI_xCR1_MCKDIV_3 0x00800000U
6024 /******************* Bit definition for SAI_xCR2 register *******************/
6025 #define SAI_xCR2_FTH 0x00000007U
6026 #define SAI_xCR2_FTH_0 0x00000001U
6027 #define SAI_xCR2_FTH_1 0x00000002U
6028 #define SAI_xCR2_FTH_2 0x00000004U
6030 #define SAI_xCR2_FFLUSH 0x00000008U
6031 #define SAI_xCR2_TRIS 0x00000010U
6032 #define SAI_xCR2_MUTE 0x00000020U
6033 #define SAI_xCR2_MUTEVAL 0x00000040U
6035 #define SAI_xCR2_MUTECNT 0x00001F80U
6036 #define SAI_xCR2_MUTECNT_0 0x00000080U
6037 #define SAI_xCR2_MUTECNT_1 0x00000100U
6038 #define SAI_xCR2_MUTECNT_2 0x00000200U
6039 #define SAI_xCR2_MUTECNT_3 0x00000400U
6040 #define SAI_xCR2_MUTECNT_4 0x00000800U
6041 #define SAI_xCR2_MUTECNT_5 0x00001000U
6043 #define SAI_xCR2_CPL 0x00002000U
6045 #define SAI_xCR2_COMP 0x0000C000U
6046 #define SAI_xCR2_COMP_0 0x00004000U
6047 #define SAI_xCR2_COMP_1 0x00008000U
6049 /****************** Bit definition for SAI_xFRCR register *******************/
6050 #define SAI_xFRCR_FRL 0x000000FFU
6051 #define SAI_xFRCR_FRL_0 0x00000001U
6052 #define SAI_xFRCR_FRL_1 0x00000002U
6053 #define SAI_xFRCR_FRL_2 0x00000004U
6054 #define SAI_xFRCR_FRL_3 0x00000008U
6055 #define SAI_xFRCR_FRL_4 0x00000010U
6056 #define SAI_xFRCR_FRL_5 0x00000020U
6057 #define SAI_xFRCR_FRL_6 0x00000040U
6058 #define SAI_xFRCR_FRL_7 0x00000080U
6060 #define SAI_xFRCR_FSALL 0x00007F00U
6061 #define SAI_xFRCR_FSALL_0 0x00000100U
6062 #define SAI_xFRCR_FSALL_1 0x00000200U
6063 #define SAI_xFRCR_FSALL_2 0x00000400U
6064 #define SAI_xFRCR_FSALL_3 0x00000800U
6065 #define SAI_xFRCR_FSALL_4 0x00001000U
6066 #define SAI_xFRCR_FSALL_5 0x00002000U
6067 #define SAI_xFRCR_FSALL_6 0x00004000U
6069 #define SAI_xFRCR_FSDEF 0x00010000U
6070 #define SAI_xFRCR_FSPOL 0x00020000U
6071 #define SAI_xFRCR_FSOFF 0x00040000U
6072 /* Legacy defines */
6073 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
6074 
6075 /****************** Bit definition for SAI_xSLOTR register *******************/
6076 #define SAI_xSLOTR_FBOFF 0x0000001FU
6077 #define SAI_xSLOTR_FBOFF_0 0x00000001U
6078 #define SAI_xSLOTR_FBOFF_1 0x00000002U
6079 #define SAI_xSLOTR_FBOFF_2 0x00000004U
6080 #define SAI_xSLOTR_FBOFF_3 0x00000008U
6081 #define SAI_xSLOTR_FBOFF_4 0x00000010U
6083 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
6084 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
6085 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
6087 #define SAI_xSLOTR_NBSLOT 0x00000F00U
6088 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
6089 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
6090 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
6091 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
6093 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
6095 /******************* Bit definition for SAI_xIMR register *******************/
6096 #define SAI_xIMR_OVRUDRIE 0x00000001U
6097 #define SAI_xIMR_MUTEDETIE 0x00000002U
6098 #define SAI_xIMR_WCKCFGIE 0x00000004U
6099 #define SAI_xIMR_FREQIE 0x00000008U
6100 #define SAI_xIMR_CNRDYIE 0x00000010U
6101 #define SAI_xIMR_AFSDETIE 0x00000020U
6102 #define SAI_xIMR_LFSDETIE 0x00000040U
6104 /******************** Bit definition for SAI_xSR register *******************/
6105 #define SAI_xSR_OVRUDR 0x00000001U
6106 #define SAI_xSR_MUTEDET 0x00000002U
6107 #define SAI_xSR_WCKCFG 0x00000004U
6108 #define SAI_xSR_FREQ 0x00000008U
6109 #define SAI_xSR_CNRDY 0x00000010U
6110 #define SAI_xSR_AFSDET 0x00000020U
6111 #define SAI_xSR_LFSDET 0x00000040U
6113 #define SAI_xSR_FLVL 0x00070000U
6114 #define SAI_xSR_FLVL_0 0x00010000U
6115 #define SAI_xSR_FLVL_1 0x00020000U
6116 #define SAI_xSR_FLVL_2 0x00040000U
6118 /****************** Bit definition for SAI_xCLRFR register ******************/
6119 #define SAI_xCLRFR_COVRUDR 0x00000001U
6120 #define SAI_xCLRFR_CMUTEDET 0x00000002U
6121 #define SAI_xCLRFR_CWCKCFG 0x00000004U
6122 #define SAI_xCLRFR_CFREQ 0x00000008U
6123 #define SAI_xCLRFR_CCNRDY 0x00000010U
6124 #define SAI_xCLRFR_CAFSDET 0x00000020U
6125 #define SAI_xCLRFR_CLFSDET 0x00000040U
6127 /****************** Bit definition for SAI_xDR register ******************/
6128 #define SAI_xDR_DATA 0xFFFFFFFFU
6129 
6130 /******************************************************************************/
6131 /* */
6132 /* SPDIF-RX Interface */
6133 /* */
6134 /******************************************************************************/
6135 /******************** Bit definition for SPDIFRX_CR register *******************/
6136 #define SPDIFRX_CR_SPDIFEN 0x00000003U
6137 #define SPDIFRX_CR_RXDMAEN 0x00000004U
6138 #define SPDIFRX_CR_RXSTEO 0x00000008U
6139 #define SPDIFRX_CR_DRFMT 0x00000030U
6140 #define SPDIFRX_CR_PMSK 0x00000040U
6141 #define SPDIFRX_CR_VMSK 0x00000080U
6142 #define SPDIFRX_CR_CUMSK 0x00000100U
6143 #define SPDIFRX_CR_PTMSK 0x00000200U
6144 #define SPDIFRX_CR_CBDMAEN 0x00000400U
6145 #define SPDIFRX_CR_CHSEL 0x00000800U
6146 #define SPDIFRX_CR_NBTR 0x00003000U
6147 #define SPDIFRX_CR_WFA 0x00004000U
6148 #define SPDIFRX_CR_INSEL 0x00070000U
6150 /******************* Bit definition for SPDIFRX_IMR register *******************/
6151 #define SPDIFRX_IMR_RXNEIE 0x00000001U
6152 #define SPDIFRX_IMR_CSRNEIE 0x00000002U
6153 #define SPDIFRX_IMR_PERRIE 0x00000004U
6154 #define SPDIFRX_IMR_OVRIE 0x00000008U
6155 #define SPDIFRX_IMR_SBLKIE 0x00000010U
6156 #define SPDIFRX_IMR_SYNCDIE 0x00000020U
6157 #define SPDIFRX_IMR_IFEIE 0x00000040U
6159 /******************* Bit definition for SPDIFRX_SR register *******************/
6160 #define SPDIFRX_SR_RXNE 0x00000001U
6161 #define SPDIFRX_SR_CSRNE 0x00000002U
6162 #define SPDIFRX_SR_PERR 0x00000004U
6163 #define SPDIFRX_SR_OVR 0x00000008U
6164 #define SPDIFRX_SR_SBD 0x00000010U
6165 #define SPDIFRX_SR_SYNCD 0x00000020U
6166 #define SPDIFRX_SR_FERR 0x00000040U
6167 #define SPDIFRX_SR_SERR 0x00000080U
6168 #define SPDIFRX_SR_TERR 0x00000100U
6169 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U
6171 /******************* Bit definition for SPDIFRX_IFCR register *******************/
6172 #define SPDIFRX_IFCR_PERRCF 0x00000004U
6173 #define SPDIFRX_IFCR_OVRCF 0x00000008U
6174 #define SPDIFRX_IFCR_SBDCF 0x00000010U
6175 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U
6177 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
6178 #define SPDIFRX_DR0_DR 0x00FFFFFFU
6179 #define SPDIFRX_DR0_PE 0x01000000U
6180 #define SPDIFRX_DR0_V 0x02000000U
6181 #define SPDIFRX_DR0_U 0x04000000U
6182 #define SPDIFRX_DR0_C 0x08000000U
6183 #define SPDIFRX_DR0_PT 0x30000000U
6185 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
6186 #define SPDIFRX_DR1_DR 0xFFFFFF00U
6187 #define SPDIFRX_DR1_PT 0x00000030U
6188 #define SPDIFRX_DR1_C 0x00000008U
6189 #define SPDIFRX_DR1_U 0x00000004U
6190 #define SPDIFRX_DR1_V 0x00000002U
6191 #define SPDIFRX_DR1_PE 0x00000001U
6193 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
6194 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U
6195 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU
6197 /******************* Bit definition for SPDIFRX_CSR register *******************/
6198 #define SPDIFRX_CSR_USR 0x0000FFFFU
6199 #define SPDIFRX_CSR_CS 0x00FF0000U
6200 #define SPDIFRX_CSR_SOB 0x01000000U
6202 /******************* Bit definition for SPDIFRX_DIR register *******************/
6203 #define SPDIFRX_DIR_THI 0x000013FFU
6204 #define SPDIFRX_DIR_TLO 0x1FFF0000U
6207 /******************************************************************************/
6208 /* */
6209 /* SD host Interface */
6210 /* */
6211 /******************************************************************************/
6212 /****************** Bit definition for SDIO_POWER register ******************/
6213 #define SDIO_POWER_PWRCTRL 0x03U
6214 #define SDIO_POWER_PWRCTRL_0 0x01U
6215 #define SDIO_POWER_PWRCTRL_1 0x02U
6217 /****************** Bit definition for SDIO_CLKCR register ******************/
6218 #define SDIO_CLKCR_CLKDIV 0x00FFU
6219 #define SDIO_CLKCR_CLKEN 0x0100U
6220 #define SDIO_CLKCR_PWRSAV 0x0200U
6221 #define SDIO_CLKCR_BYPASS 0x0400U
6223 #define SDIO_CLKCR_WIDBUS 0x1800U
6224 #define SDIO_CLKCR_WIDBUS_0 0x0800U
6225 #define SDIO_CLKCR_WIDBUS_1 0x1000U
6227 #define SDIO_CLKCR_NEGEDGE 0x2000U
6228 #define SDIO_CLKCR_HWFC_EN 0x4000U
6230 /******************* Bit definition for SDIO_ARG register *******************/
6231 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
6233 /******************* Bit definition for SDIO_CMD register *******************/
6234 #define SDIO_CMD_CMDINDEX 0x003FU
6236 #define SDIO_CMD_WAITRESP 0x00C0U
6237 #define SDIO_CMD_WAITRESP_0 0x0040U
6238 #define SDIO_CMD_WAITRESP_1 0x0080U
6240 #define SDIO_CMD_WAITINT 0x0100U
6241 #define SDIO_CMD_WAITPEND 0x0200U
6242 #define SDIO_CMD_CPSMEN 0x0400U
6243 #define SDIO_CMD_SDIOSUSPEND 0x0800U
6245 /***************** Bit definition for SDIO_RESPCMD register *****************/
6246 #define SDIO_RESPCMD_RESPCMD 0x3FU
6248 /****************** Bit definition for SDIO_RESP0 register ******************/
6249 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
6251 /****************** Bit definition for SDIO_RESP1 register ******************/
6252 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
6254 /****************** Bit definition for SDIO_RESP2 register ******************/
6255 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
6257 /****************** Bit definition for SDIO_RESP3 register ******************/
6258 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
6260 /****************** Bit definition for SDIO_RESP4 register ******************/
6261 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
6263 /****************** Bit definition for SDIO_DTIMER register *****************/
6264 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
6266 /****************** Bit definition for SDIO_DLEN register *******************/
6267 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
6269 /****************** Bit definition for SDIO_DCTRL register ******************/
6270 #define SDIO_DCTRL_DTEN 0x0001U
6271 #define SDIO_DCTRL_DTDIR 0x0002U
6272 #define SDIO_DCTRL_DTMODE 0x0004U
6273 #define SDIO_DCTRL_DMAEN 0x0008U
6275 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
6276 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
6277 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
6278 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
6279 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
6281 #define SDIO_DCTRL_RWSTART 0x0100U
6282 #define SDIO_DCTRL_RWSTOP 0x0200U
6283 #define SDIO_DCTRL_RWMOD 0x0400U
6284 #define SDIO_DCTRL_SDIOEN 0x0800U
6286 /****************** Bit definition for SDIO_DCOUNT register *****************/
6287 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
6289 /****************** Bit definition for SDIO_STA register ********************/
6290 #define SDIO_STA_CCRCFAIL 0x00000001U
6291 #define SDIO_STA_DCRCFAIL 0x00000002U
6292 #define SDIO_STA_CTIMEOUT 0x00000004U
6293 #define SDIO_STA_DTIMEOUT 0x00000008U
6294 #define SDIO_STA_TXUNDERR 0x00000010U
6295 #define SDIO_STA_RXOVERR 0x00000020U
6296 #define SDIO_STA_CMDREND 0x00000040U
6297 #define SDIO_STA_CMDSENT 0x00000080U
6298 #define SDIO_STA_DATAEND 0x00000100U
6299 #define SDIO_STA_DBCKEND 0x00000400U
6300 #define SDIO_STA_CMDACT 0x00000800U
6301 #define SDIO_STA_TXACT 0x00001000U
6302 #define SDIO_STA_RXACT 0x00002000U
6303 #define SDIO_STA_TXFIFOHE 0x00004000U
6304 #define SDIO_STA_RXFIFOHF 0x00008000U
6305 #define SDIO_STA_TXFIFOF 0x00010000U
6306 #define SDIO_STA_RXFIFOF 0x00020000U
6307 #define SDIO_STA_TXFIFOE 0x00040000U
6308 #define SDIO_STA_RXFIFOE 0x00080000U
6309 #define SDIO_STA_TXDAVL 0x00100000U
6310 #define SDIO_STA_RXDAVL 0x00200000U
6311 #define SDIO_STA_SDIOIT 0x00400000U
6313 /******************* Bit definition for SDIO_ICR register *******************/
6314 #define SDIO_ICR_CCRCFAILC 0x00000001U
6315 #define SDIO_ICR_DCRCFAILC 0x00000002U
6316 #define SDIO_ICR_CTIMEOUTC 0x00000004U
6317 #define SDIO_ICR_DTIMEOUTC 0x00000008U
6318 #define SDIO_ICR_TXUNDERRC 0x00000010U
6319 #define SDIO_ICR_RXOVERRC 0x00000020U
6320 #define SDIO_ICR_CMDRENDC 0x00000040U
6321 #define SDIO_ICR_CMDSENTC 0x00000080U
6322 #define SDIO_ICR_DATAENDC 0x00000100U
6323 #define SDIO_ICR_DBCKENDC 0x00000400U
6324 #define SDIO_ICR_SDIOITC 0x00400000U
6326 /****************** Bit definition for SDIO_MASK register *******************/
6327 #define SDIO_MASK_CCRCFAILIE 0x00000001U
6328 #define SDIO_MASK_DCRCFAILIE 0x00000002U
6329 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
6330 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
6331 #define SDIO_MASK_TXUNDERRIE 0x00000010U
6332 #define SDIO_MASK_RXOVERRIE 0x00000020U
6333 #define SDIO_MASK_CMDRENDIE 0x00000040U
6334 #define SDIO_MASK_CMDSENTIE 0x00000080U
6335 #define SDIO_MASK_DATAENDIE 0x00000100U
6336 #define SDIO_MASK_DBCKENDIE 0x00000400U
6337 #define SDIO_MASK_CMDACTIE 0x00000800U
6338 #define SDIO_MASK_TXACTIE 0x00001000U
6339 #define SDIO_MASK_RXACTIE 0x00002000U
6340 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
6341 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
6342 #define SDIO_MASK_TXFIFOFIE 0x00010000U
6343 #define SDIO_MASK_RXFIFOFIE 0x00020000U
6344 #define SDIO_MASK_TXFIFOEIE 0x00040000U
6345 #define SDIO_MASK_RXFIFOEIE 0x00080000U
6346 #define SDIO_MASK_TXDAVLIE 0x00100000U
6347 #define SDIO_MASK_RXDAVLIE 0x00200000U
6348 #define SDIO_MASK_SDIOITIE 0x00400000U
6350 /***************** Bit definition for SDIO_FIFOCNT register *****************/
6351 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
6353 /****************** Bit definition for SDIO_FIFO register *******************/
6354 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
6356 /******************************************************************************/
6357 /* */
6358 /* Serial Peripheral Interface */
6359 /* */
6360 /******************************************************************************/
6361 /******************* Bit definition for SPI_CR1 register ********************/
6362 #define SPI_CR1_CPHA 0x00000001U
6363 #define SPI_CR1_CPOL 0x00000002U
6364 #define SPI_CR1_MSTR 0x00000004U
6366 #define SPI_CR1_BR 0x00000038U
6367 #define SPI_CR1_BR_0 0x00000008U
6368 #define SPI_CR1_BR_1 0x00000010U
6369 #define SPI_CR1_BR_2 0x00000020U
6371 #define SPI_CR1_SPE 0x00000040U
6372 #define SPI_CR1_LSBFIRST 0x00000080U
6373 #define SPI_CR1_SSI 0x00000100U
6374 #define SPI_CR1_SSM 0x00000200U
6375 #define SPI_CR1_RXONLY 0x00000400U
6376 #define SPI_CR1_DFF 0x00000800U
6377 #define SPI_CR1_CRCNEXT 0x00001000U
6378 #define SPI_CR1_CRCEN 0x00002000U
6379 #define SPI_CR1_BIDIOE 0x00004000U
6380 #define SPI_CR1_BIDIMODE 0x00008000U
6382 /******************* Bit definition for SPI_CR2 register ********************/
6383 #define SPI_CR2_RXDMAEN 0x00000001U
6384 #define SPI_CR2_TXDMAEN 0x00000002U
6385 #define SPI_CR2_SSOE 0x00000004U
6386 #define SPI_CR2_FRF 0x00000010U
6387 #define SPI_CR2_ERRIE 0x00000020U
6388 #define SPI_CR2_RXNEIE 0x00000040U
6389 #define SPI_CR2_TXEIE 0x00000080U
6391 /******************** Bit definition for SPI_SR register ********************/
6392 #define SPI_SR_RXNE 0x00000001U
6393 #define SPI_SR_TXE 0x00000002U
6394 #define SPI_SR_CHSIDE 0x00000004U
6395 #define SPI_SR_UDR 0x00000008U
6396 #define SPI_SR_CRCERR 0x00000010U
6397 #define SPI_SR_MODF 0x00000020U
6398 #define SPI_SR_OVR 0x00000040U
6399 #define SPI_SR_BSY 0x00000080U
6400 #define SPI_SR_FRE 0x00000100U
6402 /******************** Bit definition for SPI_DR register ********************/
6403 #define SPI_DR_DR 0x0000FFFFU
6405 /******************* Bit definition for SPI_CRCPR register ******************/
6406 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
6408 /****************** Bit definition for SPI_RXCRCR register ******************/
6409 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
6411 /****************** Bit definition for SPI_TXCRCR register ******************/
6412 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
6414 /****************** Bit definition for SPI_I2SCFGR register *****************/
6415 #define SPI_I2SCFGR_CHLEN 0x00000001U
6417 #define SPI_I2SCFGR_DATLEN 0x00000006U
6418 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
6419 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
6421 #define SPI_I2SCFGR_CKPOL 0x00000008U
6423 #define SPI_I2SCFGR_I2SSTD 0x00000030U
6424 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
6425 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
6427 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
6429 #define SPI_I2SCFGR_I2SCFG 0x00000300U
6430 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
6431 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
6433 #define SPI_I2SCFGR_I2SE 0x00000400U
6434 #define SPI_I2SCFGR_I2SMOD 0x00000800U
6435 #define SPI_I2SCFGR_ASTRTEN 0x00001000U
6437 /****************** Bit definition for SPI_I2SPR register *******************/
6438 #define SPI_I2SPR_I2SDIV 0x000000FFU
6439 #define SPI_I2SPR_ODD 0x00000100U
6440 #define SPI_I2SPR_MCKOE 0x00000200U
6442 /******************************************************************************/
6443 /* */
6444 /* SYSCFG */
6445 /* */
6446 /******************************************************************************/
6447 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
6448 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
6449 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
6450 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
6451 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
6452 
6453 #define SYSCFG_MEMRMP_UFB_MODE 0x00000100U
6454 #define SYSCFG_SWP_FMC 0x00000C00U
6456 /****************** Bit definition for SYSCFG_PMC register ******************/
6457 #define SYSCFG_PMC_ADCxDC2 0x00070000U
6458 #define SYSCFG_PMC_ADC1DC2 0x00010000U
6459 #define SYSCFG_PMC_ADC2DC2 0x00020000U
6460 #define SYSCFG_PMC_ADC3DC2 0x00040000U
6462 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6463 #define SYSCFG_EXTICR1_EXTI0 0x000FU
6464 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
6465 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
6466 #define SYSCFG_EXTICR1_EXTI3 0xF000U
6470 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
6471 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
6472 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
6473 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
6474 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
6475 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
6476 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
6477 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
6478 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
6479 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
6480 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
6485 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
6486 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
6487 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
6488 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
6489 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
6490 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
6491 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
6492 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
6493 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
6494 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
6495 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
6501 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
6502 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
6503 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
6504 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
6505 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
6506 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
6507 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
6508 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
6509 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
6510 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
6511 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
6517 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
6518 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
6519 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
6520 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
6521 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
6522 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
6523 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
6524 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
6525 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
6526 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
6527 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
6530 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6531 #define SYSCFG_EXTICR2_EXTI4 0x000FU
6532 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
6533 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
6534 #define SYSCFG_EXTICR2_EXTI7 0xF000U
6538 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
6539 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
6540 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
6541 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
6542 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
6543 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
6544 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
6545 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
6546 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
6547 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
6548 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
6553 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
6554 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
6555 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
6556 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
6557 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
6558 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
6559 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
6560 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
6561 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
6562 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
6563 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
6568 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
6569 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
6570 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
6571 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
6572 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
6573 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
6574 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
6575 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
6576 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
6577 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
6578 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
6584 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
6585 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
6586 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
6587 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
6588 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
6589 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
6590 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
6591 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
6592 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
6593 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
6594 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
6596 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6597 #define SYSCFG_EXTICR3_EXTI8 0x000FU
6598 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
6599 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
6600 #define SYSCFG_EXTICR3_EXTI11 0xF000U
6605 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
6606 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
6607 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
6608 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
6609 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
6610 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
6611 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
6612 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
6613 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
6614 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
6619 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
6620 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
6621 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
6622 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
6623 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
6624 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
6625 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
6626 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
6627 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
6628 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
6634 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
6635 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
6636 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
6637 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
6638 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
6639 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
6640 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
6641 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
6642 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
6643 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
6649 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
6650 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
6651 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
6652 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
6653 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
6654 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
6655 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
6656 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
6657 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
6658 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
6661 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6662 #define SYSCFG_EXTICR4_EXTI12 0x000FU
6663 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
6664 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
6665 #define SYSCFG_EXTICR4_EXTI15 0xF000U
6669 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
6670 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
6671 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
6672 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
6673 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
6674 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
6675 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
6676 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
6677 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
6678 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
6684 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
6685 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
6686 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
6687 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
6688 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
6689 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
6690 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
6691 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
6692 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
6693 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
6699 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
6700 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
6701 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
6702 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
6703 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
6704 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
6705 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
6706 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
6707 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
6708 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
6714 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
6715 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
6716 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
6717 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
6718 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
6719 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
6720 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
6721 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
6722 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
6723 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
6725 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6726 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
6727 #define SYSCFG_CMPCR_READY 0x00000100U
6729 /****************** Bit definition for SYSCFG_CFGR register ****************/
6730 #define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U
6731 #define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U
6733 /******************************************************************************/
6734 /* */
6735 /* TIM */
6736 /* */
6737 /******************************************************************************/
6738 /******************* Bit definition for TIM_CR1 register ********************/
6739 #define TIM_CR1_CEN 0x0001U
6740 #define TIM_CR1_UDIS 0x0002U
6741 #define TIM_CR1_URS 0x0004U
6742 #define TIM_CR1_OPM 0x0008U
6743 #define TIM_CR1_DIR 0x0010U
6745 #define TIM_CR1_CMS 0x0060U
6746 #define TIM_CR1_CMS_0 0x0020U
6747 #define TIM_CR1_CMS_1 0x0040U
6749 #define TIM_CR1_ARPE 0x0080U
6751 #define TIM_CR1_CKD 0x0300U
6752 #define TIM_CR1_CKD_0 0x0100U
6753 #define TIM_CR1_CKD_1 0x0200U
6755 /******************* Bit definition for TIM_CR2 register ********************/
6756 #define TIM_CR2_CCPC 0x0001U
6757 #define TIM_CR2_CCUS 0x0004U
6758 #define TIM_CR2_CCDS 0x0008U
6760 #define TIM_CR2_MMS 0x0070U
6761 #define TIM_CR2_MMS_0 0x0010U
6762 #define TIM_CR2_MMS_1 0x0020U
6763 #define TIM_CR2_MMS_2 0x0040U
6765 #define TIM_CR2_TI1S 0x0080U
6766 #define TIM_CR2_OIS1 0x0100U
6767 #define TIM_CR2_OIS1N 0x0200U
6768 #define TIM_CR2_OIS2 0x0400U
6769 #define TIM_CR2_OIS2N 0x0800U
6770 #define TIM_CR2_OIS3 0x1000U
6771 #define TIM_CR2_OIS3N 0x2000U
6772 #define TIM_CR2_OIS4 0x4000U
6774 /******************* Bit definition for TIM_SMCR register *******************/
6775 #define TIM_SMCR_SMS 0x0007U
6776 #define TIM_SMCR_SMS_0 0x0001U
6777 #define TIM_SMCR_SMS_1 0x0002U
6778 #define TIM_SMCR_SMS_2 0x0004U
6780 #define TIM_SMCR_TS 0x0070U
6781 #define TIM_SMCR_TS_0 0x0010U
6782 #define TIM_SMCR_TS_1 0x0020U
6783 #define TIM_SMCR_TS_2 0x0040U
6785 #define TIM_SMCR_MSM 0x0080U
6787 #define TIM_SMCR_ETF 0x0F00U
6788 #define TIM_SMCR_ETF_0 0x0100U
6789 #define TIM_SMCR_ETF_1 0x0200U
6790 #define TIM_SMCR_ETF_2 0x0400U
6791 #define TIM_SMCR_ETF_3 0x0800U
6793 #define TIM_SMCR_ETPS 0x3000U
6794 #define TIM_SMCR_ETPS_0 0x1000U
6795 #define TIM_SMCR_ETPS_1 0x2000U
6797 #define TIM_SMCR_ECE 0x4000U
6798 #define TIM_SMCR_ETP 0x8000U
6800 /******************* Bit definition for TIM_DIER register *******************/
6801 #define TIM_DIER_UIE 0x0001U
6802 #define TIM_DIER_CC1IE 0x0002U
6803 #define TIM_DIER_CC2IE 0x0004U
6804 #define TIM_DIER_CC3IE 0x0008U
6805 #define TIM_DIER_CC4IE 0x0010U
6806 #define TIM_DIER_COMIE 0x0020U
6807 #define TIM_DIER_TIE 0x0040U
6808 #define TIM_DIER_BIE 0x0080U
6809 #define TIM_DIER_UDE 0x0100U
6810 #define TIM_DIER_CC1DE 0x0200U
6811 #define TIM_DIER_CC2DE 0x0400U
6812 #define TIM_DIER_CC3DE 0x0800U
6813 #define TIM_DIER_CC4DE 0x1000U
6814 #define TIM_DIER_COMDE 0x2000U
6815 #define TIM_DIER_TDE 0x4000U
6817 /******************** Bit definition for TIM_SR register ********************/
6818 #define TIM_SR_UIF 0x0001U
6819 #define TIM_SR_CC1IF 0x0002U
6820 #define TIM_SR_CC2IF 0x0004U
6821 #define TIM_SR_CC3IF 0x0008U
6822 #define TIM_SR_CC4IF 0x0010U
6823 #define TIM_SR_COMIF 0x0020U
6824 #define TIM_SR_TIF 0x0040U
6825 #define TIM_SR_BIF 0x0080U
6826 #define TIM_SR_CC1OF 0x0200U
6827 #define TIM_SR_CC2OF 0x0400U
6828 #define TIM_SR_CC3OF 0x0800U
6829 #define TIM_SR_CC4OF 0x1000U
6831 /******************* Bit definition for TIM_EGR register ********************/
6832 #define TIM_EGR_UG 0x01U
6833 #define TIM_EGR_CC1G 0x02U
6834 #define TIM_EGR_CC2G 0x04U
6835 #define TIM_EGR_CC3G 0x08U
6836 #define TIM_EGR_CC4G 0x10U
6837 #define TIM_EGR_COMG 0x20U
6838 #define TIM_EGR_TG 0x40U
6839 #define TIM_EGR_BG 0x80U
6841 /****************** Bit definition for TIM_CCMR1 register *******************/
6842 #define TIM_CCMR1_CC1S 0x0003U
6843 #define TIM_CCMR1_CC1S_0 0x0001U
6844 #define TIM_CCMR1_CC1S_1 0x0002U
6846 #define TIM_CCMR1_OC1FE 0x0004U
6847 #define TIM_CCMR1_OC1PE 0x0008U
6849 #define TIM_CCMR1_OC1M 0x0070U
6850 #define TIM_CCMR1_OC1M_0 0x0010U
6851 #define TIM_CCMR1_OC1M_1 0x0020U
6852 #define TIM_CCMR1_OC1M_2 0x0040U
6854 #define TIM_CCMR1_OC1CE 0x0080U
6856 #define TIM_CCMR1_CC2S 0x0300U
6857 #define TIM_CCMR1_CC2S_0 0x0100U
6858 #define TIM_CCMR1_CC2S_1 0x0200U
6860 #define TIM_CCMR1_OC2FE 0x0400U
6861 #define TIM_CCMR1_OC2PE 0x0800U
6863 #define TIM_CCMR1_OC2M 0x7000U
6864 #define TIM_CCMR1_OC2M_0 0x1000U
6865 #define TIM_CCMR1_OC2M_1 0x2000U
6866 #define TIM_CCMR1_OC2M_2 0x4000U
6868 #define TIM_CCMR1_OC2CE 0x8000U
6870 /*----------------------------------------------------------------------------*/
6871 
6872 #define TIM_CCMR1_IC1PSC 0x000CU
6873 #define TIM_CCMR1_IC1PSC_0 0x0004U
6874 #define TIM_CCMR1_IC1PSC_1 0x0008U
6876 #define TIM_CCMR1_IC1F 0x00F0U
6877 #define TIM_CCMR1_IC1F_0 0x0010U
6878 #define TIM_CCMR1_IC1F_1 0x0020U
6879 #define TIM_CCMR1_IC1F_2 0x0040U
6880 #define TIM_CCMR1_IC1F_3 0x0080U
6882 #define TIM_CCMR1_IC2PSC 0x0C00U
6883 #define TIM_CCMR1_IC2PSC_0 0x0400U
6884 #define TIM_CCMR1_IC2PSC_1 0x0800U
6886 #define TIM_CCMR1_IC2F 0xF000U
6887 #define TIM_CCMR1_IC2F_0 0x1000U
6888 #define TIM_CCMR1_IC2F_1 0x2000U
6889 #define TIM_CCMR1_IC2F_2 0x4000U
6890 #define TIM_CCMR1_IC2F_3 0x8000U
6892 /****************** Bit definition for TIM_CCMR2 register *******************/
6893 #define TIM_CCMR2_CC3S 0x0003U
6894 #define TIM_CCMR2_CC3S_0 0x0001U
6895 #define TIM_CCMR2_CC3S_1 0x0002U
6897 #define TIM_CCMR2_OC3FE 0x0004U
6898 #define TIM_CCMR2_OC3PE 0x0008U
6900 #define TIM_CCMR2_OC3M 0x0070U
6901 #define TIM_CCMR2_OC3M_0 0x0010U
6902 #define TIM_CCMR2_OC3M_1 0x0020U
6903 #define TIM_CCMR2_OC3M_2 0x0040U
6905 #define TIM_CCMR2_OC3CE 0x0080U
6907 #define TIM_CCMR2_CC4S 0x0300U
6908 #define TIM_CCMR2_CC4S_0 0x0100U
6909 #define TIM_CCMR2_CC4S_1 0x0200U
6911 #define TIM_CCMR2_OC4FE 0x0400U
6912 #define TIM_CCMR2_OC4PE 0x0800U
6914 #define TIM_CCMR2_OC4M 0x7000U
6915 #define TIM_CCMR2_OC4M_0 0x1000U
6916 #define TIM_CCMR2_OC4M_1 0x2000U
6917 #define TIM_CCMR2_OC4M_2 0x4000U
6919 #define TIM_CCMR2_OC4CE 0x8000U
6921 /*----------------------------------------------------------------------------*/
6922 
6923 #define TIM_CCMR2_IC3PSC 0x000CU
6924 #define TIM_CCMR2_IC3PSC_0 0x0004U
6925 #define TIM_CCMR2_IC3PSC_1 0x0008U
6927 #define TIM_CCMR2_IC3F 0x00F0U
6928 #define TIM_CCMR2_IC3F_0 0x0010U
6929 #define TIM_CCMR2_IC3F_1 0x0020U
6930 #define TIM_CCMR2_IC3F_2 0x0040U
6931 #define TIM_CCMR2_IC3F_3 0x0080U
6933 #define TIM_CCMR2_IC4PSC 0x0C00U
6934 #define TIM_CCMR2_IC4PSC_0 0x0400U
6935 #define TIM_CCMR2_IC4PSC_1 0x0800U
6937 #define TIM_CCMR2_IC4F 0xF000U
6938 #define TIM_CCMR2_IC4F_0 0x1000U
6939 #define TIM_CCMR2_IC4F_1 0x2000U
6940 #define TIM_CCMR2_IC4F_2 0x4000U
6941 #define TIM_CCMR2_IC4F_3 0x8000U
6943 /******************* Bit definition for TIM_CCER register *******************/
6944 #define TIM_CCER_CC1E 0x0001U
6945 #define TIM_CCER_CC1P 0x0002U
6946 #define TIM_CCER_CC1NE 0x0004U
6947 #define TIM_CCER_CC1NP 0x0008U
6948 #define TIM_CCER_CC2E 0x0010U
6949 #define TIM_CCER_CC2P 0x0020U
6950 #define TIM_CCER_CC2NE 0x0040U
6951 #define TIM_CCER_CC2NP 0x0080U
6952 #define TIM_CCER_CC3E 0x0100U
6953 #define TIM_CCER_CC3P 0x0200U
6954 #define TIM_CCER_CC3NE 0x0400U
6955 #define TIM_CCER_CC3NP 0x0800U
6956 #define TIM_CCER_CC4E 0x1000U
6957 #define TIM_CCER_CC4P 0x2000U
6958 #define TIM_CCER_CC4NP 0x8000U
6960 /******************* Bit definition for TIM_CNT register ********************/
6961 #define TIM_CNT_CNT 0xFFFFU
6963 /******************* Bit definition for TIM_PSC register ********************/
6964 #define TIM_PSC_PSC 0xFFFFU
6966 /******************* Bit definition for TIM_ARR register ********************/
6967 #define TIM_ARR_ARR 0xFFFFU
6969 /******************* Bit definition for TIM_RCR register ********************/
6970 #define TIM_RCR_REP 0xFFU
6972 /******************* Bit definition for TIM_CCR1 register *******************/
6973 #define TIM_CCR1_CCR1 0xFFFFU
6975 /******************* Bit definition for TIM_CCR2 register *******************/
6976 #define TIM_CCR2_CCR2 0xFFFFU
6978 /******************* Bit definition for TIM_CCR3 register *******************/
6979 #define TIM_CCR3_CCR3 0xFFFFU
6981 /******************* Bit definition for TIM_CCR4 register *******************/
6982 #define TIM_CCR4_CCR4 0xFFFFU
6984 /******************* Bit definition for TIM_BDTR register *******************/
6985 #define TIM_BDTR_DTG 0x00FFU
6986 #define TIM_BDTR_DTG_0 0x0001U
6987 #define TIM_BDTR_DTG_1 0x0002U
6988 #define TIM_BDTR_DTG_2 0x0004U
6989 #define TIM_BDTR_DTG_3 0x0008U
6990 #define TIM_BDTR_DTG_4 0x0010U
6991 #define TIM_BDTR_DTG_5 0x0020U
6992 #define TIM_BDTR_DTG_6 0x0040U
6993 #define TIM_BDTR_DTG_7 0x0080U
6995 #define TIM_BDTR_LOCK 0x0300U
6996 #define TIM_BDTR_LOCK_0 0x0100U
6997 #define TIM_BDTR_LOCK_1 0x0200U
6999 #define TIM_BDTR_OSSI 0x0400U
7000 #define TIM_BDTR_OSSR 0x0800U
7001 #define TIM_BDTR_BKE 0x1000U
7002 #define TIM_BDTR_BKP 0x2000U
7003 #define TIM_BDTR_AOE 0x4000U
7004 #define TIM_BDTR_MOE 0x8000U
7006 /******************* Bit definition for TIM_DCR register ********************/
7007 #define TIM_DCR_DBA 0x001FU
7008 #define TIM_DCR_DBA_0 0x0001U
7009 #define TIM_DCR_DBA_1 0x0002U
7010 #define TIM_DCR_DBA_2 0x0004U
7011 #define TIM_DCR_DBA_3 0x0008U
7012 #define TIM_DCR_DBA_4 0x0010U
7014 #define TIM_DCR_DBL 0x1F00U
7015 #define TIM_DCR_DBL_0 0x0100U
7016 #define TIM_DCR_DBL_1 0x0200U
7017 #define TIM_DCR_DBL_2 0x0400U
7018 #define TIM_DCR_DBL_3 0x0800U
7019 #define TIM_DCR_DBL_4 0x1000U
7021 /******************* Bit definition for TIM_DMAR register *******************/
7022 #define TIM_DMAR_DMAB 0xFFFFU
7024 /******************* Bit definition for TIM_OR register *********************/
7025 #define TIM_OR_TI4_RMP 0x00C0U
7026 #define TIM_OR_TI4_RMP_0 0x0040U
7027 #define TIM_OR_TI4_RMP_1 0x0080U
7028 #define TIM_OR_ITR1_RMP 0x0C00U
7029 #define TIM_OR_ITR1_RMP_0 0x0400U
7030 #define TIM_OR_ITR1_RMP_1 0x0800U
7033 /******************************************************************************/
7034 /* */
7035 /* Universal Synchronous Asynchronous Receiver Transmitter */
7036 /* */
7037 /******************************************************************************/
7038 /******************* Bit definition for USART_SR register *******************/
7039 #define USART_SR_PE 0x0001U
7040 #define USART_SR_FE 0x0002U
7041 #define USART_SR_NE 0x0004U
7042 #define USART_SR_ORE 0x0008U
7043 #define USART_SR_IDLE 0x0010U
7044 #define USART_SR_RXNE 0x0020U
7045 #define USART_SR_TC 0x0040U
7046 #define USART_SR_TXE 0x0080U
7047 #define USART_SR_LBD 0x0100U
7048 #define USART_SR_CTS 0x0200U
7050 /******************* Bit definition for USART_DR register *******************/
7051 #define USART_DR_DR 0x01FFU
7053 /****************** Bit definition for USART_BRR register *******************/
7054 #define USART_BRR_DIV_Fraction 0x000FU
7055 #define USART_BRR_DIV_Mantissa 0xFFF0U
7057 /****************** Bit definition for USART_CR1 register *******************/
7058 #define USART_CR1_SBK 0x0001U
7059 #define USART_CR1_RWU 0x0002U
7060 #define USART_CR1_RE 0x0004U
7061 #define USART_CR1_TE 0x0008U
7062 #define USART_CR1_IDLEIE 0x0010U
7063 #define USART_CR1_RXNEIE 0x0020U
7064 #define USART_CR1_TCIE 0x0040U
7065 #define USART_CR1_TXEIE 0x0080U
7066 #define USART_CR1_PEIE 0x0100U
7067 #define USART_CR1_PS 0x0200U
7068 #define USART_CR1_PCE 0x0400U
7069 #define USART_CR1_WAKE 0x0800U
7070 #define USART_CR1_M 0x1000U
7071 #define USART_CR1_UE 0x2000U
7072 #define USART_CR1_OVER8 0x8000U
7074 /****************** Bit definition for USART_CR2 register *******************/
7075 #define USART_CR2_ADD 0x000FU
7076 #define USART_CR2_LBDL 0x0020U
7077 #define USART_CR2_LBDIE 0x0040U
7078 #define USART_CR2_LBCL 0x0100U
7079 #define USART_CR2_CPHA 0x0200U
7080 #define USART_CR2_CPOL 0x0400U
7081 #define USART_CR2_CLKEN 0x0800U
7083 #define USART_CR2_STOP 0x3000U
7084 #define USART_CR2_STOP_0 0x1000U
7085 #define USART_CR2_STOP_1 0x2000U
7087 #define USART_CR2_LINEN 0x4000U
7089 /****************** Bit definition for USART_CR3 register *******************/
7090 #define USART_CR3_EIE 0x0001U
7091 #define USART_CR3_IREN 0x0002U
7092 #define USART_CR3_IRLP 0x0004U
7093 #define USART_CR3_HDSEL 0x0008U
7094 #define USART_CR3_NACK 0x0010U
7095 #define USART_CR3_SCEN 0x0020U
7096 #define USART_CR3_DMAR 0x0040U
7097 #define USART_CR3_DMAT 0x0080U
7098 #define USART_CR3_RTSE 0x0100U
7099 #define USART_CR3_CTSE 0x0200U
7100 #define USART_CR3_CTSIE 0x0400U
7101 #define USART_CR3_ONEBIT 0x0800U
7103 /****************** Bit definition for USART_GTPR register ******************/
7104 #define USART_GTPR_PSC 0x00FFU
7105 #define USART_GTPR_PSC_0 0x0001U
7106 #define USART_GTPR_PSC_1 0x0002U
7107 #define USART_GTPR_PSC_2 0x0004U
7108 #define USART_GTPR_PSC_3 0x0008U
7109 #define USART_GTPR_PSC_4 0x0010U
7110 #define USART_GTPR_PSC_5 0x0020U
7111 #define USART_GTPR_PSC_6 0x0040U
7112 #define USART_GTPR_PSC_7 0x0080U
7114 #define USART_GTPR_GT 0xFF00U
7116 /******************************************************************************/
7117 /* */
7118 /* Window WATCHDOG */
7119 /* */
7120 /******************************************************************************/
7121 /******************* Bit definition for WWDG_CR register ********************/
7122 #define WWDG_CR_T 0x7FU
7123 #define WWDG_CR_T_0 0x01U
7124 #define WWDG_CR_T_1 0x02U
7125 #define WWDG_CR_T_2 0x04U
7126 #define WWDG_CR_T_3 0x08U
7127 #define WWDG_CR_T_4 0x10U
7128 #define WWDG_CR_T_5 0x20U
7129 #define WWDG_CR_T_6 0x40U
7130 /* Legacy defines */
7131 #define WWDG_CR_T0 WWDG_CR_T_0
7132 #define WWDG_CR_T1 WWDG_CR_T_1
7133 #define WWDG_CR_T2 WWDG_CR_T_2
7134 #define WWDG_CR_T3 WWDG_CR_T_3
7135 #define WWDG_CR_T4 WWDG_CR_T_4
7136 #define WWDG_CR_T5 WWDG_CR_T_5
7137 #define WWDG_CR_T6 WWDG_CR_T_6
7138 
7139 #define WWDG_CR_WDGA 0x80U
7141 /******************* Bit definition for WWDG_CFR register *******************/
7142 #define WWDG_CFR_W 0x007FU
7143 #define WWDG_CFR_W_0 0x0001U
7144 #define WWDG_CFR_W_1 0x0002U
7145 #define WWDG_CFR_W_2 0x0004U
7146 #define WWDG_CFR_W_3 0x0008U
7147 #define WWDG_CFR_W_4 0x0010U
7148 #define WWDG_CFR_W_5 0x0020U
7149 #define WWDG_CFR_W_6 0x0040U
7150 /* Legacy defines */
7151 #define WWDG_CFR_W0 WWDG_CFR_W_0
7152 #define WWDG_CFR_W1 WWDG_CFR_W_1
7153 #define WWDG_CFR_W2 WWDG_CFR_W_2
7154 #define WWDG_CFR_W3 WWDG_CFR_W_3
7155 #define WWDG_CFR_W4 WWDG_CFR_W_4
7156 #define WWDG_CFR_W5 WWDG_CFR_W_5
7157 #define WWDG_CFR_W6 WWDG_CFR_W_6
7158 
7159 #define WWDG_CFR_WDGTB 0x0180U
7160 #define WWDG_CFR_WDGTB_0 0x0080U
7161 #define WWDG_CFR_WDGTB_1 0x0100U
7162 /* Legacy defines */
7163 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
7164 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
7165 
7166 #define WWDG_CFR_EWI 0x0200U
7168 /******************* Bit definition for WWDG_SR register ********************/
7169 #define WWDG_SR_EWIF 0x01U
7172 /******************************************************************************/
7173 /* */
7174 /* DBG */
7175 /* */
7176 /******************************************************************************/
7177 /******************** Bit definition for DBGMCU_IDCODE register *************/
7178 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
7179 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
7180 
7181 /******************** Bit definition for DBGMCU_CR register *****************/
7182 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
7183 #define DBGMCU_CR_DBG_STOP 0x00000002U
7184 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
7185 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
7186 
7187 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
7188 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
7189 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
7191 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
7192 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
7193 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
7194 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
7195 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
7196 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
7197 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
7198 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
7199 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
7200 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
7201 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
7202 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
7203 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
7204 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
7205 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
7206 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
7207 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
7208 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
7209 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
7210 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
7211 
7212 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
7213 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
7214 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
7215 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
7216 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
7217 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
7218 
7219 
7220 /******************************************************************************/
7221 /* */
7222 /* USB_OTG */
7223 /* */
7224 /******************************************************************************/
7225 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
7226 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
7227 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
7228 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
7229 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
7230 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
7231 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
7232 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
7233 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
7234 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
7235 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
7236 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
7237 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
7238 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
7239 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
7240 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
7241 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
7242 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
7243 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
7245 /******************** Bit definition for USB_OTG_HCFG register ********************/
7246 
7247 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
7248 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
7249 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
7250 #define USB_OTG_HCFG_FSLSS 0x00000004U
7252 /******************** Bit definition for USB_OTG_DCFG register ********************/
7253 
7254 #define USB_OTG_DCFG_DSPD 0x00000003U
7255 #define USB_OTG_DCFG_DSPD_0 0x00000001U
7256 #define USB_OTG_DCFG_DSPD_1 0x00000002U
7257 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
7259 #define USB_OTG_DCFG_DAD 0x000007F0U
7260 #define USB_OTG_DCFG_DAD_0 0x00000010U
7261 #define USB_OTG_DCFG_DAD_1 0x00000020U
7262 #define USB_OTG_DCFG_DAD_2 0x00000040U
7263 #define USB_OTG_DCFG_DAD_3 0x00000080U
7264 #define USB_OTG_DCFG_DAD_4 0x00000100U
7265 #define USB_OTG_DCFG_DAD_5 0x00000200U
7266 #define USB_OTG_DCFG_DAD_6 0x00000400U
7268 #define USB_OTG_DCFG_PFIVL 0x00001800U
7269 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
7270 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
7272 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
7273 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
7274 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
7276 /******************** Bit definition for USB_OTG_PCGCR register ********************/
7277 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
7278 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
7279 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
7281 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
7282 #define USB_OTG_GOTGINT_SEDET 0x00000004U
7283 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
7284 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
7285 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
7286 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
7287 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
7288 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
7290 /******************** Bit definition for USB_OTG_DCTL register ********************/
7291 #define USB_OTG_DCTL_RWUSIG 0x00000001U
7292 #define USB_OTG_DCTL_SDIS 0x00000002U
7293 #define USB_OTG_DCTL_GINSTS 0x00000004U
7294 #define USB_OTG_DCTL_GONSTS 0x00000008U
7296 #define USB_OTG_DCTL_TCTL 0x00000070U
7297 #define USB_OTG_DCTL_TCTL_0 0x00000010U
7298 #define USB_OTG_DCTL_TCTL_1 0x00000020U
7299 #define USB_OTG_DCTL_TCTL_2 0x00000040U
7300 #define USB_OTG_DCTL_SGINAK 0x00000080U
7301 #define USB_OTG_DCTL_CGINAK 0x00000100U
7302 #define USB_OTG_DCTL_SGONAK 0x00000200U
7303 #define USB_OTG_DCTL_CGONAK 0x00000400U
7304 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
7306 /******************** Bit definition for USB_OTG_HFIR register ********************/
7307 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
7309 /******************** Bit definition for USB_OTG_HFNUM register ********************/
7310 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
7311 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
7313 /******************** Bit definition for USB_OTG_DSTS register ********************/
7314 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
7316 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
7317 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
7318 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
7319 #define USB_OTG_DSTS_EERR 0x00000008U
7320 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
7322 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
7323 #define USB_OTG_GAHBCFG_GINT 0x00000001U
7324 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
7325 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
7326 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
7327 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
7328 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
7329 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
7330 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
7331 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
7333 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
7334 
7335 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
7336 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
7337 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
7338 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
7339 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
7340 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
7341 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
7342 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
7343 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
7344 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
7345 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
7346 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
7347 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
7348 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
7349 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
7350 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
7351 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
7352 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
7353 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
7354 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
7355 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
7356 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
7357 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
7358 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
7359 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
7361 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
7362 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
7363 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
7364 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
7365 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
7366 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
7367 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
7368 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
7369 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
7370 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
7371 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
7372 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
7373 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
7374 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
7376 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
7377 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
7378 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
7379 #define USB_OTG_DIEPMSK_TOM 0x00000008U
7380 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
7381 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
7382 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
7383 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
7384 #define USB_OTG_DIEPMSK_BIM 0x00000200U
7386 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
7387 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
7388 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
7389 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
7390 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
7391 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
7392 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
7393 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
7394 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
7395 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
7396 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
7398 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
7399 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
7400 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
7401 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
7402 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
7403 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
7404 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
7405 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
7406 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
7408 /******************** Bit definition for USB_OTG_HAINT register ********************/
7409 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
7411 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
7412 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
7413 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
7414 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
7415 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
7416 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
7417 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
7418 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
7419 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
7421 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
7422 #define USB_OTG_GINTSTS_CMOD 0x00000001U
7423 #define USB_OTG_GINTSTS_MMIS 0x00000002U
7424 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
7425 #define USB_OTG_GINTSTS_SOF 0x00000008U
7426 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
7427 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
7428 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
7429 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
7430 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
7431 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
7432 #define USB_OTG_GINTSTS_USBRST 0x00001000U
7433 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
7434 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
7435 #define USB_OTG_GINTSTS_EOPF 0x00008000U
7436 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
7437 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
7438 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
7439 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
7440 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
7441 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
7442 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
7443 #define USB_OTG_GINTSTS_HCINT 0x02000000U
7444 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
7445 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
7446 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
7447 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
7448 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
7449 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
7451 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
7452 #define USB_OTG_GINTMSK_MMISM 0x00000002U
7453 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
7454 #define USB_OTG_GINTMSK_SOFM 0x00000008U
7455 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
7456 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
7457 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
7458 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
7459 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
7460 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
7461 #define USB_OTG_GINTMSK_USBRST 0x00001000U
7462 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
7463 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
7464 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
7465 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
7466 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
7467 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
7468 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
7469 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
7470 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
7471 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U
7472 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
7473 #define USB_OTG_GINTMSK_HCIM 0x02000000U
7474 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
7475 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
7476 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
7477 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
7478 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
7479 #define USB_OTG_GINTMSK_WUIM 0x80000000U
7481 /******************** Bit definition for USB_OTG_DAINT register ********************/
7482 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
7483 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
7485 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
7486 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
7488 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
7489 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
7490 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
7491 #define USB_OTG_GRXSTSP_DPID 0x00018000U
7492 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
7494 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
7495 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
7496 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
7498 /******************** Bit definition for OTG register ********************/
7499 
7500 #define USB_OTG_CHNUM 0x0000000FU
7501 #define USB_OTG_CHNUM_0 0x00000001U
7502 #define USB_OTG_CHNUM_1 0x00000002U
7503 #define USB_OTG_CHNUM_2 0x00000004U
7504 #define USB_OTG_CHNUM_3 0x00000008U
7505 #define USB_OTG_BCNT 0x00007FF0U
7507 #define USB_OTG_DPID 0x00018000U
7508 #define USB_OTG_DPID_0 0x00008000U
7509 #define USB_OTG_DPID_1 0x00010000U
7511 #define USB_OTG_PKTSTS 0x001E0000U
7512 #define USB_OTG_PKTSTS_0 0x00020000U
7513 #define USB_OTG_PKTSTS_1 0x00040000U
7514 #define USB_OTG_PKTSTS_2 0x00080000U
7515 #define USB_OTG_PKTSTS_3 0x00100000U
7517 #define USB_OTG_EPNUM 0x0000000FU
7518 #define USB_OTG_EPNUM_0 0x00000001U
7519 #define USB_OTG_EPNUM_1 0x00000002U
7520 #define USB_OTG_EPNUM_2 0x00000004U
7521 #define USB_OTG_EPNUM_3 0x00000008U
7523 #define USB_OTG_FRMNUM 0x01E00000U
7524 #define USB_OTG_FRMNUM_0 0x00200000U
7525 #define USB_OTG_FRMNUM_1 0x00400000U
7526 #define USB_OTG_FRMNUM_2 0x00800000U
7527 #define USB_OTG_FRMNUM_3 0x01000000U
7529 /******************** Bit definition for OTG register ********************/
7530 
7531 #define USB_OTG_CHNUM 0x0000000FU
7532 #define USB_OTG_CHNUM_0 0x00000001U
7533 #define USB_OTG_CHNUM_1 0x00000002U
7534 #define USB_OTG_CHNUM_2 0x00000004U
7535 #define USB_OTG_CHNUM_3 0x00000008U
7536 #define USB_OTG_BCNT 0x00007FF0U
7538 #define USB_OTG_DPID 0x00018000U
7539 #define USB_OTG_DPID_0 0x00008000U
7540 #define USB_OTG_DPID_1 0x00010000U
7542 #define USB_OTG_PKTSTS 0x001E0000U
7543 #define USB_OTG_PKTSTS_0 0x00020000U
7544 #define USB_OTG_PKTSTS_1 0x00040000U
7545 #define USB_OTG_PKTSTS_2 0x00080000U
7546 #define USB_OTG_PKTSTS_3 0x00100000U
7548 #define USB_OTG_EPNUM 0x0000000FU
7549 #define USB_OTG_EPNUM_0 0x00000001U
7550 #define USB_OTG_EPNUM_1 0x00000002U
7551 #define USB_OTG_EPNUM_2 0x00000004U
7552 #define USB_OTG_EPNUM_3 0x00000008U
7554 #define USB_OTG_FRMNUM 0x01E00000U
7555 #define USB_OTG_FRMNUM_0 0x00200000U
7556 #define USB_OTG_FRMNUM_1 0x00400000U
7557 #define USB_OTG_FRMNUM_2 0x00800000U
7558 #define USB_OTG_FRMNUM_3 0x01000000U
7560 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
7561 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
7563 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
7564 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
7566 /******************** Bit definition for OTG register ********************/
7567 #define USB_OTG_NPTXFSA 0x0000FFFFU
7568 #define USB_OTG_NPTXFD 0xFFFF0000U
7569 #define USB_OTG_TX0FSA 0x0000FFFFU
7570 #define USB_OTG_TX0FD 0xFFFF0000U
7572 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
7573 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
7575 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
7576 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
7578 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
7579 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
7580 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
7581 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
7582 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
7583 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
7584 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
7585 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
7586 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
7588 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
7589 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
7590 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
7591 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
7592 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
7593 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
7594 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
7595 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
7597 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
7598 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
7599 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
7601 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
7602 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
7603 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
7604 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
7605 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
7606 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
7607 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
7608 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
7609 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
7610 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
7611 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
7613 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
7614 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
7615 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
7616 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
7617 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
7618 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
7619 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
7620 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
7621 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
7622 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
7623 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
7625 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
7626 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
7628 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
7629 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
7630 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
7632 /******************** Bit definition for USB_OTG_GCCFG register ********************/
7633 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
7634 #define USB_OTG_GCCFG_VBDEN 0x00200000U
7636 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
7637 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
7638 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
7640 /******************** Bit definition for USB_OTG_CID register ********************/
7641 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
7643 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
7644 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
7645 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
7646 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
7647 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
7648 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
7649 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
7650 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
7651 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
7652 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
7653 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
7654 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
7655 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
7656 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
7657 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
7658 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
7660 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
7661 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
7662 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
7663 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
7664 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
7665 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
7666 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
7667 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
7668 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
7669 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
7671 /******************** Bit definition for USB_OTG_HPRT register ********************/
7672 #define USB_OTG_HPRT_PCSTS 0x00000001U
7673 #define USB_OTG_HPRT_PCDET 0x00000002U
7674 #define USB_OTG_HPRT_PENA 0x00000004U
7675 #define USB_OTG_HPRT_PENCHNG 0x00000008U
7676 #define USB_OTG_HPRT_POCA 0x00000010U
7677 #define USB_OTG_HPRT_POCCHNG 0x00000020U
7678 #define USB_OTG_HPRT_PRES 0x00000040U
7679 #define USB_OTG_HPRT_PSUSP 0x00000080U
7680 #define USB_OTG_HPRT_PRST 0x00000100U
7682 #define USB_OTG_HPRT_PLSTS 0x00000C00U
7683 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
7684 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
7685 #define USB_OTG_HPRT_PPWR 0x00001000U
7687 #define USB_OTG_HPRT_PTCTL 0x0001E000U
7688 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
7689 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
7690 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
7691 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
7693 #define USB_OTG_HPRT_PSPD 0x00060000U
7694 #define USB_OTG_HPRT_PSPD_0 0x00020000U
7695 #define USB_OTG_HPRT_PSPD_1 0x00040000U
7697 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
7698 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
7699 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
7700 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
7701 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
7702 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
7703 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
7704 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
7705 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
7706 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
7707 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
7708 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
7710 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
7711 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
7712 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
7714 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
7715 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
7716 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
7717 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
7718 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
7720 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
7721 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
7722 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
7723 #define USB_OTG_DIEPCTL_STALL 0x00200000U
7725 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
7726 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
7727 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
7728 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
7729 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
7730 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
7731 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
7732 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
7733 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
7734 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
7735 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
7737 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
7738 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
7740 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
7741 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
7742 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
7743 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
7744 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
7745 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
7746 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
7748 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
7749 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
7750 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
7752 #define USB_OTG_HCCHAR_MC 0x00300000U
7753 #define USB_OTG_HCCHAR_MC_0 0x00100000U
7754 #define USB_OTG_HCCHAR_MC_1 0x00200000U
7756 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
7757 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
7758 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
7759 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
7760 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
7761 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
7762 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
7763 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
7764 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
7765 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
7766 #define USB_OTG_HCCHAR_CHENA 0x80000000U
7768 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
7769 
7770 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
7771 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
7772 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
7773 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
7774 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
7775 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
7776 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
7777 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
7779 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
7780 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
7781 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
7782 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
7783 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
7784 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
7785 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
7786 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
7788 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
7789 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
7790 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
7791 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
7792 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
7794 /******************** Bit definition for USB_OTG_HCINT register ********************/
7795 #define USB_OTG_HCINT_XFRC 0x00000001U
7796 #define USB_OTG_HCINT_CHH 0x00000002U
7797 #define USB_OTG_HCINT_AHBERR 0x00000004U
7798 #define USB_OTG_HCINT_STALL 0x00000008U
7799 #define USB_OTG_HCINT_NAK 0x00000010U
7800 #define USB_OTG_HCINT_ACK 0x00000020U
7801 #define USB_OTG_HCINT_NYET 0x00000040U
7802 #define USB_OTG_HCINT_TXERR 0x00000080U
7803 #define USB_OTG_HCINT_BBERR 0x00000100U
7804 #define USB_OTG_HCINT_FRMOR 0x00000200U
7805 #define USB_OTG_HCINT_DTERR 0x00000400U
7807 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
7808 #define USB_OTG_DIEPINT_XFRC 0x00000001U
7809 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
7810 #define USB_OTG_DIEPINT_TOC 0x00000008U
7811 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
7812 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
7813 #define USB_OTG_DIEPINT_TXFE 0x00000080U
7814 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
7815 #define USB_OTG_DIEPINT_BNA 0x00000200U
7816 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
7817 #define USB_OTG_DIEPINT_BERR 0x00001000U
7818 #define USB_OTG_DIEPINT_NAK 0x00002000U
7820 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
7821 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
7822 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
7823 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
7824 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
7825 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
7826 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
7827 #define USB_OTG_HCINTMSK_NYET 0x00000040U
7828 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
7829 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
7830 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
7831 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
7833 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
7834 
7835 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
7836 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
7837 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
7838 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
7839 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
7840 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
7841 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
7842 #define USB_OTG_HCTSIZ_DPID 0x60000000U
7843 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
7844 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
7846 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
7847 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
7849 /******************** Bit definition for USB_OTG_HCDMA register ********************/
7850 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
7852 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
7853 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
7855 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
7856 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
7857 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
7859 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
7860 
7861 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
7862 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
7863 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
7864 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
7865 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
7866 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
7867 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
7868 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
7869 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
7870 #define USB_OTG_DOEPCTL_STALL 0x00200000U
7871 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
7872 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
7873 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
7874 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
7876 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
7877 #define USB_OTG_DOEPINT_XFRC 0x00000001U
7878 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
7879 #define USB_OTG_DOEPINT_STUP 0x00000008U
7880 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
7881 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
7882 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
7883 #define USB_OTG_DOEPINT_NYET 0x00004000U
7885 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
7886 
7887 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
7888 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
7890 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
7891 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
7892 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
7894 /******************** Bit definition for PCGCCTL register ********************/
7895 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
7896 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
7897 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
7912 /******************************* ADC Instances ********************************/
7913 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
7914  ((INSTANCE) == ADC2) || \
7915  ((INSTANCE) == ADC3))
7916 
7917 /******************************* CAN Instances ********************************/
7918 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
7919  ((INSTANCE) == CAN2))
7920 
7921 /******************************* CRC Instances ********************************/
7922 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7923 
7924 /******************************* DAC Instances ********************************/
7925 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
7926 
7927 /******************************* DCMI Instances *******************************/
7928 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
7929 
7930 /******************************** DMA Instances *******************************/
7931 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7932  ((INSTANCE) == DMA1_Stream1) || \
7933  ((INSTANCE) == DMA1_Stream2) || \
7934  ((INSTANCE) == DMA1_Stream3) || \
7935  ((INSTANCE) == DMA1_Stream4) || \
7936  ((INSTANCE) == DMA1_Stream5) || \
7937  ((INSTANCE) == DMA1_Stream6) || \
7938  ((INSTANCE) == DMA1_Stream7) || \
7939  ((INSTANCE) == DMA2_Stream0) || \
7940  ((INSTANCE) == DMA2_Stream1) || \
7941  ((INSTANCE) == DMA2_Stream2) || \
7942  ((INSTANCE) == DMA2_Stream3) || \
7943  ((INSTANCE) == DMA2_Stream4) || \
7944  ((INSTANCE) == DMA2_Stream5) || \
7945  ((INSTANCE) == DMA2_Stream6) || \
7946  ((INSTANCE) == DMA2_Stream7))
7947 
7948 /******************************* GPIO Instances *******************************/
7949 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7950  ((INSTANCE) == GPIOB) || \
7951  ((INSTANCE) == GPIOC) || \
7952  ((INSTANCE) == GPIOD) || \
7953  ((INSTANCE) == GPIOE) || \
7954  ((INSTANCE) == GPIOF) || \
7955  ((INSTANCE) == GPIOG) || \
7956  ((INSTANCE) == GPIOH))
7957 
7958 /******************************** I2C Instances *******************************/
7959 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7960  ((INSTANCE) == I2C2) || \
7961  ((INSTANCE) == I2C3))
7962 
7963 /******************************** I2S Instances *******************************/
7964 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7965  ((INSTANCE) == SPI2) || \
7966  ((INSTANCE) == SPI3))
7967 
7968 /****************************** RTC Instances *********************************/
7969 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7970 
7971 /******************************* SAI Instances ********************************/
7972 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
7973  ((PERIPH) == SAI1_Block_B) || \
7974  ((PERIPH) == SAI2_Block_A) || \
7975  ((PERIPH) == SAI2_Block_B))
7976 /* Legacy define */
7977 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
7978 
7979 /******************************** SPI Instances *******************************/
7980 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7981  ((INSTANCE) == SPI2) || \
7982  ((INSTANCE) == SPI3) || \
7983  ((INSTANCE) == SPI4))
7984 
7985 /****************** TIM Instances : All supported instances *******************/
7986 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7987  ((INSTANCE) == TIM2) || \
7988  ((INSTANCE) == TIM3) || \
7989  ((INSTANCE) == TIM4) || \
7990  ((INSTANCE) == TIM5) || \
7991  ((INSTANCE) == TIM6) || \
7992  ((INSTANCE) == TIM7) || \
7993  ((INSTANCE) == TIM8) || \
7994  ((INSTANCE) == TIM9) || \
7995  ((INSTANCE) == TIM10) || \
7996  ((INSTANCE) == TIM11) || \
7997  ((INSTANCE) == TIM12) || \
7998  ((INSTANCE) == TIM13) || \
7999  ((INSTANCE) == TIM14))
8000 
8001 /************* TIM Instances : at least 1 capture/compare channel *************/
8002 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8003  ((INSTANCE) == TIM2) || \
8004  ((INSTANCE) == TIM3) || \
8005  ((INSTANCE) == TIM4) || \
8006  ((INSTANCE) == TIM5) || \
8007  ((INSTANCE) == TIM8) || \
8008  ((INSTANCE) == TIM9) || \
8009  ((INSTANCE) == TIM10) || \
8010  ((INSTANCE) == TIM11) || \
8011  ((INSTANCE) == TIM12) || \
8012  ((INSTANCE) == TIM13) || \
8013  ((INSTANCE) == TIM14))
8014 
8015 /************ TIM Instances : at least 2 capture/compare channels *************/
8016 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8017  ((INSTANCE) == TIM2) || \
8018  ((INSTANCE) == TIM3) || \
8019  ((INSTANCE) == TIM4) || \
8020  ((INSTANCE) == TIM5) || \
8021  ((INSTANCE) == TIM8) || \
8022  ((INSTANCE) == TIM9) || \
8023  ((INSTANCE) == TIM12))
8024 
8025 /************ TIM Instances : at least 3 capture/compare channels *************/
8026 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8027  ((INSTANCE) == TIM2) || \
8028  ((INSTANCE) == TIM3) || \
8029  ((INSTANCE) == TIM4) || \
8030  ((INSTANCE) == TIM5) || \
8031  ((INSTANCE) == TIM8))
8032 
8033 /************ TIM Instances : at least 4 capture/compare channels *************/
8034 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8035  ((INSTANCE) == TIM2) || \
8036  ((INSTANCE) == TIM3) || \
8037  ((INSTANCE) == TIM4) || \
8038  ((INSTANCE) == TIM5) || \
8039  ((INSTANCE) == TIM8))
8040 
8041 /******************** TIM Instances : Advanced-control timers *****************/
8042 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8043  ((INSTANCE) == TIM8))
8044 
8045 /******************* TIM Instances : Timer input XOR function *****************/
8046 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8047  ((INSTANCE) == TIM2) || \
8048  ((INSTANCE) == TIM3) || \
8049  ((INSTANCE) == TIM4) || \
8050  ((INSTANCE) == TIM5) || \
8051  ((INSTANCE) == TIM8))
8052 
8053 /****************** TIM Instances : DMA requests generation (UDE) *************/
8054 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8055  ((INSTANCE) == TIM2) || \
8056  ((INSTANCE) == TIM3) || \
8057  ((INSTANCE) == TIM4) || \
8058  ((INSTANCE) == TIM5) || \
8059  ((INSTANCE) == TIM6) || \
8060  ((INSTANCE) == TIM7) || \
8061  ((INSTANCE) == TIM8))
8062 
8063 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8064 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8065  ((INSTANCE) == TIM2) || \
8066  ((INSTANCE) == TIM3) || \
8067  ((INSTANCE) == TIM4) || \
8068  ((INSTANCE) == TIM5) || \
8069  ((INSTANCE) == TIM8))
8070 
8071 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8072 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8073  ((INSTANCE) == TIM2) || \
8074  ((INSTANCE) == TIM3) || \
8075  ((INSTANCE) == TIM4) || \
8076  ((INSTANCE) == TIM5) || \
8077  ((INSTANCE) == TIM8))
8078 
8079 /******************** TIM Instances : DMA burst feature ***********************/
8080 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8081  ((INSTANCE) == TIM2) || \
8082  ((INSTANCE) == TIM3) || \
8083  ((INSTANCE) == TIM4) || \
8084  ((INSTANCE) == TIM5) || \
8085  ((INSTANCE) == TIM8))
8086 
8087 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8088 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8089  ((INSTANCE) == TIM2) || \
8090  ((INSTANCE) == TIM3) || \
8091  ((INSTANCE) == TIM4) || \
8092  ((INSTANCE) == TIM5) || \
8093  ((INSTANCE) == TIM6) || \
8094  ((INSTANCE) == TIM7) || \
8095  ((INSTANCE) == TIM8) || \
8096  ((INSTANCE) == TIM9) || \
8097  ((INSTANCE) == TIM12))
8098 
8099 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8100 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8101  ((INSTANCE) == TIM2) || \
8102  ((INSTANCE) == TIM3) || \
8103  ((INSTANCE) == TIM4) || \
8104  ((INSTANCE) == TIM5) || \
8105  ((INSTANCE) == TIM8) || \
8106  ((INSTANCE) == TIM9) || \
8107  ((INSTANCE) == TIM12))
8108 
8109 /********************** TIM Instances : 32 bit Counter ************************/
8110 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
8111  ((INSTANCE) == TIM5))
8112 
8113 /***************** TIM Instances : external trigger input availabe ************/
8114 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8115  ((INSTANCE) == TIM2) || \
8116  ((INSTANCE) == TIM3) || \
8117  ((INSTANCE) == TIM4) || \
8118  ((INSTANCE) == TIM5) || \
8119  ((INSTANCE) == TIM8))
8120 
8121 /****************** TIM Instances : remapping capability **********************/
8122 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8123  ((INSTANCE) == TIM5) || \
8124  ((INSTANCE) == TIM11))
8125 
8126 /******************* TIM Instances : output(s) available **********************/
8127 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8128  ((((INSTANCE) == TIM1) && \
8129  (((CHANNEL) == TIM_CHANNEL_1) || \
8130  ((CHANNEL) == TIM_CHANNEL_2) || \
8131  ((CHANNEL) == TIM_CHANNEL_3) || \
8132  ((CHANNEL) == TIM_CHANNEL_4))) \
8133  || \
8134  (((INSTANCE) == TIM2) && \
8135  (((CHANNEL) == TIM_CHANNEL_1) || \
8136  ((CHANNEL) == TIM_CHANNEL_2) || \
8137  ((CHANNEL) == TIM_CHANNEL_3) || \
8138  ((CHANNEL) == TIM_CHANNEL_4))) \
8139  || \
8140  (((INSTANCE) == TIM3) && \
8141  (((CHANNEL) == TIM_CHANNEL_1) || \
8142  ((CHANNEL) == TIM_CHANNEL_2) || \
8143  ((CHANNEL) == TIM_CHANNEL_3) || \
8144  ((CHANNEL) == TIM_CHANNEL_4))) \
8145  || \
8146  (((INSTANCE) == TIM4) && \
8147  (((CHANNEL) == TIM_CHANNEL_1) || \
8148  ((CHANNEL) == TIM_CHANNEL_2) || \
8149  ((CHANNEL) == TIM_CHANNEL_3) || \
8150  ((CHANNEL) == TIM_CHANNEL_4))) \
8151  || \
8152  (((INSTANCE) == TIM5) && \
8153  (((CHANNEL) == TIM_CHANNEL_1) || \
8154  ((CHANNEL) == TIM_CHANNEL_2) || \
8155  ((CHANNEL) == TIM_CHANNEL_3) || \
8156  ((CHANNEL) == TIM_CHANNEL_4))) \
8157  || \
8158  (((INSTANCE) == TIM8) && \
8159  (((CHANNEL) == TIM_CHANNEL_1) || \
8160  ((CHANNEL) == TIM_CHANNEL_2) || \
8161  ((CHANNEL) == TIM_CHANNEL_3) || \
8162  ((CHANNEL) == TIM_CHANNEL_4))) \
8163  || \
8164  (((INSTANCE) == TIM9) && \
8165  (((CHANNEL) == TIM_CHANNEL_1) || \
8166  ((CHANNEL) == TIM_CHANNEL_2))) \
8167  || \
8168  (((INSTANCE) == TIM10) && \
8169  (((CHANNEL) == TIM_CHANNEL_1))) \
8170  || \
8171  (((INSTANCE) == TIM11) && \
8172  (((CHANNEL) == TIM_CHANNEL_1))) \
8173  || \
8174  (((INSTANCE) == TIM12) && \
8175  (((CHANNEL) == TIM_CHANNEL_1) || \
8176  ((CHANNEL) == TIM_CHANNEL_2))) \
8177  || \
8178  (((INSTANCE) == TIM13) && \
8179  (((CHANNEL) == TIM_CHANNEL_1))) \
8180  || \
8181  (((INSTANCE) == TIM14) && \
8182  (((CHANNEL) == TIM_CHANNEL_1))))
8183 
8184 /************ TIM Instances : complementary output(s) available ***************/
8185 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8186  ((((INSTANCE) == TIM1) && \
8187  (((CHANNEL) == TIM_CHANNEL_1) || \
8188  ((CHANNEL) == TIM_CHANNEL_2) || \
8189  ((CHANNEL) == TIM_CHANNEL_3))) \
8190  || \
8191  (((INSTANCE) == TIM8) && \
8192  (((CHANNEL) == TIM_CHANNEL_1) || \
8193  ((CHANNEL) == TIM_CHANNEL_2) || \
8194  ((CHANNEL) == TIM_CHANNEL_3))))
8195 
8196 /******************** USART Instances : Synchronous mode **********************/
8197 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8198  ((INSTANCE) == USART2) || \
8199  ((INSTANCE) == USART3) || \
8200  ((INSTANCE) == USART6))
8201 
8202 /******************** UART Instances : Asynchronous mode **********************/
8203 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8204  ((INSTANCE) == USART2) || \
8205  ((INSTANCE) == USART3) || \
8206  ((INSTANCE) == UART4) || \
8207  ((INSTANCE) == UART5) || \
8208  ((INSTANCE) == USART6))
8209 
8210 /****************** UART Instances : Hardware Flow control ********************/
8211 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8212  ((INSTANCE) == USART2) || \
8213  ((INSTANCE) == USART3) || \
8214  ((INSTANCE) == USART6))
8215 
8216 /********************* UART Instances : Smard card mode ***********************/
8217 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8218  ((INSTANCE) == USART2) || \
8219  ((INSTANCE) == USART3) || \
8220  ((INSTANCE) == USART6))
8221 
8222 /*********************** UART Instances : IRDA mode ***************************/
8223 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8224  ((INSTANCE) == USART2) || \
8225  ((INSTANCE) == USART3) || \
8226  ((INSTANCE) == UART4) || \
8227  ((INSTANCE) == UART5) || \
8228  ((INSTANCE) == USART6))
8229 
8230 /*********************** PCD Instances ****************************************/
8231 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
8232  ((INSTANCE) == USB_OTG_HS))
8233 
8234 /*********************** HCD Instances ****************************************/
8235 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
8236  ((INSTANCE) == USB_OTG_HS))
8237 
8238 /****************************** SDIO Instances ********************************/
8239 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
8240 
8241 /****************************** IWDG Instances ********************************/
8242 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
8243 
8244 /****************************** WWDG Instances ********************************/
8245 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8246 
8247 /****************************** QSPI Instances ********************************/
8248 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
8249 
8250 /******************************* CEC Instances ********************************/
8251 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
8252 
8253 /***************************** FMPI2C Instances *******************************/
8254 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
8255 
8256 /******************************* SPDIFRX Instances ********************************/
8257 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
8258 
8259 /****************************** USB Exported Constants ************************/
8260 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
8261 #define USB_OTG_FS_MAX_IN_ENDPOINTS 5U /* Including EP0 */
8262 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 5U /* Including EP0 */
8263 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
8264 
8265 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
8266 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
8267 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
8268 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
8269 
8270 /******************************************************************************/
8271 /* For a painless codes migration between the STM32F4xx device product */
8272 /* lines, the aliases defined below are put in place to overcome the */
8273 /* differences in the interrupt handlers and IRQn definitions. */
8274 /* No need to update developed interrupt code when moving across */
8275 /* product lines within the same STM32F4 Family */
8276 /******************************************************************************/
8277 
8278 /* Aliases for __IRQHandler */
8279 #define QuadSPI_IRQHandler QUADSPI_IRQHandler
8280 
8293 #ifdef __cplusplus
8294 }
8295 #endif /* __cplusplus */
8296 
8297 #endif /* __STM32F446xx_H */
8298 
8299 
8300 
8301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
SPDIFRX_TypeDef::IFCR
__IO uint16_t IFCR
Definition: stm32f446xx.h:752
CEC_IRQn
Definition: stm32f446xx.h:178
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
SAI1_IRQn
Definition: stm32f446xx.h:175
TAMP_STAMP_IRQn
Definition: stm32f446xx.h:98
QUADSPI_IRQn
Definition: stm32f446xx.h:177
TIM2_IRQn
Definition: stm32f446xx.h:124
UART4_IRQn
Definition: stm32f446xx.h:148
SPDIFRX_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f446xx.h:753
CEC_TypeDef::IER
__IO uint32_t IER
Definition: stm32f446xx.h:308
UART5_IRQn
Definition: stm32f446xx.h:149
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f446xx.h:122
EXTI2_IRQn
Definition: stm32f446xx.h:104
EXTI4_IRQn
Definition: stm32f446xx.h:106
USART1_IRQn
Definition: stm32f446xx.h:133
SPDIFRX_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:748
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f446xx.h:141
TIM4_IRQn
Definition: stm32f446xx.h:126
SPDIFRX_TypeDef
SPDIFRX Interface.
Definition: stm32f446xx.h:746
RTC_Alarm_IRQn
Definition: stm32f446xx.h:137
CEC_TypeDef
Consumer Electronics Control.
Definition: stm32f446xx.h:301
CAN2_SCE_IRQn
Definition: stm32f446xx.h:160
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f446xx.h:451
PendSV_IRQn
Definition: stm32f446xx.h:93
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f446xx.h:99
CAN1_RX1_IRQn
Definition: stm32f446xx.h:117
TIM6_DAC_IRQn
Definition: stm32f446xx.h:150
CAN1_TX_IRQn
Definition: stm32f446xx.h:115
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f446xx.h:131
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f427xx.h:534
OTG_FS_WKUP_IRQn
Definition: stm32f446xx.h:138
DMA_TypeDef
Definition: stm32f401xc.h:243
DMA1_Stream2_IRQn
Definition: stm32f446xx.h:109
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f446xx.h:132
SPDIFRX_TypeDef::RESERVED0
uint16_t RESERVED0
Definition: stm32f446xx.h:750
FMPI2C1_ER_IRQn
Definition: stm32f446xx.h:181
__I
#define __I
Definition: core_cm0.h:210
DMA2_Stream5_IRQn
Definition: stm32f446xx.h:162
ADC_IRQn
Definition: stm32f446xx.h:114
CAN1_RX0_IRQn
Definition: stm32f446xx.h:116
RCC_IRQn
Definition: stm32f446xx.h:101
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
SPDIFRX_TypeDef::DIR
__IO uint32_t DIR
Definition: stm32f446xx.h:756
FMC_Bank3_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:454
DebugMonitor_IRQn
Definition: stm32f446xx.h:92
SPDIFRX_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f446xx.h:757
DMA2_Stream3_IRQn
Definition: stm32f446xx.h:155
NonMaskableInt_IRQn
Definition: stm32f446xx.h:87
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f446xx.h:84
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f446xx.h:140
CEC_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f446xx.h:305
DMA1_Stream1_IRQn
Definition: stm32f446xx.h:108
DMA2_Stream7_IRQn
Definition: stm32f446xx.h:164
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f412rx.h:645
FMC_Bank3_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32f446xx.h:457
DMA2_Stream6_IRQn
Definition: stm32f446xx.h:163
BusFault_IRQn
Definition: stm32f446xx.h:89
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
CEC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:303
I2C3_ER_IRQn
Definition: stm32f446xx.h:167
CAN2_RX0_IRQn
Definition: stm32f446xx.h:158
USART6_IRQn
Definition: stm32f446xx.h:165
PVD_IRQn
Definition: stm32f446xx.h:97
FMC_Bank3_TypeDef::PATT
__IO uint32_t PATT
Definition: stm32f446xx.h:456
__IO
#define __IO
Definition: core_cm0.h:213
SPDIFRX_TypeDef::IMR
__IO uint16_t IMR
Definition: stm32f446xx.h:749
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f446xx.h:111
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f427xx.h:750
DMA1_Stream0_IRQn
Definition: stm32f446xx.h:107
OTG_HS_IRQn
Definition: stm32f446xx.h:171
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f446xx.h:174
TIM8_CC_IRQn
Definition: stm32f446xx.h:142
DMA1_Stream3_IRQn
Definition: stm32f446xx.h:110
FPU_IRQn
Definition: stm32f446xx.h:173
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
OTG_FS_IRQn
Definition: stm32f446xx.h:161
DMA2_Stream2_IRQn
Definition: stm32f446xx.h:154
OTG_HS_EP1_OUT_IRQn
Definition: stm32f446xx.h:168
OTG_HS_EP1_IN_IRQn
Definition: stm32f446xx.h:169
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f446xx.h:145
FMPI2C1_EV_IRQn
Definition: stm32f446xx.h:180
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f446xx.h:166
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f446xx.h:134
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f446xx.h:151
I2C2_EV_IRQn
Definition: stm32f446xx.h:129
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
FMC_Bank3_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32f446xx.h:453
TIM3_IRQn
Definition: stm32f446xx.h:125
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f446xx.h:103
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f446xx.h:91
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f446xx.h:123
TIM8_BRK_TIM12_IRQn
Definition: stm32f446xx.h:139
SPDIFRX_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f446xx.h:755
FLASH_IRQn
Definition: stm32f446xx.h:100
DMA1_Stream5_IRQn
Definition: stm32f446xx.h:112
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f446xx.h:94
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f427xx.h:525
TIM1_UP_TIM10_IRQn
Definition: stm32f446xx.h:121
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f446xx.h:130
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:344
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f427xx.h:578
CEC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f446xx.h:304
CEC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f446xx.h:307
SPDIF_RX_IRQn
Definition: stm32f446xx.h:179
UsageFault_IRQn
Definition: stm32f446xx.h:90
CEC_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f446xx.h:306
FMC_IRQn
Definition: stm32f446xx.h:144
SPI3_IRQn
Definition: stm32f446xx.h:147
DMA2_Stream1_IRQn
Definition: stm32f446xx.h:153
EXTI9_5_IRQn
Definition: stm32f446xx.h:119
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
SPDIFRX_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:751
I2C1_EV_IRQn
Definition: stm32f446xx.h:127
DMA1_Stream6_IRQn
Definition: stm32f446xx.h:113
OTG_HS_WKUP_IRQn
Definition: stm32f446xx.h:170
I2C1_ER_IRQn
Definition: stm32f446xx.h:128
FMPI2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f410cx.h:354
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
SAI_Block_TypeDef
Definition: stm32f427xx.h:755
FMC_Bank3_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32f446xx.h:458
CAN2_RX1_IRQn
Definition: stm32f446xx.h:159
DMA2_Stream4_IRQn
Definition: stm32f446xx.h:156
WWDG_IRQn
Definition: stm32f446xx.h:96
DMA1_Stream7_IRQn
Definition: stm32f446xx.h:143
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
EXTI15_10_IRQn
Definition: stm32f446xx.h:136
CAN1_SCE_IRQn
Definition: stm32f446xx.h:118
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f446xx.h:102
DMA2_Stream0_IRQn
Definition: stm32f446xx.h:152
SPDIFRX_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:754
FMC_Bank3_TypeDef::PMEM
__IO uint32_t PMEM
Definition: stm32f446xx.h:455
TIM1_BRK_TIM9_IRQn
Definition: stm32f446xx.h:120
CAN2_TX_IRQn
Definition: stm32f446xx.h:157
TIM5_IRQn
Definition: stm32f446xx.h:146
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f446xx.h:105
USART3_IRQn
Definition: stm32f446xx.h:135
DCMI_IRQn
Definition: stm32f446xx.h:172
MemoryManagement_IRQn
Definition: stm32f446xx.h:88
SAI2_IRQn
Definition: stm32f446xx.h:176