STM CMSIS
stm32f469xx.h
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1 
52 #ifndef __STM32F469xx_H
53 #define __STM32F469xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
66 #define __CM4_REV 0x0001U
67 #define __MPU_PRESENT 1U
68 #define __NVIC_PRIO_BITS 4U
69 #define __Vendor_SysTickConfig 0U
70 #define __FPU_PRESENT 1U
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87  NonMaskableInt_IRQn = -14,
88  MemoryManagement_IRQn = -12,
89  BusFault_IRQn = -11,
90  UsageFault_IRQn = -10,
91  SVCall_IRQn = -5,
92  DebugMonitor_IRQn = -4,
93  PendSV_IRQn = -2,
94  SysTick_IRQn = -1,
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96  WWDG_IRQn = 0,
97  PVD_IRQn = 1,
98  TAMP_STAMP_IRQn = 2,
99  RTC_WKUP_IRQn = 3,
100  FLASH_IRQn = 4,
101  RCC_IRQn = 5,
102  EXTI0_IRQn = 6,
103  EXTI1_IRQn = 7,
104  EXTI2_IRQn = 8,
105  EXTI3_IRQn = 9,
106  EXTI4_IRQn = 10,
107  DMA1_Stream0_IRQn = 11,
108  DMA1_Stream1_IRQn = 12,
109  DMA1_Stream2_IRQn = 13,
110  DMA1_Stream3_IRQn = 14,
111  DMA1_Stream4_IRQn = 15,
112  DMA1_Stream5_IRQn = 16,
113  DMA1_Stream6_IRQn = 17,
114  ADC_IRQn = 18,
115  CAN1_TX_IRQn = 19,
116  CAN1_RX0_IRQn = 20,
117  CAN1_RX1_IRQn = 21,
118  CAN1_SCE_IRQn = 22,
119  EXTI9_5_IRQn = 23,
120  TIM1_BRK_TIM9_IRQn = 24,
121  TIM1_UP_TIM10_IRQn = 25,
122  TIM1_TRG_COM_TIM11_IRQn = 26,
123  TIM1_CC_IRQn = 27,
124  TIM2_IRQn = 28,
125  TIM3_IRQn = 29,
126  TIM4_IRQn = 30,
127  I2C1_EV_IRQn = 31,
128  I2C1_ER_IRQn = 32,
129  I2C2_EV_IRQn = 33,
130  I2C2_ER_IRQn = 34,
131  SPI1_IRQn = 35,
132  SPI2_IRQn = 36,
133  USART1_IRQn = 37,
134  USART2_IRQn = 38,
135  USART3_IRQn = 39,
136  EXTI15_10_IRQn = 40,
137  RTC_Alarm_IRQn = 41,
138  OTG_FS_WKUP_IRQn = 42,
139  TIM8_BRK_TIM12_IRQn = 43,
140  TIM8_UP_TIM13_IRQn = 44,
141  TIM8_TRG_COM_TIM14_IRQn = 45,
142  TIM8_CC_IRQn = 46,
143  DMA1_Stream7_IRQn = 47,
144  FMC_IRQn = 48,
145  SDIO_IRQn = 49,
146  TIM5_IRQn = 50,
147  SPI3_IRQn = 51,
148  UART4_IRQn = 52,
149  UART5_IRQn = 53,
150  TIM6_DAC_IRQn = 54,
151  TIM7_IRQn = 55,
152  DMA2_Stream0_IRQn = 56,
153  DMA2_Stream1_IRQn = 57,
154  DMA2_Stream2_IRQn = 58,
155  DMA2_Stream3_IRQn = 59,
156  DMA2_Stream4_IRQn = 60,
157  ETH_IRQn = 61,
158  ETH_WKUP_IRQn = 62,
159  CAN2_TX_IRQn = 63,
160  CAN2_RX0_IRQn = 64,
161  CAN2_RX1_IRQn = 65,
162  CAN2_SCE_IRQn = 66,
163  OTG_FS_IRQn = 67,
164  DMA2_Stream5_IRQn = 68,
165  DMA2_Stream6_IRQn = 69,
166  DMA2_Stream7_IRQn = 70,
167  USART6_IRQn = 71,
168  I2C3_EV_IRQn = 72,
169  I2C3_ER_IRQn = 73,
170  OTG_HS_EP1_OUT_IRQn = 74,
171  OTG_HS_EP1_IN_IRQn = 75,
172  OTG_HS_WKUP_IRQn = 76,
173  OTG_HS_IRQn = 77,
174  DCMI_IRQn = 78,
175  HASH_RNG_IRQn = 80,
176  FPU_IRQn = 81,
177  UART7_IRQn = 82,
178  UART8_IRQn = 83,
179  SPI4_IRQn = 84,
180  SPI5_IRQn = 85,
181  SPI6_IRQn = 86,
182  SAI1_IRQn = 87,
183  LTDC_IRQn = 88,
184  LTDC_ER_IRQn = 89,
185  DMA2D_IRQn = 90,
186  QUADSPI_IRQn = 91,
187  DSI_IRQn = 92
188 } IRQn_Type;
189 
194 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
195 #include "system_stm32f4xx.h"
196 #include <stdint.h>
197 
206 typedef struct
207 {
208  __IO uint32_t SR;
209  __IO uint32_t CR1;
210  __IO uint32_t CR2;
211  __IO uint32_t SMPR1;
212  __IO uint32_t SMPR2;
213  __IO uint32_t JOFR1;
214  __IO uint32_t JOFR2;
215  __IO uint32_t JOFR3;
216  __IO uint32_t JOFR4;
217  __IO uint32_t HTR;
218  __IO uint32_t LTR;
219  __IO uint32_t SQR1;
220  __IO uint32_t SQR2;
221  __IO uint32_t SQR3;
222  __IO uint32_t JSQR;
223  __IO uint32_t JDR1;
224  __IO uint32_t JDR2;
225  __IO uint32_t JDR3;
226  __IO uint32_t JDR4;
227  __IO uint32_t DR;
228 } ADC_TypeDef;
229 
230 typedef struct
231 {
232  __IO uint32_t CSR;
233  __IO uint32_t CCR;
234  __IO uint32_t CDR;
236 } ADC_Common_TypeDef;
237 
238 
243 typedef struct
244 {
245  __IO uint32_t TIR;
246  __IO uint32_t TDTR;
247  __IO uint32_t TDLR;
248  __IO uint32_t TDHR;
249 } CAN_TxMailBox_TypeDef;
250 
255 typedef struct
256 {
257  __IO uint32_t RIR;
258  __IO uint32_t RDTR;
259  __IO uint32_t RDLR;
260  __IO uint32_t RDHR;
261 } CAN_FIFOMailBox_TypeDef;
262 
267 typedef struct
268 {
269  __IO uint32_t FR1;
270  __IO uint32_t FR2;
271 } CAN_FilterRegister_TypeDef;
272 
277 typedef struct
278 {
279  __IO uint32_t MCR;
280  __IO uint32_t MSR;
281  __IO uint32_t TSR;
282  __IO uint32_t RF0R;
283  __IO uint32_t RF1R;
284  __IO uint32_t IER;
285  __IO uint32_t ESR;
286  __IO uint32_t BTR;
287  uint32_t RESERVED0[88];
288  CAN_TxMailBox_TypeDef sTxMailBox[3];
289  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
290  uint32_t RESERVED1[12];
291  __IO uint32_t FMR;
292  __IO uint32_t FM1R;
293  uint32_t RESERVED2;
294  __IO uint32_t FS1R;
295  uint32_t RESERVED3;
296  __IO uint32_t FFA1R;
297  uint32_t RESERVED4;
298  __IO uint32_t FA1R;
299  uint32_t RESERVED5[8];
300  CAN_FilterRegister_TypeDef sFilterRegister[28];
301 } CAN_TypeDef;
302 
307 typedef struct
308 {
309  __IO uint32_t DR;
310  __IO uint8_t IDR;
311  uint8_t RESERVED0;
312  uint16_t RESERVED1;
313  __IO uint32_t CR;
314 } CRC_TypeDef;
315 
320 typedef struct
321 {
322  __IO uint32_t CR;
323  __IO uint32_t SWTRIGR;
324  __IO uint32_t DHR12R1;
325  __IO uint32_t DHR12L1;
326  __IO uint32_t DHR8R1;
327  __IO uint32_t DHR12R2;
328  __IO uint32_t DHR12L2;
329  __IO uint32_t DHR8R2;
330  __IO uint32_t DHR12RD;
331  __IO uint32_t DHR12LD;
332  __IO uint32_t DHR8RD;
333  __IO uint32_t DOR1;
334  __IO uint32_t DOR2;
335  __IO uint32_t SR;
336 } DAC_TypeDef;
337 
342 typedef struct
343 {
344  __IO uint32_t IDCODE;
345  __IO uint32_t CR;
346  __IO uint32_t APB1FZ;
347  __IO uint32_t APB2FZ;
348 }DBGMCU_TypeDef;
349 
354 typedef struct
355 {
356  __IO uint32_t CR;
357  __IO uint32_t SR;
358  __IO uint32_t RISR;
359  __IO uint32_t IER;
360  __IO uint32_t MISR;
361  __IO uint32_t ICR;
362  __IO uint32_t ESCR;
363  __IO uint32_t ESUR;
364  __IO uint32_t CWSTRTR;
365  __IO uint32_t CWSIZER;
366  __IO uint32_t DR;
367 } DCMI_TypeDef;
368 
373 typedef struct
374 {
375  __IO uint32_t CR;
376  __IO uint32_t NDTR;
377  __IO uint32_t PAR;
378  __IO uint32_t M0AR;
379  __IO uint32_t M1AR;
380  __IO uint32_t FCR;
381 } DMA_Stream_TypeDef;
382 
383 typedef struct
384 {
385  __IO uint32_t LISR;
386  __IO uint32_t HISR;
387  __IO uint32_t LIFCR;
388  __IO uint32_t HIFCR;
389 } DMA_TypeDef;
390 
395 typedef struct
396 {
397  __IO uint32_t CR;
398  __IO uint32_t ISR;
399  __IO uint32_t IFCR;
400  __IO uint32_t FGMAR;
401  __IO uint32_t FGOR;
402  __IO uint32_t BGMAR;
403  __IO uint32_t BGOR;
404  __IO uint32_t FGPFCCR;
405  __IO uint32_t FGCOLR;
406  __IO uint32_t BGPFCCR;
407  __IO uint32_t BGCOLR;
408  __IO uint32_t FGCMAR;
409  __IO uint32_t BGCMAR;
410  __IO uint32_t OPFCCR;
411  __IO uint32_t OCOLR;
412  __IO uint32_t OMAR;
413  __IO uint32_t OOR;
414  __IO uint32_t NLR;
415  __IO uint32_t LWR;
416  __IO uint32_t AMTCR;
417  uint32_t RESERVED[236];
418  __IO uint32_t FGCLUT[256];
419  __IO uint32_t BGCLUT[256];
420 } DMA2D_TypeDef;
421 
426 typedef struct
427 {
428  __IO uint32_t VR;
429  __IO uint32_t CR;
430  __IO uint32_t CCR;
431  __IO uint32_t LVCIDR;
432  __IO uint32_t LCOLCR;
433  __IO uint32_t LPCR;
434  __IO uint32_t LPMCR;
435  uint32_t RESERVED0[4];
436  __IO uint32_t PCR;
437  __IO uint32_t GVCIDR;
438  __IO uint32_t MCR;
439  __IO uint32_t VMCR;
440  __IO uint32_t VPCR;
441  __IO uint32_t VCCR;
442  __IO uint32_t VNPCR;
443  __IO uint32_t VHSACR;
444  __IO uint32_t VHBPCR;
445  __IO uint32_t VLCR;
446  __IO uint32_t VVSACR;
447  __IO uint32_t VVBPCR;
448  __IO uint32_t VVFPCR;
449  __IO uint32_t VVACR;
450  __IO uint32_t LCCR;
451  __IO uint32_t CMCR;
452  __IO uint32_t GHCR;
453  __IO uint32_t GPDR;
454  __IO uint32_t GPSR;
455  __IO uint32_t TCCR[6];
456  __IO uint32_t TDCR;
457  __IO uint32_t CLCR;
458  __IO uint32_t CLTCR;
459  __IO uint32_t DLTCR;
460  __IO uint32_t PCTLR;
461  __IO uint32_t PCONFR;
462  __IO uint32_t PUCR;
463  __IO uint32_t PTTCR;
464  __IO uint32_t PSR;
465  uint32_t RESERVED1[2];
466  __IO uint32_t ISR[2];
467  __IO uint32_t IER[2];
468  uint32_t RESERVED2[3];
469  __IO uint32_t FIR[2];
470  uint32_t RESERVED3[8];
471  __IO uint32_t VSCR;
472  uint32_t RESERVED4[2];
473  __IO uint32_t LCVCIDR;
474  __IO uint32_t LCCCR;
475  uint32_t RESERVED5;
476  __IO uint32_t LPMCCR;
477  uint32_t RESERVED6[7];
478  __IO uint32_t VMCCR;
479  __IO uint32_t VPCCR;
480  __IO uint32_t VCCCR;
481  __IO uint32_t VNPCCR;
482  __IO uint32_t VHSACCR;
483  __IO uint32_t VHBPCCR;
484  __IO uint32_t VLCCR;
485  __IO uint32_t VVSACCR;
486  __IO uint32_t VVBPCCR;
487  __IO uint32_t VVFPCCR;
488  __IO uint32_t VVACCR;
489  uint32_t RESERVED7[11];
490  __IO uint32_t TDCCR;
491  uint32_t RESERVED8[155];
492  __IO uint32_t WCFGR;
493  __IO uint32_t WCR;
494  __IO uint32_t WIER;
495  __IO uint32_t WISR;
496  __IO uint32_t WIFCR;
497  uint32_t RESERVED9;
498  __IO uint32_t WPCR[5];
499  uint32_t RESERVED10;
500  __IO uint32_t WRPCR;
501 } DSI_TypeDef;
502 
507 typedef struct
508 {
509  __IO uint32_t MACCR;
510  __IO uint32_t MACFFR;
511  __IO uint32_t MACHTHR;
512  __IO uint32_t MACHTLR;
513  __IO uint32_t MACMIIAR;
514  __IO uint32_t MACMIIDR;
515  __IO uint32_t MACFCR;
516  __IO uint32_t MACVLANTR; /* 8 */
517  uint32_t RESERVED0[2];
518  __IO uint32_t MACRWUFFR; /* 11 */
519  __IO uint32_t MACPMTCSR;
520  uint32_t RESERVED1[2];
521  __IO uint32_t MACSR; /* 15 */
522  __IO uint32_t MACIMR;
523  __IO uint32_t MACA0HR;
524  __IO uint32_t MACA0LR;
525  __IO uint32_t MACA1HR;
526  __IO uint32_t MACA1LR;
527  __IO uint32_t MACA2HR;
528  __IO uint32_t MACA2LR;
529  __IO uint32_t MACA3HR;
530  __IO uint32_t MACA3LR; /* 24 */
531  uint32_t RESERVED2[40];
532  __IO uint32_t MMCCR; /* 65 */
533  __IO uint32_t MMCRIR;
534  __IO uint32_t MMCTIR;
535  __IO uint32_t MMCRIMR;
536  __IO uint32_t MMCTIMR; /* 69 */
537  uint32_t RESERVED3[14];
538  __IO uint32_t MMCTGFSCCR; /* 84 */
539  __IO uint32_t MMCTGFMSCCR;
540  uint32_t RESERVED4[5];
541  __IO uint32_t MMCTGFCR;
542  uint32_t RESERVED5[10];
543  __IO uint32_t MMCRFCECR;
544  __IO uint32_t MMCRFAECR;
545  uint32_t RESERVED6[10];
546  __IO uint32_t MMCRGUFCR;
547  uint32_t RESERVED7[334];
548  __IO uint32_t PTPTSCR;
549  __IO uint32_t PTPSSIR;
550  __IO uint32_t PTPTSHR;
551  __IO uint32_t PTPTSLR;
552  __IO uint32_t PTPTSHUR;
553  __IO uint32_t PTPTSLUR;
554  __IO uint32_t PTPTSAR;
555  __IO uint32_t PTPTTHR;
556  __IO uint32_t PTPTTLR;
557  __IO uint32_t RESERVED8;
558  __IO uint32_t PTPTSSR;
559  uint32_t RESERVED9[565];
560  __IO uint32_t DMABMR;
561  __IO uint32_t DMATPDR;
562  __IO uint32_t DMARPDR;
563  __IO uint32_t DMARDLAR;
564  __IO uint32_t DMATDLAR;
565  __IO uint32_t DMASR;
566  __IO uint32_t DMAOMR;
567  __IO uint32_t DMAIER;
568  __IO uint32_t DMAMFBOCR;
569  __IO uint32_t DMARSWTR;
570  uint32_t RESERVED10[8];
571  __IO uint32_t DMACHTDR;
572  __IO uint32_t DMACHRDR;
573  __IO uint32_t DMACHTBAR;
574  __IO uint32_t DMACHRBAR;
575 } ETH_TypeDef;
576 
581 typedef struct
582 {
583  __IO uint32_t IMR;
584  __IO uint32_t EMR;
585  __IO uint32_t RTSR;
586  __IO uint32_t FTSR;
587  __IO uint32_t SWIER;
588  __IO uint32_t PR;
589 } EXTI_TypeDef;
590 
595 typedef struct
596 {
597  __IO uint32_t ACR;
598  __IO uint32_t KEYR;
599  __IO uint32_t OPTKEYR;
600  __IO uint32_t SR;
601  __IO uint32_t CR;
602  __IO uint32_t OPTCR;
603  __IO uint32_t OPTCR1;
604 } FLASH_TypeDef;
605 
610 typedef struct
611 {
612  __IO uint32_t BTCR[8];
613 } FMC_Bank1_TypeDef;
614 
619 typedef struct
620 {
621  __IO uint32_t BWTR[7];
622 } FMC_Bank1E_TypeDef;
623 
628 typedef struct
629 {
630  __IO uint32_t PCR;
631  __IO uint32_t SR;
632  __IO uint32_t PMEM;
633  __IO uint32_t PATT;
634  uint32_t RESERVED;
635  __IO uint32_t ECCR;
636 } FMC_Bank3_TypeDef;
637 
642 typedef struct
643 {
644  __IO uint32_t SDCR[2];
645  __IO uint32_t SDTR[2];
646  __IO uint32_t SDCMR;
647  __IO uint32_t SDRTR;
648  __IO uint32_t SDSR;
649 } FMC_Bank5_6_TypeDef;
650 
655 typedef struct
656 {
657  __IO uint32_t MODER;
658  __IO uint32_t OTYPER;
659  __IO uint32_t OSPEEDR;
660  __IO uint32_t PUPDR;
661  __IO uint32_t IDR;
662  __IO uint32_t ODR;
663  __IO uint32_t BSRR;
664  __IO uint32_t LCKR;
665  __IO uint32_t AFR[2];
666 } GPIO_TypeDef;
667 
672 typedef struct
673 {
674  __IO uint32_t MEMRMP;
675  __IO uint32_t PMC;
676  __IO uint32_t EXTICR[4];
677  uint32_t RESERVED[2];
678  __IO uint32_t CMPCR;
679 } SYSCFG_TypeDef;
680 
685 typedef struct
686 {
687  __IO uint32_t CR1;
688  __IO uint32_t CR2;
689  __IO uint32_t OAR1;
690  __IO uint32_t OAR2;
691  __IO uint32_t DR;
692  __IO uint32_t SR1;
693  __IO uint32_t SR2;
694  __IO uint32_t CCR;
695  __IO uint32_t TRISE;
696  __IO uint32_t FLTR;
697 } I2C_TypeDef;
698 
703 typedef struct
704 {
705  __IO uint32_t KR;
706  __IO uint32_t PR;
707  __IO uint32_t RLR;
708  __IO uint32_t SR;
709 } IWDG_TypeDef;
710 
715 typedef struct
716 {
717  uint32_t RESERVED0[2];
718  __IO uint32_t SSCR;
719  __IO uint32_t BPCR;
720  __IO uint32_t AWCR;
721  __IO uint32_t TWCR;
722  __IO uint32_t GCR;
723  uint32_t RESERVED1[2];
724  __IO uint32_t SRCR;
725  uint32_t RESERVED2[1];
726  __IO uint32_t BCCR;
727  uint32_t RESERVED3[1];
728  __IO uint32_t IER;
729  __IO uint32_t ISR;
730  __IO uint32_t ICR;
731  __IO uint32_t LIPCR;
732  __IO uint32_t CPSR;
733  __IO uint32_t CDSR;
734 } LTDC_TypeDef;
735 
740 typedef struct
741 {
742  __IO uint32_t CR;
743  __IO uint32_t WHPCR;
744  __IO uint32_t WVPCR;
745  __IO uint32_t CKCR;
746  __IO uint32_t PFCR;
747  __IO uint32_t CACR;
748  __IO uint32_t DCCR;
749  __IO uint32_t BFCR;
750  uint32_t RESERVED0[2];
751  __IO uint32_t CFBAR;
752  __IO uint32_t CFBLR;
753  __IO uint32_t CFBLNR;
754  uint32_t RESERVED1[3];
755  __IO uint32_t CLUTWR;
757 } LTDC_Layer_TypeDef;
758 
763 typedef struct
764 {
765  __IO uint32_t CR;
766  __IO uint32_t CSR;
767 } PWR_TypeDef;
768 
773 typedef struct
774 {
775  __IO uint32_t CR;
776  __IO uint32_t PLLCFGR;
777  __IO uint32_t CFGR;
778  __IO uint32_t CIR;
779  __IO uint32_t AHB1RSTR;
780  __IO uint32_t AHB2RSTR;
781  __IO uint32_t AHB3RSTR;
782  uint32_t RESERVED0;
783  __IO uint32_t APB1RSTR;
784  __IO uint32_t APB2RSTR;
785  uint32_t RESERVED1[2];
786  __IO uint32_t AHB1ENR;
787  __IO uint32_t AHB2ENR;
788  __IO uint32_t AHB3ENR;
789  uint32_t RESERVED2;
790  __IO uint32_t APB1ENR;
791  __IO uint32_t APB2ENR;
792  uint32_t RESERVED3[2];
793  __IO uint32_t AHB1LPENR;
794  __IO uint32_t AHB2LPENR;
795  __IO uint32_t AHB3LPENR;
796  uint32_t RESERVED4;
797  __IO uint32_t APB1LPENR;
798  __IO uint32_t APB2LPENR;
799  uint32_t RESERVED5[2];
800  __IO uint32_t BDCR;
801  __IO uint32_t CSR;
802  uint32_t RESERVED6[2];
803  __IO uint32_t SSCGR;
804  __IO uint32_t PLLI2SCFGR;
805  __IO uint32_t PLLSAICFGR;
806  __IO uint32_t DCKCFGR;
808 } RCC_TypeDef;
809 
814 typedef struct
815 {
816  __IO uint32_t TR;
817  __IO uint32_t DR;
818  __IO uint32_t CR;
819  __IO uint32_t ISR;
820  __IO uint32_t PRER;
821  __IO uint32_t WUTR;
822  __IO uint32_t CALIBR;
823  __IO uint32_t ALRMAR;
824  __IO uint32_t ALRMBR;
825  __IO uint32_t WPR;
826  __IO uint32_t SSR;
827  __IO uint32_t SHIFTR;
828  __IO uint32_t TSTR;
829  __IO uint32_t TSDR;
830  __IO uint32_t TSSSR;
831  __IO uint32_t CALR;
832  __IO uint32_t TAFCR;
833  __IO uint32_t ALRMASSR;
834  __IO uint32_t ALRMBSSR;
835  uint32_t RESERVED7;
836  __IO uint32_t BKP0R;
837  __IO uint32_t BKP1R;
838  __IO uint32_t BKP2R;
839  __IO uint32_t BKP3R;
840  __IO uint32_t BKP4R;
841  __IO uint32_t BKP5R;
842  __IO uint32_t BKP6R;
843  __IO uint32_t BKP7R;
844  __IO uint32_t BKP8R;
845  __IO uint32_t BKP9R;
846  __IO uint32_t BKP10R;
847  __IO uint32_t BKP11R;
848  __IO uint32_t BKP12R;
849  __IO uint32_t BKP13R;
850  __IO uint32_t BKP14R;
851  __IO uint32_t BKP15R;
852  __IO uint32_t BKP16R;
853  __IO uint32_t BKP17R;
854  __IO uint32_t BKP18R;
855  __IO uint32_t BKP19R;
856 } RTC_TypeDef;
857 
862 typedef struct
863 {
864  __IO uint32_t GCR;
865 } SAI_TypeDef;
866 
867 typedef struct
868 {
869  __IO uint32_t CR1;
870  __IO uint32_t CR2;
871  __IO uint32_t FRCR;
872  __IO uint32_t SLOTR;
873  __IO uint32_t IMR;
874  __IO uint32_t SR;
875  __IO uint32_t CLRFR;
876  __IO uint32_t DR;
877 } SAI_Block_TypeDef;
878 
883 typedef struct
884 {
885  __IO uint32_t POWER;
886  __IO uint32_t CLKCR;
887  __IO uint32_t ARG;
888  __IO uint32_t CMD;
889  __I uint32_t RESPCMD;
890  __I uint32_t RESP1;
891  __I uint32_t RESP2;
892  __I uint32_t RESP3;
893  __I uint32_t RESP4;
894  __IO uint32_t DTIMER;
895  __IO uint32_t DLEN;
896  __IO uint32_t DCTRL;
897  __I uint32_t DCOUNT;
898  __I uint32_t STA;
899  __IO uint32_t ICR;
900  __IO uint32_t MASK;
901  uint32_t RESERVED0[2];
902  __I uint32_t FIFOCNT;
903  uint32_t RESERVED1[13];
904  __IO uint32_t FIFO;
905 } SDIO_TypeDef;
906 
911 typedef struct
912 {
913  __IO uint32_t CR1;
914  __IO uint32_t CR2;
915  __IO uint32_t SR;
916  __IO uint32_t DR;
917  __IO uint32_t CRCPR;
918  __IO uint32_t RXCRCR;
919  __IO uint32_t TXCRCR;
920  __IO uint32_t I2SCFGR;
921  __IO uint32_t I2SPR;
922 } SPI_TypeDef;
923 
928 typedef struct
929 {
930  __IO uint32_t CR;
931  __IO uint32_t DCR;
932  __IO uint32_t SR;
933  __IO uint32_t FCR;
934  __IO uint32_t DLR;
935  __IO uint32_t CCR;
936  __IO uint32_t AR;
937  __IO uint32_t ABR;
938  __IO uint32_t DR;
939  __IO uint32_t PSMKR;
940  __IO uint32_t PSMAR;
941  __IO uint32_t PIR;
942  __IO uint32_t LPTR;
943 } QUADSPI_TypeDef;
944 
949 typedef struct
950 {
951  __IO uint32_t CR1;
952  __IO uint32_t CR2;
953  __IO uint32_t SMCR;
954  __IO uint32_t DIER;
955  __IO uint32_t SR;
956  __IO uint32_t EGR;
957  __IO uint32_t CCMR1;
958  __IO uint32_t CCMR2;
959  __IO uint32_t CCER;
960  __IO uint32_t CNT;
961  __IO uint32_t PSC;
962  __IO uint32_t ARR;
963  __IO uint32_t RCR;
964  __IO uint32_t CCR1;
965  __IO uint32_t CCR2;
966  __IO uint32_t CCR3;
967  __IO uint32_t CCR4;
968  __IO uint32_t BDTR;
969  __IO uint32_t DCR;
970  __IO uint32_t DMAR;
971  __IO uint32_t OR;
972 } TIM_TypeDef;
973 
978 typedef struct
979 {
980  __IO uint32_t SR;
981  __IO uint32_t DR;
982  __IO uint32_t BRR;
983  __IO uint32_t CR1;
984  __IO uint32_t CR2;
985  __IO uint32_t CR3;
986  __IO uint32_t GTPR;
987 } USART_TypeDef;
988 
993 typedef struct
994 {
995  __IO uint32_t CR;
996  __IO uint32_t CFR;
997  __IO uint32_t SR;
998 } WWDG_TypeDef;
999 
1004 typedef struct
1005 {
1006  __IO uint32_t CR;
1007  __IO uint32_t SR;
1008  __IO uint32_t DR;
1009 } RNG_TypeDef;
1010 
1011 
1015 typedef struct
1016 {
1017  __IO uint32_t GOTGCTL;
1018  __IO uint32_t GOTGINT;
1019  __IO uint32_t GAHBCFG;
1020  __IO uint32_t GUSBCFG;
1021  __IO uint32_t GRSTCTL;
1022  __IO uint32_t GINTSTS;
1023  __IO uint32_t GINTMSK;
1024  __IO uint32_t GRXSTSR;
1025  __IO uint32_t GRXSTSP;
1026  __IO uint32_t GRXFSIZ;
1027  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1028  __IO uint32_t HNPTXSTS;
1029  uint32_t Reserved30[2];
1030  __IO uint32_t GCCFG;
1031  __IO uint32_t CID;
1032  uint32_t Reserved5[3];
1033  __IO uint32_t GHWCFG3;
1034  uint32_t Reserved6;
1035  __IO uint32_t GLPMCFG;
1036  uint32_t Reserved;
1037  __IO uint32_t GDFIFOCFG;
1038  uint32_t Reserved43[40];
1039  __IO uint32_t HPTXFSIZ;
1040  __IO uint32_t DIEPTXF[0x0F];
1041 } USB_OTG_GlobalTypeDef;
1042 
1046 typedef struct
1047 {
1048  __IO uint32_t DCFG;
1049  __IO uint32_t DCTL;
1050  __IO uint32_t DSTS;
1051  uint32_t Reserved0C;
1052  __IO uint32_t DIEPMSK;
1053  __IO uint32_t DOEPMSK;
1054  __IO uint32_t DAINT;
1055  __IO uint32_t DAINTMSK;
1056  uint32_t Reserved20;
1057  uint32_t Reserved9;
1058  __IO uint32_t DVBUSDIS;
1059  __IO uint32_t DVBUSPULSE;
1060  __IO uint32_t DTHRCTL;
1061  __IO uint32_t DIEPEMPMSK;
1062  __IO uint32_t DEACHINT;
1063  __IO uint32_t DEACHMSK;
1064  uint32_t Reserved40;
1065  __IO uint32_t DINEP1MSK;
1066  uint32_t Reserved44[15];
1067  __IO uint32_t DOUTEP1MSK;
1068 } USB_OTG_DeviceTypeDef;
1069 
1073 typedef struct
1074 {
1075  __IO uint32_t DIEPCTL;
1076  uint32_t Reserved04;
1077  __IO uint32_t DIEPINT;
1078  uint32_t Reserved0C;
1079  __IO uint32_t DIEPTSIZ;
1080  __IO uint32_t DIEPDMA;
1081  __IO uint32_t DTXFSTS;
1082  uint32_t Reserved18;
1083 } USB_OTG_INEndpointTypeDef;
1084 
1088 typedef struct
1089 {
1090  __IO uint32_t DOEPCTL;
1091  uint32_t Reserved04;
1092  __IO uint32_t DOEPINT;
1093  uint32_t Reserved0C;
1094  __IO uint32_t DOEPTSIZ;
1095  __IO uint32_t DOEPDMA;
1096  uint32_t Reserved18[2];
1097 } USB_OTG_OUTEndpointTypeDef;
1098 
1102 typedef struct
1103 {
1104  __IO uint32_t HCFG;
1105  __IO uint32_t HFIR;
1106  __IO uint32_t HFNUM;
1107  uint32_t Reserved40C;
1108  __IO uint32_t HPTXSTS;
1109  __IO uint32_t HAINT;
1110  __IO uint32_t HAINTMSK;
1111 } USB_OTG_HostTypeDef;
1112 
1116 typedef struct
1117 {
1118  __IO uint32_t HCCHAR;
1119  __IO uint32_t HCSPLT;
1120  __IO uint32_t HCINT;
1121  __IO uint32_t HCINTMSK;
1122  __IO uint32_t HCTSIZ;
1123  __IO uint32_t HCDMA;
1124  uint32_t Reserved[2];
1125 } USB_OTG_HostChannelTypeDef;
1126 
1134 #define FLASH_BASE 0x08000000U
1135 #define CCMDATARAM_BASE 0x10000000U
1136 #define SRAM1_BASE 0x20000000U
1137 #define SRAM2_BASE 0x20028000U
1138 #define SRAM3_BASE 0x20030000U
1139 #define PERIPH_BASE 0x40000000U
1140 #define BKPSRAM_BASE 0x40024000U
1141 #define FMC_R_BASE 0xA0000000U
1142 #define QSPI_R_BASE 0xA0001000U
1143 #define SRAM1_BB_BASE 0x22000000U
1144 #define SRAM2_BB_BASE 0x22500000U
1145 #define SRAM3_BB_BASE 0x22600000U
1146 #define PERIPH_BB_BASE 0x42000000U
1147 #define BKPSRAM_BB_BASE 0x42480000U
1148 #define FLASH_END 0x081FFFFFU
1149 #define CCMDATARAM_END 0x1000FFFFU
1151 /* Legacy defines */
1152 #define SRAM_BASE SRAM1_BASE
1153 #define SRAM_BB_BASE SRAM1_BB_BASE
1154 
1155 
1157 #define APB1PERIPH_BASE PERIPH_BASE
1158 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1159 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1160 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1161 
1163 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1164 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1165 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1166 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1167 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1168 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1169 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1170 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1171 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1172 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1173 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1174 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1175 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1176 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1177 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1178 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1179 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1180 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1181 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1182 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1183 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1184 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1185 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1186 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1187 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1188 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1189 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1190 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1191 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1192 
1194 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1195 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1196 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1197 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1198 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1199 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1200 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1201 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1202 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1203 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1204 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1205 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1206 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1207 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1208 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1209 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1210 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1211 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1212 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1213 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1214 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1215 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1216 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1217 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1218 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
1219 
1221 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1222 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1223 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1224 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1225 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1226 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1227 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1228 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1229 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1230 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1231 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1232 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1233 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1234 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1235 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1236 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1237 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1238 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1239 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1240 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1241 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1242 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1243 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1244 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1245 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1246 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1247 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1248 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1249 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1250 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1251 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1252 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1253 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1254 #define ETH_MAC_BASE (ETH_BASE)
1255 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1256 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1257 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1258 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1259 
1261 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1262 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1263 
1265 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1266 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1267 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1268 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1269 
1271 #define DBGMCU_BASE 0xE0042000U
1272 
1274 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1275 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1276 
1277 #define USB_OTG_GLOBAL_BASE 0x000U
1278 #define USB_OTG_DEVICE_BASE 0x800U
1279 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1280 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1281 #define USB_OTG_EP_REG_SIZE 0x20U
1282 #define USB_OTG_HOST_BASE 0x400U
1283 #define USB_OTG_HOST_PORT_BASE 0x440U
1284 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1285 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1286 #define USB_OTG_PCGCCTL_BASE 0xE00U
1287 #define USB_OTG_FIFO_BASE 0x1000U
1288 #define USB_OTG_FIFO_SIZE 0x1000U
1289 
1297 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1298 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1299 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1300 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1301 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1302 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1303 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1304 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1305 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1306 #define RTC ((RTC_TypeDef *) RTC_BASE)
1307 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1308 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1309 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1310 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1311 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1312 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1313 #define USART2 ((USART_TypeDef *) USART2_BASE)
1314 #define USART3 ((USART_TypeDef *) USART3_BASE)
1315 #define UART4 ((USART_TypeDef *) UART4_BASE)
1316 #define UART5 ((USART_TypeDef *) UART5_BASE)
1317 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1318 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1319 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1320 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1321 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1322 #define PWR ((PWR_TypeDef *) PWR_BASE)
1323 #define DAC ((DAC_TypeDef *) DAC_BASE)
1324 #define UART7 ((USART_TypeDef *) UART7_BASE)
1325 #define UART8 ((USART_TypeDef *) UART8_BASE)
1326 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1327 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1328 #define USART1 ((USART_TypeDef *) USART1_BASE)
1329 #define USART6 ((USART_TypeDef *) USART6_BASE)
1330 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1331 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1332 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1333 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1334 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1335 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1336 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1337 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1338 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1339 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1340 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1341 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1342 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1343 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1344 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1345 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1346 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1347 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1348 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1349 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1350 #define DSI ((DSI_TypeDef *)DSI_BASE)
1351 
1352 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1353 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1354 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1355 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1356 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1357 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1358 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1359 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1360 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1361 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1362 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1363 #define CRC ((CRC_TypeDef *) CRC_BASE)
1364 #define RCC ((RCC_TypeDef *) RCC_BASE)
1365 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1366 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1367 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1368 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1369 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1370 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1371 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1372 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1373 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1374 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1375 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1376 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1377 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1378 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1379 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1380 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1381 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1382 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1383 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1384 #define ETH ((ETH_TypeDef *) ETH_BASE)
1385 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1386 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1387 #define RNG ((RNG_TypeDef *) RNG_BASE)
1388 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1389 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1390 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1391 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1392 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1393 
1394 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1395 
1396 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1397 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1398 
1411 /******************************************************************************/
1412 /* Peripheral Registers_Bits_Definition */
1413 /******************************************************************************/
1414 
1415 /******************************************************************************/
1416 /* */
1417 /* Analog to Digital Converter */
1418 /* */
1419 /******************************************************************************/
1420 /******************** Bit definition for ADC_SR register ********************/
1421 #define ADC_SR_AWD 0x00000001U
1422 #define ADC_SR_EOC 0x00000002U
1423 #define ADC_SR_JEOC 0x00000004U
1424 #define ADC_SR_JSTRT 0x00000008U
1425 #define ADC_SR_STRT 0x00000010U
1426 #define ADC_SR_OVR 0x00000020U
1428 /******************* Bit definition for ADC_CR1 register ********************/
1429 #define ADC_CR1_AWDCH 0x0000001FU
1430 #define ADC_CR1_AWDCH_0 0x00000001U
1431 #define ADC_CR1_AWDCH_1 0x00000002U
1432 #define ADC_CR1_AWDCH_2 0x00000004U
1433 #define ADC_CR1_AWDCH_3 0x00000008U
1434 #define ADC_CR1_AWDCH_4 0x00000010U
1435 #define ADC_CR1_EOCIE 0x00000020U
1436 #define ADC_CR1_AWDIE 0x00000040U
1437 #define ADC_CR1_JEOCIE 0x00000080U
1438 #define ADC_CR1_SCAN 0x00000100U
1439 #define ADC_CR1_AWDSGL 0x00000200U
1440 #define ADC_CR1_JAUTO 0x00000400U
1441 #define ADC_CR1_DISCEN 0x00000800U
1442 #define ADC_CR1_JDISCEN 0x00001000U
1443 #define ADC_CR1_DISCNUM 0x0000E000U
1444 #define ADC_CR1_DISCNUM_0 0x00002000U
1445 #define ADC_CR1_DISCNUM_1 0x00004000U
1446 #define ADC_CR1_DISCNUM_2 0x00008000U
1447 #define ADC_CR1_JAWDEN 0x00400000U
1448 #define ADC_CR1_AWDEN 0x00800000U
1449 #define ADC_CR1_RES 0x03000000U
1450 #define ADC_CR1_RES_0 0x01000000U
1451 #define ADC_CR1_RES_1 0x02000000U
1452 #define ADC_CR1_OVRIE 0x04000000U
1454 /******************* Bit definition for ADC_CR2 register ********************/
1455 #define ADC_CR2_ADON 0x00000001U
1456 #define ADC_CR2_CONT 0x00000002U
1457 #define ADC_CR2_DMA 0x00000100U
1458 #define ADC_CR2_DDS 0x00000200U
1459 #define ADC_CR2_EOCS 0x00000400U
1460 #define ADC_CR2_ALIGN 0x00000800U
1461 #define ADC_CR2_JEXTSEL 0x000F0000U
1462 #define ADC_CR2_JEXTSEL_0 0x00010000U
1463 #define ADC_CR2_JEXTSEL_1 0x00020000U
1464 #define ADC_CR2_JEXTSEL_2 0x00040000U
1465 #define ADC_CR2_JEXTSEL_3 0x00080000U
1466 #define ADC_CR2_JEXTEN 0x00300000U
1467 #define ADC_CR2_JEXTEN_0 0x00100000U
1468 #define ADC_CR2_JEXTEN_1 0x00200000U
1469 #define ADC_CR2_JSWSTART 0x00400000U
1470 #define ADC_CR2_EXTSEL 0x0F000000U
1471 #define ADC_CR2_EXTSEL_0 0x01000000U
1472 #define ADC_CR2_EXTSEL_1 0x02000000U
1473 #define ADC_CR2_EXTSEL_2 0x04000000U
1474 #define ADC_CR2_EXTSEL_3 0x08000000U
1475 #define ADC_CR2_EXTEN 0x30000000U
1476 #define ADC_CR2_EXTEN_0 0x10000000U
1477 #define ADC_CR2_EXTEN_1 0x20000000U
1478 #define ADC_CR2_SWSTART 0x40000000U
1480 /****************** Bit definition for ADC_SMPR1 register *******************/
1481 #define ADC_SMPR1_SMP10 0x00000007U
1482 #define ADC_SMPR1_SMP10_0 0x00000001U
1483 #define ADC_SMPR1_SMP10_1 0x00000002U
1484 #define ADC_SMPR1_SMP10_2 0x00000004U
1485 #define ADC_SMPR1_SMP11 0x00000038U
1486 #define ADC_SMPR1_SMP11_0 0x00000008U
1487 #define ADC_SMPR1_SMP11_1 0x00000010U
1488 #define ADC_SMPR1_SMP11_2 0x00000020U
1489 #define ADC_SMPR1_SMP12 0x000001C0U
1490 #define ADC_SMPR1_SMP12_0 0x00000040U
1491 #define ADC_SMPR1_SMP12_1 0x00000080U
1492 #define ADC_SMPR1_SMP12_2 0x00000100U
1493 #define ADC_SMPR1_SMP13 0x00000E00U
1494 #define ADC_SMPR1_SMP13_0 0x00000200U
1495 #define ADC_SMPR1_SMP13_1 0x00000400U
1496 #define ADC_SMPR1_SMP13_2 0x00000800U
1497 #define ADC_SMPR1_SMP14 0x00007000U
1498 #define ADC_SMPR1_SMP14_0 0x00001000U
1499 #define ADC_SMPR1_SMP14_1 0x00002000U
1500 #define ADC_SMPR1_SMP14_2 0x00004000U
1501 #define ADC_SMPR1_SMP15 0x00038000U
1502 #define ADC_SMPR1_SMP15_0 0x00008000U
1503 #define ADC_SMPR1_SMP15_1 0x00010000U
1504 #define ADC_SMPR1_SMP15_2 0x00020000U
1505 #define ADC_SMPR1_SMP16 0x001C0000U
1506 #define ADC_SMPR1_SMP16_0 0x00040000U
1507 #define ADC_SMPR1_SMP16_1 0x00080000U
1508 #define ADC_SMPR1_SMP16_2 0x00100000U
1509 #define ADC_SMPR1_SMP17 0x00E00000U
1510 #define ADC_SMPR1_SMP17_0 0x00200000U
1511 #define ADC_SMPR1_SMP17_1 0x00400000U
1512 #define ADC_SMPR1_SMP17_2 0x00800000U
1513 #define ADC_SMPR1_SMP18 0x07000000U
1514 #define ADC_SMPR1_SMP18_0 0x01000000U
1515 #define ADC_SMPR1_SMP18_1 0x02000000U
1516 #define ADC_SMPR1_SMP18_2 0x04000000U
1518 /****************** Bit definition for ADC_SMPR2 register *******************/
1519 #define ADC_SMPR2_SMP0 0x00000007U
1520 #define ADC_SMPR2_SMP0_0 0x00000001U
1521 #define ADC_SMPR2_SMP0_1 0x00000002U
1522 #define ADC_SMPR2_SMP0_2 0x00000004U
1523 #define ADC_SMPR2_SMP1 0x00000038U
1524 #define ADC_SMPR2_SMP1_0 0x00000008U
1525 #define ADC_SMPR2_SMP1_1 0x00000010U
1526 #define ADC_SMPR2_SMP1_2 0x00000020U
1527 #define ADC_SMPR2_SMP2 0x000001C0U
1528 #define ADC_SMPR2_SMP2_0 0x00000040U
1529 #define ADC_SMPR2_SMP2_1 0x00000080U
1530 #define ADC_SMPR2_SMP2_2 0x00000100U
1531 #define ADC_SMPR2_SMP3 0x00000E00U
1532 #define ADC_SMPR2_SMP3_0 0x00000200U
1533 #define ADC_SMPR2_SMP3_1 0x00000400U
1534 #define ADC_SMPR2_SMP3_2 0x00000800U
1535 #define ADC_SMPR2_SMP4 0x00007000U
1536 #define ADC_SMPR2_SMP4_0 0x00001000U
1537 #define ADC_SMPR2_SMP4_1 0x00002000U
1538 #define ADC_SMPR2_SMP4_2 0x00004000U
1539 #define ADC_SMPR2_SMP5 0x00038000U
1540 #define ADC_SMPR2_SMP5_0 0x00008000U
1541 #define ADC_SMPR2_SMP5_1 0x00010000U
1542 #define ADC_SMPR2_SMP5_2 0x00020000U
1543 #define ADC_SMPR2_SMP6 0x001C0000U
1544 #define ADC_SMPR2_SMP6_0 0x00040000U
1545 #define ADC_SMPR2_SMP6_1 0x00080000U
1546 #define ADC_SMPR2_SMP6_2 0x00100000U
1547 #define ADC_SMPR2_SMP7 0x00E00000U
1548 #define ADC_SMPR2_SMP7_0 0x00200000U
1549 #define ADC_SMPR2_SMP7_1 0x00400000U
1550 #define ADC_SMPR2_SMP7_2 0x00800000U
1551 #define ADC_SMPR2_SMP8 0x07000000U
1552 #define ADC_SMPR2_SMP8_0 0x01000000U
1553 #define ADC_SMPR2_SMP8_1 0x02000000U
1554 #define ADC_SMPR2_SMP8_2 0x04000000U
1555 #define ADC_SMPR2_SMP9 0x38000000U
1556 #define ADC_SMPR2_SMP9_0 0x08000000U
1557 #define ADC_SMPR2_SMP9_1 0x10000000U
1558 #define ADC_SMPR2_SMP9_2 0x20000000U
1560 /****************** Bit definition for ADC_JOFR1 register *******************/
1561 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1563 /****************** Bit definition for ADC_JOFR2 register *******************/
1564 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1566 /****************** Bit definition for ADC_JOFR3 register *******************/
1567 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1569 /****************** Bit definition for ADC_JOFR4 register *******************/
1570 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1572 /******************* Bit definition for ADC_HTR register ********************/
1573 #define ADC_HTR_HT 0x0FFFU
1575 /******************* Bit definition for ADC_LTR register ********************/
1576 #define ADC_LTR_LT 0x0FFFU
1578 /******************* Bit definition for ADC_SQR1 register *******************/
1579 #define ADC_SQR1_SQ13 0x0000001FU
1580 #define ADC_SQR1_SQ13_0 0x00000001U
1581 #define ADC_SQR1_SQ13_1 0x00000002U
1582 #define ADC_SQR1_SQ13_2 0x00000004U
1583 #define ADC_SQR1_SQ13_3 0x00000008U
1584 #define ADC_SQR1_SQ13_4 0x00000010U
1585 #define ADC_SQR1_SQ14 0x000003E0U
1586 #define ADC_SQR1_SQ14_0 0x00000020U
1587 #define ADC_SQR1_SQ14_1 0x00000040U
1588 #define ADC_SQR1_SQ14_2 0x00000080U
1589 #define ADC_SQR1_SQ14_3 0x00000100U
1590 #define ADC_SQR1_SQ14_4 0x00000200U
1591 #define ADC_SQR1_SQ15 0x00007C00U
1592 #define ADC_SQR1_SQ15_0 0x00000400U
1593 #define ADC_SQR1_SQ15_1 0x00000800U
1594 #define ADC_SQR1_SQ15_2 0x00001000U
1595 #define ADC_SQR1_SQ15_3 0x00002000U
1596 #define ADC_SQR1_SQ15_4 0x00004000U
1597 #define ADC_SQR1_SQ16 0x000F8000U
1598 #define ADC_SQR1_SQ16_0 0x00008000U
1599 #define ADC_SQR1_SQ16_1 0x00010000U
1600 #define ADC_SQR1_SQ16_2 0x00020000U
1601 #define ADC_SQR1_SQ16_3 0x00040000U
1602 #define ADC_SQR1_SQ16_4 0x00080000U
1603 #define ADC_SQR1_L 0x00F00000U
1604 #define ADC_SQR1_L_0 0x00100000U
1605 #define ADC_SQR1_L_1 0x00200000U
1606 #define ADC_SQR1_L_2 0x00400000U
1607 #define ADC_SQR1_L_3 0x00800000U
1609 /******************* Bit definition for ADC_SQR2 register *******************/
1610 #define ADC_SQR2_SQ7 0x0000001FU
1611 #define ADC_SQR2_SQ7_0 0x00000001U
1612 #define ADC_SQR2_SQ7_1 0x00000002U
1613 #define ADC_SQR2_SQ7_2 0x00000004U
1614 #define ADC_SQR2_SQ7_3 0x00000008U
1615 #define ADC_SQR2_SQ7_4 0x00000010U
1616 #define ADC_SQR2_SQ8 0x000003E0U
1617 #define ADC_SQR2_SQ8_0 0x00000020U
1618 #define ADC_SQR2_SQ8_1 0x00000040U
1619 #define ADC_SQR2_SQ8_2 0x00000080U
1620 #define ADC_SQR2_SQ8_3 0x00000100U
1621 #define ADC_SQR2_SQ8_4 0x00000200U
1622 #define ADC_SQR2_SQ9 0x00007C00U
1623 #define ADC_SQR2_SQ9_0 0x00000400U
1624 #define ADC_SQR2_SQ9_1 0x00000800U
1625 #define ADC_SQR2_SQ9_2 0x00001000U
1626 #define ADC_SQR2_SQ9_3 0x00002000U
1627 #define ADC_SQR2_SQ9_4 0x00004000U
1628 #define ADC_SQR2_SQ10 0x000F8000U
1629 #define ADC_SQR2_SQ10_0 0x00008000U
1630 #define ADC_SQR2_SQ10_1 0x00010000U
1631 #define ADC_SQR2_SQ10_2 0x00020000U
1632 #define ADC_SQR2_SQ10_3 0x00040000U
1633 #define ADC_SQR2_SQ10_4 0x00080000U
1634 #define ADC_SQR2_SQ11 0x01F00000U
1635 #define ADC_SQR2_SQ11_0 0x00100000U
1636 #define ADC_SQR2_SQ11_1 0x00200000U
1637 #define ADC_SQR2_SQ11_2 0x00400000U
1638 #define ADC_SQR2_SQ11_3 0x00800000U
1639 #define ADC_SQR2_SQ11_4 0x01000000U
1640 #define ADC_SQR2_SQ12 0x3E000000U
1641 #define ADC_SQR2_SQ12_0 0x02000000U
1642 #define ADC_SQR2_SQ12_1 0x04000000U
1643 #define ADC_SQR2_SQ12_2 0x08000000U
1644 #define ADC_SQR2_SQ12_3 0x10000000U
1645 #define ADC_SQR2_SQ12_4 0x20000000U
1647 /******************* Bit definition for ADC_SQR3 register *******************/
1648 #define ADC_SQR3_SQ1 0x0000001FU
1649 #define ADC_SQR3_SQ1_0 0x00000001U
1650 #define ADC_SQR3_SQ1_1 0x00000002U
1651 #define ADC_SQR3_SQ1_2 0x00000004U
1652 #define ADC_SQR3_SQ1_3 0x00000008U
1653 #define ADC_SQR3_SQ1_4 0x00000010U
1654 #define ADC_SQR3_SQ2 0x000003E0U
1655 #define ADC_SQR3_SQ2_0 0x00000020U
1656 #define ADC_SQR3_SQ2_1 0x00000040U
1657 #define ADC_SQR3_SQ2_2 0x00000080U
1658 #define ADC_SQR3_SQ2_3 0x00000100U
1659 #define ADC_SQR3_SQ2_4 0x00000200U
1660 #define ADC_SQR3_SQ3 0x00007C00U
1661 #define ADC_SQR3_SQ3_0 0x00000400U
1662 #define ADC_SQR3_SQ3_1 0x00000800U
1663 #define ADC_SQR3_SQ3_2 0x00001000U
1664 #define ADC_SQR3_SQ3_3 0x00002000U
1665 #define ADC_SQR3_SQ3_4 0x00004000U
1666 #define ADC_SQR3_SQ4 0x000F8000U
1667 #define ADC_SQR3_SQ4_0 0x00008000U
1668 #define ADC_SQR3_SQ4_1 0x00010000U
1669 #define ADC_SQR3_SQ4_2 0x00020000U
1670 #define ADC_SQR3_SQ4_3 0x00040000U
1671 #define ADC_SQR3_SQ4_4 0x00080000U
1672 #define ADC_SQR3_SQ5 0x01F00000U
1673 #define ADC_SQR3_SQ5_0 0x00100000U
1674 #define ADC_SQR3_SQ5_1 0x00200000U
1675 #define ADC_SQR3_SQ5_2 0x00400000U
1676 #define ADC_SQR3_SQ5_3 0x00800000U
1677 #define ADC_SQR3_SQ5_4 0x01000000U
1678 #define ADC_SQR3_SQ6 0x3E000000U
1679 #define ADC_SQR3_SQ6_0 0x02000000U
1680 #define ADC_SQR3_SQ6_1 0x04000000U
1681 #define ADC_SQR3_SQ6_2 0x08000000U
1682 #define ADC_SQR3_SQ6_3 0x10000000U
1683 #define ADC_SQR3_SQ6_4 0x20000000U
1685 /******************* Bit definition for ADC_JSQR register *******************/
1686 #define ADC_JSQR_JSQ1 0x0000001FU
1687 #define ADC_JSQR_JSQ1_0 0x00000001U
1688 #define ADC_JSQR_JSQ1_1 0x00000002U
1689 #define ADC_JSQR_JSQ1_2 0x00000004U
1690 #define ADC_JSQR_JSQ1_3 0x00000008U
1691 #define ADC_JSQR_JSQ1_4 0x00000010U
1692 #define ADC_JSQR_JSQ2 0x000003E0U
1693 #define ADC_JSQR_JSQ2_0 0x00000020U
1694 #define ADC_JSQR_JSQ2_1 0x00000040U
1695 #define ADC_JSQR_JSQ2_2 0x00000080U
1696 #define ADC_JSQR_JSQ2_3 0x00000100U
1697 #define ADC_JSQR_JSQ2_4 0x00000200U
1698 #define ADC_JSQR_JSQ3 0x00007C00U
1699 #define ADC_JSQR_JSQ3_0 0x00000400U
1700 #define ADC_JSQR_JSQ3_1 0x00000800U
1701 #define ADC_JSQR_JSQ3_2 0x00001000U
1702 #define ADC_JSQR_JSQ3_3 0x00002000U
1703 #define ADC_JSQR_JSQ3_4 0x00004000U
1704 #define ADC_JSQR_JSQ4 0x000F8000U
1705 #define ADC_JSQR_JSQ4_0 0x00008000U
1706 #define ADC_JSQR_JSQ4_1 0x00010000U
1707 #define ADC_JSQR_JSQ4_2 0x00020000U
1708 #define ADC_JSQR_JSQ4_3 0x00040000U
1709 #define ADC_JSQR_JSQ4_4 0x00080000U
1710 #define ADC_JSQR_JL 0x00300000U
1711 #define ADC_JSQR_JL_0 0x00100000U
1712 #define ADC_JSQR_JL_1 0x00200000U
1714 /******************* Bit definition for ADC_JDR1 register *******************/
1715 #define ADC_JDR1_JDATA 0xFFFFU
1717 /******************* Bit definition for ADC_JDR2 register *******************/
1718 #define ADC_JDR2_JDATA 0xFFFFU
1720 /******************* Bit definition for ADC_JDR3 register *******************/
1721 #define ADC_JDR3_JDATA 0xFFFFU
1723 /******************* Bit definition for ADC_JDR4 register *******************/
1724 #define ADC_JDR4_JDATA 0xFFFFU
1726 /******************** Bit definition for ADC_DR register ********************/
1727 #define ADC_DR_DATA 0x0000FFFFU
1728 #define ADC_DR_ADC2DATA 0xFFFF0000U
1730 /******************* Bit definition for ADC_CSR register ********************/
1731 #define ADC_CSR_AWD1 0x00000001U
1732 #define ADC_CSR_EOC1 0x00000002U
1733 #define ADC_CSR_JEOC1 0x00000004U
1734 #define ADC_CSR_JSTRT1 0x00000008U
1735 #define ADC_CSR_STRT1 0x00000010U
1736 #define ADC_CSR_OVR1 0x00000020U
1737 #define ADC_CSR_AWD2 0x00000100U
1738 #define ADC_CSR_EOC2 0x00000200U
1739 #define ADC_CSR_JEOC2 0x00000400U
1740 #define ADC_CSR_JSTRT2 0x00000800U
1741 #define ADC_CSR_STRT2 0x00001000U
1742 #define ADC_CSR_OVR2 0x00002000U
1743 #define ADC_CSR_AWD3 0x00010000U
1744 #define ADC_CSR_EOC3 0x00020000U
1745 #define ADC_CSR_JEOC3 0x00040000U
1746 #define ADC_CSR_JSTRT3 0x00080000U
1747 #define ADC_CSR_STRT3 0x00100000U
1748 #define ADC_CSR_OVR3 0x00200000U
1750 /* Legacy defines */
1751 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1752 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1753 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1754 
1755 /******************* Bit definition for ADC_CCR register ********************/
1756 #define ADC_CCR_MULTI 0x0000001FU
1757 #define ADC_CCR_MULTI_0 0x00000001U
1758 #define ADC_CCR_MULTI_1 0x00000002U
1759 #define ADC_CCR_MULTI_2 0x00000004U
1760 #define ADC_CCR_MULTI_3 0x00000008U
1761 #define ADC_CCR_MULTI_4 0x00000010U
1762 #define ADC_CCR_DELAY 0x00000F00U
1763 #define ADC_CCR_DELAY_0 0x00000100U
1764 #define ADC_CCR_DELAY_1 0x00000200U
1765 #define ADC_CCR_DELAY_2 0x00000400U
1766 #define ADC_CCR_DELAY_3 0x00000800U
1767 #define ADC_CCR_DDS 0x00002000U
1768 #define ADC_CCR_DMA 0x0000C000U
1769 #define ADC_CCR_DMA_0 0x00004000U
1770 #define ADC_CCR_DMA_1 0x00008000U
1771 #define ADC_CCR_ADCPRE 0x00030000U
1772 #define ADC_CCR_ADCPRE_0 0x00010000U
1773 #define ADC_CCR_ADCPRE_1 0x00020000U
1774 #define ADC_CCR_VBATE 0x00400000U
1775 #define ADC_CCR_TSVREFE 0x00800000U
1777 /******************* Bit definition for ADC_CDR register ********************/
1778 #define ADC_CDR_DATA1 0x0000FFFFU
1779 #define ADC_CDR_DATA2 0xFFFF0000U
1781 /******************************************************************************/
1782 /* */
1783 /* Controller Area Network */
1784 /* */
1785 /******************************************************************************/
1787 /******************* Bit definition for CAN_MCR register ********************/
1788 #define CAN_MCR_INRQ 0x00000001U
1789 #define CAN_MCR_SLEEP 0x00000002U
1790 #define CAN_MCR_TXFP 0x00000004U
1791 #define CAN_MCR_RFLM 0x00000008U
1792 #define CAN_MCR_NART 0x00000010U
1793 #define CAN_MCR_AWUM 0x00000020U
1794 #define CAN_MCR_ABOM 0x00000040U
1795 #define CAN_MCR_TTCM 0x00000080U
1796 #define CAN_MCR_RESET 0x00008000U
1797 #define CAN_MCR_DBF 0x00010000U
1798 /******************* Bit definition for CAN_MSR register ********************/
1799 #define CAN_MSR_INAK 0x0001U
1800 #define CAN_MSR_SLAK 0x0002U
1801 #define CAN_MSR_ERRI 0x0004U
1802 #define CAN_MSR_WKUI 0x0008U
1803 #define CAN_MSR_SLAKI 0x0010U
1804 #define CAN_MSR_TXM 0x0100U
1805 #define CAN_MSR_RXM 0x0200U
1806 #define CAN_MSR_SAMP 0x0400U
1807 #define CAN_MSR_RX 0x0800U
1809 /******************* Bit definition for CAN_TSR register ********************/
1810 #define CAN_TSR_RQCP0 0x00000001U
1811 #define CAN_TSR_TXOK0 0x00000002U
1812 #define CAN_TSR_ALST0 0x00000004U
1813 #define CAN_TSR_TERR0 0x00000008U
1814 #define CAN_TSR_ABRQ0 0x00000080U
1815 #define CAN_TSR_RQCP1 0x00000100U
1816 #define CAN_TSR_TXOK1 0x00000200U
1817 #define CAN_TSR_ALST1 0x00000400U
1818 #define CAN_TSR_TERR1 0x00000800U
1819 #define CAN_TSR_ABRQ1 0x00008000U
1820 #define CAN_TSR_RQCP2 0x00010000U
1821 #define CAN_TSR_TXOK2 0x00020000U
1822 #define CAN_TSR_ALST2 0x00040000U
1823 #define CAN_TSR_TERR2 0x00080000U
1824 #define CAN_TSR_ABRQ2 0x00800000U
1825 #define CAN_TSR_CODE 0x03000000U
1827 #define CAN_TSR_TME 0x1C000000U
1828 #define CAN_TSR_TME0 0x04000000U
1829 #define CAN_TSR_TME1 0x08000000U
1830 #define CAN_TSR_TME2 0x10000000U
1832 #define CAN_TSR_LOW 0xE0000000U
1833 #define CAN_TSR_LOW0 0x20000000U
1834 #define CAN_TSR_LOW1 0x40000000U
1835 #define CAN_TSR_LOW2 0x80000000U
1837 /******************* Bit definition for CAN_RF0R register *******************/
1838 #define CAN_RF0R_FMP0 0x03U
1839 #define CAN_RF0R_FULL0 0x08U
1840 #define CAN_RF0R_FOVR0 0x10U
1841 #define CAN_RF0R_RFOM0 0x20U
1843 /******************* Bit definition for CAN_RF1R register *******************/
1844 #define CAN_RF1R_FMP1 0x03U
1845 #define CAN_RF1R_FULL1 0x08U
1846 #define CAN_RF1R_FOVR1 0x10U
1847 #define CAN_RF1R_RFOM1 0x20U
1849 /******************** Bit definition for CAN_IER register *******************/
1850 #define CAN_IER_TMEIE 0x00000001U
1851 #define CAN_IER_FMPIE0 0x00000002U
1852 #define CAN_IER_FFIE0 0x00000004U
1853 #define CAN_IER_FOVIE0 0x00000008U
1854 #define CAN_IER_FMPIE1 0x00000010U
1855 #define CAN_IER_FFIE1 0x00000020U
1856 #define CAN_IER_FOVIE1 0x00000040U
1857 #define CAN_IER_EWGIE 0x00000100U
1858 #define CAN_IER_EPVIE 0x00000200U
1859 #define CAN_IER_BOFIE 0x00000400U
1860 #define CAN_IER_LECIE 0x00000800U
1861 #define CAN_IER_ERRIE 0x00008000U
1862 #define CAN_IER_WKUIE 0x00010000U
1863 #define CAN_IER_SLKIE 0x00020000U
1864 #define CAN_IER_EWGIE 0x00000100U
1865 #define CAN_IER_EPVIE 0x00000200U
1866 #define CAN_IER_BOFIE 0x00000400U
1867 #define CAN_IER_LECIE 0x00000800U
1868 #define CAN_IER_ERRIE 0x00008000U
1871 /******************** Bit definition for CAN_ESR register *******************/
1872 #define CAN_ESR_EWGF 0x00000001U
1873 #define CAN_ESR_EPVF 0x00000002U
1874 #define CAN_ESR_BOFF 0x00000004U
1876 #define CAN_ESR_LEC 0x00000070U
1877 #define CAN_ESR_LEC_0 0x00000010U
1878 #define CAN_ESR_LEC_1 0x00000020U
1879 #define CAN_ESR_LEC_2 0x00000040U
1881 #define CAN_ESR_TEC 0x00FF0000U
1882 #define CAN_ESR_REC 0xFF000000U
1884 /******************* Bit definition for CAN_BTR register ********************/
1885 #define CAN_BTR_BRP 0x000003FFU
1886 #define CAN_BTR_TS1 0x000F0000U
1887 #define CAN_BTR_TS1_0 0x00010000U
1888 #define CAN_BTR_TS1_1 0x00020000U
1889 #define CAN_BTR_TS1_2 0x00040000U
1890 #define CAN_BTR_TS1_3 0x00080000U
1891 #define CAN_BTR_TS2 0x00700000U
1892 #define CAN_BTR_TS2_0 0x00100000U
1893 #define CAN_BTR_TS2_1 0x00200000U
1894 #define CAN_BTR_TS2_2 0x00400000U
1895 #define CAN_BTR_SJW 0x03000000U
1896 #define CAN_BTR_SJW_0 0x01000000U
1897 #define CAN_BTR_SJW_1 0x02000000U
1898 #define CAN_BTR_LBKM 0x40000000U
1899 #define CAN_BTR_SILM 0x80000000U
1903 /****************** Bit definition for CAN_TI0R register ********************/
1904 #define CAN_TI0R_TXRQ 0x00000001U
1905 #define CAN_TI0R_RTR 0x00000002U
1906 #define CAN_TI0R_IDE 0x00000004U
1907 #define CAN_TI0R_EXID 0x001FFFF8U
1908 #define CAN_TI0R_STID 0xFFE00000U
1910 /****************** Bit definition for CAN_TDT0R register *******************/
1911 #define CAN_TDT0R_DLC 0x0000000FU
1912 #define CAN_TDT0R_TGT 0x00000100U
1913 #define CAN_TDT0R_TIME 0xFFFF0000U
1915 /****************** Bit definition for CAN_TDL0R register *******************/
1916 #define CAN_TDL0R_DATA0 0x000000FFU
1917 #define CAN_TDL0R_DATA1 0x0000FF00U
1918 #define CAN_TDL0R_DATA2 0x00FF0000U
1919 #define CAN_TDL0R_DATA3 0xFF000000U
1921 /****************** Bit definition for CAN_TDH0R register *******************/
1922 #define CAN_TDH0R_DATA4 0x000000FFU
1923 #define CAN_TDH0R_DATA5 0x0000FF00U
1924 #define CAN_TDH0R_DATA6 0x00FF0000U
1925 #define CAN_TDH0R_DATA7 0xFF000000U
1927 /******************* Bit definition for CAN_TI1R register *******************/
1928 #define CAN_TI1R_TXRQ 0x00000001U
1929 #define CAN_TI1R_RTR 0x00000002U
1930 #define CAN_TI1R_IDE 0x00000004U
1931 #define CAN_TI1R_EXID 0x001FFFF8U
1932 #define CAN_TI1R_STID 0xFFE00000U
1934 /******************* Bit definition for CAN_TDT1R register ******************/
1935 #define CAN_TDT1R_DLC 0x0000000FU
1936 #define CAN_TDT1R_TGT 0x00000100U
1937 #define CAN_TDT1R_TIME 0xFFFF0000U
1939 /******************* Bit definition for CAN_TDL1R register ******************/
1940 #define CAN_TDL1R_DATA0 0x000000FFU
1941 #define CAN_TDL1R_DATA1 0x0000FF00U
1942 #define CAN_TDL1R_DATA2 0x00FF0000U
1943 #define CAN_TDL1R_DATA3 0xFF000000U
1945 /******************* Bit definition for CAN_TDH1R register ******************/
1946 #define CAN_TDH1R_DATA4 0x000000FFU
1947 #define CAN_TDH1R_DATA5 0x0000FF00U
1948 #define CAN_TDH1R_DATA6 0x00FF0000U
1949 #define CAN_TDH1R_DATA7 0xFF000000U
1951 /******************* Bit definition for CAN_TI2R register *******************/
1952 #define CAN_TI2R_TXRQ 0x00000001U
1953 #define CAN_TI2R_RTR 0x00000002U
1954 #define CAN_TI2R_IDE 0x00000004U
1955 #define CAN_TI2R_EXID 0x001FFFF8U
1956 #define CAN_TI2R_STID 0xFFE00000U
1958 /******************* Bit definition for CAN_TDT2R register ******************/
1959 #define CAN_TDT2R_DLC 0x0000000FU
1960 #define CAN_TDT2R_TGT 0x00000100U
1961 #define CAN_TDT2R_TIME 0xFFFF0000U
1963 /******************* Bit definition for CAN_TDL2R register ******************/
1964 #define CAN_TDL2R_DATA0 0x000000FFU
1965 #define CAN_TDL2R_DATA1 0x0000FF00U
1966 #define CAN_TDL2R_DATA2 0x00FF0000U
1967 #define CAN_TDL2R_DATA3 0xFF000000U
1969 /******************* Bit definition for CAN_TDH2R register ******************/
1970 #define CAN_TDH2R_DATA4 0x000000FFU
1971 #define CAN_TDH2R_DATA5 0x0000FF00U
1972 #define CAN_TDH2R_DATA6 0x00FF0000U
1973 #define CAN_TDH2R_DATA7 0xFF000000U
1975 /******************* Bit definition for CAN_RI0R register *******************/
1976 #define CAN_RI0R_RTR 0x00000002U
1977 #define CAN_RI0R_IDE 0x00000004U
1978 #define CAN_RI0R_EXID 0x001FFFF8U
1979 #define CAN_RI0R_STID 0xFFE00000U
1981 /******************* Bit definition for CAN_RDT0R register ******************/
1982 #define CAN_RDT0R_DLC 0x0000000FU
1983 #define CAN_RDT0R_FMI 0x0000FF00U
1984 #define CAN_RDT0R_TIME 0xFFFF0000U
1986 /******************* Bit definition for CAN_RDL0R register ******************/
1987 #define CAN_RDL0R_DATA0 0x000000FFU
1988 #define CAN_RDL0R_DATA1 0x0000FF00U
1989 #define CAN_RDL0R_DATA2 0x00FF0000U
1990 #define CAN_RDL0R_DATA3 0xFF000000U
1992 /******************* Bit definition for CAN_RDH0R register ******************/
1993 #define CAN_RDH0R_DATA4 0x000000FFU
1994 #define CAN_RDH0R_DATA5 0x0000FF00U
1995 #define CAN_RDH0R_DATA6 0x00FF0000U
1996 #define CAN_RDH0R_DATA7 0xFF000000U
1998 /******************* Bit definition for CAN_RI1R register *******************/
1999 #define CAN_RI1R_RTR 0x00000002U
2000 #define CAN_RI1R_IDE 0x00000004U
2001 #define CAN_RI1R_EXID 0x001FFFF8U
2002 #define CAN_RI1R_STID 0xFFE00000U
2004 /******************* Bit definition for CAN_RDT1R register ******************/
2005 #define CAN_RDT1R_DLC 0x0000000FU
2006 #define CAN_RDT1R_FMI 0x0000FF00U
2007 #define CAN_RDT1R_TIME 0xFFFF0000U
2009 /******************* Bit definition for CAN_RDL1R register ******************/
2010 #define CAN_RDL1R_DATA0 0x000000FFU
2011 #define CAN_RDL1R_DATA1 0x0000FF00U
2012 #define CAN_RDL1R_DATA2 0x00FF0000U
2013 #define CAN_RDL1R_DATA3 0xFF000000U
2015 /******************* Bit definition for CAN_RDH1R register ******************/
2016 #define CAN_RDH1R_DATA4 0x000000FFU
2017 #define CAN_RDH1R_DATA5 0x0000FF00U
2018 #define CAN_RDH1R_DATA6 0x00FF0000U
2019 #define CAN_RDH1R_DATA7 0xFF000000U
2022 /******************* Bit definition for CAN_FMR register ********************/
2023 #define CAN_FMR_FINIT 0x01U
2024 #define CAN_FMR_CAN2SB 0x00003F00U
2026 /******************* Bit definition for CAN_FM1R register *******************/
2027 #define CAN_FM1R_FBM 0x0FFFFFFFU
2028 #define CAN_FM1R_FBM0 0x00000001U
2029 #define CAN_FM1R_FBM1 0x00000002U
2030 #define CAN_FM1R_FBM2 0x00000004U
2031 #define CAN_FM1R_FBM3 0x00000008U
2032 #define CAN_FM1R_FBM4 0x00000010U
2033 #define CAN_FM1R_FBM5 0x00000020U
2034 #define CAN_FM1R_FBM6 0x00000040U
2035 #define CAN_FM1R_FBM7 0x00000080U
2036 #define CAN_FM1R_FBM8 0x00000100U
2037 #define CAN_FM1R_FBM9 0x00000200U
2038 #define CAN_FM1R_FBM10 0x00000400U
2039 #define CAN_FM1R_FBM11 0x00000800U
2040 #define CAN_FM1R_FBM12 0x00001000U
2041 #define CAN_FM1R_FBM13 0x00002000U
2042 #define CAN_FM1R_FBM14 0x00004000U
2043 #define CAN_FM1R_FBM15 0x00008000U
2044 #define CAN_FM1R_FBM16 0x00010000U
2045 #define CAN_FM1R_FBM17 0x00020000U
2046 #define CAN_FM1R_FBM18 0x00040000U
2047 #define CAN_FM1R_FBM19 0x00080000U
2048 #define CAN_FM1R_FBM20 0x00100000U
2049 #define CAN_FM1R_FBM21 0x00200000U
2050 #define CAN_FM1R_FBM22 0x00400000U
2051 #define CAN_FM1R_FBM23 0x00800000U
2052 #define CAN_FM1R_FBM24 0x01000000U
2053 #define CAN_FM1R_FBM25 0x02000000U
2054 #define CAN_FM1R_FBM26 0x04000000U
2055 #define CAN_FM1R_FBM27 0x08000000U
2057 /******************* Bit definition for CAN_FS1R register *******************/
2058 #define CAN_FS1R_FSC 0x0FFFFFFFU
2059 #define CAN_FS1R_FSC0 0x00000001U
2060 #define CAN_FS1R_FSC1 0x00000002U
2061 #define CAN_FS1R_FSC2 0x00000004U
2062 #define CAN_FS1R_FSC3 0x00000008U
2063 #define CAN_FS1R_FSC4 0x00000010U
2064 #define CAN_FS1R_FSC5 0x00000020U
2065 #define CAN_FS1R_FSC6 0x00000040U
2066 #define CAN_FS1R_FSC7 0x00000080U
2067 #define CAN_FS1R_FSC8 0x00000100U
2068 #define CAN_FS1R_FSC9 0x00000200U
2069 #define CAN_FS1R_FSC10 0x00000400U
2070 #define CAN_FS1R_FSC11 0x00000800U
2071 #define CAN_FS1R_FSC12 0x00001000U
2072 #define CAN_FS1R_FSC13 0x00002000U
2073 #define CAN_FS1R_FSC14 0x00004000U
2074 #define CAN_FS1R_FSC15 0x00008000U
2075 #define CAN_FS1R_FSC16 0x00010000U
2076 #define CAN_FS1R_FSC17 0x00020000U
2077 #define CAN_FS1R_FSC18 0x00040000U
2078 #define CAN_FS1R_FSC19 0x00080000U
2079 #define CAN_FS1R_FSC20 0x00100000U
2080 #define CAN_FS1R_FSC21 0x00200000U
2081 #define CAN_FS1R_FSC22 0x00400000U
2082 #define CAN_FS1R_FSC23 0x00800000U
2083 #define CAN_FS1R_FSC24 0x01000000U
2084 #define CAN_FS1R_FSC25 0x02000000U
2085 #define CAN_FS1R_FSC26 0x04000000U
2086 #define CAN_FS1R_FSC27 0x08000000U
2088 /****************** Bit definition for CAN_FFA1R register *******************/
2089 #define CAN_FFA1R_FFA 0x0FFFFFFFU
2090 #define CAN_FFA1R_FFA0 0x00000001U
2091 #define CAN_FFA1R_FFA1 0x00000002U
2092 #define CAN_FFA1R_FFA2 0x00000004U
2093 #define CAN_FFA1R_FFA3 0x00000008U
2094 #define CAN_FFA1R_FFA4 0x00000010U
2095 #define CAN_FFA1R_FFA5 0x00000020U
2096 #define CAN_FFA1R_FFA6 0x00000040U
2097 #define CAN_FFA1R_FFA7 0x00000080U
2098 #define CAN_FFA1R_FFA8 0x00000100U
2099 #define CAN_FFA1R_FFA9 0x00000200U
2100 #define CAN_FFA1R_FFA10 0x00000400U
2101 #define CAN_FFA1R_FFA11 0x00000800U
2102 #define CAN_FFA1R_FFA12 0x00001000U
2103 #define CAN_FFA1R_FFA13 0x00002000U
2104 #define CAN_FFA1R_FFA14 0x00004000U
2105 #define CAN_FFA1R_FFA15 0x00008000U
2106 #define CAN_FFA1R_FFA16 0x00010000U
2107 #define CAN_FFA1R_FFA17 0x00020000U
2108 #define CAN_FFA1R_FFA18 0x00040000U
2109 #define CAN_FFA1R_FFA19 0x00080000U
2110 #define CAN_FFA1R_FFA20 0x00100000U
2111 #define CAN_FFA1R_FFA21 0x00200000U
2112 #define CAN_FFA1R_FFA22 0x00400000U
2113 #define CAN_FFA1R_FFA23 0x00800000U
2114 #define CAN_FFA1R_FFA24 0x01000000U
2115 #define CAN_FFA1R_FFA25 0x02000000U
2116 #define CAN_FFA1R_FFA26 0x04000000U
2117 #define CAN_FFA1R_FFA27 0x08000000U
2119 /******************* Bit definition for CAN_FA1R register *******************/
2120 #define CAN_FA1R_FACT 0x0FFFFFFFU
2121 #define CAN_FA1R_FACT0 0x00000001U
2122 #define CAN_FA1R_FACT1 0x00000002U
2123 #define CAN_FA1R_FACT2 0x00000004U
2124 #define CAN_FA1R_FACT3 0x00000008U
2125 #define CAN_FA1R_FACT4 0x00000010U
2126 #define CAN_FA1R_FACT5 0x00000020U
2127 #define CAN_FA1R_FACT6 0x00000040U
2128 #define CAN_FA1R_FACT7 0x00000080U
2129 #define CAN_FA1R_FACT8 0x00000100U
2130 #define CAN_FA1R_FACT9 0x00000200U
2131 #define CAN_FA1R_FACT10 0x00000400U
2132 #define CAN_FA1R_FACT11 0x00000800U
2133 #define CAN_FA1R_FACT12 0x00001000U
2134 #define CAN_FA1R_FACT13 0x00002000U
2135 #define CAN_FA1R_FACT14 0x00004000U
2136 #define CAN_FA1R_FACT15 0x00008000U
2137 #define CAN_FA1R_FACT16 0x00010000U
2138 #define CAN_FA1R_FACT17 0x00020000U
2139 #define CAN_FA1R_FACT18 0x00040000U
2140 #define CAN_FA1R_FACT19 0x00080000U
2141 #define CAN_FA1R_FACT20 0x00100000U
2142 #define CAN_FA1R_FACT21 0x00200000U
2143 #define CAN_FA1R_FACT22 0x00400000U
2144 #define CAN_FA1R_FACT23 0x00800000U
2145 #define CAN_FA1R_FACT24 0x01000000U
2146 #define CAN_FA1R_FACT25 0x02000000U
2147 #define CAN_FA1R_FACT26 0x04000000U
2148 #define CAN_FA1R_FACT27 0x08000000U
2151 /******************* Bit definition for CAN_F0R1 register *******************/
2152 #define CAN_F0R1_FB0 0x00000001U
2153 #define CAN_F0R1_FB1 0x00000002U
2154 #define CAN_F0R1_FB2 0x00000004U
2155 #define CAN_F0R1_FB3 0x00000008U
2156 #define CAN_F0R1_FB4 0x00000010U
2157 #define CAN_F0R1_FB5 0x00000020U
2158 #define CAN_F0R1_FB6 0x00000040U
2159 #define CAN_F0R1_FB7 0x00000080U
2160 #define CAN_F0R1_FB8 0x00000100U
2161 #define CAN_F0R1_FB9 0x00000200U
2162 #define CAN_F0R1_FB10 0x00000400U
2163 #define CAN_F0R1_FB11 0x00000800U
2164 #define CAN_F0R1_FB12 0x00001000U
2165 #define CAN_F0R1_FB13 0x00002000U
2166 #define CAN_F0R1_FB14 0x00004000U
2167 #define CAN_F0R1_FB15 0x00008000U
2168 #define CAN_F0R1_FB16 0x00010000U
2169 #define CAN_F0R1_FB17 0x00020000U
2170 #define CAN_F0R1_FB18 0x00040000U
2171 #define CAN_F0R1_FB19 0x00080000U
2172 #define CAN_F0R1_FB20 0x00100000U
2173 #define CAN_F0R1_FB21 0x00200000U
2174 #define CAN_F0R1_FB22 0x00400000U
2175 #define CAN_F0R1_FB23 0x00800000U
2176 #define CAN_F0R1_FB24 0x01000000U
2177 #define CAN_F0R1_FB25 0x02000000U
2178 #define CAN_F0R1_FB26 0x04000000U
2179 #define CAN_F0R1_FB27 0x08000000U
2180 #define CAN_F0R1_FB28 0x10000000U
2181 #define CAN_F0R1_FB29 0x20000000U
2182 #define CAN_F0R1_FB30 0x40000000U
2183 #define CAN_F0R1_FB31 0x80000000U
2185 /******************* Bit definition for CAN_F1R1 register *******************/
2186 #define CAN_F1R1_FB0 0x00000001U
2187 #define CAN_F1R1_FB1 0x00000002U
2188 #define CAN_F1R1_FB2 0x00000004U
2189 #define CAN_F1R1_FB3 0x00000008U
2190 #define CAN_F1R1_FB4 0x00000010U
2191 #define CAN_F1R1_FB5 0x00000020U
2192 #define CAN_F1R1_FB6 0x00000040U
2193 #define CAN_F1R1_FB7 0x00000080U
2194 #define CAN_F1R1_FB8 0x00000100U
2195 #define CAN_F1R1_FB9 0x00000200U
2196 #define CAN_F1R1_FB10 0x00000400U
2197 #define CAN_F1R1_FB11 0x00000800U
2198 #define CAN_F1R1_FB12 0x00001000U
2199 #define CAN_F1R1_FB13 0x00002000U
2200 #define CAN_F1R1_FB14 0x00004000U
2201 #define CAN_F1R1_FB15 0x00008000U
2202 #define CAN_F1R1_FB16 0x00010000U
2203 #define CAN_F1R1_FB17 0x00020000U
2204 #define CAN_F1R1_FB18 0x00040000U
2205 #define CAN_F1R1_FB19 0x00080000U
2206 #define CAN_F1R1_FB20 0x00100000U
2207 #define CAN_F1R1_FB21 0x00200000U
2208 #define CAN_F1R1_FB22 0x00400000U
2209 #define CAN_F1R1_FB23 0x00800000U
2210 #define CAN_F1R1_FB24 0x01000000U
2211 #define CAN_F1R1_FB25 0x02000000U
2212 #define CAN_F1R1_FB26 0x04000000U
2213 #define CAN_F1R1_FB27 0x08000000U
2214 #define CAN_F1R1_FB28 0x10000000U
2215 #define CAN_F1R1_FB29 0x20000000U
2216 #define CAN_F1R1_FB30 0x40000000U
2217 #define CAN_F1R1_FB31 0x80000000U
2219 /******************* Bit definition for CAN_F2R1 register *******************/
2220 #define CAN_F2R1_FB0 0x00000001U
2221 #define CAN_F2R1_FB1 0x00000002U
2222 #define CAN_F2R1_FB2 0x00000004U
2223 #define CAN_F2R1_FB3 0x00000008U
2224 #define CAN_F2R1_FB4 0x00000010U
2225 #define CAN_F2R1_FB5 0x00000020U
2226 #define CAN_F2R1_FB6 0x00000040U
2227 #define CAN_F2R1_FB7 0x00000080U
2228 #define CAN_F2R1_FB8 0x00000100U
2229 #define CAN_F2R1_FB9 0x00000200U
2230 #define CAN_F2R1_FB10 0x00000400U
2231 #define CAN_F2R1_FB11 0x00000800U
2232 #define CAN_F2R1_FB12 0x00001000U
2233 #define CAN_F2R1_FB13 0x00002000U
2234 #define CAN_F2R1_FB14 0x00004000U
2235 #define CAN_F2R1_FB15 0x00008000U
2236 #define CAN_F2R1_FB16 0x00010000U
2237 #define CAN_F2R1_FB17 0x00020000U
2238 #define CAN_F2R1_FB18 0x00040000U
2239 #define CAN_F2R1_FB19 0x00080000U
2240 #define CAN_F2R1_FB20 0x00100000U
2241 #define CAN_F2R1_FB21 0x00200000U
2242 #define CAN_F2R1_FB22 0x00400000U
2243 #define CAN_F2R1_FB23 0x00800000U
2244 #define CAN_F2R1_FB24 0x01000000U
2245 #define CAN_F2R1_FB25 0x02000000U
2246 #define CAN_F2R1_FB26 0x04000000U
2247 #define CAN_F2R1_FB27 0x08000000U
2248 #define CAN_F2R1_FB28 0x10000000U
2249 #define CAN_F2R1_FB29 0x20000000U
2250 #define CAN_F2R1_FB30 0x40000000U
2251 #define CAN_F2R1_FB31 0x80000000U
2253 /******************* Bit definition for CAN_F3R1 register *******************/
2254 #define CAN_F3R1_FB0 0x00000001U
2255 #define CAN_F3R1_FB1 0x00000002U
2256 #define CAN_F3R1_FB2 0x00000004U
2257 #define CAN_F3R1_FB3 0x00000008U
2258 #define CAN_F3R1_FB4 0x00000010U
2259 #define CAN_F3R1_FB5 0x00000020U
2260 #define CAN_F3R1_FB6 0x00000040U
2261 #define CAN_F3R1_FB7 0x00000080U
2262 #define CAN_F3R1_FB8 0x00000100U
2263 #define CAN_F3R1_FB9 0x00000200U
2264 #define CAN_F3R1_FB10 0x00000400U
2265 #define CAN_F3R1_FB11 0x00000800U
2266 #define CAN_F3R1_FB12 0x00001000U
2267 #define CAN_F3R1_FB13 0x00002000U
2268 #define CAN_F3R1_FB14 0x00004000U
2269 #define CAN_F3R1_FB15 0x00008000U
2270 #define CAN_F3R1_FB16 0x00010000U
2271 #define CAN_F3R1_FB17 0x00020000U
2272 #define CAN_F3R1_FB18 0x00040000U
2273 #define CAN_F3R1_FB19 0x00080000U
2274 #define CAN_F3R1_FB20 0x00100000U
2275 #define CAN_F3R1_FB21 0x00200000U
2276 #define CAN_F3R1_FB22 0x00400000U
2277 #define CAN_F3R1_FB23 0x00800000U
2278 #define CAN_F3R1_FB24 0x01000000U
2279 #define CAN_F3R1_FB25 0x02000000U
2280 #define CAN_F3R1_FB26 0x04000000U
2281 #define CAN_F3R1_FB27 0x08000000U
2282 #define CAN_F3R1_FB28 0x10000000U
2283 #define CAN_F3R1_FB29 0x20000000U
2284 #define CAN_F3R1_FB30 0x40000000U
2285 #define CAN_F3R1_FB31 0x80000000U
2287 /******************* Bit definition for CAN_F4R1 register *******************/
2288 #define CAN_F4R1_FB0 0x00000001U
2289 #define CAN_F4R1_FB1 0x00000002U
2290 #define CAN_F4R1_FB2 0x00000004U
2291 #define CAN_F4R1_FB3 0x00000008U
2292 #define CAN_F4R1_FB4 0x00000010U
2293 #define CAN_F4R1_FB5 0x00000020U
2294 #define CAN_F4R1_FB6 0x00000040U
2295 #define CAN_F4R1_FB7 0x00000080U
2296 #define CAN_F4R1_FB8 0x00000100U
2297 #define CAN_F4R1_FB9 0x00000200U
2298 #define CAN_F4R1_FB10 0x00000400U
2299 #define CAN_F4R1_FB11 0x00000800U
2300 #define CAN_F4R1_FB12 0x00001000U
2301 #define CAN_F4R1_FB13 0x00002000U
2302 #define CAN_F4R1_FB14 0x00004000U
2303 #define CAN_F4R1_FB15 0x00008000U
2304 #define CAN_F4R1_FB16 0x00010000U
2305 #define CAN_F4R1_FB17 0x00020000U
2306 #define CAN_F4R1_FB18 0x00040000U
2307 #define CAN_F4R1_FB19 0x00080000U
2308 #define CAN_F4R1_FB20 0x00100000U
2309 #define CAN_F4R1_FB21 0x00200000U
2310 #define CAN_F4R1_FB22 0x00400000U
2311 #define CAN_F4R1_FB23 0x00800000U
2312 #define CAN_F4R1_FB24 0x01000000U
2313 #define CAN_F4R1_FB25 0x02000000U
2314 #define CAN_F4R1_FB26 0x04000000U
2315 #define CAN_F4R1_FB27 0x08000000U
2316 #define CAN_F4R1_FB28 0x10000000U
2317 #define CAN_F4R1_FB29 0x20000000U
2318 #define CAN_F4R1_FB30 0x40000000U
2319 #define CAN_F4R1_FB31 0x80000000U
2321 /******************* Bit definition for CAN_F5R1 register *******************/
2322 #define CAN_F5R1_FB0 0x00000001U
2323 #define CAN_F5R1_FB1 0x00000002U
2324 #define CAN_F5R1_FB2 0x00000004U
2325 #define CAN_F5R1_FB3 0x00000008U
2326 #define CAN_F5R1_FB4 0x00000010U
2327 #define CAN_F5R1_FB5 0x00000020U
2328 #define CAN_F5R1_FB6 0x00000040U
2329 #define CAN_F5R1_FB7 0x00000080U
2330 #define CAN_F5R1_FB8 0x00000100U
2331 #define CAN_F5R1_FB9 0x00000200U
2332 #define CAN_F5R1_FB10 0x00000400U
2333 #define CAN_F5R1_FB11 0x00000800U
2334 #define CAN_F5R1_FB12 0x00001000U
2335 #define CAN_F5R1_FB13 0x00002000U
2336 #define CAN_F5R1_FB14 0x00004000U
2337 #define CAN_F5R1_FB15 0x00008000U
2338 #define CAN_F5R1_FB16 0x00010000U
2339 #define CAN_F5R1_FB17 0x00020000U
2340 #define CAN_F5R1_FB18 0x00040000U
2341 #define CAN_F5R1_FB19 0x00080000U
2342 #define CAN_F5R1_FB20 0x00100000U
2343 #define CAN_F5R1_FB21 0x00200000U
2344 #define CAN_F5R1_FB22 0x00400000U
2345 #define CAN_F5R1_FB23 0x00800000U
2346 #define CAN_F5R1_FB24 0x01000000U
2347 #define CAN_F5R1_FB25 0x02000000U
2348 #define CAN_F5R1_FB26 0x04000000U
2349 #define CAN_F5R1_FB27 0x08000000U
2350 #define CAN_F5R1_FB28 0x10000000U
2351 #define CAN_F5R1_FB29 0x20000000U
2352 #define CAN_F5R1_FB30 0x40000000U
2353 #define CAN_F5R1_FB31 0x80000000U
2355 /******************* Bit definition for CAN_F6R1 register *******************/
2356 #define CAN_F6R1_FB0 0x00000001U
2357 #define CAN_F6R1_FB1 0x00000002U
2358 #define CAN_F6R1_FB2 0x00000004U
2359 #define CAN_F6R1_FB3 0x00000008U
2360 #define CAN_F6R1_FB4 0x00000010U
2361 #define CAN_F6R1_FB5 0x00000020U
2362 #define CAN_F6R1_FB6 0x00000040U
2363 #define CAN_F6R1_FB7 0x00000080U
2364 #define CAN_F6R1_FB8 0x00000100U
2365 #define CAN_F6R1_FB9 0x00000200U
2366 #define CAN_F6R1_FB10 0x00000400U
2367 #define CAN_F6R1_FB11 0x00000800U
2368 #define CAN_F6R1_FB12 0x00001000U
2369 #define CAN_F6R1_FB13 0x00002000U
2370 #define CAN_F6R1_FB14 0x00004000U
2371 #define CAN_F6R1_FB15 0x00008000U
2372 #define CAN_F6R1_FB16 0x00010000U
2373 #define CAN_F6R1_FB17 0x00020000U
2374 #define CAN_F6R1_FB18 0x00040000U
2375 #define CAN_F6R1_FB19 0x00080000U
2376 #define CAN_F6R1_FB20 0x00100000U
2377 #define CAN_F6R1_FB21 0x00200000U
2378 #define CAN_F6R1_FB22 0x00400000U
2379 #define CAN_F6R1_FB23 0x00800000U
2380 #define CAN_F6R1_FB24 0x01000000U
2381 #define CAN_F6R1_FB25 0x02000000U
2382 #define CAN_F6R1_FB26 0x04000000U
2383 #define CAN_F6R1_FB27 0x08000000U
2384 #define CAN_F6R1_FB28 0x10000000U
2385 #define CAN_F6R1_FB29 0x20000000U
2386 #define CAN_F6R1_FB30 0x40000000U
2387 #define CAN_F6R1_FB31 0x80000000U
2389 /******************* Bit definition for CAN_F7R1 register *******************/
2390 #define CAN_F7R1_FB0 0x00000001U
2391 #define CAN_F7R1_FB1 0x00000002U
2392 #define CAN_F7R1_FB2 0x00000004U
2393 #define CAN_F7R1_FB3 0x00000008U
2394 #define CAN_F7R1_FB4 0x00000010U
2395 #define CAN_F7R1_FB5 0x00000020U
2396 #define CAN_F7R1_FB6 0x00000040U
2397 #define CAN_F7R1_FB7 0x00000080U
2398 #define CAN_F7R1_FB8 0x00000100U
2399 #define CAN_F7R1_FB9 0x00000200U
2400 #define CAN_F7R1_FB10 0x00000400U
2401 #define CAN_F7R1_FB11 0x00000800U
2402 #define CAN_F7R1_FB12 0x00001000U
2403 #define CAN_F7R1_FB13 0x00002000U
2404 #define CAN_F7R1_FB14 0x00004000U
2405 #define CAN_F7R1_FB15 0x00008000U
2406 #define CAN_F7R1_FB16 0x00010000U
2407 #define CAN_F7R1_FB17 0x00020000U
2408 #define CAN_F7R1_FB18 0x00040000U
2409 #define CAN_F7R1_FB19 0x00080000U
2410 #define CAN_F7R1_FB20 0x00100000U
2411 #define CAN_F7R1_FB21 0x00200000U
2412 #define CAN_F7R1_FB22 0x00400000U
2413 #define CAN_F7R1_FB23 0x00800000U
2414 #define CAN_F7R1_FB24 0x01000000U
2415 #define CAN_F7R1_FB25 0x02000000U
2416 #define CAN_F7R1_FB26 0x04000000U
2417 #define CAN_F7R1_FB27 0x08000000U
2418 #define CAN_F7R1_FB28 0x10000000U
2419 #define CAN_F7R1_FB29 0x20000000U
2420 #define CAN_F7R1_FB30 0x40000000U
2421 #define CAN_F7R1_FB31 0x80000000U
2423 /******************* Bit definition for CAN_F8R1 register *******************/
2424 #define CAN_F8R1_FB0 0x00000001U
2425 #define CAN_F8R1_FB1 0x00000002U
2426 #define CAN_F8R1_FB2 0x00000004U
2427 #define CAN_F8R1_FB3 0x00000008U
2428 #define CAN_F8R1_FB4 0x00000010U
2429 #define CAN_F8R1_FB5 0x00000020U
2430 #define CAN_F8R1_FB6 0x00000040U
2431 #define CAN_F8R1_FB7 0x00000080U
2432 #define CAN_F8R1_FB8 0x00000100U
2433 #define CAN_F8R1_FB9 0x00000200U
2434 #define CAN_F8R1_FB10 0x00000400U
2435 #define CAN_F8R1_FB11 0x00000800U
2436 #define CAN_F8R1_FB12 0x00001000U
2437 #define CAN_F8R1_FB13 0x00002000U
2438 #define CAN_F8R1_FB14 0x00004000U
2439 #define CAN_F8R1_FB15 0x00008000U
2440 #define CAN_F8R1_FB16 0x00010000U
2441 #define CAN_F8R1_FB17 0x00020000U
2442 #define CAN_F8R1_FB18 0x00040000U
2443 #define CAN_F8R1_FB19 0x00080000U
2444 #define CAN_F8R1_FB20 0x00100000U
2445 #define CAN_F8R1_FB21 0x00200000U
2446 #define CAN_F8R1_FB22 0x00400000U
2447 #define CAN_F8R1_FB23 0x00800000U
2448 #define CAN_F8R1_FB24 0x01000000U
2449 #define CAN_F8R1_FB25 0x02000000U
2450 #define CAN_F8R1_FB26 0x04000000U
2451 #define CAN_F8R1_FB27 0x08000000U
2452 #define CAN_F8R1_FB28 0x10000000U
2453 #define CAN_F8R1_FB29 0x20000000U
2454 #define CAN_F8R1_FB30 0x40000000U
2455 #define CAN_F8R1_FB31 0x80000000U
2457 /******************* Bit definition for CAN_F9R1 register *******************/
2458 #define CAN_F9R1_FB0 0x00000001U
2459 #define CAN_F9R1_FB1 0x00000002U
2460 #define CAN_F9R1_FB2 0x00000004U
2461 #define CAN_F9R1_FB3 0x00000008U
2462 #define CAN_F9R1_FB4 0x00000010U
2463 #define CAN_F9R1_FB5 0x00000020U
2464 #define CAN_F9R1_FB6 0x00000040U
2465 #define CAN_F9R1_FB7 0x00000080U
2466 #define CAN_F9R1_FB8 0x00000100U
2467 #define CAN_F9R1_FB9 0x00000200U
2468 #define CAN_F9R1_FB10 0x00000400U
2469 #define CAN_F9R1_FB11 0x00000800U
2470 #define CAN_F9R1_FB12 0x00001000U
2471 #define CAN_F9R1_FB13 0x00002000U
2472 #define CAN_F9R1_FB14 0x00004000U
2473 #define CAN_F9R1_FB15 0x00008000U
2474 #define CAN_F9R1_FB16 0x00010000U
2475 #define CAN_F9R1_FB17 0x00020000U
2476 #define CAN_F9R1_FB18 0x00040000U
2477 #define CAN_F9R1_FB19 0x00080000U
2478 #define CAN_F9R1_FB20 0x00100000U
2479 #define CAN_F9R1_FB21 0x00200000U
2480 #define CAN_F9R1_FB22 0x00400000U
2481 #define CAN_F9R1_FB23 0x00800000U
2482 #define CAN_F9R1_FB24 0x01000000U
2483 #define CAN_F9R1_FB25 0x02000000U
2484 #define CAN_F9R1_FB26 0x04000000U
2485 #define CAN_F9R1_FB27 0x08000000U
2486 #define CAN_F9R1_FB28 0x10000000U
2487 #define CAN_F9R1_FB29 0x20000000U
2488 #define CAN_F9R1_FB30 0x40000000U
2489 #define CAN_F9R1_FB31 0x80000000U
2491 /******************* Bit definition for CAN_F10R1 register ******************/
2492 #define CAN_F10R1_FB0 0x00000001U
2493 #define CAN_F10R1_FB1 0x00000002U
2494 #define CAN_F10R1_FB2 0x00000004U
2495 #define CAN_F10R1_FB3 0x00000008U
2496 #define CAN_F10R1_FB4 0x00000010U
2497 #define CAN_F10R1_FB5 0x00000020U
2498 #define CAN_F10R1_FB6 0x00000040U
2499 #define CAN_F10R1_FB7 0x00000080U
2500 #define CAN_F10R1_FB8 0x00000100U
2501 #define CAN_F10R1_FB9 0x00000200U
2502 #define CAN_F10R1_FB10 0x00000400U
2503 #define CAN_F10R1_FB11 0x00000800U
2504 #define CAN_F10R1_FB12 0x00001000U
2505 #define CAN_F10R1_FB13 0x00002000U
2506 #define CAN_F10R1_FB14 0x00004000U
2507 #define CAN_F10R1_FB15 0x00008000U
2508 #define CAN_F10R1_FB16 0x00010000U
2509 #define CAN_F10R1_FB17 0x00020000U
2510 #define CAN_F10R1_FB18 0x00040000U
2511 #define CAN_F10R1_FB19 0x00080000U
2512 #define CAN_F10R1_FB20 0x00100000U
2513 #define CAN_F10R1_FB21 0x00200000U
2514 #define CAN_F10R1_FB22 0x00400000U
2515 #define CAN_F10R1_FB23 0x00800000U
2516 #define CAN_F10R1_FB24 0x01000000U
2517 #define CAN_F10R1_FB25 0x02000000U
2518 #define CAN_F10R1_FB26 0x04000000U
2519 #define CAN_F10R1_FB27 0x08000000U
2520 #define CAN_F10R1_FB28 0x10000000U
2521 #define CAN_F10R1_FB29 0x20000000U
2522 #define CAN_F10R1_FB30 0x40000000U
2523 #define CAN_F10R1_FB31 0x80000000U
2525 /******************* Bit definition for CAN_F11R1 register ******************/
2526 #define CAN_F11R1_FB0 0x00000001U
2527 #define CAN_F11R1_FB1 0x00000002U
2528 #define CAN_F11R1_FB2 0x00000004U
2529 #define CAN_F11R1_FB3 0x00000008U
2530 #define CAN_F11R1_FB4 0x00000010U
2531 #define CAN_F11R1_FB5 0x00000020U
2532 #define CAN_F11R1_FB6 0x00000040U
2533 #define CAN_F11R1_FB7 0x00000080U
2534 #define CAN_F11R1_FB8 0x00000100U
2535 #define CAN_F11R1_FB9 0x00000200U
2536 #define CAN_F11R1_FB10 0x00000400U
2537 #define CAN_F11R1_FB11 0x00000800U
2538 #define CAN_F11R1_FB12 0x00001000U
2539 #define CAN_F11R1_FB13 0x00002000U
2540 #define CAN_F11R1_FB14 0x00004000U
2541 #define CAN_F11R1_FB15 0x00008000U
2542 #define CAN_F11R1_FB16 0x00010000U
2543 #define CAN_F11R1_FB17 0x00020000U
2544 #define CAN_F11R1_FB18 0x00040000U
2545 #define CAN_F11R1_FB19 0x00080000U
2546 #define CAN_F11R1_FB20 0x00100000U
2547 #define CAN_F11R1_FB21 0x00200000U
2548 #define CAN_F11R1_FB22 0x00400000U
2549 #define CAN_F11R1_FB23 0x00800000U
2550 #define CAN_F11R1_FB24 0x01000000U
2551 #define CAN_F11R1_FB25 0x02000000U
2552 #define CAN_F11R1_FB26 0x04000000U
2553 #define CAN_F11R1_FB27 0x08000000U
2554 #define CAN_F11R1_FB28 0x10000000U
2555 #define CAN_F11R1_FB29 0x20000000U
2556 #define CAN_F11R1_FB30 0x40000000U
2557 #define CAN_F11R1_FB31 0x80000000U
2559 /******************* Bit definition for CAN_F12R1 register ******************/
2560 #define CAN_F12R1_FB0 0x00000001U
2561 #define CAN_F12R1_FB1 0x00000002U
2562 #define CAN_F12R1_FB2 0x00000004U
2563 #define CAN_F12R1_FB3 0x00000008U
2564 #define CAN_F12R1_FB4 0x00000010U
2565 #define CAN_F12R1_FB5 0x00000020U
2566 #define CAN_F12R1_FB6 0x00000040U
2567 #define CAN_F12R1_FB7 0x00000080U
2568 #define CAN_F12R1_FB8 0x00000100U
2569 #define CAN_F12R1_FB9 0x00000200U
2570 #define CAN_F12R1_FB10 0x00000400U
2571 #define CAN_F12R1_FB11 0x00000800U
2572 #define CAN_F12R1_FB12 0x00001000U
2573 #define CAN_F12R1_FB13 0x00002000U
2574 #define CAN_F12R1_FB14 0x00004000U
2575 #define CAN_F12R1_FB15 0x00008000U
2576 #define CAN_F12R1_FB16 0x00010000U
2577 #define CAN_F12R1_FB17 0x00020000U
2578 #define CAN_F12R1_FB18 0x00040000U
2579 #define CAN_F12R1_FB19 0x00080000U
2580 #define CAN_F12R1_FB20 0x00100000U
2581 #define CAN_F12R1_FB21 0x00200000U
2582 #define CAN_F12R1_FB22 0x00400000U
2583 #define CAN_F12R1_FB23 0x00800000U
2584 #define CAN_F12R1_FB24 0x01000000U
2585 #define CAN_F12R1_FB25 0x02000000U
2586 #define CAN_F12R1_FB26 0x04000000U
2587 #define CAN_F12R1_FB27 0x08000000U
2588 #define CAN_F12R1_FB28 0x10000000U
2589 #define CAN_F12R1_FB29 0x20000000U
2590 #define CAN_F12R1_FB30 0x40000000U
2591 #define CAN_F12R1_FB31 0x80000000U
2593 /******************* Bit definition for CAN_F13R1 register ******************/
2594 #define CAN_F13R1_FB0 0x00000001U
2595 #define CAN_F13R1_FB1 0x00000002U
2596 #define CAN_F13R1_FB2 0x00000004U
2597 #define CAN_F13R1_FB3 0x00000008U
2598 #define CAN_F13R1_FB4 0x00000010U
2599 #define CAN_F13R1_FB5 0x00000020U
2600 #define CAN_F13R1_FB6 0x00000040U
2601 #define CAN_F13R1_FB7 0x00000080U
2602 #define CAN_F13R1_FB8 0x00000100U
2603 #define CAN_F13R1_FB9 0x00000200U
2604 #define CAN_F13R1_FB10 0x00000400U
2605 #define CAN_F13R1_FB11 0x00000800U
2606 #define CAN_F13R1_FB12 0x00001000U
2607 #define CAN_F13R1_FB13 0x00002000U
2608 #define CAN_F13R1_FB14 0x00004000U
2609 #define CAN_F13R1_FB15 0x00008000U
2610 #define CAN_F13R1_FB16 0x00010000U
2611 #define CAN_F13R1_FB17 0x00020000U
2612 #define CAN_F13R1_FB18 0x00040000U
2613 #define CAN_F13R1_FB19 0x00080000U
2614 #define CAN_F13R1_FB20 0x00100000U
2615 #define CAN_F13R1_FB21 0x00200000U
2616 #define CAN_F13R1_FB22 0x00400000U
2617 #define CAN_F13R1_FB23 0x00800000U
2618 #define CAN_F13R1_FB24 0x01000000U
2619 #define CAN_F13R1_FB25 0x02000000U
2620 #define CAN_F13R1_FB26 0x04000000U
2621 #define CAN_F13R1_FB27 0x08000000U
2622 #define CAN_F13R1_FB28 0x10000000U
2623 #define CAN_F13R1_FB29 0x20000000U
2624 #define CAN_F13R1_FB30 0x40000000U
2625 #define CAN_F13R1_FB31 0x80000000U
2627 /******************* Bit definition for CAN_F0R2 register *******************/
2628 #define CAN_F0R2_FB0 0x00000001U
2629 #define CAN_F0R2_FB1 0x00000002U
2630 #define CAN_F0R2_FB2 0x00000004U
2631 #define CAN_F0R2_FB3 0x00000008U
2632 #define CAN_F0R2_FB4 0x00000010U
2633 #define CAN_F0R2_FB5 0x00000020U
2634 #define CAN_F0R2_FB6 0x00000040U
2635 #define CAN_F0R2_FB7 0x00000080U
2636 #define CAN_F0R2_FB8 0x00000100U
2637 #define CAN_F0R2_FB9 0x00000200U
2638 #define CAN_F0R2_FB10 0x00000400U
2639 #define CAN_F0R2_FB11 0x00000800U
2640 #define CAN_F0R2_FB12 0x00001000U
2641 #define CAN_F0R2_FB13 0x00002000U
2642 #define CAN_F0R2_FB14 0x00004000U
2643 #define CAN_F0R2_FB15 0x00008000U
2644 #define CAN_F0R2_FB16 0x00010000U
2645 #define CAN_F0R2_FB17 0x00020000U
2646 #define CAN_F0R2_FB18 0x00040000U
2647 #define CAN_F0R2_FB19 0x00080000U
2648 #define CAN_F0R2_FB20 0x00100000U
2649 #define CAN_F0R2_FB21 0x00200000U
2650 #define CAN_F0R2_FB22 0x00400000U
2651 #define CAN_F0R2_FB23 0x00800000U
2652 #define CAN_F0R2_FB24 0x01000000U
2653 #define CAN_F0R2_FB25 0x02000000U
2654 #define CAN_F0R2_FB26 0x04000000U
2655 #define CAN_F0R2_FB27 0x08000000U
2656 #define CAN_F0R2_FB28 0x10000000U
2657 #define CAN_F0R2_FB29 0x20000000U
2658 #define CAN_F0R2_FB30 0x40000000U
2659 #define CAN_F0R2_FB31 0x80000000U
2661 /******************* Bit definition for CAN_F1R2 register *******************/
2662 #define CAN_F1R2_FB0 0x00000001U
2663 #define CAN_F1R2_FB1 0x00000002U
2664 #define CAN_F1R2_FB2 0x00000004U
2665 #define CAN_F1R2_FB3 0x00000008U
2666 #define CAN_F1R2_FB4 0x00000010U
2667 #define CAN_F1R2_FB5 0x00000020U
2668 #define CAN_F1R2_FB6 0x00000040U
2669 #define CAN_F1R2_FB7 0x00000080U
2670 #define CAN_F1R2_FB8 0x00000100U
2671 #define CAN_F1R2_FB9 0x00000200U
2672 #define CAN_F1R2_FB10 0x00000400U
2673 #define CAN_F1R2_FB11 0x00000800U
2674 #define CAN_F1R2_FB12 0x00001000U
2675 #define CAN_F1R2_FB13 0x00002000U
2676 #define CAN_F1R2_FB14 0x00004000U
2677 #define CAN_F1R2_FB15 0x00008000U
2678 #define CAN_F1R2_FB16 0x00010000U
2679 #define CAN_F1R2_FB17 0x00020000U
2680 #define CAN_F1R2_FB18 0x00040000U
2681 #define CAN_F1R2_FB19 0x00080000U
2682 #define CAN_F1R2_FB20 0x00100000U
2683 #define CAN_F1R2_FB21 0x00200000U
2684 #define CAN_F1R2_FB22 0x00400000U
2685 #define CAN_F1R2_FB23 0x00800000U
2686 #define CAN_F1R2_FB24 0x01000000U
2687 #define CAN_F1R2_FB25 0x02000000U
2688 #define CAN_F1R2_FB26 0x04000000U
2689 #define CAN_F1R2_FB27 0x08000000U
2690 #define CAN_F1R2_FB28 0x10000000U
2691 #define CAN_F1R2_FB29 0x20000000U
2692 #define CAN_F1R2_FB30 0x40000000U
2693 #define CAN_F1R2_FB31 0x80000000U
2695 /******************* Bit definition for CAN_F2R2 register *******************/
2696 #define CAN_F2R2_FB0 0x00000001U
2697 #define CAN_F2R2_FB1 0x00000002U
2698 #define CAN_F2R2_FB2 0x00000004U
2699 #define CAN_F2R2_FB3 0x00000008U
2700 #define CAN_F2R2_FB4 0x00000010U
2701 #define CAN_F2R2_FB5 0x00000020U
2702 #define CAN_F2R2_FB6 0x00000040U
2703 #define CAN_F2R2_FB7 0x00000080U
2704 #define CAN_F2R2_FB8 0x00000100U
2705 #define CAN_F2R2_FB9 0x00000200U
2706 #define CAN_F2R2_FB10 0x00000400U
2707 #define CAN_F2R2_FB11 0x00000800U
2708 #define CAN_F2R2_FB12 0x00001000U
2709 #define CAN_F2R2_FB13 0x00002000U
2710 #define CAN_F2R2_FB14 0x00004000U
2711 #define CAN_F2R2_FB15 0x00008000U
2712 #define CAN_F2R2_FB16 0x00010000U
2713 #define CAN_F2R2_FB17 0x00020000U
2714 #define CAN_F2R2_FB18 0x00040000U
2715 #define CAN_F2R2_FB19 0x00080000U
2716 #define CAN_F2R2_FB20 0x00100000U
2717 #define CAN_F2R2_FB21 0x00200000U
2718 #define CAN_F2R2_FB22 0x00400000U
2719 #define CAN_F2R2_FB23 0x00800000U
2720 #define CAN_F2R2_FB24 0x01000000U
2721 #define CAN_F2R2_FB25 0x02000000U
2722 #define CAN_F2R2_FB26 0x04000000U
2723 #define CAN_F2R2_FB27 0x08000000U
2724 #define CAN_F2R2_FB28 0x10000000U
2725 #define CAN_F2R2_FB29 0x20000000U
2726 #define CAN_F2R2_FB30 0x40000000U
2727 #define CAN_F2R2_FB31 0x80000000U
2729 /******************* Bit definition for CAN_F3R2 register *******************/
2730 #define CAN_F3R2_FB0 0x00000001U
2731 #define CAN_F3R2_FB1 0x00000002U
2732 #define CAN_F3R2_FB2 0x00000004U
2733 #define CAN_F3R2_FB3 0x00000008U
2734 #define CAN_F3R2_FB4 0x00000010U
2735 #define CAN_F3R2_FB5 0x00000020U
2736 #define CAN_F3R2_FB6 0x00000040U
2737 #define CAN_F3R2_FB7 0x00000080U
2738 #define CAN_F3R2_FB8 0x00000100U
2739 #define CAN_F3R2_FB9 0x00000200U
2740 #define CAN_F3R2_FB10 0x00000400U
2741 #define CAN_F3R2_FB11 0x00000800U
2742 #define CAN_F3R2_FB12 0x00001000U
2743 #define CAN_F3R2_FB13 0x00002000U
2744 #define CAN_F3R2_FB14 0x00004000U
2745 #define CAN_F3R2_FB15 0x00008000U
2746 #define CAN_F3R2_FB16 0x00010000U
2747 #define CAN_F3R2_FB17 0x00020000U
2748 #define CAN_F3R2_FB18 0x00040000U
2749 #define CAN_F3R2_FB19 0x00080000U
2750 #define CAN_F3R2_FB20 0x00100000U
2751 #define CAN_F3R2_FB21 0x00200000U
2752 #define CAN_F3R2_FB22 0x00400000U
2753 #define CAN_F3R2_FB23 0x00800000U
2754 #define CAN_F3R2_FB24 0x01000000U
2755 #define CAN_F3R2_FB25 0x02000000U
2756 #define CAN_F3R2_FB26 0x04000000U
2757 #define CAN_F3R2_FB27 0x08000000U
2758 #define CAN_F3R2_FB28 0x10000000U
2759 #define CAN_F3R2_FB29 0x20000000U
2760 #define CAN_F3R2_FB30 0x40000000U
2761 #define CAN_F3R2_FB31 0x80000000U
2763 /******************* Bit definition for CAN_F4R2 register *******************/
2764 #define CAN_F4R2_FB0 0x00000001U
2765 #define CAN_F4R2_FB1 0x00000002U
2766 #define CAN_F4R2_FB2 0x00000004U
2767 #define CAN_F4R2_FB3 0x00000008U
2768 #define CAN_F4R2_FB4 0x00000010U
2769 #define CAN_F4R2_FB5 0x00000020U
2770 #define CAN_F4R2_FB6 0x00000040U
2771 #define CAN_F4R2_FB7 0x00000080U
2772 #define CAN_F4R2_FB8 0x00000100U
2773 #define CAN_F4R2_FB9 0x00000200U
2774 #define CAN_F4R2_FB10 0x00000400U
2775 #define CAN_F4R2_FB11 0x00000800U
2776 #define CAN_F4R2_FB12 0x00001000U
2777 #define CAN_F4R2_FB13 0x00002000U
2778 #define CAN_F4R2_FB14 0x00004000U
2779 #define CAN_F4R2_FB15 0x00008000U
2780 #define CAN_F4R2_FB16 0x00010000U
2781 #define CAN_F4R2_FB17 0x00020000U
2782 #define CAN_F4R2_FB18 0x00040000U
2783 #define CAN_F4R2_FB19 0x00080000U
2784 #define CAN_F4R2_FB20 0x00100000U
2785 #define CAN_F4R2_FB21 0x00200000U
2786 #define CAN_F4R2_FB22 0x00400000U
2787 #define CAN_F4R2_FB23 0x00800000U
2788 #define CAN_F4R2_FB24 0x01000000U
2789 #define CAN_F4R2_FB25 0x02000000U
2790 #define CAN_F4R2_FB26 0x04000000U
2791 #define CAN_F4R2_FB27 0x08000000U
2792 #define CAN_F4R2_FB28 0x10000000U
2793 #define CAN_F4R2_FB29 0x20000000U
2794 #define CAN_F4R2_FB30 0x40000000U
2795 #define CAN_F4R2_FB31 0x80000000U
2797 /******************* Bit definition for CAN_F5R2 register *******************/
2798 #define CAN_F5R2_FB0 0x00000001U
2799 #define CAN_F5R2_FB1 0x00000002U
2800 #define CAN_F5R2_FB2 0x00000004U
2801 #define CAN_F5R2_FB3 0x00000008U
2802 #define CAN_F5R2_FB4 0x00000010U
2803 #define CAN_F5R2_FB5 0x00000020U
2804 #define CAN_F5R2_FB6 0x00000040U
2805 #define CAN_F5R2_FB7 0x00000080U
2806 #define CAN_F5R2_FB8 0x00000100U
2807 #define CAN_F5R2_FB9 0x00000200U
2808 #define CAN_F5R2_FB10 0x00000400U
2809 #define CAN_F5R2_FB11 0x00000800U
2810 #define CAN_F5R2_FB12 0x00001000U
2811 #define CAN_F5R2_FB13 0x00002000U
2812 #define CAN_F5R2_FB14 0x00004000U
2813 #define CAN_F5R2_FB15 0x00008000U
2814 #define CAN_F5R2_FB16 0x00010000U
2815 #define CAN_F5R2_FB17 0x00020000U
2816 #define CAN_F5R2_FB18 0x00040000U
2817 #define CAN_F5R2_FB19 0x00080000U
2818 #define CAN_F5R2_FB20 0x00100000U
2819 #define CAN_F5R2_FB21 0x00200000U
2820 #define CAN_F5R2_FB22 0x00400000U
2821 #define CAN_F5R2_FB23 0x00800000U
2822 #define CAN_F5R2_FB24 0x01000000U
2823 #define CAN_F5R2_FB25 0x02000000U
2824 #define CAN_F5R2_FB26 0x04000000U
2825 #define CAN_F5R2_FB27 0x08000000U
2826 #define CAN_F5R2_FB28 0x10000000U
2827 #define CAN_F5R2_FB29 0x20000000U
2828 #define CAN_F5R2_FB30 0x40000000U
2829 #define CAN_F5R2_FB31 0x80000000U
2831 /******************* Bit definition for CAN_F6R2 register *******************/
2832 #define CAN_F6R2_FB0 0x00000001U
2833 #define CAN_F6R2_FB1 0x00000002U
2834 #define CAN_F6R2_FB2 0x00000004U
2835 #define CAN_F6R2_FB3 0x00000008U
2836 #define CAN_F6R2_FB4 0x00000010U
2837 #define CAN_F6R2_FB5 0x00000020U
2838 #define CAN_F6R2_FB6 0x00000040U
2839 #define CAN_F6R2_FB7 0x00000080U
2840 #define CAN_F6R2_FB8 0x00000100U
2841 #define CAN_F6R2_FB9 0x00000200U
2842 #define CAN_F6R2_FB10 0x00000400U
2843 #define CAN_F6R2_FB11 0x00000800U
2844 #define CAN_F6R2_FB12 0x00001000U
2845 #define CAN_F6R2_FB13 0x00002000U
2846 #define CAN_F6R2_FB14 0x00004000U
2847 #define CAN_F6R2_FB15 0x00008000U
2848 #define CAN_F6R2_FB16 0x00010000U
2849 #define CAN_F6R2_FB17 0x00020000U
2850 #define CAN_F6R2_FB18 0x00040000U
2851 #define CAN_F6R2_FB19 0x00080000U
2852 #define CAN_F6R2_FB20 0x00100000U
2853 #define CAN_F6R2_FB21 0x00200000U
2854 #define CAN_F6R2_FB22 0x00400000U
2855 #define CAN_F6R2_FB23 0x00800000U
2856 #define CAN_F6R2_FB24 0x01000000U
2857 #define CAN_F6R2_FB25 0x02000000U
2858 #define CAN_F6R2_FB26 0x04000000U
2859 #define CAN_F6R2_FB27 0x08000000U
2860 #define CAN_F6R2_FB28 0x10000000U
2861 #define CAN_F6R2_FB29 0x20000000U
2862 #define CAN_F6R2_FB30 0x40000000U
2863 #define CAN_F6R2_FB31 0x80000000U
2865 /******************* Bit definition for CAN_F7R2 register *******************/
2866 #define CAN_F7R2_FB0 0x00000001U
2867 #define CAN_F7R2_FB1 0x00000002U
2868 #define CAN_F7R2_FB2 0x00000004U
2869 #define CAN_F7R2_FB3 0x00000008U
2870 #define CAN_F7R2_FB4 0x00000010U
2871 #define CAN_F7R2_FB5 0x00000020U
2872 #define CAN_F7R2_FB6 0x00000040U
2873 #define CAN_F7R2_FB7 0x00000080U
2874 #define CAN_F7R2_FB8 0x00000100U
2875 #define CAN_F7R2_FB9 0x00000200U
2876 #define CAN_F7R2_FB10 0x00000400U
2877 #define CAN_F7R2_FB11 0x00000800U
2878 #define CAN_F7R2_FB12 0x00001000U
2879 #define CAN_F7R2_FB13 0x00002000U
2880 #define CAN_F7R2_FB14 0x00004000U
2881 #define CAN_F7R2_FB15 0x00008000U
2882 #define CAN_F7R2_FB16 0x00010000U
2883 #define CAN_F7R2_FB17 0x00020000U
2884 #define CAN_F7R2_FB18 0x00040000U
2885 #define CAN_F7R2_FB19 0x00080000U
2886 #define CAN_F7R2_FB20 0x00100000U
2887 #define CAN_F7R2_FB21 0x00200000U
2888 #define CAN_F7R2_FB22 0x00400000U
2889 #define CAN_F7R2_FB23 0x00800000U
2890 #define CAN_F7R2_FB24 0x01000000U
2891 #define CAN_F7R2_FB25 0x02000000U
2892 #define CAN_F7R2_FB26 0x04000000U
2893 #define CAN_F7R2_FB27 0x08000000U
2894 #define CAN_F7R2_FB28 0x10000000U
2895 #define CAN_F7R2_FB29 0x20000000U
2896 #define CAN_F7R2_FB30 0x40000000U
2897 #define CAN_F7R2_FB31 0x80000000U
2899 /******************* Bit definition for CAN_F8R2 register *******************/
2900 #define CAN_F8R2_FB0 0x00000001U
2901 #define CAN_F8R2_FB1 0x00000002U
2902 #define CAN_F8R2_FB2 0x00000004U
2903 #define CAN_F8R2_FB3 0x00000008U
2904 #define CAN_F8R2_FB4 0x00000010U
2905 #define CAN_F8R2_FB5 0x00000020U
2906 #define CAN_F8R2_FB6 0x00000040U
2907 #define CAN_F8R2_FB7 0x00000080U
2908 #define CAN_F8R2_FB8 0x00000100U
2909 #define CAN_F8R2_FB9 0x00000200U
2910 #define CAN_F8R2_FB10 0x00000400U
2911 #define CAN_F8R2_FB11 0x00000800U
2912 #define CAN_F8R2_FB12 0x00001000U
2913 #define CAN_F8R2_FB13 0x00002000U
2914 #define CAN_F8R2_FB14 0x00004000U
2915 #define CAN_F8R2_FB15 0x00008000U
2916 #define CAN_F8R2_FB16 0x00010000U
2917 #define CAN_F8R2_FB17 0x00020000U
2918 #define CAN_F8R2_FB18 0x00040000U
2919 #define CAN_F8R2_FB19 0x00080000U
2920 #define CAN_F8R2_FB20 0x00100000U
2921 #define CAN_F8R2_FB21 0x00200000U
2922 #define CAN_F8R2_FB22 0x00400000U
2923 #define CAN_F8R2_FB23 0x00800000U
2924 #define CAN_F8R2_FB24 0x01000000U
2925 #define CAN_F8R2_FB25 0x02000000U
2926 #define CAN_F8R2_FB26 0x04000000U
2927 #define CAN_F8R2_FB27 0x08000000U
2928 #define CAN_F8R2_FB28 0x10000000U
2929 #define CAN_F8R2_FB29 0x20000000U
2930 #define CAN_F8R2_FB30 0x40000000U
2931 #define CAN_F8R2_FB31 0x80000000U
2933 /******************* Bit definition for CAN_F9R2 register *******************/
2934 #define CAN_F9R2_FB0 0x00000001U
2935 #define CAN_F9R2_FB1 0x00000002U
2936 #define CAN_F9R2_FB2 0x00000004U
2937 #define CAN_F9R2_FB3 0x00000008U
2938 #define CAN_F9R2_FB4 0x00000010U
2939 #define CAN_F9R2_FB5 0x00000020U
2940 #define CAN_F9R2_FB6 0x00000040U
2941 #define CAN_F9R2_FB7 0x00000080U
2942 #define CAN_F9R2_FB8 0x00000100U
2943 #define CAN_F9R2_FB9 0x00000200U
2944 #define CAN_F9R2_FB10 0x00000400U
2945 #define CAN_F9R2_FB11 0x00000800U
2946 #define CAN_F9R2_FB12 0x00001000U
2947 #define CAN_F9R2_FB13 0x00002000U
2948 #define CAN_F9R2_FB14 0x00004000U
2949 #define CAN_F9R2_FB15 0x00008000U
2950 #define CAN_F9R2_FB16 0x00010000U
2951 #define CAN_F9R2_FB17 0x00020000U
2952 #define CAN_F9R2_FB18 0x00040000U
2953 #define CAN_F9R2_FB19 0x00080000U
2954 #define CAN_F9R2_FB20 0x00100000U
2955 #define CAN_F9R2_FB21 0x00200000U
2956 #define CAN_F9R2_FB22 0x00400000U
2957 #define CAN_F9R2_FB23 0x00800000U
2958 #define CAN_F9R2_FB24 0x01000000U
2959 #define CAN_F9R2_FB25 0x02000000U
2960 #define CAN_F9R2_FB26 0x04000000U
2961 #define CAN_F9R2_FB27 0x08000000U
2962 #define CAN_F9R2_FB28 0x10000000U
2963 #define CAN_F9R2_FB29 0x20000000U
2964 #define CAN_F9R2_FB30 0x40000000U
2965 #define CAN_F9R2_FB31 0x80000000U
2967 /******************* Bit definition for CAN_F10R2 register ******************/
2968 #define CAN_F10R2_FB0 0x00000001U
2969 #define CAN_F10R2_FB1 0x00000002U
2970 #define CAN_F10R2_FB2 0x00000004U
2971 #define CAN_F10R2_FB3 0x00000008U
2972 #define CAN_F10R2_FB4 0x00000010U
2973 #define CAN_F10R2_FB5 0x00000020U
2974 #define CAN_F10R2_FB6 0x00000040U
2975 #define CAN_F10R2_FB7 0x00000080U
2976 #define CAN_F10R2_FB8 0x00000100U
2977 #define CAN_F10R2_FB9 0x00000200U
2978 #define CAN_F10R2_FB10 0x00000400U
2979 #define CAN_F10R2_FB11 0x00000800U
2980 #define CAN_F10R2_FB12 0x00001000U
2981 #define CAN_F10R2_FB13 0x00002000U
2982 #define CAN_F10R2_FB14 0x00004000U
2983 #define CAN_F10R2_FB15 0x00008000U
2984 #define CAN_F10R2_FB16 0x00010000U
2985 #define CAN_F10R2_FB17 0x00020000U
2986 #define CAN_F10R2_FB18 0x00040000U
2987 #define CAN_F10R2_FB19 0x00080000U
2988 #define CAN_F10R2_FB20 0x00100000U
2989 #define CAN_F10R2_FB21 0x00200000U
2990 #define CAN_F10R2_FB22 0x00400000U
2991 #define CAN_F10R2_FB23 0x00800000U
2992 #define CAN_F10R2_FB24 0x01000000U
2993 #define CAN_F10R2_FB25 0x02000000U
2994 #define CAN_F10R2_FB26 0x04000000U
2995 #define CAN_F10R2_FB27 0x08000000U
2996 #define CAN_F10R2_FB28 0x10000000U
2997 #define CAN_F10R2_FB29 0x20000000U
2998 #define CAN_F10R2_FB30 0x40000000U
2999 #define CAN_F10R2_FB31 0x80000000U
3001 /******************* Bit definition for CAN_F11R2 register ******************/
3002 #define CAN_F11R2_FB0 0x00000001U
3003 #define CAN_F11R2_FB1 0x00000002U
3004 #define CAN_F11R2_FB2 0x00000004U
3005 #define CAN_F11R2_FB3 0x00000008U
3006 #define CAN_F11R2_FB4 0x00000010U
3007 #define CAN_F11R2_FB5 0x00000020U
3008 #define CAN_F11R2_FB6 0x00000040U
3009 #define CAN_F11R2_FB7 0x00000080U
3010 #define CAN_F11R2_FB8 0x00000100U
3011 #define CAN_F11R2_FB9 0x00000200U
3012 #define CAN_F11R2_FB10 0x00000400U
3013 #define CAN_F11R2_FB11 0x00000800U
3014 #define CAN_F11R2_FB12 0x00001000U
3015 #define CAN_F11R2_FB13 0x00002000U
3016 #define CAN_F11R2_FB14 0x00004000U
3017 #define CAN_F11R2_FB15 0x00008000U
3018 #define CAN_F11R2_FB16 0x00010000U
3019 #define CAN_F11R2_FB17 0x00020000U
3020 #define CAN_F11R2_FB18 0x00040000U
3021 #define CAN_F11R2_FB19 0x00080000U
3022 #define CAN_F11R2_FB20 0x00100000U
3023 #define CAN_F11R2_FB21 0x00200000U
3024 #define CAN_F11R2_FB22 0x00400000U
3025 #define CAN_F11R2_FB23 0x00800000U
3026 #define CAN_F11R2_FB24 0x01000000U
3027 #define CAN_F11R2_FB25 0x02000000U
3028 #define CAN_F11R2_FB26 0x04000000U
3029 #define CAN_F11R2_FB27 0x08000000U
3030 #define CAN_F11R2_FB28 0x10000000U
3031 #define CAN_F11R2_FB29 0x20000000U
3032 #define CAN_F11R2_FB30 0x40000000U
3033 #define CAN_F11R2_FB31 0x80000000U
3035 /******************* Bit definition for CAN_F12R2 register ******************/
3036 #define CAN_F12R2_FB0 0x00000001U
3037 #define CAN_F12R2_FB1 0x00000002U
3038 #define CAN_F12R2_FB2 0x00000004U
3039 #define CAN_F12R2_FB3 0x00000008U
3040 #define CAN_F12R2_FB4 0x00000010U
3041 #define CAN_F12R2_FB5 0x00000020U
3042 #define CAN_F12R2_FB6 0x00000040U
3043 #define CAN_F12R2_FB7 0x00000080U
3044 #define CAN_F12R2_FB8 0x00000100U
3045 #define CAN_F12R2_FB9 0x00000200U
3046 #define CAN_F12R2_FB10 0x00000400U
3047 #define CAN_F12R2_FB11 0x00000800U
3048 #define CAN_F12R2_FB12 0x00001000U
3049 #define CAN_F12R2_FB13 0x00002000U
3050 #define CAN_F12R2_FB14 0x00004000U
3051 #define CAN_F12R2_FB15 0x00008000U
3052 #define CAN_F12R2_FB16 0x00010000U
3053 #define CAN_F12R2_FB17 0x00020000U
3054 #define CAN_F12R2_FB18 0x00040000U
3055 #define CAN_F12R2_FB19 0x00080000U
3056 #define CAN_F12R2_FB20 0x00100000U
3057 #define CAN_F12R2_FB21 0x00200000U
3058 #define CAN_F12R2_FB22 0x00400000U
3059 #define CAN_F12R2_FB23 0x00800000U
3060 #define CAN_F12R2_FB24 0x01000000U
3061 #define CAN_F12R2_FB25 0x02000000U
3062 #define CAN_F12R2_FB26 0x04000000U
3063 #define CAN_F12R2_FB27 0x08000000U
3064 #define CAN_F12R2_FB28 0x10000000U
3065 #define CAN_F12R2_FB29 0x20000000U
3066 #define CAN_F12R2_FB30 0x40000000U
3067 #define CAN_F12R2_FB31 0x80000000U
3069 /******************* Bit definition for CAN_F13R2 register ******************/
3070 #define CAN_F13R2_FB0 0x00000001U
3071 #define CAN_F13R2_FB1 0x00000002U
3072 #define CAN_F13R2_FB2 0x00000004U
3073 #define CAN_F13R2_FB3 0x00000008U
3074 #define CAN_F13R2_FB4 0x00000010U
3075 #define CAN_F13R2_FB5 0x00000020U
3076 #define CAN_F13R2_FB6 0x00000040U
3077 #define CAN_F13R2_FB7 0x00000080U
3078 #define CAN_F13R2_FB8 0x00000100U
3079 #define CAN_F13R2_FB9 0x00000200U
3080 #define CAN_F13R2_FB10 0x00000400U
3081 #define CAN_F13R2_FB11 0x00000800U
3082 #define CAN_F13R2_FB12 0x00001000U
3083 #define CAN_F13R2_FB13 0x00002000U
3084 #define CAN_F13R2_FB14 0x00004000U
3085 #define CAN_F13R2_FB15 0x00008000U
3086 #define CAN_F13R2_FB16 0x00010000U
3087 #define CAN_F13R2_FB17 0x00020000U
3088 #define CAN_F13R2_FB18 0x00040000U
3089 #define CAN_F13R2_FB19 0x00080000U
3090 #define CAN_F13R2_FB20 0x00100000U
3091 #define CAN_F13R2_FB21 0x00200000U
3092 #define CAN_F13R2_FB22 0x00400000U
3093 #define CAN_F13R2_FB23 0x00800000U
3094 #define CAN_F13R2_FB24 0x01000000U
3095 #define CAN_F13R2_FB25 0x02000000U
3096 #define CAN_F13R2_FB26 0x04000000U
3097 #define CAN_F13R2_FB27 0x08000000U
3098 #define CAN_F13R2_FB28 0x10000000U
3099 #define CAN_F13R2_FB29 0x20000000U
3100 #define CAN_F13R2_FB30 0x40000000U
3101 #define CAN_F13R2_FB31 0x80000000U
3103 /******************************************************************************/
3104 /* */
3105 /* CRC calculation unit */
3106 /* */
3107 /******************************************************************************/
3108 /******************* Bit definition for CRC_DR register *********************/
3109 #define CRC_DR_DR 0xFFFFFFFFU
3112 /******************* Bit definition for CRC_IDR register ********************/
3113 #define CRC_IDR_IDR 0xFFU
3116 /******************** Bit definition for CRC_CR register ********************/
3117 #define CRC_CR_RESET 0x01U
3120 /******************************************************************************/
3121 /* */
3122 /* Digital to Analog Converter */
3123 /* */
3124 /******************************************************************************/
3125 /******************** Bit definition for DAC_CR register ********************/
3126 #define DAC_CR_EN1 0x00000001U
3127 #define DAC_CR_BOFF1 0x00000002U
3128 #define DAC_CR_TEN1 0x00000004U
3130 #define DAC_CR_TSEL1 0x00000038U
3131 #define DAC_CR_TSEL1_0 0x00000008U
3132 #define DAC_CR_TSEL1_1 0x00000010U
3133 #define DAC_CR_TSEL1_2 0x00000020U
3135 #define DAC_CR_WAVE1 0x000000C0U
3136 #define DAC_CR_WAVE1_0 0x00000040U
3137 #define DAC_CR_WAVE1_1 0x00000080U
3139 #define DAC_CR_MAMP1 0x00000F00U
3140 #define DAC_CR_MAMP1_0 0x00000100U
3141 #define DAC_CR_MAMP1_1 0x00000200U
3142 #define DAC_CR_MAMP1_2 0x00000400U
3143 #define DAC_CR_MAMP1_3 0x00000800U
3145 #define DAC_CR_DMAEN1 0x00001000U
3146 #define DAC_CR_DMAUDRIE1 0x00002000U
3147 #define DAC_CR_EN2 0x00010000U
3148 #define DAC_CR_BOFF2 0x00020000U
3149 #define DAC_CR_TEN2 0x00040000U
3151 #define DAC_CR_TSEL2 0x00380000U
3152 #define DAC_CR_TSEL2_0 0x00080000U
3153 #define DAC_CR_TSEL2_1 0x00100000U
3154 #define DAC_CR_TSEL2_2 0x00200000U
3156 #define DAC_CR_WAVE2 0x00C00000U
3157 #define DAC_CR_WAVE2_0 0x00400000U
3158 #define DAC_CR_WAVE2_1 0x00800000U
3160 #define DAC_CR_MAMP2 0x0F000000U
3161 #define DAC_CR_MAMP2_0 0x01000000U
3162 #define DAC_CR_MAMP2_1 0x02000000U
3163 #define DAC_CR_MAMP2_2 0x04000000U
3164 #define DAC_CR_MAMP2_3 0x08000000U
3166 #define DAC_CR_DMAEN2 0x10000000U
3167 #define DAC_CR_DMAUDRIE2 0x20000000U
3169 /***************** Bit definition for DAC_SWTRIGR register ******************/
3170 #define DAC_SWTRIGR_SWTRIG1 0x01U
3171 #define DAC_SWTRIGR_SWTRIG2 0x02U
3173 /***************** Bit definition for DAC_DHR12R1 register ******************/
3174 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3176 /***************** Bit definition for DAC_DHR12L1 register ******************/
3177 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3179 /****************** Bit definition for DAC_DHR8R1 register ******************/
3180 #define DAC_DHR8R1_DACC1DHR 0xFFU
3182 /***************** Bit definition for DAC_DHR12R2 register ******************/
3183 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3185 /***************** Bit definition for DAC_DHR12L2 register ******************/
3186 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3188 /****************** Bit definition for DAC_DHR8R2 register ******************/
3189 #define DAC_DHR8R2_DACC2DHR 0xFFU
3191 /***************** Bit definition for DAC_DHR12RD register ******************/
3192 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3193 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3195 /***************** Bit definition for DAC_DHR12LD register ******************/
3196 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3197 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3199 /****************** Bit definition for DAC_DHR8RD register ******************/
3200 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3201 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3203 /******************* Bit definition for DAC_DOR1 register *******************/
3204 #define DAC_DOR1_DACC1DOR 0x0FFFU
3206 /******************* Bit definition for DAC_DOR2 register *******************/
3207 #define DAC_DOR2_DACC2DOR 0x0FFFU
3209 /******************** Bit definition for DAC_SR register ********************/
3210 #define DAC_SR_DMAUDR1 0x00002000U
3211 #define DAC_SR_DMAUDR2 0x20000000U
3213 /******************************************************************************/
3214 /* */
3215 /* Debug MCU */
3216 /* */
3217 /******************************************************************************/
3218 
3219 /******************************************************************************/
3220 /* */
3221 /* DCMI */
3222 /* */
3223 /******************************************************************************/
3224 /******************** Bits definition for DCMI_CR register ******************/
3225 #define DCMI_CR_CAPTURE 0x00000001U
3226 #define DCMI_CR_CM 0x00000002U
3227 #define DCMI_CR_CROP 0x00000004U
3228 #define DCMI_CR_JPEG 0x00000008U
3229 #define DCMI_CR_ESS 0x00000010U
3230 #define DCMI_CR_PCKPOL 0x00000020U
3231 #define DCMI_CR_HSPOL 0x00000040U
3232 #define DCMI_CR_VSPOL 0x00000080U
3233 #define DCMI_CR_FCRC_0 0x00000100U
3234 #define DCMI_CR_FCRC_1 0x00000200U
3235 #define DCMI_CR_EDM_0 0x00000400U
3236 #define DCMI_CR_EDM_1 0x00000800U
3237 #define DCMI_CR_OUTEN 0x00002000U
3238 #define DCMI_CR_ENABLE 0x00004000U
3239 #define DCMI_CR_BSM_0 0x00010000U
3240 #define DCMI_CR_BSM_1 0x00020000U
3241 #define DCMI_CR_OEBS 0x00040000U
3242 #define DCMI_CR_LSM 0x00080000U
3243 #define DCMI_CR_OELS 0x00100000U
3244 
3245 /******************** Bits definition for DCMI_SR register ******************/
3246 #define DCMI_SR_HSYNC 0x00000001U
3247 #define DCMI_SR_VSYNC 0x00000002U
3248 #define DCMI_SR_FNE 0x00000004U
3249 
3250 /******************** Bits definition for DCMI_RIS register *****************/
3251 #define DCMI_RIS_FRAME_RIS 0x00000001U
3252 #define DCMI_RIS_OVR_RIS 0x00000002U
3253 #define DCMI_RIS_ERR_RIS 0x00000004U
3254 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3255 #define DCMI_RIS_LINE_RIS 0x00000010U
3256 /* Legacy defines */
3257 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3258 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
3259 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3260 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3261 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3262 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3263 
3264 /******************** Bits definition for DCMI_IER register *****************/
3265 #define DCMI_IER_FRAME_IE 0x00000001U
3266 #define DCMI_IER_OVR_IE 0x00000002U
3267 #define DCMI_IER_ERR_IE 0x00000004U
3268 #define DCMI_IER_VSYNC_IE 0x00000008U
3269 #define DCMI_IER_LINE_IE 0x00000010U
3270 /* Legacy defines */
3271 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3272 /******************** Bits definition for DCMI_MIS register *****************/
3273 #define DCMI_MIS_FRAME_MIS 0x00000001U
3274 #define DCMI_MIS_OVR_MIS 0x00000002U
3275 #define DCMI_MIS_ERR_MIS 0x00000004U
3276 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3277 #define DCMI_MIS_LINE_MIS 0x00000010U
3278 
3279 /* Legacy defines */
3280 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3281 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3282 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3283 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3284 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3285 
3286 /******************** Bits definition for DCMI_ICR register *****************/
3287 #define DCMI_ICR_FRAME_ISC 0x00000001U
3288 #define DCMI_ICR_OVR_ISC 0x00000002U
3289 #define DCMI_ICR_ERR_ISC 0x00000004U
3290 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3291 #define DCMI_ICR_LINE_ISC 0x00000010U
3292 
3293 /* Legacy defines */
3294 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3295 
3296 /******************** Bits definition for DCMI_ESCR register ******************/
3297 #define DCMI_ESCR_FSC 0x000000FFU
3298 #define DCMI_ESCR_LSC 0x0000FF00U
3299 #define DCMI_ESCR_LEC 0x00FF0000U
3300 #define DCMI_ESCR_FEC 0xFF000000U
3301 
3302 /******************** Bits definition for DCMI_ESUR register ******************/
3303 #define DCMI_ESUR_FSU 0x000000FFU
3304 #define DCMI_ESUR_LSU 0x0000FF00U
3305 #define DCMI_ESUR_LEU 0x00FF0000U
3306 #define DCMI_ESUR_FEU 0xFF000000U
3307 
3308 /******************** Bits definition for DCMI_CWSTRT register ******************/
3309 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3310 #define DCMI_CWSTRT_VST 0x1FFF0000U
3311 
3312 /******************** Bits definition for DCMI_CWSIZE register ******************/
3313 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3314 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3315 
3316 /******************** Bits definition for DCMI_DR register ******************/
3317 #define DCMI_DR_BYTE0 0x000000FFU
3318 #define DCMI_DR_BYTE1 0x0000FF00U
3319 #define DCMI_DR_BYTE2 0x00FF0000U
3320 #define DCMI_DR_BYTE3 0xFF000000U
3321 
3322 /******************************************************************************/
3323 /* */
3324 /* DMA Controller */
3325 /* */
3326 /******************************************************************************/
3327 /******************** Bits definition for DMA_SxCR register *****************/
3328 #define DMA_SxCR_CHSEL 0x0E000000U
3329 #define DMA_SxCR_CHSEL_0 0x02000000U
3330 #define DMA_SxCR_CHSEL_1 0x04000000U
3331 #define DMA_SxCR_CHSEL_2 0x08000000U
3332 #define DMA_SxCR_MBURST 0x01800000U
3333 #define DMA_SxCR_MBURST_0 0x00800000U
3334 #define DMA_SxCR_MBURST_1 0x01000000U
3335 #define DMA_SxCR_PBURST 0x00600000U
3336 #define DMA_SxCR_PBURST_0 0x00200000U
3337 #define DMA_SxCR_PBURST_1 0x00400000U
3338 #define DMA_SxCR_CT 0x00080000U
3339 #define DMA_SxCR_DBM 0x00040000U
3340 #define DMA_SxCR_PL 0x00030000U
3341 #define DMA_SxCR_PL_0 0x00010000U
3342 #define DMA_SxCR_PL_1 0x00020000U
3343 #define DMA_SxCR_PINCOS 0x00008000U
3344 #define DMA_SxCR_MSIZE 0x00006000U
3345 #define DMA_SxCR_MSIZE_0 0x00002000U
3346 #define DMA_SxCR_MSIZE_1 0x00004000U
3347 #define DMA_SxCR_PSIZE 0x00001800U
3348 #define DMA_SxCR_PSIZE_0 0x00000800U
3349 #define DMA_SxCR_PSIZE_1 0x00001000U
3350 #define DMA_SxCR_MINC 0x00000400U
3351 #define DMA_SxCR_PINC 0x00000200U
3352 #define DMA_SxCR_CIRC 0x00000100U
3353 #define DMA_SxCR_DIR 0x000000C0U
3354 #define DMA_SxCR_DIR_0 0x00000040U
3355 #define DMA_SxCR_DIR_1 0x00000080U
3356 #define DMA_SxCR_PFCTRL 0x00000020U
3357 #define DMA_SxCR_TCIE 0x00000010U
3358 #define DMA_SxCR_HTIE 0x00000008U
3359 #define DMA_SxCR_TEIE 0x00000004U
3360 #define DMA_SxCR_DMEIE 0x00000002U
3361 #define DMA_SxCR_EN 0x00000001U
3362 
3363 /* Legacy defines */
3364 #define DMA_SxCR_ACK 0x00100000U
3365 
3366 /******************** Bits definition for DMA_SxCNDTR register **************/
3367 #define DMA_SxNDT 0x0000FFFFU
3368 #define DMA_SxNDT_0 0x00000001U
3369 #define DMA_SxNDT_1 0x00000002U
3370 #define DMA_SxNDT_2 0x00000004U
3371 #define DMA_SxNDT_3 0x00000008U
3372 #define DMA_SxNDT_4 0x00000010U
3373 #define DMA_SxNDT_5 0x00000020U
3374 #define DMA_SxNDT_6 0x00000040U
3375 #define DMA_SxNDT_7 0x00000080U
3376 #define DMA_SxNDT_8 0x00000100U
3377 #define DMA_SxNDT_9 0x00000200U
3378 #define DMA_SxNDT_10 0x00000400U
3379 #define DMA_SxNDT_11 0x00000800U
3380 #define DMA_SxNDT_12 0x00001000U
3381 #define DMA_SxNDT_13 0x00002000U
3382 #define DMA_SxNDT_14 0x00004000U
3383 #define DMA_SxNDT_15 0x00008000U
3384 
3385 /******************** Bits definition for DMA_SxFCR register ****************/
3386 #define DMA_SxFCR_FEIE 0x00000080U
3387 #define DMA_SxFCR_FS 0x00000038U
3388 #define DMA_SxFCR_FS_0 0x00000008U
3389 #define DMA_SxFCR_FS_1 0x00000010U
3390 #define DMA_SxFCR_FS_2 0x00000020U
3391 #define DMA_SxFCR_DMDIS 0x00000004U
3392 #define DMA_SxFCR_FTH 0x00000003U
3393 #define DMA_SxFCR_FTH_0 0x00000001U
3394 #define DMA_SxFCR_FTH_1 0x00000002U
3395 
3396 /******************** Bits definition for DMA_LISR register *****************/
3397 #define DMA_LISR_TCIF3 0x08000000U
3398 #define DMA_LISR_HTIF3 0x04000000U
3399 #define DMA_LISR_TEIF3 0x02000000U
3400 #define DMA_LISR_DMEIF3 0x01000000U
3401 #define DMA_LISR_FEIF3 0x00400000U
3402 #define DMA_LISR_TCIF2 0x00200000U
3403 #define DMA_LISR_HTIF2 0x00100000U
3404 #define DMA_LISR_TEIF2 0x00080000U
3405 #define DMA_LISR_DMEIF2 0x00040000U
3406 #define DMA_LISR_FEIF2 0x00010000U
3407 #define DMA_LISR_TCIF1 0x00000800U
3408 #define DMA_LISR_HTIF1 0x00000400U
3409 #define DMA_LISR_TEIF1 0x00000200U
3410 #define DMA_LISR_DMEIF1 0x00000100U
3411 #define DMA_LISR_FEIF1 0x00000040U
3412 #define DMA_LISR_TCIF0 0x00000020U
3413 #define DMA_LISR_HTIF0 0x00000010U
3414 #define DMA_LISR_TEIF0 0x00000008U
3415 #define DMA_LISR_DMEIF0 0x00000004U
3416 #define DMA_LISR_FEIF0 0x00000001U
3417 
3418 /******************** Bits definition for DMA_HISR register *****************/
3419 #define DMA_HISR_TCIF7 0x08000000U
3420 #define DMA_HISR_HTIF7 0x04000000U
3421 #define DMA_HISR_TEIF7 0x02000000U
3422 #define DMA_HISR_DMEIF7 0x01000000U
3423 #define DMA_HISR_FEIF7 0x00400000U
3424 #define DMA_HISR_TCIF6 0x00200000U
3425 #define DMA_HISR_HTIF6 0x00100000U
3426 #define DMA_HISR_TEIF6 0x00080000U
3427 #define DMA_HISR_DMEIF6 0x00040000U
3428 #define DMA_HISR_FEIF6 0x00010000U
3429 #define DMA_HISR_TCIF5 0x00000800U
3430 #define DMA_HISR_HTIF5 0x00000400U
3431 #define DMA_HISR_TEIF5 0x00000200U
3432 #define DMA_HISR_DMEIF5 0x00000100U
3433 #define DMA_HISR_FEIF5 0x00000040U
3434 #define DMA_HISR_TCIF4 0x00000020U
3435 #define DMA_HISR_HTIF4 0x00000010U
3436 #define DMA_HISR_TEIF4 0x00000008U
3437 #define DMA_HISR_DMEIF4 0x00000004U
3438 #define DMA_HISR_FEIF4 0x00000001U
3439 
3440 /******************** Bits definition for DMA_LIFCR register ****************/
3441 #define DMA_LIFCR_CTCIF3 0x08000000U
3442 #define DMA_LIFCR_CHTIF3 0x04000000U
3443 #define DMA_LIFCR_CTEIF3 0x02000000U
3444 #define DMA_LIFCR_CDMEIF3 0x01000000U
3445 #define DMA_LIFCR_CFEIF3 0x00400000U
3446 #define DMA_LIFCR_CTCIF2 0x00200000U
3447 #define DMA_LIFCR_CHTIF2 0x00100000U
3448 #define DMA_LIFCR_CTEIF2 0x00080000U
3449 #define DMA_LIFCR_CDMEIF2 0x00040000U
3450 #define DMA_LIFCR_CFEIF2 0x00010000U
3451 #define DMA_LIFCR_CTCIF1 0x00000800U
3452 #define DMA_LIFCR_CHTIF1 0x00000400U
3453 #define DMA_LIFCR_CTEIF1 0x00000200U
3454 #define DMA_LIFCR_CDMEIF1 0x00000100U
3455 #define DMA_LIFCR_CFEIF1 0x00000040U
3456 #define DMA_LIFCR_CTCIF0 0x00000020U
3457 #define DMA_LIFCR_CHTIF0 0x00000010U
3458 #define DMA_LIFCR_CTEIF0 0x00000008U
3459 #define DMA_LIFCR_CDMEIF0 0x00000004U
3460 #define DMA_LIFCR_CFEIF0 0x00000001U
3461 
3462 /******************** Bits definition for DMA_HIFCR register ****************/
3463 #define DMA_HIFCR_CTCIF7 0x08000000U
3464 #define DMA_HIFCR_CHTIF7 0x04000000U
3465 #define DMA_HIFCR_CTEIF7 0x02000000U
3466 #define DMA_HIFCR_CDMEIF7 0x01000000U
3467 #define DMA_HIFCR_CFEIF7 0x00400000U
3468 #define DMA_HIFCR_CTCIF6 0x00200000U
3469 #define DMA_HIFCR_CHTIF6 0x00100000U
3470 #define DMA_HIFCR_CTEIF6 0x00080000U
3471 #define DMA_HIFCR_CDMEIF6 0x00040000U
3472 #define DMA_HIFCR_CFEIF6 0x00010000U
3473 #define DMA_HIFCR_CTCIF5 0x00000800U
3474 #define DMA_HIFCR_CHTIF5 0x00000400U
3475 #define DMA_HIFCR_CTEIF5 0x00000200U
3476 #define DMA_HIFCR_CDMEIF5 0x00000100U
3477 #define DMA_HIFCR_CFEIF5 0x00000040U
3478 #define DMA_HIFCR_CTCIF4 0x00000020U
3479 #define DMA_HIFCR_CHTIF4 0x00000010U
3480 #define DMA_HIFCR_CTEIF4 0x00000008U
3481 #define DMA_HIFCR_CDMEIF4 0x00000004U
3482 #define DMA_HIFCR_CFEIF4 0x00000001U
3483 
3484 
3485 /******************************************************************************/
3486 /* */
3487 /* AHB Master DMA2D Controller (DMA2D) */
3488 /* */
3489 /******************************************************************************/
3490 
3491 /******************** Bit definition for DMA2D_CR register ******************/
3492 
3493 #define DMA2D_CR_START 0x00000001U
3494 #define DMA2D_CR_SUSP 0x00000002U
3495 #define DMA2D_CR_ABORT 0x00000004U
3496 #define DMA2D_CR_TEIE 0x00000100U
3497 #define DMA2D_CR_TCIE 0x00000200U
3498 #define DMA2D_CR_TWIE 0x00000400U
3499 #define DMA2D_CR_CAEIE 0x00000800U
3500 #define DMA2D_CR_CTCIE 0x00001000U
3501 #define DMA2D_CR_CEIE 0x00002000U
3502 #define DMA2D_CR_MODE 0x00030000U
3503 #define DMA2D_CR_MODE_0 0x00010000U
3504 #define DMA2D_CR_MODE_1 0x00020000U
3506 /******************** Bit definition for DMA2D_ISR register *****************/
3507 
3508 #define DMA2D_ISR_TEIF 0x00000001U
3509 #define DMA2D_ISR_TCIF 0x00000002U
3510 #define DMA2D_ISR_TWIF 0x00000004U
3511 #define DMA2D_ISR_CAEIF 0x00000008U
3512 #define DMA2D_ISR_CTCIF 0x00000010U
3513 #define DMA2D_ISR_CEIF 0x00000020U
3515 /******************** Bit definition for DMA2D_IFCR register ****************/
3516 
3517 #define DMA2D_IFCR_CTEIF 0x00000001U
3518 #define DMA2D_IFCR_CTCIF 0x00000002U
3519 #define DMA2D_IFCR_CTWIF 0x00000004U
3520 #define DMA2D_IFCR_CAECIF 0x00000008U
3521 #define DMA2D_IFCR_CCTCIF 0x00000010U
3522 #define DMA2D_IFCR_CCEIF 0x00000020U
3524 /* Legacy defines */
3525 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3526 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3527 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3528 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3529 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3530 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3532 /******************** Bit definition for DMA2D_FGMAR register ***************/
3533 
3534 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3536 /******************** Bit definition for DMA2D_FGOR register ****************/
3537 
3538 #define DMA2D_FGOR_LO 0x00003FFFU
3540 /******************** Bit definition for DMA2D_BGMAR register ***************/
3541 
3542 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3544 /******************** Bit definition for DMA2D_BGOR register ****************/
3545 
3546 #define DMA2D_BGOR_LO 0x00003FFFU
3548 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3549 
3550 #define DMA2D_FGPFCCR_CM 0x0000000FU
3551 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3552 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3553 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3554 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3555 #define DMA2D_FGPFCCR_CCM 0x00000010U
3556 #define DMA2D_FGPFCCR_START 0x00000020U
3557 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3558 #define DMA2D_FGPFCCR_AM 0x00030000U
3559 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3560 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3561 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3563 /******************** Bit definition for DMA2D_FGCOLR register **************/
3564 
3565 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3566 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3567 #define DMA2D_FGCOLR_RED 0x00FF0000U
3569 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3570 
3571 #define DMA2D_BGPFCCR_CM 0x0000000FU
3572 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3573 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3574 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3575 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3576 #define DMA2D_BGPFCCR_CCM 0x00000010U
3577 #define DMA2D_BGPFCCR_START 0x00000020U
3578 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3579 #define DMA2D_BGPFCCR_AM 0x00030000U
3580 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3581 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3582 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3584 /******************** Bit definition for DMA2D_BGCOLR register **************/
3585 
3586 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3587 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3588 #define DMA2D_BGCOLR_RED 0x00FF0000U
3590 /******************** Bit definition for DMA2D_FGCMAR register **************/
3591 
3592 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3594 /******************** Bit definition for DMA2D_BGCMAR register **************/
3595 
3596 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3598 /******************** Bit definition for DMA2D_OPFCCR register **************/
3599 
3600 #define DMA2D_OPFCCR_CM 0x00000007U
3601 #define DMA2D_OPFCCR_CM_0 0x00000001U
3602 #define DMA2D_OPFCCR_CM_1 0x00000002U
3603 #define DMA2D_OPFCCR_CM_2 0x00000004U
3605 /******************** Bit definition for DMA2D_OCOLR register ***************/
3606 
3609 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3610 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3611 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3612 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3615 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3616 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3617 #define DMA2D_OCOLR_RED_2 0x0000F800U
3620 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3621 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3622 #define DMA2D_OCOLR_RED_3 0x00007C00U
3623 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3626 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3627 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3628 #define DMA2D_OCOLR_RED_4 0x00000F00U
3629 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3631 /******************** Bit definition for DMA2D_OMAR register ****************/
3632 
3633 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3635 /******************** Bit definition for DMA2D_OOR register *****************/
3636 
3637 #define DMA2D_OOR_LO 0x00003FFFU
3639 /******************** Bit definition for DMA2D_NLR register *****************/
3640 
3641 #define DMA2D_NLR_NL 0x0000FFFFU
3642 #define DMA2D_NLR_PL 0x3FFF0000U
3644 /******************** Bit definition for DMA2D_LWR register *****************/
3645 
3646 #define DMA2D_LWR_LW 0x0000FFFFU
3648 /******************** Bit definition for DMA2D_AMTCR register ***************/
3649 
3650 #define DMA2D_AMTCR_EN 0x00000001U
3651 #define DMA2D_AMTCR_DT 0x0000FF00U
3653 /******************** Bit definition for DMA2D_FGCLUT register **************/
3654 
3655 /******************** Bit definition for DMA2D_BGCLUT register **************/
3656 
3657 
3658 /******************************************************************************/
3659 /* */
3660 /* Display Serial Interface (DSI) */
3661 /* */
3662 /******************************************************************************/
3663 /******************* Bit definition for DSI_VR register *****************/
3664 #define DSI_VR 0x3133302AU
3666 /******************* Bit definition for DSI_CR register *****************/
3667 #define DSI_CR_EN 0x00000001U
3669 /******************* Bit definition for DSI_CCR register ****************/
3670 #define DSI_CCR_TXECKDIV 0x000000FFU
3671 #define DSI_CCR_TXECKDIV0 0x00000001U
3672 #define DSI_CCR_TXECKDIV1 0x00000002U
3673 #define DSI_CCR_TXECKDIV2 0x00000004U
3674 #define DSI_CCR_TXECKDIV3 0x00000008U
3675 #define DSI_CCR_TXECKDIV4 0x00000010U
3676 #define DSI_CCR_TXECKDIV5 0x00000020U
3677 #define DSI_CCR_TXECKDIV6 0x00000040U
3678 #define DSI_CCR_TXECKDIV7 0x00000080U
3679 
3680 #define DSI_CCR_TOCKDIV 0x0000FF00U
3681 #define DSI_CCR_TOCKDIV0 0x00000100U
3682 #define DSI_CCR_TOCKDIV1 0x00000200U
3683 #define DSI_CCR_TOCKDIV2 0x00000400U
3684 #define DSI_CCR_TOCKDIV3 0x00000800U
3685 #define DSI_CCR_TOCKDIV4 0x00001000U
3686 #define DSI_CCR_TOCKDIV5 0x00002000U
3687 #define DSI_CCR_TOCKDIV6 0x00004000U
3688 #define DSI_CCR_TOCKDIV7 0x00008000U
3689 
3690 /******************* Bit definition for DSI_LVCIDR register *************/
3691 #define DSI_LVCIDR_VCID 0x00000003U
3692 #define DSI_LVCIDR_VCID0 0x00000001U
3693 #define DSI_LVCIDR_VCID1 0x00000002U
3694 
3695 /******************* Bit definition for DSI_LCOLCR register *************/
3696 #define DSI_LCOLCR_COLC 0x0000000FU
3697 #define DSI_LCOLCR_COLC0 0x00000001U
3698 #define DSI_LCOLCR_COLC1 0x00000020U
3699 #define DSI_LCOLCR_COLC2 0x00000040U
3700 #define DSI_LCOLCR_COLC3 0x00000080U
3701 
3702 #define DSI_LCOLCR_LPE 0x00000100U
3704 /******************* Bit definition for DSI_LPCR register ***************/
3705 #define DSI_LPCR_DEP 0x00000001U
3706 #define DSI_LPCR_VSP 0x00000002U
3707 #define DSI_LPCR_HSP 0x00000004U
3709 /******************* Bit definition for DSI_LPMCR register **************/
3710 #define DSI_LPMCR_VLPSIZE 0x000000FFU
3711 #define DSI_LPMCR_VLPSIZE0 0x00000001U
3712 #define DSI_LPMCR_VLPSIZE1 0x00000002U
3713 #define DSI_LPMCR_VLPSIZE2 0x00000004U
3714 #define DSI_LPMCR_VLPSIZE3 0x00000008U
3715 #define DSI_LPMCR_VLPSIZE4 0x00000010U
3716 #define DSI_LPMCR_VLPSIZE5 0x00000020U
3717 #define DSI_LPMCR_VLPSIZE6 0x00000040U
3718 #define DSI_LPMCR_VLPSIZE7 0x00000080U
3719 
3720 #define DSI_LPMCR_LPSIZE 0x00FF0000U
3721 #define DSI_LPMCR_LPSIZE0 0x00010000U
3722 #define DSI_LPMCR_LPSIZE1 0x00020000U
3723 #define DSI_LPMCR_LPSIZE2 0x00040000U
3724 #define DSI_LPMCR_LPSIZE3 0x00080000U
3725 #define DSI_LPMCR_LPSIZE4 0x00100000U
3726 #define DSI_LPMCR_LPSIZE5 0x00200000U
3727 #define DSI_LPMCR_LPSIZE6 0x00400000U
3728 #define DSI_LPMCR_LPSIZE7 0x00800000U
3729 
3730 /******************* Bit definition for DSI_PCR register ****************/
3731 #define DSI_PCR_ETTXE 0x00000001U
3732 #define DSI_PCR_ETRXE 0x00000002U
3733 #define DSI_PCR_BTAE 0x00000004U
3734 #define DSI_PCR_ECCRXE 0x00000008U
3735 #define DSI_PCR_CRCRXE 0x00000010U
3737 /******************* Bit definition for DSI_GVCIDR register *************/
3738 #define DSI_GVCIDR_VCID 0x00000003U
3739 #define DSI_GVCIDR_VCID0 0x00000001U
3740 #define DSI_GVCIDR_VCID1 0x00000002U
3741 
3742 /******************* Bit definition for DSI_MCR register ****************/
3743 #define DSI_MCR_CMDM 0x00000001U
3745 /******************* Bit definition for DSI_VMCR register ***************/
3746 #define DSI_VMCR_VMT 0x00000003U
3747 #define DSI_VMCR_VMT0 0x00000001U
3748 #define DSI_VMCR_VMT1 0x00000002U
3749 
3750 #define DSI_VMCR_LPVSAE 0x00000100U
3751 #define DSI_VMCR_LPVBPE 0x00000200U
3752 #define DSI_VMCR_LPVFPE 0x00000400U
3753 #define DSI_VMCR_LPVAE 0x00000800U
3754 #define DSI_VMCR_LPHBPE 0x00001000U
3755 #define DSI_VMCR_LPHFPE 0x00002000U
3756 #define DSI_VMCR_FBTAAE 0x00004000U
3757 #define DSI_VMCR_LPCE 0x00008000U
3758 #define DSI_VMCR_PGE 0x00010000U
3759 #define DSI_VMCR_PGM 0x00100000U
3760 #define DSI_VMCR_PGO 0x01000000U
3762 /******************* Bit definition for DSI_VPCR register ***************/
3763 #define DSI_VPCR_VPSIZE 0x00003FFFU
3764 #define DSI_VPCR_VPSIZE0 0x00000001U
3765 #define DSI_VPCR_VPSIZE1 0x00000002U
3766 #define DSI_VPCR_VPSIZE2 0x00000004U
3767 #define DSI_VPCR_VPSIZE3 0x00000008U
3768 #define DSI_VPCR_VPSIZE4 0x00000010U
3769 #define DSI_VPCR_VPSIZE5 0x00000020U
3770 #define DSI_VPCR_VPSIZE6 0x00000040U
3771 #define DSI_VPCR_VPSIZE7 0x00000080U
3772 #define DSI_VPCR_VPSIZE8 0x00000100U
3773 #define DSI_VPCR_VPSIZE9 0x00000200U
3774 #define DSI_VPCR_VPSIZE10 0x00000400U
3775 #define DSI_VPCR_VPSIZE11 0x00000800U
3776 #define DSI_VPCR_VPSIZE12 0x00001000U
3777 #define DSI_VPCR_VPSIZE13 0x00002000U
3778 
3779 /******************* Bit definition for DSI_VCCR register ***************/
3780 #define DSI_VCCR_NUMC 0x00001FFFU
3781 #define DSI_VCCR_NUMC0 0x00000001U
3782 #define DSI_VCCR_NUMC1 0x00000002U
3783 #define DSI_VCCR_NUMC2 0x00000004U
3784 #define DSI_VCCR_NUMC3 0x00000008U
3785 #define DSI_VCCR_NUMC4 0x00000010U
3786 #define DSI_VCCR_NUMC5 0x00000020U
3787 #define DSI_VCCR_NUMC6 0x00000040U
3788 #define DSI_VCCR_NUMC7 0x00000080U
3789 #define DSI_VCCR_NUMC8 0x00000100U
3790 #define DSI_VCCR_NUMC9 0x00000200U
3791 #define DSI_VCCR_NUMC10 0x00000400U
3792 #define DSI_VCCR_NUMC11 0x00000800U
3793 #define DSI_VCCR_NUMC12 0x00001000U
3794 
3795 /******************* Bit definition for DSI_VNPCR register **************/
3796 #define DSI_VNPCR_NPSIZE 0x00001FFFU
3797 #define DSI_VNPCR_NPSIZE0 0x00000001U
3798 #define DSI_VNPCR_NPSIZE1 0x00000002U
3799 #define DSI_VNPCR_NPSIZE2 0x00000004U
3800 #define DSI_VNPCR_NPSIZE3 0x00000008U
3801 #define DSI_VNPCR_NPSIZE4 0x00000010U
3802 #define DSI_VNPCR_NPSIZE5 0x00000020U
3803 #define DSI_VNPCR_NPSIZE6 0x00000040U
3804 #define DSI_VNPCR_NPSIZE7 0x00000080U
3805 #define DSI_VNPCR_NPSIZE8 0x00000100U
3806 #define DSI_VNPCR_NPSIZE9 0x00000200U
3807 #define DSI_VNPCR_NPSIZE10 0x00000400U
3808 #define DSI_VNPCR_NPSIZE11 0x00000800U
3809 #define DSI_VNPCR_NPSIZE12 0x00001000U
3810 
3811 /******************* Bit definition for DSI_VHSACR register *************/
3812 #define DSI_VHSACR_HSA 0x00000FFFU
3813 #define DSI_VHSACR_HSA0 0x00000001U
3814 #define DSI_VHSACR_HSA1 0x00000002U
3815 #define DSI_VHSACR_HSA2 0x00000004U
3816 #define DSI_VHSACR_HSA3 0x00000008U
3817 #define DSI_VHSACR_HSA4 0x00000010U
3818 #define DSI_VHSACR_HSA5 0x00000020U
3819 #define DSI_VHSACR_HSA6 0x00000040U
3820 #define DSI_VHSACR_HSA7 0x00000080U
3821 #define DSI_VHSACR_HSA8 0x00000100U
3822 #define DSI_VHSACR_HSA9 0x00000200U
3823 #define DSI_VHSACR_HSA10 0x00000400U
3824 #define DSI_VHSACR_HSA11 0x00000800U
3825 
3826 /******************* Bit definition for DSI_VHBPCR register *************/
3827 #define DSI_VHBPCR_HBP 0x00000FFFU
3828 #define DSI_VHBPCR_HBP0 0x00000001U
3829 #define DSI_VHBPCR_HBP1 0x00000002U
3830 #define DSI_VHBPCR_HBP2 0x00000004U
3831 #define DSI_VHBPCR_HBP3 0x00000008U
3832 #define DSI_VHBPCR_HBP4 0x00000010U
3833 #define DSI_VHBPCR_HBP5 0x00000020U
3834 #define DSI_VHBPCR_HBP6 0x00000040U
3835 #define DSI_VHBPCR_HBP7 0x00000080U
3836 #define DSI_VHBPCR_HBP8 0x00000100U
3837 #define DSI_VHBPCR_HBP9 0x00000200U
3838 #define DSI_VHBPCR_HBP10 0x00000400U
3839 #define DSI_VHBPCR_HBP11 0x00000800U
3840 
3841 /******************* Bit definition for DSI_VLCR register ***************/
3842 #define DSI_VLCR_HLINE 0x00007FFFU
3843 #define DSI_VLCR_HLINE0 0x00000001U
3844 #define DSI_VLCR_HLINE1 0x00000002U
3845 #define DSI_VLCR_HLINE2 0x00000004U
3846 #define DSI_VLCR_HLINE3 0x00000008U
3847 #define DSI_VLCR_HLINE4 0x00000010U
3848 #define DSI_VLCR_HLINE5 0x00000020U
3849 #define DSI_VLCR_HLINE6 0x00000040U
3850 #define DSI_VLCR_HLINE7 0x00000080U
3851 #define DSI_VLCR_HLINE8 0x00000100U
3852 #define DSI_VLCR_HLINE9 0x00000200U
3853 #define DSI_VLCR_HLINE10 0x00000400U
3854 #define DSI_VLCR_HLINE11 0x00000800U
3855 #define DSI_VLCR_HLINE12 0x00001000U
3856 #define DSI_VLCR_HLINE13 0x00002000U
3857 #define DSI_VLCR_HLINE14 0x00004000U
3858 
3859 /******************* Bit definition for DSI_VVSACR register *************/
3860 #define DSI_VVSACR_VSA 0x000003FFU
3861 #define DSI_VVSACR_VSA0 0x00000001U
3862 #define DSI_VVSACR_VSA1 0x00000002U
3863 #define DSI_VVSACR_VSA2 0x00000004U
3864 #define DSI_VVSACR_VSA3 0x00000008U
3865 #define DSI_VVSACR_VSA4 0x00000010U
3866 #define DSI_VVSACR_VSA5 0x00000020U
3867 #define DSI_VVSACR_VSA6 0x00000040U
3868 #define DSI_VVSACR_VSA7 0x00000080U
3869 #define DSI_VVSACR_VSA8 0x00000100U
3870 #define DSI_VVSACR_VSA9 0x00000200U
3871 
3872 /******************* Bit definition for DSI_VVBPCR register *************/
3873 #define DSI_VVBPCR_VBP 0x000003FFU
3874 #define DSI_VVBPCR_VBP0 0x00000001U
3875 #define DSI_VVBPCR_VBP1 0x00000002U
3876 #define DSI_VVBPCR_VBP2 0x00000004U
3877 #define DSI_VVBPCR_VBP3 0x00000008U
3878 #define DSI_VVBPCR_VBP4 0x00000010U
3879 #define DSI_VVBPCR_VBP5 0x00000020U
3880 #define DSI_VVBPCR_VBP6 0x00000040U
3881 #define DSI_VVBPCR_VBP7 0x00000080U
3882 #define DSI_VVBPCR_VBP8 0x00000100U
3883 #define DSI_VVBPCR_VBP9 0x00000200U
3884 
3885 /******************* Bit definition for DSI_VVFPCR register *************/
3886 #define DSI_VVFPCR_VFP 0x000003FFU
3887 #define DSI_VVFPCR_VFP0 0x00000001U
3888 #define DSI_VVFPCR_VFP1 0x00000002U
3889 #define DSI_VVFPCR_VFP2 0x00000004U
3890 #define DSI_VVFPCR_VFP3 0x00000008U
3891 #define DSI_VVFPCR_VFP4 0x00000010U
3892 #define DSI_VVFPCR_VFP5 0x00000020U
3893 #define DSI_VVFPCR_VFP6 0x00000040U
3894 #define DSI_VVFPCR_VFP7 0x00000080U
3895 #define DSI_VVFPCR_VFP8 0x00000100U
3896 #define DSI_VVFPCR_VFP9 0x00000200U
3897 
3898 /******************* Bit definition for DSI_VVACR register **************/
3899 #define DSI_VVACR_VA 0x00003FFFU
3900 #define DSI_VVACR_VA0 0x00000001U
3901 #define DSI_VVACR_VA1 0x00000002U
3902 #define DSI_VVACR_VA2 0x00000004U
3903 #define DSI_VVACR_VA3 0x00000008U
3904 #define DSI_VVACR_VA4 0x00000010U
3905 #define DSI_VVACR_VA5 0x00000020U
3906 #define DSI_VVACR_VA6 0x00000040U
3907 #define DSI_VVACR_VA7 0x00000080U
3908 #define DSI_VVACR_VA8 0x00000100U
3909 #define DSI_VVACR_VA9 0x00000200U
3910 #define DSI_VVACR_VA10 0x00000400U
3911 #define DSI_VVACR_VA11 0x00000800U
3912 #define DSI_VVACR_VA12 0x00001000U
3913 #define DSI_VVACR_VA13 0x00002000U
3914 
3915 /******************* Bit definition for DSI_LCCR register ***************/
3916 #define DSI_LCCR_CMDSIZE 0x0000FFFFU
3917 #define DSI_LCCR_CMDSIZE0 0x00000001U
3918 #define DSI_LCCR_CMDSIZE1 0x00000002U
3919 #define DSI_LCCR_CMDSIZE2 0x00000004U
3920 #define DSI_LCCR_CMDSIZE3 0x00000008U
3921 #define DSI_LCCR_CMDSIZE4 0x00000010U
3922 #define DSI_LCCR_CMDSIZE5 0x00000020U
3923 #define DSI_LCCR_CMDSIZE6 0x00000040U
3924 #define DSI_LCCR_CMDSIZE7 0x00000080U
3925 #define DSI_LCCR_CMDSIZE8 0x00000100U
3926 #define DSI_LCCR_CMDSIZE9 0x00000200U
3927 #define DSI_LCCR_CMDSIZE10 0x00000400U
3928 #define DSI_LCCR_CMDSIZE11 0x00000800U
3929 #define DSI_LCCR_CMDSIZE12 0x00001000U
3930 #define DSI_LCCR_CMDSIZE13 0x00002000U
3931 #define DSI_LCCR_CMDSIZE14 0x00004000U
3932 #define DSI_LCCR_CMDSIZE15 0x00008000U
3933 
3934 /******************* Bit definition for DSI_CMCR register ***************/
3935 #define DSI_CMCR_TEARE 0x00000001U
3936 #define DSI_CMCR_ARE 0x00000002U
3937 #define DSI_CMCR_GSW0TX 0x00000100U
3938 #define DSI_CMCR_GSW1TX 0x00000200U
3939 #define DSI_CMCR_GSW2TX 0x00000400U
3940 #define DSI_CMCR_GSR0TX 0x00000800U
3941 #define DSI_CMCR_GSR1TX 0x00001000U
3942 #define DSI_CMCR_GSR2TX 0x00002000U
3943 #define DSI_CMCR_GLWTX 0x00004000U
3944 #define DSI_CMCR_DSW0TX 0x00010000U
3945 #define DSI_CMCR_DSW1TX 0x00020000U
3946 #define DSI_CMCR_DSR0TX 0x00040000U
3947 #define DSI_CMCR_DLWTX 0x00080000U
3948 #define DSI_CMCR_MRDPS 0x01000000U
3950 /******************* Bit definition for DSI_GHCR register ***************/
3951 #define DSI_GHCR_DT 0x0000003FU
3952 #define DSI_GHCR_DT0 0x00000001U
3953 #define DSI_GHCR_DT1 0x00000002U
3954 #define DSI_GHCR_DT2 0x00000004U
3955 #define DSI_GHCR_DT3 0x00000008U
3956 #define DSI_GHCR_DT4 0x00000010U
3957 #define DSI_GHCR_DT5 0x00000020U
3958 
3959 #define DSI_GHCR_VCID 0x000000C0U
3960 #define DSI_GHCR_VCID0 0x00000040U
3961 #define DSI_GHCR_VCID1 0x00000080U
3962 
3963 #define DSI_GHCR_WCLSB 0x0000FF00U
3964 #define DSI_GHCR_WCLSB0 0x00000100U
3965 #define DSI_GHCR_WCLSB1 0x00000200U
3966 #define DSI_GHCR_WCLSB2 0x00000400U
3967 #define DSI_GHCR_WCLSB3 0x00000800U
3968 #define DSI_GHCR_WCLSB4 0x00001000U
3969 #define DSI_GHCR_WCLSB5 0x00002000U
3970 #define DSI_GHCR_WCLSB6 0x00004000U
3971 #define DSI_GHCR_WCLSB7 0x00008000U
3972 
3973 #define DSI_GHCR_WCMSB 0x00FF0000U
3974 #define DSI_GHCR_WCMSB0 0x00010000U
3975 #define DSI_GHCR_WCMSB1 0x00020000U
3976 #define DSI_GHCR_WCMSB2 0x00040000U
3977 #define DSI_GHCR_WCMSB3 0x00080000U
3978 #define DSI_GHCR_WCMSB4 0x00100000U
3979 #define DSI_GHCR_WCMSB5 0x00200000U
3980 #define DSI_GHCR_WCMSB6 0x00400000U
3981 #define DSI_GHCR_WCMSB7 0x00800000U
3982 
3983 /******************* Bit definition for DSI_GPDR register ***************/
3984 #define DSI_GPDR_DATA1 0x000000FFU
3985 #define DSI_GPDR_DATA1_0 0x00000001U
3986 #define DSI_GPDR_DATA1_1 0x00000002U
3987 #define DSI_GPDR_DATA1_2 0x00000004U
3988 #define DSI_GPDR_DATA1_3 0x00000008U
3989 #define DSI_GPDR_DATA1_4 0x00000010U
3990 #define DSI_GPDR_DATA1_5 0x00000020U
3991 #define DSI_GPDR_DATA1_6 0x00000040U
3992 #define DSI_GPDR_DATA1_7 0x00000080U
3993 
3994 #define DSI_GPDR_DATA2 0x0000FF00U
3995 #define DSI_GPDR_DATA2_0 0x00000100U
3996 #define DSI_GPDR_DATA2_1 0x00000200U
3997 #define DSI_GPDR_DATA2_2 0x00000400U
3998 #define DSI_GPDR_DATA2_3 0x00000800U
3999 #define DSI_GPDR_DATA2_4 0x00001000U
4000 #define DSI_GPDR_DATA2_5 0x00002000U
4001 #define DSI_GPDR_DATA2_6 0x00004000U
4002 #define DSI_GPDR_DATA2_7 0x00008000U
4003 
4004 #define DSI_GPDR_DATA3 0x00FF0000U
4005 #define DSI_GPDR_DATA3_0 0x00010000U
4006 #define DSI_GPDR_DATA3_1 0x00020000U
4007 #define DSI_GPDR_DATA3_2 0x00040000U
4008 #define DSI_GPDR_DATA3_3 0x00080000U
4009 #define DSI_GPDR_DATA3_4 0x00100000U
4010 #define DSI_GPDR_DATA3_5 0x00200000U
4011 #define DSI_GPDR_DATA3_6 0x00400000U
4012 #define DSI_GPDR_DATA3_7 0x00800000U
4013 
4014 #define DSI_GPDR_DATA4 0xFF000000U
4015 #define DSI_GPDR_DATA4_0 0x01000000U
4016 #define DSI_GPDR_DATA4_1 0x02000000U
4017 #define DSI_GPDR_DATA4_2 0x04000000U
4018 #define DSI_GPDR_DATA4_3 0x08000000U
4019 #define DSI_GPDR_DATA4_4 0x10000000U
4020 #define DSI_GPDR_DATA4_5 0x20000000U
4021 #define DSI_GPDR_DATA4_6 0x40000000U
4022 #define DSI_GPDR_DATA4_7 0x80000000U
4023 
4024 /******************* Bit definition for DSI_GPSR register ***************/
4025 #define DSI_GPSR_CMDFE 0x00000001U
4026 #define DSI_GPSR_CMDFF 0x00000002U
4027 #define DSI_GPSR_PWRFE 0x00000004U
4028 #define DSI_GPSR_PWRFF 0x00000008U
4029 #define DSI_GPSR_PRDFE 0x00000010U
4030 #define DSI_GPSR_PRDFF 0x00000020U
4031 #define DSI_GPSR_RCB 0x00000040U
4033 /******************* Bit definition for DSI_TCCR0 register **************/
4034 #define DSI_TCCR0_LPRX_TOCNT 0x0000FFFFU
4035 #define DSI_TCCR0_LPRX_TOCNT0 0x00000001U
4036 #define DSI_TCCR0_LPRX_TOCNT1 0x00000002U
4037 #define DSI_TCCR0_LPRX_TOCNT2 0x00000004U
4038 #define DSI_TCCR0_LPRX_TOCNT3 0x00000008U
4039 #define DSI_TCCR0_LPRX_TOCNT4 0x00000010U
4040 #define DSI_TCCR0_LPRX_TOCNT5 0x00000020U
4041 #define DSI_TCCR0_LPRX_TOCNT6 0x00000040U
4042 #define DSI_TCCR0_LPRX_TOCNT7 0x00000080U
4043 #define DSI_TCCR0_LPRX_TOCNT8 0x00000100U
4044 #define DSI_TCCR0_LPRX_TOCNT9 0x00000200U
4045 #define DSI_TCCR0_LPRX_TOCNT10 0x00000400U
4046 #define DSI_TCCR0_LPRX_TOCNT11 0x00000800U
4047 #define DSI_TCCR0_LPRX_TOCNT12 0x00001000U
4048 #define DSI_TCCR0_LPRX_TOCNT13 0x00002000U
4049 #define DSI_TCCR0_LPRX_TOCNT14 0x00004000U
4050 #define DSI_TCCR0_LPRX_TOCNT15 0x00008000U
4051 
4052 #define DSI_TCCR0_HSTX_TOCNT 0xFFFF0000U
4053 #define DSI_TCCR0_HSTX_TOCNT0 0x00010000U
4054 #define DSI_TCCR0_HSTX_TOCNT1 0x00020000U
4055 #define DSI_TCCR0_HSTX_TOCNT2 0x00040000U
4056 #define DSI_TCCR0_HSTX_TOCNT3 0x00080000U
4057 #define DSI_TCCR0_HSTX_TOCNT4 0x00100000U
4058 #define DSI_TCCR0_HSTX_TOCNT5 0x00200000U
4059 #define DSI_TCCR0_HSTX_TOCNT6 0x00400000U
4060 #define DSI_TCCR0_HSTX_TOCNT7 0x00800000U
4061 #define DSI_TCCR0_HSTX_TOCNT8 0x01000000U
4062 #define DSI_TCCR0_HSTX_TOCNT9 0x02000000U
4063 #define DSI_TCCR0_HSTX_TOCNT10 0x04000000U
4064 #define DSI_TCCR0_HSTX_TOCNT11 0x08000000U
4065 #define DSI_TCCR0_HSTX_TOCNT12 0x10000000U
4066 #define DSI_TCCR0_HSTX_TOCNT13 0x20000000U
4067 #define DSI_TCCR0_HSTX_TOCNT14 0x40000000U
4068 #define DSI_TCCR0_HSTX_TOCNT15 0x80000000U
4069 
4070 /******************* Bit definition for DSI_TCCR1 register **************/
4071 #define DSI_TCCR1_HSRD_TOCNT 0x0000FFFFU
4072 #define DSI_TCCR1_HSRD_TOCNT0 0x00000001U
4073 #define DSI_TCCR1_HSRD_TOCNT1 0x00000002U
4074 #define DSI_TCCR1_HSRD_TOCNT2 0x00000004U
4075 #define DSI_TCCR1_HSRD_TOCNT3 0x00000008U
4076 #define DSI_TCCR1_HSRD_TOCNT4 0x00000010U
4077 #define DSI_TCCR1_HSRD_TOCNT5 0x00000020U
4078 #define DSI_TCCR1_HSRD_TOCNT6 0x00000040U
4079 #define DSI_TCCR1_HSRD_TOCNT7 0x00000080U
4080 #define DSI_TCCR1_HSRD_TOCNT8 0x00000100U
4081 #define DSI_TCCR1_HSRD_TOCNT9 0x00000200U
4082 #define DSI_TCCR1_HSRD_TOCNT10 0x00000400U
4083 #define DSI_TCCR1_HSRD_TOCNT11 0x00000800U
4084 #define DSI_TCCR1_HSRD_TOCNT12 0x00001000U
4085 #define DSI_TCCR1_HSRD_TOCNT13 0x00002000U
4086 #define DSI_TCCR1_HSRD_TOCNT14 0x00004000U
4087 #define DSI_TCCR1_HSRD_TOCNT15 0x00008000U
4088 
4089 /******************* Bit definition for DSI_TCCR2 register **************/
4090 #define DSI_TCCR2_LPRD_TOCNT 0x0000FFFFU
4091 #define DSI_TCCR2_LPRD_TOCNT0 0x00000001U
4092 #define DSI_TCCR2_LPRD_TOCNT1 0x00000002U
4093 #define DSI_TCCR2_LPRD_TOCNT2 0x00000004U
4094 #define DSI_TCCR2_LPRD_TOCNT3 0x00000008U
4095 #define DSI_TCCR2_LPRD_TOCNT4 0x00000010U
4096 #define DSI_TCCR2_LPRD_TOCNT5 0x00000020U
4097 #define DSI_TCCR2_LPRD_TOCNT6 0x00000040U
4098 #define DSI_TCCR2_LPRD_TOCNT7 0x00000080U
4099 #define DSI_TCCR2_LPRD_TOCNT8 0x00000100U
4100 #define DSI_TCCR2_LPRD_TOCNT9 0x00000200U
4101 #define DSI_TCCR2_LPRD_TOCNT10 0x00000400U
4102 #define DSI_TCCR2_LPRD_TOCNT11 0x00000800U
4103 #define DSI_TCCR2_LPRD_TOCNT12 0x00001000U
4104 #define DSI_TCCR2_LPRD_TOCNT13 0x00002000U
4105 #define DSI_TCCR2_LPRD_TOCNT14 0x00004000U
4106 #define DSI_TCCR2_LPRD_TOCNT15 0x00008000U
4107 
4108 /******************* Bit definition for DSI_TCCR3 register **************/
4109 #define DSI_TCCR3_HSWR_TOCNT 0x0000FFFFU
4110 #define DSI_TCCR3_HSWR_TOCNT0 0x00000001U
4111 #define DSI_TCCR3_HSWR_TOCNT1 0x00000002U
4112 #define DSI_TCCR3_HSWR_TOCNT2 0x00000004U
4113 #define DSI_TCCR3_HSWR_TOCNT3 0x00000008U
4114 #define DSI_TCCR3_HSWR_TOCNT4 0x00000010U
4115 #define DSI_TCCR3_HSWR_TOCNT5 0x00000020U
4116 #define DSI_TCCR3_HSWR_TOCNT6 0x00000040U
4117 #define DSI_TCCR3_HSWR_TOCNT7 0x00000080U
4118 #define DSI_TCCR3_HSWR_TOCNT8 0x00000100U
4119 #define DSI_TCCR3_HSWR_TOCNT9 0x00000200U
4120 #define DSI_TCCR3_HSWR_TOCNT10 0x00000400U
4121 #define DSI_TCCR3_HSWR_TOCNT11 0x00000800U
4122 #define DSI_TCCR3_HSWR_TOCNT12 0x00001000U
4123 #define DSI_TCCR3_HSWR_TOCNT13 0x00002000U
4124 #define DSI_TCCR3_HSWR_TOCNT14 0x00004000U
4125 #define DSI_TCCR3_HSWR_TOCNT15 0x00008000U
4126 
4127 #define DSI_TCCR3_PM 0x01000000U
4129 /******************* Bit definition for DSI_TCCR4 register **************/
4130 #define DSI_TCCR4_LPWR_TOCNT 0x0000FFFFU
4131 #define DSI_TCCR4_LPWR_TOCNT0 0x00000001U
4132 #define DSI_TCCR4_LPWR_TOCNT1 0x00000002U
4133 #define DSI_TCCR4_LPWR_TOCNT2 0x00000004U
4134 #define DSI_TCCR4_LPWR_TOCNT3 0x00000008U
4135 #define DSI_TCCR4_LPWR_TOCNT4 0x00000010U
4136 #define DSI_TCCR4_LPWR_TOCNT5 0x00000020U
4137 #define DSI_TCCR4_LPWR_TOCNT6 0x00000040U
4138 #define DSI_TCCR4_LPWR_TOCNT7 0x00000080U
4139 #define DSI_TCCR4_LPWR_TOCNT8 0x00000100U
4140 #define DSI_TCCR4_LPWR_TOCNT9 0x00000200U
4141 #define DSI_TCCR4_LPWR_TOCNT10 0x00000400U
4142 #define DSI_TCCR4_LPWR_TOCNT11 0x00000800U
4143 #define DSI_TCCR4_LPWR_TOCNT12 0x00001000U
4144 #define DSI_TCCR4_LPWR_TOCNT13 0x00002000U
4145 #define DSI_TCCR4_LPWR_TOCNT14 0x00004000U
4146 #define DSI_TCCR4_LPWR_TOCNT15 0x00008000U
4147 
4148 /******************* Bit definition for DSI_TCCR5 register **************/
4149 #define DSI_TCCR5_BTA_TOCNT 0x0000FFFFU
4150 #define DSI_TCCR5_BTA_TOCNT0 0x00000001U
4151 #define DSI_TCCR5_BTA_TOCNT1 0x00000002U
4152 #define DSI_TCCR5_BTA_TOCNT2 0x00000004U
4153 #define DSI_TCCR5_BTA_TOCNT3 0x00000008U
4154 #define DSI_TCCR5_BTA_TOCNT4 0x00000010U
4155 #define DSI_TCCR5_BTA_TOCNT5 0x00000020U
4156 #define DSI_TCCR5_BTA_TOCNT6 0x00000040U
4157 #define DSI_TCCR5_BTA_TOCNT7 0x00000080U
4158 #define DSI_TCCR5_BTA_TOCNT8 0x00000100U
4159 #define DSI_TCCR5_BTA_TOCNT9 0x00000200U
4160 #define DSI_TCCR5_BTA_TOCNT10 0x00000400U
4161 #define DSI_TCCR5_BTA_TOCNT11 0x00000800U
4162 #define DSI_TCCR5_BTA_TOCNT12 0x00001000U
4163 #define DSI_TCCR5_BTA_TOCNT13 0x00002000U
4164 #define DSI_TCCR5_BTA_TOCNT14 0x00004000U
4165 #define DSI_TCCR5_BTA_TOCNT15 0x00008000U
4166 
4167 /******************* Bit definition for DSI_TDCR register ***************/
4168 #define DSI_TDCR_3DM 0x00000003U
4169 #define DSI_TDCR_3DM0 0x00000001U
4170 #define DSI_TDCR_3DM1 0x00000002U
4171 
4172 #define DSI_TDCR_3DF 0x0000000CU
4173 #define DSI_TDCR_3DF0 0x00000004U
4174 #define DSI_TDCR_3DF1 0x00000008U
4175 
4176 #define DSI_TDCR_SVS 0x00000010U
4177 #define DSI_TDCR_RF 0x00000020U
4178 #define DSI_TDCR_S3DC 0x00010000U
4180 /******************* Bit definition for DSI_CLCR register ***************/
4181 #define DSI_CLCR_DPCC 0x00000001U
4182 #define DSI_CLCR_ACR 0x00000002U
4184 /******************* Bit definition for DSI_CLTCR register **************/
4185 #define DSI_CLTCR_LP2HS_TIME 0x000003FFU
4186 #define DSI_CLTCR_LP2HS_TIME0 0x00000001U
4187 #define DSI_CLTCR_LP2HS_TIME1 0x00000002U
4188 #define DSI_CLTCR_LP2HS_TIME2 0x00000004U
4189 #define DSI_CLTCR_LP2HS_TIME3 0x00000008U
4190 #define DSI_CLTCR_LP2HS_TIME4 0x00000010U
4191 #define DSI_CLTCR_LP2HS_TIME5 0x00000020U
4192 #define DSI_CLTCR_LP2HS_TIME6 0x00000040U
4193 #define DSI_CLTCR_LP2HS_TIME7 0x00000080U
4194 #define DSI_CLTCR_LP2HS_TIME8 0x00000100U
4195 #define DSI_CLTCR_LP2HS_TIME9 0x00000200U
4196 
4197 #define DSI_CLTCR_HS2LP_TIME 0x03FF0000U
4198 #define DSI_CLTCR_HS2LP_TIME0 0x00010000U
4199 #define DSI_CLTCR_HS2LP_TIME1 0x00020000U
4200 #define DSI_CLTCR_HS2LP_TIME2 0x00040000U
4201 #define DSI_CLTCR_HS2LP_TIME3 0x00080000U
4202 #define DSI_CLTCR_HS2LP_TIME4 0x00100000U
4203 #define DSI_CLTCR_HS2LP_TIME5 0x00200000U
4204 #define DSI_CLTCR_HS2LP_TIME6 0x00400000U
4205 #define DSI_CLTCR_HS2LP_TIME7 0x00800000U
4206 #define DSI_CLTCR_HS2LP_TIME8 0x01000000U
4207 #define DSI_CLTCR_HS2LP_TIME9 0x02000000U
4208 
4209 /******************* Bit definition for DSI_DLTCR register **************/
4210 #define DSI_DLTCR_MRD_TIME 0x00007FFFU
4211 #define DSI_DLTCR_MRD_TIME0 0x00000001U
4212 #define DSI_DLTCR_MRD_TIME1 0x00000002U
4213 #define DSI_DLTCR_MRD_TIME2 0x00000004U
4214 #define DSI_DLTCR_MRD_TIME3 0x00000008U
4215 #define DSI_DLTCR_MRD_TIME4 0x00000010U
4216 #define DSI_DLTCR_MRD_TIME5 0x00000020U
4217 #define DSI_DLTCR_MRD_TIME6 0x00000040U
4218 #define DSI_DLTCR_MRD_TIME7 0x00000080U
4219 #define DSI_DLTCR_MRD_TIME8 0x00000100U
4220 #define DSI_DLTCR_MRD_TIME9 0x00000200U
4221 #define DSI_DLTCR_MRD_TIME10 0x00000400U
4222 #define DSI_DLTCR_MRD_TIME11 0x00000800U
4223 #define DSI_DLTCR_MRD_TIME12 0x00001000U
4224 #define DSI_DLTCR_MRD_TIME13 0x00002000U
4225 #define DSI_DLTCR_MRD_TIME14 0x00004000U
4226 
4227 #define DSI_DLTCR_LP2HS_TIME 0x00FF0000U
4228 #define DSI_DLTCR_LP2HS_TIME0 0x00010000U
4229 #define DSI_DLTCR_LP2HS_TIME1 0x00020000U
4230 #define DSI_DLTCR_LP2HS_TIME2 0x00040000U
4231 #define DSI_DLTCR_LP2HS_TIME3 0x00080000U
4232 #define DSI_DLTCR_LP2HS_TIME4 0x00100000U
4233 #define DSI_DLTCR_LP2HS_TIME5 0x00200000U
4234 #define DSI_DLTCR_LP2HS_TIME6 0x00400000U
4235 #define DSI_DLTCR_LP2HS_TIME7 0x00800000U
4236 
4237 #define DSI_DLTCR_HS2LP_TIME 0xFF000000U
4238 #define DSI_DLTCR_HS2LP_TIME0 0x01000000U
4239 #define DSI_DLTCR_HS2LP_TIME1 0x02000000U
4240 #define DSI_DLTCR_HS2LP_TIME2 0x04000000U
4241 #define DSI_DLTCR_HS2LP_TIME3 0x08000000U
4242 #define DSI_DLTCR_HS2LP_TIME4 0x10000000U
4243 #define DSI_DLTCR_HS2LP_TIME5 0x20000000U
4244 #define DSI_DLTCR_HS2LP_TIME6 0x40000000U
4245 #define DSI_DLTCR_HS2LP_TIME7 0x80000000U
4246 
4247 /******************* Bit definition for DSI_PCTLR register **************/
4248 #define DSI_PCTLR_DEN 0x00000002U
4249 #define DSI_PCTLR_CKE 0x00000004U
4251 /******************* Bit definition for DSI_PCONFR register *************/
4252 #define DSI_PCONFR_NL 0x00000003U
4253 #define DSI_PCONFR_NL0 0x00000001U
4254 #define DSI_PCONFR_NL1 0x00000002U
4255 
4256 #define DSI_PCONFR_SW_TIME 0x0000FF00U
4257 #define DSI_PCONFR_SW_TIME0 0x00000100U
4258 #define DSI_PCONFR_SW_TIME1 0x00000200U
4259 #define DSI_PCONFR_SW_TIME2 0x00000400U
4260 #define DSI_PCONFR_SW_TIME3 0x00000800U
4261 #define DSI_PCONFR_SW_TIME4 0x00001000U
4262 #define DSI_PCONFR_SW_TIME5 0x00002000U
4263 #define DSI_PCONFR_SW_TIME6 0x00004000U
4264 #define DSI_PCONFR_SW_TIME7 0x00008000U
4265 
4266 /******************* Bit definition for DSI_PUCR register ***************/
4267 #define DSI_PUCR_URCL 0x00000001U
4268 #define DSI_PUCR_UECL 0x00000002U
4269 #define DSI_PUCR_URDL 0x00000004U
4270 #define DSI_PUCR_UEDL 0x00000008U
4272 /******************* Bit definition for DSI_PTTCR register **************/
4273 #define DSI_PTTCR_TX_TRIG 0x0000000FU
4274 #define DSI_PTTCR_TX_TRIG0 0x00000001U
4275 #define DSI_PTTCR_TX_TRIG1 0x00000002U
4276 #define DSI_PTTCR_TX_TRIG2 0x00000004U
4277 #define DSI_PTTCR_TX_TRIG3 0x00000008U
4278 
4279 /******************* Bit definition for DSI_PSR register ****************/
4280 #define DSI_PSR_PD 0x00000002U
4281 #define DSI_PSR_PSSC 0x00000004U
4282 #define DSI_PSR_UANC 0x00000008U
4283 #define DSI_PSR_PSS0 0x00000010U
4284 #define DSI_PSR_UAN0 0x00000020U
4285 #define DSI_PSR_RUE0 0x00000040U
4286 #define DSI_PSR_PSS1 0x00000080U
4287 #define DSI_PSR_UAN1 0x00000100U
4289 /******************* Bit definition for DSI_ISR0 register ***************/
4290 #define DSI_ISR0_AE0 0x00000001U
4291 #define DSI_ISR0_AE1 0x00000002U
4292 #define DSI_ISR0_AE2 0x00000004U
4293 #define DSI_ISR0_AE3 0x00000008U
4294 #define DSI_ISR0_AE4 0x00000010U
4295 #define DSI_ISR0_AE5 0x00000020U
4296 #define DSI_ISR0_AE6 0x00000040U
4297 #define DSI_ISR0_AE7 0x00000080U
4298 #define DSI_ISR0_AE8 0x00000100U
4299 #define DSI_ISR0_AE9 0x00000200U
4300 #define DSI_ISR0_AE10 0x00000400U
4301 #define DSI_ISR0_AE11 0x00000800U
4302 #define DSI_ISR0_AE12 0x00001000U
4303 #define DSI_ISR0_AE13 0x00002000U
4304 #define DSI_ISR0_AE14 0x00004000U
4305 #define DSI_ISR0_AE15 0x00008000U
4306 #define DSI_ISR0_PE0 0x00010000U
4307 #define DSI_ISR0_PE1 0x00020000U
4308 #define DSI_ISR0_PE2 0x00040000U
4309 #define DSI_ISR0_PE3 0x00080000U
4310 #define DSI_ISR0_PE4 0x00100000U
4312 /******************* Bit definition for DSI_ISR1 register ***************/
4313 #define DSI_ISR1_TOHSTX 0x00000001U
4314 #define DSI_ISR1_TOLPRX 0x00000002U
4315 #define DSI_ISR1_ECCSE 0x00000004U
4316 #define DSI_ISR1_ECCME 0x00000008U
4317 #define DSI_ISR1_CRCE 0x00000010U
4318 #define DSI_ISR1_PSE 0x00000020U
4319 #define DSI_ISR1_EOTPE 0x00000040U
4320 #define DSI_ISR1_LPWRE 0x00000080U
4321 #define DSI_ISR1_GCWRE 0x00000100U
4322 #define DSI_ISR1_GPWRE 0x00000200U
4323 #define DSI_ISR1_GPTXE 0x00000400U
4324 #define DSI_ISR1_GPRDE 0x00000800U
4325 #define DSI_ISR1_GPRXE 0x00001000U
4327 /******************* Bit definition for DSI_IER0 register ***************/
4328 #define DSI_IER0_AE0IE 0x00000001U
4329 #define DSI_IER0_AE1IE 0x00000002U
4330 #define DSI_IER0_AE2IE 0x00000004U
4331 #define DSI_IER0_AE3IE 0x00000008U
4332 #define DSI_IER0_AE4IE 0x00000010U
4333 #define DSI_IER0_AE5IE 0x00000020U
4334 #define DSI_IER0_AE6IE 0x00000040U
4335 #define DSI_IER0_AE7IE 0x00000080U
4336 #define DSI_IER0_AE8IE 0x00000100U
4337 #define DSI_IER0_AE9IE 0x00000200U
4338 #define DSI_IER0_AE10IE 0x00000400U
4339 #define DSI_IER0_AE11IE 0x00000800U
4340 #define DSI_IER0_AE12IE 0x00001000U
4341 #define DSI_IER0_AE13IE 0x00002000U
4342 #define DSI_IER0_AE14IE 0x00004000U
4343 #define DSI_IER0_AE15IE 0x00008000U
4344 #define DSI_IER0_PE0IE 0x00010000U
4345 #define DSI_IER0_PE1IE 0x00020000U
4346 #define DSI_IER0_PE2IE 0x00040000U
4347 #define DSI_IER0_PE3IE 0x00080000U
4348 #define DSI_IER0_PE4IE 0x00100000U
4350 /******************* Bit definition for DSI_IER1 register ***************/
4351 #define DSI_IER1_TOHSTXIE 0x00000001U
4352 #define DSI_IER1_TOLPRXIE 0x00000002U
4353 #define DSI_IER1_ECCSEIE 0x00000004U
4354 #define DSI_IER1_ECCMEIE 0x00000008U
4355 #define DSI_IER1_CRCEIE 0x00000010U
4356 #define DSI_IER1_PSEIE 0x00000020U
4357 #define DSI_IER1_EOTPEIE 0x00000040U
4358 #define DSI_IER1_LPWREIE 0x00000080U
4359 #define DSI_IER1_GCWREIE 0x00000100U
4360 #define DSI_IER1_GPWREIE 0x00000200U
4361 #define DSI_IER1_GPTXEIE 0x00000400U
4362 #define DSI_IER1_GPRDEIE 0x00000800U
4363 #define DSI_IER1_GPRXEIE 0x00001000U
4365 /******************* Bit definition for DSI_FIR0 register ***************/
4366 #define DSI_FIR0_FAE0 0x00000001U
4367 #define DSI_FIR0_FAE1 0x00000002U
4368 #define DSI_FIR0_FAE2 0x00000004U
4369 #define DSI_FIR0_FAE3 0x00000008U
4370 #define DSI_FIR0_FAE4 0x00000010U
4371 #define DSI_FIR0_FAE5 0x00000020U
4372 #define DSI_FIR0_FAE6 0x00000040U
4373 #define DSI_FIR0_FAE7 0x00000080U
4374 #define DSI_FIR0_FAE8 0x00000100U
4375 #define DSI_FIR0_FAE9 0x00000200U
4376 #define DSI_FIR0_FAE10 0x00000400U
4377 #define DSI_FIR0_FAE11 0x00000800U
4378 #define DSI_FIR0_FAE12 0x00001000U
4379 #define DSI_FIR0_FAE13 0x00002000U
4380 #define DSI_FIR0_FAE14 0x00004000U
4381 #define DSI_FIR0_FAE15 0x00008000U
4382 #define DSI_FIR0_FPE0 0x00010000U
4383 #define DSI_FIR0_FPE1 0x00020000U
4384 #define DSI_FIR0_FPE2 0x00040000U
4385 #define DSI_FIR0_FPE3 0x00080000U
4386 #define DSI_FIR0_FPE4 0x00100000U
4388 /******************* Bit definition for DSI_FIR1 register ***************/
4389 #define DSI_FIR1_FTOHSTX 0x00000001U
4390 #define DSI_FIR1_FTOLPRX 0x00000002U
4391 #define DSI_FIR1_FECCSE 0x00000004U
4392 #define DSI_FIR1_FECCME 0x00000008U
4393 #define DSI_FIR1_FCRCE 0x00000010U
4394 #define DSI_FIR1_FPSE 0x00000020U
4395 #define DSI_FIR1_FEOTPE 0x00000040U
4396 #define DSI_FIR1_FLPWRE 0x00000080U
4397 #define DSI_FIR1_FGCWRE 0x00000100U
4398 #define DSI_FIR1_FGPWRE 0x00000200U
4399 #define DSI_FIR1_FGPTXE 0x00000400U
4400 #define DSI_FIR1_FGPRDE 0x00000800U
4401 #define DSI_FIR1_FGPRXE 0x00001000U
4403 /******************* Bit definition for DSI_VSCR register ***************/
4404 #define DSI_VSCR_EN 0x00000001U
4405 #define DSI_VSCR_UR 0x00000100U
4407 /******************* Bit definition for DSI_LCVCIDR register ************/
4408 #define DSI_LCVCIDR_VCID 0x00000003U
4409 #define DSI_LCVCIDR_VCID0 0x00000001U
4410 #define DSI_LCVCIDR_VCID1 0x00000002U
4411 
4412 /******************* Bit definition for DSI_LCCCR register **************/
4413 #define DSI_LCCCR_COLC 0x0000000FU
4414 #define DSI_LCCCR_COLC0 0x00000001U
4415 #define DSI_LCCCR_COLC1 0x00000002U
4416 #define DSI_LCCCR_COLC2 0x00000004U
4417 #define DSI_LCCCR_COLC3 0x00000008U
4418 
4419 #define DSI_LCCCR_LPE 0x00000100U
4421 /******************* Bit definition for DSI_LPMCCR register *************/
4422 #define DSI_LPMCCR_VLPSIZE 0x000000FFU
4423 #define DSI_LPMCCR_VLPSIZE0 0x00000001U
4424 #define DSI_LPMCCR_VLPSIZE1 0x00000002U
4425 #define DSI_LPMCCR_VLPSIZE2 0x00000004U
4426 #define DSI_LPMCCR_VLPSIZE3 0x00000008U
4427 #define DSI_LPMCCR_VLPSIZE4 0x00000010U
4428 #define DSI_LPMCCR_VLPSIZE5 0x00000020U
4429 #define DSI_LPMCCR_VLPSIZE6 0x00000040U
4430 #define DSI_LPMCCR_VLPSIZE7 0x00000080U
4431 
4432 #define DSI_LPMCCR_LPSIZE 0x00FF0000U
4433 #define DSI_LPMCCR_LPSIZE0 0x00010000U
4434 #define DSI_LPMCCR_LPSIZE1 0x00020000U
4435 #define DSI_LPMCCR_LPSIZE2 0x00040000U
4436 #define DSI_LPMCCR_LPSIZE3 0x00080000U
4437 #define DSI_LPMCCR_LPSIZE4 0x00100000U
4438 #define DSI_LPMCCR_LPSIZE5 0x00200000U
4439 #define DSI_LPMCCR_LPSIZE6 0x00400000U
4440 #define DSI_LPMCCR_LPSIZE7 0x00800000U
4441 
4442 /******************* Bit definition for DSI_VMCCR register **************/
4443 #define DSI_VMCCR_VMT 0x00000003U
4444 #define DSI_VMCCR_VMT0 0x00000001U
4445 #define DSI_VMCCR_VMT1 0x00000002U
4446 
4447 #define DSI_VMCCR_LPVSAE 0x00000100U
4448 #define DSI_VMCCR_LPVBPE 0x00000200U
4449 #define DSI_VMCCR_LPVFPE 0x00000400U
4450 #define DSI_VMCCR_LPVAE 0x00000800U
4451 #define DSI_VMCCR_LPHBPE 0x00001000U
4452 #define DSI_VMCCR_LPHFE 0x00002000U
4453 #define DSI_VMCCR_FBTAAE 0x00004000U
4454 #define DSI_VMCCR_LPCE 0x00008000U
4456 /******************* Bit definition for DSI_VPCCR register **************/
4457 #define DSI_VPCCR_VPSIZE 0x00003FFFU
4458 #define DSI_VPCCR_VPSIZE0 0x00000001U
4459 #define DSI_VPCCR_VPSIZE1 0x00000002U
4460 #define DSI_VPCCR_VPSIZE2 0x00000004U
4461 #define DSI_VPCCR_VPSIZE3 0x00000008U
4462 #define DSI_VPCCR_VPSIZE4 0x00000010U
4463 #define DSI_VPCCR_VPSIZE5 0x00000020U
4464 #define DSI_VPCCR_VPSIZE6 0x00000040U
4465 #define DSI_VPCCR_VPSIZE7 0x00000080U
4466 #define DSI_VPCCR_VPSIZE8 0x00000100U
4467 #define DSI_VPCCR_VPSIZE9 0x00000200U
4468 #define DSI_VPCCR_VPSIZE10 0x00000400U
4469 #define DSI_VPCCR_VPSIZE11 0x00000800U
4470 #define DSI_VPCCR_VPSIZE12 0x00001000U
4471 #define DSI_VPCCR_VPSIZE13 0x00002000U
4472 
4473 /******************* Bit definition for DSI_VCCCR register **************/
4474 #define DSI_VCCCR_NUMC 0x00001FFFU
4475 #define DSI_VCCCR_NUMC0 0x00000001U
4476 #define DSI_VCCCR_NUMC1 0x00000002U
4477 #define DSI_VCCCR_NUMC2 0x00000004U
4478 #define DSI_VCCCR_NUMC3 0x00000008U
4479 #define DSI_VCCCR_NUMC4 0x00000010U
4480 #define DSI_VCCCR_NUMC5 0x00000020U
4481 #define DSI_VCCCR_NUMC6 0x00000040U
4482 #define DSI_VCCCR_NUMC7 0x00000080U
4483 #define DSI_VCCCR_NUMC8 0x00000100U
4484 #define DSI_VCCCR_NUMC9 0x00000200U
4485 #define DSI_VCCCR_NUMC10 0x00000400U
4486 #define DSI_VCCCR_NUMC11 0x00000800U
4487 #define DSI_VCCCR_NUMC12 0x00001000U
4488 
4489 /******************* Bit definition for DSI_VNPCCR register *************/
4490 #define DSI_VNPCCR_NPSIZE 0x00001FFFU
4491 #define DSI_VNPCCR_NPSIZE0 0x00000001U
4492 #define DSI_VNPCCR_NPSIZE1 0x00000002U
4493 #define DSI_VNPCCR_NPSIZE2 0x00000004U
4494 #define DSI_VNPCCR_NPSIZE3 0x00000008U
4495 #define DSI_VNPCCR_NPSIZE4 0x00000010U
4496 #define DSI_VNPCCR_NPSIZE5 0x00000020U
4497 #define DSI_VNPCCR_NPSIZE6 0x00000040U
4498 #define DSI_VNPCCR_NPSIZE7 0x00000080U
4499 #define DSI_VNPCCR_NPSIZE8 0x00000100U
4500 #define DSI_VNPCCR_NPSIZE9 0x00000200U
4501 #define DSI_VNPCCR_NPSIZE10 0x00000400U
4502 #define DSI_VNPCCR_NPSIZE11 0x00000800U
4503 #define DSI_VNPCCR_NPSIZE12 0x00001000U
4504 
4505 /******************* Bit definition for DSI_VHSACCR register ************/
4506 #define DSI_VHSACCR_HSA 0x00000FFFU
4507 #define DSI_VHSACCR_HSA0 0x00000001U
4508 #define DSI_VHSACCR_HSA1 0x00000002U
4509 #define DSI_VHSACCR_HSA2 0x00000004U
4510 #define DSI_VHSACCR_HSA3 0x00000008U
4511 #define DSI_VHSACCR_HSA4 0x00000010U
4512 #define DSI_VHSACCR_HSA5 0x00000020U
4513 #define DSI_VHSACCR_HSA6 0x00000040U
4514 #define DSI_VHSACCR_HSA7 0x00000080U
4515 #define DSI_VHSACCR_HSA8 0x00000100U
4516 #define DSI_VHSACCR_HSA9 0x00000200U
4517 #define DSI_VHSACCR_HSA10 0x00000400U
4518 #define DSI_VHSACCR_HSA11 0x00000800U
4519 
4520 /******************* Bit definition for DSI_VHBPCCR register ************/
4521 #define DSI_VHBPCCR_HBP 0x00000FFFU
4522 #define DSI_VHBPCCR_HBP0 0x00000001U
4523 #define DSI_VHBPCCR_HBP1 0x00000002U
4524 #define DSI_VHBPCCR_HBP2 0x00000004U
4525 #define DSI_VHBPCCR_HBP3 0x00000008U
4526 #define DSI_VHBPCCR_HBP4 0x00000010U
4527 #define DSI_VHBPCCR_HBP5 0x00000020U
4528 #define DSI_VHBPCCR_HBP6 0x00000040U
4529 #define DSI_VHBPCCR_HBP7 0x00000080U
4530 #define DSI_VHBPCCR_HBP8 0x00000100U
4531 #define DSI_VHBPCCR_HBP9 0x00000200U
4532 #define DSI_VHBPCCR_HBP10 0x00000400U
4533 #define DSI_VHBPCCR_HBP11 0x00000800U
4534 
4535 /******************* Bit definition for DSI_VLCCR register **************/
4536 #define DSI_VLCCR_HLINE 0x00007FFFU
4537 #define DSI_VLCCR_HLINE0 0x00000001U
4538 #define DSI_VLCCR_HLINE1 0x00000002U
4539 #define DSI_VLCCR_HLINE2 0x00000004U
4540 #define DSI_VLCCR_HLINE3 0x00000008U
4541 #define DSI_VLCCR_HLINE4 0x00000010U
4542 #define DSI_VLCCR_HLINE5 0x00000020U
4543 #define DSI_VLCCR_HLINE6 0x00000040U
4544 #define DSI_VLCCR_HLINE7 0x00000080U
4545 #define DSI_VLCCR_HLINE8 0x00000100U
4546 #define DSI_VLCCR_HLINE9 0x00000200U
4547 #define DSI_VLCCR_HLINE10 0x00000400U
4548 #define DSI_VLCCR_HLINE11 0x00000800U
4549 #define DSI_VLCCR_HLINE12 0x00001000U
4550 #define DSI_VLCCR_HLINE13 0x00002000U
4551 #define DSI_VLCCR_HLINE14 0x00004000U
4552 
4553 /******************* Bit definition for DSI_VVSACCR register ***************/
4554 #define DSI_VVSACCR_VSA 0x000003FFU
4555 #define DSI_VVSACCR_VSA0 0x00000001U
4556 #define DSI_VVSACCR_VSA1 0x00000002U
4557 #define DSI_VVSACCR_VSA2 0x00000004U
4558 #define DSI_VVSACCR_VSA3 0x00000008U
4559 #define DSI_VVSACCR_VSA4 0x00000010U
4560 #define DSI_VVSACCR_VSA5 0x00000020U
4561 #define DSI_VVSACCR_VSA6 0x00000040U
4562 #define DSI_VVSACCR_VSA7 0x00000080U
4563 #define DSI_VVSACCR_VSA8 0x00000100U
4564 #define DSI_VVSACCR_VSA9 0x00000200U
4565 
4566 /******************* Bit definition for DSI_VVBPCCR register ************/
4567 #define DSI_VVBPCCR_VBP 0x000003FFU
4568 #define DSI_VVBPCCR_VBP0 0x00000001U
4569 #define DSI_VVBPCCR_VBP1 0x00000002U
4570 #define DSI_VVBPCCR_VBP2 0x00000004U
4571 #define DSI_VVBPCCR_VBP3 0x00000008U
4572 #define DSI_VVBPCCR_VBP4 0x00000010U
4573 #define DSI_VVBPCCR_VBP5 0x00000020U
4574 #define DSI_VVBPCCR_VBP6 0x00000040U
4575 #define DSI_VVBPCCR_VBP7 0x00000080U
4576 #define DSI_VVBPCCR_VBP8 0x00000100U
4577 #define DSI_VVBPCCR_VBP9 0x00000200U
4578 
4579 /******************* Bit definition for DSI_VVFPCCR register ************/
4580 #define DSI_VVFPCCR_VFP 0x000003FFU
4581 #define DSI_VVFPCCR_VFP0 0x00000001U
4582 #define DSI_VVFPCCR_VFP1 0x00000002U
4583 #define DSI_VVFPCCR_VFP2 0x00000004U
4584 #define DSI_VVFPCCR_VFP3 0x00000008U
4585 #define DSI_VVFPCCR_VFP4 0x00000010U
4586 #define DSI_VVFPCCR_VFP5 0x00000020U
4587 #define DSI_VVFPCCR_VFP6 0x00000040U
4588 #define DSI_VVFPCCR_VFP7 0x00000080U
4589 #define DSI_VVFPCCR_VFP8 0x00000100U
4590 #define DSI_VVFPCCR_VFP9 0x00000200U
4591 
4592 /******************* Bit definition for DSI_VVACCR register *************/
4593 #define DSI_VVACCR_VA 0x00003FFFU
4594 #define DSI_VVACCR_VA0 0x00000001U
4595 #define DSI_VVACCR_VA1 0x00000002U
4596 #define DSI_VVACCR_VA2 0x00000004U
4597 #define DSI_VVACCR_VA3 0x00000008U
4598 #define DSI_VVACCR_VA4 0x00000010U
4599 #define DSI_VVACCR_VA5 0x00000020U
4600 #define DSI_VVACCR_VA6 0x00000040U
4601 #define DSI_VVACCR_VA7 0x00000080U
4602 #define DSI_VVACCR_VA8 0x00000100U
4603 #define DSI_VVACCR_VA9 0x00000200U
4604 #define DSI_VVACCR_VA10 0x00000400U
4605 #define DSI_VVACCR_VA11 0x00000800U
4606 #define DSI_VVACCR_VA12 0x00001000U
4607 #define DSI_VVACCR_VA13 0x00002000U
4608 
4609 /******************* Bit definition for DSI_TDCCR register **************/
4610 #define DSI_TDCCR_3DM 0x00000003U
4611 #define DSI_TDCCR_3DM0 0x00000001U
4612 #define DSI_TDCCR_3DM1 0x00000002U
4613 
4614 #define DSI_TDCCR_3DF 0x0000000CU
4615 #define DSI_TDCCR_3DF0 0x00000004U
4616 #define DSI_TDCCR_3DF1 0x00000008U
4617 
4618 #define DSI_TDCCR_SVS 0x00000010U
4619 #define DSI_TDCCR_RF 0x00000020U
4620 #define DSI_TDCCR_S3DC 0x00010000U
4622 /******************* Bit definition for DSI_WCFGR register ***************/
4623 #define DSI_WCFGR_DSIM 0x00000001U
4624 #define DSI_WCFGR_COLMUX 0x0000000EU
4625 #define DSI_WCFGR_COLMUX0 0x00000002U
4626 #define DSI_WCFGR_COLMUX1 0x00000004U
4627 #define DSI_WCFGR_COLMUX2 0x00000008U
4628 
4629 #define DSI_WCFGR_TESRC 0x00000010U
4630 #define DSI_WCFGR_TEPOL 0x00000020U
4631 #define DSI_WCFGR_AR 0x00000040U
4632 #define DSI_WCFGR_VSPOL 0x00000080U
4634 /******************* Bit definition for DSI_WCR register *****************/
4635 #define DSI_WCR_COLM 0x00000001U
4636 #define DSI_WCR_SHTDN 0x00000002U
4637 #define DSI_WCR_LTDCEN 0x00000004U
4638 #define DSI_WCR_DSIEN 0x00000008U
4640 /******************* Bit definition for DSI_WIER register ****************/
4641 #define DSI_WIER_TEIE 0x00000001U
4642 #define DSI_WIER_ERIE 0x00000002U
4643 #define DSI_WIER_PLLLIE 0x00000200U
4644 #define DSI_WIER_PLLUIE 0x00000400U
4645 #define DSI_WIER_RRIE 0x00002000U
4647 /******************* Bit definition for DSI_WISR register ****************/
4648 #define DSI_WISR_TEIF 0x00000001U
4649 #define DSI_WISR_ERIF 0x00000002U
4650 #define DSI_WISR_BUSY 0x00000004U
4651 #define DSI_WISR_PLLLS 0x00000100U
4652 #define DSI_WISR_PLLLIF 0x00000200U
4653 #define DSI_WISR_PLLUIF 0x00000400U
4654 #define DSI_WISR_RRS 0x00001000U
4655 #define DSI_WISR_RRIF 0x00002000U
4657 /******************* Bit definition for DSI_WIFCR register ***************/
4658 #define DSI_WIFCR_CTEIF 0x00000001U
4659 #define DSI_WIFCR_CERIF 0x00000002U
4660 #define DSI_WIFCR_CPLLLIF 0x00000200U
4661 #define DSI_WIFCR_CPLLUIF 0x00000400U
4662 #define DSI_WIFCR_CRRIF 0x00002000U
4664 /******************* Bit definition for DSI_WPCR0 register ***************/
4665 #define DSI_WPCR0_UIX4 0x0000003FU
4666 #define DSI_WPCR0_UIX4_0 0x00000001U
4667 #define DSI_WPCR0_UIX4_1 0x00000002U
4668 #define DSI_WPCR0_UIX4_2 0x00000004U
4669 #define DSI_WPCR0_UIX4_3 0x00000008U
4670 #define DSI_WPCR0_UIX4_4 0x00000010U
4671 #define DSI_WPCR0_UIX4_5 0x00000020U
4672 
4673 #define DSI_WPCR0_SWCL 0x00000040U
4674 #define DSI_WPCR0_SWDL0 0x00000080U
4675 #define DSI_WPCR0_SWDL1 0x00000100U
4676 #define DSI_WPCR0_HSICL 0x00000200U
4677 #define DSI_WPCR0_HSIDL0 0x00000400U
4678 #define DSI_WPCR0_HSIDL1 0x00000800U
4679 #define DSI_WPCR0_FTXSMCL 0x00001000U
4680 #define DSI_WPCR0_FTXSMDL 0x00002000U
4681 #define DSI_WPCR0_CDOFFDL 0x00004000U
4682 #define DSI_WPCR0_TDDL 0x00010000U
4683 #define DSI_WPCR0_PDEN 0x00040000U
4684 #define DSI_WPCR0_TCLKPREPEN 0x00080000U
4685 #define DSI_WPCR0_TCLKZEROEN 0x00100000U
4686 #define DSI_WPCR0_THSPREPEN 0x00200000U
4687 #define DSI_WPCR0_THSTRAILEN 0x00400000U
4688 #define DSI_WPCR0_THSZEROEN 0x00800000U
4689 #define DSI_WPCR0_TLPXDEN 0x01000000U
4690 #define DSI_WPCR0_THSEXITEN 0x02000000U
4691 #define DSI_WPCR0_TLPXCEN 0x04000000U
4692 #define DSI_WPCR0_TCLKPOSTEN 0x08000000U
4694 /******************* Bit definition for DSI_WPCR1 register ***************/
4695 #define DSI_WPCR1_HSTXDCL 0x00000003U
4696 #define DSI_WPCR1_HSTXDCL0 0x00000001U
4697 #define DSI_WPCR1_HSTXDCL1 0x00000002U
4698 
4699 #define DSI_WPCR1_HSTXDDL 0x0000000CU
4700 #define DSI_WPCR1_HSTXDDL0 0x00000004U
4701 #define DSI_WPCR1_HSTXDDL1 0x00000008U
4702 
4703 #define DSI_WPCR1_LPSRCCL 0x000000C0U
4704 #define DSI_WPCR1_LPSRCCL0 0x00000040U
4705 #define DSI_WPCR1_LPSRCCL1 0x00000080U
4706 
4707 #define DSI_WPCR1_LPSRCDL 0x00000300U
4708 #define DSI_WPCR1_LPSRCDL0 0x00000100U
4709 #define DSI_WPCR1_LPSRCDL1 0x00000200U
4710 
4711 #define DSI_WPCR1_SDDC 0x00001000U
4713 #define DSI_WPCR1_LPRXVCDL 0x0000C000U
4714 #define DSI_WPCR1_LPRXVCDL0 0x00004000U
4715 #define DSI_WPCR1_LPRXVCDL1 0x00008000U
4716 
4717 #define DSI_WPCR1_HSTXSRCCL 0x00030000U
4718 #define DSI_WPCR1_HSTXSRCCL0 0x00010000U
4719 #define DSI_WPCR1_HSTXSRCCL1 0x00020000U
4720 
4721 #define DSI_WPCR1_HSTXSRCDL 0x000C0000U
4722 #define DSI_WPCR1_HSTXSRCDL0 0x00040000U
4723 #define DSI_WPCR1_HSTXSRCDL1 0x00080000U
4724 
4725 #define DSI_WPCR1_FLPRXLPM 0x00400000U
4727 #define DSI_WPCR1_LPRXFT 0x06000000U
4728 #define DSI_WPCR1_LPRXFT0 0x02000000U
4729 #define DSI_WPCR1_LPRXFT1 0x04000000U
4730 
4731 /******************* Bit definition for DSI_WPCR2 register ***************/
4732 #define DSI_WPCR2_TCLKPREP 0x000000FFU
4733 #define DSI_WPCR2_TCLKPREP0 0x00000001U
4734 #define DSI_WPCR2_TCLKPREP1 0x00000002U
4735 #define DSI_WPCR2_TCLKPREP2 0x00000004U
4736 #define DSI_WPCR2_TCLKPREP3 0x00000008U
4737 #define DSI_WPCR2_TCLKPREP4 0x00000010U
4738 #define DSI_WPCR2_TCLKPREP5 0x00000020U
4739 #define DSI_WPCR2_TCLKPREP6 0x00000040U
4740 #define DSI_WPCR2_TCLKPREP7 0x00000080U
4741 
4742 #define DSI_WPCR2_TCLKZERO 0x0000FF00U
4743 #define DSI_WPCR2_TCLKZERO0 0x00000100U
4744 #define DSI_WPCR2_TCLKZERO1 0x00000200U
4745 #define DSI_WPCR2_TCLKZERO2 0x00000400U
4746 #define DSI_WPCR2_TCLKZERO3 0x00000800U
4747 #define DSI_WPCR2_TCLKZERO4 0x00001000U
4748 #define DSI_WPCR2_TCLKZERO5 0x00002000U
4749 #define DSI_WPCR2_TCLKZERO6 0x00004000U
4750 #define DSI_WPCR2_TCLKZERO7 0x00008000U
4751 
4752 #define DSI_WPCR2_THSPREP 0x00FF0000U
4753 #define DSI_WPCR2_THSPREP0 0x00010000U
4754 #define DSI_WPCR2_THSPREP1 0x00020000U
4755 #define DSI_WPCR2_THSPREP2 0x00040000U
4756 #define DSI_WPCR2_THSPREP3 0x00080000U
4757 #define DSI_WPCR2_THSPREP4 0x00100000U
4758 #define DSI_WPCR2_THSPREP5 0x00200000U
4759 #define DSI_WPCR2_THSPREP6 0x00400000U
4760 #define DSI_WPCR2_THSPREP7 0x00800000U
4761 
4762 #define DSI_WPCR2_THSTRAIL 0xFF000000U
4763 #define DSI_WPCR2_THSTRAIL0 0x01000000U
4764 #define DSI_WPCR2_THSTRAIL1 0x02000000U
4765 #define DSI_WPCR2_THSTRAIL2 0x04000000U
4766 #define DSI_WPCR2_THSTRAIL3 0x08000000U
4767 #define DSI_WPCR2_THSTRAIL4 0x10000000U
4768 #define DSI_WPCR2_THSTRAIL5 0x20000000U
4769 #define DSI_WPCR2_THSTRAIL6 0x40000000U
4770 #define DSI_WPCR2_THSTRAIL7 0x80000000U
4771 
4772 /******************* Bit definition for DSI_WPCR3 register ***************/
4773 #define DSI_WPCR3_THSZERO 0x000000FFU
4774 #define DSI_WPCR3_THSZERO0 0x00000001U
4775 #define DSI_WPCR3_THSZERO1 0x00000002U
4776 #define DSI_WPCR3_THSZERO2 0x00000004U
4777 #define DSI_WPCR3_THSZERO3 0x00000008U
4778 #define DSI_WPCR3_THSZERO4 0x00000010U
4779 #define DSI_WPCR3_THSZERO5 0x00000020U
4780 #define DSI_WPCR3_THSZERO6 0x00000040U
4781 #define DSI_WPCR3_THSZERO7 0x00000080U
4782 
4783 #define DSI_WPCR3_TLPXD 0x0000FF00U
4784 #define DSI_WPCR3_TLPXD0 0x00000100U
4785 #define DSI_WPCR3_TLPXD1 0x00000200U
4786 #define DSI_WPCR3_TLPXD2 0x00000400U
4787 #define DSI_WPCR3_TLPXD3 0x00000800U
4788 #define DSI_WPCR3_TLPXD4 0x00001000U
4789 #define DSI_WPCR3_TLPXD5 0x00002000U
4790 #define DSI_WPCR3_TLPXD6 0x00004000U
4791 #define DSI_WPCR3_TLPXD7 0x00008000U
4792 
4793 #define DSI_WPCR3_THSEXIT 0x00FF0000U
4794 #define DSI_WPCR3_THSEXIT0 0x00010000U
4795 #define DSI_WPCR3_THSEXIT1 0x00020000U
4796 #define DSI_WPCR3_THSEXIT2 0x00040000U
4797 #define DSI_WPCR3_THSEXIT3 0x00080000U
4798 #define DSI_WPCR3_THSEXIT4 0x00100000U
4799 #define DSI_WPCR3_THSEXIT5 0x00200000U
4800 #define DSI_WPCR3_THSEXIT6 0x00400000U
4801 #define DSI_WPCR3_THSEXIT7 0x00800000U
4802 
4803 #define DSI_WPCR3_TLPXC 0xFF000000U
4804 #define DSI_WPCR3_TLPXC0 0x01000000U
4805 #define DSI_WPCR3_TLPXC1 0x02000000U
4806 #define DSI_WPCR3_TLPXC2 0x04000000U
4807 #define DSI_WPCR3_TLPXC3 0x08000000U
4808 #define DSI_WPCR3_TLPXC4 0x10000000U
4809 #define DSI_WPCR3_TLPXC5 0x20000000U
4810 #define DSI_WPCR3_TLPXC6 0x40000000U
4811 #define DSI_WPCR3_TLPXC7 0x80000000U
4812 
4813 /******************* Bit definition for DSI_WPCR4 register ***************/
4814 #define DSI_WPCR4_TCLKPOST 0x000000FFU
4815 #define DSI_WPCR4_TCLKPOST0 0x00000001U
4816 #define DSI_WPCR4_TCLKPOST1 0x00000002U
4817 #define DSI_WPCR4_TCLKPOST2 0x00000004U
4818 #define DSI_WPCR4_TCLKPOST3 0x00000008U
4819 #define DSI_WPCR4_TCLKPOST4 0x00000010U
4820 #define DSI_WPCR4_TCLKPOST5 0x00000020U
4821 #define DSI_WPCR4_TCLKPOST6 0x00000040U
4822 #define DSI_WPCR4_TCLKPOST7 0x00000080U
4823 
4824 /******************* Bit definition for DSI_WRPCR register ***************/
4825 #define DSI_WRPCR_PLLEN 0x00000001U
4826 #define DSI_WRPCR_PLL_NDIV 0x000001FCU
4827 #define DSI_WRPCR_PLL_NDIV0 0x00000004U
4828 #define DSI_WRPCR_PLL_NDIV1 0x00000008U
4829 #define DSI_WRPCR_PLL_NDIV2 0x00000010U
4830 #define DSI_WRPCR_PLL_NDIV3 0x00000020U
4831 #define DSI_WRPCR_PLL_NDIV4 0x00000040U
4832 #define DSI_WRPCR_PLL_NDIV5 0x00000080U
4833 #define DSI_WRPCR_PLL_NDIV6 0x00000100U
4834 
4835 #define DSI_WRPCR_PLL_IDF 0x00007800U
4836 #define DSI_WRPCR_PLL_IDF0 0x00000800U
4837 #define DSI_WRPCR_PLL_IDF1 0x00001000U
4838 #define DSI_WRPCR_PLL_IDF2 0x00002000U
4839 #define DSI_WRPCR_PLL_IDF3 0x00004000U
4840 
4841 #define DSI_WRPCR_PLL_ODF 0x00030000U
4842 #define DSI_WRPCR_PLL_ODF0 0x00010000U
4843 #define DSI_WRPCR_PLL_ODF1 0x00020000U
4844 
4845 #define DSI_WRPCR_REGEN 0x01000000U
4847 /******************************************************************************/
4848 /* */
4849 /* External Interrupt/Event Controller */
4850 /* */
4851 /******************************************************************************/
4852 /******************* Bit definition for EXTI_IMR register *******************/
4853 #define EXTI_IMR_MR0 0x00000001U
4854 #define EXTI_IMR_MR1 0x00000002U
4855 #define EXTI_IMR_MR2 0x00000004U
4856 #define EXTI_IMR_MR3 0x00000008U
4857 #define EXTI_IMR_MR4 0x00000010U
4858 #define EXTI_IMR_MR5 0x00000020U
4859 #define EXTI_IMR_MR6 0x00000040U
4860 #define EXTI_IMR_MR7 0x00000080U
4861 #define EXTI_IMR_MR8 0x00000100U
4862 #define EXTI_IMR_MR9 0x00000200U
4863 #define EXTI_IMR_MR10 0x00000400U
4864 #define EXTI_IMR_MR11 0x00000800U
4865 #define EXTI_IMR_MR12 0x00001000U
4866 #define EXTI_IMR_MR13 0x00002000U
4867 #define EXTI_IMR_MR14 0x00004000U
4868 #define EXTI_IMR_MR15 0x00008000U
4869 #define EXTI_IMR_MR16 0x00010000U
4870 #define EXTI_IMR_MR17 0x00020000U
4871 #define EXTI_IMR_MR18 0x00040000U
4872 #define EXTI_IMR_MR19 0x00080000U
4873 #define EXTI_IMR_MR20 0x00100000U
4874 #define EXTI_IMR_MR21 0x00200000U
4875 #define EXTI_IMR_MR22 0x00400000U
4877 /******************* Bit definition for EXTI_EMR register *******************/
4878 #define EXTI_EMR_MR0 0x00000001U
4879 #define EXTI_EMR_MR1 0x00000002U
4880 #define EXTI_EMR_MR2 0x00000004U
4881 #define EXTI_EMR_MR3 0x00000008U
4882 #define EXTI_EMR_MR4 0x00000010U
4883 #define EXTI_EMR_MR5 0x00000020U
4884 #define EXTI_EMR_MR6 0x00000040U
4885 #define EXTI_EMR_MR7 0x00000080U
4886 #define EXTI_EMR_MR8 0x00000100U
4887 #define EXTI_EMR_MR9 0x00000200U
4888 #define EXTI_EMR_MR10 0x00000400U
4889 #define EXTI_EMR_MR11 0x00000800U
4890 #define EXTI_EMR_MR12 0x00001000U
4891 #define EXTI_EMR_MR13 0x00002000U
4892 #define EXTI_EMR_MR14 0x00004000U
4893 #define EXTI_EMR_MR15 0x00008000U
4894 #define EXTI_EMR_MR16 0x00010000U
4895 #define EXTI_EMR_MR17 0x00020000U
4896 #define EXTI_EMR_MR18 0x00040000U
4897 #define EXTI_EMR_MR19 0x00080000U
4898 #define EXTI_EMR_MR20 0x00100000U
4899 #define EXTI_EMR_MR21 0x00200000U
4900 #define EXTI_EMR_MR22 0x00400000U
4902 /****************** Bit definition for EXTI_RTSR register *******************/
4903 #define EXTI_RTSR_TR0 0x00000001U
4904 #define EXTI_RTSR_TR1 0x00000002U
4905 #define EXTI_RTSR_TR2 0x00000004U
4906 #define EXTI_RTSR_TR3 0x00000008U
4907 #define EXTI_RTSR_TR4 0x00000010U
4908 #define EXTI_RTSR_TR5 0x00000020U
4909 #define EXTI_RTSR_TR6 0x00000040U
4910 #define EXTI_RTSR_TR7 0x00000080U
4911 #define EXTI_RTSR_TR8 0x00000100U
4912 #define EXTI_RTSR_TR9 0x00000200U
4913 #define EXTI_RTSR_TR10 0x00000400U
4914 #define EXTI_RTSR_TR11 0x00000800U
4915 #define EXTI_RTSR_TR12 0x00001000U
4916 #define EXTI_RTSR_TR13 0x00002000U
4917 #define EXTI_RTSR_TR14 0x00004000U
4918 #define EXTI_RTSR_TR15 0x00008000U
4919 #define EXTI_RTSR_TR16 0x00010000U
4920 #define EXTI_RTSR_TR17 0x00020000U
4921 #define EXTI_RTSR_TR18 0x00040000U
4922 #define EXTI_RTSR_TR19 0x00080000U
4923 #define EXTI_RTSR_TR20 0x00100000U
4924 #define EXTI_RTSR_TR21 0x00200000U
4925 #define EXTI_RTSR_TR22 0x00400000U
4927 /****************** Bit definition for EXTI_FTSR register *******************/
4928 #define EXTI_FTSR_TR0 0x00000001U
4929 #define EXTI_FTSR_TR1 0x00000002U
4930 #define EXTI_FTSR_TR2 0x00000004U
4931 #define EXTI_FTSR_TR3 0x00000008U
4932 #define EXTI_FTSR_TR4 0x00000010U
4933 #define EXTI_FTSR_TR5 0x00000020U
4934 #define EXTI_FTSR_TR6 0x00000040U
4935 #define EXTI_FTSR_TR7 0x00000080U
4936 #define EXTI_FTSR_TR8 0x00000100U
4937 #define EXTI_FTSR_TR9 0x00000200U
4938 #define EXTI_FTSR_TR10 0x00000400U
4939 #define EXTI_FTSR_TR11 0x00000800U
4940 #define EXTI_FTSR_TR12 0x00001000U
4941 #define EXTI_FTSR_TR13 0x00002000U
4942 #define EXTI_FTSR_TR14 0x00004000U
4943 #define EXTI_FTSR_TR15 0x00008000U
4944 #define EXTI_FTSR_TR16 0x00010000U
4945 #define EXTI_FTSR_TR17 0x00020000U
4946 #define EXTI_FTSR_TR18 0x00040000U
4947 #define EXTI_FTSR_TR19 0x00080000U
4948 #define EXTI_FTSR_TR20 0x00100000U
4949 #define EXTI_FTSR_TR21 0x00200000U
4950 #define EXTI_FTSR_TR22 0x00400000U
4952 /****************** Bit definition for EXTI_SWIER register ******************/
4953 #define EXTI_SWIER_SWIER0 0x00000001U
4954 #define EXTI_SWIER_SWIER1 0x00000002U
4955 #define EXTI_SWIER_SWIER2 0x00000004U
4956 #define EXTI_SWIER_SWIER3 0x00000008U
4957 #define EXTI_SWIER_SWIER4 0x00000010U
4958 #define EXTI_SWIER_SWIER5 0x00000020U
4959 #define EXTI_SWIER_SWIER6 0x00000040U
4960 #define EXTI_SWIER_SWIER7 0x00000080U
4961 #define EXTI_SWIER_SWIER8 0x00000100U
4962 #define EXTI_SWIER_SWIER9 0x00000200U
4963 #define EXTI_SWIER_SWIER10 0x00000400U
4964 #define EXTI_SWIER_SWIER11 0x00000800U
4965 #define EXTI_SWIER_SWIER12 0x00001000U
4966 #define EXTI_SWIER_SWIER13 0x00002000U
4967 #define EXTI_SWIER_SWIER14 0x00004000U
4968 #define EXTI_SWIER_SWIER15 0x00008000U
4969 #define EXTI_SWIER_SWIER16 0x00010000U
4970 #define EXTI_SWIER_SWIER17 0x00020000U
4971 #define EXTI_SWIER_SWIER18 0x00040000U
4972 #define EXTI_SWIER_SWIER19 0x00080000U
4973 #define EXTI_SWIER_SWIER20 0x00100000U
4974 #define EXTI_SWIER_SWIER21 0x00200000U
4975 #define EXTI_SWIER_SWIER22 0x00400000U
4977 /******************* Bit definition for EXTI_PR register ********************/
4978 #define EXTI_PR_PR0 0x00000001U
4979 #define EXTI_PR_PR1 0x00000002U
4980 #define EXTI_PR_PR2 0x00000004U
4981 #define EXTI_PR_PR3 0x00000008U
4982 #define EXTI_PR_PR4 0x00000010U
4983 #define EXTI_PR_PR5 0x00000020U
4984 #define EXTI_PR_PR6 0x00000040U
4985 #define EXTI_PR_PR7 0x00000080U
4986 #define EXTI_PR_PR8 0x00000100U
4987 #define EXTI_PR_PR9 0x00000200U
4988 #define EXTI_PR_PR10 0x00000400U
4989 #define EXTI_PR_PR11 0x00000800U
4990 #define EXTI_PR_PR12 0x00001000U
4991 #define EXTI_PR_PR13 0x00002000U
4992 #define EXTI_PR_PR14 0x00004000U
4993 #define EXTI_PR_PR15 0x00008000U
4994 #define EXTI_PR_PR16 0x00010000U
4995 #define EXTI_PR_PR17 0x00020000U
4996 #define EXTI_PR_PR18 0x00040000U
4997 #define EXTI_PR_PR19 0x00080000U
4998 #define EXTI_PR_PR20 0x00100000U
4999 #define EXTI_PR_PR21 0x00200000U
5000 #define EXTI_PR_PR22 0x00400000U
5002 /******************************************************************************/
5003 /* */
5004 /* FLASH */
5005 /* */
5006 /******************************************************************************/
5007 /******************* Bits definition for FLASH_ACR register *****************/
5008 #define FLASH_ACR_LATENCY 0x0000000FU
5009 #define FLASH_ACR_LATENCY_0WS 0x00000000U
5010 #define FLASH_ACR_LATENCY_1WS 0x00000001U
5011 #define FLASH_ACR_LATENCY_2WS 0x00000002U
5012 #define FLASH_ACR_LATENCY_3WS 0x00000003U
5013 #define FLASH_ACR_LATENCY_4WS 0x00000004U
5014 #define FLASH_ACR_LATENCY_5WS 0x00000005U
5015 #define FLASH_ACR_LATENCY_6WS 0x00000006U
5016 #define FLASH_ACR_LATENCY_7WS 0x00000007U
5017 #define FLASH_ACR_LATENCY_8WS 0x00000008U
5018 #define FLASH_ACR_LATENCY_9WS 0x00000009U
5019 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
5020 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
5021 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
5022 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
5023 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
5024 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
5025 #define FLASH_ACR_PRFTEN 0x00000100U
5026 #define FLASH_ACR_ICEN 0x00000200U
5027 #define FLASH_ACR_DCEN 0x00000400U
5028 #define FLASH_ACR_ICRST 0x00000800U
5029 #define FLASH_ACR_DCRST 0x00001000U
5030 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
5031 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
5032 
5033 /******************* Bits definition for FLASH_SR register ******************/
5034 #define FLASH_SR_EOP 0x00000001U
5035 #define FLASH_SR_SOP 0x00000002U
5036 #define FLASH_SR_WRPERR 0x00000010U
5037 #define FLASH_SR_PGAERR 0x00000020U
5038 #define FLASH_SR_PGPERR 0x00000040U
5039 #define FLASH_SR_PGSERR 0x00000080U
5040 #define FLASH_SR_BSY 0x00010000U
5041 
5042 /******************* Bits definition for FLASH_CR register ******************/
5043 #define FLASH_CR_PG 0x00000001U
5044 #define FLASH_CR_SER 0x00000002U
5045 #define FLASH_CR_MER 0x00000004U
5046 #define FLASH_CR_MER1 FLASH_CR_MER
5047 #define FLASH_CR_SNB 0x000000F8U
5048 #define FLASH_CR_SNB_0 0x00000008U
5049 #define FLASH_CR_SNB_1 0x00000010U
5050 #define FLASH_CR_SNB_2 0x00000020U
5051 #define FLASH_CR_SNB_3 0x00000040U
5052 #define FLASH_CR_SNB_4 0x00000080U
5053 #define FLASH_CR_PSIZE 0x00000300U
5054 #define FLASH_CR_PSIZE_0 0x00000100U
5055 #define FLASH_CR_PSIZE_1 0x00000200U
5056 #define FLASH_CR_MER2 0x00008000U
5057 #define FLASH_CR_STRT 0x00010000U
5058 #define FLASH_CR_EOPIE 0x01000000U
5059 #define FLASH_CR_LOCK 0x80000000U
5060 
5061 /******************* Bits definition for FLASH_OPTCR register ***************/
5062 #define FLASH_OPTCR_OPTLOCK 0x00000001U
5063 #define FLASH_OPTCR_OPTSTRT 0x00000002U
5064 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
5065 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
5066 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
5067 #define FLASH_OPTCR_BFB2 0x00000010U
5068 #define FLASH_OPTCR_WDG_SW 0x00000020U
5069 #define FLASH_OPTCR_nRST_STOP 0x00000040U
5070 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
5071 #define FLASH_OPTCR_RDP 0x0000FF00U
5072 #define FLASH_OPTCR_RDP_0 0x00000100U
5073 #define FLASH_OPTCR_RDP_1 0x00000200U
5074 #define FLASH_OPTCR_RDP_2 0x00000400U
5075 #define FLASH_OPTCR_RDP_3 0x00000800U
5076 #define FLASH_OPTCR_RDP_4 0x00001000U
5077 #define FLASH_OPTCR_RDP_5 0x00002000U
5078 #define FLASH_OPTCR_RDP_6 0x00004000U
5079 #define FLASH_OPTCR_RDP_7 0x00008000U
5080 #define FLASH_OPTCR_nWRP 0x0FFF0000U
5081 #define FLASH_OPTCR_nWRP_0 0x00010000U
5082 #define FLASH_OPTCR_nWRP_1 0x00020000U
5083 #define FLASH_OPTCR_nWRP_2 0x00040000U
5084 #define FLASH_OPTCR_nWRP_3 0x00080000U
5085 #define FLASH_OPTCR_nWRP_4 0x00100000U
5086 #define FLASH_OPTCR_nWRP_5 0x00200000U
5087 #define FLASH_OPTCR_nWRP_6 0x00400000U
5088 #define FLASH_OPTCR_nWRP_7 0x00800000U
5089 #define FLASH_OPTCR_nWRP_8 0x01000000U
5090 #define FLASH_OPTCR_nWRP_9 0x02000000U
5091 #define FLASH_OPTCR_nWRP_10 0x04000000U
5092 #define FLASH_OPTCR_nWRP_11 0x08000000U
5093 #define FLASH_OPTCR_DB1M 0x40000000U
5094 #define FLASH_OPTCR_SPRMOD 0x80000000U
5095 
5096 /****************** Bits definition for FLASH_OPTCR1 register ***************/
5097 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
5098 #define FLASH_OPTCR1_nWRP_0 0x00010000U
5099 #define FLASH_OPTCR1_nWRP_1 0x00020000U
5100 #define FLASH_OPTCR1_nWRP_2 0x00040000U
5101 #define FLASH_OPTCR1_nWRP_3 0x00080000U
5102 #define FLASH_OPTCR1_nWRP_4 0x00100000U
5103 #define FLASH_OPTCR1_nWRP_5 0x00200000U
5104 #define FLASH_OPTCR1_nWRP_6 0x00400000U
5105 #define FLASH_OPTCR1_nWRP_7 0x00800000U
5106 #define FLASH_OPTCR1_nWRP_8 0x01000000U
5107 #define FLASH_OPTCR1_nWRP_9 0x02000000U
5108 #define FLASH_OPTCR1_nWRP_10 0x04000000U
5109 #define FLASH_OPTCR1_nWRP_11 0x08000000U
5110 
5111 /******************************************************************************/
5112 /* */
5113 /* Flexible Memory Controller */
5114 /* */
5115 /******************************************************************************/
5116 /****************** Bit definition for FMC_BCR1 register *******************/
5117 #define FMC_BCR1_MBKEN 0x00000001U
5118 #define FMC_BCR1_MUXEN 0x00000002U
5120 #define FMC_BCR1_MTYP 0x0000000CU
5121 #define FMC_BCR1_MTYP_0 0x00000004U
5122 #define FMC_BCR1_MTYP_1 0x00000008U
5124 #define FMC_BCR1_MWID 0x00000030U
5125 #define FMC_BCR1_MWID_0 0x00000010U
5126 #define FMC_BCR1_MWID_1 0x00000020U
5128 #define FMC_BCR1_FACCEN 0x00000040U
5129 #define FMC_BCR1_BURSTEN 0x00000100U
5130 #define FMC_BCR1_WAITPOL 0x00000200U
5131 #define FMC_BCR1_WAITCFG 0x00000800U
5132 #define FMC_BCR1_WREN 0x00001000U
5133 #define FMC_BCR1_WAITEN 0x00002000U
5134 #define FMC_BCR1_EXTMOD 0x00004000U
5135 #define FMC_BCR1_ASYNCWAIT 0x00008000U
5136 #define FMC_BCR1_CPSIZE 0x00070000U
5137 #define FMC_BCR1_CPSIZE_0 0x00010000U
5138 #define FMC_BCR1_CPSIZE_1 0x00020000U
5139 #define FMC_BCR1_CPSIZE_2 0x00040000U
5140 #define FMC_BCR1_CBURSTRW 0x00080000U
5141 #define FMC_BCR1_CCLKEN 0x00100000U
5142 #define FMC_BCR1_WFDIS 0x00200000U
5144 /****************** Bit definition for FMC_BCR2 register *******************/
5145 #define FMC_BCR2_MBKEN 0x00000001U
5146 #define FMC_BCR2_MUXEN 0x00000002U
5148 #define FMC_BCR2_MTYP 0x0000000CU
5149 #define FMC_BCR2_MTYP_0 0x00000004U
5150 #define FMC_BCR2_MTYP_1 0x00000008U
5152 #define FMC_BCR2_MWID 0x00000030U
5153 #define FMC_BCR2_MWID_0 0x00000010U
5154 #define FMC_BCR2_MWID_1 0x00000020U
5156 #define FMC_BCR2_FACCEN 0x00000040U
5157 #define FMC_BCR2_BURSTEN 0x00000100U
5158 #define FMC_BCR2_WAITPOL 0x00000200U
5159 #define FMC_BCR2_WAITCFG 0x00000800U
5160 #define FMC_BCR2_WREN 0x00001000U
5161 #define FMC_BCR2_WAITEN 0x00002000U
5162 #define FMC_BCR2_EXTMOD 0x00004000U
5163 #define FMC_BCR2_ASYNCWAIT 0x00008000U
5164 #define FMC_BCR2_CBURSTRW 0x00080000U
5166 /****************** Bit definition for FMC_BCR3 register *******************/
5167 #define FMC_BCR3_MBKEN 0x00000001U
5168 #define FMC_BCR3_MUXEN 0x00000002U
5170 #define FMC_BCR3_MTYP 0x0000000CU
5171 #define FMC_BCR3_MTYP_0 0x00000004U
5172 #define FMC_BCR3_MTYP_1 0x00000008U
5174 #define FMC_BCR3_MWID 0x00000030U
5175 #define FMC_BCR3_MWID_0 0x00000010U
5176 #define FMC_BCR3_MWID_1 0x00000020U
5178 #define FMC_BCR3_FACCEN 0x00000040U
5179 #define FMC_BCR3_BURSTEN 0x00000100U
5180 #define FMC_BCR3_WAITPOL 0x00000200U
5181 #define FMC_BCR3_WAITCFG 0x00000800U
5182 #define FMC_BCR3_WREN 0x00001000U
5183 #define FMC_BCR3_WAITEN 0x00002000U
5184 #define FMC_BCR3_EXTMOD 0x00004000U
5185 #define FMC_BCR3_ASYNCWAIT 0x00008000U
5186 #define FMC_BCR3_CBURSTRW 0x00080000U
5188 /****************** Bit definition for FMC_BCR4 register *******************/
5189 #define FMC_BCR4_MBKEN 0x00000001U
5190 #define FMC_BCR4_MUXEN 0x00000002U
5192 #define FMC_BCR4_MTYP 0x0000000CU
5193 #define FMC_BCR4_MTYP_0 0x00000004U
5194 #define FMC_BCR4_MTYP_1 0x00000008U
5196 #define FMC_BCR4_MWID 0x00000030U
5197 #define FMC_BCR4_MWID_0 0x00000010U
5198 #define FMC_BCR4_MWID_1 0x00000020U
5200 #define FMC_BCR4_FACCEN 0x00000040U
5201 #define FMC_BCR4_BURSTEN 0x00000100U
5202 #define FMC_BCR4_WAITPOL 0x00000200U
5203 #define FMC_BCR4_WAITCFG 0x00000800U
5204 #define FMC_BCR4_WREN 0x00001000U
5205 #define FMC_BCR4_WAITEN 0x00002000U
5206 #define FMC_BCR4_EXTMOD 0x00004000U
5207 #define FMC_BCR4_ASYNCWAIT 0x00008000U
5208 #define FMC_BCR4_CBURSTRW 0x00080000U
5210 /****************** Bit definition for FMC_BTR1 register ******************/
5211 #define FMC_BTR1_ADDSET 0x0000000FU
5212 #define FMC_BTR1_ADDSET_0 0x00000001U
5213 #define FMC_BTR1_ADDSET_1 0x00000002U
5214 #define FMC_BTR1_ADDSET_2 0x00000004U
5215 #define FMC_BTR1_ADDSET_3 0x00000008U
5217 #define FMC_BTR1_ADDHLD 0x000000F0U
5218 #define FMC_BTR1_ADDHLD_0 0x00000010U
5219 #define FMC_BTR1_ADDHLD_1 0x00000020U
5220 #define FMC_BTR1_ADDHLD_2 0x00000040U
5221 #define FMC_BTR1_ADDHLD_3 0x00000080U
5223 #define FMC_BTR1_DATAST 0x0000FF00U
5224 #define FMC_BTR1_DATAST_0 0x00000100U
5225 #define FMC_BTR1_DATAST_1 0x00000200U
5226 #define FMC_BTR1_DATAST_2 0x00000400U
5227 #define FMC_BTR1_DATAST_3 0x00000800U
5228 #define FMC_BTR1_DATAST_4 0x00001000U
5229 #define FMC_BTR1_DATAST_5 0x00002000U
5230 #define FMC_BTR1_DATAST_6 0x00004000U
5231 #define FMC_BTR1_DATAST_7 0x00008000U
5233 #define FMC_BTR1_BUSTURN 0x000F0000U
5234 #define FMC_BTR1_BUSTURN_0 0x00010000U
5235 #define FMC_BTR1_BUSTURN_1 0x00020000U
5236 #define FMC_BTR1_BUSTURN_2 0x00040000U
5237 #define FMC_BTR1_BUSTURN_3 0x00080000U
5239 #define FMC_BTR1_CLKDIV 0x00F00000U
5240 #define FMC_BTR1_CLKDIV_0 0x00100000U
5241 #define FMC_BTR1_CLKDIV_1 0x00200000U
5242 #define FMC_BTR1_CLKDIV_2 0x00400000U
5243 #define FMC_BTR1_CLKDIV_3 0x00800000U
5245 #define FMC_BTR1_DATLAT 0x0F000000U
5246 #define FMC_BTR1_DATLAT_0 0x01000000U
5247 #define FMC_BTR1_DATLAT_1 0x02000000U
5248 #define FMC_BTR1_DATLAT_2 0x04000000U
5249 #define FMC_BTR1_DATLAT_3 0x08000000U
5251 #define FMC_BTR1_ACCMOD 0x30000000U
5252 #define FMC_BTR1_ACCMOD_0 0x10000000U
5253 #define FMC_BTR1_ACCMOD_1 0x20000000U
5255 /****************** Bit definition for FMC_BTR2 register *******************/
5256 #define FMC_BTR2_ADDSET 0x0000000FU
5257 #define FMC_BTR2_ADDSET_0 0x00000001U
5258 #define FMC_BTR2_ADDSET_1 0x00000002U
5259 #define FMC_BTR2_ADDSET_2 0x00000004U
5260 #define FMC_BTR2_ADDSET_3 0x00000008U
5262 #define FMC_BTR2_ADDHLD 0x000000F0U
5263 #define FMC_BTR2_ADDHLD_0 0x00000010U
5264 #define FMC_BTR2_ADDHLD_1 0x00000020U
5265 #define FMC_BTR2_ADDHLD_2 0x00000040U
5266 #define FMC_BTR2_ADDHLD_3 0x00000080U
5268 #define FMC_BTR2_DATAST 0x0000FF00U
5269 #define FMC_BTR2_DATAST_0 0x00000100U
5270 #define FMC_BTR2_DATAST_1 0x00000200U
5271 #define FMC_BTR2_DATAST_2 0x00000400U
5272 #define FMC_BTR2_DATAST_3 0x00000800U
5273 #define FMC_BTR2_DATAST_4 0x00001000U
5274 #define FMC_BTR2_DATAST_5 0x00002000U
5275 #define FMC_BTR2_DATAST_6 0x00004000U
5276 #define FMC_BTR2_DATAST_7 0x00008000U
5278 #define FMC_BTR2_BUSTURN 0x000F0000U
5279 #define FMC_BTR2_BUSTURN_0 0x00010000U
5280 #define FMC_BTR2_BUSTURN_1 0x00020000U
5281 #define FMC_BTR2_BUSTURN_2 0x00040000U
5282 #define FMC_BTR2_BUSTURN_3 0x00080000U
5284 #define FMC_BTR2_CLKDIV 0x00F00000U
5285 #define FMC_BTR2_CLKDIV_0 0x00100000U
5286 #define FMC_BTR2_CLKDIV_1 0x00200000U
5287 #define FMC_BTR2_CLKDIV_2 0x00400000U
5288 #define FMC_BTR2_CLKDIV_3 0x00800000U
5290 #define FMC_BTR2_DATLAT 0x0F000000U
5291 #define FMC_BTR2_DATLAT_0 0x01000000U
5292 #define FMC_BTR2_DATLAT_1 0x02000000U
5293 #define FMC_BTR2_DATLAT_2 0x04000000U
5294 #define FMC_BTR2_DATLAT_3 0x08000000U
5296 #define FMC_BTR2_ACCMOD 0x30000000U
5297 #define FMC_BTR2_ACCMOD_0 0x10000000U
5298 #define FMC_BTR2_ACCMOD_1 0x20000000U
5300 /******************* Bit definition for FMC_BTR3 register *******************/
5301 #define FMC_BTR3_ADDSET 0x0000000FU
5302 #define FMC_BTR3_ADDSET_0 0x00000001U
5303 #define FMC_BTR3_ADDSET_1 0x00000002U
5304 #define FMC_BTR3_ADDSET_2 0x00000004U
5305 #define FMC_BTR3_ADDSET_3 0x00000008U
5307 #define FMC_BTR3_ADDHLD 0x000000F0U
5308 #define FMC_BTR3_ADDHLD_0 0x00000010U
5309 #define FMC_BTR3_ADDHLD_1 0x00000020U
5310 #define FMC_BTR3_ADDHLD_2 0x00000040U
5311 #define FMC_BTR3_ADDHLD_3 0x00000080U
5313 #define FMC_BTR3_DATAST 0x0000FF00U
5314 #define FMC_BTR3_DATAST_0 0x00000100U
5315 #define FMC_BTR3_DATAST_1 0x00000200U
5316 #define FMC_BTR3_DATAST_2 0x00000400U
5317 #define FMC_BTR3_DATAST_3 0x00000800U
5318 #define FMC_BTR3_DATAST_4 0x00001000U
5319 #define FMC_BTR3_DATAST_5 0x00002000U
5320 #define FMC_BTR3_DATAST_6 0x00004000U
5321 #define FMC_BTR3_DATAST_7 0x00008000U
5323 #define FMC_BTR3_BUSTURN 0x000F0000U
5324 #define FMC_BTR3_BUSTURN_0 0x00010000U
5325 #define FMC_BTR3_BUSTURN_1 0x00020000U
5326 #define FMC_BTR3_BUSTURN_2 0x00040000U
5327 #define FMC_BTR3_BUSTURN_3 0x00080000U
5329 #define FMC_BTR3_CLKDIV 0x00F00000U
5330 #define FMC_BTR3_CLKDIV_0 0x00100000U
5331 #define FMC_BTR3_CLKDIV_1 0x00200000U
5332 #define FMC_BTR3_CLKDIV_2 0x00400000U
5333 #define FMC_BTR3_CLKDIV_3 0x00800000U
5335 #define FMC_BTR3_DATLAT 0x0F000000U
5336 #define FMC_BTR3_DATLAT_0 0x01000000U
5337 #define FMC_BTR3_DATLAT_1 0x02000000U
5338 #define FMC_BTR3_DATLAT_2 0x04000000U
5339 #define FMC_BTR3_DATLAT_3 0x08000000U
5341 #define FMC_BTR3_ACCMOD 0x30000000U
5342 #define FMC_BTR3_ACCMOD_0 0x10000000U
5343 #define FMC_BTR3_ACCMOD_1 0x20000000U
5345 /****************** Bit definition for FMC_BTR4 register *******************/
5346 #define FMC_BTR4_ADDSET 0x0000000FU
5347 #define FMC_BTR4_ADDSET_0 0x00000001U
5348 #define FMC_BTR4_ADDSET_1 0x00000002U
5349 #define FMC_BTR4_ADDSET_2 0x00000004U
5350 #define FMC_BTR4_ADDSET_3 0x00000008U
5352 #define FMC_BTR4_ADDHLD 0x000000F0U
5353 #define FMC_BTR4_ADDHLD_0 0x00000010U
5354 #define FMC_BTR4_ADDHLD_1 0x00000020U
5355 #define FMC_BTR4_ADDHLD_2 0x00000040U
5356 #define FMC_BTR4_ADDHLD_3 0x00000080U
5358 #define FMC_BTR4_DATAST 0x0000FF00U
5359 #define FMC_BTR4_DATAST_0 0x00000100U
5360 #define FMC_BTR4_DATAST_1 0x00000200U
5361 #define FMC_BTR4_DATAST_2 0x00000400U
5362 #define FMC_BTR4_DATAST_3 0x00000800U
5363 #define FMC_BTR4_DATAST_4 0x00001000U
5364 #define FMC_BTR4_DATAST_5 0x00002000U
5365 #define FMC_BTR4_DATAST_6 0x00004000U
5366 #define FMC_BTR4_DATAST_7 0x00008000U
5368 #define FMC_BTR4_BUSTURN 0x000F0000U
5369 #define FMC_BTR4_BUSTURN_0 0x00010000U
5370 #define FMC_BTR4_BUSTURN_1 0x00020000U
5371 #define FMC_BTR4_BUSTURN_2 0x00040000U
5372 #define FMC_BTR4_BUSTURN_3 0x00080000U
5374 #define FMC_BTR4_CLKDIV 0x00F00000U
5375 #define FMC_BTR4_CLKDIV_0 0x00100000U
5376 #define FMC_BTR4_CLKDIV_1 0x00200000U
5377 #define FMC_BTR4_CLKDIV_2 0x00400000U
5378 #define FMC_BTR4_CLKDIV_3 0x00800000U
5380 #define FMC_BTR4_DATLAT 0x0F000000U
5381 #define FMC_BTR4_DATLAT_0 0x01000000U
5382 #define FMC_BTR4_DATLAT_1 0x02000000U
5383 #define FMC_BTR4_DATLAT_2 0x04000000U
5384 #define FMC_BTR4_DATLAT_3 0x08000000U
5386 #define FMC_BTR4_ACCMOD 0x30000000U
5387 #define FMC_BTR4_ACCMOD_0 0x10000000U
5388 #define FMC_BTR4_ACCMOD_1 0x20000000U
5390 /****************** Bit definition for FMC_BWTR1 register ******************/
5391 #define FMC_BWTR1_ADDSET 0x0000000FU
5392 #define FMC_BWTR1_ADDSET_0 0x00000001U
5393 #define FMC_BWTR1_ADDSET_1 0x00000002U
5394 #define FMC_BWTR1_ADDSET_2 0x00000004U
5395 #define FMC_BWTR1_ADDSET_3 0x00000008U
5397 #define FMC_BWTR1_ADDHLD 0x000000F0U
5398 #define FMC_BWTR1_ADDHLD_0 0x00000010U
5399 #define FMC_BWTR1_ADDHLD_1 0x00000020U
5400 #define FMC_BWTR1_ADDHLD_2 0x00000040U
5401 #define FMC_BWTR1_ADDHLD_3 0x00000080U
5403 #define FMC_BWTR1_DATAST 0x0000FF00U
5404 #define FMC_BWTR1_DATAST_0 0x00000100U
5405 #define FMC_BWTR1_DATAST_1 0x00000200U
5406 #define FMC_BWTR1_DATAST_2 0x00000400U
5407 #define FMC_BWTR1_DATAST_3 0x00000800U
5408 #define FMC_BWTR1_DATAST_4 0x00001000U
5409 #define FMC_BWTR1_DATAST_5 0x00002000U
5410 #define FMC_BWTR1_DATAST_6 0x00004000U
5411 #define FMC_BWTR1_DATAST_7 0x00008000U
5413 #define FMC_BWTR1_BUSTURN 0x000F0000U
5414 #define FMC_BWTR1_BUSTURN_0 0x00010000U
5415 #define FMC_BWTR1_BUSTURN_1 0x00020000U
5416 #define FMC_BWTR1_BUSTURN_2 0x00040000U
5417 #define FMC_BWTR1_BUSTURN_3 0x00080000U
5419 #define FMC_BWTR1_ACCMOD 0x30000000U
5420 #define FMC_BWTR1_ACCMOD_0 0x10000000U
5421 #define FMC_BWTR1_ACCMOD_1 0x20000000U
5423 /****************** Bit definition for FMC_BWTR2 register ******************/
5424 #define FMC_BWTR2_ADDSET 0x0000000FU
5425 #define FMC_BWTR2_ADDSET_0 0x00000001U
5426 #define FMC_BWTR2_ADDSET_1 0x00000002U
5427 #define FMC_BWTR2_ADDSET_2 0x00000004U
5428 #define FMC_BWTR2_ADDSET_3 0x00000008U
5430 #define FMC_BWTR2_ADDHLD 0x000000F0U
5431 #define FMC_BWTR2_ADDHLD_0 0x00000010U
5432 #define FMC_BWTR2_ADDHLD_1 0x00000020U
5433 #define FMC_BWTR2_ADDHLD_2 0x00000040U
5434 #define FMC_BWTR2_ADDHLD_3 0x00000080U
5436 #define FMC_BWTR2_DATAST 0x0000FF00U
5437 #define FMC_BWTR2_DATAST_0 0x00000100U
5438 #define FMC_BWTR2_DATAST_1 0x00000200U
5439 #define FMC_BWTR2_DATAST_2 0x00000400U
5440 #define FMC_BWTR2_DATAST_3 0x00000800U
5441 #define FMC_BWTR2_DATAST_4 0x00001000U
5442 #define FMC_BWTR2_DATAST_5 0x00002000U
5443 #define FMC_BWTR2_DATAST_6 0x00004000U
5444 #define FMC_BWTR2_DATAST_7 0x00008000U
5446 #define FMC_BWTR2_BUSTURN 0x000F0000U
5447 #define FMC_BWTR2_BUSTURN_0 0x00010000U
5448 #define FMC_BWTR2_BUSTURN_1 0x00020000U
5449 #define FMC_BWTR2_BUSTURN_2 0x00040000U
5450 #define FMC_BWTR2_BUSTURN_3 0x00080000U
5452 #define FMC_BWTR2_ACCMOD 0x30000000U
5453 #define FMC_BWTR2_ACCMOD_0 0x10000000U
5454 #define FMC_BWTR2_ACCMOD_1 0x20000000U
5456 /****************** Bit definition for FMC_BWTR3 register ******************/
5457 #define FMC_BWTR3_ADDSET 0x0000000FU
5458 #define FMC_BWTR3_ADDSET_0 0x00000001U
5459 #define FMC_BWTR3_ADDSET_1 0x00000002U
5460 #define FMC_BWTR3_ADDSET_2 0x00000004U
5461 #define FMC_BWTR3_ADDSET_3 0x00000008U
5463 #define FMC_BWTR3_ADDHLD 0x000000F0U
5464 #define FMC_BWTR3_ADDHLD_0 0x00000010U
5465 #define FMC_BWTR3_ADDHLD_1 0x00000020U
5466 #define FMC_BWTR3_ADDHLD_2 0x00000040U
5467 #define FMC_BWTR3_ADDHLD_3 0x00000080U
5469 #define FMC_BWTR3_DATAST 0x0000FF00U
5470 #define FMC_BWTR3_DATAST_0 0x00000100U
5471 #define FMC_BWTR3_DATAST_1 0x00000200U
5472 #define FMC_BWTR3_DATAST_2 0x00000400U
5473 #define FMC_BWTR3_DATAST_3 0x00000800U
5474 #define FMC_BWTR3_DATAST_4 0x00001000U
5475 #define FMC_BWTR3_DATAST_5 0x00002000U
5476 #define FMC_BWTR3_DATAST_6 0x00004000U
5477 #define FMC_BWTR3_DATAST_7 0x00008000U
5479 #define FMC_BWTR3_BUSTURN 0x000F0000U
5480 #define FMC_BWTR3_BUSTURN_0 0x00010000U
5481 #define FMC_BWTR3_BUSTURN_1 0x00020000U
5482 #define FMC_BWTR3_BUSTURN_2 0x00040000U
5483 #define FMC_BWTR3_BUSTURN_3 0x00080000U
5485 #define FMC_BWTR3_ACCMOD 0x30000000U
5486 #define FMC_BWTR3_ACCMOD_0 0x10000000U
5487 #define FMC_BWTR3_ACCMOD_1 0x20000000U
5489 /****************** Bit definition for FMC_BWTR4 register ******************/
5490 #define FMC_BWTR4_ADDSET 0x0000000FU
5491 #define FMC_BWTR4_ADDSET_0 0x00000001U
5492 #define FMC_BWTR4_ADDSET_1 0x00000002U
5493 #define FMC_BWTR4_ADDSET_2 0x00000004U
5494 #define FMC_BWTR4_ADDSET_3 0x00000008U
5496 #define FMC_BWTR4_ADDHLD 0x000000F0U
5497 #define FMC_BWTR4_ADDHLD_0 0x00000010U
5498 #define FMC_BWTR4_ADDHLD_1 0x00000020U
5499 #define FMC_BWTR4_ADDHLD_2 0x00000040U
5500 #define FMC_BWTR4_ADDHLD_3 0x00000080U
5502 #define FMC_BWTR4_DATAST 0x0000FF00U
5503 #define FMC_BWTR4_DATAST_0 0x00000100U
5504 #define FMC_BWTR4_DATAST_1 0x00000200U
5505 #define FMC_BWTR4_DATAST_2 0x00000400U
5506 #define FMC_BWTR4_DATAST_3 0x00000800U
5507 #define FMC_BWTR4_DATAST_4 0x00001000U
5508 #define FMC_BWTR4_DATAST_5 0x00002000U
5509 #define FMC_BWTR4_DATAST_6 0x00004000U
5510 #define FMC_BWTR4_DATAST_7 0x00008000U
5512 #define FMC_BWTR4_BUSTURN 0x000F0000U
5513 #define FMC_BWTR4_BUSTURN_0 0x00010000U
5514 #define FMC_BWTR4_BUSTURN_1 0x00020000U
5515 #define FMC_BWTR4_BUSTURN_2 0x00040000U
5516 #define FMC_BWTR4_BUSTURN_3 0x00080000U
5518 #define FMC_BWTR4_ACCMOD 0x30000000U
5519 #define FMC_BWTR4_ACCMOD_0 0x10000000U
5520 #define FMC_BWTR4_ACCMOD_1 0x20000000U
5522 /****************** Bit definition for FMC_PCR register *******************/
5523 #define FMC_PCR_PWAITEN 0x00000002U
5524 #define FMC_PCR_PBKEN 0x00000004U
5525 #define FMC_PCR_PTYP 0x00000008U
5527 #define FMC_PCR_PWID 0x00000030U
5528 #define FMC_PCR_PWID_0 0x00000010U
5529 #define FMC_PCR_PWID_1 0x00000020U
5531 #define FMC_PCR_ECCEN 0x00000040U
5533 #define FMC_PCR_TCLR 0x00001E00U
5534 #define FMC_PCR_TCLR_0 0x00000200U
5535 #define FMC_PCR_TCLR_1 0x00000400U
5536 #define FMC_PCR_TCLR_2 0x00000800U
5537 #define FMC_PCR_TCLR_3 0x00001000U
5539 #define FMC_PCR_TAR 0x0001E000U
5540 #define FMC_PCR_TAR_0 0x00002000U
5541 #define FMC_PCR_TAR_1 0x00004000U
5542 #define FMC_PCR_TAR_2 0x00008000U
5543 #define FMC_PCR_TAR_3 0x00010000U
5545 #define FMC_PCR_ECCPS 0x000E0000U
5546 #define FMC_PCR_ECCPS_0 0x00020000U
5547 #define FMC_PCR_ECCPS_1 0x00040000U
5548 #define FMC_PCR_ECCPS_2 0x00080000U
5550 /******************* Bit definition for FMC_SR register *******************/
5551 #define FMC_SR_IRS 0x01U
5552 #define FMC_SR_ILS 0x02U
5553 #define FMC_SR_IFS 0x04U
5554 #define FMC_SR_IREN 0x08U
5555 #define FMC_SR_ILEN 0x10U
5556 #define FMC_SR_IFEN 0x20U
5557 #define FMC_SR_FEMPT 0x40U
5559 /****************** Bit definition for FMC_PMEM register ******************/
5560 #define FMC_PMEM_MEMSET2 0x000000FFU
5561 #define FMC_PMEM_MEMSET2_0 0x00000001U
5562 #define FMC_PMEM_MEMSET2_1 0x00000002U
5563 #define FMC_PMEM_MEMSET2_2 0x00000004U
5564 #define FMC_PMEM_MEMSET2_3 0x00000008U
5565 #define FMC_PMEM_MEMSET2_4 0x00000010U
5566 #define FMC_PMEM_MEMSET2_5 0x00000020U
5567 #define FMC_PMEM_MEMSET2_6 0x00000040U
5568 #define FMC_PMEM_MEMSET2_7 0x00000080U
5570 #define FMC_PMEM_MEMWAIT2 0x0000FF00U
5571 #define FMC_PMEM_MEMWAIT2_0 0x00000100U
5572 #define FMC_PMEM_MEMWAIT2_1 0x00000200U
5573 #define FMC_PMEM_MEMWAIT2_2 0x00000400U
5574 #define FMC_PMEM_MEMWAIT2_3 0x00000800U
5575 #define FMC_PMEM_MEMWAIT2_4 0x00001000U
5576 #define FMC_PMEM_MEMWAIT2_5 0x00002000U
5577 #define FMC_PMEM_MEMWAIT2_6 0x00004000U
5578 #define FMC_PMEM_MEMWAIT2_7 0x00008000U
5580 #define FMC_PMEM_MEMHOLD2 0x00FF0000U
5581 #define FMC_PMEM_MEMHOLD2_0 0x00010000U
5582 #define FMC_PMEM_MEMHOLD2_1 0x00020000U
5583 #define FMC_PMEM_MEMHOLD2_2 0x00040000U
5584 #define FMC_PMEM_MEMHOLD2_3 0x00080000U
5585 #define FMC_PMEM_MEMHOLD2_4 0x00100000U
5586 #define FMC_PMEM_MEMHOLD2_5 0x00200000U
5587 #define FMC_PMEM_MEMHOLD2_6 0x00400000U
5588 #define FMC_PMEM_MEMHOLD2_7 0x00800000U
5590 #define FMC_PMEM_MEMHIZ2 0xFF000000U
5591 #define FMC_PMEM_MEMHIZ2_0 0x01000000U
5592 #define FMC_PMEM_MEMHIZ2_1 0x02000000U
5593 #define FMC_PMEM_MEMHIZ2_2 0x04000000U
5594 #define FMC_PMEM_MEMHIZ2_3 0x08000000U
5595 #define FMC_PMEM_MEMHIZ2_4 0x10000000U
5596 #define FMC_PMEM_MEMHIZ2_5 0x20000000U
5597 #define FMC_PMEM_MEMHIZ2_6 0x40000000U
5598 #define FMC_PMEM_MEMHIZ2_7 0x80000000U
5600 /****************** Bit definition for FMC_PATT register ******************/
5601 #define FMC_PATT_ATTSET2 0x000000FFU
5602 #define FMC_PATT_ATTSET2_0 0x00000001U
5603 #define FMC_PATT_ATTSET2_1 0x00000002U
5604 #define FMC_PATT_ATTSET2_2 0x00000004U
5605 #define FMC_PATT_ATTSET2_3 0x00000008U
5606 #define FMC_PATT_ATTSET2_4 0x00000010U
5607 #define FMC_PATT_ATTSET2_5 0x00000020U
5608 #define FMC_PATT_ATTSET2_6 0x00000040U
5609 #define FMC_PATT_ATTSET2_7 0x00000080U
5611 #define FMC_PATT_ATTWAIT2 0x0000FF00U
5612 #define FMC_PATT_ATTWAIT2_0 0x00000100U
5613 #define FMC_PATT_ATTWAIT2_1 0x00000200U
5614 #define FMC_PATT_ATTWAIT2_2 0x00000400U
5615 #define FMC_PATT_ATTWAIT2_3 0x00000800U
5616 #define FMC_PATT_ATTWAIT2_4 0x00001000U
5617 #define FMC_PATT_ATTWAIT2_5 0x00002000U
5618 #define FMC_PATT_ATTWAIT2_6 0x00004000U
5619 #define FMC_PATT_ATTWAIT2_7 0x00008000U
5621 #define FMC_PATT_ATTHOLD2 0x00FF0000U
5622 #define FMC_PATT_ATTHOLD2_0 0x00010000U
5623 #define FMC_PATT_ATTHOLD2_1 0x00020000U
5624 #define FMC_PATT_ATTHOLD2_2 0x00040000U
5625 #define FMC_PATT_ATTHOLD2_3 0x00080000U
5626 #define FMC_PATT_ATTHOLD2_4 0x00100000U
5627 #define FMC_PATT_ATTHOLD2_5 0x00200000U
5628 #define FMC_PATT_ATTHOLD2_6 0x00400000U
5629 #define FMC_PATT_ATTHOLD2_7 0x00800000U
5631 #define FMC_PATT_ATTHIZ2 0xFF000000U
5632 #define FMC_PATT_ATTHIZ2_0 0x01000000U
5633 #define FMC_PATT_ATTHIZ2_1 0x02000000U
5634 #define FMC_PATT_ATTHIZ2_2 0x04000000U
5635 #define FMC_PATT_ATTHIZ2_3 0x08000000U
5636 #define FMC_PATT_ATTHIZ2_4 0x10000000U
5637 #define FMC_PATT_ATTHIZ2_5 0x20000000U
5638 #define FMC_PATT_ATTHIZ2_6 0x40000000U
5639 #define FMC_PATT_ATTHIZ2_7 0x80000000U
5641 /****************** Bit definition for FMC_ECCR register ******************/
5642 #define FMC_ECCR_ECC2 0xFFFFFFFFU
5644 /****************** Bit definition for FMC_SDCR1 register ******************/
5645 #define FMC_SDCR1_NC 0x00000003U
5646 #define FMC_SDCR1_NC_0 0x00000001U
5647 #define FMC_SDCR1_NC_1 0x00000002U
5649 #define FMC_SDCR1_NR 0x0000000CU
5650 #define FMC_SDCR1_NR_0 0x00000004U
5651 #define FMC_SDCR1_NR_1 0x00000008U
5653 #define FMC_SDCR1_MWID 0x00000030U
5654 #define FMC_SDCR1_MWID_0 0x00000010U
5655 #define FMC_SDCR1_MWID_1 0x00000020U
5657 #define FMC_SDCR1_NB 0x00000040U
5659 #define FMC_SDCR1_CAS 0x00000180U
5660 #define FMC_SDCR1_CAS_0 0x00000080U
5661 #define FMC_SDCR1_CAS_1 0x00000100U
5663 #define FMC_SDCR1_WP 0x00000200U
5665 #define FMC_SDCR1_SDCLK 0x00000C00U
5666 #define FMC_SDCR1_SDCLK_0 0x00000400U
5667 #define FMC_SDCR1_SDCLK_1 0x00000800U
5669 #define FMC_SDCR1_RBURST 0x00001000U
5671 #define FMC_SDCR1_RPIPE 0x00006000U
5672 #define FMC_SDCR1_RPIPE_0 0x00002000U
5673 #define FMC_SDCR1_RPIPE_1 0x00004000U
5675 /****************** Bit definition for FMC_SDCR2 register ******************/
5676 #define FMC_SDCR2_NC 0x00000003U
5677 #define FMC_SDCR2_NC_0 0x00000001U
5678 #define FMC_SDCR2_NC_1 0x00000002U
5680 #define FMC_SDCR2_NR 0x0000000CU
5681 #define FMC_SDCR2_NR_0 0x00000004U
5682 #define FMC_SDCR2_NR_1 0x00000008U
5684 #define FMC_SDCR2_MWID 0x00000030U
5685 #define FMC_SDCR2_MWID_0 0x00000010U
5686 #define FMC_SDCR2_MWID_1 0x00000020U
5688 #define FMC_SDCR2_NB 0x00000040U
5690 #define FMC_SDCR2_CAS 0x00000180U
5691 #define FMC_SDCR2_CAS_0 0x00000080U
5692 #define FMC_SDCR2_CAS_1 0x00000100U
5694 #define FMC_SDCR2_WP 0x00000200U
5696 #define FMC_SDCR2_SDCLK 0x00000C00U
5697 #define FMC_SDCR2_SDCLK_0 0x00000400U
5698 #define FMC_SDCR2_SDCLK_1 0x00000800U
5700 #define FMC_SDCR2_RBURST 0x00001000U
5702 #define FMC_SDCR2_RPIPE 0x00006000U
5703 #define FMC_SDCR2_RPIPE_0 0x00002000U
5704 #define FMC_SDCR2_RPIPE_1 0x00004000U
5706 /****************** Bit definition for FMC_SDTR1 register ******************/
5707 #define FMC_SDTR1_TMRD 0x0000000FU
5708 #define FMC_SDTR1_TMRD_0 0x00000001U
5709 #define FMC_SDTR1_TMRD_1 0x00000002U
5710 #define FMC_SDTR1_TMRD_2 0x00000004U
5711 #define FMC_SDTR1_TMRD_3 0x00000008U
5713 #define FMC_SDTR1_TXSR 0x000000F0U
5714 #define FMC_SDTR1_TXSR_0 0x00000010U
5715 #define FMC_SDTR1_TXSR_1 0x00000020U
5716 #define FMC_SDTR1_TXSR_2 0x00000040U
5717 #define FMC_SDTR1_TXSR_3 0x00000080U
5719 #define FMC_SDTR1_TRAS 0x00000F00U
5720 #define FMC_SDTR1_TRAS_0 0x00000100U
5721 #define FMC_SDTR1_TRAS_1 0x00000200U
5722 #define FMC_SDTR1_TRAS_2 0x00000400U
5723 #define FMC_SDTR1_TRAS_3 0x00000800U
5725 #define FMC_SDTR1_TRC 0x0000F000U
5726 #define FMC_SDTR1_TRC_0 0x00001000U
5727 #define FMC_SDTR1_TRC_1 0x00002000U
5728 #define FMC_SDTR1_TRC_2 0x00004000U
5730 #define FMC_SDTR1_TWR 0x000F0000U
5731 #define FMC_SDTR1_TWR_0 0x00010000U
5732 #define FMC_SDTR1_TWR_1 0x00020000U
5733 #define FMC_SDTR1_TWR_2 0x00040000U
5735 #define FMC_SDTR1_TRP 0x00F00000U
5736 #define FMC_SDTR1_TRP_0 0x00100000U
5737 #define FMC_SDTR1_TRP_1 0x00200000U
5738 #define FMC_SDTR1_TRP_2 0x00400000U
5740 #define FMC_SDTR1_TRCD 0x0F000000U
5741 #define FMC_SDTR1_TRCD_0 0x01000000U
5742 #define FMC_SDTR1_TRCD_1 0x02000000U
5743 #define FMC_SDTR1_TRCD_2 0x04000000U
5745 /****************** Bit definition for FMC_SDTR2 register ******************/
5746 #define FMC_SDTR2_TMRD 0x0000000FU
5747 #define FMC_SDTR2_TMRD_0 0x00000001U
5748 #define FMC_SDTR2_TMRD_1 0x00000002U
5749 #define FMC_SDTR2_TMRD_2 0x00000004U
5750 #define FMC_SDTR2_TMRD_3 0x00000008U
5752 #define FMC_SDTR2_TXSR 0x000000F0U
5753 #define FMC_SDTR2_TXSR_0 0x00000010U
5754 #define FMC_SDTR2_TXSR_1 0x00000020U
5755 #define FMC_SDTR2_TXSR_2 0x00000040U
5756 #define FMC_SDTR2_TXSR_3 0x00000080U
5758 #define FMC_SDTR2_TRAS 0x00000F00U
5759 #define FMC_SDTR2_TRAS_0 0x00000100U
5760 #define FMC_SDTR2_TRAS_1 0x00000200U
5761 #define FMC_SDTR2_TRAS_2 0x00000400U
5762 #define FMC_SDTR2_TRAS_3 0x00000800U
5764 #define FMC_SDTR2_TRC 0x0000F000U
5765 #define FMC_SDTR2_TRC_0 0x00001000U
5766 #define FMC_SDTR2_TRC_1 0x00002000U
5767 #define FMC_SDTR2_TRC_2 0x00004000U
5769 #define FMC_SDTR2_TWR 0x000F0000U
5770 #define FMC_SDTR2_TWR_0 0x00010000U
5771 #define FMC_SDTR2_TWR_1 0x00020000U
5772 #define FMC_SDTR2_TWR_2 0x00040000U
5774 #define FMC_SDTR2_TRP 0x00F00000U
5775 #define FMC_SDTR2_TRP_0 0x00100000U
5776 #define FMC_SDTR2_TRP_1 0x00200000U
5777 #define FMC_SDTR2_TRP_2 0x00400000U
5779 #define FMC_SDTR2_TRCD 0x0F000000U
5780 #define FMC_SDTR2_TRCD_0 0x01000000U
5781 #define FMC_SDTR2_TRCD_1 0x02000000U
5782 #define FMC_SDTR2_TRCD_2 0x04000000U
5784 /****************** Bit definition for FMC_SDCMR register ******************/
5785 #define FMC_SDCMR_MODE 0x00000007U
5786 #define FMC_SDCMR_MODE_0 0x00000001U
5787 #define FMC_SDCMR_MODE_1 0x00000002U
5788 #define FMC_SDCMR_MODE_2 0x00000004U
5790 #define FMC_SDCMR_CTB2 0x00000008U
5792 #define FMC_SDCMR_CTB1 0x00000010U
5794 #define FMC_SDCMR_NRFS 0x000001E0U
5795 #define FMC_SDCMR_NRFS_0 0x00000020U
5796 #define FMC_SDCMR_NRFS_1 0x00000040U
5797 #define FMC_SDCMR_NRFS_2 0x00000080U
5798 #define FMC_SDCMR_NRFS_3 0x00000100U
5800 #define FMC_SDCMR_MRD 0x003FFE00U
5802 /****************** Bit definition for FMC_SDRTR register ******************/
5803 #define FMC_SDRTR_CRE 0x00000001U
5805 #define FMC_SDRTR_COUNT 0x00003FFEU
5807 #define FMC_SDRTR_REIE 0x00004000U
5809 /****************** Bit definition for FMC_SDSR register ******************/
5810 #define FMC_SDSR_RE 0x00000001U
5812 #define FMC_SDSR_MODES1 0x00000006U
5813 #define FMC_SDSR_MODES1_0 0x00000002U
5814 #define FMC_SDSR_MODES1_1 0x00000004U
5816 #define FMC_SDSR_MODES2 0x00000018U
5817 #define FMC_SDSR_MODES2_0 0x00000008U
5818 #define FMC_SDSR_MODES2_1 0x00000010U
5819 #define FMC_SDSR_BUSY 0x00000020U
5821 /******************************************************************************/
5822 /* */
5823 /* General Purpose I/O */
5824 /* */
5825 /******************************************************************************/
5826 /****************** Bits definition for GPIO_MODER register *****************/
5827 #define GPIO_MODER_MODER0 0x00000003U
5828 #define GPIO_MODER_MODER0_0 0x00000001U
5829 #define GPIO_MODER_MODER0_1 0x00000002U
5830 
5831 #define GPIO_MODER_MODER1 0x0000000CU
5832 #define GPIO_MODER_MODER1_0 0x00000004U
5833 #define GPIO_MODER_MODER1_1 0x00000008U
5834 
5835 #define GPIO_MODER_MODER2 0x00000030U
5836 #define GPIO_MODER_MODER2_0 0x00000010U
5837 #define GPIO_MODER_MODER2_1 0x00000020U
5838 
5839 #define GPIO_MODER_MODER3 0x000000C0U
5840 #define GPIO_MODER_MODER3_0 0x00000040U
5841 #define GPIO_MODER_MODER3_1 0x00000080U
5842 
5843 #define GPIO_MODER_MODER4 0x00000300U
5844 #define GPIO_MODER_MODER4_0 0x00000100U
5845 #define GPIO_MODER_MODER4_1 0x00000200U
5846 
5847 #define GPIO_MODER_MODER5 0x00000C00U
5848 #define GPIO_MODER_MODER5_0 0x00000400U
5849 #define GPIO_MODER_MODER5_1 0x00000800U
5850 
5851 #define GPIO_MODER_MODER6 0x00003000U
5852 #define GPIO_MODER_MODER6_0 0x00001000U
5853 #define GPIO_MODER_MODER6_1 0x00002000U
5854 
5855 #define GPIO_MODER_MODER7 0x0000C000U
5856 #define GPIO_MODER_MODER7_0 0x00004000U
5857 #define GPIO_MODER_MODER7_1 0x00008000U
5858 
5859 #define GPIO_MODER_MODER8 0x00030000U
5860 #define GPIO_MODER_MODER8_0 0x00010000U
5861 #define GPIO_MODER_MODER8_1 0x00020000U
5862 
5863 #define GPIO_MODER_MODER9 0x000C0000U
5864 #define GPIO_MODER_MODER9_0 0x00040000U
5865 #define GPIO_MODER_MODER9_1 0x00080000U
5866 
5867 #define GPIO_MODER_MODER10 0x00300000U
5868 #define GPIO_MODER_MODER10_0 0x00100000U
5869 #define GPIO_MODER_MODER10_1 0x00200000U
5870 
5871 #define GPIO_MODER_MODER11 0x00C00000U
5872 #define GPIO_MODER_MODER11_0 0x00400000U
5873 #define GPIO_MODER_MODER11_1 0x00800000U
5874 
5875 #define GPIO_MODER_MODER12 0x03000000U
5876 #define GPIO_MODER_MODER12_0 0x01000000U
5877 #define GPIO_MODER_MODER12_1 0x02000000U
5878 
5879 #define GPIO_MODER_MODER13 0x0C000000U
5880 #define GPIO_MODER_MODER13_0 0x04000000U
5881 #define GPIO_MODER_MODER13_1 0x08000000U
5882 
5883 #define GPIO_MODER_MODER14 0x30000000U
5884 #define GPIO_MODER_MODER14_0 0x10000000U
5885 #define GPIO_MODER_MODER14_1 0x20000000U
5886 
5887 #define GPIO_MODER_MODER15 0xC0000000U
5888 #define GPIO_MODER_MODER15_0 0x40000000U
5889 #define GPIO_MODER_MODER15_1 0x80000000U
5890 
5891 /****************** Bits definition for GPIO_OTYPER register ****************/
5892 #define GPIO_OTYPER_OT_0 0x00000001U
5893 #define GPIO_OTYPER_OT_1 0x00000002U
5894 #define GPIO_OTYPER_OT_2 0x00000004U
5895 #define GPIO_OTYPER_OT_3 0x00000008U
5896 #define GPIO_OTYPER_OT_4 0x00000010U
5897 #define GPIO_OTYPER_OT_5 0x00000020U
5898 #define GPIO_OTYPER_OT_6 0x00000040U
5899 #define GPIO_OTYPER_OT_7 0x00000080U
5900 #define GPIO_OTYPER_OT_8 0x00000100U
5901 #define GPIO_OTYPER_OT_9 0x00000200U
5902 #define GPIO_OTYPER_OT_10 0x00000400U
5903 #define GPIO_OTYPER_OT_11 0x00000800U
5904 #define GPIO_OTYPER_OT_12 0x00001000U
5905 #define GPIO_OTYPER_OT_13 0x00002000U
5906 #define GPIO_OTYPER_OT_14 0x00004000U
5907 #define GPIO_OTYPER_OT_15 0x00008000U
5908 
5909 /****************** Bits definition for GPIO_OSPEEDR register ***************/
5910 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
5911 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
5912 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
5913 
5914 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
5915 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
5916 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
5917 
5918 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
5919 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
5920 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
5921 
5922 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
5923 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
5924 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
5925 
5926 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
5927 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
5928 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
5929 
5930 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
5931 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
5932 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
5933 
5934 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
5935 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
5936 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
5937 
5938 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
5939 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
5940 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
5941 
5942 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
5943 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
5944 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
5945 
5946 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
5947 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
5948 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
5949 
5950 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
5951 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
5952 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
5953 
5954 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
5955 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
5956 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
5957 
5958 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
5959 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
5960 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
5961 
5962 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
5963 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
5964 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
5965 
5966 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
5967 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
5968 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
5969 
5970 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
5971 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
5972 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
5973 
5974 /****************** Bits definition for GPIO_PUPDR register *****************/
5975 #define GPIO_PUPDR_PUPDR0 0x00000003U
5976 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
5977 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
5978 
5979 #define GPIO_PUPDR_PUPDR1 0x0000000CU
5980 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
5981 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
5982 
5983 #define GPIO_PUPDR_PUPDR2 0x00000030U
5984 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
5985 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
5986 
5987 #define GPIO_PUPDR_PUPDR3 0x000000C0U
5988 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
5989 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
5990 
5991 #define GPIO_PUPDR_PUPDR4 0x00000300U
5992 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
5993 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
5994 
5995 #define GPIO_PUPDR_PUPDR5 0x00000C00U
5996 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
5997 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
5998 
5999 #define GPIO_PUPDR_PUPDR6 0x00003000U
6000 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
6001 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
6002 
6003 #define GPIO_PUPDR_PUPDR7 0x0000C000U
6004 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
6005 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
6006 
6007 #define GPIO_PUPDR_PUPDR8 0x00030000U
6008 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
6009 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
6010 
6011 #define GPIO_PUPDR_PUPDR9 0x000C0000U
6012 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
6013 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
6014 
6015 #define GPIO_PUPDR_PUPDR10 0x00300000U
6016 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
6017 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
6018 
6019 #define GPIO_PUPDR_PUPDR11 0x00C00000U
6020 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
6021 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
6022 
6023 #define GPIO_PUPDR_PUPDR12 0x03000000U
6024 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
6025 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
6026 
6027 #define GPIO_PUPDR_PUPDR13 0x0C000000U
6028 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
6029 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
6030 
6031 #define GPIO_PUPDR_PUPDR14 0x30000000U
6032 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
6033 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
6034 
6035 #define GPIO_PUPDR_PUPDR15 0xC0000000U
6036 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
6037 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
6038 
6039 /****************** Bits definition for GPIO_IDR register *******************/
6040 #define GPIO_IDR_IDR_0 0x00000001U
6041 #define GPIO_IDR_IDR_1 0x00000002U
6042 #define GPIO_IDR_IDR_2 0x00000004U
6043 #define GPIO_IDR_IDR_3 0x00000008U
6044 #define GPIO_IDR_IDR_4 0x00000010U
6045 #define GPIO_IDR_IDR_5 0x00000020U
6046 #define GPIO_IDR_IDR_6 0x00000040U
6047 #define GPIO_IDR_IDR_7 0x00000080U
6048 #define GPIO_IDR_IDR_8 0x00000100U
6049 #define GPIO_IDR_IDR_9 0x00000200U
6050 #define GPIO_IDR_IDR_10 0x00000400U
6051 #define GPIO_IDR_IDR_11 0x00000800U
6052 #define GPIO_IDR_IDR_12 0x00001000U
6053 #define GPIO_IDR_IDR_13 0x00002000U
6054 #define GPIO_IDR_IDR_14 0x00004000U
6055 #define GPIO_IDR_IDR_15 0x00008000U
6056 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
6057 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
6058 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
6059 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
6060 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
6061 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
6062 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
6063 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
6064 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
6065 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
6066 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
6067 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
6068 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
6069 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
6070 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
6071 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
6072 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
6073 
6074 /****************** Bits definition for GPIO_ODR register *******************/
6075 #define GPIO_ODR_ODR_0 0x00000001U
6076 #define GPIO_ODR_ODR_1 0x00000002U
6077 #define GPIO_ODR_ODR_2 0x00000004U
6078 #define GPIO_ODR_ODR_3 0x00000008U
6079 #define GPIO_ODR_ODR_4 0x00000010U
6080 #define GPIO_ODR_ODR_5 0x00000020U
6081 #define GPIO_ODR_ODR_6 0x00000040U
6082 #define GPIO_ODR_ODR_7 0x00000080U
6083 #define GPIO_ODR_ODR_8 0x00000100U
6084 #define GPIO_ODR_ODR_9 0x00000200U
6085 #define GPIO_ODR_ODR_10 0x00000400U
6086 #define GPIO_ODR_ODR_11 0x00000800U
6087 #define GPIO_ODR_ODR_12 0x00001000U
6088 #define GPIO_ODR_ODR_13 0x00002000U
6089 #define GPIO_ODR_ODR_14 0x00004000U
6090 #define GPIO_ODR_ODR_15 0x00008000U
6091 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6092 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
6093 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
6094 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
6095 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
6096 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
6097 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
6098 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
6099 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
6100 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
6101 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
6102 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
6103 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
6104 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
6105 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
6106 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
6107 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
6108 
6109 /****************** Bits definition for GPIO_BSRR register ******************/
6110 #define GPIO_BSRR_BS_0 0x00000001U
6111 #define GPIO_BSRR_BS_1 0x00000002U
6112 #define GPIO_BSRR_BS_2 0x00000004U
6113 #define GPIO_BSRR_BS_3 0x00000008U
6114 #define GPIO_BSRR_BS_4 0x00000010U
6115 #define GPIO_BSRR_BS_5 0x00000020U
6116 #define GPIO_BSRR_BS_6 0x00000040U
6117 #define GPIO_BSRR_BS_7 0x00000080U
6118 #define GPIO_BSRR_BS_8 0x00000100U
6119 #define GPIO_BSRR_BS_9 0x00000200U
6120 #define GPIO_BSRR_BS_10 0x00000400U
6121 #define GPIO_BSRR_BS_11 0x00000800U
6122 #define GPIO_BSRR_BS_12 0x00001000U
6123 #define GPIO_BSRR_BS_13 0x00002000U
6124 #define GPIO_BSRR_BS_14 0x00004000U
6125 #define GPIO_BSRR_BS_15 0x00008000U
6126 #define GPIO_BSRR_BR_0 0x00010000U
6127 #define GPIO_BSRR_BR_1 0x00020000U
6128 #define GPIO_BSRR_BR_2 0x00040000U
6129 #define GPIO_BSRR_BR_3 0x00080000U
6130 #define GPIO_BSRR_BR_4 0x00100000U
6131 #define GPIO_BSRR_BR_5 0x00200000U
6132 #define GPIO_BSRR_BR_6 0x00400000U
6133 #define GPIO_BSRR_BR_7 0x00800000U
6134 #define GPIO_BSRR_BR_8 0x01000000U
6135 #define GPIO_BSRR_BR_9 0x02000000U
6136 #define GPIO_BSRR_BR_10 0x04000000U
6137 #define GPIO_BSRR_BR_11 0x08000000U
6138 #define GPIO_BSRR_BR_12 0x10000000U
6139 #define GPIO_BSRR_BR_13 0x20000000U
6140 #define GPIO_BSRR_BR_14 0x40000000U
6141 #define GPIO_BSRR_BR_15 0x80000000U
6142 
6143 /****************** Bit definition for GPIO_LCKR register *********************/
6144 #define GPIO_LCKR_LCK0 0x00000001U
6145 #define GPIO_LCKR_LCK1 0x00000002U
6146 #define GPIO_LCKR_LCK2 0x00000004U
6147 #define GPIO_LCKR_LCK3 0x00000008U
6148 #define GPIO_LCKR_LCK4 0x00000010U
6149 #define GPIO_LCKR_LCK5 0x00000020U
6150 #define GPIO_LCKR_LCK6 0x00000040U
6151 #define GPIO_LCKR_LCK7 0x00000080U
6152 #define GPIO_LCKR_LCK8 0x00000100U
6153 #define GPIO_LCKR_LCK9 0x00000200U
6154 #define GPIO_LCKR_LCK10 0x00000400U
6155 #define GPIO_LCKR_LCK11 0x00000800U
6156 #define GPIO_LCKR_LCK12 0x00001000U
6157 #define GPIO_LCKR_LCK13 0x00002000U
6158 #define GPIO_LCKR_LCK14 0x00004000U
6159 #define GPIO_LCKR_LCK15 0x00008000U
6160 #define GPIO_LCKR_LCKK 0x00010000U
6161 
6162 /******************************************************************************/
6163 /* */
6164 /* Inter-integrated Circuit Interface */
6165 /* */
6166 /******************************************************************************/
6167 /******************* Bit definition for I2C_CR1 register ********************/
6168 #define I2C_CR1_PE 0x00000001U
6169 #define I2C_CR1_SMBUS 0x00000002U
6170 #define I2C_CR1_SMBTYPE 0x00000008U
6171 #define I2C_CR1_ENARP 0x00000010U
6172 #define I2C_CR1_ENPEC 0x00000020U
6173 #define I2C_CR1_ENGC 0x00000040U
6174 #define I2C_CR1_NOSTRETCH 0x00000080U
6175 #define I2C_CR1_START 0x00000100U
6176 #define I2C_CR1_STOP 0x00000200U
6177 #define I2C_CR1_ACK 0x00000400U
6178 #define I2C_CR1_POS 0x00000800U
6179 #define I2C_CR1_PEC 0x00001000U
6180 #define I2C_CR1_ALERT 0x00002000U
6181 #define I2C_CR1_SWRST 0x00008000U
6183 /******************* Bit definition for I2C_CR2 register ********************/
6184 #define I2C_CR2_FREQ 0x0000003FU
6185 #define I2C_CR2_FREQ_0 0x00000001U
6186 #define I2C_CR2_FREQ_1 0x00000002U
6187 #define I2C_CR2_FREQ_2 0x00000004U
6188 #define I2C_CR2_FREQ_3 0x00000008U
6189 #define I2C_CR2_FREQ_4 0x00000010U
6190 #define I2C_CR2_FREQ_5 0x00000020U
6192 #define I2C_CR2_ITERREN 0x00000100U
6193 #define I2C_CR2_ITEVTEN 0x00000200U
6194 #define I2C_CR2_ITBUFEN 0x00000400U
6195 #define I2C_CR2_DMAEN 0x00000800U
6196 #define I2C_CR2_LAST 0x00001000U
6198 /******************* Bit definition for I2C_OAR1 register *******************/
6199 #define I2C_OAR1_ADD1_7 0x000000FEU
6200 #define I2C_OAR1_ADD8_9 0x00000300U
6202 #define I2C_OAR1_ADD0 0x00000001U
6203 #define I2C_OAR1_ADD1 0x00000002U
6204 #define I2C_OAR1_ADD2 0x00000004U
6205 #define I2C_OAR1_ADD3 0x00000008U
6206 #define I2C_OAR1_ADD4 0x00000010U
6207 #define I2C_OAR1_ADD5 0x00000020U
6208 #define I2C_OAR1_ADD6 0x00000040U
6209 #define I2C_OAR1_ADD7 0x00000080U
6210 #define I2C_OAR1_ADD8 0x00000100U
6211 #define I2C_OAR1_ADD9 0x00000200U
6213 #define I2C_OAR1_ADDMODE 0x00008000U
6215 /******************* Bit definition for I2C_OAR2 register *******************/
6216 #define I2C_OAR2_ENDUAL 0x00000001U
6217 #define I2C_OAR2_ADD2 0x000000FEU
6219 /******************** Bit definition for I2C_DR register ********************/
6220 #define I2C_DR_DR 0x000000FFU
6222 /******************* Bit definition for I2C_SR1 register ********************/
6223 #define I2C_SR1_SB 0x00000001U
6224 #define I2C_SR1_ADDR 0x00000002U
6225 #define I2C_SR1_BTF 0x00000004U
6226 #define I2C_SR1_ADD10 0x00000008U
6227 #define I2C_SR1_STOPF 0x00000010U
6228 #define I2C_SR1_RXNE 0x00000040U
6229 #define I2C_SR1_TXE 0x00000080U
6230 #define I2C_SR1_BERR 0x00000100U
6231 #define I2C_SR1_ARLO 0x00000200U
6232 #define I2C_SR1_AF 0x00000400U
6233 #define I2C_SR1_OVR 0x00000800U
6234 #define I2C_SR1_PECERR 0x00001000U
6235 #define I2C_SR1_TIMEOUT 0x00004000U
6236 #define I2C_SR1_SMBALERT 0x00008000U
6238 /******************* Bit definition for I2C_SR2 register ********************/
6239 #define I2C_SR2_MSL 0x00000001U
6240 #define I2C_SR2_BUSY 0x00000002U
6241 #define I2C_SR2_TRA 0x00000004U
6242 #define I2C_SR2_GENCALL 0x00000010U
6243 #define I2C_SR2_SMBDEFAULT 0x00000020U
6244 #define I2C_SR2_SMBHOST 0x00000040U
6245 #define I2C_SR2_DUALF 0x00000080U
6246 #define I2C_SR2_PEC 0x0000FF00U
6248 /******************* Bit definition for I2C_CCR register ********************/
6249 #define I2C_CCR_CCR 0x00000FFFU
6250 #define I2C_CCR_DUTY 0x00004000U
6251 #define I2C_CCR_FS 0x00008000U
6253 /****************** Bit definition for I2C_TRISE register *******************/
6254 #define I2C_TRISE_TRISE 0x0000003FU
6256 /****************** Bit definition for I2C_FLTR register *******************/
6257 #define I2C_FLTR_DNF 0x0000000FU
6258 #define I2C_FLTR_ANOFF 0x00000010U
6260 /******************************************************************************/
6261 /* */
6262 /* Independent WATCHDOG */
6263 /* */
6264 /******************************************************************************/
6265 /******************* Bit definition for IWDG_KR register ********************/
6266 #define IWDG_KR_KEY 0xFFFFU
6268 /******************* Bit definition for IWDG_PR register ********************/
6269 #define IWDG_PR_PR 0x07U
6270 #define IWDG_PR_PR_0 0x01U
6271 #define IWDG_PR_PR_1 0x02U
6272 #define IWDG_PR_PR_2 0x04U
6274 /******************* Bit definition for IWDG_RLR register *******************/
6275 #define IWDG_RLR_RL 0x0FFFU
6277 /******************* Bit definition for IWDG_SR register ********************/
6278 #define IWDG_SR_PVU 0x01U
6279 #define IWDG_SR_RVU 0x02U
6282 /******************************************************************************/
6283 /* */
6284 /* LCD-TFT Display Controller (LTDC) */
6285 /* */
6286 /******************************************************************************/
6287 
6288 /******************** Bit definition for LTDC_SSCR register *****************/
6289 
6290 #define LTDC_SSCR_VSH 0x000007FFU
6291 #define LTDC_SSCR_HSW 0x0FFF0000U
6293 /******************** Bit definition for LTDC_BPCR register *****************/
6294 
6295 #define LTDC_BPCR_AVBP 0x000007FFU
6296 #define LTDC_BPCR_AHBP 0x0FFF0000U
6298 /******************** Bit definition for LTDC_AWCR register *****************/
6299 
6300 #define LTDC_AWCR_AAH 0x000007FFU
6301 #define LTDC_AWCR_AAW 0x0FFF0000U
6303 /******************** Bit definition for LTDC_TWCR register *****************/
6304 
6305 #define LTDC_TWCR_TOTALH 0x000007FFU
6306 #define LTDC_TWCR_TOTALW 0x0FFF0000U
6308 /******************** Bit definition for LTDC_GCR register ******************/
6309 
6310 #define LTDC_GCR_LTDCEN 0x00000001U
6311 #define LTDC_GCR_DBW 0x00000070U
6312 #define LTDC_GCR_DGW 0x00000700U
6313 #define LTDC_GCR_DRW 0x00007000U
6314 #define LTDC_GCR_DEN 0x00010000U
6315 #define LTDC_GCR_PCPOL 0x10000000U
6316 #define LTDC_GCR_DEPOL 0x20000000U
6317 #define LTDC_GCR_VSPOL 0x40000000U
6318 #define LTDC_GCR_HSPOL 0x80000000U
6320 /* Legacy defines */
6321 #define LTDC_GCR_DTEN LTDC_GCR_DEN
6322 
6323 /******************** Bit definition for LTDC_SRCR register *****************/
6324 
6325 #define LTDC_SRCR_IMR 0x00000001U
6326 #define LTDC_SRCR_VBR 0x00000002U
6328 /******************** Bit definition for LTDC_BCCR register *****************/
6329 
6330 #define LTDC_BCCR_BCBLUE 0x000000FFU
6331 #define LTDC_BCCR_BCGREEN 0x0000FF00U
6332 #define LTDC_BCCR_BCRED 0x00FF0000U
6334 /******************** Bit definition for LTDC_IER register ******************/
6335 
6336 #define LTDC_IER_LIE 0x00000001U
6337 #define LTDC_IER_FUIE 0x00000002U
6338 #define LTDC_IER_TERRIE 0x00000004U
6339 #define LTDC_IER_RRIE 0x00000008U
6341 /******************** Bit definition for LTDC_ISR register ******************/
6342 
6343 #define LTDC_ISR_LIF 0x00000001U
6344 #define LTDC_ISR_FUIF 0x00000002U
6345 #define LTDC_ISR_TERRIF 0x00000004U
6346 #define LTDC_ISR_RRIF 0x00000008U
6348 /******************** Bit definition for LTDC_ICR register ******************/
6349 
6350 #define LTDC_ICR_CLIF 0x00000001U
6351 #define LTDC_ICR_CFUIF 0x00000002U
6352 #define LTDC_ICR_CTERRIF 0x00000004U
6353 #define LTDC_ICR_CRRIF 0x00000008U
6355 /******************** Bit definition for LTDC_LIPCR register ****************/
6356 
6357 #define LTDC_LIPCR_LIPOS 0x000007FFU
6359 /******************** Bit definition for LTDC_CPSR register *****************/
6360 
6361 #define LTDC_CPSR_CYPOS 0x0000FFFFU
6362 #define LTDC_CPSR_CXPOS 0xFFFF0000U
6364 /******************** Bit definition for LTDC_CDSR register *****************/
6365 
6366 #define LTDC_CDSR_VDES 0x00000001U
6367 #define LTDC_CDSR_HDES 0x00000002U
6368 #define LTDC_CDSR_VSYNCS 0x00000004U
6369 #define LTDC_CDSR_HSYNCS 0x00000008U
6371 /******************** Bit definition for LTDC_LxCR register *****************/
6372 
6373 #define LTDC_LxCR_LEN 0x00000001U
6374 #define LTDC_LxCR_COLKEN 0x00000002U
6375 #define LTDC_LxCR_CLUTEN 0x00000010U
6377 /******************** Bit definition for LTDC_LxWHPCR register **************/
6378 
6379 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU
6380 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U
6382 /******************** Bit definition for LTDC_LxWVPCR register **************/
6383 
6384 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU
6385 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U
6387 /******************** Bit definition for LTDC_LxCKCR register ***************/
6388 
6389 #define LTDC_LxCKCR_CKBLUE 0x000000FFU
6390 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U
6391 #define LTDC_LxCKCR_CKRED 0x00FF0000U
6393 /******************** Bit definition for LTDC_LxPFCR register ***************/
6394 
6395 #define LTDC_LxPFCR_PF 0x00000007U
6397 /******************** Bit definition for LTDC_LxCACR register ***************/
6398 
6399 #define LTDC_LxCACR_CONSTA 0x000000FFU
6401 /******************** Bit definition for LTDC_LxDCCR register ***************/
6402 
6403 #define LTDC_LxDCCR_DCBLUE 0x000000FFU
6404 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U
6405 #define LTDC_LxDCCR_DCRED 0x00FF0000U
6406 #define LTDC_LxDCCR_DCALPHA 0xFF000000U
6408 /******************** Bit definition for LTDC_LxBFCR register ***************/
6409 
6410 #define LTDC_LxBFCR_BF2 0x00000007U
6411 #define LTDC_LxBFCR_BF1 0x00000700U
6413 /******************** Bit definition for LTDC_LxCFBAR register **************/
6414 
6415 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU
6417 /******************** Bit definition for LTDC_LxCFBLR register **************/
6418 
6419 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU
6420 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U
6422 /******************** Bit definition for LTDC_LxCFBLNR register *************/
6423 
6424 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU
6426 /******************** Bit definition for LTDC_LxCLUTWR register *************/
6427 
6428 #define LTDC_LxCLUTWR_BLUE 0x000000FFU
6429 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U
6430 #define LTDC_LxCLUTWR_RED 0x00FF0000U
6431 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U
6434 /******************************************************************************/
6435 /* */
6436 /* Power Control */
6437 /* */
6438 /******************************************************************************/
6439 /******************** Bit definition for PWR_CR register ********************/
6440 #define PWR_CR_LPDS 0x00000001U
6441 #define PWR_CR_PDDS 0x00000002U
6442 #define PWR_CR_CWUF 0x00000004U
6443 #define PWR_CR_CSBF 0x00000008U
6444 #define PWR_CR_PVDE 0x00000010U
6446 #define PWR_CR_PLS 0x000000E0U
6447 #define PWR_CR_PLS_0 0x00000020U
6448 #define PWR_CR_PLS_1 0x00000040U
6449 #define PWR_CR_PLS_2 0x00000080U
6452 #define PWR_CR_PLS_LEV0 0x00000000U
6453 #define PWR_CR_PLS_LEV1 0x00000020U
6454 #define PWR_CR_PLS_LEV2 0x00000040U
6455 #define PWR_CR_PLS_LEV3 0x00000060U
6456 #define PWR_CR_PLS_LEV4 0x00000080U
6457 #define PWR_CR_PLS_LEV5 0x000000A0U
6458 #define PWR_CR_PLS_LEV6 0x000000C0U
6459 #define PWR_CR_PLS_LEV7 0x000000E0U
6460 #define PWR_CR_DBP 0x00000100U
6461 #define PWR_CR_FPDS 0x00000200U
6462 #define PWR_CR_LPLVDS 0x00000400U
6463 #define PWR_CR_MRLVDS 0x00000800U
6464 #define PWR_CR_ADCDC1 0x00002000U
6465 #define PWR_CR_VOS 0x0000C000U
6466 #define PWR_CR_VOS_0 0x00004000U
6467 #define PWR_CR_VOS_1 0x00008000U
6468 #define PWR_CR_ODEN 0x00010000U
6469 #define PWR_CR_ODSWEN 0x00020000U
6470 #define PWR_CR_UDEN 0x000C0000U
6471 #define PWR_CR_UDEN_0 0x00040000U
6472 #define PWR_CR_UDEN_1 0x00080000U
6474 /* Legacy define */
6475 #define PWR_CR_PMODE PWR_CR_VOS
6476 #define PWR_CR_LPUDS PWR_CR_LPLVDS
6477 #define PWR_CR_MRUDS PWR_CR_MRLVDS
6479 /******************* Bit definition for PWR_CSR register ********************/
6480 #define PWR_CSR_WUF 0x00000001U
6481 #define PWR_CSR_SBF 0x00000002U
6482 #define PWR_CSR_PVDO 0x00000004U
6483 #define PWR_CSR_BRR 0x00000008U
6484 #define PWR_CSR_WUPP 0x00000080U
6485 #define PWR_CSR_EWUP 0x00000100U
6486 #define PWR_CSR_BRE 0x00000200U
6487 #define PWR_CSR_VOSRDY 0x00004000U
6488 #define PWR_CSR_ODRDY 0x00010000U
6489 #define PWR_CSR_ODSWRDY 0x00020000U
6490 #define PWR_CSR_UDSWRDY 0x000C0000U
6492 /* Legacy define */
6493 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
6494 
6495 /******************************************************************************/
6496 /* */
6497 /* QUADSPI */
6498 /* */
6499 /******************************************************************************/
6500 /***************** Bit definition for QUADSPI_CR register *******************/
6501 #define QUADSPI_CR_EN 0x00000001U
6502 #define QUADSPI_CR_ABORT 0x00000002U
6503 #define QUADSPI_CR_DMAEN 0x00000004U
6504 #define QUADSPI_CR_TCEN 0x00000008U
6505 #define QUADSPI_CR_SSHIFT 0x00000010U
6506 #define QUADSPI_CR_DFM 0x00000040U
6507 #define QUADSPI_CR_FSEL 0x00000080U
6508 #define QUADSPI_CR_FTHRES 0x00001F00U
6509 #define QUADSPI_CR_FTHRES_0 0x00000100U
6510 #define QUADSPI_CR_FTHRES_1 0x00000200U
6511 #define QUADSPI_CR_FTHRES_2 0x00000400U
6512 #define QUADSPI_CR_FTHRES_3 0x00000800U
6513 #define QUADSPI_CR_FTHRES_4 0x00001000U
6514 #define QUADSPI_CR_TEIE 0x00010000U
6515 #define QUADSPI_CR_TCIE 0x00020000U
6516 #define QUADSPI_CR_FTIE 0x00040000U
6517 #define QUADSPI_CR_SMIE 0x00080000U
6518 #define QUADSPI_CR_TOIE 0x00100000U
6519 #define QUADSPI_CR_APMS 0x00400000U
6520 #define QUADSPI_CR_PMM 0x00800000U
6521 #define QUADSPI_CR_PRESCALER 0xFF000000U
6522 #define QUADSPI_CR_PRESCALER_0 0x01000000U
6523 #define QUADSPI_CR_PRESCALER_1 0x02000000U
6524 #define QUADSPI_CR_PRESCALER_2 0x04000000U
6525 #define QUADSPI_CR_PRESCALER_3 0x08000000U
6526 #define QUADSPI_CR_PRESCALER_4 0x10000000U
6527 #define QUADSPI_CR_PRESCALER_5 0x20000000U
6528 #define QUADSPI_CR_PRESCALER_6 0x40000000U
6529 #define QUADSPI_CR_PRESCALER_7 0x80000000U
6531 /***************** Bit definition for QUADSPI_DCR register ******************/
6532 #define QUADSPI_DCR_CKMODE 0x00000001U
6533 #define QUADSPI_DCR_CSHT 0x00000700U
6534 #define QUADSPI_DCR_CSHT_0 0x00000100U
6535 #define QUADSPI_DCR_CSHT_1 0x00000200U
6536 #define QUADSPI_DCR_CSHT_2 0x00000400U
6537 #define QUADSPI_DCR_FSIZE 0x001F0000U
6538 #define QUADSPI_DCR_FSIZE_0 0x00010000U
6539 #define QUADSPI_DCR_FSIZE_1 0x00020000U
6540 #define QUADSPI_DCR_FSIZE_2 0x00040000U
6541 #define QUADSPI_DCR_FSIZE_3 0x00080000U
6542 #define QUADSPI_DCR_FSIZE_4 0x00100000U
6544 /****************** Bit definition for QUADSPI_SR register *******************/
6545 #define QUADSPI_SR_TEF 0x00000001U
6546 #define QUADSPI_SR_TCF 0x00000002U
6547 #define QUADSPI_SR_FTF 0x00000004U
6548 #define QUADSPI_SR_SMF 0x00000008U
6549 #define QUADSPI_SR_TOF 0x00000010U
6550 #define QUADSPI_SR_BUSY 0x00000020U
6551 #define QUADSPI_SR_FLEVEL 0x00003F00U
6552 #define QUADSPI_SR_FLEVEL_0 0x00000100U
6553 #define QUADSPI_SR_FLEVEL_1 0x00000200U
6554 #define QUADSPI_SR_FLEVEL_2 0x00000400U
6555 #define QUADSPI_SR_FLEVEL_3 0x00000800U
6556 #define QUADSPI_SR_FLEVEL_4 0x00001000U
6557 #define QUADSPI_SR_FLEVEL_5 0x00002000U
6559 /****************** Bit definition for QUADSPI_FCR register ******************/
6560 #define QUADSPI_FCR_CTEF 0x00000001U
6561 #define QUADSPI_FCR_CTCF 0x00000002U
6562 #define QUADSPI_FCR_CSMF 0x00000008U
6563 #define QUADSPI_FCR_CTOF 0x00000010U
6565 /****************** Bit definition for QUADSPI_DLR register ******************/
6566 #define QUADSPI_DLR_DL 0xFFFFFFFFU
6568 /****************** Bit definition for QUADSPI_CCR register ******************/
6569 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
6570 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
6571 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
6572 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
6573 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
6574 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
6575 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
6576 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
6577 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
6578 #define QUADSPI_CCR_IMODE 0x00000300U
6579 #define QUADSPI_CCR_IMODE_0 0x00000100U
6580 #define QUADSPI_CCR_IMODE_1 0x00000200U
6581 #define QUADSPI_CCR_ADMODE 0x00000C00U
6582 #define QUADSPI_CCR_ADMODE_0 0x00000400U
6583 #define QUADSPI_CCR_ADMODE_1 0x00000800U
6584 #define QUADSPI_CCR_ADSIZE 0x00003000U
6585 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
6586 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
6587 #define QUADSPI_CCR_ABMODE 0x0000C000U
6588 #define QUADSPI_CCR_ABMODE_0 0x00004000U
6589 #define QUADSPI_CCR_ABMODE_1 0x00008000U
6590 #define QUADSPI_CCR_ABSIZE 0x00030000U
6591 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
6592 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
6593 #define QUADSPI_CCR_DCYC 0x007C0000U
6594 #define QUADSPI_CCR_DCYC_0 0x00040000U
6595 #define QUADSPI_CCR_DCYC_1 0x00080000U
6596 #define QUADSPI_CCR_DCYC_2 0x00100000U
6597 #define QUADSPI_CCR_DCYC_3 0x00200000U
6598 #define QUADSPI_CCR_DCYC_4 0x00400000U
6599 #define QUADSPI_CCR_DMODE 0x03000000U
6600 #define QUADSPI_CCR_DMODE_0 0x01000000U
6601 #define QUADSPI_CCR_DMODE_1 0x02000000U
6602 #define QUADSPI_CCR_FMODE 0x0C000000U
6603 #define QUADSPI_CCR_FMODE_0 0x04000000U
6604 #define QUADSPI_CCR_FMODE_1 0x08000000U
6605 #define QUADSPI_CCR_SIOO 0x10000000U
6606 #define QUADSPI_CCR_DHHC 0x40000000U
6607 #define QUADSPI_CCR_DDRM 0x80000000U
6608 /****************** Bit definition for QUADSPI_AR register *******************/
6609 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
6611 /****************** Bit definition for QUADSPI_ABR register ******************/
6612 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
6614 /****************** Bit definition for QUADSPI_DR register *******************/
6615 #define QUADSPI_DR_DATA 0xFFFFFFFFU
6617 /****************** Bit definition for QUADSPI_PSMKR register ****************/
6618 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
6620 /****************** Bit definition for QUADSPI_PSMAR register ****************/
6621 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
6623 /****************** Bit definition for QUADSPI_PIR register *****************/
6624 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
6626 /****************** Bit definition for QUADSPI_LPTR register *****************/
6627 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
6629 /******************************************************************************/
6630 /* */
6631 /* Reset and Clock Control */
6632 /* */
6633 /******************************************************************************/
6634 /******************** Bit definition for RCC_CR register ********************/
6635 #define RCC_CR_HSION 0x00000001U
6636 #define RCC_CR_HSIRDY 0x00000002U
6637 
6638 #define RCC_CR_HSITRIM 0x000000F8U
6639 #define RCC_CR_HSITRIM_0 0x00000008U
6640 #define RCC_CR_HSITRIM_1 0x00000010U
6641 #define RCC_CR_HSITRIM_2 0x00000020U
6642 #define RCC_CR_HSITRIM_3 0x00000040U
6643 #define RCC_CR_HSITRIM_4 0x00000080U
6645 #define RCC_CR_HSICAL 0x0000FF00U
6646 #define RCC_CR_HSICAL_0 0x00000100U
6647 #define RCC_CR_HSICAL_1 0x00000200U
6648 #define RCC_CR_HSICAL_2 0x00000400U
6649 #define RCC_CR_HSICAL_3 0x00000800U
6650 #define RCC_CR_HSICAL_4 0x00001000U
6651 #define RCC_CR_HSICAL_5 0x00002000U
6652 #define RCC_CR_HSICAL_6 0x00004000U
6653 #define RCC_CR_HSICAL_7 0x00008000U
6655 #define RCC_CR_HSEON 0x00010000U
6656 #define RCC_CR_HSERDY 0x00020000U
6657 #define RCC_CR_HSEBYP 0x00040000U
6658 #define RCC_CR_CSSON 0x00080000U
6659 #define RCC_CR_PLLON 0x01000000U
6660 #define RCC_CR_PLLRDY 0x02000000U
6661 #define RCC_CR_PLLI2SON 0x04000000U
6662 #define RCC_CR_PLLI2SRDY 0x08000000U
6663 #define RCC_CR_PLLSAION 0x10000000U
6664 #define RCC_CR_PLLSAIRDY 0x20000000U
6665 
6666 /******************** Bit definition for RCC_PLLCFGR register ***************/
6667 #define RCC_PLLCFGR_PLLM 0x0000003FU
6668 #define RCC_PLLCFGR_PLLM_0 0x00000001U
6669 #define RCC_PLLCFGR_PLLM_1 0x00000002U
6670 #define RCC_PLLCFGR_PLLM_2 0x00000004U
6671 #define RCC_PLLCFGR_PLLM_3 0x00000008U
6672 #define RCC_PLLCFGR_PLLM_4 0x00000010U
6673 #define RCC_PLLCFGR_PLLM_5 0x00000020U
6674 
6675 #define RCC_PLLCFGR_PLLN 0x00007FC0U
6676 #define RCC_PLLCFGR_PLLN_0 0x00000040U
6677 #define RCC_PLLCFGR_PLLN_1 0x00000080U
6678 #define RCC_PLLCFGR_PLLN_2 0x00000100U
6679 #define RCC_PLLCFGR_PLLN_3 0x00000200U
6680 #define RCC_PLLCFGR_PLLN_4 0x00000400U
6681 #define RCC_PLLCFGR_PLLN_5 0x00000800U
6682 #define RCC_PLLCFGR_PLLN_6 0x00001000U
6683 #define RCC_PLLCFGR_PLLN_7 0x00002000U
6684 #define RCC_PLLCFGR_PLLN_8 0x00004000U
6685 
6686 #define RCC_PLLCFGR_PLLP 0x00030000U
6687 #define RCC_PLLCFGR_PLLP_0 0x00010000U
6688 #define RCC_PLLCFGR_PLLP_1 0x00020000U
6689 
6690 #define RCC_PLLCFGR_PLLSRC 0x00400000U
6691 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
6692 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
6693 
6694 #define RCC_PLLCFGR_PLLQ 0x0F000000U
6695 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
6696 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
6697 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
6698 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
6699 
6700 #define RCC_PLLCFGR_PLLR 0x70000000U
6701 #define RCC_PLLCFGR_PLLR_0 0x10000000U
6702 #define RCC_PLLCFGR_PLLR_1 0x20000000U
6703 #define RCC_PLLCFGR_PLLR_2 0x40000000U
6704 
6705 
6706 /******************** Bit definition for RCC_CFGR register ******************/
6708 #define RCC_CFGR_SW 0x00000003U
6709 #define RCC_CFGR_SW_0 0x00000001U
6710 #define RCC_CFGR_SW_1 0x00000002U
6712 #define RCC_CFGR_SW_HSI 0x00000000U
6713 #define RCC_CFGR_SW_HSE 0x00000001U
6714 #define RCC_CFGR_SW_PLL 0x00000002U
6717 #define RCC_CFGR_SWS 0x0000000CU
6718 #define RCC_CFGR_SWS_0 0x00000004U
6719 #define RCC_CFGR_SWS_1 0x00000008U
6721 #define RCC_CFGR_SWS_HSI 0x00000000U
6722 #define RCC_CFGR_SWS_HSE 0x00000004U
6723 #define RCC_CFGR_SWS_PLL 0x00000008U
6726 #define RCC_CFGR_HPRE 0x000000F0U
6727 #define RCC_CFGR_HPRE_0 0x00000010U
6728 #define RCC_CFGR_HPRE_1 0x00000020U
6729 #define RCC_CFGR_HPRE_2 0x00000040U
6730 #define RCC_CFGR_HPRE_3 0x00000080U
6732 #define RCC_CFGR_HPRE_DIV1 0x00000000U
6733 #define RCC_CFGR_HPRE_DIV2 0x00000080U
6734 #define RCC_CFGR_HPRE_DIV4 0x00000090U
6735 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
6736 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
6737 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
6738 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
6739 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
6740 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
6743 #define RCC_CFGR_PPRE1 0x00001C00U
6744 #define RCC_CFGR_PPRE1_0 0x00000400U
6745 #define RCC_CFGR_PPRE1_1 0x00000800U
6746 #define RCC_CFGR_PPRE1_2 0x00001000U
6748 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
6749 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
6750 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
6751 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
6752 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
6755 #define RCC_CFGR_PPRE2 0x0000E000U
6756 #define RCC_CFGR_PPRE2_0 0x00002000U
6757 #define RCC_CFGR_PPRE2_1 0x00004000U
6758 #define RCC_CFGR_PPRE2_2 0x00008000U
6760 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
6761 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
6762 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
6763 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
6764 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
6767 #define RCC_CFGR_RTCPRE 0x001F0000U
6768 #define RCC_CFGR_RTCPRE_0 0x00010000U
6769 #define RCC_CFGR_RTCPRE_1 0x00020000U
6770 #define RCC_CFGR_RTCPRE_2 0x00040000U
6771 #define RCC_CFGR_RTCPRE_3 0x00080000U
6772 #define RCC_CFGR_RTCPRE_4 0x00100000U
6773 
6775 #define RCC_CFGR_MCO1 0x00600000U
6776 #define RCC_CFGR_MCO1_0 0x00200000U
6777 #define RCC_CFGR_MCO1_1 0x00400000U
6778 
6779 #define RCC_CFGR_I2SSRC 0x00800000U
6780 
6781 #define RCC_CFGR_MCO1PRE 0x07000000U
6782 #define RCC_CFGR_MCO1PRE_0 0x01000000U
6783 #define RCC_CFGR_MCO1PRE_1 0x02000000U
6784 #define RCC_CFGR_MCO1PRE_2 0x04000000U
6785 
6786 #define RCC_CFGR_MCO2PRE 0x38000000U
6787 #define RCC_CFGR_MCO2PRE_0 0x08000000U
6788 #define RCC_CFGR_MCO2PRE_1 0x10000000U
6789 #define RCC_CFGR_MCO2PRE_2 0x20000000U
6790 
6791 #define RCC_CFGR_MCO2 0xC0000000U
6792 #define RCC_CFGR_MCO2_0 0x40000000U
6793 #define RCC_CFGR_MCO2_1 0x80000000U
6794 
6795 /******************** Bit definition for RCC_CIR register *******************/
6796 #define RCC_CIR_LSIRDYF 0x00000001U
6797 #define RCC_CIR_LSERDYF 0x00000002U
6798 #define RCC_CIR_HSIRDYF 0x00000004U
6799 #define RCC_CIR_HSERDYF 0x00000008U
6800 #define RCC_CIR_PLLRDYF 0x00000010U
6801 #define RCC_CIR_PLLI2SRDYF 0x00000020U
6802 #define RCC_CIR_PLLSAIRDYF 0x00000040U
6803 #define RCC_CIR_CSSF 0x00000080U
6804 #define RCC_CIR_LSIRDYIE 0x00000100U
6805 #define RCC_CIR_LSERDYIE 0x00000200U
6806 #define RCC_CIR_HSIRDYIE 0x00000400U
6807 #define RCC_CIR_HSERDYIE 0x00000800U
6808 #define RCC_CIR_PLLRDYIE 0x00001000U
6809 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
6810 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
6811 #define RCC_CIR_LSIRDYC 0x00010000U
6812 #define RCC_CIR_LSERDYC 0x00020000U
6813 #define RCC_CIR_HSIRDYC 0x00040000U
6814 #define RCC_CIR_HSERDYC 0x00080000U
6815 #define RCC_CIR_PLLRDYC 0x00100000U
6816 #define RCC_CIR_PLLI2SRDYC 0x00200000U
6817 #define RCC_CIR_PLLSAIRDYC 0x00400000U
6818 #define RCC_CIR_CSSC 0x00800000U
6819 
6820 /******************** Bit definition for RCC_AHB1RSTR register **************/
6821 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
6822 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
6823 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
6824 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
6825 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
6826 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
6827 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
6828 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
6829 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
6830 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
6831 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
6832 #define RCC_AHB1RSTR_CRCRST 0x00001000U
6833 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
6834 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
6835 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
6836 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
6837 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
6838 
6839 /******************** Bit definition for RCC_AHB2RSTR register **************/
6840 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
6841 #define RCC_AHB2RSTR_RNGRST 0x00000040U
6842 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
6843 
6844 /******************** Bit definition for RCC_AHB3RSTR register **************/
6845 #define RCC_AHB3RSTR_FMCRST 0x00000001U
6846 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
6847 
6848 /******************** Bit definition for RCC_APB1RSTR register **************/
6849 #define RCC_APB1RSTR_TIM2RST 0x00000001U
6850 #define RCC_APB1RSTR_TIM3RST 0x00000002U
6851 #define RCC_APB1RSTR_TIM4RST 0x00000004U
6852 #define RCC_APB1RSTR_TIM5RST 0x00000008U
6853 #define RCC_APB1RSTR_TIM6RST 0x00000010U
6854 #define RCC_APB1RSTR_TIM7RST 0x00000020U
6855 #define RCC_APB1RSTR_TIM12RST 0x00000040U
6856 #define RCC_APB1RSTR_TIM13RST 0x00000080U
6857 #define RCC_APB1RSTR_TIM14RST 0x00000100U
6858 #define RCC_APB1RSTR_WWDGRST 0x00000800U
6859 #define RCC_APB1RSTR_SPI2RST 0x00004000U
6860 #define RCC_APB1RSTR_SPI3RST 0x00008000U
6861 #define RCC_APB1RSTR_USART2RST 0x00020000U
6862 #define RCC_APB1RSTR_USART3RST 0x00040000U
6863 #define RCC_APB1RSTR_UART4RST 0x00080000U
6864 #define RCC_APB1RSTR_UART5RST 0x00100000U
6865 #define RCC_APB1RSTR_I2C1RST 0x00200000U
6866 #define RCC_APB1RSTR_I2C2RST 0x00400000U
6867 #define RCC_APB1RSTR_I2C3RST 0x00800000U
6868 #define RCC_APB1RSTR_CAN1RST 0x02000000U
6869 #define RCC_APB1RSTR_CAN2RST 0x04000000U
6870 #define RCC_APB1RSTR_PWRRST 0x10000000U
6871 #define RCC_APB1RSTR_DACRST 0x20000000U
6872 #define RCC_APB1RSTR_UART7RST 0x40000000U
6873 #define RCC_APB1RSTR_UART8RST 0x80000000U
6874 
6875 /******************** Bit definition for RCC_APB2RSTR register **************/
6876 #define RCC_APB2RSTR_TIM1RST 0x00000001U
6877 #define RCC_APB2RSTR_TIM8RST 0x00000002U
6878 #define RCC_APB2RSTR_USART1RST 0x00000010U
6879 #define RCC_APB2RSTR_USART6RST 0x00000020U
6880 #define RCC_APB2RSTR_ADCRST 0x00000100U
6881 #define RCC_APB2RSTR_SDIORST 0x00000800U
6882 #define RCC_APB2RSTR_SPI1RST 0x00001000U
6883 #define RCC_APB2RSTR_SPI4RST 0x00002000U
6884 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
6885 #define RCC_APB2RSTR_TIM9RST 0x00010000U
6886 #define RCC_APB2RSTR_TIM10RST 0x00020000U
6887 #define RCC_APB2RSTR_TIM11RST 0x00040000U
6888 #define RCC_APB2RSTR_SPI5RST 0x00100000U
6889 #define RCC_APB2RSTR_SPI6RST 0x00200000U
6890 #define RCC_APB2RSTR_SAI1RST 0x00400000U
6891 #define RCC_APB2RSTR_LTDCRST 0x04000000U
6892 #define RCC_APB2RSTR_DSIRST 0x08000000U
6893 
6894 /* Old SPI1RST bit definition, maintained for legacy purpose */
6895 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
6896 
6897 /******************** Bit definition for RCC_AHB1ENR register ***************/
6898 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
6899 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
6900 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
6901 #define RCC_AHB1ENR_GPIODEN 0x00000008U
6902 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
6903 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
6904 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
6905 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
6906 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
6907 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
6908 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
6909 
6910 #define RCC_AHB1ENR_CRCEN 0x00001000U
6911 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
6912 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
6913 #define RCC_AHB1ENR_DMA1EN 0x00200000U
6914 #define RCC_AHB1ENR_DMA2EN 0x00400000U
6915 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
6916 
6917 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
6918 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
6919 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
6920 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
6921 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
6922 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
6923 
6924 /******************** Bit definition for RCC_AHB2ENR register ***************/
6925 #define RCC_AHB2ENR_DCMIEN 0x00000001U
6926 #define RCC_AHB2ENR_RNGEN 0x00000040U
6927 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
6928 
6929 /******************** Bit definition for RCC_AHB3ENR register ***************/
6930 #define RCC_AHB3ENR_FMCEN 0x00000001U
6931 #define RCC_AHB3ENR_QSPIEN 0x00000002U
6932 
6933 /******************** Bit definition for RCC_APB1ENR register ***************/
6934 #define RCC_APB1ENR_TIM2EN 0x00000001U
6935 #define RCC_APB1ENR_TIM3EN 0x00000002U
6936 #define RCC_APB1ENR_TIM4EN 0x00000004U
6937 #define RCC_APB1ENR_TIM5EN 0x00000008U
6938 #define RCC_APB1ENR_TIM6EN 0x00000010U
6939 #define RCC_APB1ENR_TIM7EN 0x00000020U
6940 #define RCC_APB1ENR_TIM12EN 0x00000040U
6941 #define RCC_APB1ENR_TIM13EN 0x00000080U
6942 #define RCC_APB1ENR_TIM14EN 0x00000100U
6943 #define RCC_APB1ENR_WWDGEN 0x00000800U
6944 #define RCC_APB1ENR_SPI2EN 0x00004000U
6945 #define RCC_APB1ENR_SPI3EN 0x00008000U
6946 #define RCC_APB1ENR_USART2EN 0x00020000U
6947 #define RCC_APB1ENR_USART3EN 0x00040000U
6948 #define RCC_APB1ENR_UART4EN 0x00080000U
6949 #define RCC_APB1ENR_UART5EN 0x00100000U
6950 #define RCC_APB1ENR_I2C1EN 0x00200000U
6951 #define RCC_APB1ENR_I2C2EN 0x00400000U
6952 #define RCC_APB1ENR_I2C3EN 0x00800000U
6953 #define RCC_APB1ENR_CAN1EN 0x02000000U
6954 #define RCC_APB1ENR_CAN2EN 0x04000000U
6955 #define RCC_APB1ENR_PWREN 0x10000000U
6956 #define RCC_APB1ENR_DACEN 0x20000000U
6957 #define RCC_APB1ENR_UART7EN 0x40000000U
6958 #define RCC_APB1ENR_UART8EN 0x80000000U
6959 
6960 /******************** Bit definition for RCC_APB2ENR register ***************/
6961 #define RCC_APB2ENR_TIM1EN 0x00000001U
6962 #define RCC_APB2ENR_TIM8EN 0x00000002U
6963 #define RCC_APB2ENR_USART1EN 0x00000010U
6964 #define RCC_APB2ENR_USART6EN 0x00000020U
6965 #define RCC_APB2ENR_ADC1EN 0x00000100U
6966 #define RCC_APB2ENR_ADC2EN 0x00000200U
6967 #define RCC_APB2ENR_ADC3EN 0x00000400U
6968 #define RCC_APB2ENR_SDIOEN 0x00000800U
6969 #define RCC_APB2ENR_SPI1EN 0x00001000U
6970 #define RCC_APB2ENR_SPI4EN 0x00002000U
6971 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
6972 #define RCC_APB2ENR_TIM9EN 0x00010000U
6973 #define RCC_APB2ENR_TIM10EN 0x00020000U
6974 #define RCC_APB2ENR_TIM11EN 0x00040000U
6975 #define RCC_APB2ENR_SPI5EN 0x00100000U
6976 #define RCC_APB2ENR_SPI6EN 0x00200000U
6977 #define RCC_APB2ENR_SAI1EN 0x00400000U
6978 #define RCC_APB2ENR_LTDCEN 0x04000000U
6979 #define RCC_APB2ENR_DSIEN 0x08000000U
6980 
6981 /******************** Bit definition for RCC_AHB1LPENR register *************/
6982 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
6983 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
6984 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
6985 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
6986 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
6987 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
6988 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
6989 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
6990 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
6991 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
6992 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
6993 
6994 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
6995 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
6996 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
6997 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
6998 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
6999 #define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
7000 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
7001 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
7002 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
7003 
7004 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
7005 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
7006 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
7007 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
7008 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
7009 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
7010 
7011 /******************** Bit definition for RCC_AHB2LPENR register *************/
7012 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
7013 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
7014 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
7015 
7016 /******************** Bit definition for RCC_AHB3LPENR register *************/
7017 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
7018 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
7019 
7020 /******************** Bit definition for RCC_APB1LPENR register *************/
7021 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
7022 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
7023 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
7024 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
7025 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
7026 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
7027 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
7028 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
7029 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
7030 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
7031 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
7032 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
7033 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
7034 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
7035 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
7036 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
7037 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
7038 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
7039 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
7040 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
7041 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
7042 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
7043 #define RCC_APB1LPENR_DACLPEN 0x20000000U
7044 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
7045 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
7046 
7047 /******************** Bit definition for RCC_APB2LPENR register *************/
7048 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
7049 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
7050 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
7051 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
7052 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
7053 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
7054 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
7055 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
7056 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
7057 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
7058 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
7059 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
7060 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
7061 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
7062 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
7063 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
7064 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
7065 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
7066 #define RCC_APB2LPENR_DSILPEN 0x08000000U
7067 
7068 /******************** Bit definition for RCC_BDCR register ******************/
7069 #define RCC_BDCR_LSEON 0x00000001U
7070 #define RCC_BDCR_LSERDY 0x00000002U
7071 #define RCC_BDCR_LSEBYP 0x00000004U
7072 #define RCC_BDCR_LSEMOD 0x00000008U
7073 
7074 #define RCC_BDCR_RTCSEL 0x00000300U
7075 #define RCC_BDCR_RTCSEL_0 0x00000100U
7076 #define RCC_BDCR_RTCSEL_1 0x00000200U
7077 
7078 #define RCC_BDCR_RTCEN 0x00008000U
7079 #define RCC_BDCR_BDRST 0x00010000U
7080 
7081 /******************** Bit definition for RCC_CSR register *******************/
7082 #define RCC_CSR_LSION 0x00000001U
7083 #define RCC_CSR_LSIRDY 0x00000002U
7084 #define RCC_CSR_RMVF 0x01000000U
7085 #define RCC_CSR_BORRSTF 0x02000000U
7086 #define RCC_CSR_PADRSTF 0x04000000U
7087 #define RCC_CSR_PORRSTF 0x08000000U
7088 #define RCC_CSR_SFTRSTF 0x10000000U
7089 #define RCC_CSR_WDGRSTF 0x20000000U
7090 #define RCC_CSR_WWDGRSTF 0x40000000U
7091 #define RCC_CSR_LPWRRSTF 0x80000000U
7092 
7093 /******************** Bit definition for RCC_SSCGR register *****************/
7094 #define RCC_SSCGR_MODPER 0x00001FFFU
7095 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
7096 #define RCC_SSCGR_SPREADSEL 0x40000000U
7097 #define RCC_SSCGR_SSCGEN 0x80000000U
7098 
7099 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
7100 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
7101 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
7102 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
7103 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
7104 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
7105 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
7106 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
7107 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
7108 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
7109 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
7110 
7111 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
7112 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
7113 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
7114 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
7115 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
7116 
7117 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
7118 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
7119 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
7120 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
7121 
7122 
7123 /******************** Bit definition for RCC_PLLSAICFGR register ************/
7124 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
7125 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
7126 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
7127 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
7128 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
7129 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
7130 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
7131 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
7132 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
7133 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
7134 
7135 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
7136 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
7137 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
7138 
7139 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
7140 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
7141 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
7142 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
7143 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
7144 
7145 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
7146 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
7147 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
7148 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
7149 
7150 /******************** Bit definition for RCC_DCKCFGR register ***************/
7151 #define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
7152 #define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
7153 #define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
7154 #define RCC_DCKCFGR_SAI1ASRC 0x00300000U
7155 #define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
7156 #define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
7157 #define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
7158 #define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
7159 #define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
7160 #define RCC_DCKCFGR_TIMPRE 0x01000000U
7161 #define RCC_DCKCFGR_CK48MSEL 0x08000000U
7162 #define RCC_DCKCFGR_SDIOSEL 0x10000000U
7163 #define RCC_DCKCFGR_DSISEL 0x20000000U
7164 
7165 /******************************************************************************/
7166 /* */
7167 /* RNG */
7168 /* */
7169 /******************************************************************************/
7170 /******************** Bits definition for RNG_CR register *******************/
7171 #define RNG_CR_RNGEN 0x00000004U
7172 #define RNG_CR_IE 0x00000008U
7173 
7174 /******************** Bits definition for RNG_SR register *******************/
7175 #define RNG_SR_DRDY 0x00000001U
7176 #define RNG_SR_CECS 0x00000002U
7177 #define RNG_SR_SECS 0x00000004U
7178 #define RNG_SR_CEIS 0x00000020U
7179 #define RNG_SR_SEIS 0x00000040U
7180 
7181 /******************************************************************************/
7182 /* */
7183 /* Real-Time Clock (RTC) */
7184 /* */
7185 /******************************************************************************/
7186 /******************** Bits definition for RTC_TR register *******************/
7187 #define RTC_TR_PM 0x00400000U
7188 #define RTC_TR_HT 0x00300000U
7189 #define RTC_TR_HT_0 0x00100000U
7190 #define RTC_TR_HT_1 0x00200000U
7191 #define RTC_TR_HU 0x000F0000U
7192 #define RTC_TR_HU_0 0x00010000U
7193 #define RTC_TR_HU_1 0x00020000U
7194 #define RTC_TR_HU_2 0x00040000U
7195 #define RTC_TR_HU_3 0x00080000U
7196 #define RTC_TR_MNT 0x00007000U
7197 #define RTC_TR_MNT_0 0x00001000U
7198 #define RTC_TR_MNT_1 0x00002000U
7199 #define RTC_TR_MNT_2 0x00004000U
7200 #define RTC_TR_MNU 0x00000F00U
7201 #define RTC_TR_MNU_0 0x00000100U
7202 #define RTC_TR_MNU_1 0x00000200U
7203 #define RTC_TR_MNU_2 0x00000400U
7204 #define RTC_TR_MNU_3 0x00000800U
7205 #define RTC_TR_ST 0x00000070U
7206 #define RTC_TR_ST_0 0x00000010U
7207 #define RTC_TR_ST_1 0x00000020U
7208 #define RTC_TR_ST_2 0x00000040U
7209 #define RTC_TR_SU 0x0000000FU
7210 #define RTC_TR_SU_0 0x00000001U
7211 #define RTC_TR_SU_1 0x00000002U
7212 #define RTC_TR_SU_2 0x00000004U
7213 #define RTC_TR_SU_3 0x00000008U
7214 
7215 /******************** Bits definition for RTC_DR register *******************/
7216 #define RTC_DR_YT 0x00F00000U
7217 #define RTC_DR_YT_0 0x00100000U
7218 #define RTC_DR_YT_1 0x00200000U
7219 #define RTC_DR_YT_2 0x00400000U
7220 #define RTC_DR_YT_3 0x00800000U
7221 #define RTC_DR_YU 0x000F0000U
7222 #define RTC_DR_YU_0 0x00010000U
7223 #define RTC_DR_YU_1 0x00020000U
7224 #define RTC_DR_YU_2 0x00040000U
7225 #define RTC_DR_YU_3 0x00080000U
7226 #define RTC_DR_WDU 0x0000E000U
7227 #define RTC_DR_WDU_0 0x00002000U
7228 #define RTC_DR_WDU_1 0x00004000U
7229 #define RTC_DR_WDU_2 0x00008000U
7230 #define RTC_DR_MT 0x00001000U
7231 #define RTC_DR_MU 0x00000F00U
7232 #define RTC_DR_MU_0 0x00000100U
7233 #define RTC_DR_MU_1 0x00000200U
7234 #define RTC_DR_MU_2 0x00000400U
7235 #define RTC_DR_MU_3 0x00000800U
7236 #define RTC_DR_DT 0x00000030U
7237 #define RTC_DR_DT_0 0x00000010U
7238 #define RTC_DR_DT_1 0x00000020U
7239 #define RTC_DR_DU 0x0000000FU
7240 #define RTC_DR_DU_0 0x00000001U
7241 #define RTC_DR_DU_1 0x00000002U
7242 #define RTC_DR_DU_2 0x00000004U
7243 #define RTC_DR_DU_3 0x00000008U
7244 
7245 /******************** Bits definition for RTC_CR register *******************/
7246 #define RTC_CR_COE 0x00800000U
7247 #define RTC_CR_OSEL 0x00600000U
7248 #define RTC_CR_OSEL_0 0x00200000U
7249 #define RTC_CR_OSEL_1 0x00400000U
7250 #define RTC_CR_POL 0x00100000U
7251 #define RTC_CR_COSEL 0x00080000U
7252 #define RTC_CR_BCK 0x00040000U
7253 #define RTC_CR_SUB1H 0x00020000U
7254 #define RTC_CR_ADD1H 0x00010000U
7255 #define RTC_CR_TSIE 0x00008000U
7256 #define RTC_CR_WUTIE 0x00004000U
7257 #define RTC_CR_ALRBIE 0x00002000U
7258 #define RTC_CR_ALRAIE 0x00001000U
7259 #define RTC_CR_TSE 0x00000800U
7260 #define RTC_CR_WUTE 0x00000400U
7261 #define RTC_CR_ALRBE 0x00000200U
7262 #define RTC_CR_ALRAE 0x00000100U
7263 #define RTC_CR_DCE 0x00000080U
7264 #define RTC_CR_FMT 0x00000040U
7265 #define RTC_CR_BYPSHAD 0x00000020U
7266 #define RTC_CR_REFCKON 0x00000010U
7267 #define RTC_CR_TSEDGE 0x00000008U
7268 #define RTC_CR_WUCKSEL 0x00000007U
7269 #define RTC_CR_WUCKSEL_0 0x00000001U
7270 #define RTC_CR_WUCKSEL_1 0x00000002U
7271 #define RTC_CR_WUCKSEL_2 0x00000004U
7272 
7273 /******************** Bits definition for RTC_ISR register ******************/
7274 #define RTC_ISR_RECALPF 0x00010000U
7275 #define RTC_ISR_TAMP1F 0x00002000U
7276 #define RTC_ISR_TAMP2F 0x00004000U
7277 #define RTC_ISR_TSOVF 0x00001000U
7278 #define RTC_ISR_TSF 0x00000800U
7279 #define RTC_ISR_WUTF 0x00000400U
7280 #define RTC_ISR_ALRBF 0x00000200U
7281 #define RTC_ISR_ALRAF 0x00000100U
7282 #define RTC_ISR_INIT 0x00000080U
7283 #define RTC_ISR_INITF 0x00000040U
7284 #define RTC_ISR_RSF 0x00000020U
7285 #define RTC_ISR_INITS 0x00000010U
7286 #define RTC_ISR_SHPF 0x00000008U
7287 #define RTC_ISR_WUTWF 0x00000004U
7288 #define RTC_ISR_ALRBWF 0x00000002U
7289 #define RTC_ISR_ALRAWF 0x00000001U
7290 
7291 /******************** Bits definition for RTC_PRER register *****************/
7292 #define RTC_PRER_PREDIV_A 0x007F0000U
7293 #define RTC_PRER_PREDIV_S 0x00007FFFU
7294 
7295 /******************** Bits definition for RTC_WUTR register *****************/
7296 #define RTC_WUTR_WUT 0x0000FFFFU
7297 
7298 /******************** Bits definition for RTC_CALIBR register ***************/
7299 #define RTC_CALIBR_DCS 0x00000080U
7300 #define RTC_CALIBR_DC 0x0000001FU
7301 
7302 /******************** Bits definition for RTC_ALRMAR register ***************/
7303 #define RTC_ALRMAR_MSK4 0x80000000U
7304 #define RTC_ALRMAR_WDSEL 0x40000000U
7305 #define RTC_ALRMAR_DT 0x30000000U
7306 #define RTC_ALRMAR_DT_0 0x10000000U
7307 #define RTC_ALRMAR_DT_1 0x20000000U
7308 #define RTC_ALRMAR_DU 0x0F000000U
7309 #define RTC_ALRMAR_DU_0 0x01000000U
7310 #define RTC_ALRMAR_DU_1 0x02000000U
7311 #define RTC_ALRMAR_DU_2 0x04000000U
7312 #define RTC_ALRMAR_DU_3 0x08000000U
7313 #define RTC_ALRMAR_MSK3 0x00800000U
7314 #define RTC_ALRMAR_PM 0x00400000U
7315 #define RTC_ALRMAR_HT 0x00300000U
7316 #define RTC_ALRMAR_HT_0 0x00100000U
7317 #define RTC_ALRMAR_HT_1 0x00200000U
7318 #define RTC_ALRMAR_HU 0x000F0000U
7319 #define RTC_ALRMAR_HU_0 0x00010000U
7320 #define RTC_ALRMAR_HU_1 0x00020000U
7321 #define RTC_ALRMAR_HU_2 0x00040000U
7322 #define RTC_ALRMAR_HU_3 0x00080000U
7323 #define RTC_ALRMAR_MSK2 0x00008000U
7324 #define RTC_ALRMAR_MNT 0x00007000U
7325 #define RTC_ALRMAR_MNT_0 0x00001000U
7326 #define RTC_ALRMAR_MNT_1 0x00002000U
7327 #define RTC_ALRMAR_MNT_2 0x00004000U
7328 #define RTC_ALRMAR_MNU 0x00000F00U
7329 #define RTC_ALRMAR_MNU_0 0x00000100U
7330 #define RTC_ALRMAR_MNU_1 0x00000200U
7331 #define RTC_ALRMAR_MNU_2 0x00000400U
7332 #define RTC_ALRMAR_MNU_3 0x00000800U
7333 #define RTC_ALRMAR_MSK1 0x00000080U
7334 #define RTC_ALRMAR_ST 0x00000070U
7335 #define RTC_ALRMAR_ST_0 0x00000010U
7336 #define RTC_ALRMAR_ST_1 0x00000020U
7337 #define RTC_ALRMAR_ST_2 0x00000040U
7338 #define RTC_ALRMAR_SU 0x0000000FU
7339 #define RTC_ALRMAR_SU_0 0x00000001U
7340 #define RTC_ALRMAR_SU_1 0x00000002U
7341 #define RTC_ALRMAR_SU_2 0x00000004U
7342 #define RTC_ALRMAR_SU_3 0x00000008U
7343 
7344 /******************** Bits definition for RTC_ALRMBR register ***************/
7345 #define RTC_ALRMBR_MSK4 0x80000000U
7346 #define RTC_ALRMBR_WDSEL 0x40000000U
7347 #define RTC_ALRMBR_DT 0x30000000U
7348 #define RTC_ALRMBR_DT_0 0x10000000U
7349 #define RTC_ALRMBR_DT_1 0x20000000U
7350 #define RTC_ALRMBR_DU 0x0F000000U
7351 #define RTC_ALRMBR_DU_0 0x01000000U
7352 #define RTC_ALRMBR_DU_1 0x02000000U
7353 #define RTC_ALRMBR_DU_2 0x04000000U
7354 #define RTC_ALRMBR_DU_3 0x08000000U
7355 #define RTC_ALRMBR_MSK3 0x00800000U
7356 #define RTC_ALRMBR_PM 0x00400000U
7357 #define RTC_ALRMBR_HT 0x00300000U
7358 #define RTC_ALRMBR_HT_0 0x00100000U
7359 #define RTC_ALRMBR_HT_1 0x00200000U
7360 #define RTC_ALRMBR_HU 0x000F0000U
7361 #define RTC_ALRMBR_HU_0 0x00010000U
7362 #define RTC_ALRMBR_HU_1 0x00020000U
7363 #define RTC_ALRMBR_HU_2 0x00040000U
7364 #define RTC_ALRMBR_HU_3 0x00080000U
7365 #define RTC_ALRMBR_MSK2 0x00008000U
7366 #define RTC_ALRMBR_MNT 0x00007000U
7367 #define RTC_ALRMBR_MNT_0 0x00001000U
7368 #define RTC_ALRMBR_MNT_1 0x00002000U
7369 #define RTC_ALRMBR_MNT_2 0x00004000U
7370 #define RTC_ALRMBR_MNU 0x00000F00U
7371 #define RTC_ALRMBR_MNU_0 0x00000100U
7372 #define RTC_ALRMBR_MNU_1 0x00000200U
7373 #define RTC_ALRMBR_MNU_2 0x00000400U
7374 #define RTC_ALRMBR_MNU_3 0x00000800U
7375 #define RTC_ALRMBR_MSK1 0x00000080U
7376 #define RTC_ALRMBR_ST 0x00000070U
7377 #define RTC_ALRMBR_ST_0 0x00000010U
7378 #define RTC_ALRMBR_ST_1 0x00000020U
7379 #define RTC_ALRMBR_ST_2 0x00000040U
7380 #define RTC_ALRMBR_SU 0x0000000FU
7381 #define RTC_ALRMBR_SU_0 0x00000001U
7382 #define RTC_ALRMBR_SU_1 0x00000002U
7383 #define RTC_ALRMBR_SU_2 0x00000004U
7384 #define RTC_ALRMBR_SU_3 0x00000008U
7385 
7386 /******************** Bits definition for RTC_WPR register ******************/
7387 #define RTC_WPR_KEY 0x000000FFU
7388 
7389 /******************** Bits definition for RTC_SSR register ******************/
7390 #define RTC_SSR_SS 0x0000FFFFU
7391 
7392 /******************** Bits definition for RTC_SHIFTR register ***************/
7393 #define RTC_SHIFTR_SUBFS 0x00007FFFU
7394 #define RTC_SHIFTR_ADD1S 0x80000000U
7395 
7396 /******************** Bits definition for RTC_TSTR register *****************/
7397 #define RTC_TSTR_PM 0x00400000U
7398 #define RTC_TSTR_HT 0x00300000U
7399 #define RTC_TSTR_HT_0 0x00100000U
7400 #define RTC_TSTR_HT_1 0x00200000U
7401 #define RTC_TSTR_HU 0x000F0000U
7402 #define RTC_TSTR_HU_0 0x00010000U
7403 #define RTC_TSTR_HU_1 0x00020000U
7404 #define RTC_TSTR_HU_2 0x00040000U
7405 #define RTC_TSTR_HU_3 0x00080000U
7406 #define RTC_TSTR_MNT 0x00007000U
7407 #define RTC_TSTR_MNT_0 0x00001000U
7408 #define RTC_TSTR_MNT_1 0x00002000U
7409 #define RTC_TSTR_MNT_2 0x00004000U
7410 #define RTC_TSTR_MNU 0x00000F00U
7411 #define RTC_TSTR_MNU_0 0x00000100U
7412 #define RTC_TSTR_MNU_1 0x00000200U
7413 #define RTC_TSTR_MNU_2 0x00000400U
7414 #define RTC_TSTR_MNU_3 0x00000800U
7415 #define RTC_TSTR_ST 0x00000070U
7416 #define RTC_TSTR_ST_0 0x00000010U
7417 #define RTC_TSTR_ST_1 0x00000020U
7418 #define RTC_TSTR_ST_2 0x00000040U
7419 #define RTC_TSTR_SU 0x0000000FU
7420 #define RTC_TSTR_SU_0 0x00000001U
7421 #define RTC_TSTR_SU_1 0x00000002U
7422 #define RTC_TSTR_SU_2 0x00000004U
7423 #define RTC_TSTR_SU_3 0x00000008U
7424 
7425 /******************** Bits definition for RTC_TSDR register *****************/
7426 #define RTC_TSDR_WDU 0x0000E000U
7427 #define RTC_TSDR_WDU_0 0x00002000U
7428 #define RTC_TSDR_WDU_1 0x00004000U
7429 #define RTC_TSDR_WDU_2 0x00008000U
7430 #define RTC_TSDR_MT 0x00001000U
7431 #define RTC_TSDR_MU 0x00000F00U
7432 #define RTC_TSDR_MU_0 0x00000100U
7433 #define RTC_TSDR_MU_1 0x00000200U
7434 #define RTC_TSDR_MU_2 0x00000400U
7435 #define RTC_TSDR_MU_3 0x00000800U
7436 #define RTC_TSDR_DT 0x00000030U
7437 #define RTC_TSDR_DT_0 0x00000010U
7438 #define RTC_TSDR_DT_1 0x00000020U
7439 #define RTC_TSDR_DU 0x0000000FU
7440 #define RTC_TSDR_DU_0 0x00000001U
7441 #define RTC_TSDR_DU_1 0x00000002U
7442 #define RTC_TSDR_DU_2 0x00000004U
7443 #define RTC_TSDR_DU_3 0x00000008U
7444 
7445 /******************** Bits definition for RTC_TSSSR register ****************/
7446 #define RTC_TSSSR_SS 0x0000FFFFU
7447 
7448 /******************** Bits definition for RTC_CAL register *****************/
7449 #define RTC_CALR_CALP 0x00008000U
7450 #define RTC_CALR_CALW8 0x00004000U
7451 #define RTC_CALR_CALW16 0x00002000U
7452 #define RTC_CALR_CALM 0x000001FFU
7453 #define RTC_CALR_CALM_0 0x00000001U
7454 #define RTC_CALR_CALM_1 0x00000002U
7455 #define RTC_CALR_CALM_2 0x00000004U
7456 #define RTC_CALR_CALM_3 0x00000008U
7457 #define RTC_CALR_CALM_4 0x00000010U
7458 #define RTC_CALR_CALM_5 0x00000020U
7459 #define RTC_CALR_CALM_6 0x00000040U
7460 #define RTC_CALR_CALM_7 0x00000080U
7461 #define RTC_CALR_CALM_8 0x00000100U
7462 
7463 /******************** Bits definition for RTC_TAFCR register ****************/
7464 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
7465 #define RTC_TAFCR_TSINSEL 0x00020000U
7466 #define RTC_TAFCR_TAMPINSEL 0x00010000U
7467 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
7468 #define RTC_TAFCR_TAMPPRCH 0x00006000U
7469 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
7470 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
7471 #define RTC_TAFCR_TAMPFLT 0x00001800U
7472 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
7473 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
7474 #define RTC_TAFCR_TAMPFREQ 0x00000700U
7475 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
7476 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
7477 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
7478 #define RTC_TAFCR_TAMPTS 0x00000080U
7479 #define RTC_TAFCR_TAMP2TRG 0x00000010U
7480 #define RTC_TAFCR_TAMP2E 0x00000008U
7481 #define RTC_TAFCR_TAMPIE 0x00000004U
7482 #define RTC_TAFCR_TAMP1TRG 0x00000002U
7483 #define RTC_TAFCR_TAMP1E 0x00000001U
7484 
7485 /******************** Bits definition for RTC_ALRMASSR register *************/
7486 #define RTC_ALRMASSR_MASKSS 0x0F000000U
7487 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
7488 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
7489 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
7490 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
7491 #define RTC_ALRMASSR_SS 0x00007FFFU
7492 
7493 /******************** Bits definition for RTC_ALRMBSSR register *************/
7494 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
7495 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
7496 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
7497 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
7498 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
7499 #define RTC_ALRMBSSR_SS 0x00007FFFU
7500 
7501 /******************** Bits definition for RTC_BKP0R register ****************/
7502 #define RTC_BKP0R 0xFFFFFFFFU
7503 
7504 /******************** Bits definition for RTC_BKP1R register ****************/
7505 #define RTC_BKP1R 0xFFFFFFFFU
7506 
7507 /******************** Bits definition for RTC_BKP2R register ****************/
7508 #define RTC_BKP2R 0xFFFFFFFFU
7509 
7510 /******************** Bits definition for RTC_BKP3R register ****************/
7511 #define RTC_BKP3R 0xFFFFFFFFU
7512 
7513 /******************** Bits definition for RTC_BKP4R register ****************/
7514 #define RTC_BKP4R 0xFFFFFFFFU
7515 
7516 /******************** Bits definition for RTC_BKP5R register ****************/
7517 #define RTC_BKP5R 0xFFFFFFFFU
7518 
7519 /******************** Bits definition for RTC_BKP6R register ****************/
7520 #define RTC_BKP6R 0xFFFFFFFFU
7521 
7522 /******************** Bits definition for RTC_BKP7R register ****************/
7523 #define RTC_BKP7R 0xFFFFFFFFU
7524 
7525 /******************** Bits definition for RTC_BKP8R register ****************/
7526 #define RTC_BKP8R 0xFFFFFFFFU
7527 
7528 /******************** Bits definition for RTC_BKP9R register ****************/
7529 #define RTC_BKP9R 0xFFFFFFFFU
7530 
7531 /******************** Bits definition for RTC_BKP10R register ***************/
7532 #define RTC_BKP10R 0xFFFFFFFFU
7533 
7534 /******************** Bits definition for RTC_BKP11R register ***************/
7535 #define RTC_BKP11R 0xFFFFFFFFU
7536 
7537 /******************** Bits definition for RTC_BKP12R register ***************/
7538 #define RTC_BKP12R 0xFFFFFFFFU
7539 
7540 /******************** Bits definition for RTC_BKP13R register ***************/
7541 #define RTC_BKP13R 0xFFFFFFFFU
7542 
7543 /******************** Bits definition for RTC_BKP14R register ***************/
7544 #define RTC_BKP14R 0xFFFFFFFFU
7545 
7546 /******************** Bits definition for RTC_BKP15R register ***************/
7547 #define RTC_BKP15R 0xFFFFFFFFU
7548 
7549 /******************** Bits definition for RTC_BKP16R register ***************/
7550 #define RTC_BKP16R 0xFFFFFFFFU
7551 
7552 /******************** Bits definition for RTC_BKP17R register ***************/
7553 #define RTC_BKP17R 0xFFFFFFFFU
7554 
7555 /******************** Bits definition for RTC_BKP18R register ***************/
7556 #define RTC_BKP18R 0xFFFFFFFFU
7557 
7558 /******************** Bits definition for RTC_BKP19R register ***************/
7559 #define RTC_BKP19R 0xFFFFFFFFU
7560 
7561 /******************************************************************************/
7562 /* */
7563 /* Serial Audio Interface */
7564 /* */
7565 /******************************************************************************/
7566 /******************** Bit definition for SAI_GCR register *******************/
7567 #define SAI_GCR_SYNCIN 0x00000003U
7568 #define SAI_GCR_SYNCIN_0 0x00000001U
7569 #define SAI_GCR_SYNCIN_1 0x00000002U
7571 #define SAI_GCR_SYNCOUT 0x00000030U
7572 #define SAI_GCR_SYNCOUT_0 0x00000010U
7573 #define SAI_GCR_SYNCOUT_1 0x00000020U
7575 /******************* Bit definition for SAI_xCR1 register *******************/
7576 #define SAI_xCR1_MODE 0x00000003U
7577 #define SAI_xCR1_MODE_0 0x00000001U
7578 #define SAI_xCR1_MODE_1 0x00000002U
7580 #define SAI_xCR1_PRTCFG 0x0000000CU
7581 #define SAI_xCR1_PRTCFG_0 0x00000004U
7582 #define SAI_xCR1_PRTCFG_1 0x00000008U
7584 #define SAI_xCR1_DS 0x000000E0U
7585 #define SAI_xCR1_DS_0 0x00000020U
7586 #define SAI_xCR1_DS_1 0x00000040U
7587 #define SAI_xCR1_DS_2 0x00000080U
7589 #define SAI_xCR1_LSBFIRST 0x00000100U
7590 #define SAI_xCR1_CKSTR 0x00000200U
7592 #define SAI_xCR1_SYNCEN 0x00000C00U
7593 #define SAI_xCR1_SYNCEN_0 0x00000400U
7594 #define SAI_xCR1_SYNCEN_1 0x00000800U
7596 #define SAI_xCR1_MONO 0x00001000U
7597 #define SAI_xCR1_OUTDRIV 0x00002000U
7598 #define SAI_xCR1_SAIEN 0x00010000U
7599 #define SAI_xCR1_DMAEN 0x00020000U
7600 #define SAI_xCR1_NODIV 0x00080000U
7602 #define SAI_xCR1_MCKDIV 0x00F00000U
7603 #define SAI_xCR1_MCKDIV_0 0x00100000U
7604 #define SAI_xCR1_MCKDIV_1 0x00200000U
7605 #define SAI_xCR1_MCKDIV_2 0x00400000U
7606 #define SAI_xCR1_MCKDIV_3 0x00800000U
7608 /******************* Bit definition for SAI_xCR2 register *******************/
7609 #define SAI_xCR2_FTH 0x00000007U
7610 #define SAI_xCR2_FTH_0 0x00000001U
7611 #define SAI_xCR2_FTH_1 0x00000002U
7612 #define SAI_xCR2_FTH_2 0x00000004U
7614 #define SAI_xCR2_FFLUSH 0x00000008U
7615 #define SAI_xCR2_TRIS 0x00000010U
7616 #define SAI_xCR2_MUTE 0x00000020U
7617 #define SAI_xCR2_MUTEVAL 0x00000040U
7619 #define SAI_xCR2_MUTECNT 0x00001F80U
7620 #define SAI_xCR2_MUTECNT_0 0x00000080U
7621 #define SAI_xCR2_MUTECNT_1 0x00000100U
7622 #define SAI_xCR2_MUTECNT_2 0x00000200U
7623 #define SAI_xCR2_MUTECNT_3 0x00000400U
7624 #define SAI_xCR2_MUTECNT_4 0x00000800U
7625 #define SAI_xCR2_MUTECNT_5 0x00001000U
7627 #define SAI_xCR2_CPL 0x00002000U
7629 #define SAI_xCR2_COMP 0x0000C000U
7630 #define SAI_xCR2_COMP_0 0x00004000U
7631 #define SAI_xCR2_COMP_1 0x00008000U
7633 /****************** Bit definition for SAI_xFRCR register *******************/
7634 #define SAI_xFRCR_FRL 0x000000FFU
7635 #define SAI_xFRCR_FRL_0 0x00000001U
7636 #define SAI_xFRCR_FRL_1 0x00000002U
7637 #define SAI_xFRCR_FRL_2 0x00000004U
7638 #define SAI_xFRCR_FRL_3 0x00000008U
7639 #define SAI_xFRCR_FRL_4 0x00000010U
7640 #define SAI_xFRCR_FRL_5 0x00000020U
7641 #define SAI_xFRCR_FRL_6 0x00000040U
7642 #define SAI_xFRCR_FRL_7 0x00000080U
7644 #define SAI_xFRCR_FSALL 0x00007F00U
7645 #define SAI_xFRCR_FSALL_0 0x00000100U
7646 #define SAI_xFRCR_FSALL_1 0x00000200U
7647 #define SAI_xFRCR_FSALL_2 0x00000400U
7648 #define SAI_xFRCR_FSALL_3 0x00000800U
7649 #define SAI_xFRCR_FSALL_4 0x00001000U
7650 #define SAI_xFRCR_FSALL_5 0x00002000U
7651 #define SAI_xFRCR_FSALL_6 0x00004000U
7653 #define SAI_xFRCR_FSDEF 0x00010000U
7654 #define SAI_xFRCR_FSPOL 0x00020000U
7655 #define SAI_xFRCR_FSOFF 0x00040000U
7656 /* Legacy defines */
7657 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
7658 
7659 /****************** Bit definition for SAI_xSLOTR register *******************/
7660 #define SAI_xSLOTR_FBOFF 0x0000001FU
7661 #define SAI_xSLOTR_FBOFF_0 0x00000001U
7662 #define SAI_xSLOTR_FBOFF_1 0x00000002U
7663 #define SAI_xSLOTR_FBOFF_2 0x00000004U
7664 #define SAI_xSLOTR_FBOFF_3 0x00000008U
7665 #define SAI_xSLOTR_FBOFF_4 0x00000010U
7667 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
7668 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
7669 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
7671 #define SAI_xSLOTR_NBSLOT 0x00000F00U
7672 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
7673 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
7674 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
7675 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
7677 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
7679 /******************* Bit definition for SAI_xIMR register *******************/
7680 #define SAI_xIMR_OVRUDRIE 0x00000001U
7681 #define SAI_xIMR_MUTEDETIE 0x00000002U
7682 #define SAI_xIMR_WCKCFGIE 0x00000004U
7683 #define SAI_xIMR_FREQIE 0x00000008U
7684 #define SAI_xIMR_CNRDYIE 0x00000010U
7685 #define SAI_xIMR_AFSDETIE 0x00000020U
7686 #define SAI_xIMR_LFSDETIE 0x00000040U
7688 /******************** Bit definition for SAI_xSR register *******************/
7689 #define SAI_xSR_OVRUDR 0x00000001U
7690 #define SAI_xSR_MUTEDET 0x00000002U
7691 #define SAI_xSR_WCKCFG 0x00000004U
7692 #define SAI_xSR_FREQ 0x00000008U
7693 #define SAI_xSR_CNRDY 0x00000010U
7694 #define SAI_xSR_AFSDET 0x00000020U
7695 #define SAI_xSR_LFSDET 0x00000040U
7697 #define SAI_xSR_FLVL 0x00070000U
7698 #define SAI_xSR_FLVL_0 0x00010000U
7699 #define SAI_xSR_FLVL_1 0x00020000U
7700 #define SAI_xSR_FLVL_2 0x00040000U
7702 /****************** Bit definition for SAI_xCLRFR register ******************/
7703 #define SAI_xCLRFR_COVRUDR 0x00000001U
7704 #define SAI_xCLRFR_CMUTEDET 0x00000002U
7705 #define SAI_xCLRFR_CWCKCFG 0x00000004U
7706 #define SAI_xCLRFR_CFREQ 0x00000008U
7707 #define SAI_xCLRFR_CCNRDY 0x00000010U
7708 #define SAI_xCLRFR_CAFSDET 0x00000020U
7709 #define SAI_xCLRFR_CLFSDET 0x00000040U
7711 /****************** Bit definition for SAI_xDR register ******************/
7712 #define SAI_xDR_DATA 0xFFFFFFFFU
7713 
7714 
7715 /******************************************************************************/
7716 /* */
7717 /* SD host Interface */
7718 /* */
7719 /******************************************************************************/
7720 /****************** Bit definition for SDIO_POWER register ******************/
7721 #define SDIO_POWER_PWRCTRL 0x03U
7722 #define SDIO_POWER_PWRCTRL_0 0x01U
7723 #define SDIO_POWER_PWRCTRL_1 0x02U
7725 /****************** Bit definition for SDIO_CLKCR register ******************/
7726 #define SDIO_CLKCR_CLKDIV 0x00FFU
7727 #define SDIO_CLKCR_CLKEN 0x0100U
7728 #define SDIO_CLKCR_PWRSAV 0x0200U
7729 #define SDIO_CLKCR_BYPASS 0x0400U
7731 #define SDIO_CLKCR_WIDBUS 0x1800U
7732 #define SDIO_CLKCR_WIDBUS_0 0x0800U
7733 #define SDIO_CLKCR_WIDBUS_1 0x1000U
7735 #define SDIO_CLKCR_NEGEDGE 0x2000U
7736 #define SDIO_CLKCR_HWFC_EN 0x4000U
7738 /******************* Bit definition for SDIO_ARG register *******************/
7739 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
7741 /******************* Bit definition for SDIO_CMD register *******************/
7742 #define SDIO_CMD_CMDINDEX 0x003FU
7744 #define SDIO_CMD_WAITRESP 0x00C0U
7745 #define SDIO_CMD_WAITRESP_0 0x0040U
7746 #define SDIO_CMD_WAITRESP_1 0x0080U
7748 #define SDIO_CMD_WAITINT 0x0100U
7749 #define SDIO_CMD_WAITPEND 0x0200U
7750 #define SDIO_CMD_CPSMEN 0x0400U
7751 #define SDIO_CMD_SDIOSUSPEND 0x0800U
7753 /***************** Bit definition for SDIO_RESPCMD register *****************/
7754 #define SDIO_RESPCMD_RESPCMD 0x3FU
7756 /****************** Bit definition for SDIO_RESP0 register ******************/
7757 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
7759 /****************** Bit definition for SDIO_RESP1 register ******************/
7760 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
7762 /****************** Bit definition for SDIO_RESP2 register ******************/
7763 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
7765 /****************** Bit definition for SDIO_RESP3 register ******************/
7766 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
7768 /****************** Bit definition for SDIO_RESP4 register ******************/
7769 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
7771 /****************** Bit definition for SDIO_DTIMER register *****************/
7772 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
7774 /****************** Bit definition for SDIO_DLEN register *******************/
7775 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
7777 /****************** Bit definition for SDIO_DCTRL register ******************/
7778 #define SDIO_DCTRL_DTEN 0x0001U
7779 #define SDIO_DCTRL_DTDIR 0x0002U
7780 #define SDIO_DCTRL_DTMODE 0x0004U
7781 #define SDIO_DCTRL_DMAEN 0x0008U
7783 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
7784 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
7785 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
7786 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
7787 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
7789 #define SDIO_DCTRL_RWSTART 0x0100U
7790 #define SDIO_DCTRL_RWSTOP 0x0200U
7791 #define SDIO_DCTRL_RWMOD 0x0400U
7792 #define SDIO_DCTRL_SDIOEN 0x0800U
7794 /****************** Bit definition for SDIO_DCOUNT register *****************/
7795 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
7797 /****************** Bit definition for SDIO_STA register ********************/
7798 #define SDIO_STA_CCRCFAIL 0x00000001U
7799 #define SDIO_STA_DCRCFAIL 0x00000002U
7800 #define SDIO_STA_CTIMEOUT 0x00000004U
7801 #define SDIO_STA_DTIMEOUT 0x00000008U
7802 #define SDIO_STA_TXUNDERR 0x00000010U
7803 #define SDIO_STA_RXOVERR 0x00000020U
7804 #define SDIO_STA_CMDREND 0x00000040U
7805 #define SDIO_STA_CMDSENT 0x00000080U
7806 #define SDIO_STA_DATAEND 0x00000100U
7807 #define SDIO_STA_DBCKEND 0x00000400U
7808 #define SDIO_STA_CMDACT 0x00000800U
7809 #define SDIO_STA_TXACT 0x00001000U
7810 #define SDIO_STA_RXACT 0x00002000U
7811 #define SDIO_STA_TXFIFOHE 0x00004000U
7812 #define SDIO_STA_RXFIFOHF 0x00008000U
7813 #define SDIO_STA_TXFIFOF 0x00010000U
7814 #define SDIO_STA_RXFIFOF 0x00020000U
7815 #define SDIO_STA_TXFIFOE 0x00040000U
7816 #define SDIO_STA_RXFIFOE 0x00080000U
7817 #define SDIO_STA_TXDAVL 0x00100000U
7818 #define SDIO_STA_RXDAVL 0x00200000U
7819 #define SDIO_STA_SDIOIT 0x00400000U
7821 /******************* Bit definition for SDIO_ICR register *******************/
7822 #define SDIO_ICR_CCRCFAILC 0x00000001U
7823 #define SDIO_ICR_DCRCFAILC 0x00000002U
7824 #define SDIO_ICR_CTIMEOUTC 0x00000004U
7825 #define SDIO_ICR_DTIMEOUTC 0x00000008U
7826 #define SDIO_ICR_TXUNDERRC 0x00000010U
7827 #define SDIO_ICR_RXOVERRC 0x00000020U
7828 #define SDIO_ICR_CMDRENDC 0x00000040U
7829 #define SDIO_ICR_CMDSENTC 0x00000080U
7830 #define SDIO_ICR_DATAENDC 0x00000100U
7831 #define SDIO_ICR_DBCKENDC 0x00000400U
7832 #define SDIO_ICR_SDIOITC 0x00400000U
7834 /****************** Bit definition for SDIO_MASK register *******************/
7835 #define SDIO_MASK_CCRCFAILIE 0x00000001U
7836 #define SDIO_MASK_DCRCFAILIE 0x00000002U
7837 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
7838 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
7839 #define SDIO_MASK_TXUNDERRIE 0x00000010U
7840 #define SDIO_MASK_RXOVERRIE 0x00000020U
7841 #define SDIO_MASK_CMDRENDIE 0x00000040U
7842 #define SDIO_MASK_CMDSENTIE 0x00000080U
7843 #define SDIO_MASK_DATAENDIE 0x00000100U
7844 #define SDIO_MASK_DBCKENDIE 0x00000400U
7845 #define SDIO_MASK_CMDACTIE 0x00000800U
7846 #define SDIO_MASK_TXACTIE 0x00001000U
7847 #define SDIO_MASK_RXACTIE 0x00002000U
7848 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
7849 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
7850 #define SDIO_MASK_TXFIFOFIE 0x00010000U
7851 #define SDIO_MASK_RXFIFOFIE 0x00020000U
7852 #define SDIO_MASK_TXFIFOEIE 0x00040000U
7853 #define SDIO_MASK_RXFIFOEIE 0x00080000U
7854 #define SDIO_MASK_TXDAVLIE 0x00100000U
7855 #define SDIO_MASK_RXDAVLIE 0x00200000U
7856 #define SDIO_MASK_SDIOITIE 0x00400000U
7858 /***************** Bit definition for SDIO_FIFOCNT register *****************/
7859 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
7861 /****************** Bit definition for SDIO_FIFO register *******************/
7862 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
7864 /******************************************************************************/
7865 /* */
7866 /* Serial Peripheral Interface */
7867 /* */
7868 /******************************************************************************/
7869 /******************* Bit definition for SPI_CR1 register ********************/
7870 #define SPI_CR1_CPHA 0x00000001U
7871 #define SPI_CR1_CPOL 0x00000002U
7872 #define SPI_CR1_MSTR 0x00000004U
7874 #define SPI_CR1_BR 0x00000038U
7875 #define SPI_CR1_BR_0 0x00000008U
7876 #define SPI_CR1_BR_1 0x00000010U
7877 #define SPI_CR1_BR_2 0x00000020U
7879 #define SPI_CR1_SPE 0x00000040U
7880 #define SPI_CR1_LSBFIRST 0x00000080U
7881 #define SPI_CR1_SSI 0x00000100U
7882 #define SPI_CR1_SSM 0x00000200U
7883 #define SPI_CR1_RXONLY 0x00000400U
7884 #define SPI_CR1_DFF 0x00000800U
7885 #define SPI_CR1_CRCNEXT 0x00001000U
7886 #define SPI_CR1_CRCEN 0x00002000U
7887 #define SPI_CR1_BIDIOE 0x00004000U
7888 #define SPI_CR1_BIDIMODE 0x00008000U
7890 /******************* Bit definition for SPI_CR2 register ********************/
7891 #define SPI_CR2_RXDMAEN 0x00000001U
7892 #define SPI_CR2_TXDMAEN 0x00000002U
7893 #define SPI_CR2_SSOE 0x00000004U
7894 #define SPI_CR2_FRF 0x00000010U
7895 #define SPI_CR2_ERRIE 0x00000020U
7896 #define SPI_CR2_RXNEIE 0x00000040U
7897 #define SPI_CR2_TXEIE 0x00000080U
7899 /******************** Bit definition for SPI_SR register ********************/
7900 #define SPI_SR_RXNE 0x00000001U
7901 #define SPI_SR_TXE 0x00000002U
7902 #define SPI_SR_CHSIDE 0x00000004U
7903 #define SPI_SR_UDR 0x00000008U
7904 #define SPI_SR_CRCERR 0x00000010U
7905 #define SPI_SR_MODF 0x00000020U
7906 #define SPI_SR_OVR 0x00000040U
7907 #define SPI_SR_BSY 0x00000080U
7908 #define SPI_SR_FRE 0x00000100U
7910 /******************** Bit definition for SPI_DR register ********************/
7911 #define SPI_DR_DR 0x0000FFFFU
7913 /******************* Bit definition for SPI_CRCPR register ******************/
7914 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
7916 /****************** Bit definition for SPI_RXCRCR register ******************/
7917 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
7919 /****************** Bit definition for SPI_TXCRCR register ******************/
7920 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
7922 /****************** Bit definition for SPI_I2SCFGR register *****************/
7923 #define SPI_I2SCFGR_CHLEN 0x00000001U
7925 #define SPI_I2SCFGR_DATLEN 0x00000006U
7926 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
7927 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
7929 #define SPI_I2SCFGR_CKPOL 0x00000008U
7931 #define SPI_I2SCFGR_I2SSTD 0x00000030U
7932 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
7933 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
7935 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
7937 #define SPI_I2SCFGR_I2SCFG 0x00000300U
7938 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
7939 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
7941 #define SPI_I2SCFGR_I2SE 0x00000400U
7942 #define SPI_I2SCFGR_I2SMOD 0x00000800U
7943 #define SPI_I2SCFGR_ASTRTEN 0x00001000U
7945 /****************** Bit definition for SPI_I2SPR register *******************/
7946 #define SPI_I2SPR_I2SDIV 0x000000FFU
7947 #define SPI_I2SPR_ODD 0x00000100U
7948 #define SPI_I2SPR_MCKOE 0x00000200U
7950 /******************************************************************************/
7951 /* */
7952 /* SYSCFG */
7953 /* */
7954 /******************************************************************************/
7955 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
7956 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
7957 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
7958 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
7959 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
7960 
7961 #define SYSCFG_MEMRMP_UFB_MODE 0x00000100U
7962 #define SYSCFG_SWP_FMC 0x00000C00U
7964 /****************** Bit definition for SYSCFG_PMC register ******************/
7965 #define SYSCFG_PMC_ADCxDC2 0x00070000U
7966 #define SYSCFG_PMC_ADC1DC2 0x00010000U
7967 #define SYSCFG_PMC_ADC2DC2 0x00020000U
7968 #define SYSCFG_PMC_ADC3DC2 0x00040000U
7970 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
7972 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
7973 #define SYSCFG_EXTICR1_EXTI0 0x000FU
7974 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
7975 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
7976 #define SYSCFG_EXTICR1_EXTI3 0xF000U
7980 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
7981 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
7982 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
7983 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
7984 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
7985 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
7986 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
7987 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
7988 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
7989 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
7990 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
7995 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
7996 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
7997 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
7998 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
7999 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
8000 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
8001 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
8002 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
8003 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
8004 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
8005 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
8011 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
8012 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
8013 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
8014 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
8015 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
8016 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
8017 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
8018 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
8019 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
8020 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
8021 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
8027 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
8028 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
8029 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
8030 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
8031 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
8032 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
8033 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
8034 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
8035 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
8036 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
8037 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
8040 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
8041 #define SYSCFG_EXTICR2_EXTI4 0x000FU
8042 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
8043 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
8044 #define SYSCFG_EXTICR2_EXTI7 0xF000U
8048 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
8049 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
8050 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
8051 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
8052 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
8053 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
8054 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
8055 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
8056 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
8057 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
8058 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
8063 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
8064 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
8065 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
8066 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
8067 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
8068 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
8069 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
8070 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
8071 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
8072 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
8073 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
8078 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
8079 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
8080 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
8081 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
8082 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
8083 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
8084 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
8085 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
8086 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
8087 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
8088 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
8094 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
8095 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
8096 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
8097 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
8098 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
8099 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
8100 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
8101 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
8102 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
8103 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
8104 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
8106 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
8107 #define SYSCFG_EXTICR3_EXTI8 0x000FU
8108 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
8109 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
8110 #define SYSCFG_EXTICR3_EXTI11 0xF000U
8115 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
8116 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
8117 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
8118 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
8119 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
8120 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
8121 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
8122 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
8123 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
8124 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
8129 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
8130 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
8131 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
8132 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
8133 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
8134 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
8135 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
8136 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
8137 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
8138 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
8144 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
8145 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
8146 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
8147 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
8148 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
8149 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
8150 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
8151 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
8152 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
8153 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
8159 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
8160 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
8161 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
8162 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
8163 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
8164 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
8165 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
8166 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
8167 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
8168 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
8171 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
8172 #define SYSCFG_EXTICR4_EXTI12 0x000FU
8173 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
8174 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
8175 #define SYSCFG_EXTICR4_EXTI15 0xF000U
8179 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
8180 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
8181 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
8182 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
8183 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
8184 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
8185 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
8186 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
8187 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
8188 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
8194 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
8195 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
8196 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
8197 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
8198 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
8199 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
8200 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
8201 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
8202 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
8203 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
8209 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
8210 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
8211 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
8212 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
8213 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
8214 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
8215 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
8216 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
8217 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
8218 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
8224 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
8225 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
8226 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
8227 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
8228 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
8229 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
8230 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
8231 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
8232 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
8233 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
8235 /****************** Bit definition for SYSCFG_CMPCR register ****************/
8236 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
8237 #define SYSCFG_CMPCR_READY 0x00000100U
8239 /******************************************************************************/
8240 /* */
8241 /* TIM */
8242 /* */
8243 /******************************************************************************/
8244 /******************* Bit definition for TIM_CR1 register ********************/
8245 #define TIM_CR1_CEN 0x0001U
8246 #define TIM_CR1_UDIS 0x0002U
8247 #define TIM_CR1_URS 0x0004U
8248 #define TIM_CR1_OPM 0x0008U
8249 #define TIM_CR1_DIR 0x0010U
8251 #define TIM_CR1_CMS 0x0060U
8252 #define TIM_CR1_CMS_0 0x0020U
8253 #define TIM_CR1_CMS_1 0x0040U
8255 #define TIM_CR1_ARPE 0x0080U
8257 #define TIM_CR1_CKD 0x0300U
8258 #define TIM_CR1_CKD_0 0x0100U
8259 #define TIM_CR1_CKD_1 0x0200U
8261 /******************* Bit definition for TIM_CR2 register ********************/
8262 #define TIM_CR2_CCPC 0x0001U
8263 #define TIM_CR2_CCUS 0x0004U
8264 #define TIM_CR2_CCDS 0x0008U
8266 #define TIM_CR2_MMS 0x0070U
8267 #define TIM_CR2_MMS_0 0x0010U
8268 #define TIM_CR2_MMS_1 0x0020U
8269 #define TIM_CR2_MMS_2 0x0040U
8271 #define TIM_CR2_TI1S 0x0080U
8272 #define TIM_CR2_OIS1 0x0100U
8273 #define TIM_CR2_OIS1N 0x0200U
8274 #define TIM_CR2_OIS2 0x0400U
8275 #define TIM_CR2_OIS2N 0x0800U
8276 #define TIM_CR2_OIS3 0x1000U
8277 #define TIM_CR2_OIS3N 0x2000U
8278 #define TIM_CR2_OIS4 0x4000U
8280 /******************* Bit definition for TIM_SMCR register *******************/
8281 #define TIM_SMCR_SMS 0x0007U
8282 #define TIM_SMCR_SMS_0 0x0001U
8283 #define TIM_SMCR_SMS_1 0x0002U
8284 #define TIM_SMCR_SMS_2 0x0004U
8286 #define TIM_SMCR_TS 0x0070U
8287 #define TIM_SMCR_TS_0 0x0010U
8288 #define TIM_SMCR_TS_1 0x0020U
8289 #define TIM_SMCR_TS_2 0x0040U
8291 #define TIM_SMCR_MSM 0x0080U
8293 #define TIM_SMCR_ETF 0x0F00U
8294 #define TIM_SMCR_ETF_0 0x0100U
8295 #define TIM_SMCR_ETF_1 0x0200U
8296 #define TIM_SMCR_ETF_2 0x0400U
8297 #define TIM_SMCR_ETF_3 0x0800U
8299 #define TIM_SMCR_ETPS 0x3000U
8300 #define TIM_SMCR_ETPS_0 0x1000U
8301 #define TIM_SMCR_ETPS_1 0x2000U
8303 #define TIM_SMCR_ECE 0x4000U
8304 #define TIM_SMCR_ETP 0x8000U
8306 /******************* Bit definition for TIM_DIER register *******************/
8307 #define TIM_DIER_UIE 0x0001U
8308 #define TIM_DIER_CC1IE 0x0002U
8309 #define TIM_DIER_CC2IE 0x0004U
8310 #define TIM_DIER_CC3IE 0x0008U
8311 #define TIM_DIER_CC4IE 0x0010U
8312 #define TIM_DIER_COMIE 0x0020U
8313 #define TIM_DIER_TIE 0x0040U
8314 #define TIM_DIER_BIE 0x0080U
8315 #define TIM_DIER_UDE 0x0100U
8316 #define TIM_DIER_CC1DE 0x0200U
8317 #define TIM_DIER_CC2DE 0x0400U
8318 #define TIM_DIER_CC3DE 0x0800U
8319 #define TIM_DIER_CC4DE 0x1000U
8320 #define TIM_DIER_COMDE 0x2000U
8321 #define TIM_DIER_TDE 0x4000U
8323 /******************** Bit definition for TIM_SR register ********************/
8324 #define TIM_SR_UIF 0x0001U
8325 #define TIM_SR_CC1IF 0x0002U
8326 #define TIM_SR_CC2IF 0x0004U
8327 #define TIM_SR_CC3IF 0x0008U
8328 #define TIM_SR_CC4IF 0x0010U
8329 #define TIM_SR_COMIF 0x0020U
8330 #define TIM_SR_TIF 0x0040U
8331 #define TIM_SR_BIF 0x0080U
8332 #define TIM_SR_CC1OF 0x0200U
8333 #define TIM_SR_CC2OF 0x0400U
8334 #define TIM_SR_CC3OF 0x0800U
8335 #define TIM_SR_CC4OF 0x1000U
8337 /******************* Bit definition for TIM_EGR register ********************/
8338 #define TIM_EGR_UG 0x01U
8339 #define TIM_EGR_CC1G 0x02U
8340 #define TIM_EGR_CC2G 0x04U
8341 #define TIM_EGR_CC3G 0x08U
8342 #define TIM_EGR_CC4G 0x10U
8343 #define TIM_EGR_COMG 0x20U
8344 #define TIM_EGR_TG 0x40U
8345 #define TIM_EGR_BG 0x80U
8347 /****************** Bit definition for TIM_CCMR1 register *******************/
8348 #define TIM_CCMR1_CC1S 0x0003U
8349 #define TIM_CCMR1_CC1S_0 0x0001U
8350 #define TIM_CCMR1_CC1S_1 0x0002U
8352 #define TIM_CCMR1_OC1FE 0x0004U
8353 #define TIM_CCMR1_OC1PE 0x0008U
8355 #define TIM_CCMR1_OC1M 0x0070U
8356 #define TIM_CCMR1_OC1M_0 0x0010U
8357 #define TIM_CCMR1_OC1M_1 0x0020U
8358 #define TIM_CCMR1_OC1M_2 0x0040U
8360 #define TIM_CCMR1_OC1CE 0x0080U
8362 #define TIM_CCMR1_CC2S 0x0300U
8363 #define TIM_CCMR1_CC2S_0 0x0100U
8364 #define TIM_CCMR1_CC2S_1 0x0200U
8366 #define TIM_CCMR1_OC2FE 0x0400U
8367 #define TIM_CCMR1_OC2PE 0x0800U
8369 #define TIM_CCMR1_OC2M 0x7000U
8370 #define TIM_CCMR1_OC2M_0 0x1000U
8371 #define TIM_CCMR1_OC2M_1 0x2000U
8372 #define TIM_CCMR1_OC2M_2 0x4000U
8374 #define TIM_CCMR1_OC2CE 0x8000U
8376 /*----------------------------------------------------------------------------*/
8377 
8378 #define TIM_CCMR1_IC1PSC 0x000CU
8379 #define TIM_CCMR1_IC1PSC_0 0x0004U
8380 #define TIM_CCMR1_IC1PSC_1 0x0008U
8382 #define TIM_CCMR1_IC1F 0x00F0U
8383 #define TIM_CCMR1_IC1F_0 0x0010U
8384 #define TIM_CCMR1_IC1F_1 0x0020U
8385 #define TIM_CCMR1_IC1F_2 0x0040U
8386 #define TIM_CCMR1_IC1F_3 0x0080U
8388 #define TIM_CCMR1_IC2PSC 0x0C00U
8389 #define TIM_CCMR1_IC2PSC_0 0x0400U
8390 #define TIM_CCMR1_IC2PSC_1 0x0800U
8392 #define TIM_CCMR1_IC2F 0xF000U
8393 #define TIM_CCMR1_IC2F_0 0x1000U
8394 #define TIM_CCMR1_IC2F_1 0x2000U
8395 #define TIM_CCMR1_IC2F_2 0x4000U
8396 #define TIM_CCMR1_IC2F_3 0x8000U
8398 /****************** Bit definition for TIM_CCMR2 register *******************/
8399 #define TIM_CCMR2_CC3S 0x0003U
8400 #define TIM_CCMR2_CC3S_0 0x0001U
8401 #define TIM_CCMR2_CC3S_1 0x0002U
8403 #define TIM_CCMR2_OC3FE 0x0004U
8404 #define TIM_CCMR2_OC3PE 0x0008U
8406 #define TIM_CCMR2_OC3M 0x0070U
8407 #define TIM_CCMR2_OC3M_0 0x0010U
8408 #define TIM_CCMR2_OC3M_1 0x0020U
8409 #define TIM_CCMR2_OC3M_2 0x0040U
8411 #define TIM_CCMR2_OC3CE 0x0080U
8413 #define TIM_CCMR2_CC4S 0x0300U
8414 #define TIM_CCMR2_CC4S_0 0x0100U
8415 #define TIM_CCMR2_CC4S_1 0x0200U
8417 #define TIM_CCMR2_OC4FE 0x0400U
8418 #define TIM_CCMR2_OC4PE 0x0800U
8420 #define TIM_CCMR2_OC4M 0x7000U
8421 #define TIM_CCMR2_OC4M_0 0x1000U
8422 #define TIM_CCMR2_OC4M_1 0x2000U
8423 #define TIM_CCMR2_OC4M_2 0x4000U
8425 #define TIM_CCMR2_OC4CE 0x8000U
8427 /*----------------------------------------------------------------------------*/
8428 
8429 #define TIM_CCMR2_IC3PSC 0x000CU
8430 #define TIM_CCMR2_IC3PSC_0 0x0004U
8431 #define TIM_CCMR2_IC3PSC_1 0x0008U
8433 #define TIM_CCMR2_IC3F 0x00F0U
8434 #define TIM_CCMR2_IC3F_0 0x0010U
8435 #define TIM_CCMR2_IC3F_1 0x0020U
8436 #define TIM_CCMR2_IC3F_2 0x0040U
8437 #define TIM_CCMR2_IC3F_3 0x0080U
8439 #define TIM_CCMR2_IC4PSC 0x0C00U
8440 #define TIM_CCMR2_IC4PSC_0 0x0400U
8441 #define TIM_CCMR2_IC4PSC_1 0x0800U
8443 #define TIM_CCMR2_IC4F 0xF000U
8444 #define TIM_CCMR2_IC4F_0 0x1000U
8445 #define TIM_CCMR2_IC4F_1 0x2000U
8446 #define TIM_CCMR2_IC4F_2 0x4000U
8447 #define TIM_CCMR2_IC4F_3 0x8000U
8449 /******************* Bit definition for TIM_CCER register *******************/
8450 #define TIM_CCER_CC1E 0x0001U
8451 #define TIM_CCER_CC1P 0x0002U
8452 #define TIM_CCER_CC1NE 0x0004U
8453 #define TIM_CCER_CC1NP 0x0008U
8454 #define TIM_CCER_CC2E 0x0010U
8455 #define TIM_CCER_CC2P 0x0020U
8456 #define TIM_CCER_CC2NE 0x0040U
8457 #define TIM_CCER_CC2NP 0x0080U
8458 #define TIM_CCER_CC3E 0x0100U
8459 #define TIM_CCER_CC3P 0x0200U
8460 #define TIM_CCER_CC3NE 0x0400U
8461 #define TIM_CCER_CC3NP 0x0800U
8462 #define TIM_CCER_CC4E 0x1000U
8463 #define TIM_CCER_CC4P 0x2000U
8464 #define TIM_CCER_CC4NP 0x8000U
8466 /******************* Bit definition for TIM_CNT register ********************/
8467 #define TIM_CNT_CNT 0xFFFFU
8469 /******************* Bit definition for TIM_PSC register ********************/
8470 #define TIM_PSC_PSC 0xFFFFU
8472 /******************* Bit definition for TIM_ARR register ********************/
8473 #define TIM_ARR_ARR 0xFFFFU
8475 /******************* Bit definition for TIM_RCR register ********************/
8476 #define TIM_RCR_REP 0xFFU
8478 /******************* Bit definition for TIM_CCR1 register *******************/
8479 #define TIM_CCR1_CCR1 0xFFFFU
8481 /******************* Bit definition for TIM_CCR2 register *******************/
8482 #define TIM_CCR2_CCR2 0xFFFFU
8484 /******************* Bit definition for TIM_CCR3 register *******************/
8485 #define TIM_CCR3_CCR3 0xFFFFU
8487 /******************* Bit definition for TIM_CCR4 register *******************/
8488 #define TIM_CCR4_CCR4 0xFFFFU
8490 /******************* Bit definition for TIM_BDTR register *******************/
8491 #define TIM_BDTR_DTG 0x00FFU
8492 #define TIM_BDTR_DTG_0 0x0001U
8493 #define TIM_BDTR_DTG_1 0x0002U
8494 #define TIM_BDTR_DTG_2 0x0004U
8495 #define TIM_BDTR_DTG_3 0x0008U
8496 #define TIM_BDTR_DTG_4 0x0010U
8497 #define TIM_BDTR_DTG_5 0x0020U
8498 #define TIM_BDTR_DTG_6 0x0040U
8499 #define TIM_BDTR_DTG_7 0x0080U
8501 #define TIM_BDTR_LOCK 0x0300U
8502 #define TIM_BDTR_LOCK_0 0x0100U
8503 #define TIM_BDTR_LOCK_1 0x0200U
8505 #define TIM_BDTR_OSSI 0x0400U
8506 #define TIM_BDTR_OSSR 0x0800U
8507 #define TIM_BDTR_BKE 0x1000U
8508 #define TIM_BDTR_BKP 0x2000U
8509 #define TIM_BDTR_AOE 0x4000U
8510 #define TIM_BDTR_MOE 0x8000U
8512 /******************* Bit definition for TIM_DCR register ********************/
8513 #define TIM_DCR_DBA 0x001FU
8514 #define TIM_DCR_DBA_0 0x0001U
8515 #define TIM_DCR_DBA_1 0x0002U
8516 #define TIM_DCR_DBA_2 0x0004U
8517 #define TIM_DCR_DBA_3 0x0008U
8518 #define TIM_DCR_DBA_4 0x0010U
8520 #define TIM_DCR_DBL 0x1F00U
8521 #define TIM_DCR_DBL_0 0x0100U
8522 #define TIM_DCR_DBL_1 0x0200U
8523 #define TIM_DCR_DBL_2 0x0400U
8524 #define TIM_DCR_DBL_3 0x0800U
8525 #define TIM_DCR_DBL_4 0x1000U
8527 /******************* Bit definition for TIM_DMAR register *******************/
8528 #define TIM_DMAR_DMAB 0xFFFFU
8530 /******************* Bit definition for TIM_OR register *********************/
8531 #define TIM_OR_TI4_RMP 0x00C0U
8532 #define TIM_OR_TI4_RMP_0 0x0040U
8533 #define TIM_OR_TI4_RMP_1 0x0080U
8534 #define TIM_OR_ITR1_RMP 0x0C00U
8535 #define TIM_OR_ITR1_RMP_0 0x0400U
8536 #define TIM_OR_ITR1_RMP_1 0x0800U
8539 /******************************************************************************/
8540 /* */
8541 /* Universal Synchronous Asynchronous Receiver Transmitter */
8542 /* */
8543 /******************************************************************************/
8544 /******************* Bit definition for USART_SR register *******************/
8545 #define USART_SR_PE 0x0001U
8546 #define USART_SR_FE 0x0002U
8547 #define USART_SR_NE 0x0004U
8548 #define USART_SR_ORE 0x0008U
8549 #define USART_SR_IDLE 0x0010U
8550 #define USART_SR_RXNE 0x0020U
8551 #define USART_SR_TC 0x0040U
8552 #define USART_SR_TXE 0x0080U
8553 #define USART_SR_LBD 0x0100U
8554 #define USART_SR_CTS 0x0200U
8556 /******************* Bit definition for USART_DR register *******************/
8557 #define USART_DR_DR 0x01FFU
8559 /****************** Bit definition for USART_BRR register *******************/
8560 #define USART_BRR_DIV_Fraction 0x000FU
8561 #define USART_BRR_DIV_Mantissa 0xFFF0U
8563 /****************** Bit definition for USART_CR1 register *******************/
8564 #define USART_CR1_SBK 0x0001U
8565 #define USART_CR1_RWU 0x0002U
8566 #define USART_CR1_RE 0x0004U
8567 #define USART_CR1_TE 0x0008U
8568 #define USART_CR1_IDLEIE 0x0010U
8569 #define USART_CR1_RXNEIE 0x0020U
8570 #define USART_CR1_TCIE 0x0040U
8571 #define USART_CR1_TXEIE 0x0080U
8572 #define USART_CR1_PEIE 0x0100U
8573 #define USART_CR1_PS 0x0200U
8574 #define USART_CR1_PCE 0x0400U
8575 #define USART_CR1_WAKE 0x0800U
8576 #define USART_CR1_M 0x1000U
8577 #define USART_CR1_UE 0x2000U
8578 #define USART_CR1_OVER8 0x8000U
8580 /****************** Bit definition for USART_CR2 register *******************/
8581 #define USART_CR2_ADD 0x000FU
8582 #define USART_CR2_LBDL 0x0020U
8583 #define USART_CR2_LBDIE 0x0040U
8584 #define USART_CR2_LBCL 0x0100U
8585 #define USART_CR2_CPHA 0x0200U
8586 #define USART_CR2_CPOL 0x0400U
8587 #define USART_CR2_CLKEN 0x0800U
8589 #define USART_CR2_STOP 0x3000U
8590 #define USART_CR2_STOP_0 0x1000U
8591 #define USART_CR2_STOP_1 0x2000U
8593 #define USART_CR2_LINEN 0x4000U
8595 /****************** Bit definition for USART_CR3 register *******************/
8596 #define USART_CR3_EIE 0x0001U
8597 #define USART_CR3_IREN 0x0002U
8598 #define USART_CR3_IRLP 0x0004U
8599 #define USART_CR3_HDSEL 0x0008U
8600 #define USART_CR3_NACK 0x0010U
8601 #define USART_CR3_SCEN 0x0020U
8602 #define USART_CR3_DMAR 0x0040U
8603 #define USART_CR3_DMAT 0x0080U
8604 #define USART_CR3_RTSE 0x0100U
8605 #define USART_CR3_CTSE 0x0200U
8606 #define USART_CR3_CTSIE 0x0400U
8607 #define USART_CR3_ONEBIT 0x0800U
8609 /****************** Bit definition for USART_GTPR register ******************/
8610 #define USART_GTPR_PSC 0x00FFU
8611 #define USART_GTPR_PSC_0 0x0001U
8612 #define USART_GTPR_PSC_1 0x0002U
8613 #define USART_GTPR_PSC_2 0x0004U
8614 #define USART_GTPR_PSC_3 0x0008U
8615 #define USART_GTPR_PSC_4 0x0010U
8616 #define USART_GTPR_PSC_5 0x0020U
8617 #define USART_GTPR_PSC_6 0x0040U
8618 #define USART_GTPR_PSC_7 0x0080U
8620 #define USART_GTPR_GT 0xFF00U
8622 /******************************************************************************/
8623 /* */
8624 /* Window WATCHDOG */
8625 /* */
8626 /******************************************************************************/
8627 /******************* Bit definition for WWDG_CR register ********************/
8628 #define WWDG_CR_T 0x7FU
8629 #define WWDG_CR_T_0 0x01U
8630 #define WWDG_CR_T_1 0x02U
8631 #define WWDG_CR_T_2 0x04U
8632 #define WWDG_CR_T_3 0x08U
8633 #define WWDG_CR_T_4 0x10U
8634 #define WWDG_CR_T_5 0x20U
8635 #define WWDG_CR_T_6 0x40U
8636 /* Legacy defines */
8637 #define WWDG_CR_T0 WWDG_CR_T_0
8638 #define WWDG_CR_T1 WWDG_CR_T_1
8639 #define WWDG_CR_T2 WWDG_CR_T_2
8640 #define WWDG_CR_T3 WWDG_CR_T_3
8641 #define WWDG_CR_T4 WWDG_CR_T_4
8642 #define WWDG_CR_T5 WWDG_CR_T_5
8643 #define WWDG_CR_T6 WWDG_CR_T_6
8644 
8645 #define WWDG_CR_WDGA 0x80U
8647 /******************* Bit definition for WWDG_CFR register *******************/
8648 #define WWDG_CFR_W 0x007FU
8649 #define WWDG_CFR_W_0 0x0001U
8650 #define WWDG_CFR_W_1 0x0002U
8651 #define WWDG_CFR_W_2 0x0004U
8652 #define WWDG_CFR_W_3 0x0008U
8653 #define WWDG_CFR_W_4 0x0010U
8654 #define WWDG_CFR_W_5 0x0020U
8655 #define WWDG_CFR_W_6 0x0040U
8656 /* Legacy defines */
8657 #define WWDG_CFR_W0 WWDG_CFR_W_0
8658 #define WWDG_CFR_W1 WWDG_CFR_W_1
8659 #define WWDG_CFR_W2 WWDG_CFR_W_2
8660 #define WWDG_CFR_W3 WWDG_CFR_W_3
8661 #define WWDG_CFR_W4 WWDG_CFR_W_4
8662 #define WWDG_CFR_W5 WWDG_CFR_W_5
8663 #define WWDG_CFR_W6 WWDG_CFR_W_6
8664 
8665 #define WWDG_CFR_WDGTB 0x0180U
8666 #define WWDG_CFR_WDGTB_0 0x0080U
8667 #define WWDG_CFR_WDGTB_1 0x0100U
8668 /* Legacy defines */
8669 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
8670 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
8671 
8672 #define WWDG_CFR_EWI 0x0200U
8674 /******************* Bit definition for WWDG_SR register ********************/
8675 #define WWDG_SR_EWIF 0x01U
8678 /******************************************************************************/
8679 /* */
8680 /* DBG */
8681 /* */
8682 /******************************************************************************/
8683 /******************** Bit definition for DBGMCU_IDCODE register *************/
8684 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
8685 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
8686 
8687 /******************** Bit definition for DBGMCU_CR register *****************/
8688 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
8689 #define DBGMCU_CR_DBG_STOP 0x00000002U
8690 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
8691 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
8692 
8693 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
8694 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
8695 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
8697 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
8698 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
8699 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
8700 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
8701 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
8702 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
8703 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
8704 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
8705 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
8706 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
8707 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
8708 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
8709 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
8710 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
8711 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
8712 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
8713 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
8714 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
8715 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
8716 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
8717 
8718 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
8719 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
8720 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
8721 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
8722 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
8723 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
8724 
8725 /******************************************************************************/
8726 /* */
8727 /* Ethernet MAC Registers bits definitions */
8728 /* */
8729 /******************************************************************************/
8730 /* Bit definition for Ethernet MAC Control Register register */
8731 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
8732 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
8733 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
8734 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
8735  #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
8736  #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
8737  #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
8738  #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
8739  #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
8740  #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
8741  #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
8742 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
8743 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
8744 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
8745 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
8746 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
8747 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
8748 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
8749 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
8750 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
8751  a transmission attempt during retries after a collision: 0 =< r <2^k */
8752  #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
8753  #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
8754  #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
8755  #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
8756 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
8757 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
8758 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
8759 
8760 /* Bit definition for Ethernet MAC Frame Filter Register */
8761 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
8762 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
8763 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
8764 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
8765 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
8766  #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
8767  #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
8768  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
8769 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
8770 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
8771 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
8772 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
8773 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
8774 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
8775 
8776 /* Bit definition for Ethernet MAC Hash Table High Register */
8777 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
8778 
8779 /* Bit definition for Ethernet MAC Hash Table Low Register */
8780 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
8781 
8782 /* Bit definition for Ethernet MAC MII Address Register */
8783 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
8784 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
8785 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
8786  #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
8787  #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
8788  #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
8789  #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
8790  #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
8791 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
8792 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
8793 
8794 /* Bit definition for Ethernet MAC MII Data Register */
8795 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
8796 
8797 /* Bit definition for Ethernet MAC Flow Control Register */
8798 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
8799 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
8800 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
8801  #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
8802  #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
8803  #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
8804  #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
8805 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
8806 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
8807 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
8808 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
8809 
8810 /* Bit definition for Ethernet MAC VLAN Tag Register */
8811 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
8812 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
8813 
8814 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
8815 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
8816 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
8817  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
8818 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
8819  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
8820  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
8821  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
8822  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
8823  RSVD - Filter1 Command - RSVD - Filter0 Command
8824  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
8825  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
8826  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
8827 
8828 /* Bit definition for Ethernet MAC PMT Control and Status Register */
8829 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
8830 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
8831 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
8832 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
8833 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
8834 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
8835 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
8836 
8837 /* Bit definition for Ethernet MAC Status Register */
8838 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
8839 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
8840 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
8841 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
8842 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
8843 
8844 /* Bit definition for Ethernet MAC Interrupt Mask Register */
8845 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
8846 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
8847 
8848 /* Bit definition for Ethernet MAC Address0 High Register */
8849 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
8850 
8851 /* Bit definition for Ethernet MAC Address0 Low Register */
8852 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
8853 
8854 /* Bit definition for Ethernet MAC Address1 High Register */
8855 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
8856 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
8857 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8858  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8859  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8860  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8861  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8862  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8863  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
8864 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
8865 
8866 /* Bit definition for Ethernet MAC Address1 Low Register */
8867 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
8868 
8869 /* Bit definition for Ethernet MAC Address2 High Register */
8870 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
8871 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
8872 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
8873  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8874  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8875  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8876  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8877  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8878  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8879 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
8880 
8881 /* Bit definition for Ethernet MAC Address2 Low Register */
8882 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
8883 
8884 /* Bit definition for Ethernet MAC Address3 High Register */
8885 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
8886 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
8887 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
8888  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
8889  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
8890  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
8891  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
8892  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
8893  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
8894 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
8895 
8896 /* Bit definition for Ethernet MAC Address3 Low Register */
8897 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
8898 
8899 /******************************************************************************/
8900 /* Ethernet MMC Registers bits definition */
8901 /******************************************************************************/
8902 
8903 /* Bit definition for Ethernet MMC Contol Register */
8904 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
8905 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
8906 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
8907 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
8908 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
8909 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
8910 
8911 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8912 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
8913 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
8914 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
8915 
8916 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8917 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
8918 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
8919 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
8920 
8921 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8922 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8923 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8924 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8925 
8926 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8927 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8928 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8929 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8930 
8931 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8932 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8933 
8934 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8935 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8936 
8937 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8938 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
8939 
8940 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8941 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
8942 
8943 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8944 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
8945 
8946 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8947 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
8948 
8949 /******************************************************************************/
8950 /* Ethernet PTP Registers bits definition */
8951 /******************************************************************************/
8952 
8953 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8954 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
8955 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
8956 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
8957 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
8958 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
8959 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
8960 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
8961 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
8962 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
8963 
8964 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
8965 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
8966 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
8967 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
8968 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
8969 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
8970 
8971 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8972 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
8973 
8974 /* Bit definition for Ethernet PTP Time Stamp High Register */
8975 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
8976 
8977 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8978 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
8979 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
8980 
8981 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8982 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
8983 
8984 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8985 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
8986 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
8987 
8988 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8989 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
8990 
8991 /* Bit definition for Ethernet PTP Target Time High Register */
8992 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
8993 
8994 /* Bit definition for Ethernet PTP Target Time Low Register */
8995 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
8996 
8997 /* Bit definition for Ethernet PTP Time Stamp Status Register */
8998 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
8999 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
9000 
9001 /******************************************************************************/
9002 /* Ethernet DMA Registers bits definition */
9003 /******************************************************************************/
9004 
9005 /* Bit definition for Ethernet DMA Bus Mode Register */
9006 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
9007 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
9008 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
9009 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
9010  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
9011  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
9012  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
9013  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
9014  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
9015  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
9016  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
9017  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
9018  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
9019  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
9020  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
9021  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
9022 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
9023 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
9024  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
9025  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
9026  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
9027  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
9028 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
9029  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
9030  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
9031  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
9032  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
9033  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
9034  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
9035  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
9036  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
9037  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
9038  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
9039  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
9040  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
9041 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
9042 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
9043 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
9044 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
9045 
9046 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
9047 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
9048 
9049 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
9050 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
9051 
9052 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
9053 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
9054 
9055 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
9056 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
9057 
9058 /* Bit definition for Ethernet DMA Status Register */
9059 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
9060 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
9061 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
9062 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
9063  /* combination with EBS[2:0] for GetFlagStatus function */
9064  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
9065  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
9066  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
9067 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
9068  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
9069  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
9070  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
9071  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
9072  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
9073  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
9074 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
9075  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
9076  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
9077  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
9078  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
9079  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
9080  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
9081 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
9082 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
9083 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
9084 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
9085 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
9086 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
9087 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
9088 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
9089 #define ETH_DMASR_RS 0x00000040U /* Receive status */
9090 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
9091 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
9092 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
9093 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
9094 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
9095 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
9096 
9097 /* Bit definition for Ethernet DMA Operation Mode Register */
9098 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
9099 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
9100 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
9101 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
9102 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
9103 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
9104  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
9105  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
9106  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
9107  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
9108  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
9109  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
9110  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
9111  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
9112 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
9113 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
9114 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
9115 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
9116  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
9117  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
9118  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
9119  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
9120 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
9121 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
9122 
9123 /* Bit definition for Ethernet DMA Interrupt Enable Register */
9124 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
9125 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
9126 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
9127 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
9128 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
9129 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
9130 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
9131 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
9132 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
9133 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
9134 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
9135 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
9136 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
9137 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
9138 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
9139 
9140 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
9141 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
9142 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
9143 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
9144 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
9145 
9146 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
9147 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
9148 
9149 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
9150 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
9151 
9152 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
9153 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
9154 
9155 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
9156 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
9157 
9158 /******************************************************************************/
9159 /* */
9160 /* USB_OTG */
9161 /* */
9162 /******************************************************************************/
9163 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
9164 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
9165 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
9166 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
9167 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
9168 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
9169 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
9170 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
9171 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
9172 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
9173 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
9174 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
9175 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
9176 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
9177 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
9178 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
9179 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
9180 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
9181 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
9183 /******************** Bit definition forUSB_OTG_HCFG register ********************/
9184 
9185 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
9186 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
9187 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
9188 #define USB_OTG_HCFG_FSLSS 0x00000004U
9190 /******************** Bit definition forUSB_OTG_DCFG register ********************/
9191 
9192 #define USB_OTG_DCFG_DSPD 0x00000003U
9193 #define USB_OTG_DCFG_DSPD_0 0x00000001U
9194 #define USB_OTG_DCFG_DSPD_1 0x00000002U
9195 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
9197 #define USB_OTG_DCFG_DAD 0x000007F0U
9198 #define USB_OTG_DCFG_DAD_0 0x00000010U
9199 #define USB_OTG_DCFG_DAD_1 0x00000020U
9200 #define USB_OTG_DCFG_DAD_2 0x00000040U
9201 #define USB_OTG_DCFG_DAD_3 0x00000080U
9202 #define USB_OTG_DCFG_DAD_4 0x00000100U
9203 #define USB_OTG_DCFG_DAD_5 0x00000200U
9204 #define USB_OTG_DCFG_DAD_6 0x00000400U
9206 #define USB_OTG_DCFG_PFIVL 0x00001800U
9207 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
9208 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
9210 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
9211 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
9212 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
9214 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
9215 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
9216 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
9217 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
9219 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
9220 #define USB_OTG_GOTGINT_SEDET 0x00000004U
9221 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
9222 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
9223 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
9224 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
9225 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
9226 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
9228 /******************** Bit definition forUSB_OTG_DCTL register ********************/
9229 #define USB_OTG_DCTL_RWUSIG 0x00000001U
9230 #define USB_OTG_DCTL_SDIS 0x00000002U
9231 #define USB_OTG_DCTL_GINSTS 0x00000004U
9232 #define USB_OTG_DCTL_GONSTS 0x00000008U
9234 #define USB_OTG_DCTL_TCTL 0x00000070U
9235 #define USB_OTG_DCTL_TCTL_0 0x00000010U
9236 #define USB_OTG_DCTL_TCTL_1 0x00000020U
9237 #define USB_OTG_DCTL_TCTL_2 0x00000040U
9238 #define USB_OTG_DCTL_SGINAK 0x00000080U
9239 #define USB_OTG_DCTL_CGINAK 0x00000100U
9240 #define USB_OTG_DCTL_SGONAK 0x00000200U
9241 #define USB_OTG_DCTL_CGONAK 0x00000400U
9242 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
9244 /******************** Bit definition forUSB_OTG_HFIR register ********************/
9245 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
9247 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
9248 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
9249 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
9251 /******************** Bit definition forUSB_OTG_DSTS register ********************/
9252 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
9254 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
9255 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
9256 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
9257 #define USB_OTG_DSTS_EERR 0x00000008U
9258 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
9260 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
9261 #define USB_OTG_GAHBCFG_GINT 0x00000001U
9262 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
9263 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
9264 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
9265 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
9266 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
9267 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
9268 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
9269 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
9271 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
9272 
9273 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
9274 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
9275 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
9276 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
9277 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
9278 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
9279 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
9280 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
9281 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
9282 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
9283 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
9284 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
9285 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
9286 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
9287 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
9288 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
9289 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
9290 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
9291 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
9292 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
9293 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
9294 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
9295 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
9296 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
9297 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
9299 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
9300 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
9301 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
9302 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
9303 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
9304 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
9305 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
9306 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
9307 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
9308 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
9309 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
9310 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
9311 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
9312 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
9314 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
9315 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
9316 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
9317 #define USB_OTG_DIEPMSK_TOM 0x00000008U
9318 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
9319 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
9320 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
9321 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
9322 #define USB_OTG_DIEPMSK_BIM 0x00000200U
9324 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
9325 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
9326 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
9327 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
9328 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
9329 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
9330 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
9331 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
9332 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
9333 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
9334 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
9336 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
9337 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
9338 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
9339 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
9340 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
9341 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
9342 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
9343 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
9344 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
9346 /******************** Bit definition forUSB_OTG_HAINT register ********************/
9347 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
9349 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
9350 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
9351 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
9352 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
9353 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
9354 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
9355 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
9356 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
9357 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
9359 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
9360 #define USB_OTG_GINTSTS_CMOD 0x00000001U
9361 #define USB_OTG_GINTSTS_MMIS 0x00000002U
9362 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
9363 #define USB_OTG_GINTSTS_SOF 0x00000008U
9364 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
9365 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
9366 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
9367 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
9368 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
9369 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
9370 #define USB_OTG_GINTSTS_USBRST 0x00001000U
9371 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
9372 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
9373 #define USB_OTG_GINTSTS_EOPF 0x00008000U
9374 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
9375 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
9376 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
9377 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
9378 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
9379 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
9380 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
9381 #define USB_OTG_GINTSTS_HCINT 0x02000000U
9382 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
9383 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
9384 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
9385 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
9386 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
9387 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
9389 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
9390 #define USB_OTG_GINTMSK_MMISM 0x00000002U
9391 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
9392 #define USB_OTG_GINTMSK_SOFM 0x00000008U
9393 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
9394 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
9395 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
9396 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
9397 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
9398 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
9399 #define USB_OTG_GINTMSK_USBRST 0x00001000U
9400 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
9401 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
9402 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
9403 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
9404 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
9405 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
9406 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
9407 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
9408 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
9409 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U
9410 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
9411 #define USB_OTG_GINTMSK_HCIM 0x02000000U
9412 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
9413 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
9414 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
9415 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
9416 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
9417 #define USB_OTG_GINTMSK_WUIM 0x80000000U
9419 /******************** Bit definition forUSB_OTG_DAINT register ********************/
9420 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
9421 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
9423 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
9424 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
9426 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
9427 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
9428 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
9429 #define USB_OTG_GRXSTSP_DPID 0x00018000U
9430 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
9432 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
9433 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
9434 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
9436 /******************** Bit definition for OTG register ********************/
9437 
9438 #define USB_OTG_CHNUM 0x0000000FU
9439 #define USB_OTG_CHNUM_0 0x00000001U
9440 #define USB_OTG_CHNUM_1 0x00000002U
9441 #define USB_OTG_CHNUM_2 0x00000004U
9442 #define USB_OTG_CHNUM_3 0x00000008U
9443 #define USB_OTG_BCNT 0x00007FF0U
9445 #define USB_OTG_DPID 0x00018000U
9446 #define USB_OTG_DPID_0 0x00008000U
9447 #define USB_OTG_DPID_1 0x00010000U
9449 #define USB_OTG_PKTSTS 0x001E0000U
9450 #define USB_OTG_PKTSTS_0 0x00020000U
9451 #define USB_OTG_PKTSTS_1 0x00040000U
9452 #define USB_OTG_PKTSTS_2 0x00080000U
9453 #define USB_OTG_PKTSTS_3 0x00100000U
9455 #define USB_OTG_EPNUM 0x0000000FU
9456 #define USB_OTG_EPNUM_0 0x00000001U
9457 #define USB_OTG_EPNUM_1 0x00000002U
9458 #define USB_OTG_EPNUM_2 0x00000004U
9459 #define USB_OTG_EPNUM_3 0x00000008U
9461 #define USB_OTG_FRMNUM 0x01E00000U
9462 #define USB_OTG_FRMNUM_0 0x00200000U
9463 #define USB_OTG_FRMNUM_1 0x00400000U
9464 #define USB_OTG_FRMNUM_2 0x00800000U
9465 #define USB_OTG_FRMNUM_3 0x01000000U
9467 /******************** Bit definition for OTG register ********************/
9468 
9469 #define USB_OTG_CHNUM 0x0000000FU
9470 #define USB_OTG_CHNUM_0 0x00000001U
9471 #define USB_OTG_CHNUM_1 0x00000002U
9472 #define USB_OTG_CHNUM_2 0x00000004U
9473 #define USB_OTG_CHNUM_3 0x00000008U
9474 #define USB_OTG_BCNT 0x00007FF0U
9476 #define USB_OTG_DPID 0x00018000U
9477 #define USB_OTG_DPID_0 0x00008000U
9478 #define USB_OTG_DPID_1 0x00010000U
9480 #define USB_OTG_PKTSTS 0x001E0000U
9481 #define USB_OTG_PKTSTS_0 0x00020000U
9482 #define USB_OTG_PKTSTS_1 0x00040000U
9483 #define USB_OTG_PKTSTS_2 0x00080000U
9484 #define USB_OTG_PKTSTS_3 0x00100000U
9486 #define USB_OTG_EPNUM 0x0000000FU
9487 #define USB_OTG_EPNUM_0 0x00000001U
9488 #define USB_OTG_EPNUM_1 0x00000002U
9489 #define USB_OTG_EPNUM_2 0x00000004U
9490 #define USB_OTG_EPNUM_3 0x00000008U
9492 #define USB_OTG_FRMNUM 0x01E00000U
9493 #define USB_OTG_FRMNUM_0 0x00200000U
9494 #define USB_OTG_FRMNUM_1 0x00400000U
9495 #define USB_OTG_FRMNUM_2 0x00800000U
9496 #define USB_OTG_FRMNUM_3 0x01000000U
9498 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
9499 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
9501 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
9502 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
9504 /******************** Bit definition for OTG register ********************/
9505 #define USB_OTG_NPTXFSA 0x0000FFFFU
9506 #define USB_OTG_NPTXFD 0xFFFF0000U
9507 #define USB_OTG_TX0FSA 0x0000FFFFU
9508 #define USB_OTG_TX0FD 0xFFFF0000U
9510 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
9511 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
9513 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
9514 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
9516 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
9517 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
9518 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
9519 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
9520 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
9521 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
9522 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
9523 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
9524 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
9526 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
9527 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
9528 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
9529 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
9530 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
9531 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
9532 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
9533 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
9535 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
9536 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
9537 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
9539 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
9540 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
9541 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
9542 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
9543 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
9544 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
9545 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
9546 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
9547 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
9548 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
9549 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
9551 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
9552 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
9553 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
9554 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
9555 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
9556 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
9557 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
9558 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
9559 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
9560 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
9561 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
9563 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
9564 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
9566 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
9567 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
9568 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
9570 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
9571 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
9572 #define USB_OTG_GCCFG_VBDEN 0x00200000U
9574 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
9575 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
9576 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
9578 /******************** Bit definition forUSB_OTG_CID register ********************/
9579 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
9581 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
9582 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
9583 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
9584 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
9585 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
9586 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
9587 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
9588 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
9589 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
9590 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
9591 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
9592 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
9593 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
9594 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
9595 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
9596 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
9598 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
9599 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
9600 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
9601 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
9602 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
9603 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
9604 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
9605 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
9606 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
9607 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
9609 /******************** Bit definition forUSB_OTG_HPRT register ********************/
9610 #define USB_OTG_HPRT_PCSTS 0x00000001U
9611 #define USB_OTG_HPRT_PCDET 0x00000002U
9612 #define USB_OTG_HPRT_PENA 0x00000004U
9613 #define USB_OTG_HPRT_PENCHNG 0x00000008U
9614 #define USB_OTG_HPRT_POCA 0x00000010U
9615 #define USB_OTG_HPRT_POCCHNG 0x00000020U
9616 #define USB_OTG_HPRT_PRES 0x00000040U
9617 #define USB_OTG_HPRT_PSUSP 0x00000080U
9618 #define USB_OTG_HPRT_PRST 0x00000100U
9620 #define USB_OTG_HPRT_PLSTS 0x00000C00U
9621 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
9622 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
9623 #define USB_OTG_HPRT_PPWR 0x00001000U
9625 #define USB_OTG_HPRT_PTCTL 0x0001E000U
9626 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
9627 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
9628 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
9629 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
9631 #define USB_OTG_HPRT_PSPD 0x00060000U
9632 #define USB_OTG_HPRT_PSPD_0 0x00020000U
9633 #define USB_OTG_HPRT_PSPD_1 0x00040000U
9635 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
9636 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
9637 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
9638 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
9639 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
9640 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
9641 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
9642 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
9643 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
9644 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
9645 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
9646 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
9648 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
9649 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
9650 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
9652 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
9653 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
9654 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
9655 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
9656 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
9658 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
9659 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
9660 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
9661 #define USB_OTG_DIEPCTL_STALL 0x00200000U
9663 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
9664 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
9665 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
9666 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
9667 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
9668 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
9669 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
9670 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
9671 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
9672 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
9673 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
9675 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
9676 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
9678 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
9679 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
9680 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
9681 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
9682 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
9683 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
9684 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
9686 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
9687 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
9688 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
9690 #define USB_OTG_HCCHAR_MC 0x00300000U
9691 #define USB_OTG_HCCHAR_MC_0 0x00100000U
9692 #define USB_OTG_HCCHAR_MC_1 0x00200000U
9694 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
9695 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
9696 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
9697 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
9698 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
9699 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
9700 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
9701 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
9702 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
9703 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
9704 #define USB_OTG_HCCHAR_CHENA 0x80000000U
9706 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
9707 
9708 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
9709 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
9710 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
9711 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
9712 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
9713 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
9714 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
9715 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
9717 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
9718 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
9719 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
9720 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
9721 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
9722 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
9723 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
9724 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
9726 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
9727 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
9728 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
9729 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
9730 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
9732 /******************** Bit definition forUSB_OTG_HCINT register ********************/
9733 #define USB_OTG_HCINT_XFRC 0x00000001U
9734 #define USB_OTG_HCINT_CHH 0x00000002U
9735 #define USB_OTG_HCINT_AHBERR 0x00000004U
9736 #define USB_OTG_HCINT_STALL 0x00000008U
9737 #define USB_OTG_HCINT_NAK 0x00000010U
9738 #define USB_OTG_HCINT_ACK 0x00000020U
9739 #define USB_OTG_HCINT_NYET 0x00000040U
9740 #define USB_OTG_HCINT_TXERR 0x00000080U
9741 #define USB_OTG_HCINT_BBERR 0x00000100U
9742 #define USB_OTG_HCINT_FRMOR 0x00000200U
9743 #define USB_OTG_HCINT_DTERR 0x00000400U
9745 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
9746 #define USB_OTG_DIEPINT_XFRC 0x00000001U
9747 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
9748 #define USB_OTG_DIEPINT_TOC 0x00000008U
9749 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
9750 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
9751 #define USB_OTG_DIEPINT_TXFE 0x00000080U
9752 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
9753 #define USB_OTG_DIEPINT_BNA 0x00000200U
9754 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
9755 #define USB_OTG_DIEPINT_BERR 0x00001000U
9756 #define USB_OTG_DIEPINT_NAK 0x00002000U
9758 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
9759 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
9760 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
9761 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
9762 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
9763 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
9764 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
9765 #define USB_OTG_HCINTMSK_NYET 0x00000040U
9766 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
9767 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
9768 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
9769 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
9771 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
9772 
9773 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
9774 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
9775 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
9776 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
9777 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
9778 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
9779 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
9780 #define USB_OTG_HCTSIZ_DPID 0x60000000U
9781 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
9782 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
9784 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
9785 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
9787 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
9788 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
9790 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
9791 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
9793 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
9794 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
9795 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
9797 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
9798 
9799 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
9800 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
9801 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
9802 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
9803 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
9804 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
9805 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
9806 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
9807 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
9808 #define USB_OTG_DOEPCTL_STALL 0x00200000U
9809 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
9810 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
9811 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
9812 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
9814 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
9815 #define USB_OTG_DOEPINT_XFRC 0x00000001U
9816 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
9817 #define USB_OTG_DOEPINT_STUP 0x00000008U
9818 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
9819 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
9820 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
9821 #define USB_OTG_DOEPINT_NYET 0x00004000U
9823 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
9824 
9825 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
9826 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
9828 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
9829 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
9830 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
9832 /******************** Bit definition for PCGCCTL register ********************/
9833 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
9834 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
9835 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
9850 /******************************* ADC Instances ********************************/
9851 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
9852  ((INSTANCE) == ADC2) || \
9853  ((INSTANCE) == ADC3))
9854 
9855 /******************************* CAN Instances ********************************/
9856 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
9857  ((INSTANCE) == CAN2))
9858 
9859 /******************************* CRC Instances ********************************/
9860 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
9861 
9862 /******************************* DAC Instances ********************************/
9863 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
9864 
9865 /******************************* DCMI Instances *******************************/
9866 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
9867 
9868 /******************************* DMA2D Instances *******************************/
9869 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
9870 
9871 /******************************** DMA Instances *******************************/
9872 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
9873  ((INSTANCE) == DMA1_Stream1) || \
9874  ((INSTANCE) == DMA1_Stream2) || \
9875  ((INSTANCE) == DMA1_Stream3) || \
9876  ((INSTANCE) == DMA1_Stream4) || \
9877  ((INSTANCE) == DMA1_Stream5) || \
9878  ((INSTANCE) == DMA1_Stream6) || \
9879  ((INSTANCE) == DMA1_Stream7) || \
9880  ((INSTANCE) == DMA2_Stream0) || \
9881  ((INSTANCE) == DMA2_Stream1) || \
9882  ((INSTANCE) == DMA2_Stream2) || \
9883  ((INSTANCE) == DMA2_Stream3) || \
9884  ((INSTANCE) == DMA2_Stream4) || \
9885  ((INSTANCE) == DMA2_Stream5) || \
9886  ((INSTANCE) == DMA2_Stream6) || \
9887  ((INSTANCE) == DMA2_Stream7))
9888 
9889 /******************************* GPIO Instances *******************************/
9890 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9891  ((INSTANCE) == GPIOB) || \
9892  ((INSTANCE) == GPIOC) || \
9893  ((INSTANCE) == GPIOD) || \
9894  ((INSTANCE) == GPIOE) || \
9895  ((INSTANCE) == GPIOF) || \
9896  ((INSTANCE) == GPIOG) || \
9897  ((INSTANCE) == GPIOH) || \
9898  ((INSTANCE) == GPIOI) || \
9899  ((INSTANCE) == GPIOJ) || \
9900  ((INSTANCE) == GPIOK))
9901 
9902 /******************************** I2C Instances *******************************/
9903 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
9904  ((INSTANCE) == I2C2) || \
9905  ((INSTANCE) == I2C3))
9906 
9907 /******************************** I2S Instances *******************************/
9908 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
9909  ((INSTANCE) == SPI3))
9910 
9911 /*************************** I2S Extended Instances ***************************/
9912 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
9913  ((INSTANCE) == SPI3) || \
9914  ((INSTANCE) == I2S2ext) || \
9915  ((INSTANCE) == I2S3ext))
9916 
9917 /****************************** LTDC Instances ********************************/
9918 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
9919 
9920 /******************************* RNG Instances ********************************/
9921 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
9922 
9923 /****************************** RTC Instances *********************************/
9924 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
9925 
9926 /******************************* SAI Instances ********************************/
9927 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
9928  ((PERIPH) == SAI1_Block_B))
9929 /* Legacy define */
9930 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
9931 
9932 /******************************** SPI Instances *******************************/
9933 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
9934  ((INSTANCE) == SPI2) || \
9935  ((INSTANCE) == SPI3) || \
9936  ((INSTANCE) == SPI4) || \
9937  ((INSTANCE) == SPI5) || \
9938  ((INSTANCE) == SPI6))
9939 
9940 /*************************** SPI Extended Instances ***************************/
9941 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
9942  ((INSTANCE) == SPI2) || \
9943  ((INSTANCE) == SPI3) || \
9944  ((INSTANCE) == SPI4) || \
9945  ((INSTANCE) == SPI5) || \
9946  ((INSTANCE) == SPI6) || \
9947  ((INSTANCE) == I2S2ext) || \
9948  ((INSTANCE) == I2S3ext))
9949 
9950 /****************** TIM Instances : All supported instances *******************/
9951 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9952  ((INSTANCE) == TIM2) || \
9953  ((INSTANCE) == TIM3) || \
9954  ((INSTANCE) == TIM4) || \
9955  ((INSTANCE) == TIM5) || \
9956  ((INSTANCE) == TIM6) || \
9957  ((INSTANCE) == TIM7) || \
9958  ((INSTANCE) == TIM8) || \
9959  ((INSTANCE) == TIM9) || \
9960  ((INSTANCE) == TIM10) || \
9961  ((INSTANCE) == TIM11) || \
9962  ((INSTANCE) == TIM12) || \
9963  ((INSTANCE) == TIM13) || \
9964  ((INSTANCE) == TIM14))
9965 
9966 /************* TIM Instances : at least 1 capture/compare channel *************/
9967 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9968  ((INSTANCE) == TIM2) || \
9969  ((INSTANCE) == TIM3) || \
9970  ((INSTANCE) == TIM4) || \
9971  ((INSTANCE) == TIM5) || \
9972  ((INSTANCE) == TIM8) || \
9973  ((INSTANCE) == TIM9) || \
9974  ((INSTANCE) == TIM10) || \
9975  ((INSTANCE) == TIM11) || \
9976  ((INSTANCE) == TIM12) || \
9977  ((INSTANCE) == TIM13) || \
9978  ((INSTANCE) == TIM14))
9979 
9980 /************ TIM Instances : at least 2 capture/compare channels *************/
9981 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9982  ((INSTANCE) == TIM2) || \
9983  ((INSTANCE) == TIM3) || \
9984  ((INSTANCE) == TIM4) || \
9985  ((INSTANCE) == TIM5) || \
9986  ((INSTANCE) == TIM8) || \
9987  ((INSTANCE) == TIM9) || \
9988  ((INSTANCE) == TIM12))
9989 
9990 /************ TIM Instances : at least 3 capture/compare channels *************/
9991 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9992  ((INSTANCE) == TIM2) || \
9993  ((INSTANCE) == TIM3) || \
9994  ((INSTANCE) == TIM4) || \
9995  ((INSTANCE) == TIM5) || \
9996  ((INSTANCE) == TIM8))
9997 
9998 /************ TIM Instances : at least 4 capture/compare channels *************/
9999 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10000  ((INSTANCE) == TIM2) || \
10001  ((INSTANCE) == TIM3) || \
10002  ((INSTANCE) == TIM4) || \
10003  ((INSTANCE) == TIM5) || \
10004  ((INSTANCE) == TIM8))
10005 
10006 /******************** TIM Instances : Advanced-control timers *****************/
10007 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10008  ((INSTANCE) == TIM8))
10009 
10010 /******************* TIM Instances : Timer input XOR function *****************/
10011 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10012  ((INSTANCE) == TIM2) || \
10013  ((INSTANCE) == TIM3) || \
10014  ((INSTANCE) == TIM4) || \
10015  ((INSTANCE) == TIM5) || \
10016  ((INSTANCE) == TIM8))
10017 
10018 /****************** TIM Instances : DMA requests generation (UDE) *************/
10019 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10020  ((INSTANCE) == TIM2) || \
10021  ((INSTANCE) == TIM3) || \
10022  ((INSTANCE) == TIM4) || \
10023  ((INSTANCE) == TIM5) || \
10024  ((INSTANCE) == TIM6) || \
10025  ((INSTANCE) == TIM7) || \
10026  ((INSTANCE) == TIM8))
10027 
10028 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
10029 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10030  ((INSTANCE) == TIM2) || \
10031  ((INSTANCE) == TIM3) || \
10032  ((INSTANCE) == TIM4) || \
10033  ((INSTANCE) == TIM5) || \
10034  ((INSTANCE) == TIM8))
10035 
10036 /************ TIM Instances : DMA requests generation (COMDE) *****************/
10037 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10038  ((INSTANCE) == TIM2) || \
10039  ((INSTANCE) == TIM3) || \
10040  ((INSTANCE) == TIM4) || \
10041  ((INSTANCE) == TIM5) || \
10042  ((INSTANCE) == TIM8))
10043 
10044 /******************** TIM Instances : DMA burst feature ***********************/
10045 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10046  ((INSTANCE) == TIM2) || \
10047  ((INSTANCE) == TIM3) || \
10048  ((INSTANCE) == TIM4) || \
10049  ((INSTANCE) == TIM5) || \
10050  ((INSTANCE) == TIM8))
10051 
10052 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
10053 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10054  ((INSTANCE) == TIM2) || \
10055  ((INSTANCE) == TIM3) || \
10056  ((INSTANCE) == TIM4) || \
10057  ((INSTANCE) == TIM5) || \
10058  ((INSTANCE) == TIM6) || \
10059  ((INSTANCE) == TIM7) || \
10060  ((INSTANCE) == TIM8) || \
10061  ((INSTANCE) == TIM9) || \
10062  ((INSTANCE) == TIM12))
10063 
10064 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
10065 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10066  ((INSTANCE) == TIM2) || \
10067  ((INSTANCE) == TIM3) || \
10068  ((INSTANCE) == TIM4) || \
10069  ((INSTANCE) == TIM5) || \
10070  ((INSTANCE) == TIM8) || \
10071  ((INSTANCE) == TIM9) || \
10072  ((INSTANCE) == TIM12))
10073 
10074 /********************** TIM Instances : 32 bit Counter ************************/
10075 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
10076  ((INSTANCE) == TIM5))
10077 
10078 /***************** TIM Instances : external trigger input availabe ************/
10079 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10080  ((INSTANCE) == TIM2) || \
10081  ((INSTANCE) == TIM3) || \
10082  ((INSTANCE) == TIM4) || \
10083  ((INSTANCE) == TIM5) || \
10084  ((INSTANCE) == TIM8))
10085 
10086 /****************** TIM Instances : remapping capability **********************/
10087 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
10088  ((INSTANCE) == TIM5) || \
10089  ((INSTANCE) == TIM11))
10090 
10091 /******************* TIM Instances : output(s) available **********************/
10092 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10093  ((((INSTANCE) == TIM1) && \
10094  (((CHANNEL) == TIM_CHANNEL_1) || \
10095  ((CHANNEL) == TIM_CHANNEL_2) || \
10096  ((CHANNEL) == TIM_CHANNEL_3) || \
10097  ((CHANNEL) == TIM_CHANNEL_4))) \
10098  || \
10099  (((INSTANCE) == TIM2) && \
10100  (((CHANNEL) == TIM_CHANNEL_1) || \
10101  ((CHANNEL) == TIM_CHANNEL_2) || \
10102  ((CHANNEL) == TIM_CHANNEL_3) || \
10103  ((CHANNEL) == TIM_CHANNEL_4))) \
10104  || \
10105  (((INSTANCE) == TIM3) && \
10106  (((CHANNEL) == TIM_CHANNEL_1) || \
10107  ((CHANNEL) == TIM_CHANNEL_2) || \
10108  ((CHANNEL) == TIM_CHANNEL_3) || \
10109  ((CHANNEL) == TIM_CHANNEL_4))) \
10110  || \
10111  (((INSTANCE) == TIM4) && \
10112  (((CHANNEL) == TIM_CHANNEL_1) || \
10113  ((CHANNEL) == TIM_CHANNEL_2) || \
10114  ((CHANNEL) == TIM_CHANNEL_3) || \
10115  ((CHANNEL) == TIM_CHANNEL_4))) \
10116  || \
10117  (((INSTANCE) == TIM5) && \
10118  (((CHANNEL) == TIM_CHANNEL_1) || \
10119  ((CHANNEL) == TIM_CHANNEL_2) || \
10120  ((CHANNEL) == TIM_CHANNEL_3) || \
10121  ((CHANNEL) == TIM_CHANNEL_4))) \
10122  || \
10123  (((INSTANCE) == TIM8) && \
10124  (((CHANNEL) == TIM_CHANNEL_1) || \
10125  ((CHANNEL) == TIM_CHANNEL_2) || \
10126  ((CHANNEL) == TIM_CHANNEL_3) || \
10127  ((CHANNEL) == TIM_CHANNEL_4))) \
10128  || \
10129  (((INSTANCE) == TIM9) && \
10130  (((CHANNEL) == TIM_CHANNEL_1) || \
10131  ((CHANNEL) == TIM_CHANNEL_2))) \
10132  || \
10133  (((INSTANCE) == TIM10) && \
10134  (((CHANNEL) == TIM_CHANNEL_1))) \
10135  || \
10136  (((INSTANCE) == TIM11) && \
10137  (((CHANNEL) == TIM_CHANNEL_1))) \
10138  || \
10139  (((INSTANCE) == TIM12) && \
10140  (((CHANNEL) == TIM_CHANNEL_1) || \
10141  ((CHANNEL) == TIM_CHANNEL_2))) \
10142  || \
10143  (((INSTANCE) == TIM13) && \
10144  (((CHANNEL) == TIM_CHANNEL_1))) \
10145  || \
10146  (((INSTANCE) == TIM14) && \
10147  (((CHANNEL) == TIM_CHANNEL_1))))
10148 
10149 /************ TIM Instances : complementary output(s) available ***************/
10150 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10151  ((((INSTANCE) == TIM1) && \
10152  (((CHANNEL) == TIM_CHANNEL_1) || \
10153  ((CHANNEL) == TIM_CHANNEL_2) || \
10154  ((CHANNEL) == TIM_CHANNEL_3))) \
10155  || \
10156  (((INSTANCE) == TIM8) && \
10157  (((CHANNEL) == TIM_CHANNEL_1) || \
10158  ((CHANNEL) == TIM_CHANNEL_2) || \
10159  ((CHANNEL) == TIM_CHANNEL_3))))
10160 
10161 /******************** USART Instances : Synchronous mode **********************/
10162 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10163  ((INSTANCE) == USART2) || \
10164  ((INSTANCE) == USART3) || \
10165  ((INSTANCE) == USART6))
10166 
10167 /******************** UART Instances : Asynchronous mode **********************/
10168 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10169  ((INSTANCE) == USART2) || \
10170  ((INSTANCE) == USART3) || \
10171  ((INSTANCE) == UART4) || \
10172  ((INSTANCE) == UART5) || \
10173  ((INSTANCE) == USART6) || \
10174  ((INSTANCE) == UART7) || \
10175  ((INSTANCE) == UART8))
10176 
10177 /****************** UART Instances : Hardware Flow control ********************/
10178 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10179  ((INSTANCE) == USART2) || \
10180  ((INSTANCE) == USART3) || \
10181  ((INSTANCE) == USART6))
10182 
10183 /********************* UART Instances : Smard card mode ***********************/
10184 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10185  ((INSTANCE) == USART2) || \
10186  ((INSTANCE) == USART3) || \
10187  ((INSTANCE) == USART6))
10188 
10189 /*********************** UART Instances : IRDA mode ***************************/
10190 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10191  ((INSTANCE) == USART2) || \
10192  ((INSTANCE) == USART3) || \
10193  ((INSTANCE) == UART4) || \
10194  ((INSTANCE) == UART5) || \
10195  ((INSTANCE) == USART6) || \
10196  ((INSTANCE) == UART7) || \
10197  ((INSTANCE) == UART8))
10198 
10199 /*********************** PCD Instances ****************************************/
10200 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
10201  ((INSTANCE) == USB_OTG_HS))
10202 
10203 /*********************** HCD Instances ****************************************/
10204 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
10205  ((INSTANCE) == USB_OTG_HS))
10206 
10207 /****************************** SDIO Instances ********************************/
10208 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
10209 
10210 /****************************** IWDG Instances ********************************/
10211 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
10212 
10213 /****************************** WWDG Instances ********************************/
10214 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
10215 
10216 /****************************** QSPI Instances ********************************/
10217 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
10218 
10219 /****************************** USB Exported Constants ************************/
10220 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
10221 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
10222 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
10223 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
10224 
10225 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
10226 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
10227 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
10228 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
10229 
10242 #ifdef __cplusplus
10243 }
10244 #endif /* __cplusplus */
10245 
10246 #endif /* __STM32F469xx_H */
10247 
10248 
10249 
10250 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DSI_TypeDef::VMCCR
__IO uint32_t VMCCR
Definition: stm32f469xx.h:478
DSI_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f469xx.h:438
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f429xx.h:653
DSI_TypeDef::WRPCR
__IO uint32_t WRPCR
Definition: stm32f469xx.h:500
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
DSI_TypeDef::VCCR
__IO uint32_t VCCR
Definition: stm32f469xx.h:441
SAI1_IRQn
Definition: stm32f469xx.h:182
TAMP_STAMP_IRQn
Definition: stm32f469xx.h:98
DSI_TypeDef::VVBPCCR
__IO uint32_t VVBPCCR
Definition: stm32f469xx.h:486
QUADSPI_IRQn
Definition: stm32f469xx.h:186
TIM2_IRQn
Definition: stm32f469xx.h:124
UART4_IRQn
Definition: stm32f469xx.h:148
DSI_TypeDef::VHBPCCR
__IO uint32_t VHBPCCR
Definition: stm32f469xx.h:483
UART5_IRQn
Definition: stm32f469xx.h:149
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f469xx.h:122
EXTI2_IRQn
Definition: stm32f469xx.h:104
EXTI4_IRQn
Definition: stm32f469xx.h:106
USART1_IRQn
Definition: stm32f469xx.h:133
DSI_TypeDef::RESERVED10
uint32_t RESERVED10
Definition: stm32f469xx.h:499
DSI_TypeDef::LVCIDR
__IO uint32_t LVCIDR
Definition: stm32f469xx.h:431
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
ETH_WKUP_IRQn
Definition: stm32f469xx.h:158
DSI_TypeDef::LCCCR
__IO uint32_t LCCCR
Definition: stm32f469xx.h:474
DMA2D_IRQn
Definition: stm32f469xx.h:185
DSI_TypeDef::GPDR
__IO uint32_t GPDR
Definition: stm32f469xx.h:453
DSI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f469xx.h:430
DSI_TypeDef::VHSACCR
__IO uint32_t VHSACCR
Definition: stm32f469xx.h:482
DSI_TypeDef::LCOLCR
__IO uint32_t LCOLCR
Definition: stm32f469xx.h:432
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f469xx.h:141
TIM4_IRQn
Definition: stm32f469xx.h:126
RTC_Alarm_IRQn
Definition: stm32f469xx.h:137
DSI_TypeDef::PCTLR
__IO uint32_t PCTLR
Definition: stm32f469xx.h:460
DSI_IRQn
Definition: stm32f469xx.h:187
CAN2_SCE_IRQn
Definition: stm32f469xx.h:162
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f446xx.h:451
PendSV_IRQn
Definition: stm32f469xx.h:93
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f469xx.h:99
DSI_TypeDef::VR
__IO uint32_t VR
Definition: stm32f469xx.h:428
DSI_TypeDef::VVACR
__IO uint32_t VVACR
Definition: stm32f469xx.h:449
DSI_TypeDef::GPSR
__IO uint32_t GPSR
Definition: stm32f469xx.h:454
CAN1_RX1_IRQn
Definition: stm32f469xx.h:117
TIM6_DAC_IRQn
Definition: stm32f469xx.h:150
LTDC_IRQn
Definition: stm32f469xx.h:183
DSI_TypeDef::VPCR
__IO uint32_t VPCR
Definition: stm32f469xx.h:440
CAN1_TX_IRQn
Definition: stm32f469xx.h:115
DSI_TypeDef::WIFCR
__IO uint32_t WIFCR
Definition: stm32f469xx.h:496
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
DSI_TypeDef::VLCCR
__IO uint32_t VLCCR
Definition: stm32f469xx.h:484
SPI1_IRQn
Definition: stm32f469xx.h:131
DSI_TypeDef::GHCR
__IO uint32_t GHCR
Definition: stm32f469xx.h:452
DSI_TypeDef::WCR
__IO uint32_t WCR
Definition: stm32f469xx.h:493
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f427xx.h:534
OTG_FS_WKUP_IRQn
Definition: stm32f469xx.h:138
DSI_TypeDef::CLTCR
__IO uint32_t CLTCR
Definition: stm32f469xx.h:458
DMA_TypeDef
Definition: stm32f401xc.h:243
ETH_IRQn
Definition: stm32f469xx.h:157
DSI_TypeDef::LCVCIDR
__IO uint32_t LCVCIDR
Definition: stm32f469xx.h:473
DMA1_Stream2_IRQn
Definition: stm32f469xx.h:109
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f469xx.h:132
DSI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f469xx.h:429
DSI_TypeDef::VNPCR
__IO uint32_t VNPCR
Definition: stm32f469xx.h:442
__I
#define __I
Definition: core_cm0.h:210
DSI_TypeDef::RESERVED5
uint32_t RESERVED5
Definition: stm32f469xx.h:475
DSI_TypeDef::PUCR
__IO uint32_t PUCR
Definition: stm32f469xx.h:462
DMA2_Stream5_IRQn
Definition: stm32f469xx.h:164
DSI_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32f469xx.h:497
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f429xx.h:678
ADC_IRQn
Definition: stm32f469xx.h:114
CAN1_RX0_IRQn
Definition: stm32f469xx.h:116
DSI_TypeDef::DLTCR
__IO uint32_t DLTCR
Definition: stm32f469xx.h:459
DSI_TypeDef::TDCR
__IO uint32_t TDCR
Definition: stm32f469xx.h:456
RCC_IRQn
Definition: stm32f469xx.h:101
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f469xx.h:92
DSI_TypeDef::PSR
__IO uint32_t PSR
Definition: stm32f469xx.h:464
DMA2_Stream3_IRQn
Definition: stm32f469xx.h:155
NonMaskableInt_IRQn
Definition: stm32f469xx.h:87
UART8_IRQn
Definition: stm32f469xx.h:178
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f469xx.h:84
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f469xx.h:140
DMA1_Stream1_IRQn
Definition: stm32f469xx.h:108
DMA2_Stream7_IRQn
Definition: stm32f469xx.h:166
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f412rx.h:645
DMA2_Stream6_IRQn
Definition: stm32f469xx.h:165
BusFault_IRQn
Definition: stm32f469xx.h:89
DSI_TypeDef::TDCCR
__IO uint32_t TDCCR
Definition: stm32f469xx.h:490
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
I2C3_ER_IRQn
Definition: stm32f469xx.h:169
DSI_TypeDef::CMCR
__IO uint32_t CMCR
Definition: stm32f469xx.h:451
CAN2_RX0_IRQn
Definition: stm32f469xx.h:160
USART6_IRQn
Definition: stm32f469xx.h:167
DSI_TypeDef::VVFPCCR
__IO uint32_t VVFPCCR
Definition: stm32f469xx.h:487
PVD_IRQn
Definition: stm32f469xx.h:97
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f427xx.h:391
__IO
#define __IO
Definition: core_cm0.h:213
DSI_TypeDef::VSCR
__IO uint32_t VSCR
Definition: stm32f469xx.h:471
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f469xx.h:111
DSI_TypeDef::VVACCR
__IO uint32_t VVACCR
Definition: stm32f469xx.h:488
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f427xx.h:750
DMA1_Stream0_IRQn
Definition: stm32f469xx.h:107
OTG_HS_IRQn
Definition: stm32f469xx.h:173
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f469xx.h:179
TIM8_CC_IRQn
Definition: stm32f469xx.h:142
DSI_TypeDef::VMCR
__IO uint32_t VMCR
Definition: stm32f469xx.h:439
DMA1_Stream3_IRQn
Definition: stm32f469xx.h:110
DSI_TypeDef::VHBPCR
__IO uint32_t VHBPCR
Definition: stm32f469xx.h:444
FPU_IRQn
Definition: stm32f469xx.h:176
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:386
DSI_TypeDef::VPCCR
__IO uint32_t VPCCR
Definition: stm32f469xx.h:479
OTG_FS_IRQn
Definition: stm32f469xx.h:163
DMA2_Stream2_IRQn
Definition: stm32f469xx.h:154
DSI_TypeDef::VVSACCR
__IO uint32_t VVSACCR
Definition: stm32f469xx.h:485
OTG_HS_EP1_OUT_IRQn
Definition: stm32f469xx.h:170
OTG_HS_EP1_IN_IRQn
Definition: stm32f469xx.h:171
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f469xx.h:145
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f469xx.h:168
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f469xx.h:134
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
LTDC_ER_IRQn
Definition: stm32f469xx.h:184
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f469xx.h:151
I2C2_EV_IRQn
Definition: stm32f469xx.h:129
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f469xx.h:125
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f469xx.h:103
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f469xx.h:91
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f469xx.h:123
TIM8_BRK_TIM12_IRQn
Definition: stm32f469xx.h:139
DSI_TypeDef::LPCR
__IO uint32_t LPCR
Definition: stm32f469xx.h:433
DSI_TypeDef::LCCR
__IO uint32_t LCCR
Definition: stm32f469xx.h:450
HASH_RNG_IRQn
Definition: stm32f469xx.h:175
FLASH_IRQn
Definition: stm32f469xx.h:100
DMA1_Stream5_IRQn
Definition: stm32f469xx.h:112
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f469xx.h:94
DSI_TypeDef::WIER
__IO uint32_t WIER
Definition: stm32f469xx.h:494
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f427xx.h:525
SPI6_IRQn
Definition: stm32f469xx.h:181
TIM1_UP_TIM10_IRQn
Definition: stm32f469xx.h:121
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f469xx.h:130
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:344
DSI_TypeDef::LPMCCR
__IO uint32_t LPMCCR
Definition: stm32f469xx.h:476
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f427xx.h:578
UsageFault_IRQn
Definition: stm32f469xx.h:90
FMC_IRQn
Definition: stm32f469xx.h:144
SPI3_IRQn
Definition: stm32f469xx.h:147
DMA2_Stream1_IRQn
Definition: stm32f469xx.h:153
EXTI9_5_IRQn
Definition: stm32f469xx.h:119
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f469xx.h:127
DMA1_Stream6_IRQn
Definition: stm32f469xx.h:113
OTG_HS_WKUP_IRQn
Definition: stm32f469xx.h:172
I2C1_ER_IRQn
Definition: stm32f469xx.h:128
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
DSI_TypeDef::VLCR
__IO uint32_t VLCR
Definition: stm32f469xx.h:445
UART7_IRQn
Definition: stm32f469xx.h:177
DSI_TypeDef::PTTCR
__IO uint32_t PTTCR
Definition: stm32f469xx.h:463
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
DSI_TypeDef::VNPCCR
__IO uint32_t VNPCCR
Definition: stm32f469xx.h:481
DSI_TypeDef::WISR
__IO uint32_t WISR
Definition: stm32f469xx.h:495
DSI_TypeDef::VVBPCR
__IO uint32_t VVBPCR
Definition: stm32f469xx.h:447
DSI_TypeDef::LPMCR
__IO uint32_t LPMCR
Definition: stm32f469xx.h:434
DSI_TypeDef::GVCIDR
__IO uint32_t GVCIDR
Definition: stm32f469xx.h:437
SAI_Block_TypeDef
Definition: stm32f427xx.h:755
CAN2_RX1_IRQn
Definition: stm32f469xx.h:161
DMA2_Stream4_IRQn
Definition: stm32f469xx.h:156
WWDG_IRQn
Definition: stm32f469xx.h:96
DMA1_Stream7_IRQn
Definition: stm32f469xx.h:143
DSI_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32f469xx.h:436
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
DSI_TypeDef::VCCCR
__IO uint32_t VCCCR
Definition: stm32f469xx.h:480
SPI5_IRQn
Definition: stm32f469xx.h:180
EXTI15_10_IRQn
Definition: stm32f469xx.h:136
CAN1_SCE_IRQn
Definition: stm32f469xx.h:118
DSI_TypeDef::CLCR
__IO uint32_t CLCR
Definition: stm32f469xx.h:457
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f469xx.h:102
DMA2_Stream0_IRQn
Definition: stm32f469xx.h:152
DSI_TypeDef::WCFGR
__IO uint32_t WCFGR
Definition: stm32f469xx.h:492
DSI_TypeDef::VVFPCR
__IO uint32_t VVFPCR
Definition: stm32f469xx.h:448
DSI_TypeDef::VHSACR
__IO uint32_t VHSACR
Definition: stm32f469xx.h:443
TIM1_BRK_TIM9_IRQn
Definition: stm32f469xx.h:120
CAN2_TX_IRQn
Definition: stm32f469xx.h:159
TIM5_IRQn
Definition: stm32f469xx.h:146
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
DSI_TypeDef::VVSACR
__IO uint32_t VVSACR
Definition: stm32f469xx.h:446
EXTI3_IRQn
Definition: stm32f469xx.h:105
USART3_IRQn
Definition: stm32f469xx.h:135
DCMI_IRQn
Definition: stm32f469xx.h:174
DSI_TypeDef
DSI Controller.
Definition: stm32f469xx.h:426
DSI_TypeDef::PCONFR
__IO uint32_t PCONFR
Definition: stm32f469xx.h:461
MemoryManagement_IRQn
Definition: stm32f469xx.h:88