STM CMSIS
stm32f479xx.h
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1 
52 #ifndef __STM32F479xx_H
53 #define __STM32F479xx_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif /* __cplusplus */
58 
66 #define __CM4_REV 0x0001U
67 #define __MPU_PRESENT 1U
68 #define __NVIC_PRIO_BITS 4U
69 #define __Vendor_SysTickConfig 0U
70 #define __FPU_PRESENT 1U
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87  NonMaskableInt_IRQn = -14,
88  MemoryManagement_IRQn = -12,
89  BusFault_IRQn = -11,
90  UsageFault_IRQn = -10,
91  SVCall_IRQn = -5,
92  DebugMonitor_IRQn = -4,
93  PendSV_IRQn = -2,
94  SysTick_IRQn = -1,
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96  WWDG_IRQn = 0,
97  PVD_IRQn = 1,
98  TAMP_STAMP_IRQn = 2,
99  RTC_WKUP_IRQn = 3,
100  FLASH_IRQn = 4,
101  RCC_IRQn = 5,
102  EXTI0_IRQn = 6,
103  EXTI1_IRQn = 7,
104  EXTI2_IRQn = 8,
105  EXTI3_IRQn = 9,
106  EXTI4_IRQn = 10,
107  DMA1_Stream0_IRQn = 11,
108  DMA1_Stream1_IRQn = 12,
109  DMA1_Stream2_IRQn = 13,
110  DMA1_Stream3_IRQn = 14,
111  DMA1_Stream4_IRQn = 15,
112  DMA1_Stream5_IRQn = 16,
113  DMA1_Stream6_IRQn = 17,
114  ADC_IRQn = 18,
115  CAN1_TX_IRQn = 19,
116  CAN1_RX0_IRQn = 20,
117  CAN1_RX1_IRQn = 21,
118  CAN1_SCE_IRQn = 22,
119  EXTI9_5_IRQn = 23,
120  TIM1_BRK_TIM9_IRQn = 24,
121  TIM1_UP_TIM10_IRQn = 25,
122  TIM1_TRG_COM_TIM11_IRQn = 26,
123  TIM1_CC_IRQn = 27,
124  TIM2_IRQn = 28,
125  TIM3_IRQn = 29,
126  TIM4_IRQn = 30,
127  I2C1_EV_IRQn = 31,
128  I2C1_ER_IRQn = 32,
129  I2C2_EV_IRQn = 33,
130  I2C2_ER_IRQn = 34,
131  SPI1_IRQn = 35,
132  SPI2_IRQn = 36,
133  USART1_IRQn = 37,
134  USART2_IRQn = 38,
135  USART3_IRQn = 39,
136  EXTI15_10_IRQn = 40,
137  RTC_Alarm_IRQn = 41,
138  OTG_FS_WKUP_IRQn = 42,
139  TIM8_BRK_TIM12_IRQn = 43,
140  TIM8_UP_TIM13_IRQn = 44,
141  TIM8_TRG_COM_TIM14_IRQn = 45,
142  TIM8_CC_IRQn = 46,
143  DMA1_Stream7_IRQn = 47,
144  FMC_IRQn = 48,
145  SDIO_IRQn = 49,
146  TIM5_IRQn = 50,
147  SPI3_IRQn = 51,
148  UART4_IRQn = 52,
149  UART5_IRQn = 53,
150  TIM6_DAC_IRQn = 54,
151  TIM7_IRQn = 55,
152  DMA2_Stream0_IRQn = 56,
153  DMA2_Stream1_IRQn = 57,
154  DMA2_Stream2_IRQn = 58,
155  DMA2_Stream3_IRQn = 59,
156  DMA2_Stream4_IRQn = 60,
157  ETH_IRQn = 61,
158  ETH_WKUP_IRQn = 62,
159  CAN2_TX_IRQn = 63,
160  CAN2_RX0_IRQn = 64,
161  CAN2_RX1_IRQn = 65,
162  CAN2_SCE_IRQn = 66,
163  OTG_FS_IRQn = 67,
164  DMA2_Stream5_IRQn = 68,
165  DMA2_Stream6_IRQn = 69,
166  DMA2_Stream7_IRQn = 70,
167  USART6_IRQn = 71,
168  I2C3_EV_IRQn = 72,
169  I2C3_ER_IRQn = 73,
170  OTG_HS_EP1_OUT_IRQn = 74,
171  OTG_HS_EP1_IN_IRQn = 75,
172  OTG_HS_WKUP_IRQn = 76,
173  OTG_HS_IRQn = 77,
174  DCMI_IRQn = 78,
175  CRYP_IRQn = 79,
176  HASH_RNG_IRQn = 80,
177  FPU_IRQn = 81,
178  UART7_IRQn = 82,
179  UART8_IRQn = 83,
180  SPI4_IRQn = 84,
181  SPI5_IRQn = 85,
182  SPI6_IRQn = 86,
183  SAI1_IRQn = 87,
184  LTDC_IRQn = 88,
185  LTDC_ER_IRQn = 89,
186  DMA2D_IRQn = 90,
187  QUADSPI_IRQn = 91,
188  DSI_IRQn = 92
189 } IRQn_Type;
190 
195 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
196 #include "system_stm32f4xx.h"
197 #include <stdint.h>
198 
207 typedef struct
208 {
209  __IO uint32_t SR;
210  __IO uint32_t CR1;
211  __IO uint32_t CR2;
212  __IO uint32_t SMPR1;
213  __IO uint32_t SMPR2;
214  __IO uint32_t JOFR1;
215  __IO uint32_t JOFR2;
216  __IO uint32_t JOFR3;
217  __IO uint32_t JOFR4;
218  __IO uint32_t HTR;
219  __IO uint32_t LTR;
220  __IO uint32_t SQR1;
221  __IO uint32_t SQR2;
222  __IO uint32_t SQR3;
223  __IO uint32_t JSQR;
224  __IO uint32_t JDR1;
225  __IO uint32_t JDR2;
226  __IO uint32_t JDR3;
227  __IO uint32_t JDR4;
228  __IO uint32_t DR;
229 } ADC_TypeDef;
230 
231 typedef struct
232 {
233  __IO uint32_t CSR;
234  __IO uint32_t CCR;
235  __IO uint32_t CDR;
237 } ADC_Common_TypeDef;
238 
239 
244 typedef struct
245 {
246  __IO uint32_t TIR;
247  __IO uint32_t TDTR;
248  __IO uint32_t TDLR;
249  __IO uint32_t TDHR;
250 } CAN_TxMailBox_TypeDef;
251 
256 typedef struct
257 {
258  __IO uint32_t RIR;
259  __IO uint32_t RDTR;
260  __IO uint32_t RDLR;
261  __IO uint32_t RDHR;
262 } CAN_FIFOMailBox_TypeDef;
263 
268 typedef struct
269 {
270  __IO uint32_t FR1;
271  __IO uint32_t FR2;
272 } CAN_FilterRegister_TypeDef;
273 
278 typedef struct
279 {
280  __IO uint32_t MCR;
281  __IO uint32_t MSR;
282  __IO uint32_t TSR;
283  __IO uint32_t RF0R;
284  __IO uint32_t RF1R;
285  __IO uint32_t IER;
286  __IO uint32_t ESR;
287  __IO uint32_t BTR;
288  uint32_t RESERVED0[88];
289  CAN_TxMailBox_TypeDef sTxMailBox[3];
290  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
291  uint32_t RESERVED1[12];
292  __IO uint32_t FMR;
293  __IO uint32_t FM1R;
294  uint32_t RESERVED2;
295  __IO uint32_t FS1R;
296  uint32_t RESERVED3;
297  __IO uint32_t FFA1R;
298  uint32_t RESERVED4;
299  __IO uint32_t FA1R;
300  uint32_t RESERVED5[8];
301  CAN_FilterRegister_TypeDef sFilterRegister[28];
302 } CAN_TypeDef;
303 
308 typedef struct
309 {
310  __IO uint32_t DR;
311  __IO uint8_t IDR;
312  uint8_t RESERVED0;
313  uint16_t RESERVED1;
314  __IO uint32_t CR;
315 } CRC_TypeDef;
316 
321 typedef struct
322 {
323  __IO uint32_t CR;
324  __IO uint32_t SWTRIGR;
325  __IO uint32_t DHR12R1;
326  __IO uint32_t DHR12L1;
327  __IO uint32_t DHR8R1;
328  __IO uint32_t DHR12R2;
329  __IO uint32_t DHR12L2;
330  __IO uint32_t DHR8R2;
331  __IO uint32_t DHR12RD;
332  __IO uint32_t DHR12LD;
333  __IO uint32_t DHR8RD;
334  __IO uint32_t DOR1;
335  __IO uint32_t DOR2;
336  __IO uint32_t SR;
337 } DAC_TypeDef;
338 
343 typedef struct
344 {
345  __IO uint32_t IDCODE;
346  __IO uint32_t CR;
347  __IO uint32_t APB1FZ;
348  __IO uint32_t APB2FZ;
349 }DBGMCU_TypeDef;
350 
355 typedef struct
356 {
357  __IO uint32_t CR;
358  __IO uint32_t SR;
359  __IO uint32_t RISR;
360  __IO uint32_t IER;
361  __IO uint32_t MISR;
362  __IO uint32_t ICR;
363  __IO uint32_t ESCR;
364  __IO uint32_t ESUR;
365  __IO uint32_t CWSTRTR;
366  __IO uint32_t CWSIZER;
367  __IO uint32_t DR;
368 } DCMI_TypeDef;
369 
374 typedef struct
375 {
376  __IO uint32_t CR;
377  __IO uint32_t NDTR;
378  __IO uint32_t PAR;
379  __IO uint32_t M0AR;
380  __IO uint32_t M1AR;
381  __IO uint32_t FCR;
382 } DMA_Stream_TypeDef;
383 
384 typedef struct
385 {
386  __IO uint32_t LISR;
387  __IO uint32_t HISR;
388  __IO uint32_t LIFCR;
389  __IO uint32_t HIFCR;
390 } DMA_TypeDef;
391 
396 typedef struct
397 {
398  __IO uint32_t CR;
399  __IO uint32_t ISR;
400  __IO uint32_t IFCR;
401  __IO uint32_t FGMAR;
402  __IO uint32_t FGOR;
403  __IO uint32_t BGMAR;
404  __IO uint32_t BGOR;
405  __IO uint32_t FGPFCCR;
406  __IO uint32_t FGCOLR;
407  __IO uint32_t BGPFCCR;
408  __IO uint32_t BGCOLR;
409  __IO uint32_t FGCMAR;
410  __IO uint32_t BGCMAR;
411  __IO uint32_t OPFCCR;
412  __IO uint32_t OCOLR;
413  __IO uint32_t OMAR;
414  __IO uint32_t OOR;
415  __IO uint32_t NLR;
416  __IO uint32_t LWR;
417  __IO uint32_t AMTCR;
418  uint32_t RESERVED[236];
419  __IO uint32_t FGCLUT[256];
420  __IO uint32_t BGCLUT[256];
421 } DMA2D_TypeDef;
422 
427 typedef struct
428 {
429  __IO uint32_t VR;
430  __IO uint32_t CR;
431  __IO uint32_t CCR;
432  __IO uint32_t LVCIDR;
433  __IO uint32_t LCOLCR;
434  __IO uint32_t LPCR;
435  __IO uint32_t LPMCR;
436  uint32_t RESERVED0[4];
437  __IO uint32_t PCR;
438  __IO uint32_t GVCIDR;
439  __IO uint32_t MCR;
440  __IO uint32_t VMCR;
441  __IO uint32_t VPCR;
442  __IO uint32_t VCCR;
443  __IO uint32_t VNPCR;
444  __IO uint32_t VHSACR;
445  __IO uint32_t VHBPCR;
446  __IO uint32_t VLCR;
447  __IO uint32_t VVSACR;
448  __IO uint32_t VVBPCR;
449  __IO uint32_t VVFPCR;
450  __IO uint32_t VVACR;
451  __IO uint32_t LCCR;
452  __IO uint32_t CMCR;
453  __IO uint32_t GHCR;
454  __IO uint32_t GPDR;
455  __IO uint32_t GPSR;
456  __IO uint32_t TCCR[6];
457  __IO uint32_t TDCR;
458  __IO uint32_t CLCR;
459  __IO uint32_t CLTCR;
460  __IO uint32_t DLTCR;
461  __IO uint32_t PCTLR;
462  __IO uint32_t PCONFR;
463  __IO uint32_t PUCR;
464  __IO uint32_t PTTCR;
465  __IO uint32_t PSR;
466  uint32_t RESERVED1[2];
467  __IO uint32_t ISR[2];
468  __IO uint32_t IER[2];
469  uint32_t RESERVED2[3];
470  __IO uint32_t FIR[2];
471  uint32_t RESERVED3[8];
472  __IO uint32_t VSCR;
473  uint32_t RESERVED4[2];
474  __IO uint32_t LCVCIDR;
475  __IO uint32_t LCCCR;
476  uint32_t RESERVED5;
477  __IO uint32_t LPMCCR;
478  uint32_t RESERVED6[7];
479  __IO uint32_t VMCCR;
480  __IO uint32_t VPCCR;
481  __IO uint32_t VCCCR;
482  __IO uint32_t VNPCCR;
483  __IO uint32_t VHSACCR;
484  __IO uint32_t VHBPCCR;
485  __IO uint32_t VLCCR;
486  __IO uint32_t VVSACCR;
487  __IO uint32_t VVBPCCR;
488  __IO uint32_t VVFPCCR;
489  __IO uint32_t VVACCR;
490  uint32_t RESERVED7[11];
491  __IO uint32_t TDCCR;
492  uint32_t RESERVED8[155];
493  __IO uint32_t WCFGR;
494  __IO uint32_t WCR;
495  __IO uint32_t WIER;
496  __IO uint32_t WISR;
497  __IO uint32_t WIFCR;
498  uint32_t RESERVED9;
499  __IO uint32_t WPCR[5];
500  uint32_t RESERVED10;
501  __IO uint32_t WRPCR;
502 } DSI_TypeDef;
503 
508 typedef struct
509 {
510  __IO uint32_t MACCR;
511  __IO uint32_t MACFFR;
512  __IO uint32_t MACHTHR;
513  __IO uint32_t MACHTLR;
514  __IO uint32_t MACMIIAR;
515  __IO uint32_t MACMIIDR;
516  __IO uint32_t MACFCR;
517  __IO uint32_t MACVLANTR; /* 8 */
518  uint32_t RESERVED0[2];
519  __IO uint32_t MACRWUFFR; /* 11 */
520  __IO uint32_t MACPMTCSR;
521  uint32_t RESERVED1[2];
522  __IO uint32_t MACSR; /* 15 */
523  __IO uint32_t MACIMR;
524  __IO uint32_t MACA0HR;
525  __IO uint32_t MACA0LR;
526  __IO uint32_t MACA1HR;
527  __IO uint32_t MACA1LR;
528  __IO uint32_t MACA2HR;
529  __IO uint32_t MACA2LR;
530  __IO uint32_t MACA3HR;
531  __IO uint32_t MACA3LR; /* 24 */
532  uint32_t RESERVED2[40];
533  __IO uint32_t MMCCR; /* 65 */
534  __IO uint32_t MMCRIR;
535  __IO uint32_t MMCTIR;
536  __IO uint32_t MMCRIMR;
537  __IO uint32_t MMCTIMR; /* 69 */
538  uint32_t RESERVED3[14];
539  __IO uint32_t MMCTGFSCCR; /* 84 */
540  __IO uint32_t MMCTGFMSCCR;
541  uint32_t RESERVED4[5];
542  __IO uint32_t MMCTGFCR;
543  uint32_t RESERVED5[10];
544  __IO uint32_t MMCRFCECR;
545  __IO uint32_t MMCRFAECR;
546  uint32_t RESERVED6[10];
547  __IO uint32_t MMCRGUFCR;
548  uint32_t RESERVED7[334];
549  __IO uint32_t PTPTSCR;
550  __IO uint32_t PTPSSIR;
551  __IO uint32_t PTPTSHR;
552  __IO uint32_t PTPTSLR;
553  __IO uint32_t PTPTSHUR;
554  __IO uint32_t PTPTSLUR;
555  __IO uint32_t PTPTSAR;
556  __IO uint32_t PTPTTHR;
557  __IO uint32_t PTPTTLR;
558  __IO uint32_t RESERVED8;
559  __IO uint32_t PTPTSSR;
560  uint32_t RESERVED9[565];
561  __IO uint32_t DMABMR;
562  __IO uint32_t DMATPDR;
563  __IO uint32_t DMARPDR;
564  __IO uint32_t DMARDLAR;
565  __IO uint32_t DMATDLAR;
566  __IO uint32_t DMASR;
567  __IO uint32_t DMAOMR;
568  __IO uint32_t DMAIER;
569  __IO uint32_t DMAMFBOCR;
570  __IO uint32_t DMARSWTR;
571  uint32_t RESERVED10[8];
572  __IO uint32_t DMACHTDR;
573  __IO uint32_t DMACHRDR;
574  __IO uint32_t DMACHTBAR;
575  __IO uint32_t DMACHRBAR;
576 } ETH_TypeDef;
577 
582 typedef struct
583 {
584  __IO uint32_t IMR;
585  __IO uint32_t EMR;
586  __IO uint32_t RTSR;
587  __IO uint32_t FTSR;
588  __IO uint32_t SWIER;
589  __IO uint32_t PR;
590 } EXTI_TypeDef;
591 
596 typedef struct
597 {
598  __IO uint32_t ACR;
599  __IO uint32_t KEYR;
600  __IO uint32_t OPTKEYR;
601  __IO uint32_t SR;
602  __IO uint32_t CR;
603  __IO uint32_t OPTCR;
604  __IO uint32_t OPTCR1;
605 } FLASH_TypeDef;
606 
611 typedef struct
612 {
613  __IO uint32_t BTCR[8];
614 } FMC_Bank1_TypeDef;
615 
620 typedef struct
621 {
622  __IO uint32_t BWTR[7];
623 } FMC_Bank1E_TypeDef;
624 
629 typedef struct
630 {
631  __IO uint32_t PCR;
632  __IO uint32_t SR;
633  __IO uint32_t PMEM;
634  __IO uint32_t PATT;
635  uint32_t RESERVED;
636  __IO uint32_t ECCR;
637 } FMC_Bank3_TypeDef;
638 
643 typedef struct
644 {
645  __IO uint32_t SDCR[2];
646  __IO uint32_t SDTR[2];
647  __IO uint32_t SDCMR;
648  __IO uint32_t SDRTR;
649  __IO uint32_t SDSR;
650 } FMC_Bank5_6_TypeDef;
651 
656 typedef struct
657 {
658  __IO uint32_t MODER;
659  __IO uint32_t OTYPER;
660  __IO uint32_t OSPEEDR;
661  __IO uint32_t PUPDR;
662  __IO uint32_t IDR;
663  __IO uint32_t ODR;
664  __IO uint32_t BSRR;
665  __IO uint32_t LCKR;
666  __IO uint32_t AFR[2];
667 } GPIO_TypeDef;
668 
673 typedef struct
674 {
675  __IO uint32_t MEMRMP;
676  __IO uint32_t PMC;
677  __IO uint32_t EXTICR[4];
678  uint32_t RESERVED[2];
679  __IO uint32_t CMPCR;
680 } SYSCFG_TypeDef;
681 
686 typedef struct
687 {
688  __IO uint32_t CR1;
689  __IO uint32_t CR2;
690  __IO uint32_t OAR1;
691  __IO uint32_t OAR2;
692  __IO uint32_t DR;
693  __IO uint32_t SR1;
694  __IO uint32_t SR2;
695  __IO uint32_t CCR;
696  __IO uint32_t TRISE;
697  __IO uint32_t FLTR;
698 } I2C_TypeDef;
699 
704 typedef struct
705 {
706  __IO uint32_t KR;
707  __IO uint32_t PR;
708  __IO uint32_t RLR;
709  __IO uint32_t SR;
710 } IWDG_TypeDef;
711 
716 typedef struct
717 {
718  uint32_t RESERVED0[2];
719  __IO uint32_t SSCR;
720  __IO uint32_t BPCR;
721  __IO uint32_t AWCR;
722  __IO uint32_t TWCR;
723  __IO uint32_t GCR;
724  uint32_t RESERVED1[2];
725  __IO uint32_t SRCR;
726  uint32_t RESERVED2[1];
727  __IO uint32_t BCCR;
728  uint32_t RESERVED3[1];
729  __IO uint32_t IER;
730  __IO uint32_t ISR;
731  __IO uint32_t ICR;
732  __IO uint32_t LIPCR;
733  __IO uint32_t CPSR;
734  __IO uint32_t CDSR;
735 } LTDC_TypeDef;
736 
741 typedef struct
742 {
743  __IO uint32_t CR;
744  __IO uint32_t WHPCR;
745  __IO uint32_t WVPCR;
746  __IO uint32_t CKCR;
747  __IO uint32_t PFCR;
748  __IO uint32_t CACR;
749  __IO uint32_t DCCR;
750  __IO uint32_t BFCR;
751  uint32_t RESERVED0[2];
752  __IO uint32_t CFBAR;
753  __IO uint32_t CFBLR;
754  __IO uint32_t CFBLNR;
755  uint32_t RESERVED1[3];
756  __IO uint32_t CLUTWR;
758 } LTDC_Layer_TypeDef;
759 
764 typedef struct
765 {
766  __IO uint32_t CR;
767  __IO uint32_t CSR;
768 } PWR_TypeDef;
769 
774 typedef struct
775 {
776  __IO uint32_t CR;
777  __IO uint32_t PLLCFGR;
778  __IO uint32_t CFGR;
779  __IO uint32_t CIR;
780  __IO uint32_t AHB1RSTR;
781  __IO uint32_t AHB2RSTR;
782  __IO uint32_t AHB3RSTR;
783  uint32_t RESERVED0;
784  __IO uint32_t APB1RSTR;
785  __IO uint32_t APB2RSTR;
786  uint32_t RESERVED1[2];
787  __IO uint32_t AHB1ENR;
788  __IO uint32_t AHB2ENR;
789  __IO uint32_t AHB3ENR;
790  uint32_t RESERVED2;
791  __IO uint32_t APB1ENR;
792  __IO uint32_t APB2ENR;
793  uint32_t RESERVED3[2];
794  __IO uint32_t AHB1LPENR;
795  __IO uint32_t AHB2LPENR;
796  __IO uint32_t AHB3LPENR;
797  uint32_t RESERVED4;
798  __IO uint32_t APB1LPENR;
799  __IO uint32_t APB2LPENR;
800  uint32_t RESERVED5[2];
801  __IO uint32_t BDCR;
802  __IO uint32_t CSR;
803  uint32_t RESERVED6[2];
804  __IO uint32_t SSCGR;
805  __IO uint32_t PLLI2SCFGR;
806  __IO uint32_t PLLSAICFGR;
807  __IO uint32_t DCKCFGR;
809 } RCC_TypeDef;
810 
815 typedef struct
816 {
817  __IO uint32_t TR;
818  __IO uint32_t DR;
819  __IO uint32_t CR;
820  __IO uint32_t ISR;
821  __IO uint32_t PRER;
822  __IO uint32_t WUTR;
823  __IO uint32_t CALIBR;
824  __IO uint32_t ALRMAR;
825  __IO uint32_t ALRMBR;
826  __IO uint32_t WPR;
827  __IO uint32_t SSR;
828  __IO uint32_t SHIFTR;
829  __IO uint32_t TSTR;
830  __IO uint32_t TSDR;
831  __IO uint32_t TSSSR;
832  __IO uint32_t CALR;
833  __IO uint32_t TAFCR;
834  __IO uint32_t ALRMASSR;
835  __IO uint32_t ALRMBSSR;
836  uint32_t RESERVED7;
837  __IO uint32_t BKP0R;
838  __IO uint32_t BKP1R;
839  __IO uint32_t BKP2R;
840  __IO uint32_t BKP3R;
841  __IO uint32_t BKP4R;
842  __IO uint32_t BKP5R;
843  __IO uint32_t BKP6R;
844  __IO uint32_t BKP7R;
845  __IO uint32_t BKP8R;
846  __IO uint32_t BKP9R;
847  __IO uint32_t BKP10R;
848  __IO uint32_t BKP11R;
849  __IO uint32_t BKP12R;
850  __IO uint32_t BKP13R;
851  __IO uint32_t BKP14R;
852  __IO uint32_t BKP15R;
853  __IO uint32_t BKP16R;
854  __IO uint32_t BKP17R;
855  __IO uint32_t BKP18R;
856  __IO uint32_t BKP19R;
857 } RTC_TypeDef;
858 
863 typedef struct
864 {
865  __IO uint32_t GCR;
866 } SAI_TypeDef;
867 
868 typedef struct
869 {
870  __IO uint32_t CR1;
871  __IO uint32_t CR2;
872  __IO uint32_t FRCR;
873  __IO uint32_t SLOTR;
874  __IO uint32_t IMR;
875  __IO uint32_t SR;
876  __IO uint32_t CLRFR;
877  __IO uint32_t DR;
878 } SAI_Block_TypeDef;
879 
884 typedef struct
885 {
886  __IO uint32_t POWER;
887  __IO uint32_t CLKCR;
888  __IO uint32_t ARG;
889  __IO uint32_t CMD;
890  __I uint32_t RESPCMD;
891  __I uint32_t RESP1;
892  __I uint32_t RESP2;
893  __I uint32_t RESP3;
894  __I uint32_t RESP4;
895  __IO uint32_t DTIMER;
896  __IO uint32_t DLEN;
897  __IO uint32_t DCTRL;
898  __I uint32_t DCOUNT;
899  __I uint32_t STA;
900  __IO uint32_t ICR;
901  __IO uint32_t MASK;
902  uint32_t RESERVED0[2];
903  __I uint32_t FIFOCNT;
904  uint32_t RESERVED1[13];
905  __IO uint32_t FIFO;
906 } SDIO_TypeDef;
907 
912 typedef struct
913 {
914  __IO uint32_t CR1;
915  __IO uint32_t CR2;
916  __IO uint32_t SR;
917  __IO uint32_t DR;
918  __IO uint32_t CRCPR;
919  __IO uint32_t RXCRCR;
920  __IO uint32_t TXCRCR;
921  __IO uint32_t I2SCFGR;
922  __IO uint32_t I2SPR;
923 } SPI_TypeDef;
924 
929 typedef struct
930 {
931  __IO uint32_t CR;
932  __IO uint32_t DCR;
933  __IO uint32_t SR;
934  __IO uint32_t FCR;
935  __IO uint32_t DLR;
936  __IO uint32_t CCR;
937  __IO uint32_t AR;
938  __IO uint32_t ABR;
939  __IO uint32_t DR;
940  __IO uint32_t PSMKR;
941  __IO uint32_t PSMAR;
942  __IO uint32_t PIR;
943  __IO uint32_t LPTR;
944 } QUADSPI_TypeDef;
945 
950 typedef struct
951 {
952  __IO uint32_t CR1;
953  __IO uint32_t CR2;
954  __IO uint32_t SMCR;
955  __IO uint32_t DIER;
956  __IO uint32_t SR;
957  __IO uint32_t EGR;
958  __IO uint32_t CCMR1;
959  __IO uint32_t CCMR2;
960  __IO uint32_t CCER;
961  __IO uint32_t CNT;
962  __IO uint32_t PSC;
963  __IO uint32_t ARR;
964  __IO uint32_t RCR;
965  __IO uint32_t CCR1;
966  __IO uint32_t CCR2;
967  __IO uint32_t CCR3;
968  __IO uint32_t CCR4;
969  __IO uint32_t BDTR;
970  __IO uint32_t DCR;
971  __IO uint32_t DMAR;
972  __IO uint32_t OR;
973 } TIM_TypeDef;
974 
979 typedef struct
980 {
981  __IO uint32_t SR;
982  __IO uint32_t DR;
983  __IO uint32_t BRR;
984  __IO uint32_t CR1;
985  __IO uint32_t CR2;
986  __IO uint32_t CR3;
987  __IO uint32_t GTPR;
988 } USART_TypeDef;
989 
994 typedef struct
995 {
996  __IO uint32_t CR;
997  __IO uint32_t CFR;
998  __IO uint32_t SR;
999 } WWDG_TypeDef;
1000 
1005 typedef struct
1006 {
1007  __IO uint32_t CR;
1008  __IO uint32_t SR;
1009  __IO uint32_t DR;
1010  __IO uint32_t DOUT;
1011  __IO uint32_t DMACR;
1012  __IO uint32_t IMSCR;
1013  __IO uint32_t RISR;
1014  __IO uint32_t MISR;
1015  __IO uint32_t K0LR;
1016  __IO uint32_t K0RR;
1017  __IO uint32_t K1LR;
1018  __IO uint32_t K1RR;
1019  __IO uint32_t K2LR;
1020  __IO uint32_t K2RR;
1021  __IO uint32_t K3LR;
1022  __IO uint32_t K3RR;
1023  __IO uint32_t IV0LR;
1024  __IO uint32_t IV0RR;
1025  __IO uint32_t IV1LR;
1026  __IO uint32_t IV1RR;
1027  __IO uint32_t CSGCMCCM0R;
1028  __IO uint32_t CSGCMCCM1R;
1029  __IO uint32_t CSGCMCCM2R;
1030  __IO uint32_t CSGCMCCM3R;
1031  __IO uint32_t CSGCMCCM4R;
1032  __IO uint32_t CSGCMCCM5R;
1033  __IO uint32_t CSGCMCCM6R;
1034  __IO uint32_t CSGCMCCM7R;
1035  __IO uint32_t CSGCM0R;
1036  __IO uint32_t CSGCM1R;
1037  __IO uint32_t CSGCM2R;
1038  __IO uint32_t CSGCM3R;
1039  __IO uint32_t CSGCM4R;
1040  __IO uint32_t CSGCM5R;
1041  __IO uint32_t CSGCM6R;
1042  __IO uint32_t CSGCM7R;
1043 } CRYP_TypeDef;
1044 
1049 typedef struct
1050 {
1051  __IO uint32_t CR;
1052  __IO uint32_t DIN;
1053  __IO uint32_t STR;
1054  __IO uint32_t HR[5];
1055  __IO uint32_t IMR;
1056  __IO uint32_t SR;
1057  uint32_t RESERVED[52];
1058  __IO uint32_t CSR[54];
1059 } HASH_TypeDef;
1060 
1065 typedef struct
1066 {
1067  __IO uint32_t HR[8];
1068 } HASH_DIGEST_TypeDef;
1069 
1074 typedef struct
1075 {
1076  __IO uint32_t CR;
1077  __IO uint32_t SR;
1078  __IO uint32_t DR;
1079 } RNG_TypeDef;
1080 
1081 
1085 typedef struct
1086 {
1087  __IO uint32_t GOTGCTL;
1088  __IO uint32_t GOTGINT;
1089  __IO uint32_t GAHBCFG;
1090  __IO uint32_t GUSBCFG;
1091  __IO uint32_t GRSTCTL;
1092  __IO uint32_t GINTSTS;
1093  __IO uint32_t GINTMSK;
1094  __IO uint32_t GRXSTSR;
1095  __IO uint32_t GRXSTSP;
1096  __IO uint32_t GRXFSIZ;
1097  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1098  __IO uint32_t HNPTXSTS;
1099  uint32_t Reserved30[2];
1100  __IO uint32_t GCCFG;
1101  __IO uint32_t CID;
1102  uint32_t Reserved5[3];
1103  __IO uint32_t GHWCFG3;
1104  uint32_t Reserved6;
1105  __IO uint32_t GLPMCFG;
1106  uint32_t Reserved;
1107  __IO uint32_t GDFIFOCFG;
1108  uint32_t Reserved43[40];
1109  __IO uint32_t HPTXFSIZ;
1110  __IO uint32_t DIEPTXF[0x0F];
1111 } USB_OTG_GlobalTypeDef;
1112 
1116 typedef struct
1117 {
1118  __IO uint32_t DCFG;
1119  __IO uint32_t DCTL;
1120  __IO uint32_t DSTS;
1121  uint32_t Reserved0C;
1122  __IO uint32_t DIEPMSK;
1123  __IO uint32_t DOEPMSK;
1124  __IO uint32_t DAINT;
1125  __IO uint32_t DAINTMSK;
1126  uint32_t Reserved20;
1127  uint32_t Reserved9;
1128  __IO uint32_t DVBUSDIS;
1129  __IO uint32_t DVBUSPULSE;
1130  __IO uint32_t DTHRCTL;
1131  __IO uint32_t DIEPEMPMSK;
1132  __IO uint32_t DEACHINT;
1133  __IO uint32_t DEACHMSK;
1134  uint32_t Reserved40;
1135  __IO uint32_t DINEP1MSK;
1136  uint32_t Reserved44[15];
1137  __IO uint32_t DOUTEP1MSK;
1138 } USB_OTG_DeviceTypeDef;
1139 
1143 typedef struct
1144 {
1145  __IO uint32_t DIEPCTL;
1146  uint32_t Reserved04;
1147  __IO uint32_t DIEPINT;
1148  uint32_t Reserved0C;
1149  __IO uint32_t DIEPTSIZ;
1150  __IO uint32_t DIEPDMA;
1151  __IO uint32_t DTXFSTS;
1152  uint32_t Reserved18;
1153 } USB_OTG_INEndpointTypeDef;
1154 
1158 typedef struct
1159 {
1160  __IO uint32_t DOEPCTL;
1161  uint32_t Reserved04;
1162  __IO uint32_t DOEPINT;
1163  uint32_t Reserved0C;
1164  __IO uint32_t DOEPTSIZ;
1165  __IO uint32_t DOEPDMA;
1166  uint32_t Reserved18[2];
1167 } USB_OTG_OUTEndpointTypeDef;
1168 
1172 typedef struct
1173 {
1174  __IO uint32_t HCFG;
1175  __IO uint32_t HFIR;
1176  __IO uint32_t HFNUM;
1177  uint32_t Reserved40C;
1178  __IO uint32_t HPTXSTS;
1179  __IO uint32_t HAINT;
1180  __IO uint32_t HAINTMSK;
1181 } USB_OTG_HostTypeDef;
1182 
1186 typedef struct
1187 {
1188  __IO uint32_t HCCHAR;
1189  __IO uint32_t HCSPLT;
1190  __IO uint32_t HCINT;
1191  __IO uint32_t HCINTMSK;
1192  __IO uint32_t HCTSIZ;
1193  __IO uint32_t HCDMA;
1194  uint32_t Reserved[2];
1195 } USB_OTG_HostChannelTypeDef;
1196 
1204 #define FLASH_BASE 0x08000000U
1205 #define CCMDATARAM_BASE 0x10000000U
1206 #define SRAM1_BASE 0x20000000U
1207 #define SRAM2_BASE 0x20028000U
1208 #define SRAM3_BASE 0x20030000U
1209 #define PERIPH_BASE 0x40000000U
1210 #define BKPSRAM_BASE 0x40024000U
1211 #define FMC_R_BASE 0xA0000000U
1212 #define QSPI_R_BASE 0xA0001000U
1213 #define SRAM1_BB_BASE 0x22000000U
1214 #define SRAM2_BB_BASE 0x22500000U
1215 #define SRAM3_BB_BASE 0x22600000U
1216 #define PERIPH_BB_BASE 0x42000000U
1217 #define BKPSRAM_BB_BASE 0x42480000U
1218 #define FLASH_END 0x081FFFFFU
1219 #define CCMDATARAM_END 0x1000FFFFU
1221 /* Legacy defines */
1222 #define SRAM_BASE SRAM1_BASE
1223 #define SRAM_BB_BASE SRAM1_BB_BASE
1224 
1225 
1227 #define APB1PERIPH_BASE PERIPH_BASE
1228 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1229 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1230 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1231 
1233 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1234 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1235 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1236 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1237 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1238 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1239 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1240 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1241 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1242 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1243 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1244 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1245 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1246 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1247 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1248 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1249 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1250 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1251 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1252 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1253 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1254 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1255 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1256 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1257 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1258 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1259 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1260 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1261 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1262 
1264 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1265 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1266 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1267 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1268 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1269 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1270 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1271 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1272 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1273 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1274 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1275 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1276 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1277 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1278 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1279 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1280 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1281 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1282 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1283 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1284 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1285 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1286 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1287 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1288 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
1289 
1291 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1292 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1293 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1294 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1295 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1296 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1297 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1298 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1299 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1300 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1301 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1302 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1303 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1304 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1305 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1306 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1307 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1308 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1309 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1310 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1311 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1312 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1313 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1314 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1315 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1316 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1317 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1318 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1319 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1320 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1321 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1322 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1323 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1324 #define ETH_MAC_BASE (ETH_BASE)
1325 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1326 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1327 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1328 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1329 
1331 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1332 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1333 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1334 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1335 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1336 
1338 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1339 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1340 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1341 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1342 
1344 #define DBGMCU_BASE 0xE0042000U
1345 
1347 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1348 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1349 
1350 #define USB_OTG_GLOBAL_BASE 0x000U
1351 #define USB_OTG_DEVICE_BASE 0x800U
1352 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1353 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1354 #define USB_OTG_EP_REG_SIZE 0x20U
1355 #define USB_OTG_HOST_BASE 0x400U
1356 #define USB_OTG_HOST_PORT_BASE 0x440U
1357 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1358 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1359 #define USB_OTG_PCGCCTL_BASE 0xE00U
1360 #define USB_OTG_FIFO_BASE 0x1000U
1361 #define USB_OTG_FIFO_SIZE 0x1000U
1362 
1370 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1371 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1372 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1373 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1374 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1375 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1376 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1377 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1378 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1379 #define RTC ((RTC_TypeDef *) RTC_BASE)
1380 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1381 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1382 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1383 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1384 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1385 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1386 #define USART2 ((USART_TypeDef *) USART2_BASE)
1387 #define USART3 ((USART_TypeDef *) USART3_BASE)
1388 #define UART4 ((USART_TypeDef *) UART4_BASE)
1389 #define UART5 ((USART_TypeDef *) UART5_BASE)
1390 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1391 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1392 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1393 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1394 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1395 #define PWR ((PWR_TypeDef *) PWR_BASE)
1396 #define DAC ((DAC_TypeDef *) DAC_BASE)
1397 #define UART7 ((USART_TypeDef *) UART7_BASE)
1398 #define UART8 ((USART_TypeDef *) UART8_BASE)
1399 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1400 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1401 #define USART1 ((USART_TypeDef *) USART1_BASE)
1402 #define USART6 ((USART_TypeDef *) USART6_BASE)
1403 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1404 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1405 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1406 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1407 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1408 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1409 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1410 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1411 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1412 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1413 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1414 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1415 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1416 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1417 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1418 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1419 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1420 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1421 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1422 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1423 #define DSI ((DSI_TypeDef *)DSI_BASE)
1424 
1425 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1426 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1427 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1428 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1429 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1430 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1431 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1432 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1433 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1434 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1435 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1436 #define CRC ((CRC_TypeDef *) CRC_BASE)
1437 #define RCC ((RCC_TypeDef *) RCC_BASE)
1438 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1439 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1440 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1441 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1442 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1443 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1444 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1445 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1446 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1447 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1448 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1449 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1450 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1451 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1452 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1453 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1454 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1455 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1456 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1457 #define ETH ((ETH_TypeDef *) ETH_BASE)
1458 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1459 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1460 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1461 #define HASH ((HASH_TypeDef *) HASH_BASE)
1462 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1463 #define RNG ((RNG_TypeDef *) RNG_BASE)
1464 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1465 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1466 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1467 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1468 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1469 
1470 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1471 
1472 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1473 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1474 
1487 /******************************************************************************/
1488 /* Peripheral Registers_Bits_Definition */
1489 /******************************************************************************/
1490 
1491 /******************************************************************************/
1492 /* */
1493 /* Analog to Digital Converter */
1494 /* */
1495 /******************************************************************************/
1496 /******************** Bit definition for ADC_SR register ********************/
1497 #define ADC_SR_AWD 0x00000001U
1498 #define ADC_SR_EOC 0x00000002U
1499 #define ADC_SR_JEOC 0x00000004U
1500 #define ADC_SR_JSTRT 0x00000008U
1501 #define ADC_SR_STRT 0x00000010U
1502 #define ADC_SR_OVR 0x00000020U
1504 /******************* Bit definition for ADC_CR1 register ********************/
1505 #define ADC_CR1_AWDCH 0x0000001FU
1506 #define ADC_CR1_AWDCH_0 0x00000001U
1507 #define ADC_CR1_AWDCH_1 0x00000002U
1508 #define ADC_CR1_AWDCH_2 0x00000004U
1509 #define ADC_CR1_AWDCH_3 0x00000008U
1510 #define ADC_CR1_AWDCH_4 0x00000010U
1511 #define ADC_CR1_EOCIE 0x00000020U
1512 #define ADC_CR1_AWDIE 0x00000040U
1513 #define ADC_CR1_JEOCIE 0x00000080U
1514 #define ADC_CR1_SCAN 0x00000100U
1515 #define ADC_CR1_AWDSGL 0x00000200U
1516 #define ADC_CR1_JAUTO 0x00000400U
1517 #define ADC_CR1_DISCEN 0x00000800U
1518 #define ADC_CR1_JDISCEN 0x00001000U
1519 #define ADC_CR1_DISCNUM 0x0000E000U
1520 #define ADC_CR1_DISCNUM_0 0x00002000U
1521 #define ADC_CR1_DISCNUM_1 0x00004000U
1522 #define ADC_CR1_DISCNUM_2 0x00008000U
1523 #define ADC_CR1_JAWDEN 0x00400000U
1524 #define ADC_CR1_AWDEN 0x00800000U
1525 #define ADC_CR1_RES 0x03000000U
1526 #define ADC_CR1_RES_0 0x01000000U
1527 #define ADC_CR1_RES_1 0x02000000U
1528 #define ADC_CR1_OVRIE 0x04000000U
1530 /******************* Bit definition for ADC_CR2 register ********************/
1531 #define ADC_CR2_ADON 0x00000001U
1532 #define ADC_CR2_CONT 0x00000002U
1533 #define ADC_CR2_DMA 0x00000100U
1534 #define ADC_CR2_DDS 0x00000200U
1535 #define ADC_CR2_EOCS 0x00000400U
1536 #define ADC_CR2_ALIGN 0x00000800U
1537 #define ADC_CR2_JEXTSEL 0x000F0000U
1538 #define ADC_CR2_JEXTSEL_0 0x00010000U
1539 #define ADC_CR2_JEXTSEL_1 0x00020000U
1540 #define ADC_CR2_JEXTSEL_2 0x00040000U
1541 #define ADC_CR2_JEXTSEL_3 0x00080000U
1542 #define ADC_CR2_JEXTEN 0x00300000U
1543 #define ADC_CR2_JEXTEN_0 0x00100000U
1544 #define ADC_CR2_JEXTEN_1 0x00200000U
1545 #define ADC_CR2_JSWSTART 0x00400000U
1546 #define ADC_CR2_EXTSEL 0x0F000000U
1547 #define ADC_CR2_EXTSEL_0 0x01000000U
1548 #define ADC_CR2_EXTSEL_1 0x02000000U
1549 #define ADC_CR2_EXTSEL_2 0x04000000U
1550 #define ADC_CR2_EXTSEL_3 0x08000000U
1551 #define ADC_CR2_EXTEN 0x30000000U
1552 #define ADC_CR2_EXTEN_0 0x10000000U
1553 #define ADC_CR2_EXTEN_1 0x20000000U
1554 #define ADC_CR2_SWSTART 0x40000000U
1556 /****************** Bit definition for ADC_SMPR1 register *******************/
1557 #define ADC_SMPR1_SMP10 0x00000007U
1558 #define ADC_SMPR1_SMP10_0 0x00000001U
1559 #define ADC_SMPR1_SMP10_1 0x00000002U
1560 #define ADC_SMPR1_SMP10_2 0x00000004U
1561 #define ADC_SMPR1_SMP11 0x00000038U
1562 #define ADC_SMPR1_SMP11_0 0x00000008U
1563 #define ADC_SMPR1_SMP11_1 0x00000010U
1564 #define ADC_SMPR1_SMP11_2 0x00000020U
1565 #define ADC_SMPR1_SMP12 0x000001C0U
1566 #define ADC_SMPR1_SMP12_0 0x00000040U
1567 #define ADC_SMPR1_SMP12_1 0x00000080U
1568 #define ADC_SMPR1_SMP12_2 0x00000100U
1569 #define ADC_SMPR1_SMP13 0x00000E00U
1570 #define ADC_SMPR1_SMP13_0 0x00000200U
1571 #define ADC_SMPR1_SMP13_1 0x00000400U
1572 #define ADC_SMPR1_SMP13_2 0x00000800U
1573 #define ADC_SMPR1_SMP14 0x00007000U
1574 #define ADC_SMPR1_SMP14_0 0x00001000U
1575 #define ADC_SMPR1_SMP14_1 0x00002000U
1576 #define ADC_SMPR1_SMP14_2 0x00004000U
1577 #define ADC_SMPR1_SMP15 0x00038000U
1578 #define ADC_SMPR1_SMP15_0 0x00008000U
1579 #define ADC_SMPR1_SMP15_1 0x00010000U
1580 #define ADC_SMPR1_SMP15_2 0x00020000U
1581 #define ADC_SMPR1_SMP16 0x001C0000U
1582 #define ADC_SMPR1_SMP16_0 0x00040000U
1583 #define ADC_SMPR1_SMP16_1 0x00080000U
1584 #define ADC_SMPR1_SMP16_2 0x00100000U
1585 #define ADC_SMPR1_SMP17 0x00E00000U
1586 #define ADC_SMPR1_SMP17_0 0x00200000U
1587 #define ADC_SMPR1_SMP17_1 0x00400000U
1588 #define ADC_SMPR1_SMP17_2 0x00800000U
1589 #define ADC_SMPR1_SMP18 0x07000000U
1590 #define ADC_SMPR1_SMP18_0 0x01000000U
1591 #define ADC_SMPR1_SMP18_1 0x02000000U
1592 #define ADC_SMPR1_SMP18_2 0x04000000U
1594 /****************** Bit definition for ADC_SMPR2 register *******************/
1595 #define ADC_SMPR2_SMP0 0x00000007U
1596 #define ADC_SMPR2_SMP0_0 0x00000001U
1597 #define ADC_SMPR2_SMP0_1 0x00000002U
1598 #define ADC_SMPR2_SMP0_2 0x00000004U
1599 #define ADC_SMPR2_SMP1 0x00000038U
1600 #define ADC_SMPR2_SMP1_0 0x00000008U
1601 #define ADC_SMPR2_SMP1_1 0x00000010U
1602 #define ADC_SMPR2_SMP1_2 0x00000020U
1603 #define ADC_SMPR2_SMP2 0x000001C0U
1604 #define ADC_SMPR2_SMP2_0 0x00000040U
1605 #define ADC_SMPR2_SMP2_1 0x00000080U
1606 #define ADC_SMPR2_SMP2_2 0x00000100U
1607 #define ADC_SMPR2_SMP3 0x00000E00U
1608 #define ADC_SMPR2_SMP3_0 0x00000200U
1609 #define ADC_SMPR2_SMP3_1 0x00000400U
1610 #define ADC_SMPR2_SMP3_2 0x00000800U
1611 #define ADC_SMPR2_SMP4 0x00007000U
1612 #define ADC_SMPR2_SMP4_0 0x00001000U
1613 #define ADC_SMPR2_SMP4_1 0x00002000U
1614 #define ADC_SMPR2_SMP4_2 0x00004000U
1615 #define ADC_SMPR2_SMP5 0x00038000U
1616 #define ADC_SMPR2_SMP5_0 0x00008000U
1617 #define ADC_SMPR2_SMP5_1 0x00010000U
1618 #define ADC_SMPR2_SMP5_2 0x00020000U
1619 #define ADC_SMPR2_SMP6 0x001C0000U
1620 #define ADC_SMPR2_SMP6_0 0x00040000U
1621 #define ADC_SMPR2_SMP6_1 0x00080000U
1622 #define ADC_SMPR2_SMP6_2 0x00100000U
1623 #define ADC_SMPR2_SMP7 0x00E00000U
1624 #define ADC_SMPR2_SMP7_0 0x00200000U
1625 #define ADC_SMPR2_SMP7_1 0x00400000U
1626 #define ADC_SMPR2_SMP7_2 0x00800000U
1627 #define ADC_SMPR2_SMP8 0x07000000U
1628 #define ADC_SMPR2_SMP8_0 0x01000000U
1629 #define ADC_SMPR2_SMP8_1 0x02000000U
1630 #define ADC_SMPR2_SMP8_2 0x04000000U
1631 #define ADC_SMPR2_SMP9 0x38000000U
1632 #define ADC_SMPR2_SMP9_0 0x08000000U
1633 #define ADC_SMPR2_SMP9_1 0x10000000U
1634 #define ADC_SMPR2_SMP9_2 0x20000000U
1636 /****************** Bit definition for ADC_JOFR1 register *******************/
1637 #define ADC_JOFR1_JOFFSET1 0x0FFFU
1639 /****************** Bit definition for ADC_JOFR2 register *******************/
1640 #define ADC_JOFR2_JOFFSET2 0x0FFFU
1642 /****************** Bit definition for ADC_JOFR3 register *******************/
1643 #define ADC_JOFR3_JOFFSET3 0x0FFFU
1645 /****************** Bit definition for ADC_JOFR4 register *******************/
1646 #define ADC_JOFR4_JOFFSET4 0x0FFFU
1648 /******************* Bit definition for ADC_HTR register ********************/
1649 #define ADC_HTR_HT 0x0FFFU
1651 /******************* Bit definition for ADC_LTR register ********************/
1652 #define ADC_LTR_LT 0x0FFFU
1654 /******************* Bit definition for ADC_SQR1 register *******************/
1655 #define ADC_SQR1_SQ13 0x0000001FU
1656 #define ADC_SQR1_SQ13_0 0x00000001U
1657 #define ADC_SQR1_SQ13_1 0x00000002U
1658 #define ADC_SQR1_SQ13_2 0x00000004U
1659 #define ADC_SQR1_SQ13_3 0x00000008U
1660 #define ADC_SQR1_SQ13_4 0x00000010U
1661 #define ADC_SQR1_SQ14 0x000003E0U
1662 #define ADC_SQR1_SQ14_0 0x00000020U
1663 #define ADC_SQR1_SQ14_1 0x00000040U
1664 #define ADC_SQR1_SQ14_2 0x00000080U
1665 #define ADC_SQR1_SQ14_3 0x00000100U
1666 #define ADC_SQR1_SQ14_4 0x00000200U
1667 #define ADC_SQR1_SQ15 0x00007C00U
1668 #define ADC_SQR1_SQ15_0 0x00000400U
1669 #define ADC_SQR1_SQ15_1 0x00000800U
1670 #define ADC_SQR1_SQ15_2 0x00001000U
1671 #define ADC_SQR1_SQ15_3 0x00002000U
1672 #define ADC_SQR1_SQ15_4 0x00004000U
1673 #define ADC_SQR1_SQ16 0x000F8000U
1674 #define ADC_SQR1_SQ16_0 0x00008000U
1675 #define ADC_SQR1_SQ16_1 0x00010000U
1676 #define ADC_SQR1_SQ16_2 0x00020000U
1677 #define ADC_SQR1_SQ16_3 0x00040000U
1678 #define ADC_SQR1_SQ16_4 0x00080000U
1679 #define ADC_SQR1_L 0x00F00000U
1680 #define ADC_SQR1_L_0 0x00100000U
1681 #define ADC_SQR1_L_1 0x00200000U
1682 #define ADC_SQR1_L_2 0x00400000U
1683 #define ADC_SQR1_L_3 0x00800000U
1685 /******************* Bit definition for ADC_SQR2 register *******************/
1686 #define ADC_SQR2_SQ7 0x0000001FU
1687 #define ADC_SQR2_SQ7_0 0x00000001U
1688 #define ADC_SQR2_SQ7_1 0x00000002U
1689 #define ADC_SQR2_SQ7_2 0x00000004U
1690 #define ADC_SQR2_SQ7_3 0x00000008U
1691 #define ADC_SQR2_SQ7_4 0x00000010U
1692 #define ADC_SQR2_SQ8 0x000003E0U
1693 #define ADC_SQR2_SQ8_0 0x00000020U
1694 #define ADC_SQR2_SQ8_1 0x00000040U
1695 #define ADC_SQR2_SQ8_2 0x00000080U
1696 #define ADC_SQR2_SQ8_3 0x00000100U
1697 #define ADC_SQR2_SQ8_4 0x00000200U
1698 #define ADC_SQR2_SQ9 0x00007C00U
1699 #define ADC_SQR2_SQ9_0 0x00000400U
1700 #define ADC_SQR2_SQ9_1 0x00000800U
1701 #define ADC_SQR2_SQ9_2 0x00001000U
1702 #define ADC_SQR2_SQ9_3 0x00002000U
1703 #define ADC_SQR2_SQ9_4 0x00004000U
1704 #define ADC_SQR2_SQ10 0x000F8000U
1705 #define ADC_SQR2_SQ10_0 0x00008000U
1706 #define ADC_SQR2_SQ10_1 0x00010000U
1707 #define ADC_SQR2_SQ10_2 0x00020000U
1708 #define ADC_SQR2_SQ10_3 0x00040000U
1709 #define ADC_SQR2_SQ10_4 0x00080000U
1710 #define ADC_SQR2_SQ11 0x01F00000U
1711 #define ADC_SQR2_SQ11_0 0x00100000U
1712 #define ADC_SQR2_SQ11_1 0x00200000U
1713 #define ADC_SQR2_SQ11_2 0x00400000U
1714 #define ADC_SQR2_SQ11_3 0x00800000U
1715 #define ADC_SQR2_SQ11_4 0x01000000U
1716 #define ADC_SQR2_SQ12 0x3E000000U
1717 #define ADC_SQR2_SQ12_0 0x02000000U
1718 #define ADC_SQR2_SQ12_1 0x04000000U
1719 #define ADC_SQR2_SQ12_2 0x08000000U
1720 #define ADC_SQR2_SQ12_3 0x10000000U
1721 #define ADC_SQR2_SQ12_4 0x20000000U
1723 /******************* Bit definition for ADC_SQR3 register *******************/
1724 #define ADC_SQR3_SQ1 0x0000001FU
1725 #define ADC_SQR3_SQ1_0 0x00000001U
1726 #define ADC_SQR3_SQ1_1 0x00000002U
1727 #define ADC_SQR3_SQ1_2 0x00000004U
1728 #define ADC_SQR3_SQ1_3 0x00000008U
1729 #define ADC_SQR3_SQ1_4 0x00000010U
1730 #define ADC_SQR3_SQ2 0x000003E0U
1731 #define ADC_SQR3_SQ2_0 0x00000020U
1732 #define ADC_SQR3_SQ2_1 0x00000040U
1733 #define ADC_SQR3_SQ2_2 0x00000080U
1734 #define ADC_SQR3_SQ2_3 0x00000100U
1735 #define ADC_SQR3_SQ2_4 0x00000200U
1736 #define ADC_SQR3_SQ3 0x00007C00U
1737 #define ADC_SQR3_SQ3_0 0x00000400U
1738 #define ADC_SQR3_SQ3_1 0x00000800U
1739 #define ADC_SQR3_SQ3_2 0x00001000U
1740 #define ADC_SQR3_SQ3_3 0x00002000U
1741 #define ADC_SQR3_SQ3_4 0x00004000U
1742 #define ADC_SQR3_SQ4 0x000F8000U
1743 #define ADC_SQR3_SQ4_0 0x00008000U
1744 #define ADC_SQR3_SQ4_1 0x00010000U
1745 #define ADC_SQR3_SQ4_2 0x00020000U
1746 #define ADC_SQR3_SQ4_3 0x00040000U
1747 #define ADC_SQR3_SQ4_4 0x00080000U
1748 #define ADC_SQR3_SQ5 0x01F00000U
1749 #define ADC_SQR3_SQ5_0 0x00100000U
1750 #define ADC_SQR3_SQ5_1 0x00200000U
1751 #define ADC_SQR3_SQ5_2 0x00400000U
1752 #define ADC_SQR3_SQ5_3 0x00800000U
1753 #define ADC_SQR3_SQ5_4 0x01000000U
1754 #define ADC_SQR3_SQ6 0x3E000000U
1755 #define ADC_SQR3_SQ6_0 0x02000000U
1756 #define ADC_SQR3_SQ6_1 0x04000000U
1757 #define ADC_SQR3_SQ6_2 0x08000000U
1758 #define ADC_SQR3_SQ6_3 0x10000000U
1759 #define ADC_SQR3_SQ6_4 0x20000000U
1761 /******************* Bit definition for ADC_JSQR register *******************/
1762 #define ADC_JSQR_JSQ1 0x0000001FU
1763 #define ADC_JSQR_JSQ1_0 0x00000001U
1764 #define ADC_JSQR_JSQ1_1 0x00000002U
1765 #define ADC_JSQR_JSQ1_2 0x00000004U
1766 #define ADC_JSQR_JSQ1_3 0x00000008U
1767 #define ADC_JSQR_JSQ1_4 0x00000010U
1768 #define ADC_JSQR_JSQ2 0x000003E0U
1769 #define ADC_JSQR_JSQ2_0 0x00000020U
1770 #define ADC_JSQR_JSQ2_1 0x00000040U
1771 #define ADC_JSQR_JSQ2_2 0x00000080U
1772 #define ADC_JSQR_JSQ2_3 0x00000100U
1773 #define ADC_JSQR_JSQ2_4 0x00000200U
1774 #define ADC_JSQR_JSQ3 0x00007C00U
1775 #define ADC_JSQR_JSQ3_0 0x00000400U
1776 #define ADC_JSQR_JSQ3_1 0x00000800U
1777 #define ADC_JSQR_JSQ3_2 0x00001000U
1778 #define ADC_JSQR_JSQ3_3 0x00002000U
1779 #define ADC_JSQR_JSQ3_4 0x00004000U
1780 #define ADC_JSQR_JSQ4 0x000F8000U
1781 #define ADC_JSQR_JSQ4_0 0x00008000U
1782 #define ADC_JSQR_JSQ4_1 0x00010000U
1783 #define ADC_JSQR_JSQ4_2 0x00020000U
1784 #define ADC_JSQR_JSQ4_3 0x00040000U
1785 #define ADC_JSQR_JSQ4_4 0x00080000U
1786 #define ADC_JSQR_JL 0x00300000U
1787 #define ADC_JSQR_JL_0 0x00100000U
1788 #define ADC_JSQR_JL_1 0x00200000U
1790 /******************* Bit definition for ADC_JDR1 register *******************/
1791 #define ADC_JDR1_JDATA 0xFFFFU
1793 /******************* Bit definition for ADC_JDR2 register *******************/
1794 #define ADC_JDR2_JDATA 0xFFFFU
1796 /******************* Bit definition for ADC_JDR3 register *******************/
1797 #define ADC_JDR3_JDATA 0xFFFFU
1799 /******************* Bit definition for ADC_JDR4 register *******************/
1800 #define ADC_JDR4_JDATA 0xFFFFU
1802 /******************** Bit definition for ADC_DR register ********************/
1803 #define ADC_DR_DATA 0x0000FFFFU
1804 #define ADC_DR_ADC2DATA 0xFFFF0000U
1806 /******************* Bit definition for ADC_CSR register ********************/
1807 #define ADC_CSR_AWD1 0x00000001U
1808 #define ADC_CSR_EOC1 0x00000002U
1809 #define ADC_CSR_JEOC1 0x00000004U
1810 #define ADC_CSR_JSTRT1 0x00000008U
1811 #define ADC_CSR_STRT1 0x00000010U
1812 #define ADC_CSR_OVR1 0x00000020U
1813 #define ADC_CSR_AWD2 0x00000100U
1814 #define ADC_CSR_EOC2 0x00000200U
1815 #define ADC_CSR_JEOC2 0x00000400U
1816 #define ADC_CSR_JSTRT2 0x00000800U
1817 #define ADC_CSR_STRT2 0x00001000U
1818 #define ADC_CSR_OVR2 0x00002000U
1819 #define ADC_CSR_AWD3 0x00010000U
1820 #define ADC_CSR_EOC3 0x00020000U
1821 #define ADC_CSR_JEOC3 0x00040000U
1822 #define ADC_CSR_JSTRT3 0x00080000U
1823 #define ADC_CSR_STRT3 0x00100000U
1824 #define ADC_CSR_OVR3 0x00200000U
1826 /* Legacy defines */
1827 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1828 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1829 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1830 
1831 /******************* Bit definition for ADC_CCR register ********************/
1832 #define ADC_CCR_MULTI 0x0000001FU
1833 #define ADC_CCR_MULTI_0 0x00000001U
1834 #define ADC_CCR_MULTI_1 0x00000002U
1835 #define ADC_CCR_MULTI_2 0x00000004U
1836 #define ADC_CCR_MULTI_3 0x00000008U
1837 #define ADC_CCR_MULTI_4 0x00000010U
1838 #define ADC_CCR_DELAY 0x00000F00U
1839 #define ADC_CCR_DELAY_0 0x00000100U
1840 #define ADC_CCR_DELAY_1 0x00000200U
1841 #define ADC_CCR_DELAY_2 0x00000400U
1842 #define ADC_CCR_DELAY_3 0x00000800U
1843 #define ADC_CCR_DDS 0x00002000U
1844 #define ADC_CCR_DMA 0x0000C000U
1845 #define ADC_CCR_DMA_0 0x00004000U
1846 #define ADC_CCR_DMA_1 0x00008000U
1847 #define ADC_CCR_ADCPRE 0x00030000U
1848 #define ADC_CCR_ADCPRE_0 0x00010000U
1849 #define ADC_CCR_ADCPRE_1 0x00020000U
1850 #define ADC_CCR_VBATE 0x00400000U
1851 #define ADC_CCR_TSVREFE 0x00800000U
1853 /******************* Bit definition for ADC_CDR register ********************/
1854 #define ADC_CDR_DATA1 0x0000FFFFU
1855 #define ADC_CDR_DATA2 0xFFFF0000U
1857 /******************************************************************************/
1858 /* */
1859 /* Controller Area Network */
1860 /* */
1861 /******************************************************************************/
1863 /******************* Bit definition for CAN_MCR register ********************/
1864 #define CAN_MCR_INRQ 0x00000001U
1865 #define CAN_MCR_SLEEP 0x00000002U
1866 #define CAN_MCR_TXFP 0x00000004U
1867 #define CAN_MCR_RFLM 0x00000008U
1868 #define CAN_MCR_NART 0x00000010U
1869 #define CAN_MCR_AWUM 0x00000020U
1870 #define CAN_MCR_ABOM 0x00000040U
1871 #define CAN_MCR_TTCM 0x00000080U
1872 #define CAN_MCR_RESET 0x00008000U
1873 #define CAN_MCR_DBF 0x00010000U
1874 /******************* Bit definition for CAN_MSR register ********************/
1875 #define CAN_MSR_INAK 0x0001U
1876 #define CAN_MSR_SLAK 0x0002U
1877 #define CAN_MSR_ERRI 0x0004U
1878 #define CAN_MSR_WKUI 0x0008U
1879 #define CAN_MSR_SLAKI 0x0010U
1880 #define CAN_MSR_TXM 0x0100U
1881 #define CAN_MSR_RXM 0x0200U
1882 #define CAN_MSR_SAMP 0x0400U
1883 #define CAN_MSR_RX 0x0800U
1885 /******************* Bit definition for CAN_TSR register ********************/
1886 #define CAN_TSR_RQCP0 0x00000001U
1887 #define CAN_TSR_TXOK0 0x00000002U
1888 #define CAN_TSR_ALST0 0x00000004U
1889 #define CAN_TSR_TERR0 0x00000008U
1890 #define CAN_TSR_ABRQ0 0x00000080U
1891 #define CAN_TSR_RQCP1 0x00000100U
1892 #define CAN_TSR_TXOK1 0x00000200U
1893 #define CAN_TSR_ALST1 0x00000400U
1894 #define CAN_TSR_TERR1 0x00000800U
1895 #define CAN_TSR_ABRQ1 0x00008000U
1896 #define CAN_TSR_RQCP2 0x00010000U
1897 #define CAN_TSR_TXOK2 0x00020000U
1898 #define CAN_TSR_ALST2 0x00040000U
1899 #define CAN_TSR_TERR2 0x00080000U
1900 #define CAN_TSR_ABRQ2 0x00800000U
1901 #define CAN_TSR_CODE 0x03000000U
1903 #define CAN_TSR_TME 0x1C000000U
1904 #define CAN_TSR_TME0 0x04000000U
1905 #define CAN_TSR_TME1 0x08000000U
1906 #define CAN_TSR_TME2 0x10000000U
1908 #define CAN_TSR_LOW 0xE0000000U
1909 #define CAN_TSR_LOW0 0x20000000U
1910 #define CAN_TSR_LOW1 0x40000000U
1911 #define CAN_TSR_LOW2 0x80000000U
1913 /******************* Bit definition for CAN_RF0R register *******************/
1914 #define CAN_RF0R_FMP0 0x03U
1915 #define CAN_RF0R_FULL0 0x08U
1916 #define CAN_RF0R_FOVR0 0x10U
1917 #define CAN_RF0R_RFOM0 0x20U
1919 /******************* Bit definition for CAN_RF1R register *******************/
1920 #define CAN_RF1R_FMP1 0x03U
1921 #define CAN_RF1R_FULL1 0x08U
1922 #define CAN_RF1R_FOVR1 0x10U
1923 #define CAN_RF1R_RFOM1 0x20U
1925 /******************** Bit definition for CAN_IER register *******************/
1926 #define CAN_IER_TMEIE 0x00000001U
1927 #define CAN_IER_FMPIE0 0x00000002U
1928 #define CAN_IER_FFIE0 0x00000004U
1929 #define CAN_IER_FOVIE0 0x00000008U
1930 #define CAN_IER_FMPIE1 0x00000010U
1931 #define CAN_IER_FFIE1 0x00000020U
1932 #define CAN_IER_FOVIE1 0x00000040U
1933 #define CAN_IER_EWGIE 0x00000100U
1934 #define CAN_IER_EPVIE 0x00000200U
1935 #define CAN_IER_BOFIE 0x00000400U
1936 #define CAN_IER_LECIE 0x00000800U
1937 #define CAN_IER_ERRIE 0x00008000U
1938 #define CAN_IER_WKUIE 0x00010000U
1939 #define CAN_IER_SLKIE 0x00020000U
1940 #define CAN_IER_EWGIE 0x00000100U
1941 #define CAN_IER_EPVIE 0x00000200U
1942 #define CAN_IER_BOFIE 0x00000400U
1943 #define CAN_IER_LECIE 0x00000800U
1944 #define CAN_IER_ERRIE 0x00008000U
1947 /******************** Bit definition for CAN_ESR register *******************/
1948 #define CAN_ESR_EWGF 0x00000001U
1949 #define CAN_ESR_EPVF 0x00000002U
1950 #define CAN_ESR_BOFF 0x00000004U
1952 #define CAN_ESR_LEC 0x00000070U
1953 #define CAN_ESR_LEC_0 0x00000010U
1954 #define CAN_ESR_LEC_1 0x00000020U
1955 #define CAN_ESR_LEC_2 0x00000040U
1957 #define CAN_ESR_TEC 0x00FF0000U
1958 #define CAN_ESR_REC 0xFF000000U
1960 /******************* Bit definition for CAN_BTR register ********************/
1961 #define CAN_BTR_BRP 0x000003FFU
1962 #define CAN_BTR_TS1 0x000F0000U
1963 #define CAN_BTR_TS1_0 0x00010000U
1964 #define CAN_BTR_TS1_1 0x00020000U
1965 #define CAN_BTR_TS1_2 0x00040000U
1966 #define CAN_BTR_TS1_3 0x00080000U
1967 #define CAN_BTR_TS2 0x00700000U
1968 #define CAN_BTR_TS2_0 0x00100000U
1969 #define CAN_BTR_TS2_1 0x00200000U
1970 #define CAN_BTR_TS2_2 0x00400000U
1971 #define CAN_BTR_SJW 0x03000000U
1972 #define CAN_BTR_SJW_0 0x01000000U
1973 #define CAN_BTR_SJW_1 0x02000000U
1974 #define CAN_BTR_LBKM 0x40000000U
1975 #define CAN_BTR_SILM 0x80000000U
1979 /****************** Bit definition for CAN_TI0R register ********************/
1980 #define CAN_TI0R_TXRQ 0x00000001U
1981 #define CAN_TI0R_RTR 0x00000002U
1982 #define CAN_TI0R_IDE 0x00000004U
1983 #define CAN_TI0R_EXID 0x001FFFF8U
1984 #define CAN_TI0R_STID 0xFFE00000U
1986 /****************** Bit definition for CAN_TDT0R register *******************/
1987 #define CAN_TDT0R_DLC 0x0000000FU
1988 #define CAN_TDT0R_TGT 0x00000100U
1989 #define CAN_TDT0R_TIME 0xFFFF0000U
1991 /****************** Bit definition for CAN_TDL0R register *******************/
1992 #define CAN_TDL0R_DATA0 0x000000FFU
1993 #define CAN_TDL0R_DATA1 0x0000FF00U
1994 #define CAN_TDL0R_DATA2 0x00FF0000U
1995 #define CAN_TDL0R_DATA3 0xFF000000U
1997 /****************** Bit definition for CAN_TDH0R register *******************/
1998 #define CAN_TDH0R_DATA4 0x000000FFU
1999 #define CAN_TDH0R_DATA5 0x0000FF00U
2000 #define CAN_TDH0R_DATA6 0x00FF0000U
2001 #define CAN_TDH0R_DATA7 0xFF000000U
2003 /******************* Bit definition for CAN_TI1R register *******************/
2004 #define CAN_TI1R_TXRQ 0x00000001U
2005 #define CAN_TI1R_RTR 0x00000002U
2006 #define CAN_TI1R_IDE 0x00000004U
2007 #define CAN_TI1R_EXID 0x001FFFF8U
2008 #define CAN_TI1R_STID 0xFFE00000U
2010 /******************* Bit definition for CAN_TDT1R register ******************/
2011 #define CAN_TDT1R_DLC 0x0000000FU
2012 #define CAN_TDT1R_TGT 0x00000100U
2013 #define CAN_TDT1R_TIME 0xFFFF0000U
2015 /******************* Bit definition for CAN_TDL1R register ******************/
2016 #define CAN_TDL1R_DATA0 0x000000FFU
2017 #define CAN_TDL1R_DATA1 0x0000FF00U
2018 #define CAN_TDL1R_DATA2 0x00FF0000U
2019 #define CAN_TDL1R_DATA3 0xFF000000U
2021 /******************* Bit definition for CAN_TDH1R register ******************/
2022 #define CAN_TDH1R_DATA4 0x000000FFU
2023 #define CAN_TDH1R_DATA5 0x0000FF00U
2024 #define CAN_TDH1R_DATA6 0x00FF0000U
2025 #define CAN_TDH1R_DATA7 0xFF000000U
2027 /******************* Bit definition for CAN_TI2R register *******************/
2028 #define CAN_TI2R_TXRQ 0x00000001U
2029 #define CAN_TI2R_RTR 0x00000002U
2030 #define CAN_TI2R_IDE 0x00000004U
2031 #define CAN_TI2R_EXID 0x001FFFF8U
2032 #define CAN_TI2R_STID 0xFFE00000U
2034 /******************* Bit definition for CAN_TDT2R register ******************/
2035 #define CAN_TDT2R_DLC 0x0000000FU
2036 #define CAN_TDT2R_TGT 0x00000100U
2037 #define CAN_TDT2R_TIME 0xFFFF0000U
2039 /******************* Bit definition for CAN_TDL2R register ******************/
2040 #define CAN_TDL2R_DATA0 0x000000FFU
2041 #define CAN_TDL2R_DATA1 0x0000FF00U
2042 #define CAN_TDL2R_DATA2 0x00FF0000U
2043 #define CAN_TDL2R_DATA3 0xFF000000U
2045 /******************* Bit definition for CAN_TDH2R register ******************/
2046 #define CAN_TDH2R_DATA4 0x000000FFU
2047 #define CAN_TDH2R_DATA5 0x0000FF00U
2048 #define CAN_TDH2R_DATA6 0x00FF0000U
2049 #define CAN_TDH2R_DATA7 0xFF000000U
2051 /******************* Bit definition for CAN_RI0R register *******************/
2052 #define CAN_RI0R_RTR 0x00000002U
2053 #define CAN_RI0R_IDE 0x00000004U
2054 #define CAN_RI0R_EXID 0x001FFFF8U
2055 #define CAN_RI0R_STID 0xFFE00000U
2057 /******************* Bit definition for CAN_RDT0R register ******************/
2058 #define CAN_RDT0R_DLC 0x0000000FU
2059 #define CAN_RDT0R_FMI 0x0000FF00U
2060 #define CAN_RDT0R_TIME 0xFFFF0000U
2062 /******************* Bit definition for CAN_RDL0R register ******************/
2063 #define CAN_RDL0R_DATA0 0x000000FFU
2064 #define CAN_RDL0R_DATA1 0x0000FF00U
2065 #define CAN_RDL0R_DATA2 0x00FF0000U
2066 #define CAN_RDL0R_DATA3 0xFF000000U
2068 /******************* Bit definition for CAN_RDH0R register ******************/
2069 #define CAN_RDH0R_DATA4 0x000000FFU
2070 #define CAN_RDH0R_DATA5 0x0000FF00U
2071 #define CAN_RDH0R_DATA6 0x00FF0000U
2072 #define CAN_RDH0R_DATA7 0xFF000000U
2074 /******************* Bit definition for CAN_RI1R register *******************/
2075 #define CAN_RI1R_RTR 0x00000002U
2076 #define CAN_RI1R_IDE 0x00000004U
2077 #define CAN_RI1R_EXID 0x001FFFF8U
2078 #define CAN_RI1R_STID 0xFFE00000U
2080 /******************* Bit definition for CAN_RDT1R register ******************/
2081 #define CAN_RDT1R_DLC 0x0000000FU
2082 #define CAN_RDT1R_FMI 0x0000FF00U
2083 #define CAN_RDT1R_TIME 0xFFFF0000U
2085 /******************* Bit definition for CAN_RDL1R register ******************/
2086 #define CAN_RDL1R_DATA0 0x000000FFU
2087 #define CAN_RDL1R_DATA1 0x0000FF00U
2088 #define CAN_RDL1R_DATA2 0x00FF0000U
2089 #define CAN_RDL1R_DATA3 0xFF000000U
2091 /******************* Bit definition for CAN_RDH1R register ******************/
2092 #define CAN_RDH1R_DATA4 0x000000FFU
2093 #define CAN_RDH1R_DATA5 0x0000FF00U
2094 #define CAN_RDH1R_DATA6 0x00FF0000U
2095 #define CAN_RDH1R_DATA7 0xFF000000U
2098 /******************* Bit definition for CAN_FMR register ********************/
2099 #define CAN_FMR_FINIT 0x01U
2100 #define CAN_FMR_CAN2SB 0x00003F00U
2102 /******************* Bit definition for CAN_FM1R register *******************/
2103 #define CAN_FM1R_FBM 0x0FFFFFFFU
2104 #define CAN_FM1R_FBM0 0x00000001U
2105 #define CAN_FM1R_FBM1 0x00000002U
2106 #define CAN_FM1R_FBM2 0x00000004U
2107 #define CAN_FM1R_FBM3 0x00000008U
2108 #define CAN_FM1R_FBM4 0x00000010U
2109 #define CAN_FM1R_FBM5 0x00000020U
2110 #define CAN_FM1R_FBM6 0x00000040U
2111 #define CAN_FM1R_FBM7 0x00000080U
2112 #define CAN_FM1R_FBM8 0x00000100U
2113 #define CAN_FM1R_FBM9 0x00000200U
2114 #define CAN_FM1R_FBM10 0x00000400U
2115 #define CAN_FM1R_FBM11 0x00000800U
2116 #define CAN_FM1R_FBM12 0x00001000U
2117 #define CAN_FM1R_FBM13 0x00002000U
2118 #define CAN_FM1R_FBM14 0x00004000U
2119 #define CAN_FM1R_FBM15 0x00008000U
2120 #define CAN_FM1R_FBM16 0x00010000U
2121 #define CAN_FM1R_FBM17 0x00020000U
2122 #define CAN_FM1R_FBM18 0x00040000U
2123 #define CAN_FM1R_FBM19 0x00080000U
2124 #define CAN_FM1R_FBM20 0x00100000U
2125 #define CAN_FM1R_FBM21 0x00200000U
2126 #define CAN_FM1R_FBM22 0x00400000U
2127 #define CAN_FM1R_FBM23 0x00800000U
2128 #define CAN_FM1R_FBM24 0x01000000U
2129 #define CAN_FM1R_FBM25 0x02000000U
2130 #define CAN_FM1R_FBM26 0x04000000U
2131 #define CAN_FM1R_FBM27 0x08000000U
2133 /******************* Bit definition for CAN_FS1R register *******************/
2134 #define CAN_FS1R_FSC 0x0FFFFFFFU
2135 #define CAN_FS1R_FSC0 0x00000001U
2136 #define CAN_FS1R_FSC1 0x00000002U
2137 #define CAN_FS1R_FSC2 0x00000004U
2138 #define CAN_FS1R_FSC3 0x00000008U
2139 #define CAN_FS1R_FSC4 0x00000010U
2140 #define CAN_FS1R_FSC5 0x00000020U
2141 #define CAN_FS1R_FSC6 0x00000040U
2142 #define CAN_FS1R_FSC7 0x00000080U
2143 #define CAN_FS1R_FSC8 0x00000100U
2144 #define CAN_FS1R_FSC9 0x00000200U
2145 #define CAN_FS1R_FSC10 0x00000400U
2146 #define CAN_FS1R_FSC11 0x00000800U
2147 #define CAN_FS1R_FSC12 0x00001000U
2148 #define CAN_FS1R_FSC13 0x00002000U
2149 #define CAN_FS1R_FSC14 0x00004000U
2150 #define CAN_FS1R_FSC15 0x00008000U
2151 #define CAN_FS1R_FSC16 0x00010000U
2152 #define CAN_FS1R_FSC17 0x00020000U
2153 #define CAN_FS1R_FSC18 0x00040000U
2154 #define CAN_FS1R_FSC19 0x00080000U
2155 #define CAN_FS1R_FSC20 0x00100000U
2156 #define CAN_FS1R_FSC21 0x00200000U
2157 #define CAN_FS1R_FSC22 0x00400000U
2158 #define CAN_FS1R_FSC23 0x00800000U
2159 #define CAN_FS1R_FSC24 0x01000000U
2160 #define CAN_FS1R_FSC25 0x02000000U
2161 #define CAN_FS1R_FSC26 0x04000000U
2162 #define CAN_FS1R_FSC27 0x08000000U
2164 /****************** Bit definition for CAN_FFA1R register *******************/
2165 #define CAN_FFA1R_FFA 0x0FFFFFFFU
2166 #define CAN_FFA1R_FFA0 0x00000001U
2167 #define CAN_FFA1R_FFA1 0x00000002U
2168 #define CAN_FFA1R_FFA2 0x00000004U
2169 #define CAN_FFA1R_FFA3 0x00000008U
2170 #define CAN_FFA1R_FFA4 0x00000010U
2171 #define CAN_FFA1R_FFA5 0x00000020U
2172 #define CAN_FFA1R_FFA6 0x00000040U
2173 #define CAN_FFA1R_FFA7 0x00000080U
2174 #define CAN_FFA1R_FFA8 0x00000100U
2175 #define CAN_FFA1R_FFA9 0x00000200U
2176 #define CAN_FFA1R_FFA10 0x00000400U
2177 #define CAN_FFA1R_FFA11 0x00000800U
2178 #define CAN_FFA1R_FFA12 0x00001000U
2179 #define CAN_FFA1R_FFA13 0x00002000U
2180 #define CAN_FFA1R_FFA14 0x00004000U
2181 #define CAN_FFA1R_FFA15 0x00008000U
2182 #define CAN_FFA1R_FFA16 0x00010000U
2183 #define CAN_FFA1R_FFA17 0x00020000U
2184 #define CAN_FFA1R_FFA18 0x00040000U
2185 #define CAN_FFA1R_FFA19 0x00080000U
2186 #define CAN_FFA1R_FFA20 0x00100000U
2187 #define CAN_FFA1R_FFA21 0x00200000U
2188 #define CAN_FFA1R_FFA22 0x00400000U
2189 #define CAN_FFA1R_FFA23 0x00800000U
2190 #define CAN_FFA1R_FFA24 0x01000000U
2191 #define CAN_FFA1R_FFA25 0x02000000U
2192 #define CAN_FFA1R_FFA26 0x04000000U
2193 #define CAN_FFA1R_FFA27 0x08000000U
2195 /******************* Bit definition for CAN_FA1R register *******************/
2196 #define CAN_FA1R_FACT 0x0FFFFFFFU
2197 #define CAN_FA1R_FACT0 0x00000001U
2198 #define CAN_FA1R_FACT1 0x00000002U
2199 #define CAN_FA1R_FACT2 0x00000004U
2200 #define CAN_FA1R_FACT3 0x00000008U
2201 #define CAN_FA1R_FACT4 0x00000010U
2202 #define CAN_FA1R_FACT5 0x00000020U
2203 #define CAN_FA1R_FACT6 0x00000040U
2204 #define CAN_FA1R_FACT7 0x00000080U
2205 #define CAN_FA1R_FACT8 0x00000100U
2206 #define CAN_FA1R_FACT9 0x00000200U
2207 #define CAN_FA1R_FACT10 0x00000400U
2208 #define CAN_FA1R_FACT11 0x00000800U
2209 #define CAN_FA1R_FACT12 0x00001000U
2210 #define CAN_FA1R_FACT13 0x00002000U
2211 #define CAN_FA1R_FACT14 0x00004000U
2212 #define CAN_FA1R_FACT15 0x00008000U
2213 #define CAN_FA1R_FACT16 0x00010000U
2214 #define CAN_FA1R_FACT17 0x00020000U
2215 #define CAN_FA1R_FACT18 0x00040000U
2216 #define CAN_FA1R_FACT19 0x00080000U
2217 #define CAN_FA1R_FACT20 0x00100000U
2218 #define CAN_FA1R_FACT21 0x00200000U
2219 #define CAN_FA1R_FACT22 0x00400000U
2220 #define CAN_FA1R_FACT23 0x00800000U
2221 #define CAN_FA1R_FACT24 0x01000000U
2222 #define CAN_FA1R_FACT25 0x02000000U
2223 #define CAN_FA1R_FACT26 0x04000000U
2224 #define CAN_FA1R_FACT27 0x08000000U
2227 /******************* Bit definition for CAN_F0R1 register *******************/
2228 #define CAN_F0R1_FB0 0x00000001U
2229 #define CAN_F0R1_FB1 0x00000002U
2230 #define CAN_F0R1_FB2 0x00000004U
2231 #define CAN_F0R1_FB3 0x00000008U
2232 #define CAN_F0R1_FB4 0x00000010U
2233 #define CAN_F0R1_FB5 0x00000020U
2234 #define CAN_F0R1_FB6 0x00000040U
2235 #define CAN_F0R1_FB7 0x00000080U
2236 #define CAN_F0R1_FB8 0x00000100U
2237 #define CAN_F0R1_FB9 0x00000200U
2238 #define CAN_F0R1_FB10 0x00000400U
2239 #define CAN_F0R1_FB11 0x00000800U
2240 #define CAN_F0R1_FB12 0x00001000U
2241 #define CAN_F0R1_FB13 0x00002000U
2242 #define CAN_F0R1_FB14 0x00004000U
2243 #define CAN_F0R1_FB15 0x00008000U
2244 #define CAN_F0R1_FB16 0x00010000U
2245 #define CAN_F0R1_FB17 0x00020000U
2246 #define CAN_F0R1_FB18 0x00040000U
2247 #define CAN_F0R1_FB19 0x00080000U
2248 #define CAN_F0R1_FB20 0x00100000U
2249 #define CAN_F0R1_FB21 0x00200000U
2250 #define CAN_F0R1_FB22 0x00400000U
2251 #define CAN_F0R1_FB23 0x00800000U
2252 #define CAN_F0R1_FB24 0x01000000U
2253 #define CAN_F0R1_FB25 0x02000000U
2254 #define CAN_F0R1_FB26 0x04000000U
2255 #define CAN_F0R1_FB27 0x08000000U
2256 #define CAN_F0R1_FB28 0x10000000U
2257 #define CAN_F0R1_FB29 0x20000000U
2258 #define CAN_F0R1_FB30 0x40000000U
2259 #define CAN_F0R1_FB31 0x80000000U
2261 /******************* Bit definition for CAN_F1R1 register *******************/
2262 #define CAN_F1R1_FB0 0x00000001U
2263 #define CAN_F1R1_FB1 0x00000002U
2264 #define CAN_F1R1_FB2 0x00000004U
2265 #define CAN_F1R1_FB3 0x00000008U
2266 #define CAN_F1R1_FB4 0x00000010U
2267 #define CAN_F1R1_FB5 0x00000020U
2268 #define CAN_F1R1_FB6 0x00000040U
2269 #define CAN_F1R1_FB7 0x00000080U
2270 #define CAN_F1R1_FB8 0x00000100U
2271 #define CAN_F1R1_FB9 0x00000200U
2272 #define CAN_F1R1_FB10 0x00000400U
2273 #define CAN_F1R1_FB11 0x00000800U
2274 #define CAN_F1R1_FB12 0x00001000U
2275 #define CAN_F1R1_FB13 0x00002000U
2276 #define CAN_F1R1_FB14 0x00004000U
2277 #define CAN_F1R1_FB15 0x00008000U
2278 #define CAN_F1R1_FB16 0x00010000U
2279 #define CAN_F1R1_FB17 0x00020000U
2280 #define CAN_F1R1_FB18 0x00040000U
2281 #define CAN_F1R1_FB19 0x00080000U
2282 #define CAN_F1R1_FB20 0x00100000U
2283 #define CAN_F1R1_FB21 0x00200000U
2284 #define CAN_F1R1_FB22 0x00400000U
2285 #define CAN_F1R1_FB23 0x00800000U
2286 #define CAN_F1R1_FB24 0x01000000U
2287 #define CAN_F1R1_FB25 0x02000000U
2288 #define CAN_F1R1_FB26 0x04000000U
2289 #define CAN_F1R1_FB27 0x08000000U
2290 #define CAN_F1R1_FB28 0x10000000U
2291 #define CAN_F1R1_FB29 0x20000000U
2292 #define CAN_F1R1_FB30 0x40000000U
2293 #define CAN_F1R1_FB31 0x80000000U
2295 /******************* Bit definition for CAN_F2R1 register *******************/
2296 #define CAN_F2R1_FB0 0x00000001U
2297 #define CAN_F2R1_FB1 0x00000002U
2298 #define CAN_F2R1_FB2 0x00000004U
2299 #define CAN_F2R1_FB3 0x00000008U
2300 #define CAN_F2R1_FB4 0x00000010U
2301 #define CAN_F2R1_FB5 0x00000020U
2302 #define CAN_F2R1_FB6 0x00000040U
2303 #define CAN_F2R1_FB7 0x00000080U
2304 #define CAN_F2R1_FB8 0x00000100U
2305 #define CAN_F2R1_FB9 0x00000200U
2306 #define CAN_F2R1_FB10 0x00000400U
2307 #define CAN_F2R1_FB11 0x00000800U
2308 #define CAN_F2R1_FB12 0x00001000U
2309 #define CAN_F2R1_FB13 0x00002000U
2310 #define CAN_F2R1_FB14 0x00004000U
2311 #define CAN_F2R1_FB15 0x00008000U
2312 #define CAN_F2R1_FB16 0x00010000U
2313 #define CAN_F2R1_FB17 0x00020000U
2314 #define CAN_F2R1_FB18 0x00040000U
2315 #define CAN_F2R1_FB19 0x00080000U
2316 #define CAN_F2R1_FB20 0x00100000U
2317 #define CAN_F2R1_FB21 0x00200000U
2318 #define CAN_F2R1_FB22 0x00400000U
2319 #define CAN_F2R1_FB23 0x00800000U
2320 #define CAN_F2R1_FB24 0x01000000U
2321 #define CAN_F2R1_FB25 0x02000000U
2322 #define CAN_F2R1_FB26 0x04000000U
2323 #define CAN_F2R1_FB27 0x08000000U
2324 #define CAN_F2R1_FB28 0x10000000U
2325 #define CAN_F2R1_FB29 0x20000000U
2326 #define CAN_F2R1_FB30 0x40000000U
2327 #define CAN_F2R1_FB31 0x80000000U
2329 /******************* Bit definition for CAN_F3R1 register *******************/
2330 #define CAN_F3R1_FB0 0x00000001U
2331 #define CAN_F3R1_FB1 0x00000002U
2332 #define CAN_F3R1_FB2 0x00000004U
2333 #define CAN_F3R1_FB3 0x00000008U
2334 #define CAN_F3R1_FB4 0x00000010U
2335 #define CAN_F3R1_FB5 0x00000020U
2336 #define CAN_F3R1_FB6 0x00000040U
2337 #define CAN_F3R1_FB7 0x00000080U
2338 #define CAN_F3R1_FB8 0x00000100U
2339 #define CAN_F3R1_FB9 0x00000200U
2340 #define CAN_F3R1_FB10 0x00000400U
2341 #define CAN_F3R1_FB11 0x00000800U
2342 #define CAN_F3R1_FB12 0x00001000U
2343 #define CAN_F3R1_FB13 0x00002000U
2344 #define CAN_F3R1_FB14 0x00004000U
2345 #define CAN_F3R1_FB15 0x00008000U
2346 #define CAN_F3R1_FB16 0x00010000U
2347 #define CAN_F3R1_FB17 0x00020000U
2348 #define CAN_F3R1_FB18 0x00040000U
2349 #define CAN_F3R1_FB19 0x00080000U
2350 #define CAN_F3R1_FB20 0x00100000U
2351 #define CAN_F3R1_FB21 0x00200000U
2352 #define CAN_F3R1_FB22 0x00400000U
2353 #define CAN_F3R1_FB23 0x00800000U
2354 #define CAN_F3R1_FB24 0x01000000U
2355 #define CAN_F3R1_FB25 0x02000000U
2356 #define CAN_F3R1_FB26 0x04000000U
2357 #define CAN_F3R1_FB27 0x08000000U
2358 #define CAN_F3R1_FB28 0x10000000U
2359 #define CAN_F3R1_FB29 0x20000000U
2360 #define CAN_F3R1_FB30 0x40000000U
2361 #define CAN_F3R1_FB31 0x80000000U
2363 /******************* Bit definition for CAN_F4R1 register *******************/
2364 #define CAN_F4R1_FB0 0x00000001U
2365 #define CAN_F4R1_FB1 0x00000002U
2366 #define CAN_F4R1_FB2 0x00000004U
2367 #define CAN_F4R1_FB3 0x00000008U
2368 #define CAN_F4R1_FB4 0x00000010U
2369 #define CAN_F4R1_FB5 0x00000020U
2370 #define CAN_F4R1_FB6 0x00000040U
2371 #define CAN_F4R1_FB7 0x00000080U
2372 #define CAN_F4R1_FB8 0x00000100U
2373 #define CAN_F4R1_FB9 0x00000200U
2374 #define CAN_F4R1_FB10 0x00000400U
2375 #define CAN_F4R1_FB11 0x00000800U
2376 #define CAN_F4R1_FB12 0x00001000U
2377 #define CAN_F4R1_FB13 0x00002000U
2378 #define CAN_F4R1_FB14 0x00004000U
2379 #define CAN_F4R1_FB15 0x00008000U
2380 #define CAN_F4R1_FB16 0x00010000U
2381 #define CAN_F4R1_FB17 0x00020000U
2382 #define CAN_F4R1_FB18 0x00040000U
2383 #define CAN_F4R1_FB19 0x00080000U
2384 #define CAN_F4R1_FB20 0x00100000U
2385 #define CAN_F4R1_FB21 0x00200000U
2386 #define CAN_F4R1_FB22 0x00400000U
2387 #define CAN_F4R1_FB23 0x00800000U
2388 #define CAN_F4R1_FB24 0x01000000U
2389 #define CAN_F4R1_FB25 0x02000000U
2390 #define CAN_F4R1_FB26 0x04000000U
2391 #define CAN_F4R1_FB27 0x08000000U
2392 #define CAN_F4R1_FB28 0x10000000U
2393 #define CAN_F4R1_FB29 0x20000000U
2394 #define CAN_F4R1_FB30 0x40000000U
2395 #define CAN_F4R1_FB31 0x80000000U
2397 /******************* Bit definition for CAN_F5R1 register *******************/
2398 #define CAN_F5R1_FB0 0x00000001U
2399 #define CAN_F5R1_FB1 0x00000002U
2400 #define CAN_F5R1_FB2 0x00000004U
2401 #define CAN_F5R1_FB3 0x00000008U
2402 #define CAN_F5R1_FB4 0x00000010U
2403 #define CAN_F5R1_FB5 0x00000020U
2404 #define CAN_F5R1_FB6 0x00000040U
2405 #define CAN_F5R1_FB7 0x00000080U
2406 #define CAN_F5R1_FB8 0x00000100U
2407 #define CAN_F5R1_FB9 0x00000200U
2408 #define CAN_F5R1_FB10 0x00000400U
2409 #define CAN_F5R1_FB11 0x00000800U
2410 #define CAN_F5R1_FB12 0x00001000U
2411 #define CAN_F5R1_FB13 0x00002000U
2412 #define CAN_F5R1_FB14 0x00004000U
2413 #define CAN_F5R1_FB15 0x00008000U
2414 #define CAN_F5R1_FB16 0x00010000U
2415 #define CAN_F5R1_FB17 0x00020000U
2416 #define CAN_F5R1_FB18 0x00040000U
2417 #define CAN_F5R1_FB19 0x00080000U
2418 #define CAN_F5R1_FB20 0x00100000U
2419 #define CAN_F5R1_FB21 0x00200000U
2420 #define CAN_F5R1_FB22 0x00400000U
2421 #define CAN_F5R1_FB23 0x00800000U
2422 #define CAN_F5R1_FB24 0x01000000U
2423 #define CAN_F5R1_FB25 0x02000000U
2424 #define CAN_F5R1_FB26 0x04000000U
2425 #define CAN_F5R1_FB27 0x08000000U
2426 #define CAN_F5R1_FB28 0x10000000U
2427 #define CAN_F5R1_FB29 0x20000000U
2428 #define CAN_F5R1_FB30 0x40000000U
2429 #define CAN_F5R1_FB31 0x80000000U
2431 /******************* Bit definition for CAN_F6R1 register *******************/
2432 #define CAN_F6R1_FB0 0x00000001U
2433 #define CAN_F6R1_FB1 0x00000002U
2434 #define CAN_F6R1_FB2 0x00000004U
2435 #define CAN_F6R1_FB3 0x00000008U
2436 #define CAN_F6R1_FB4 0x00000010U
2437 #define CAN_F6R1_FB5 0x00000020U
2438 #define CAN_F6R1_FB6 0x00000040U
2439 #define CAN_F6R1_FB7 0x00000080U
2440 #define CAN_F6R1_FB8 0x00000100U
2441 #define CAN_F6R1_FB9 0x00000200U
2442 #define CAN_F6R1_FB10 0x00000400U
2443 #define CAN_F6R1_FB11 0x00000800U
2444 #define CAN_F6R1_FB12 0x00001000U
2445 #define CAN_F6R1_FB13 0x00002000U
2446 #define CAN_F6R1_FB14 0x00004000U
2447 #define CAN_F6R1_FB15 0x00008000U
2448 #define CAN_F6R1_FB16 0x00010000U
2449 #define CAN_F6R1_FB17 0x00020000U
2450 #define CAN_F6R1_FB18 0x00040000U
2451 #define CAN_F6R1_FB19 0x00080000U
2452 #define CAN_F6R1_FB20 0x00100000U
2453 #define CAN_F6R1_FB21 0x00200000U
2454 #define CAN_F6R1_FB22 0x00400000U
2455 #define CAN_F6R1_FB23 0x00800000U
2456 #define CAN_F6R1_FB24 0x01000000U
2457 #define CAN_F6R1_FB25 0x02000000U
2458 #define CAN_F6R1_FB26 0x04000000U
2459 #define CAN_F6R1_FB27 0x08000000U
2460 #define CAN_F6R1_FB28 0x10000000U
2461 #define CAN_F6R1_FB29 0x20000000U
2462 #define CAN_F6R1_FB30 0x40000000U
2463 #define CAN_F6R1_FB31 0x80000000U
2465 /******************* Bit definition for CAN_F7R1 register *******************/
2466 #define CAN_F7R1_FB0 0x00000001U
2467 #define CAN_F7R1_FB1 0x00000002U
2468 #define CAN_F7R1_FB2 0x00000004U
2469 #define CAN_F7R1_FB3 0x00000008U
2470 #define CAN_F7R1_FB4 0x00000010U
2471 #define CAN_F7R1_FB5 0x00000020U
2472 #define CAN_F7R1_FB6 0x00000040U
2473 #define CAN_F7R1_FB7 0x00000080U
2474 #define CAN_F7R1_FB8 0x00000100U
2475 #define CAN_F7R1_FB9 0x00000200U
2476 #define CAN_F7R1_FB10 0x00000400U
2477 #define CAN_F7R1_FB11 0x00000800U
2478 #define CAN_F7R1_FB12 0x00001000U
2479 #define CAN_F7R1_FB13 0x00002000U
2480 #define CAN_F7R1_FB14 0x00004000U
2481 #define CAN_F7R1_FB15 0x00008000U
2482 #define CAN_F7R1_FB16 0x00010000U
2483 #define CAN_F7R1_FB17 0x00020000U
2484 #define CAN_F7R1_FB18 0x00040000U
2485 #define CAN_F7R1_FB19 0x00080000U
2486 #define CAN_F7R1_FB20 0x00100000U
2487 #define CAN_F7R1_FB21 0x00200000U
2488 #define CAN_F7R1_FB22 0x00400000U
2489 #define CAN_F7R1_FB23 0x00800000U
2490 #define CAN_F7R1_FB24 0x01000000U
2491 #define CAN_F7R1_FB25 0x02000000U
2492 #define CAN_F7R1_FB26 0x04000000U
2493 #define CAN_F7R1_FB27 0x08000000U
2494 #define CAN_F7R1_FB28 0x10000000U
2495 #define CAN_F7R1_FB29 0x20000000U
2496 #define CAN_F7R1_FB30 0x40000000U
2497 #define CAN_F7R1_FB31 0x80000000U
2499 /******************* Bit definition for CAN_F8R1 register *******************/
2500 #define CAN_F8R1_FB0 0x00000001U
2501 #define CAN_F8R1_FB1 0x00000002U
2502 #define CAN_F8R1_FB2 0x00000004U
2503 #define CAN_F8R1_FB3 0x00000008U
2504 #define CAN_F8R1_FB4 0x00000010U
2505 #define CAN_F8R1_FB5 0x00000020U
2506 #define CAN_F8R1_FB6 0x00000040U
2507 #define CAN_F8R1_FB7 0x00000080U
2508 #define CAN_F8R1_FB8 0x00000100U
2509 #define CAN_F8R1_FB9 0x00000200U
2510 #define CAN_F8R1_FB10 0x00000400U
2511 #define CAN_F8R1_FB11 0x00000800U
2512 #define CAN_F8R1_FB12 0x00001000U
2513 #define CAN_F8R1_FB13 0x00002000U
2514 #define CAN_F8R1_FB14 0x00004000U
2515 #define CAN_F8R1_FB15 0x00008000U
2516 #define CAN_F8R1_FB16 0x00010000U
2517 #define CAN_F8R1_FB17 0x00020000U
2518 #define CAN_F8R1_FB18 0x00040000U
2519 #define CAN_F8R1_FB19 0x00080000U
2520 #define CAN_F8R1_FB20 0x00100000U
2521 #define CAN_F8R1_FB21 0x00200000U
2522 #define CAN_F8R1_FB22 0x00400000U
2523 #define CAN_F8R1_FB23 0x00800000U
2524 #define CAN_F8R1_FB24 0x01000000U
2525 #define CAN_F8R1_FB25 0x02000000U
2526 #define CAN_F8R1_FB26 0x04000000U
2527 #define CAN_F8R1_FB27 0x08000000U
2528 #define CAN_F8R1_FB28 0x10000000U
2529 #define CAN_F8R1_FB29 0x20000000U
2530 #define CAN_F8R1_FB30 0x40000000U
2531 #define CAN_F8R1_FB31 0x80000000U
2533 /******************* Bit definition for CAN_F9R1 register *******************/
2534 #define CAN_F9R1_FB0 0x00000001U
2535 #define CAN_F9R1_FB1 0x00000002U
2536 #define CAN_F9R1_FB2 0x00000004U
2537 #define CAN_F9R1_FB3 0x00000008U
2538 #define CAN_F9R1_FB4 0x00000010U
2539 #define CAN_F9R1_FB5 0x00000020U
2540 #define CAN_F9R1_FB6 0x00000040U
2541 #define CAN_F9R1_FB7 0x00000080U
2542 #define CAN_F9R1_FB8 0x00000100U
2543 #define CAN_F9R1_FB9 0x00000200U
2544 #define CAN_F9R1_FB10 0x00000400U
2545 #define CAN_F9R1_FB11 0x00000800U
2546 #define CAN_F9R1_FB12 0x00001000U
2547 #define CAN_F9R1_FB13 0x00002000U
2548 #define CAN_F9R1_FB14 0x00004000U
2549 #define CAN_F9R1_FB15 0x00008000U
2550 #define CAN_F9R1_FB16 0x00010000U
2551 #define CAN_F9R1_FB17 0x00020000U
2552 #define CAN_F9R1_FB18 0x00040000U
2553 #define CAN_F9R1_FB19 0x00080000U
2554 #define CAN_F9R1_FB20 0x00100000U
2555 #define CAN_F9R1_FB21 0x00200000U
2556 #define CAN_F9R1_FB22 0x00400000U
2557 #define CAN_F9R1_FB23 0x00800000U
2558 #define CAN_F9R1_FB24 0x01000000U
2559 #define CAN_F9R1_FB25 0x02000000U
2560 #define CAN_F9R1_FB26 0x04000000U
2561 #define CAN_F9R1_FB27 0x08000000U
2562 #define CAN_F9R1_FB28 0x10000000U
2563 #define CAN_F9R1_FB29 0x20000000U
2564 #define CAN_F9R1_FB30 0x40000000U
2565 #define CAN_F9R1_FB31 0x80000000U
2567 /******************* Bit definition for CAN_F10R1 register ******************/
2568 #define CAN_F10R1_FB0 0x00000001U
2569 #define CAN_F10R1_FB1 0x00000002U
2570 #define CAN_F10R1_FB2 0x00000004U
2571 #define CAN_F10R1_FB3 0x00000008U
2572 #define CAN_F10R1_FB4 0x00000010U
2573 #define CAN_F10R1_FB5 0x00000020U
2574 #define CAN_F10R1_FB6 0x00000040U
2575 #define CAN_F10R1_FB7 0x00000080U
2576 #define CAN_F10R1_FB8 0x00000100U
2577 #define CAN_F10R1_FB9 0x00000200U
2578 #define CAN_F10R1_FB10 0x00000400U
2579 #define CAN_F10R1_FB11 0x00000800U
2580 #define CAN_F10R1_FB12 0x00001000U
2581 #define CAN_F10R1_FB13 0x00002000U
2582 #define CAN_F10R1_FB14 0x00004000U
2583 #define CAN_F10R1_FB15 0x00008000U
2584 #define CAN_F10R1_FB16 0x00010000U
2585 #define CAN_F10R1_FB17 0x00020000U
2586 #define CAN_F10R1_FB18 0x00040000U
2587 #define CAN_F10R1_FB19 0x00080000U
2588 #define CAN_F10R1_FB20 0x00100000U
2589 #define CAN_F10R1_FB21 0x00200000U
2590 #define CAN_F10R1_FB22 0x00400000U
2591 #define CAN_F10R1_FB23 0x00800000U
2592 #define CAN_F10R1_FB24 0x01000000U
2593 #define CAN_F10R1_FB25 0x02000000U
2594 #define CAN_F10R1_FB26 0x04000000U
2595 #define CAN_F10R1_FB27 0x08000000U
2596 #define CAN_F10R1_FB28 0x10000000U
2597 #define CAN_F10R1_FB29 0x20000000U
2598 #define CAN_F10R1_FB30 0x40000000U
2599 #define CAN_F10R1_FB31 0x80000000U
2601 /******************* Bit definition for CAN_F11R1 register ******************/
2602 #define CAN_F11R1_FB0 0x00000001U
2603 #define CAN_F11R1_FB1 0x00000002U
2604 #define CAN_F11R1_FB2 0x00000004U
2605 #define CAN_F11R1_FB3 0x00000008U
2606 #define CAN_F11R1_FB4 0x00000010U
2607 #define CAN_F11R1_FB5 0x00000020U
2608 #define CAN_F11R1_FB6 0x00000040U
2609 #define CAN_F11R1_FB7 0x00000080U
2610 #define CAN_F11R1_FB8 0x00000100U
2611 #define CAN_F11R1_FB9 0x00000200U
2612 #define CAN_F11R1_FB10 0x00000400U
2613 #define CAN_F11R1_FB11 0x00000800U
2614 #define CAN_F11R1_FB12 0x00001000U
2615 #define CAN_F11R1_FB13 0x00002000U
2616 #define CAN_F11R1_FB14 0x00004000U
2617 #define CAN_F11R1_FB15 0x00008000U
2618 #define CAN_F11R1_FB16 0x00010000U
2619 #define CAN_F11R1_FB17 0x00020000U
2620 #define CAN_F11R1_FB18 0x00040000U
2621 #define CAN_F11R1_FB19 0x00080000U
2622 #define CAN_F11R1_FB20 0x00100000U
2623 #define CAN_F11R1_FB21 0x00200000U
2624 #define CAN_F11R1_FB22 0x00400000U
2625 #define CAN_F11R1_FB23 0x00800000U
2626 #define CAN_F11R1_FB24 0x01000000U
2627 #define CAN_F11R1_FB25 0x02000000U
2628 #define CAN_F11R1_FB26 0x04000000U
2629 #define CAN_F11R1_FB27 0x08000000U
2630 #define CAN_F11R1_FB28 0x10000000U
2631 #define CAN_F11R1_FB29 0x20000000U
2632 #define CAN_F11R1_FB30 0x40000000U
2633 #define CAN_F11R1_FB31 0x80000000U
2635 /******************* Bit definition for CAN_F12R1 register ******************/
2636 #define CAN_F12R1_FB0 0x00000001U
2637 #define CAN_F12R1_FB1 0x00000002U
2638 #define CAN_F12R1_FB2 0x00000004U
2639 #define CAN_F12R1_FB3 0x00000008U
2640 #define CAN_F12R1_FB4 0x00000010U
2641 #define CAN_F12R1_FB5 0x00000020U
2642 #define CAN_F12R1_FB6 0x00000040U
2643 #define CAN_F12R1_FB7 0x00000080U
2644 #define CAN_F12R1_FB8 0x00000100U
2645 #define CAN_F12R1_FB9 0x00000200U
2646 #define CAN_F12R1_FB10 0x00000400U
2647 #define CAN_F12R1_FB11 0x00000800U
2648 #define CAN_F12R1_FB12 0x00001000U
2649 #define CAN_F12R1_FB13 0x00002000U
2650 #define CAN_F12R1_FB14 0x00004000U
2651 #define CAN_F12R1_FB15 0x00008000U
2652 #define CAN_F12R1_FB16 0x00010000U
2653 #define CAN_F12R1_FB17 0x00020000U
2654 #define CAN_F12R1_FB18 0x00040000U
2655 #define CAN_F12R1_FB19 0x00080000U
2656 #define CAN_F12R1_FB20 0x00100000U
2657 #define CAN_F12R1_FB21 0x00200000U
2658 #define CAN_F12R1_FB22 0x00400000U
2659 #define CAN_F12R1_FB23 0x00800000U
2660 #define CAN_F12R1_FB24 0x01000000U
2661 #define CAN_F12R1_FB25 0x02000000U
2662 #define CAN_F12R1_FB26 0x04000000U
2663 #define CAN_F12R1_FB27 0x08000000U
2664 #define CAN_F12R1_FB28 0x10000000U
2665 #define CAN_F12R1_FB29 0x20000000U
2666 #define CAN_F12R1_FB30 0x40000000U
2667 #define CAN_F12R1_FB31 0x80000000U
2669 /******************* Bit definition for CAN_F13R1 register ******************/
2670 #define CAN_F13R1_FB0 0x00000001U
2671 #define CAN_F13R1_FB1 0x00000002U
2672 #define CAN_F13R1_FB2 0x00000004U
2673 #define CAN_F13R1_FB3 0x00000008U
2674 #define CAN_F13R1_FB4 0x00000010U
2675 #define CAN_F13R1_FB5 0x00000020U
2676 #define CAN_F13R1_FB6 0x00000040U
2677 #define CAN_F13R1_FB7 0x00000080U
2678 #define CAN_F13R1_FB8 0x00000100U
2679 #define CAN_F13R1_FB9 0x00000200U
2680 #define CAN_F13R1_FB10 0x00000400U
2681 #define CAN_F13R1_FB11 0x00000800U
2682 #define CAN_F13R1_FB12 0x00001000U
2683 #define CAN_F13R1_FB13 0x00002000U
2684 #define CAN_F13R1_FB14 0x00004000U
2685 #define CAN_F13R1_FB15 0x00008000U
2686 #define CAN_F13R1_FB16 0x00010000U
2687 #define CAN_F13R1_FB17 0x00020000U
2688 #define CAN_F13R1_FB18 0x00040000U
2689 #define CAN_F13R1_FB19 0x00080000U
2690 #define CAN_F13R1_FB20 0x00100000U
2691 #define CAN_F13R1_FB21 0x00200000U
2692 #define CAN_F13R1_FB22 0x00400000U
2693 #define CAN_F13R1_FB23 0x00800000U
2694 #define CAN_F13R1_FB24 0x01000000U
2695 #define CAN_F13R1_FB25 0x02000000U
2696 #define CAN_F13R1_FB26 0x04000000U
2697 #define CAN_F13R1_FB27 0x08000000U
2698 #define CAN_F13R1_FB28 0x10000000U
2699 #define CAN_F13R1_FB29 0x20000000U
2700 #define CAN_F13R1_FB30 0x40000000U
2701 #define CAN_F13R1_FB31 0x80000000U
2703 /******************* Bit definition for CAN_F0R2 register *******************/
2704 #define CAN_F0R2_FB0 0x00000001U
2705 #define CAN_F0R2_FB1 0x00000002U
2706 #define CAN_F0R2_FB2 0x00000004U
2707 #define CAN_F0R2_FB3 0x00000008U
2708 #define CAN_F0R2_FB4 0x00000010U
2709 #define CAN_F0R2_FB5 0x00000020U
2710 #define CAN_F0R2_FB6 0x00000040U
2711 #define CAN_F0R2_FB7 0x00000080U
2712 #define CAN_F0R2_FB8 0x00000100U
2713 #define CAN_F0R2_FB9 0x00000200U
2714 #define CAN_F0R2_FB10 0x00000400U
2715 #define CAN_F0R2_FB11 0x00000800U
2716 #define CAN_F0R2_FB12 0x00001000U
2717 #define CAN_F0R2_FB13 0x00002000U
2718 #define CAN_F0R2_FB14 0x00004000U
2719 #define CAN_F0R2_FB15 0x00008000U
2720 #define CAN_F0R2_FB16 0x00010000U
2721 #define CAN_F0R2_FB17 0x00020000U
2722 #define CAN_F0R2_FB18 0x00040000U
2723 #define CAN_F0R2_FB19 0x00080000U
2724 #define CAN_F0R2_FB20 0x00100000U
2725 #define CAN_F0R2_FB21 0x00200000U
2726 #define CAN_F0R2_FB22 0x00400000U
2727 #define CAN_F0R2_FB23 0x00800000U
2728 #define CAN_F0R2_FB24 0x01000000U
2729 #define CAN_F0R2_FB25 0x02000000U
2730 #define CAN_F0R2_FB26 0x04000000U
2731 #define CAN_F0R2_FB27 0x08000000U
2732 #define CAN_F0R2_FB28 0x10000000U
2733 #define CAN_F0R2_FB29 0x20000000U
2734 #define CAN_F0R2_FB30 0x40000000U
2735 #define CAN_F0R2_FB31 0x80000000U
2737 /******************* Bit definition for CAN_F1R2 register *******************/
2738 #define CAN_F1R2_FB0 0x00000001U
2739 #define CAN_F1R2_FB1 0x00000002U
2740 #define CAN_F1R2_FB2 0x00000004U
2741 #define CAN_F1R2_FB3 0x00000008U
2742 #define CAN_F1R2_FB4 0x00000010U
2743 #define CAN_F1R2_FB5 0x00000020U
2744 #define CAN_F1R2_FB6 0x00000040U
2745 #define CAN_F1R2_FB7 0x00000080U
2746 #define CAN_F1R2_FB8 0x00000100U
2747 #define CAN_F1R2_FB9 0x00000200U
2748 #define CAN_F1R2_FB10 0x00000400U
2749 #define CAN_F1R2_FB11 0x00000800U
2750 #define CAN_F1R2_FB12 0x00001000U
2751 #define CAN_F1R2_FB13 0x00002000U
2752 #define CAN_F1R2_FB14 0x00004000U
2753 #define CAN_F1R2_FB15 0x00008000U
2754 #define CAN_F1R2_FB16 0x00010000U
2755 #define CAN_F1R2_FB17 0x00020000U
2756 #define CAN_F1R2_FB18 0x00040000U
2757 #define CAN_F1R2_FB19 0x00080000U
2758 #define CAN_F1R2_FB20 0x00100000U
2759 #define CAN_F1R2_FB21 0x00200000U
2760 #define CAN_F1R2_FB22 0x00400000U
2761 #define CAN_F1R2_FB23 0x00800000U
2762 #define CAN_F1R2_FB24 0x01000000U
2763 #define CAN_F1R2_FB25 0x02000000U
2764 #define CAN_F1R2_FB26 0x04000000U
2765 #define CAN_F1R2_FB27 0x08000000U
2766 #define CAN_F1R2_FB28 0x10000000U
2767 #define CAN_F1R2_FB29 0x20000000U
2768 #define CAN_F1R2_FB30 0x40000000U
2769 #define CAN_F1R2_FB31 0x80000000U
2771 /******************* Bit definition for CAN_F2R2 register *******************/
2772 #define CAN_F2R2_FB0 0x00000001U
2773 #define CAN_F2R2_FB1 0x00000002U
2774 #define CAN_F2R2_FB2 0x00000004U
2775 #define CAN_F2R2_FB3 0x00000008U
2776 #define CAN_F2R2_FB4 0x00000010U
2777 #define CAN_F2R2_FB5 0x00000020U
2778 #define CAN_F2R2_FB6 0x00000040U
2779 #define CAN_F2R2_FB7 0x00000080U
2780 #define CAN_F2R2_FB8 0x00000100U
2781 #define CAN_F2R2_FB9 0x00000200U
2782 #define CAN_F2R2_FB10 0x00000400U
2783 #define CAN_F2R2_FB11 0x00000800U
2784 #define CAN_F2R2_FB12 0x00001000U
2785 #define CAN_F2R2_FB13 0x00002000U
2786 #define CAN_F2R2_FB14 0x00004000U
2787 #define CAN_F2R2_FB15 0x00008000U
2788 #define CAN_F2R2_FB16 0x00010000U
2789 #define CAN_F2R2_FB17 0x00020000U
2790 #define CAN_F2R2_FB18 0x00040000U
2791 #define CAN_F2R2_FB19 0x00080000U
2792 #define CAN_F2R2_FB20 0x00100000U
2793 #define CAN_F2R2_FB21 0x00200000U
2794 #define CAN_F2R2_FB22 0x00400000U
2795 #define CAN_F2R2_FB23 0x00800000U
2796 #define CAN_F2R2_FB24 0x01000000U
2797 #define CAN_F2R2_FB25 0x02000000U
2798 #define CAN_F2R2_FB26 0x04000000U
2799 #define CAN_F2R2_FB27 0x08000000U
2800 #define CAN_F2R2_FB28 0x10000000U
2801 #define CAN_F2R2_FB29 0x20000000U
2802 #define CAN_F2R2_FB30 0x40000000U
2803 #define CAN_F2R2_FB31 0x80000000U
2805 /******************* Bit definition for CAN_F3R2 register *******************/
2806 #define CAN_F3R2_FB0 0x00000001U
2807 #define CAN_F3R2_FB1 0x00000002U
2808 #define CAN_F3R2_FB2 0x00000004U
2809 #define CAN_F3R2_FB3 0x00000008U
2810 #define CAN_F3R2_FB4 0x00000010U
2811 #define CAN_F3R2_FB5 0x00000020U
2812 #define CAN_F3R2_FB6 0x00000040U
2813 #define CAN_F3R2_FB7 0x00000080U
2814 #define CAN_F3R2_FB8 0x00000100U
2815 #define CAN_F3R2_FB9 0x00000200U
2816 #define CAN_F3R2_FB10 0x00000400U
2817 #define CAN_F3R2_FB11 0x00000800U
2818 #define CAN_F3R2_FB12 0x00001000U
2819 #define CAN_F3R2_FB13 0x00002000U
2820 #define CAN_F3R2_FB14 0x00004000U
2821 #define CAN_F3R2_FB15 0x00008000U
2822 #define CAN_F3R2_FB16 0x00010000U
2823 #define CAN_F3R2_FB17 0x00020000U
2824 #define CAN_F3R2_FB18 0x00040000U
2825 #define CAN_F3R2_FB19 0x00080000U
2826 #define CAN_F3R2_FB20 0x00100000U
2827 #define CAN_F3R2_FB21 0x00200000U
2828 #define CAN_F3R2_FB22 0x00400000U
2829 #define CAN_F3R2_FB23 0x00800000U
2830 #define CAN_F3R2_FB24 0x01000000U
2831 #define CAN_F3R2_FB25 0x02000000U
2832 #define CAN_F3R2_FB26 0x04000000U
2833 #define CAN_F3R2_FB27 0x08000000U
2834 #define CAN_F3R2_FB28 0x10000000U
2835 #define CAN_F3R2_FB29 0x20000000U
2836 #define CAN_F3R2_FB30 0x40000000U
2837 #define CAN_F3R2_FB31 0x80000000U
2839 /******************* Bit definition for CAN_F4R2 register *******************/
2840 #define CAN_F4R2_FB0 0x00000001U
2841 #define CAN_F4R2_FB1 0x00000002U
2842 #define CAN_F4R2_FB2 0x00000004U
2843 #define CAN_F4R2_FB3 0x00000008U
2844 #define CAN_F4R2_FB4 0x00000010U
2845 #define CAN_F4R2_FB5 0x00000020U
2846 #define CAN_F4R2_FB6 0x00000040U
2847 #define CAN_F4R2_FB7 0x00000080U
2848 #define CAN_F4R2_FB8 0x00000100U
2849 #define CAN_F4R2_FB9 0x00000200U
2850 #define CAN_F4R2_FB10 0x00000400U
2851 #define CAN_F4R2_FB11 0x00000800U
2852 #define CAN_F4R2_FB12 0x00001000U
2853 #define CAN_F4R2_FB13 0x00002000U
2854 #define CAN_F4R2_FB14 0x00004000U
2855 #define CAN_F4R2_FB15 0x00008000U
2856 #define CAN_F4R2_FB16 0x00010000U
2857 #define CAN_F4R2_FB17 0x00020000U
2858 #define CAN_F4R2_FB18 0x00040000U
2859 #define CAN_F4R2_FB19 0x00080000U
2860 #define CAN_F4R2_FB20 0x00100000U
2861 #define CAN_F4R2_FB21 0x00200000U
2862 #define CAN_F4R2_FB22 0x00400000U
2863 #define CAN_F4R2_FB23 0x00800000U
2864 #define CAN_F4R2_FB24 0x01000000U
2865 #define CAN_F4R2_FB25 0x02000000U
2866 #define CAN_F4R2_FB26 0x04000000U
2867 #define CAN_F4R2_FB27 0x08000000U
2868 #define CAN_F4R2_FB28 0x10000000U
2869 #define CAN_F4R2_FB29 0x20000000U
2870 #define CAN_F4R2_FB30 0x40000000U
2871 #define CAN_F4R2_FB31 0x80000000U
2873 /******************* Bit definition for CAN_F5R2 register *******************/
2874 #define CAN_F5R2_FB0 0x00000001U
2875 #define CAN_F5R2_FB1 0x00000002U
2876 #define CAN_F5R2_FB2 0x00000004U
2877 #define CAN_F5R2_FB3 0x00000008U
2878 #define CAN_F5R2_FB4 0x00000010U
2879 #define CAN_F5R2_FB5 0x00000020U
2880 #define CAN_F5R2_FB6 0x00000040U
2881 #define CAN_F5R2_FB7 0x00000080U
2882 #define CAN_F5R2_FB8 0x00000100U
2883 #define CAN_F5R2_FB9 0x00000200U
2884 #define CAN_F5R2_FB10 0x00000400U
2885 #define CAN_F5R2_FB11 0x00000800U
2886 #define CAN_F5R2_FB12 0x00001000U
2887 #define CAN_F5R2_FB13 0x00002000U
2888 #define CAN_F5R2_FB14 0x00004000U
2889 #define CAN_F5R2_FB15 0x00008000U
2890 #define CAN_F5R2_FB16 0x00010000U
2891 #define CAN_F5R2_FB17 0x00020000U
2892 #define CAN_F5R2_FB18 0x00040000U
2893 #define CAN_F5R2_FB19 0x00080000U
2894 #define CAN_F5R2_FB20 0x00100000U
2895 #define CAN_F5R2_FB21 0x00200000U
2896 #define CAN_F5R2_FB22 0x00400000U
2897 #define CAN_F5R2_FB23 0x00800000U
2898 #define CAN_F5R2_FB24 0x01000000U
2899 #define CAN_F5R2_FB25 0x02000000U
2900 #define CAN_F5R2_FB26 0x04000000U
2901 #define CAN_F5R2_FB27 0x08000000U
2902 #define CAN_F5R2_FB28 0x10000000U
2903 #define CAN_F5R2_FB29 0x20000000U
2904 #define CAN_F5R2_FB30 0x40000000U
2905 #define CAN_F5R2_FB31 0x80000000U
2907 /******************* Bit definition for CAN_F6R2 register *******************/
2908 #define CAN_F6R2_FB0 0x00000001U
2909 #define CAN_F6R2_FB1 0x00000002U
2910 #define CAN_F6R2_FB2 0x00000004U
2911 #define CAN_F6R2_FB3 0x00000008U
2912 #define CAN_F6R2_FB4 0x00000010U
2913 #define CAN_F6R2_FB5 0x00000020U
2914 #define CAN_F6R2_FB6 0x00000040U
2915 #define CAN_F6R2_FB7 0x00000080U
2916 #define CAN_F6R2_FB8 0x00000100U
2917 #define CAN_F6R2_FB9 0x00000200U
2918 #define CAN_F6R2_FB10 0x00000400U
2919 #define CAN_F6R2_FB11 0x00000800U
2920 #define CAN_F6R2_FB12 0x00001000U
2921 #define CAN_F6R2_FB13 0x00002000U
2922 #define CAN_F6R2_FB14 0x00004000U
2923 #define CAN_F6R2_FB15 0x00008000U
2924 #define CAN_F6R2_FB16 0x00010000U
2925 #define CAN_F6R2_FB17 0x00020000U
2926 #define CAN_F6R2_FB18 0x00040000U
2927 #define CAN_F6R2_FB19 0x00080000U
2928 #define CAN_F6R2_FB20 0x00100000U
2929 #define CAN_F6R2_FB21 0x00200000U
2930 #define CAN_F6R2_FB22 0x00400000U
2931 #define CAN_F6R2_FB23 0x00800000U
2932 #define CAN_F6R2_FB24 0x01000000U
2933 #define CAN_F6R2_FB25 0x02000000U
2934 #define CAN_F6R2_FB26 0x04000000U
2935 #define CAN_F6R2_FB27 0x08000000U
2936 #define CAN_F6R2_FB28 0x10000000U
2937 #define CAN_F6R2_FB29 0x20000000U
2938 #define CAN_F6R2_FB30 0x40000000U
2939 #define CAN_F6R2_FB31 0x80000000U
2941 /******************* Bit definition for CAN_F7R2 register *******************/
2942 #define CAN_F7R2_FB0 0x00000001U
2943 #define CAN_F7R2_FB1 0x00000002U
2944 #define CAN_F7R2_FB2 0x00000004U
2945 #define CAN_F7R2_FB3 0x00000008U
2946 #define CAN_F7R2_FB4 0x00000010U
2947 #define CAN_F7R2_FB5 0x00000020U
2948 #define CAN_F7R2_FB6 0x00000040U
2949 #define CAN_F7R2_FB7 0x00000080U
2950 #define CAN_F7R2_FB8 0x00000100U
2951 #define CAN_F7R2_FB9 0x00000200U
2952 #define CAN_F7R2_FB10 0x00000400U
2953 #define CAN_F7R2_FB11 0x00000800U
2954 #define CAN_F7R2_FB12 0x00001000U
2955 #define CAN_F7R2_FB13 0x00002000U
2956 #define CAN_F7R2_FB14 0x00004000U
2957 #define CAN_F7R2_FB15 0x00008000U
2958 #define CAN_F7R2_FB16 0x00010000U
2959 #define CAN_F7R2_FB17 0x00020000U
2960 #define CAN_F7R2_FB18 0x00040000U
2961 #define CAN_F7R2_FB19 0x00080000U
2962 #define CAN_F7R2_FB20 0x00100000U
2963 #define CAN_F7R2_FB21 0x00200000U
2964 #define CAN_F7R2_FB22 0x00400000U
2965 #define CAN_F7R2_FB23 0x00800000U
2966 #define CAN_F7R2_FB24 0x01000000U
2967 #define CAN_F7R2_FB25 0x02000000U
2968 #define CAN_F7R2_FB26 0x04000000U
2969 #define CAN_F7R2_FB27 0x08000000U
2970 #define CAN_F7R2_FB28 0x10000000U
2971 #define CAN_F7R2_FB29 0x20000000U
2972 #define CAN_F7R2_FB30 0x40000000U
2973 #define CAN_F7R2_FB31 0x80000000U
2975 /******************* Bit definition for CAN_F8R2 register *******************/
2976 #define CAN_F8R2_FB0 0x00000001U
2977 #define CAN_F8R2_FB1 0x00000002U
2978 #define CAN_F8R2_FB2 0x00000004U
2979 #define CAN_F8R2_FB3 0x00000008U
2980 #define CAN_F8R2_FB4 0x00000010U
2981 #define CAN_F8R2_FB5 0x00000020U
2982 #define CAN_F8R2_FB6 0x00000040U
2983 #define CAN_F8R2_FB7 0x00000080U
2984 #define CAN_F8R2_FB8 0x00000100U
2985 #define CAN_F8R2_FB9 0x00000200U
2986 #define CAN_F8R2_FB10 0x00000400U
2987 #define CAN_F8R2_FB11 0x00000800U
2988 #define CAN_F8R2_FB12 0x00001000U
2989 #define CAN_F8R2_FB13 0x00002000U
2990 #define CAN_F8R2_FB14 0x00004000U
2991 #define CAN_F8R2_FB15 0x00008000U
2992 #define CAN_F8R2_FB16 0x00010000U
2993 #define CAN_F8R2_FB17 0x00020000U
2994 #define CAN_F8R2_FB18 0x00040000U
2995 #define CAN_F8R2_FB19 0x00080000U
2996 #define CAN_F8R2_FB20 0x00100000U
2997 #define CAN_F8R2_FB21 0x00200000U
2998 #define CAN_F8R2_FB22 0x00400000U
2999 #define CAN_F8R2_FB23 0x00800000U
3000 #define CAN_F8R2_FB24 0x01000000U
3001 #define CAN_F8R2_FB25 0x02000000U
3002 #define CAN_F8R2_FB26 0x04000000U
3003 #define CAN_F8R2_FB27 0x08000000U
3004 #define CAN_F8R2_FB28 0x10000000U
3005 #define CAN_F8R2_FB29 0x20000000U
3006 #define CAN_F8R2_FB30 0x40000000U
3007 #define CAN_F8R2_FB31 0x80000000U
3009 /******************* Bit definition for CAN_F9R2 register *******************/
3010 #define CAN_F9R2_FB0 0x00000001U
3011 #define CAN_F9R2_FB1 0x00000002U
3012 #define CAN_F9R2_FB2 0x00000004U
3013 #define CAN_F9R2_FB3 0x00000008U
3014 #define CAN_F9R2_FB4 0x00000010U
3015 #define CAN_F9R2_FB5 0x00000020U
3016 #define CAN_F9R2_FB6 0x00000040U
3017 #define CAN_F9R2_FB7 0x00000080U
3018 #define CAN_F9R2_FB8 0x00000100U
3019 #define CAN_F9R2_FB9 0x00000200U
3020 #define CAN_F9R2_FB10 0x00000400U
3021 #define CAN_F9R2_FB11 0x00000800U
3022 #define CAN_F9R2_FB12 0x00001000U
3023 #define CAN_F9R2_FB13 0x00002000U
3024 #define CAN_F9R2_FB14 0x00004000U
3025 #define CAN_F9R2_FB15 0x00008000U
3026 #define CAN_F9R2_FB16 0x00010000U
3027 #define CAN_F9R2_FB17 0x00020000U
3028 #define CAN_F9R2_FB18 0x00040000U
3029 #define CAN_F9R2_FB19 0x00080000U
3030 #define CAN_F9R2_FB20 0x00100000U
3031 #define CAN_F9R2_FB21 0x00200000U
3032 #define CAN_F9R2_FB22 0x00400000U
3033 #define CAN_F9R2_FB23 0x00800000U
3034 #define CAN_F9R2_FB24 0x01000000U
3035 #define CAN_F9R2_FB25 0x02000000U
3036 #define CAN_F9R2_FB26 0x04000000U
3037 #define CAN_F9R2_FB27 0x08000000U
3038 #define CAN_F9R2_FB28 0x10000000U
3039 #define CAN_F9R2_FB29 0x20000000U
3040 #define CAN_F9R2_FB30 0x40000000U
3041 #define CAN_F9R2_FB31 0x80000000U
3043 /******************* Bit definition for CAN_F10R2 register ******************/
3044 #define CAN_F10R2_FB0 0x00000001U
3045 #define CAN_F10R2_FB1 0x00000002U
3046 #define CAN_F10R2_FB2 0x00000004U
3047 #define CAN_F10R2_FB3 0x00000008U
3048 #define CAN_F10R2_FB4 0x00000010U
3049 #define CAN_F10R2_FB5 0x00000020U
3050 #define CAN_F10R2_FB6 0x00000040U
3051 #define CAN_F10R2_FB7 0x00000080U
3052 #define CAN_F10R2_FB8 0x00000100U
3053 #define CAN_F10R2_FB9 0x00000200U
3054 #define CAN_F10R2_FB10 0x00000400U
3055 #define CAN_F10R2_FB11 0x00000800U
3056 #define CAN_F10R2_FB12 0x00001000U
3057 #define CAN_F10R2_FB13 0x00002000U
3058 #define CAN_F10R2_FB14 0x00004000U
3059 #define CAN_F10R2_FB15 0x00008000U
3060 #define CAN_F10R2_FB16 0x00010000U
3061 #define CAN_F10R2_FB17 0x00020000U
3062 #define CAN_F10R2_FB18 0x00040000U
3063 #define CAN_F10R2_FB19 0x00080000U
3064 #define CAN_F10R2_FB20 0x00100000U
3065 #define CAN_F10R2_FB21 0x00200000U
3066 #define CAN_F10R2_FB22 0x00400000U
3067 #define CAN_F10R2_FB23 0x00800000U
3068 #define CAN_F10R2_FB24 0x01000000U
3069 #define CAN_F10R2_FB25 0x02000000U
3070 #define CAN_F10R2_FB26 0x04000000U
3071 #define CAN_F10R2_FB27 0x08000000U
3072 #define CAN_F10R2_FB28 0x10000000U
3073 #define CAN_F10R2_FB29 0x20000000U
3074 #define CAN_F10R2_FB30 0x40000000U
3075 #define CAN_F10R2_FB31 0x80000000U
3077 /******************* Bit definition for CAN_F11R2 register ******************/
3078 #define CAN_F11R2_FB0 0x00000001U
3079 #define CAN_F11R2_FB1 0x00000002U
3080 #define CAN_F11R2_FB2 0x00000004U
3081 #define CAN_F11R2_FB3 0x00000008U
3082 #define CAN_F11R2_FB4 0x00000010U
3083 #define CAN_F11R2_FB5 0x00000020U
3084 #define CAN_F11R2_FB6 0x00000040U
3085 #define CAN_F11R2_FB7 0x00000080U
3086 #define CAN_F11R2_FB8 0x00000100U
3087 #define CAN_F11R2_FB9 0x00000200U
3088 #define CAN_F11R2_FB10 0x00000400U
3089 #define CAN_F11R2_FB11 0x00000800U
3090 #define CAN_F11R2_FB12 0x00001000U
3091 #define CAN_F11R2_FB13 0x00002000U
3092 #define CAN_F11R2_FB14 0x00004000U
3093 #define CAN_F11R2_FB15 0x00008000U
3094 #define CAN_F11R2_FB16 0x00010000U
3095 #define CAN_F11R2_FB17 0x00020000U
3096 #define CAN_F11R2_FB18 0x00040000U
3097 #define CAN_F11R2_FB19 0x00080000U
3098 #define CAN_F11R2_FB20 0x00100000U
3099 #define CAN_F11R2_FB21 0x00200000U
3100 #define CAN_F11R2_FB22 0x00400000U
3101 #define CAN_F11R2_FB23 0x00800000U
3102 #define CAN_F11R2_FB24 0x01000000U
3103 #define CAN_F11R2_FB25 0x02000000U
3104 #define CAN_F11R2_FB26 0x04000000U
3105 #define CAN_F11R2_FB27 0x08000000U
3106 #define CAN_F11R2_FB28 0x10000000U
3107 #define CAN_F11R2_FB29 0x20000000U
3108 #define CAN_F11R2_FB30 0x40000000U
3109 #define CAN_F11R2_FB31 0x80000000U
3111 /******************* Bit definition for CAN_F12R2 register ******************/
3112 #define CAN_F12R2_FB0 0x00000001U
3113 #define CAN_F12R2_FB1 0x00000002U
3114 #define CAN_F12R2_FB2 0x00000004U
3115 #define CAN_F12R2_FB3 0x00000008U
3116 #define CAN_F12R2_FB4 0x00000010U
3117 #define CAN_F12R2_FB5 0x00000020U
3118 #define CAN_F12R2_FB6 0x00000040U
3119 #define CAN_F12R2_FB7 0x00000080U
3120 #define CAN_F12R2_FB8 0x00000100U
3121 #define CAN_F12R2_FB9 0x00000200U
3122 #define CAN_F12R2_FB10 0x00000400U
3123 #define CAN_F12R2_FB11 0x00000800U
3124 #define CAN_F12R2_FB12 0x00001000U
3125 #define CAN_F12R2_FB13 0x00002000U
3126 #define CAN_F12R2_FB14 0x00004000U
3127 #define CAN_F12R2_FB15 0x00008000U
3128 #define CAN_F12R2_FB16 0x00010000U
3129 #define CAN_F12R2_FB17 0x00020000U
3130 #define CAN_F12R2_FB18 0x00040000U
3131 #define CAN_F12R2_FB19 0x00080000U
3132 #define CAN_F12R2_FB20 0x00100000U
3133 #define CAN_F12R2_FB21 0x00200000U
3134 #define CAN_F12R2_FB22 0x00400000U
3135 #define CAN_F12R2_FB23 0x00800000U
3136 #define CAN_F12R2_FB24 0x01000000U
3137 #define CAN_F12R2_FB25 0x02000000U
3138 #define CAN_F12R2_FB26 0x04000000U
3139 #define CAN_F12R2_FB27 0x08000000U
3140 #define CAN_F12R2_FB28 0x10000000U
3141 #define CAN_F12R2_FB29 0x20000000U
3142 #define CAN_F12R2_FB30 0x40000000U
3143 #define CAN_F12R2_FB31 0x80000000U
3145 /******************* Bit definition for CAN_F13R2 register ******************/
3146 #define CAN_F13R2_FB0 0x00000001U
3147 #define CAN_F13R2_FB1 0x00000002U
3148 #define CAN_F13R2_FB2 0x00000004U
3149 #define CAN_F13R2_FB3 0x00000008U
3150 #define CAN_F13R2_FB4 0x00000010U
3151 #define CAN_F13R2_FB5 0x00000020U
3152 #define CAN_F13R2_FB6 0x00000040U
3153 #define CAN_F13R2_FB7 0x00000080U
3154 #define CAN_F13R2_FB8 0x00000100U
3155 #define CAN_F13R2_FB9 0x00000200U
3156 #define CAN_F13R2_FB10 0x00000400U
3157 #define CAN_F13R2_FB11 0x00000800U
3158 #define CAN_F13R2_FB12 0x00001000U
3159 #define CAN_F13R2_FB13 0x00002000U
3160 #define CAN_F13R2_FB14 0x00004000U
3161 #define CAN_F13R2_FB15 0x00008000U
3162 #define CAN_F13R2_FB16 0x00010000U
3163 #define CAN_F13R2_FB17 0x00020000U
3164 #define CAN_F13R2_FB18 0x00040000U
3165 #define CAN_F13R2_FB19 0x00080000U
3166 #define CAN_F13R2_FB20 0x00100000U
3167 #define CAN_F13R2_FB21 0x00200000U
3168 #define CAN_F13R2_FB22 0x00400000U
3169 #define CAN_F13R2_FB23 0x00800000U
3170 #define CAN_F13R2_FB24 0x01000000U
3171 #define CAN_F13R2_FB25 0x02000000U
3172 #define CAN_F13R2_FB26 0x04000000U
3173 #define CAN_F13R2_FB27 0x08000000U
3174 #define CAN_F13R2_FB28 0x10000000U
3175 #define CAN_F13R2_FB29 0x20000000U
3176 #define CAN_F13R2_FB30 0x40000000U
3177 #define CAN_F13R2_FB31 0x80000000U
3179 /******************************************************************************/
3180 /* */
3181 /* CRC calculation unit */
3182 /* */
3183 /******************************************************************************/
3184 /******************* Bit definition for CRC_DR register *********************/
3185 #define CRC_DR_DR 0xFFFFFFFFU
3188 /******************* Bit definition for CRC_IDR register ********************/
3189 #define CRC_IDR_IDR 0xFFU
3192 /******************** Bit definition for CRC_CR register ********************/
3193 #define CRC_CR_RESET 0x01U
3195 /******************************************************************************/
3196 /* */
3197 /* Crypto Processor */
3198 /* */
3199 /******************************************************************************/
3200 /******************* Bits definition for CRYP_CR register ********************/
3201 #define CRYP_CR_ALGODIR 0x00000004U
3202 
3203 #define CRYP_CR_ALGOMODE 0x00080038U
3204 #define CRYP_CR_ALGOMODE_0 0x00000008U
3205 #define CRYP_CR_ALGOMODE_1 0x00000010U
3206 #define CRYP_CR_ALGOMODE_2 0x00000020U
3207 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
3208 #define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
3209 #define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
3210 #define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
3211 #define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
3212 #define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
3213 #define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
3214 #define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
3215 
3216 #define CRYP_CR_DATATYPE 0x000000C0U
3217 #define CRYP_CR_DATATYPE_0 0x00000040U
3218 #define CRYP_CR_DATATYPE_1 0x00000080U
3219 #define CRYP_CR_KEYSIZE 0x00000300U
3220 #define CRYP_CR_KEYSIZE_0 0x00000100U
3221 #define CRYP_CR_KEYSIZE_1 0x00000200U
3222 #define CRYP_CR_FFLUSH 0x00004000U
3223 #define CRYP_CR_CRYPEN 0x00008000U
3224 
3225 #define CRYP_CR_GCM_CCMPH 0x00030000U
3226 #define CRYP_CR_GCM_CCMPH_0 0x00010000U
3227 #define CRYP_CR_GCM_CCMPH_1 0x00020000U
3228 #define CRYP_CR_ALGOMODE_3 0x00080000U
3229 
3230 /****************** Bits definition for CRYP_SR register *********************/
3231 #define CRYP_SR_IFEM 0x00000001U
3232 #define CRYP_SR_IFNF 0x00000002U
3233 #define CRYP_SR_OFNE 0x00000004U
3234 #define CRYP_SR_OFFU 0x00000008U
3235 #define CRYP_SR_BUSY 0x00000010U
3236 /****************** Bits definition for CRYP_DMACR register ******************/
3237 #define CRYP_DMACR_DIEN 0x00000001U
3238 #define CRYP_DMACR_DOEN 0x00000002U
3239 /***************** Bits definition for CRYP_IMSCR register ******************/
3240 #define CRYP_IMSCR_INIM 0x00000001U
3241 #define CRYP_IMSCR_OUTIM 0x00000002U
3242 /****************** Bits definition for CRYP_RISR register *******************/
3243 #define CRYP_RISR_OUTRIS 0x00000001U
3244 #define CRYP_RISR_INRIS 0x00000002U
3245 /****************** Bits definition for CRYP_MISR register *******************/
3246 #define CRYP_MISR_INMIS 0x00000001U
3247 #define CRYP_MISR_OUTMIS 0x00000002U
3248 
3249 /******************************************************************************/
3250 /* */
3251 /* Digital to Analog Converter */
3252 /* */
3253 /******************************************************************************/
3254 /******************** Bit definition for DAC_CR register ********************/
3255 #define DAC_CR_EN1 0x00000001U
3256 #define DAC_CR_BOFF1 0x00000002U
3257 #define DAC_CR_TEN1 0x00000004U
3259 #define DAC_CR_TSEL1 0x00000038U
3260 #define DAC_CR_TSEL1_0 0x00000008U
3261 #define DAC_CR_TSEL1_1 0x00000010U
3262 #define DAC_CR_TSEL1_2 0x00000020U
3264 #define DAC_CR_WAVE1 0x000000C0U
3265 #define DAC_CR_WAVE1_0 0x00000040U
3266 #define DAC_CR_WAVE1_1 0x00000080U
3268 #define DAC_CR_MAMP1 0x00000F00U
3269 #define DAC_CR_MAMP1_0 0x00000100U
3270 #define DAC_CR_MAMP1_1 0x00000200U
3271 #define DAC_CR_MAMP1_2 0x00000400U
3272 #define DAC_CR_MAMP1_3 0x00000800U
3274 #define DAC_CR_DMAEN1 0x00001000U
3275 #define DAC_CR_DMAUDRIE1 0x00002000U
3276 #define DAC_CR_EN2 0x00010000U
3277 #define DAC_CR_BOFF2 0x00020000U
3278 #define DAC_CR_TEN2 0x00040000U
3280 #define DAC_CR_TSEL2 0x00380000U
3281 #define DAC_CR_TSEL2_0 0x00080000U
3282 #define DAC_CR_TSEL2_1 0x00100000U
3283 #define DAC_CR_TSEL2_2 0x00200000U
3285 #define DAC_CR_WAVE2 0x00C00000U
3286 #define DAC_CR_WAVE2_0 0x00400000U
3287 #define DAC_CR_WAVE2_1 0x00800000U
3289 #define DAC_CR_MAMP2 0x0F000000U
3290 #define DAC_CR_MAMP2_0 0x01000000U
3291 #define DAC_CR_MAMP2_1 0x02000000U
3292 #define DAC_CR_MAMP2_2 0x04000000U
3293 #define DAC_CR_MAMP2_3 0x08000000U
3295 #define DAC_CR_DMAEN2 0x10000000U
3296 #define DAC_CR_DMAUDRIE2 0x20000000U
3298 /***************** Bit definition for DAC_SWTRIGR register ******************/
3299 #define DAC_SWTRIGR_SWTRIG1 0x01U
3300 #define DAC_SWTRIGR_SWTRIG2 0x02U
3302 /***************** Bit definition for DAC_DHR12R1 register ******************/
3303 #define DAC_DHR12R1_DACC1DHR 0x0FFFU
3305 /***************** Bit definition for DAC_DHR12L1 register ******************/
3306 #define DAC_DHR12L1_DACC1DHR 0xFFF0U
3308 /****************** Bit definition for DAC_DHR8R1 register ******************/
3309 #define DAC_DHR8R1_DACC1DHR 0xFFU
3311 /***************** Bit definition for DAC_DHR12R2 register ******************/
3312 #define DAC_DHR12R2_DACC2DHR 0x0FFFU
3314 /***************** Bit definition for DAC_DHR12L2 register ******************/
3315 #define DAC_DHR12L2_DACC2DHR 0xFFF0U
3317 /****************** Bit definition for DAC_DHR8R2 register ******************/
3318 #define DAC_DHR8R2_DACC2DHR 0xFFU
3320 /***************** Bit definition for DAC_DHR12RD register ******************/
3321 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU
3322 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U
3324 /***************** Bit definition for DAC_DHR12LD register ******************/
3325 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U
3326 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U
3328 /****************** Bit definition for DAC_DHR8RD register ******************/
3329 #define DAC_DHR8RD_DACC1DHR 0x00FFU
3330 #define DAC_DHR8RD_DACC2DHR 0xFF00U
3332 /******************* Bit definition for DAC_DOR1 register *******************/
3333 #define DAC_DOR1_DACC1DOR 0x0FFFU
3335 /******************* Bit definition for DAC_DOR2 register *******************/
3336 #define DAC_DOR2_DACC2DOR 0x0FFFU
3338 /******************** Bit definition for DAC_SR register ********************/
3339 #define DAC_SR_DMAUDR1 0x00002000U
3340 #define DAC_SR_DMAUDR2 0x20000000U
3342 /******************************************************************************/
3343 /* */
3344 /* Debug MCU */
3345 /* */
3346 /******************************************************************************/
3347 
3348 /******************************************************************************/
3349 /* */
3350 /* DCMI */
3351 /* */
3352 /******************************************************************************/
3353 /******************** Bits definition for DCMI_CR register ******************/
3354 #define DCMI_CR_CAPTURE 0x00000001U
3355 #define DCMI_CR_CM 0x00000002U
3356 #define DCMI_CR_CROP 0x00000004U
3357 #define DCMI_CR_JPEG 0x00000008U
3358 #define DCMI_CR_ESS 0x00000010U
3359 #define DCMI_CR_PCKPOL 0x00000020U
3360 #define DCMI_CR_HSPOL 0x00000040U
3361 #define DCMI_CR_VSPOL 0x00000080U
3362 #define DCMI_CR_FCRC_0 0x00000100U
3363 #define DCMI_CR_FCRC_1 0x00000200U
3364 #define DCMI_CR_EDM_0 0x00000400U
3365 #define DCMI_CR_EDM_1 0x00000800U
3366 #define DCMI_CR_OUTEN 0x00002000U
3367 #define DCMI_CR_ENABLE 0x00004000U
3368 #define DCMI_CR_BSM_0 0x00010000U
3369 #define DCMI_CR_BSM_1 0x00020000U
3370 #define DCMI_CR_OEBS 0x00040000U
3371 #define DCMI_CR_LSM 0x00080000U
3372 #define DCMI_CR_OELS 0x00100000U
3373 
3374 /******************** Bits definition for DCMI_SR register ******************/
3375 #define DCMI_SR_HSYNC 0x00000001U
3376 #define DCMI_SR_VSYNC 0x00000002U
3377 #define DCMI_SR_FNE 0x00000004U
3378 
3379 /******************** Bits definition for DCMI_RIS register *****************/
3380 #define DCMI_RIS_FRAME_RIS 0x00000001U
3381 #define DCMI_RIS_OVR_RIS 0x00000002U
3382 #define DCMI_RIS_ERR_RIS 0x00000004U
3383 #define DCMI_RIS_VSYNC_RIS 0x00000008U
3384 #define DCMI_RIS_LINE_RIS 0x00000010U
3385 /* Legacy defines */
3386 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
3387 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
3388 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
3389 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
3390 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
3391 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
3392 
3393 /******************** Bits definition for DCMI_IER register *****************/
3394 #define DCMI_IER_FRAME_IE 0x00000001U
3395 #define DCMI_IER_OVR_IE 0x00000002U
3396 #define DCMI_IER_ERR_IE 0x00000004U
3397 #define DCMI_IER_VSYNC_IE 0x00000008U
3398 #define DCMI_IER_LINE_IE 0x00000010U
3399 /* Legacy defines */
3400 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
3401 
3402 /******************** Bits definition for DCMI_MIS register *****************/
3403 #define DCMI_MIS_FRAME_MIS 0x00000001U
3404 #define DCMI_MIS_OVR_MIS 0x00000002U
3405 #define DCMI_MIS_ERR_MIS 0x00000004U
3406 #define DCMI_MIS_VSYNC_MIS 0x00000008U
3407 #define DCMI_MIS_LINE_MIS 0x00000010U
3408 
3409 /* Legacy defines */
3410 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
3411 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
3412 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
3413 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
3414 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
3415 
3416 /******************** Bits definition for DCMI_ICR register *****************/
3417 #define DCMI_ICR_FRAME_ISC 0x00000001U
3418 #define DCMI_ICR_OVR_ISC 0x00000002U
3419 #define DCMI_ICR_ERR_ISC 0x00000004U
3420 #define DCMI_ICR_VSYNC_ISC 0x00000008U
3421 #define DCMI_ICR_LINE_ISC 0x00000010U
3422 
3423 /* Legacy defines */
3424 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
3425 
3426 /******************** Bits definition for DCMI_ESCR register ******************/
3427 #define DCMI_ESCR_FSC 0x000000FFU
3428 #define DCMI_ESCR_LSC 0x0000FF00U
3429 #define DCMI_ESCR_LEC 0x00FF0000U
3430 #define DCMI_ESCR_FEC 0xFF000000U
3431 
3432 /******************** Bits definition for DCMI_ESUR register ******************/
3433 #define DCMI_ESUR_FSU 0x000000FFU
3434 #define DCMI_ESUR_LSU 0x0000FF00U
3435 #define DCMI_ESUR_LEU 0x00FF0000U
3436 #define DCMI_ESUR_FEU 0xFF000000U
3437 
3438 /******************** Bits definition for DCMI_CWSTRT register ******************/
3439 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
3440 #define DCMI_CWSTRT_VST 0x1FFF0000U
3441 
3442 /******************** Bits definition for DCMI_CWSIZE register ******************/
3443 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
3444 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
3445 
3446 /******************** Bits definition for DCMI_DR register *********************/
3447 #define DCMI_DR_BYTE0 0x000000FFU
3448 #define DCMI_DR_BYTE1 0x0000FF00U
3449 #define DCMI_DR_BYTE2 0x00FF0000U
3450 #define DCMI_DR_BYTE3 0xFF000000U
3451 
3452 /******************************************************************************/
3453 /* */
3454 /* DMA Controller */
3455 /* */
3456 /******************************************************************************/
3457 /******************** Bits definition for DMA_SxCR register *****************/
3458 #define DMA_SxCR_CHSEL 0x0E000000U
3459 #define DMA_SxCR_CHSEL_0 0x02000000U
3460 #define DMA_SxCR_CHSEL_1 0x04000000U
3461 #define DMA_SxCR_CHSEL_2 0x08000000U
3462 #define DMA_SxCR_MBURST 0x01800000U
3463 #define DMA_SxCR_MBURST_0 0x00800000U
3464 #define DMA_SxCR_MBURST_1 0x01000000U
3465 #define DMA_SxCR_PBURST 0x00600000U
3466 #define DMA_SxCR_PBURST_0 0x00200000U
3467 #define DMA_SxCR_PBURST_1 0x00400000U
3468 #define DMA_SxCR_CT 0x00080000U
3469 #define DMA_SxCR_DBM 0x00040000U
3470 #define DMA_SxCR_PL 0x00030000U
3471 #define DMA_SxCR_PL_0 0x00010000U
3472 #define DMA_SxCR_PL_1 0x00020000U
3473 #define DMA_SxCR_PINCOS 0x00008000U
3474 #define DMA_SxCR_MSIZE 0x00006000U
3475 #define DMA_SxCR_MSIZE_0 0x00002000U
3476 #define DMA_SxCR_MSIZE_1 0x00004000U
3477 #define DMA_SxCR_PSIZE 0x00001800U
3478 #define DMA_SxCR_PSIZE_0 0x00000800U
3479 #define DMA_SxCR_PSIZE_1 0x00001000U
3480 #define DMA_SxCR_MINC 0x00000400U
3481 #define DMA_SxCR_PINC 0x00000200U
3482 #define DMA_SxCR_CIRC 0x00000100U
3483 #define DMA_SxCR_DIR 0x000000C0U
3484 #define DMA_SxCR_DIR_0 0x00000040U
3485 #define DMA_SxCR_DIR_1 0x00000080U
3486 #define DMA_SxCR_PFCTRL 0x00000020U
3487 #define DMA_SxCR_TCIE 0x00000010U
3488 #define DMA_SxCR_HTIE 0x00000008U
3489 #define DMA_SxCR_TEIE 0x00000004U
3490 #define DMA_SxCR_DMEIE 0x00000002U
3491 #define DMA_SxCR_EN 0x00000001U
3492 
3493 /* Legacy defines */
3494 #define DMA_SxCR_ACK 0x00100000U
3495 
3496 /******************** Bits definition for DMA_SxCNDTR register **************/
3497 #define DMA_SxNDT 0x0000FFFFU
3498 #define DMA_SxNDT_0 0x00000001U
3499 #define DMA_SxNDT_1 0x00000002U
3500 #define DMA_SxNDT_2 0x00000004U
3501 #define DMA_SxNDT_3 0x00000008U
3502 #define DMA_SxNDT_4 0x00000010U
3503 #define DMA_SxNDT_5 0x00000020U
3504 #define DMA_SxNDT_6 0x00000040U
3505 #define DMA_SxNDT_7 0x00000080U
3506 #define DMA_SxNDT_8 0x00000100U
3507 #define DMA_SxNDT_9 0x00000200U
3508 #define DMA_SxNDT_10 0x00000400U
3509 #define DMA_SxNDT_11 0x00000800U
3510 #define DMA_SxNDT_12 0x00001000U
3511 #define DMA_SxNDT_13 0x00002000U
3512 #define DMA_SxNDT_14 0x00004000U
3513 #define DMA_SxNDT_15 0x00008000U
3514 
3515 /******************** Bits definition for DMA_SxFCR register ****************/
3516 #define DMA_SxFCR_FEIE 0x00000080U
3517 #define DMA_SxFCR_FS 0x00000038U
3518 #define DMA_SxFCR_FS_0 0x00000008U
3519 #define DMA_SxFCR_FS_1 0x00000010U
3520 #define DMA_SxFCR_FS_2 0x00000020U
3521 #define DMA_SxFCR_DMDIS 0x00000004U
3522 #define DMA_SxFCR_FTH 0x00000003U
3523 #define DMA_SxFCR_FTH_0 0x00000001U
3524 #define DMA_SxFCR_FTH_1 0x00000002U
3525 
3526 /******************** Bits definition for DMA_LISR register *****************/
3527 #define DMA_LISR_TCIF3 0x08000000U
3528 #define DMA_LISR_HTIF3 0x04000000U
3529 #define DMA_LISR_TEIF3 0x02000000U
3530 #define DMA_LISR_DMEIF3 0x01000000U
3531 #define DMA_LISR_FEIF3 0x00400000U
3532 #define DMA_LISR_TCIF2 0x00200000U
3533 #define DMA_LISR_HTIF2 0x00100000U
3534 #define DMA_LISR_TEIF2 0x00080000U
3535 #define DMA_LISR_DMEIF2 0x00040000U
3536 #define DMA_LISR_FEIF2 0x00010000U
3537 #define DMA_LISR_TCIF1 0x00000800U
3538 #define DMA_LISR_HTIF1 0x00000400U
3539 #define DMA_LISR_TEIF1 0x00000200U
3540 #define DMA_LISR_DMEIF1 0x00000100U
3541 #define DMA_LISR_FEIF1 0x00000040U
3542 #define DMA_LISR_TCIF0 0x00000020U
3543 #define DMA_LISR_HTIF0 0x00000010U
3544 #define DMA_LISR_TEIF0 0x00000008U
3545 #define DMA_LISR_DMEIF0 0x00000004U
3546 #define DMA_LISR_FEIF0 0x00000001U
3547 
3548 /******************** Bits definition for DMA_HISR register *****************/
3549 #define DMA_HISR_TCIF7 0x08000000U
3550 #define DMA_HISR_HTIF7 0x04000000U
3551 #define DMA_HISR_TEIF7 0x02000000U
3552 #define DMA_HISR_DMEIF7 0x01000000U
3553 #define DMA_HISR_FEIF7 0x00400000U
3554 #define DMA_HISR_TCIF6 0x00200000U
3555 #define DMA_HISR_HTIF6 0x00100000U
3556 #define DMA_HISR_TEIF6 0x00080000U
3557 #define DMA_HISR_DMEIF6 0x00040000U
3558 #define DMA_HISR_FEIF6 0x00010000U
3559 #define DMA_HISR_TCIF5 0x00000800U
3560 #define DMA_HISR_HTIF5 0x00000400U
3561 #define DMA_HISR_TEIF5 0x00000200U
3562 #define DMA_HISR_DMEIF5 0x00000100U
3563 #define DMA_HISR_FEIF5 0x00000040U
3564 #define DMA_HISR_TCIF4 0x00000020U
3565 #define DMA_HISR_HTIF4 0x00000010U
3566 #define DMA_HISR_TEIF4 0x00000008U
3567 #define DMA_HISR_DMEIF4 0x00000004U
3568 #define DMA_HISR_FEIF4 0x00000001U
3569 
3570 /******************** Bits definition for DMA_LIFCR register ****************/
3571 #define DMA_LIFCR_CTCIF3 0x08000000U
3572 #define DMA_LIFCR_CHTIF3 0x04000000U
3573 #define DMA_LIFCR_CTEIF3 0x02000000U
3574 #define DMA_LIFCR_CDMEIF3 0x01000000U
3575 #define DMA_LIFCR_CFEIF3 0x00400000U
3576 #define DMA_LIFCR_CTCIF2 0x00200000U
3577 #define DMA_LIFCR_CHTIF2 0x00100000U
3578 #define DMA_LIFCR_CTEIF2 0x00080000U
3579 #define DMA_LIFCR_CDMEIF2 0x00040000U
3580 #define DMA_LIFCR_CFEIF2 0x00010000U
3581 #define DMA_LIFCR_CTCIF1 0x00000800U
3582 #define DMA_LIFCR_CHTIF1 0x00000400U
3583 #define DMA_LIFCR_CTEIF1 0x00000200U
3584 #define DMA_LIFCR_CDMEIF1 0x00000100U
3585 #define DMA_LIFCR_CFEIF1 0x00000040U
3586 #define DMA_LIFCR_CTCIF0 0x00000020U
3587 #define DMA_LIFCR_CHTIF0 0x00000010U
3588 #define DMA_LIFCR_CTEIF0 0x00000008U
3589 #define DMA_LIFCR_CDMEIF0 0x00000004U
3590 #define DMA_LIFCR_CFEIF0 0x00000001U
3591 
3592 /******************** Bits definition for DMA_HIFCR register ****************/
3593 #define DMA_HIFCR_CTCIF7 0x08000000U
3594 #define DMA_HIFCR_CHTIF7 0x04000000U
3595 #define DMA_HIFCR_CTEIF7 0x02000000U
3596 #define DMA_HIFCR_CDMEIF7 0x01000000U
3597 #define DMA_HIFCR_CFEIF7 0x00400000U
3598 #define DMA_HIFCR_CTCIF6 0x00200000U
3599 #define DMA_HIFCR_CHTIF6 0x00100000U
3600 #define DMA_HIFCR_CTEIF6 0x00080000U
3601 #define DMA_HIFCR_CDMEIF6 0x00040000U
3602 #define DMA_HIFCR_CFEIF6 0x00010000U
3603 #define DMA_HIFCR_CTCIF5 0x00000800U
3604 #define DMA_HIFCR_CHTIF5 0x00000400U
3605 #define DMA_HIFCR_CTEIF5 0x00000200U
3606 #define DMA_HIFCR_CDMEIF5 0x00000100U
3607 #define DMA_HIFCR_CFEIF5 0x00000040U
3608 #define DMA_HIFCR_CTCIF4 0x00000020U
3609 #define DMA_HIFCR_CHTIF4 0x00000010U
3610 #define DMA_HIFCR_CTEIF4 0x00000008U
3611 #define DMA_HIFCR_CDMEIF4 0x00000004U
3612 #define DMA_HIFCR_CFEIF4 0x00000001U
3613 
3614 
3615 /******************************************************************************/
3616 /* */
3617 /* AHB Master DMA2D Controller (DMA2D) */
3618 /* */
3619 /******************************************************************************/
3620 
3621 /******************** Bit definition for DMA2D_CR register ******************/
3622 
3623 #define DMA2D_CR_START 0x00000001U
3624 #define DMA2D_CR_SUSP 0x00000002U
3625 #define DMA2D_CR_ABORT 0x00000004U
3626 #define DMA2D_CR_TEIE 0x00000100U
3627 #define DMA2D_CR_TCIE 0x00000200U
3628 #define DMA2D_CR_TWIE 0x00000400U
3629 #define DMA2D_CR_CAEIE 0x00000800U
3630 #define DMA2D_CR_CTCIE 0x00001000U
3631 #define DMA2D_CR_CEIE 0x00002000U
3632 #define DMA2D_CR_MODE 0x00030000U
3633 #define DMA2D_CR_MODE_0 0x00010000U
3634 #define DMA2D_CR_MODE_1 0x00020000U
3636 /******************** Bit definition for DMA2D_ISR register *****************/
3637 
3638 #define DMA2D_ISR_TEIF 0x00000001U
3639 #define DMA2D_ISR_TCIF 0x00000002U
3640 #define DMA2D_ISR_TWIF 0x00000004U
3641 #define DMA2D_ISR_CAEIF 0x00000008U
3642 #define DMA2D_ISR_CTCIF 0x00000010U
3643 #define DMA2D_ISR_CEIF 0x00000020U
3645 /******************** Bit definition for DMA2D_IFCR register ****************/
3646 
3647 #define DMA2D_IFCR_CTEIF 0x00000001U
3648 #define DMA2D_IFCR_CTCIF 0x00000002U
3649 #define DMA2D_IFCR_CTWIF 0x00000004U
3650 #define DMA2D_IFCR_CAECIF 0x00000008U
3651 #define DMA2D_IFCR_CCTCIF 0x00000010U
3652 #define DMA2D_IFCR_CCEIF 0x00000020U
3654 /* Legacy defines */
3655 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
3656 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
3657 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
3658 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
3659 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
3660 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
3662 /******************** Bit definition for DMA2D_FGMAR register ***************/
3663 
3664 #define DMA2D_FGMAR_MA 0xFFFFFFFFU
3666 /******************** Bit definition for DMA2D_FGOR register ****************/
3667 
3668 #define DMA2D_FGOR_LO 0x00003FFFU
3670 /******************** Bit definition for DMA2D_BGMAR register ***************/
3671 
3672 #define DMA2D_BGMAR_MA 0xFFFFFFFFU
3674 /******************** Bit definition for DMA2D_BGOR register ****************/
3675 
3676 #define DMA2D_BGOR_LO 0x00003FFFU
3678 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3679 
3680 #define DMA2D_FGPFCCR_CM 0x0000000FU
3681 #define DMA2D_FGPFCCR_CM_0 0x00000001U
3682 #define DMA2D_FGPFCCR_CM_1 0x00000002U
3683 #define DMA2D_FGPFCCR_CM_2 0x00000004U
3684 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3685 #define DMA2D_FGPFCCR_CCM 0x00000010U
3686 #define DMA2D_FGPFCCR_START 0x00000020U
3687 #define DMA2D_FGPFCCR_CS 0x0000FF00U
3688 #define DMA2D_FGPFCCR_AM 0x00030000U
3689 #define DMA2D_FGPFCCR_AM_0 0x00010000U
3690 #define DMA2D_FGPFCCR_AM_1 0x00020000U
3691 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U
3693 /******************** Bit definition for DMA2D_FGCOLR register **************/
3694 
3695 #define DMA2D_FGCOLR_BLUE 0x000000FFU
3696 #define DMA2D_FGCOLR_GREEN 0x0000FF00U
3697 #define DMA2D_FGCOLR_RED 0x00FF0000U
3699 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3700 
3701 #define DMA2D_BGPFCCR_CM 0x0000000FU
3702 #define DMA2D_BGPFCCR_CM_0 0x00000001U
3703 #define DMA2D_BGPFCCR_CM_1 0x00000002U
3704 #define DMA2D_BGPFCCR_CM_2 0x00000004U
3705 #define DMA2D_FGPFCCR_CM_3 0x00000008U
3706 #define DMA2D_BGPFCCR_CCM 0x00000010U
3707 #define DMA2D_BGPFCCR_START 0x00000020U
3708 #define DMA2D_BGPFCCR_CS 0x0000FF00U
3709 #define DMA2D_BGPFCCR_AM 0x00030000U
3710 #define DMA2D_BGPFCCR_AM_0 0x00010000U
3711 #define DMA2D_BGPFCCR_AM_1 0x00020000U
3712 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U
3714 /******************** Bit definition for DMA2D_BGCOLR register **************/
3715 
3716 #define DMA2D_BGCOLR_BLUE 0x000000FFU
3717 #define DMA2D_BGCOLR_GREEN 0x0000FF00U
3718 #define DMA2D_BGCOLR_RED 0x00FF0000U
3720 /******************** Bit definition for DMA2D_FGCMAR register **************/
3721 
3722 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU
3724 /******************** Bit definition for DMA2D_BGCMAR register **************/
3725 
3726 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU
3728 /******************** Bit definition for DMA2D_OPFCCR register **************/
3729 
3730 #define DMA2D_OPFCCR_CM 0x00000007U
3731 #define DMA2D_OPFCCR_CM_0 0x00000001U
3732 #define DMA2D_OPFCCR_CM_1 0x00000002U
3733 #define DMA2D_OPFCCR_CM_2 0x00000004U
3735 /******************** Bit definition for DMA2D_OCOLR register ***************/
3736 
3739 #define DMA2D_OCOLR_BLUE_1 0x000000FFU
3740 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U
3741 #define DMA2D_OCOLR_RED_1 0x00FF0000U
3742 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U
3745 #define DMA2D_OCOLR_BLUE_2 0x0000001FU
3746 #define DMA2D_OCOLR_GREEN_2 0x000007E0U
3747 #define DMA2D_OCOLR_RED_2 0x0000F800U
3750 #define DMA2D_OCOLR_BLUE_3 0x0000001FU
3751 #define DMA2D_OCOLR_GREEN_3 0x000003E0U
3752 #define DMA2D_OCOLR_RED_3 0x00007C00U
3753 #define DMA2D_OCOLR_ALPHA_3 0x00008000U
3756 #define DMA2D_OCOLR_BLUE_4 0x0000000FU
3757 #define DMA2D_OCOLR_GREEN_4 0x000000F0U
3758 #define DMA2D_OCOLR_RED_4 0x00000F00U
3759 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U
3761 /******************** Bit definition for DMA2D_OMAR register ****************/
3762 
3763 #define DMA2D_OMAR_MA 0xFFFFFFFFU
3765 /******************** Bit definition for DMA2D_OOR register *****************/
3766 
3767 #define DMA2D_OOR_LO 0x00003FFFU
3769 /******************** Bit definition for DMA2D_NLR register *****************/
3770 
3771 #define DMA2D_NLR_NL 0x0000FFFFU
3772 #define DMA2D_NLR_PL 0x3FFF0000U
3774 /******************** Bit definition for DMA2D_LWR register *****************/
3775 
3776 #define DMA2D_LWR_LW 0x0000FFFFU
3778 /******************** Bit definition for DMA2D_AMTCR register ***************/
3779 
3780 #define DMA2D_AMTCR_EN 0x00000001U
3781 #define DMA2D_AMTCR_DT 0x0000FF00U
3783 /******************** Bit definition for DMA2D_FGCLUT register **************/
3784 
3785 /******************** Bit definition for DMA2D_BGCLUT register **************/
3786 
3787 
3788 /******************************************************************************/
3789 /* */
3790 /* Display Serial Interface (DSI) */
3791 /* */
3792 /******************************************************************************/
3793 /******************* Bit definition for DSI_VR register *****************/
3794 #define DSI_VR 0x3133302AU
3796 /******************* Bit definition for DSI_CR register *****************/
3797 #define DSI_CR_EN 0x00000001U
3799 /******************* Bit definition for DSI_CCR register ****************/
3800 #define DSI_CCR_TXECKDIV 0x000000FFU
3801 #define DSI_CCR_TXECKDIV0 0x00000001U
3802 #define DSI_CCR_TXECKDIV1 0x00000002U
3803 #define DSI_CCR_TXECKDIV2 0x00000004U
3804 #define DSI_CCR_TXECKDIV3 0x00000008U
3805 #define DSI_CCR_TXECKDIV4 0x00000010U
3806 #define DSI_CCR_TXECKDIV5 0x00000020U
3807 #define DSI_CCR_TXECKDIV6 0x00000040U
3808 #define DSI_CCR_TXECKDIV7 0x00000080U
3809 
3810 #define DSI_CCR_TOCKDIV 0x0000FF00U
3811 #define DSI_CCR_TOCKDIV0 0x00000100U
3812 #define DSI_CCR_TOCKDIV1 0x00000200U
3813 #define DSI_CCR_TOCKDIV2 0x00000400U
3814 #define DSI_CCR_TOCKDIV3 0x00000800U
3815 #define DSI_CCR_TOCKDIV4 0x00001000U
3816 #define DSI_CCR_TOCKDIV5 0x00002000U
3817 #define DSI_CCR_TOCKDIV6 0x00004000U
3818 #define DSI_CCR_TOCKDIV7 0x00008000U
3819 
3820 /******************* Bit definition for DSI_LVCIDR register *************/
3821 #define DSI_LVCIDR_VCID 0x00000003U
3822 #define DSI_LVCIDR_VCID0 0x00000001U
3823 #define DSI_LVCIDR_VCID1 0x00000002U
3824 
3825 /******************* Bit definition for DSI_LCOLCR register *************/
3826 #define DSI_LCOLCR_COLC 0x0000000FU
3827 #define DSI_LCOLCR_COLC0 0x00000001U
3828 #define DSI_LCOLCR_COLC1 0x00000020U
3829 #define DSI_LCOLCR_COLC2 0x00000040U
3830 #define DSI_LCOLCR_COLC3 0x00000080U
3831 
3832 #define DSI_LCOLCR_LPE 0x00000100U
3834 /******************* Bit definition for DSI_LPCR register ***************/
3835 #define DSI_LPCR_DEP 0x00000001U
3836 #define DSI_LPCR_VSP 0x00000002U
3837 #define DSI_LPCR_HSP 0x00000004U
3839 /******************* Bit definition for DSI_LPMCR register **************/
3840 #define DSI_LPMCR_VLPSIZE 0x000000FFU
3841 #define DSI_LPMCR_VLPSIZE0 0x00000001U
3842 #define DSI_LPMCR_VLPSIZE1 0x00000002U
3843 #define DSI_LPMCR_VLPSIZE2 0x00000004U
3844 #define DSI_LPMCR_VLPSIZE3 0x00000008U
3845 #define DSI_LPMCR_VLPSIZE4 0x00000010U
3846 #define DSI_LPMCR_VLPSIZE5 0x00000020U
3847 #define DSI_LPMCR_VLPSIZE6 0x00000040U
3848 #define DSI_LPMCR_VLPSIZE7 0x00000080U
3849 
3850 #define DSI_LPMCR_LPSIZE 0x00FF0000U
3851 #define DSI_LPMCR_LPSIZE0 0x00010000U
3852 #define DSI_LPMCR_LPSIZE1 0x00020000U
3853 #define DSI_LPMCR_LPSIZE2 0x00040000U
3854 #define DSI_LPMCR_LPSIZE3 0x00080000U
3855 #define DSI_LPMCR_LPSIZE4 0x00100000U
3856 #define DSI_LPMCR_LPSIZE5 0x00200000U
3857 #define DSI_LPMCR_LPSIZE6 0x00400000U
3858 #define DSI_LPMCR_LPSIZE7 0x00800000U
3859 
3860 /******************* Bit definition for DSI_PCR register ****************/
3861 #define DSI_PCR_ETTXE 0x00000001U
3862 #define DSI_PCR_ETRXE 0x00000002U
3863 #define DSI_PCR_BTAE 0x00000004U
3864 #define DSI_PCR_ECCRXE 0x00000008U
3865 #define DSI_PCR_CRCRXE 0x00000010U
3867 /******************* Bit definition for DSI_GVCIDR register *************/
3868 #define DSI_GVCIDR_VCID 0x00000003U
3869 #define DSI_GVCIDR_VCID0 0x00000001U
3870 #define DSI_GVCIDR_VCID1 0x00000002U
3871 
3872 /******************* Bit definition for DSI_MCR register ****************/
3873 #define DSI_MCR_CMDM 0x00000001U
3875 /******************* Bit definition for DSI_VMCR register ***************/
3876 #define DSI_VMCR_VMT 0x00000003U
3877 #define DSI_VMCR_VMT0 0x00000001U
3878 #define DSI_VMCR_VMT1 0x00000002U
3879 
3880 #define DSI_VMCR_LPVSAE 0x00000100U
3881 #define DSI_VMCR_LPVBPE 0x00000200U
3882 #define DSI_VMCR_LPVFPE 0x00000400U
3883 #define DSI_VMCR_LPVAE 0x00000800U
3884 #define DSI_VMCR_LPHBPE 0x00001000U
3885 #define DSI_VMCR_LPHFPE 0x00002000U
3886 #define DSI_VMCR_FBTAAE 0x00004000U
3887 #define DSI_VMCR_LPCE 0x00008000U
3888 #define DSI_VMCR_PGE 0x00010000U
3889 #define DSI_VMCR_PGM 0x00100000U
3890 #define DSI_VMCR_PGO 0x01000000U
3892 /******************* Bit definition for DSI_VPCR register ***************/
3893 #define DSI_VPCR_VPSIZE 0x00003FFFU
3894 #define DSI_VPCR_VPSIZE0 0x00000001U
3895 #define DSI_VPCR_VPSIZE1 0x00000002U
3896 #define DSI_VPCR_VPSIZE2 0x00000004U
3897 #define DSI_VPCR_VPSIZE3 0x00000008U
3898 #define DSI_VPCR_VPSIZE4 0x00000010U
3899 #define DSI_VPCR_VPSIZE5 0x00000020U
3900 #define DSI_VPCR_VPSIZE6 0x00000040U
3901 #define DSI_VPCR_VPSIZE7 0x00000080U
3902 #define DSI_VPCR_VPSIZE8 0x00000100U
3903 #define DSI_VPCR_VPSIZE9 0x00000200U
3904 #define DSI_VPCR_VPSIZE10 0x00000400U
3905 #define DSI_VPCR_VPSIZE11 0x00000800U
3906 #define DSI_VPCR_VPSIZE12 0x00001000U
3907 #define DSI_VPCR_VPSIZE13 0x00002000U
3908 
3909 /******************* Bit definition for DSI_VCCR register ***************/
3910 #define DSI_VCCR_NUMC 0x00001FFFU
3911 #define DSI_VCCR_NUMC0 0x00000001U
3912 #define DSI_VCCR_NUMC1 0x00000002U
3913 #define DSI_VCCR_NUMC2 0x00000004U
3914 #define DSI_VCCR_NUMC3 0x00000008U
3915 #define DSI_VCCR_NUMC4 0x00000010U
3916 #define DSI_VCCR_NUMC5 0x00000020U
3917 #define DSI_VCCR_NUMC6 0x00000040U
3918 #define DSI_VCCR_NUMC7 0x00000080U
3919 #define DSI_VCCR_NUMC8 0x00000100U
3920 #define DSI_VCCR_NUMC9 0x00000200U
3921 #define DSI_VCCR_NUMC10 0x00000400U
3922 #define DSI_VCCR_NUMC11 0x00000800U
3923 #define DSI_VCCR_NUMC12 0x00001000U
3924 
3925 /******************* Bit definition for DSI_VNPCR register **************/
3926 #define DSI_VNPCR_NPSIZE 0x00001FFFU
3927 #define DSI_VNPCR_NPSIZE0 0x00000001U
3928 #define DSI_VNPCR_NPSIZE1 0x00000002U
3929 #define DSI_VNPCR_NPSIZE2 0x00000004U
3930 #define DSI_VNPCR_NPSIZE3 0x00000008U
3931 #define DSI_VNPCR_NPSIZE4 0x00000010U
3932 #define DSI_VNPCR_NPSIZE5 0x00000020U
3933 #define DSI_VNPCR_NPSIZE6 0x00000040U
3934 #define DSI_VNPCR_NPSIZE7 0x00000080U
3935 #define DSI_VNPCR_NPSIZE8 0x00000100U
3936 #define DSI_VNPCR_NPSIZE9 0x00000200U
3937 #define DSI_VNPCR_NPSIZE10 0x00000400U
3938 #define DSI_VNPCR_NPSIZE11 0x00000800U
3939 #define DSI_VNPCR_NPSIZE12 0x00001000U
3940 
3941 /******************* Bit definition for DSI_VHSACR register *************/
3942 #define DSI_VHSACR_HSA 0x00000FFFU
3943 #define DSI_VHSACR_HSA0 0x00000001U
3944 #define DSI_VHSACR_HSA1 0x00000002U
3945 #define DSI_VHSACR_HSA2 0x00000004U
3946 #define DSI_VHSACR_HSA3 0x00000008U
3947 #define DSI_VHSACR_HSA4 0x00000010U
3948 #define DSI_VHSACR_HSA5 0x00000020U
3949 #define DSI_VHSACR_HSA6 0x00000040U
3950 #define DSI_VHSACR_HSA7 0x00000080U
3951 #define DSI_VHSACR_HSA8 0x00000100U
3952 #define DSI_VHSACR_HSA9 0x00000200U
3953 #define DSI_VHSACR_HSA10 0x00000400U
3954 #define DSI_VHSACR_HSA11 0x00000800U
3955 
3956 /******************* Bit definition for DSI_VHBPCR register *************/
3957 #define DSI_VHBPCR_HBP 0x00000FFFU
3958 #define DSI_VHBPCR_HBP0 0x00000001U
3959 #define DSI_VHBPCR_HBP1 0x00000002U
3960 #define DSI_VHBPCR_HBP2 0x00000004U
3961 #define DSI_VHBPCR_HBP3 0x00000008U
3962 #define DSI_VHBPCR_HBP4 0x00000010U
3963 #define DSI_VHBPCR_HBP5 0x00000020U
3964 #define DSI_VHBPCR_HBP6 0x00000040U
3965 #define DSI_VHBPCR_HBP7 0x00000080U
3966 #define DSI_VHBPCR_HBP8 0x00000100U
3967 #define DSI_VHBPCR_HBP9 0x00000200U
3968 #define DSI_VHBPCR_HBP10 0x00000400U
3969 #define DSI_VHBPCR_HBP11 0x00000800U
3970 
3971 /******************* Bit definition for DSI_VLCR register ***************/
3972 #define DSI_VLCR_HLINE 0x00007FFFU
3973 #define DSI_VLCR_HLINE0 0x00000001U
3974 #define DSI_VLCR_HLINE1 0x00000002U
3975 #define DSI_VLCR_HLINE2 0x00000004U
3976 #define DSI_VLCR_HLINE3 0x00000008U
3977 #define DSI_VLCR_HLINE4 0x00000010U
3978 #define DSI_VLCR_HLINE5 0x00000020U
3979 #define DSI_VLCR_HLINE6 0x00000040U
3980 #define DSI_VLCR_HLINE7 0x00000080U
3981 #define DSI_VLCR_HLINE8 0x00000100U
3982 #define DSI_VLCR_HLINE9 0x00000200U
3983 #define DSI_VLCR_HLINE10 0x00000400U
3984 #define DSI_VLCR_HLINE11 0x00000800U
3985 #define DSI_VLCR_HLINE12 0x00001000U
3986 #define DSI_VLCR_HLINE13 0x00002000U
3987 #define DSI_VLCR_HLINE14 0x00004000U
3988 
3989 /******************* Bit definition for DSI_VVSACR register *************/
3990 #define DSI_VVSACR_VSA 0x000003FFU
3991 #define DSI_VVSACR_VSA0 0x00000001U
3992 #define DSI_VVSACR_VSA1 0x00000002U
3993 #define DSI_VVSACR_VSA2 0x00000004U
3994 #define DSI_VVSACR_VSA3 0x00000008U
3995 #define DSI_VVSACR_VSA4 0x00000010U
3996 #define DSI_VVSACR_VSA5 0x00000020U
3997 #define DSI_VVSACR_VSA6 0x00000040U
3998 #define DSI_VVSACR_VSA7 0x00000080U
3999 #define DSI_VVSACR_VSA8 0x00000100U
4000 #define DSI_VVSACR_VSA9 0x00000200U
4001 
4002 /******************* Bit definition for DSI_VVBPCR register *************/
4003 #define DSI_VVBPCR_VBP 0x000003FFU
4004 #define DSI_VVBPCR_VBP0 0x00000001U
4005 #define DSI_VVBPCR_VBP1 0x00000002U
4006 #define DSI_VVBPCR_VBP2 0x00000004U
4007 #define DSI_VVBPCR_VBP3 0x00000008U
4008 #define DSI_VVBPCR_VBP4 0x00000010U
4009 #define DSI_VVBPCR_VBP5 0x00000020U
4010 #define DSI_VVBPCR_VBP6 0x00000040U
4011 #define DSI_VVBPCR_VBP7 0x00000080U
4012 #define DSI_VVBPCR_VBP8 0x00000100U
4013 #define DSI_VVBPCR_VBP9 0x00000200U
4014 
4015 /******************* Bit definition for DSI_VVFPCR register *************/
4016 #define DSI_VVFPCR_VFP 0x000003FFU
4017 #define DSI_VVFPCR_VFP0 0x00000001U
4018 #define DSI_VVFPCR_VFP1 0x00000002U
4019 #define DSI_VVFPCR_VFP2 0x00000004U
4020 #define DSI_VVFPCR_VFP3 0x00000008U
4021 #define DSI_VVFPCR_VFP4 0x00000010U
4022 #define DSI_VVFPCR_VFP5 0x00000020U
4023 #define DSI_VVFPCR_VFP6 0x00000040U
4024 #define DSI_VVFPCR_VFP7 0x00000080U
4025 #define DSI_VVFPCR_VFP8 0x00000100U
4026 #define DSI_VVFPCR_VFP9 0x00000200U
4027 
4028 /******************* Bit definition for DSI_VVACR register **************/
4029 #define DSI_VVACR_VA 0x00003FFFU
4030 #define DSI_VVACR_VA0 0x00000001U
4031 #define DSI_VVACR_VA1 0x00000002U
4032 #define DSI_VVACR_VA2 0x00000004U
4033 #define DSI_VVACR_VA3 0x00000008U
4034 #define DSI_VVACR_VA4 0x00000010U
4035 #define DSI_VVACR_VA5 0x00000020U
4036 #define DSI_VVACR_VA6 0x00000040U
4037 #define DSI_VVACR_VA7 0x00000080U
4038 #define DSI_VVACR_VA8 0x00000100U
4039 #define DSI_VVACR_VA9 0x00000200U
4040 #define DSI_VVACR_VA10 0x00000400U
4041 #define DSI_VVACR_VA11 0x00000800U
4042 #define DSI_VVACR_VA12 0x00001000U
4043 #define DSI_VVACR_VA13 0x00002000U
4044 
4045 /******************* Bit definition for DSI_LCCR register ***************/
4046 #define DSI_LCCR_CMDSIZE 0x0000FFFFU
4047 #define DSI_LCCR_CMDSIZE0 0x00000001U
4048 #define DSI_LCCR_CMDSIZE1 0x00000002U
4049 #define DSI_LCCR_CMDSIZE2 0x00000004U
4050 #define DSI_LCCR_CMDSIZE3 0x00000008U
4051 #define DSI_LCCR_CMDSIZE4 0x00000010U
4052 #define DSI_LCCR_CMDSIZE5 0x00000020U
4053 #define DSI_LCCR_CMDSIZE6 0x00000040U
4054 #define DSI_LCCR_CMDSIZE7 0x00000080U
4055 #define DSI_LCCR_CMDSIZE8 0x00000100U
4056 #define DSI_LCCR_CMDSIZE9 0x00000200U
4057 #define DSI_LCCR_CMDSIZE10 0x00000400U
4058 #define DSI_LCCR_CMDSIZE11 0x00000800U
4059 #define DSI_LCCR_CMDSIZE12 0x00001000U
4060 #define DSI_LCCR_CMDSIZE13 0x00002000U
4061 #define DSI_LCCR_CMDSIZE14 0x00004000U
4062 #define DSI_LCCR_CMDSIZE15 0x00008000U
4063 
4064 /******************* Bit definition for DSI_CMCR register ***************/
4065 #define DSI_CMCR_TEARE 0x00000001U
4066 #define DSI_CMCR_ARE 0x00000002U
4067 #define DSI_CMCR_GSW0TX 0x00000100U
4068 #define DSI_CMCR_GSW1TX 0x00000200U
4069 #define DSI_CMCR_GSW2TX 0x00000400U
4070 #define DSI_CMCR_GSR0TX 0x00000800U
4071 #define DSI_CMCR_GSR1TX 0x00001000U
4072 #define DSI_CMCR_GSR2TX 0x00002000U
4073 #define DSI_CMCR_GLWTX 0x00004000U
4074 #define DSI_CMCR_DSW0TX 0x00010000U
4075 #define DSI_CMCR_DSW1TX 0x00020000U
4076 #define DSI_CMCR_DSR0TX 0x00040000U
4077 #define DSI_CMCR_DLWTX 0x00080000U
4078 #define DSI_CMCR_MRDPS 0x01000000U
4080 /******************* Bit definition for DSI_GHCR register ***************/
4081 #define DSI_GHCR_DT 0x0000003FU
4082 #define DSI_GHCR_DT0 0x00000001U
4083 #define DSI_GHCR_DT1 0x00000002U
4084 #define DSI_GHCR_DT2 0x00000004U
4085 #define DSI_GHCR_DT3 0x00000008U
4086 #define DSI_GHCR_DT4 0x00000010U
4087 #define DSI_GHCR_DT5 0x00000020U
4088 
4089 #define DSI_GHCR_VCID 0x000000C0U
4090 #define DSI_GHCR_VCID0 0x00000040U
4091 #define DSI_GHCR_VCID1 0x00000080U
4092 
4093 #define DSI_GHCR_WCLSB 0x0000FF00U
4094 #define DSI_GHCR_WCLSB0 0x00000100U
4095 #define DSI_GHCR_WCLSB1 0x00000200U
4096 #define DSI_GHCR_WCLSB2 0x00000400U
4097 #define DSI_GHCR_WCLSB3 0x00000800U
4098 #define DSI_GHCR_WCLSB4 0x00001000U
4099 #define DSI_GHCR_WCLSB5 0x00002000U
4100 #define DSI_GHCR_WCLSB6 0x00004000U
4101 #define DSI_GHCR_WCLSB7 0x00008000U
4102 
4103 #define DSI_GHCR_WCMSB 0x00FF0000U
4104 #define DSI_GHCR_WCMSB0 0x00010000U
4105 #define DSI_GHCR_WCMSB1 0x00020000U
4106 #define DSI_GHCR_WCMSB2 0x00040000U
4107 #define DSI_GHCR_WCMSB3 0x00080000U
4108 #define DSI_GHCR_WCMSB4 0x00100000U
4109 #define DSI_GHCR_WCMSB5 0x00200000U
4110 #define DSI_GHCR_WCMSB6 0x00400000U
4111 #define DSI_GHCR_WCMSB7 0x00800000U
4112 
4113 /******************* Bit definition for DSI_GPDR register ***************/
4114 #define DSI_GPDR_DATA1 0x000000FFU
4115 #define DSI_GPDR_DATA1_0 0x00000001U
4116 #define DSI_GPDR_DATA1_1 0x00000002U
4117 #define DSI_GPDR_DATA1_2 0x00000004U
4118 #define DSI_GPDR_DATA1_3 0x00000008U
4119 #define DSI_GPDR_DATA1_4 0x00000010U
4120 #define DSI_GPDR_DATA1_5 0x00000020U
4121 #define DSI_GPDR_DATA1_6 0x00000040U
4122 #define DSI_GPDR_DATA1_7 0x00000080U
4123 
4124 #define DSI_GPDR_DATA2 0x0000FF00U
4125 #define DSI_GPDR_DATA2_0 0x00000100U
4126 #define DSI_GPDR_DATA2_1 0x00000200U
4127 #define DSI_GPDR_DATA2_2 0x00000400U
4128 #define DSI_GPDR_DATA2_3 0x00000800U
4129 #define DSI_GPDR_DATA2_4 0x00001000U
4130 #define DSI_GPDR_DATA2_5 0x00002000U
4131 #define DSI_GPDR_DATA2_6 0x00004000U
4132 #define DSI_GPDR_DATA2_7 0x00008000U
4133 
4134 #define DSI_GPDR_DATA3 0x00FF0000U
4135 #define DSI_GPDR_DATA3_0 0x00010000U
4136 #define DSI_GPDR_DATA3_1 0x00020000U
4137 #define DSI_GPDR_DATA3_2 0x00040000U
4138 #define DSI_GPDR_DATA3_3 0x00080000U
4139 #define DSI_GPDR_DATA3_4 0x00100000U
4140 #define DSI_GPDR_DATA3_5 0x00200000U
4141 #define DSI_GPDR_DATA3_6 0x00400000U
4142 #define DSI_GPDR_DATA3_7 0x00800000U
4143 
4144 #define DSI_GPDR_DATA4 0xFF000000U
4145 #define DSI_GPDR_DATA4_0 0x01000000U
4146 #define DSI_GPDR_DATA4_1 0x02000000U
4147 #define DSI_GPDR_DATA4_2 0x04000000U
4148 #define DSI_GPDR_DATA4_3 0x08000000U
4149 #define DSI_GPDR_DATA4_4 0x10000000U
4150 #define DSI_GPDR_DATA4_5 0x20000000U
4151 #define DSI_GPDR_DATA4_6 0x40000000U
4152 #define DSI_GPDR_DATA4_7 0x80000000U
4153 
4154 /******************* Bit definition for DSI_GPSR register ***************/
4155 #define DSI_GPSR_CMDFE 0x00000001U
4156 #define DSI_GPSR_CMDFF 0x00000002U
4157 #define DSI_GPSR_PWRFE 0x00000004U
4158 #define DSI_GPSR_PWRFF 0x00000008U
4159 #define DSI_GPSR_PRDFE 0x00000010U
4160 #define DSI_GPSR_PRDFF 0x00000020U
4161 #define DSI_GPSR_RCB 0x00000040U
4163 /******************* Bit definition for DSI_TCCR0 register **************/
4164 #define DSI_TCCR0_LPRX_TOCNT 0x0000FFFFU
4165 #define DSI_TCCR0_LPRX_TOCNT0 0x00000001U
4166 #define DSI_TCCR0_LPRX_TOCNT1 0x00000002U
4167 #define DSI_TCCR0_LPRX_TOCNT2 0x00000004U
4168 #define DSI_TCCR0_LPRX_TOCNT3 0x00000008U
4169 #define DSI_TCCR0_LPRX_TOCNT4 0x00000010U
4170 #define DSI_TCCR0_LPRX_TOCNT5 0x00000020U
4171 #define DSI_TCCR0_LPRX_TOCNT6 0x00000040U
4172 #define DSI_TCCR0_LPRX_TOCNT7 0x00000080U
4173 #define DSI_TCCR0_LPRX_TOCNT8 0x00000100U
4174 #define DSI_TCCR0_LPRX_TOCNT9 0x00000200U
4175 #define DSI_TCCR0_LPRX_TOCNT10 0x00000400U
4176 #define DSI_TCCR0_LPRX_TOCNT11 0x00000800U
4177 #define DSI_TCCR0_LPRX_TOCNT12 0x00001000U
4178 #define DSI_TCCR0_LPRX_TOCNT13 0x00002000U
4179 #define DSI_TCCR0_LPRX_TOCNT14 0x00004000U
4180 #define DSI_TCCR0_LPRX_TOCNT15 0x00008000U
4181 
4182 #define DSI_TCCR0_HSTX_TOCNT 0xFFFF0000U
4183 #define DSI_TCCR0_HSTX_TOCNT0 0x00010000U
4184 #define DSI_TCCR0_HSTX_TOCNT1 0x00020000U
4185 #define DSI_TCCR0_HSTX_TOCNT2 0x00040000U
4186 #define DSI_TCCR0_HSTX_TOCNT3 0x00080000U
4187 #define DSI_TCCR0_HSTX_TOCNT4 0x00100000U
4188 #define DSI_TCCR0_HSTX_TOCNT5 0x00200000U
4189 #define DSI_TCCR0_HSTX_TOCNT6 0x00400000U
4190 #define DSI_TCCR0_HSTX_TOCNT7 0x00800000U
4191 #define DSI_TCCR0_HSTX_TOCNT8 0x01000000U
4192 #define DSI_TCCR0_HSTX_TOCNT9 0x02000000U
4193 #define DSI_TCCR0_HSTX_TOCNT10 0x04000000U
4194 #define DSI_TCCR0_HSTX_TOCNT11 0x08000000U
4195 #define DSI_TCCR0_HSTX_TOCNT12 0x10000000U
4196 #define DSI_TCCR0_HSTX_TOCNT13 0x20000000U
4197 #define DSI_TCCR0_HSTX_TOCNT14 0x40000000U
4198 #define DSI_TCCR0_HSTX_TOCNT15 0x80000000U
4199 
4200 /******************* Bit definition for DSI_TCCR1 register **************/
4201 #define DSI_TCCR1_HSRD_TOCNT 0x0000FFFFU
4202 #define DSI_TCCR1_HSRD_TOCNT0 0x00000001U
4203 #define DSI_TCCR1_HSRD_TOCNT1 0x00000002U
4204 #define DSI_TCCR1_HSRD_TOCNT2 0x00000004U
4205 #define DSI_TCCR1_HSRD_TOCNT3 0x00000008U
4206 #define DSI_TCCR1_HSRD_TOCNT4 0x00000010U
4207 #define DSI_TCCR1_HSRD_TOCNT5 0x00000020U
4208 #define DSI_TCCR1_HSRD_TOCNT6 0x00000040U
4209 #define DSI_TCCR1_HSRD_TOCNT7 0x00000080U
4210 #define DSI_TCCR1_HSRD_TOCNT8 0x00000100U
4211 #define DSI_TCCR1_HSRD_TOCNT9 0x00000200U
4212 #define DSI_TCCR1_HSRD_TOCNT10 0x00000400U
4213 #define DSI_TCCR1_HSRD_TOCNT11 0x00000800U
4214 #define DSI_TCCR1_HSRD_TOCNT12 0x00001000U
4215 #define DSI_TCCR1_HSRD_TOCNT13 0x00002000U
4216 #define DSI_TCCR1_HSRD_TOCNT14 0x00004000U
4217 #define DSI_TCCR1_HSRD_TOCNT15 0x00008000U
4218 
4219 /******************* Bit definition for DSI_TCCR2 register **************/
4220 #define DSI_TCCR2_LPRD_TOCNT 0x0000FFFFU
4221 #define DSI_TCCR2_LPRD_TOCNT0 0x00000001U
4222 #define DSI_TCCR2_LPRD_TOCNT1 0x00000002U
4223 #define DSI_TCCR2_LPRD_TOCNT2 0x00000004U
4224 #define DSI_TCCR2_LPRD_TOCNT3 0x00000008U
4225 #define DSI_TCCR2_LPRD_TOCNT4 0x00000010U
4226 #define DSI_TCCR2_LPRD_TOCNT5 0x00000020U
4227 #define DSI_TCCR2_LPRD_TOCNT6 0x00000040U
4228 #define DSI_TCCR2_LPRD_TOCNT7 0x00000080U
4229 #define DSI_TCCR2_LPRD_TOCNT8 0x00000100U
4230 #define DSI_TCCR2_LPRD_TOCNT9 0x00000200U
4231 #define DSI_TCCR2_LPRD_TOCNT10 0x00000400U
4232 #define DSI_TCCR2_LPRD_TOCNT11 0x00000800U
4233 #define DSI_TCCR2_LPRD_TOCNT12 0x00001000U
4234 #define DSI_TCCR2_LPRD_TOCNT13 0x00002000U
4235 #define DSI_TCCR2_LPRD_TOCNT14 0x00004000U
4236 #define DSI_TCCR2_LPRD_TOCNT15 0x00008000U
4237 
4238 /******************* Bit definition for DSI_TCCR3 register **************/
4239 #define DSI_TCCR3_HSWR_TOCNT 0x0000FFFFU
4240 #define DSI_TCCR3_HSWR_TOCNT0 0x00000001U
4241 #define DSI_TCCR3_HSWR_TOCNT1 0x00000002U
4242 #define DSI_TCCR3_HSWR_TOCNT2 0x00000004U
4243 #define DSI_TCCR3_HSWR_TOCNT3 0x00000008U
4244 #define DSI_TCCR3_HSWR_TOCNT4 0x00000010U
4245 #define DSI_TCCR3_HSWR_TOCNT5 0x00000020U
4246 #define DSI_TCCR3_HSWR_TOCNT6 0x00000040U
4247 #define DSI_TCCR3_HSWR_TOCNT7 0x00000080U
4248 #define DSI_TCCR3_HSWR_TOCNT8 0x00000100U
4249 #define DSI_TCCR3_HSWR_TOCNT9 0x00000200U
4250 #define DSI_TCCR3_HSWR_TOCNT10 0x00000400U
4251 #define DSI_TCCR3_HSWR_TOCNT11 0x00000800U
4252 #define DSI_TCCR3_HSWR_TOCNT12 0x00001000U
4253 #define DSI_TCCR3_HSWR_TOCNT13 0x00002000U
4254 #define DSI_TCCR3_HSWR_TOCNT14 0x00004000U
4255 #define DSI_TCCR3_HSWR_TOCNT15 0x00008000U
4256 
4257 #define DSI_TCCR3_PM 0x01000000U
4259 /******************* Bit definition for DSI_TCCR4 register **************/
4260 #define DSI_TCCR4_LPWR_TOCNT 0x0000FFFFU
4261 #define DSI_TCCR4_LPWR_TOCNT0 0x00000001U
4262 #define DSI_TCCR4_LPWR_TOCNT1 0x00000002U
4263 #define DSI_TCCR4_LPWR_TOCNT2 0x00000004U
4264 #define DSI_TCCR4_LPWR_TOCNT3 0x00000008U
4265 #define DSI_TCCR4_LPWR_TOCNT4 0x00000010U
4266 #define DSI_TCCR4_LPWR_TOCNT5 0x00000020U
4267 #define DSI_TCCR4_LPWR_TOCNT6 0x00000040U
4268 #define DSI_TCCR4_LPWR_TOCNT7 0x00000080U
4269 #define DSI_TCCR4_LPWR_TOCNT8 0x00000100U
4270 #define DSI_TCCR4_LPWR_TOCNT9 0x00000200U
4271 #define DSI_TCCR4_LPWR_TOCNT10 0x00000400U
4272 #define DSI_TCCR4_LPWR_TOCNT11 0x00000800U
4273 #define DSI_TCCR4_LPWR_TOCNT12 0x00001000U
4274 #define DSI_TCCR4_LPWR_TOCNT13 0x00002000U
4275 #define DSI_TCCR4_LPWR_TOCNT14 0x00004000U
4276 #define DSI_TCCR4_LPWR_TOCNT15 0x00008000U
4277 
4278 /******************* Bit definition for DSI_TCCR5 register **************/
4279 #define DSI_TCCR5_BTA_TOCNT 0x0000FFFFU
4280 #define DSI_TCCR5_BTA_TOCNT0 0x00000001U
4281 #define DSI_TCCR5_BTA_TOCNT1 0x00000002U
4282 #define DSI_TCCR5_BTA_TOCNT2 0x00000004U
4283 #define DSI_TCCR5_BTA_TOCNT3 0x00000008U
4284 #define DSI_TCCR5_BTA_TOCNT4 0x00000010U
4285 #define DSI_TCCR5_BTA_TOCNT5 0x00000020U
4286 #define DSI_TCCR5_BTA_TOCNT6 0x00000040U
4287 #define DSI_TCCR5_BTA_TOCNT7 0x00000080U
4288 #define DSI_TCCR5_BTA_TOCNT8 0x00000100U
4289 #define DSI_TCCR5_BTA_TOCNT9 0x00000200U
4290 #define DSI_TCCR5_BTA_TOCNT10 0x00000400U
4291 #define DSI_TCCR5_BTA_TOCNT11 0x00000800U
4292 #define DSI_TCCR5_BTA_TOCNT12 0x00001000U
4293 #define DSI_TCCR5_BTA_TOCNT13 0x00002000U
4294 #define DSI_TCCR5_BTA_TOCNT14 0x00004000U
4295 #define DSI_TCCR5_BTA_TOCNT15 0x00008000U
4296 
4297 /******************* Bit definition for DSI_TDCR register ***************/
4298 #define DSI_TDCR_3DM 0x00000003U
4299 #define DSI_TDCR_3DM0 0x00000001U
4300 #define DSI_TDCR_3DM1 0x00000002U
4301 
4302 #define DSI_TDCR_3DF 0x0000000CU
4303 #define DSI_TDCR_3DF0 0x00000004U
4304 #define DSI_TDCR_3DF1 0x00000008U
4305 
4306 #define DSI_TDCR_SVS 0x00000010U
4307 #define DSI_TDCR_RF 0x00000020U
4308 #define DSI_TDCR_S3DC 0x00010000U
4310 /******************* Bit definition for DSI_CLCR register ***************/
4311 #define DSI_CLCR_DPCC 0x00000001U
4312 #define DSI_CLCR_ACR 0x00000002U
4314 /******************* Bit definition for DSI_CLTCR register **************/
4315 #define DSI_CLTCR_LP2HS_TIME 0x000003FFU
4316 #define DSI_CLTCR_LP2HS_TIME0 0x00000001U
4317 #define DSI_CLTCR_LP2HS_TIME1 0x00000002U
4318 #define DSI_CLTCR_LP2HS_TIME2 0x00000004U
4319 #define DSI_CLTCR_LP2HS_TIME3 0x00000008U
4320 #define DSI_CLTCR_LP2HS_TIME4 0x00000010U
4321 #define DSI_CLTCR_LP2HS_TIME5 0x00000020U
4322 #define DSI_CLTCR_LP2HS_TIME6 0x00000040U
4323 #define DSI_CLTCR_LP2HS_TIME7 0x00000080U
4324 #define DSI_CLTCR_LP2HS_TIME8 0x00000100U
4325 #define DSI_CLTCR_LP2HS_TIME9 0x00000200U
4326 
4327 #define DSI_CLTCR_HS2LP_TIME 0x03FF0000U
4328 #define DSI_CLTCR_HS2LP_TIME0 0x00010000U
4329 #define DSI_CLTCR_HS2LP_TIME1 0x00020000U
4330 #define DSI_CLTCR_HS2LP_TIME2 0x00040000U
4331 #define DSI_CLTCR_HS2LP_TIME3 0x00080000U
4332 #define DSI_CLTCR_HS2LP_TIME4 0x00100000U
4333 #define DSI_CLTCR_HS2LP_TIME5 0x00200000U
4334 #define DSI_CLTCR_HS2LP_TIME6 0x00400000U
4335 #define DSI_CLTCR_HS2LP_TIME7 0x00800000U
4336 #define DSI_CLTCR_HS2LP_TIME8 0x01000000U
4337 #define DSI_CLTCR_HS2LP_TIME9 0x02000000U
4338 
4339 /******************* Bit definition for DSI_DLTCR register **************/
4340 #define DSI_DLTCR_MRD_TIME 0x00007FFFU
4341 #define DSI_DLTCR_MRD_TIME0 0x00000001U
4342 #define DSI_DLTCR_MRD_TIME1 0x00000002U
4343 #define DSI_DLTCR_MRD_TIME2 0x00000004U
4344 #define DSI_DLTCR_MRD_TIME3 0x00000008U
4345 #define DSI_DLTCR_MRD_TIME4 0x00000010U
4346 #define DSI_DLTCR_MRD_TIME5 0x00000020U
4347 #define DSI_DLTCR_MRD_TIME6 0x00000040U
4348 #define DSI_DLTCR_MRD_TIME7 0x00000080U
4349 #define DSI_DLTCR_MRD_TIME8 0x00000100U
4350 #define DSI_DLTCR_MRD_TIME9 0x00000200U
4351 #define DSI_DLTCR_MRD_TIME10 0x00000400U
4352 #define DSI_DLTCR_MRD_TIME11 0x00000800U
4353 #define DSI_DLTCR_MRD_TIME12 0x00001000U
4354 #define DSI_DLTCR_MRD_TIME13 0x00002000U
4355 #define DSI_DLTCR_MRD_TIME14 0x00004000U
4356 
4357 #define DSI_DLTCR_LP2HS_TIME 0x00FF0000U
4358 #define DSI_DLTCR_LP2HS_TIME0 0x00010000U
4359 #define DSI_DLTCR_LP2HS_TIME1 0x00020000U
4360 #define DSI_DLTCR_LP2HS_TIME2 0x00040000U
4361 #define DSI_DLTCR_LP2HS_TIME3 0x00080000U
4362 #define DSI_DLTCR_LP2HS_TIME4 0x00100000U
4363 #define DSI_DLTCR_LP2HS_TIME5 0x00200000U
4364 #define DSI_DLTCR_LP2HS_TIME6 0x00400000U
4365 #define DSI_DLTCR_LP2HS_TIME7 0x00800000U
4366 
4367 #define DSI_DLTCR_HS2LP_TIME 0xFF000000U
4368 #define DSI_DLTCR_HS2LP_TIME0 0x01000000U
4369 #define DSI_DLTCR_HS2LP_TIME1 0x02000000U
4370 #define DSI_DLTCR_HS2LP_TIME2 0x04000000U
4371 #define DSI_DLTCR_HS2LP_TIME3 0x08000000U
4372 #define DSI_DLTCR_HS2LP_TIME4 0x10000000U
4373 #define DSI_DLTCR_HS2LP_TIME5 0x20000000U
4374 #define DSI_DLTCR_HS2LP_TIME6 0x40000000U
4375 #define DSI_DLTCR_HS2LP_TIME7 0x80000000U
4376 
4377 /******************* Bit definition for DSI_PCTLR register **************/
4378 #define DSI_PCTLR_DEN 0x00000002U
4379 #define DSI_PCTLR_CKE 0x00000004U
4381 /******************* Bit definition for DSI_PCONFR register *************/
4382 #define DSI_PCONFR_NL 0x00000003U
4383 #define DSI_PCONFR_NL0 0x00000001U
4384 #define DSI_PCONFR_NL1 0x00000002U
4385 
4386 #define DSI_PCONFR_SW_TIME 0x0000FF00U
4387 #define DSI_PCONFR_SW_TIME0 0x00000100U
4388 #define DSI_PCONFR_SW_TIME1 0x00000200U
4389 #define DSI_PCONFR_SW_TIME2 0x00000400U
4390 #define DSI_PCONFR_SW_TIME3 0x00000800U
4391 #define DSI_PCONFR_SW_TIME4 0x00001000U
4392 #define DSI_PCONFR_SW_TIME5 0x00002000U
4393 #define DSI_PCONFR_SW_TIME6 0x00004000U
4394 #define DSI_PCONFR_SW_TIME7 0x00008000U
4395 
4396 /******************* Bit definition for DSI_PUCR register ***************/
4397 #define DSI_PUCR_URCL 0x00000001U
4398 #define DSI_PUCR_UECL 0x00000002U
4399 #define DSI_PUCR_URDL 0x00000004U
4400 #define DSI_PUCR_UEDL 0x00000008U
4402 /******************* Bit definition for DSI_PTTCR register **************/
4403 #define DSI_PTTCR_TX_TRIG 0x0000000FU
4404 #define DSI_PTTCR_TX_TRIG0 0x00000001U
4405 #define DSI_PTTCR_TX_TRIG1 0x00000002U
4406 #define DSI_PTTCR_TX_TRIG2 0x00000004U
4407 #define DSI_PTTCR_TX_TRIG3 0x00000008U
4408 
4409 /******************* Bit definition for DSI_PSR register ****************/
4410 #define DSI_PSR_PD 0x00000002U
4411 #define DSI_PSR_PSSC 0x00000004U
4412 #define DSI_PSR_UANC 0x00000008U
4413 #define DSI_PSR_PSS0 0x00000010U
4414 #define DSI_PSR_UAN0 0x00000020U
4415 #define DSI_PSR_RUE0 0x00000040U
4416 #define DSI_PSR_PSS1 0x00000080U
4417 #define DSI_PSR_UAN1 0x00000100U
4419 /******************* Bit definition for DSI_ISR0 register ***************/
4420 #define DSI_ISR0_AE0 0x00000001U
4421 #define DSI_ISR0_AE1 0x00000002U
4422 #define DSI_ISR0_AE2 0x00000004U
4423 #define DSI_ISR0_AE3 0x00000008U
4424 #define DSI_ISR0_AE4 0x00000010U
4425 #define DSI_ISR0_AE5 0x00000020U
4426 #define DSI_ISR0_AE6 0x00000040U
4427 #define DSI_ISR0_AE7 0x00000080U
4428 #define DSI_ISR0_AE8 0x00000100U
4429 #define DSI_ISR0_AE9 0x00000200U
4430 #define DSI_ISR0_AE10 0x00000400U
4431 #define DSI_ISR0_AE11 0x00000800U
4432 #define DSI_ISR0_AE12 0x00001000U
4433 #define DSI_ISR0_AE13 0x00002000U
4434 #define DSI_ISR0_AE14 0x00004000U
4435 #define DSI_ISR0_AE15 0x00008000U
4436 #define DSI_ISR0_PE0 0x00010000U
4437 #define DSI_ISR0_PE1 0x00020000U
4438 #define DSI_ISR0_PE2 0x00040000U
4439 #define DSI_ISR0_PE3 0x00080000U
4440 #define DSI_ISR0_PE4 0x00100000U
4442 /******************* Bit definition for DSI_ISR1 register ***************/
4443 #define DSI_ISR1_TOHSTX 0x00000001U
4444 #define DSI_ISR1_TOLPRX 0x00000002U
4445 #define DSI_ISR1_ECCSE 0x00000004U
4446 #define DSI_ISR1_ECCME 0x00000008U
4447 #define DSI_ISR1_CRCE 0x00000010U
4448 #define DSI_ISR1_PSE 0x00000020U
4449 #define DSI_ISR1_EOTPE 0x00000040U
4450 #define DSI_ISR1_LPWRE 0x00000080U
4451 #define DSI_ISR1_GCWRE 0x00000100U
4452 #define DSI_ISR1_GPWRE 0x00000200U
4453 #define DSI_ISR1_GPTXE 0x00000400U
4454 #define DSI_ISR1_GPRDE 0x00000800U
4455 #define DSI_ISR1_GPRXE 0x00001000U
4457 /******************* Bit definition for DSI_IER0 register ***************/
4458 #define DSI_IER0_AE0IE 0x00000001U
4459 #define DSI_IER0_AE1IE 0x00000002U
4460 #define DSI_IER0_AE2IE 0x00000004U
4461 #define DSI_IER0_AE3IE 0x00000008U
4462 #define DSI_IER0_AE4IE 0x00000010U
4463 #define DSI_IER0_AE5IE 0x00000020U
4464 #define DSI_IER0_AE6IE 0x00000040U
4465 #define DSI_IER0_AE7IE 0x00000080U
4466 #define DSI_IER0_AE8IE 0x00000100U
4467 #define DSI_IER0_AE9IE 0x00000200U
4468 #define DSI_IER0_AE10IE 0x00000400U
4469 #define DSI_IER0_AE11IE 0x00000800U
4470 #define DSI_IER0_AE12IE 0x00001000U
4471 #define DSI_IER0_AE13IE 0x00002000U
4472 #define DSI_IER0_AE14IE 0x00004000U
4473 #define DSI_IER0_AE15IE 0x00008000U
4474 #define DSI_IER0_PE0IE 0x00010000U
4475 #define DSI_IER0_PE1IE 0x00020000U
4476 #define DSI_IER0_PE2IE 0x00040000U
4477 #define DSI_IER0_PE3IE 0x00080000U
4478 #define DSI_IER0_PE4IE 0x00100000U
4480 /******************* Bit definition for DSI_IER1 register ***************/
4481 #define DSI_IER1_TOHSTXIE 0x00000001U
4482 #define DSI_IER1_TOLPRXIE 0x00000002U
4483 #define DSI_IER1_ECCSEIE 0x00000004U
4484 #define DSI_IER1_ECCMEIE 0x00000008U
4485 #define DSI_IER1_CRCEIE 0x00000010U
4486 #define DSI_IER1_PSEIE 0x00000020U
4487 #define DSI_IER1_EOTPEIE 0x00000040U
4488 #define DSI_IER1_LPWREIE 0x00000080U
4489 #define DSI_IER1_GCWREIE 0x00000100U
4490 #define DSI_IER1_GPWREIE 0x00000200U
4491 #define DSI_IER1_GPTXEIE 0x00000400U
4492 #define DSI_IER1_GPRDEIE 0x00000800U
4493 #define DSI_IER1_GPRXEIE 0x00001000U
4495 /******************* Bit definition for DSI_FIR0 register ***************/
4496 #define DSI_FIR0_FAE0 0x00000001U
4497 #define DSI_FIR0_FAE1 0x00000002U
4498 #define DSI_FIR0_FAE2 0x00000004U
4499 #define DSI_FIR0_FAE3 0x00000008U
4500 #define DSI_FIR0_FAE4 0x00000010U
4501 #define DSI_FIR0_FAE5 0x00000020U
4502 #define DSI_FIR0_FAE6 0x00000040U
4503 #define DSI_FIR0_FAE7 0x00000080U
4504 #define DSI_FIR0_FAE8 0x00000100U
4505 #define DSI_FIR0_FAE9 0x00000200U
4506 #define DSI_FIR0_FAE10 0x00000400U
4507 #define DSI_FIR0_FAE11 0x00000800U
4508 #define DSI_FIR0_FAE12 0x00001000U
4509 #define DSI_FIR0_FAE13 0x00002000U
4510 #define DSI_FIR0_FAE14 0x00004000U
4511 #define DSI_FIR0_FAE15 0x00008000U
4512 #define DSI_FIR0_FPE0 0x00010000U
4513 #define DSI_FIR0_FPE1 0x00020000U
4514 #define DSI_FIR0_FPE2 0x00040000U
4515 #define DSI_FIR0_FPE3 0x00080000U
4516 #define DSI_FIR0_FPE4 0x00100000U
4518 /******************* Bit definition for DSI_FIR1 register ***************/
4519 #define DSI_FIR1_FTOHSTX 0x00000001U
4520 #define DSI_FIR1_FTOLPRX 0x00000002U
4521 #define DSI_FIR1_FECCSE 0x00000004U
4522 #define DSI_FIR1_FECCME 0x00000008U
4523 #define DSI_FIR1_FCRCE 0x00000010U
4524 #define DSI_FIR1_FPSE 0x00000020U
4525 #define DSI_FIR1_FEOTPE 0x00000040U
4526 #define DSI_FIR1_FLPWRE 0x00000080U
4527 #define DSI_FIR1_FGCWRE 0x00000100U
4528 #define DSI_FIR1_FGPWRE 0x00000200U
4529 #define DSI_FIR1_FGPTXE 0x00000400U
4530 #define DSI_FIR1_FGPRDE 0x00000800U
4531 #define DSI_FIR1_FGPRXE 0x00001000U
4533 /******************* Bit definition for DSI_VSCR register ***************/
4534 #define DSI_VSCR_EN 0x00000001U
4535 #define DSI_VSCR_UR 0x00000100U
4537 /******************* Bit definition for DSI_LCVCIDR register ************/
4538 #define DSI_LCVCIDR_VCID 0x00000003U
4539 #define DSI_LCVCIDR_VCID0 0x00000001U
4540 #define DSI_LCVCIDR_VCID1 0x00000002U
4541 
4542 /******************* Bit definition for DSI_LCCCR register **************/
4543 #define DSI_LCCCR_COLC 0x0000000FU
4544 #define DSI_LCCCR_COLC0 0x00000001U
4545 #define DSI_LCCCR_COLC1 0x00000002U
4546 #define DSI_LCCCR_COLC2 0x00000004U
4547 #define DSI_LCCCR_COLC3 0x00000008U
4548 
4549 #define DSI_LCCCR_LPE 0x00000100U
4551 /******************* Bit definition for DSI_LPMCCR register *************/
4552 #define DSI_LPMCCR_VLPSIZE 0x000000FFU
4553 #define DSI_LPMCCR_VLPSIZE0 0x00000001U
4554 #define DSI_LPMCCR_VLPSIZE1 0x00000002U
4555 #define DSI_LPMCCR_VLPSIZE2 0x00000004U
4556 #define DSI_LPMCCR_VLPSIZE3 0x00000008U
4557 #define DSI_LPMCCR_VLPSIZE4 0x00000010U
4558 #define DSI_LPMCCR_VLPSIZE5 0x00000020U
4559 #define DSI_LPMCCR_VLPSIZE6 0x00000040U
4560 #define DSI_LPMCCR_VLPSIZE7 0x00000080U
4561 
4562 #define DSI_LPMCCR_LPSIZE 0x00FF0000U
4563 #define DSI_LPMCCR_LPSIZE0 0x00010000U
4564 #define DSI_LPMCCR_LPSIZE1 0x00020000U
4565 #define DSI_LPMCCR_LPSIZE2 0x00040000U
4566 #define DSI_LPMCCR_LPSIZE3 0x00080000U
4567 #define DSI_LPMCCR_LPSIZE4 0x00100000U
4568 #define DSI_LPMCCR_LPSIZE5 0x00200000U
4569 #define DSI_LPMCCR_LPSIZE6 0x00400000U
4570 #define DSI_LPMCCR_LPSIZE7 0x00800000U
4571 
4572 /******************* Bit definition for DSI_VMCCR register **************/
4573 #define DSI_VMCCR_VMT 0x00000003U
4574 #define DSI_VMCCR_VMT0 0x00000001U
4575 #define DSI_VMCCR_VMT1 0x00000002U
4576 
4577 #define DSI_VMCCR_LPVSAE 0x00000100U
4578 #define DSI_VMCCR_LPVBPE 0x00000200U
4579 #define DSI_VMCCR_LPVFPE 0x00000400U
4580 #define DSI_VMCCR_LPVAE 0x00000800U
4581 #define DSI_VMCCR_LPHBPE 0x00001000U
4582 #define DSI_VMCCR_LPHFE 0x00002000U
4583 #define DSI_VMCCR_FBTAAE 0x00004000U
4584 #define DSI_VMCCR_LPCE 0x00008000U
4586 /******************* Bit definition for DSI_VPCCR register **************/
4587 #define DSI_VPCCR_VPSIZE 0x00003FFFU
4588 #define DSI_VPCCR_VPSIZE0 0x00000001U
4589 #define DSI_VPCCR_VPSIZE1 0x00000002U
4590 #define DSI_VPCCR_VPSIZE2 0x00000004U
4591 #define DSI_VPCCR_VPSIZE3 0x00000008U
4592 #define DSI_VPCCR_VPSIZE4 0x00000010U
4593 #define DSI_VPCCR_VPSIZE5 0x00000020U
4594 #define DSI_VPCCR_VPSIZE6 0x00000040U
4595 #define DSI_VPCCR_VPSIZE7 0x00000080U
4596 #define DSI_VPCCR_VPSIZE8 0x00000100U
4597 #define DSI_VPCCR_VPSIZE9 0x00000200U
4598 #define DSI_VPCCR_VPSIZE10 0x00000400U
4599 #define DSI_VPCCR_VPSIZE11 0x00000800U
4600 #define DSI_VPCCR_VPSIZE12 0x00001000U
4601 #define DSI_VPCCR_VPSIZE13 0x00002000U
4602 
4603 /******************* Bit definition for DSI_VCCCR register **************/
4604 #define DSI_VCCCR_NUMC 0x00001FFFU
4605 #define DSI_VCCCR_NUMC0 0x00000001U
4606 #define DSI_VCCCR_NUMC1 0x00000002U
4607 #define DSI_VCCCR_NUMC2 0x00000004U
4608 #define DSI_VCCCR_NUMC3 0x00000008U
4609 #define DSI_VCCCR_NUMC4 0x00000010U
4610 #define DSI_VCCCR_NUMC5 0x00000020U
4611 #define DSI_VCCCR_NUMC6 0x00000040U
4612 #define DSI_VCCCR_NUMC7 0x00000080U
4613 #define DSI_VCCCR_NUMC8 0x00000100U
4614 #define DSI_VCCCR_NUMC9 0x00000200U
4615 #define DSI_VCCCR_NUMC10 0x00000400U
4616 #define DSI_VCCCR_NUMC11 0x00000800U
4617 #define DSI_VCCCR_NUMC12 0x00001000U
4618 
4619 /******************* Bit definition for DSI_VNPCCR register *************/
4620 #define DSI_VNPCCR_NPSIZE 0x00001FFFU
4621 #define DSI_VNPCCR_NPSIZE0 0x00000001U
4622 #define DSI_VNPCCR_NPSIZE1 0x00000002U
4623 #define DSI_VNPCCR_NPSIZE2 0x00000004U
4624 #define DSI_VNPCCR_NPSIZE3 0x00000008U
4625 #define DSI_VNPCCR_NPSIZE4 0x00000010U
4626 #define DSI_VNPCCR_NPSIZE5 0x00000020U
4627 #define DSI_VNPCCR_NPSIZE6 0x00000040U
4628 #define DSI_VNPCCR_NPSIZE7 0x00000080U
4629 #define DSI_VNPCCR_NPSIZE8 0x00000100U
4630 #define DSI_VNPCCR_NPSIZE9 0x00000200U
4631 #define DSI_VNPCCR_NPSIZE10 0x00000400U
4632 #define DSI_VNPCCR_NPSIZE11 0x00000800U
4633 #define DSI_VNPCCR_NPSIZE12 0x00001000U
4634 
4635 /******************* Bit definition for DSI_VHSACCR register ************/
4636 #define DSI_VHSACCR_HSA 0x00000FFFU
4637 #define DSI_VHSACCR_HSA0 0x00000001U
4638 #define DSI_VHSACCR_HSA1 0x00000002U
4639 #define DSI_VHSACCR_HSA2 0x00000004U
4640 #define DSI_VHSACCR_HSA3 0x00000008U
4641 #define DSI_VHSACCR_HSA4 0x00000010U
4642 #define DSI_VHSACCR_HSA5 0x00000020U
4643 #define DSI_VHSACCR_HSA6 0x00000040U
4644 #define DSI_VHSACCR_HSA7 0x00000080U
4645 #define DSI_VHSACCR_HSA8 0x00000100U
4646 #define DSI_VHSACCR_HSA9 0x00000200U
4647 #define DSI_VHSACCR_HSA10 0x00000400U
4648 #define DSI_VHSACCR_HSA11 0x00000800U
4649 
4650 /******************* Bit definition for DSI_VHBPCCR register ************/
4651 #define DSI_VHBPCCR_HBP 0x00000FFFU
4652 #define DSI_VHBPCCR_HBP0 0x00000001U
4653 #define DSI_VHBPCCR_HBP1 0x00000002U
4654 #define DSI_VHBPCCR_HBP2 0x00000004U
4655 #define DSI_VHBPCCR_HBP3 0x00000008U
4656 #define DSI_VHBPCCR_HBP4 0x00000010U
4657 #define DSI_VHBPCCR_HBP5 0x00000020U
4658 #define DSI_VHBPCCR_HBP6 0x00000040U
4659 #define DSI_VHBPCCR_HBP7 0x00000080U
4660 #define DSI_VHBPCCR_HBP8 0x00000100U
4661 #define DSI_VHBPCCR_HBP9 0x00000200U
4662 #define DSI_VHBPCCR_HBP10 0x00000400U
4663 #define DSI_VHBPCCR_HBP11 0x00000800U
4664 
4665 /******************* Bit definition for DSI_VLCCR register **************/
4666 #define DSI_VLCCR_HLINE 0x00007FFFU
4667 #define DSI_VLCCR_HLINE0 0x00000001U
4668 #define DSI_VLCCR_HLINE1 0x00000002U
4669 #define DSI_VLCCR_HLINE2 0x00000004U
4670 #define DSI_VLCCR_HLINE3 0x00000008U
4671 #define DSI_VLCCR_HLINE4 0x00000010U
4672 #define DSI_VLCCR_HLINE5 0x00000020U
4673 #define DSI_VLCCR_HLINE6 0x00000040U
4674 #define DSI_VLCCR_HLINE7 0x00000080U
4675 #define DSI_VLCCR_HLINE8 0x00000100U
4676 #define DSI_VLCCR_HLINE9 0x00000200U
4677 #define DSI_VLCCR_HLINE10 0x00000400U
4678 #define DSI_VLCCR_HLINE11 0x00000800U
4679 #define DSI_VLCCR_HLINE12 0x00001000U
4680 #define DSI_VLCCR_HLINE13 0x00002000U
4681 #define DSI_VLCCR_HLINE14 0x00004000U
4682 
4683 /******************* Bit definition for DSI_VVSACCR register ***************/
4684 #define DSI_VVSACCR_VSA 0x000003FFU
4685 #define DSI_VVSACCR_VSA0 0x00000001U
4686 #define DSI_VVSACCR_VSA1 0x00000002U
4687 #define DSI_VVSACCR_VSA2 0x00000004U
4688 #define DSI_VVSACCR_VSA3 0x00000008U
4689 #define DSI_VVSACCR_VSA4 0x00000010U
4690 #define DSI_VVSACCR_VSA5 0x00000020U
4691 #define DSI_VVSACCR_VSA6 0x00000040U
4692 #define DSI_VVSACCR_VSA7 0x00000080U
4693 #define DSI_VVSACCR_VSA8 0x00000100U
4694 #define DSI_VVSACCR_VSA9 0x00000200U
4695 
4696 /******************* Bit definition for DSI_VVBPCCR register ************/
4697 #define DSI_VVBPCCR_VBP 0x000003FFU
4698 #define DSI_VVBPCCR_VBP0 0x00000001U
4699 #define DSI_VVBPCCR_VBP1 0x00000002U
4700 #define DSI_VVBPCCR_VBP2 0x00000004U
4701 #define DSI_VVBPCCR_VBP3 0x00000008U
4702 #define DSI_VVBPCCR_VBP4 0x00000010U
4703 #define DSI_VVBPCCR_VBP5 0x00000020U
4704 #define DSI_VVBPCCR_VBP6 0x00000040U
4705 #define DSI_VVBPCCR_VBP7 0x00000080U
4706 #define DSI_VVBPCCR_VBP8 0x00000100U
4707 #define DSI_VVBPCCR_VBP9 0x00000200U
4708 
4709 /******************* Bit definition for DSI_VVFPCCR register ************/
4710 #define DSI_VVFPCCR_VFP 0x000003FFU
4711 #define DSI_VVFPCCR_VFP0 0x00000001U
4712 #define DSI_VVFPCCR_VFP1 0x00000002U
4713 #define DSI_VVFPCCR_VFP2 0x00000004U
4714 #define DSI_VVFPCCR_VFP3 0x00000008U
4715 #define DSI_VVFPCCR_VFP4 0x00000010U
4716 #define DSI_VVFPCCR_VFP5 0x00000020U
4717 #define DSI_VVFPCCR_VFP6 0x00000040U
4718 #define DSI_VVFPCCR_VFP7 0x00000080U
4719 #define DSI_VVFPCCR_VFP8 0x00000100U
4720 #define DSI_VVFPCCR_VFP9 0x00000200U
4721 
4722 /******************* Bit definition for DSI_VVACCR register *************/
4723 #define DSI_VVACCR_VA 0x00003FFFU
4724 #define DSI_VVACCR_VA0 0x00000001U
4725 #define DSI_VVACCR_VA1 0x00000002U
4726 #define DSI_VVACCR_VA2 0x00000004U
4727 #define DSI_VVACCR_VA3 0x00000008U
4728 #define DSI_VVACCR_VA4 0x00000010U
4729 #define DSI_VVACCR_VA5 0x00000020U
4730 #define DSI_VVACCR_VA6 0x00000040U
4731 #define DSI_VVACCR_VA7 0x00000080U
4732 #define DSI_VVACCR_VA8 0x00000100U
4733 #define DSI_VVACCR_VA9 0x00000200U
4734 #define DSI_VVACCR_VA10 0x00000400U
4735 #define DSI_VVACCR_VA11 0x00000800U
4736 #define DSI_VVACCR_VA12 0x00001000U
4737 #define DSI_VVACCR_VA13 0x00002000U
4738 
4739 /******************* Bit definition for DSI_TDCCR register **************/
4740 #define DSI_TDCCR_3DM 0x00000003U
4741 #define DSI_TDCCR_3DM0 0x00000001U
4742 #define DSI_TDCCR_3DM1 0x00000002U
4743 
4744 #define DSI_TDCCR_3DF 0x0000000CU
4745 #define DSI_TDCCR_3DF0 0x00000004U
4746 #define DSI_TDCCR_3DF1 0x00000008U
4747 
4748 #define DSI_TDCCR_SVS 0x00000010U
4749 #define DSI_TDCCR_RF 0x00000020U
4750 #define DSI_TDCCR_S3DC 0x00010000U
4752 /******************* Bit definition for DSI_WCFGR register ***************/
4753 #define DSI_WCFGR_DSIM 0x00000001U
4754 #define DSI_WCFGR_COLMUX 0x0000000EU
4755 #define DSI_WCFGR_COLMUX0 0x00000002U
4756 #define DSI_WCFGR_COLMUX1 0x00000004U
4757 #define DSI_WCFGR_COLMUX2 0x00000008U
4758 
4759 #define DSI_WCFGR_TESRC 0x00000010U
4760 #define DSI_WCFGR_TEPOL 0x00000020U
4761 #define DSI_WCFGR_AR 0x00000040U
4762 #define DSI_WCFGR_VSPOL 0x00000080U
4764 /******************* Bit definition for DSI_WCR register *****************/
4765 #define DSI_WCR_COLM 0x00000001U
4766 #define DSI_WCR_SHTDN 0x00000002U
4767 #define DSI_WCR_LTDCEN 0x00000004U
4768 #define DSI_WCR_DSIEN 0x00000008U
4770 /******************* Bit definition for DSI_WIER register ****************/
4771 #define DSI_WIER_TEIE 0x00000001U
4772 #define DSI_WIER_ERIE 0x00000002U
4773 #define DSI_WIER_PLLLIE 0x00000200U
4774 #define DSI_WIER_PLLUIE 0x00000400U
4775 #define DSI_WIER_RRIE 0x00002000U
4777 /******************* Bit definition for DSI_WISR register ****************/
4778 #define DSI_WISR_TEIF 0x00000001U
4779 #define DSI_WISR_ERIF 0x00000002U
4780 #define DSI_WISR_BUSY 0x00000004U
4781 #define DSI_WISR_PLLLS 0x00000100U
4782 #define DSI_WISR_PLLLIF 0x00000200U
4783 #define DSI_WISR_PLLUIF 0x00000400U
4784 #define DSI_WISR_RRS 0x00001000U
4785 #define DSI_WISR_RRIF 0x00002000U
4787 /******************* Bit definition for DSI_WIFCR register ***************/
4788 #define DSI_WIFCR_CTEIF 0x00000001U
4789 #define DSI_WIFCR_CERIF 0x00000002U
4790 #define DSI_WIFCR_CPLLLIF 0x00000200U
4791 #define DSI_WIFCR_CPLLUIF 0x00000400U
4792 #define DSI_WIFCR_CRRIF 0x00002000U
4794 /******************* Bit definition for DSI_WPCR0 register ***************/
4795 #define DSI_WPCR0_UIX4 0x0000003FU
4796 #define DSI_WPCR0_UIX4_0 0x00000001U
4797 #define DSI_WPCR0_UIX4_1 0x00000002U
4798 #define DSI_WPCR0_UIX4_2 0x00000004U
4799 #define DSI_WPCR0_UIX4_3 0x00000008U
4800 #define DSI_WPCR0_UIX4_4 0x00000010U
4801 #define DSI_WPCR0_UIX4_5 0x00000020U
4802 
4803 #define DSI_WPCR0_SWCL 0x00000040U
4804 #define DSI_WPCR0_SWDL0 0x00000080U
4805 #define DSI_WPCR0_SWDL1 0x00000100U
4806 #define DSI_WPCR0_HSICL 0x00000200U
4807 #define DSI_WPCR0_HSIDL0 0x00000400U
4808 #define DSI_WPCR0_HSIDL1 0x00000800U
4809 #define DSI_WPCR0_FTXSMCL 0x00001000U
4810 #define DSI_WPCR0_FTXSMDL 0x00002000U
4811 #define DSI_WPCR0_CDOFFDL 0x00004000U
4812 #define DSI_WPCR0_TDDL 0x00010000U
4813 #define DSI_WPCR0_PDEN 0x00040000U
4814 #define DSI_WPCR0_TCLKPREPEN 0x00080000U
4815 #define DSI_WPCR0_TCLKZEROEN 0x00100000U
4816 #define DSI_WPCR0_THSPREPEN 0x00200000U
4817 #define DSI_WPCR0_THSTRAILEN 0x00400000U
4818 #define DSI_WPCR0_THSZEROEN 0x00800000U
4819 #define DSI_WPCR0_TLPXDEN 0x01000000U
4820 #define DSI_WPCR0_THSEXITEN 0x02000000U
4821 #define DSI_WPCR0_TLPXCEN 0x04000000U
4822 #define DSI_WPCR0_TCLKPOSTEN 0x08000000U
4824 /******************* Bit definition for DSI_WPCR1 register ***************/
4825 #define DSI_WPCR1_HSTXDCL 0x00000003U
4826 #define DSI_WPCR1_HSTXDCL0 0x00000001U
4827 #define DSI_WPCR1_HSTXDCL1 0x00000002U
4828 
4829 #define DSI_WPCR1_HSTXDDL 0x0000000CU
4830 #define DSI_WPCR1_HSTXDDL0 0x00000004U
4831 #define DSI_WPCR1_HSTXDDL1 0x00000008U
4832 
4833 #define DSI_WPCR1_LPSRCCL 0x000000C0U
4834 #define DSI_WPCR1_LPSRCCL0 0x00000040U
4835 #define DSI_WPCR1_LPSRCCL1 0x00000080U
4836 
4837 #define DSI_WPCR1_LPSRCDL 0x00000300U
4838 #define DSI_WPCR1_LPSRCDL0 0x00000100U
4839 #define DSI_WPCR1_LPSRCDL1 0x00000200U
4840 
4841 #define DSI_WPCR1_SDDC 0x00001000U
4843 #define DSI_WPCR1_LPRXVCDL 0x0000C000U
4844 #define DSI_WPCR1_LPRXVCDL0 0x00004000U
4845 #define DSI_WPCR1_LPRXVCDL1 0x00008000U
4846 
4847 #define DSI_WPCR1_HSTXSRCCL 0x00030000U
4848 #define DSI_WPCR1_HSTXSRCCL0 0x00010000U
4849 #define DSI_WPCR1_HSTXSRCCL1 0x00020000U
4850 
4851 #define DSI_WPCR1_HSTXSRCDL 0x000C0000U
4852 #define DSI_WPCR1_HSTXSRCDL0 0x00040000U
4853 #define DSI_WPCR1_HSTXSRCDL1 0x00080000U
4854 
4855 #define DSI_WPCR1_FLPRXLPM 0x00400000U
4857 #define DSI_WPCR1_LPRXFT 0x06000000U
4858 #define DSI_WPCR1_LPRXFT0 0x02000000U
4859 #define DSI_WPCR1_LPRXFT1 0x04000000U
4860 
4861 /******************* Bit definition for DSI_WPCR2 register ***************/
4862 #define DSI_WPCR2_TCLKPREP 0x000000FFU
4863 #define DSI_WPCR2_TCLKPREP0 0x00000001U
4864 #define DSI_WPCR2_TCLKPREP1 0x00000002U
4865 #define DSI_WPCR2_TCLKPREP2 0x00000004U
4866 #define DSI_WPCR2_TCLKPREP3 0x00000008U
4867 #define DSI_WPCR2_TCLKPREP4 0x00000010U
4868 #define DSI_WPCR2_TCLKPREP5 0x00000020U
4869 #define DSI_WPCR2_TCLKPREP6 0x00000040U
4870 #define DSI_WPCR2_TCLKPREP7 0x00000080U
4871 
4872 #define DSI_WPCR2_TCLKZERO 0x0000FF00U
4873 #define DSI_WPCR2_TCLKZERO0 0x00000100U
4874 #define DSI_WPCR2_TCLKZERO1 0x00000200U
4875 #define DSI_WPCR2_TCLKZERO2 0x00000400U
4876 #define DSI_WPCR2_TCLKZERO3 0x00000800U
4877 #define DSI_WPCR2_TCLKZERO4 0x00001000U
4878 #define DSI_WPCR2_TCLKZERO5 0x00002000U
4879 #define DSI_WPCR2_TCLKZERO6 0x00004000U
4880 #define DSI_WPCR2_TCLKZERO7 0x00008000U
4881 
4882 #define DSI_WPCR2_THSPREP 0x00FF0000U
4883 #define DSI_WPCR2_THSPREP0 0x00010000U
4884 #define DSI_WPCR2_THSPREP1 0x00020000U
4885 #define DSI_WPCR2_THSPREP2 0x00040000U
4886 #define DSI_WPCR2_THSPREP3 0x00080000U
4887 #define DSI_WPCR2_THSPREP4 0x00100000U
4888 #define DSI_WPCR2_THSPREP5 0x00200000U
4889 #define DSI_WPCR2_THSPREP6 0x00400000U
4890 #define DSI_WPCR2_THSPREP7 0x00800000U
4891 
4892 #define DSI_WPCR2_THSTRAIL 0xFF000000U
4893 #define DSI_WPCR2_THSTRAIL0 0x01000000U
4894 #define DSI_WPCR2_THSTRAIL1 0x02000000U
4895 #define DSI_WPCR2_THSTRAIL2 0x04000000U
4896 #define DSI_WPCR2_THSTRAIL3 0x08000000U
4897 #define DSI_WPCR2_THSTRAIL4 0x10000000U
4898 #define DSI_WPCR2_THSTRAIL5 0x20000000U
4899 #define DSI_WPCR2_THSTRAIL6 0x40000000U
4900 #define DSI_WPCR2_THSTRAIL7 0x80000000U
4901 
4902 /******************* Bit definition for DSI_WPCR3 register ***************/
4903 #define DSI_WPCR3_THSZERO 0x000000FFU
4904 #define DSI_WPCR3_THSZERO0 0x00000001U
4905 #define DSI_WPCR3_THSZERO1 0x00000002U
4906 #define DSI_WPCR3_THSZERO2 0x00000004U
4907 #define DSI_WPCR3_THSZERO3 0x00000008U
4908 #define DSI_WPCR3_THSZERO4 0x00000010U
4909 #define DSI_WPCR3_THSZERO5 0x00000020U
4910 #define DSI_WPCR3_THSZERO6 0x00000040U
4911 #define DSI_WPCR3_THSZERO7 0x00000080U
4912 
4913 #define DSI_WPCR3_TLPXD 0x0000FF00U
4914 #define DSI_WPCR3_TLPXD0 0x00000100U
4915 #define DSI_WPCR3_TLPXD1 0x00000200U
4916 #define DSI_WPCR3_TLPXD2 0x00000400U
4917 #define DSI_WPCR3_TLPXD3 0x00000800U
4918 #define DSI_WPCR3_TLPXD4 0x00001000U
4919 #define DSI_WPCR3_TLPXD5 0x00002000U
4920 #define DSI_WPCR3_TLPXD6 0x00004000U
4921 #define DSI_WPCR3_TLPXD7 0x00008000U
4922 
4923 #define DSI_WPCR3_THSEXIT 0x00FF0000U
4924 #define DSI_WPCR3_THSEXIT0 0x00010000U
4925 #define DSI_WPCR3_THSEXIT1 0x00020000U
4926 #define DSI_WPCR3_THSEXIT2 0x00040000U
4927 #define DSI_WPCR3_THSEXIT3 0x00080000U
4928 #define DSI_WPCR3_THSEXIT4 0x00100000U
4929 #define DSI_WPCR3_THSEXIT5 0x00200000U
4930 #define DSI_WPCR3_THSEXIT6 0x00400000U
4931 #define DSI_WPCR3_THSEXIT7 0x00800000U
4932 
4933 #define DSI_WPCR3_TLPXC 0xFF000000U
4934 #define DSI_WPCR3_TLPXC0 0x01000000U
4935 #define DSI_WPCR3_TLPXC1 0x02000000U
4936 #define DSI_WPCR3_TLPXC2 0x04000000U
4937 #define DSI_WPCR3_TLPXC3 0x08000000U
4938 #define DSI_WPCR3_TLPXC4 0x10000000U
4939 #define DSI_WPCR3_TLPXC5 0x20000000U
4940 #define DSI_WPCR3_TLPXC6 0x40000000U
4941 #define DSI_WPCR3_TLPXC7 0x80000000U
4942 
4943 /******************* Bit definition for DSI_WPCR4 register ***************/
4944 #define DSI_WPCR4_TCLKPOST 0x000000FFU
4945 #define DSI_WPCR4_TCLKPOST0 0x00000001U
4946 #define DSI_WPCR4_TCLKPOST1 0x00000002U
4947 #define DSI_WPCR4_TCLKPOST2 0x00000004U
4948 #define DSI_WPCR4_TCLKPOST3 0x00000008U
4949 #define DSI_WPCR4_TCLKPOST4 0x00000010U
4950 #define DSI_WPCR4_TCLKPOST5 0x00000020U
4951 #define DSI_WPCR4_TCLKPOST6 0x00000040U
4952 #define DSI_WPCR4_TCLKPOST7 0x00000080U
4953 
4954 /******************* Bit definition for DSI_WRPCR register ***************/
4955 #define DSI_WRPCR_PLLEN 0x00000001U
4956 #define DSI_WRPCR_PLL_NDIV 0x000001FCU
4957 #define DSI_WRPCR_PLL_NDIV0 0x00000004U
4958 #define DSI_WRPCR_PLL_NDIV1 0x00000008U
4959 #define DSI_WRPCR_PLL_NDIV2 0x00000010U
4960 #define DSI_WRPCR_PLL_NDIV3 0x00000020U
4961 #define DSI_WRPCR_PLL_NDIV4 0x00000040U
4962 #define DSI_WRPCR_PLL_NDIV5 0x00000080U
4963 #define DSI_WRPCR_PLL_NDIV6 0x00000100U
4964 
4965 #define DSI_WRPCR_PLL_IDF 0x00007800U
4966 #define DSI_WRPCR_PLL_IDF0 0x00000800U
4967 #define DSI_WRPCR_PLL_IDF1 0x00001000U
4968 #define DSI_WRPCR_PLL_IDF2 0x00002000U
4969 #define DSI_WRPCR_PLL_IDF3 0x00004000U
4970 
4971 #define DSI_WRPCR_PLL_ODF 0x00030000U
4972 #define DSI_WRPCR_PLL_ODF0 0x00010000U
4973 #define DSI_WRPCR_PLL_ODF1 0x00020000U
4974 
4975 #define DSI_WRPCR_REGEN 0x01000000U
4977 /******************************************************************************/
4978 /* */
4979 /* External Interrupt/Event Controller */
4980 /* */
4981 /******************************************************************************/
4982 /******************* Bit definition for EXTI_IMR register *******************/
4983 #define EXTI_IMR_MR0 0x00000001U
4984 #define EXTI_IMR_MR1 0x00000002U
4985 #define EXTI_IMR_MR2 0x00000004U
4986 #define EXTI_IMR_MR3 0x00000008U
4987 #define EXTI_IMR_MR4 0x00000010U
4988 #define EXTI_IMR_MR5 0x00000020U
4989 #define EXTI_IMR_MR6 0x00000040U
4990 #define EXTI_IMR_MR7 0x00000080U
4991 #define EXTI_IMR_MR8 0x00000100U
4992 #define EXTI_IMR_MR9 0x00000200U
4993 #define EXTI_IMR_MR10 0x00000400U
4994 #define EXTI_IMR_MR11 0x00000800U
4995 #define EXTI_IMR_MR12 0x00001000U
4996 #define EXTI_IMR_MR13 0x00002000U
4997 #define EXTI_IMR_MR14 0x00004000U
4998 #define EXTI_IMR_MR15 0x00008000U
4999 #define EXTI_IMR_MR16 0x00010000U
5000 #define EXTI_IMR_MR17 0x00020000U
5001 #define EXTI_IMR_MR18 0x00040000U
5002 #define EXTI_IMR_MR19 0x00080000U
5003 #define EXTI_IMR_MR20 0x00100000U
5004 #define EXTI_IMR_MR21 0x00200000U
5005 #define EXTI_IMR_MR22 0x00400000U
5007 /******************* Bit definition for EXTI_EMR register *******************/
5008 #define EXTI_EMR_MR0 0x00000001U
5009 #define EXTI_EMR_MR1 0x00000002U
5010 #define EXTI_EMR_MR2 0x00000004U
5011 #define EXTI_EMR_MR3 0x00000008U
5012 #define EXTI_EMR_MR4 0x00000010U
5013 #define EXTI_EMR_MR5 0x00000020U
5014 #define EXTI_EMR_MR6 0x00000040U
5015 #define EXTI_EMR_MR7 0x00000080U
5016 #define EXTI_EMR_MR8 0x00000100U
5017 #define EXTI_EMR_MR9 0x00000200U
5018 #define EXTI_EMR_MR10 0x00000400U
5019 #define EXTI_EMR_MR11 0x00000800U
5020 #define EXTI_EMR_MR12 0x00001000U
5021 #define EXTI_EMR_MR13 0x00002000U
5022 #define EXTI_EMR_MR14 0x00004000U
5023 #define EXTI_EMR_MR15 0x00008000U
5024 #define EXTI_EMR_MR16 0x00010000U
5025 #define EXTI_EMR_MR17 0x00020000U
5026 #define EXTI_EMR_MR18 0x00040000U
5027 #define EXTI_EMR_MR19 0x00080000U
5028 #define EXTI_EMR_MR20 0x00100000U
5029 #define EXTI_EMR_MR21 0x00200000U
5030 #define EXTI_EMR_MR22 0x00400000U
5032 /****************** Bit definition for EXTI_RTSR register *******************/
5033 #define EXTI_RTSR_TR0 0x00000001U
5034 #define EXTI_RTSR_TR1 0x00000002U
5035 #define EXTI_RTSR_TR2 0x00000004U
5036 #define EXTI_RTSR_TR3 0x00000008U
5037 #define EXTI_RTSR_TR4 0x00000010U
5038 #define EXTI_RTSR_TR5 0x00000020U
5039 #define EXTI_RTSR_TR6 0x00000040U
5040 #define EXTI_RTSR_TR7 0x00000080U
5041 #define EXTI_RTSR_TR8 0x00000100U
5042 #define EXTI_RTSR_TR9 0x00000200U
5043 #define EXTI_RTSR_TR10 0x00000400U
5044 #define EXTI_RTSR_TR11 0x00000800U
5045 #define EXTI_RTSR_TR12 0x00001000U
5046 #define EXTI_RTSR_TR13 0x00002000U
5047 #define EXTI_RTSR_TR14 0x00004000U
5048 #define EXTI_RTSR_TR15 0x00008000U
5049 #define EXTI_RTSR_TR16 0x00010000U
5050 #define EXTI_RTSR_TR17 0x00020000U
5051 #define EXTI_RTSR_TR18 0x00040000U
5052 #define EXTI_RTSR_TR19 0x00080000U
5053 #define EXTI_RTSR_TR20 0x00100000U
5054 #define EXTI_RTSR_TR21 0x00200000U
5055 #define EXTI_RTSR_TR22 0x00400000U
5057 /****************** Bit definition for EXTI_FTSR register *******************/
5058 #define EXTI_FTSR_TR0 0x00000001U
5059 #define EXTI_FTSR_TR1 0x00000002U
5060 #define EXTI_FTSR_TR2 0x00000004U
5061 #define EXTI_FTSR_TR3 0x00000008U
5062 #define EXTI_FTSR_TR4 0x00000010U
5063 #define EXTI_FTSR_TR5 0x00000020U
5064 #define EXTI_FTSR_TR6 0x00000040U
5065 #define EXTI_FTSR_TR7 0x00000080U
5066 #define EXTI_FTSR_TR8 0x00000100U
5067 #define EXTI_FTSR_TR9 0x00000200U
5068 #define EXTI_FTSR_TR10 0x00000400U
5069 #define EXTI_FTSR_TR11 0x00000800U
5070 #define EXTI_FTSR_TR12 0x00001000U
5071 #define EXTI_FTSR_TR13 0x00002000U
5072 #define EXTI_FTSR_TR14 0x00004000U
5073 #define EXTI_FTSR_TR15 0x00008000U
5074 #define EXTI_FTSR_TR16 0x00010000U
5075 #define EXTI_FTSR_TR17 0x00020000U
5076 #define EXTI_FTSR_TR18 0x00040000U
5077 #define EXTI_FTSR_TR19 0x00080000U
5078 #define EXTI_FTSR_TR20 0x00100000U
5079 #define EXTI_FTSR_TR21 0x00200000U
5080 #define EXTI_FTSR_TR22 0x00400000U
5082 /****************** Bit definition for EXTI_SWIER register ******************/
5083 #define EXTI_SWIER_SWIER0 0x00000001U
5084 #define EXTI_SWIER_SWIER1 0x00000002U
5085 #define EXTI_SWIER_SWIER2 0x00000004U
5086 #define EXTI_SWIER_SWIER3 0x00000008U
5087 #define EXTI_SWIER_SWIER4 0x00000010U
5088 #define EXTI_SWIER_SWIER5 0x00000020U
5089 #define EXTI_SWIER_SWIER6 0x00000040U
5090 #define EXTI_SWIER_SWIER7 0x00000080U
5091 #define EXTI_SWIER_SWIER8 0x00000100U
5092 #define EXTI_SWIER_SWIER9 0x00000200U
5093 #define EXTI_SWIER_SWIER10 0x00000400U
5094 #define EXTI_SWIER_SWIER11 0x00000800U
5095 #define EXTI_SWIER_SWIER12 0x00001000U
5096 #define EXTI_SWIER_SWIER13 0x00002000U
5097 #define EXTI_SWIER_SWIER14 0x00004000U
5098 #define EXTI_SWIER_SWIER15 0x00008000U
5099 #define EXTI_SWIER_SWIER16 0x00010000U
5100 #define EXTI_SWIER_SWIER17 0x00020000U
5101 #define EXTI_SWIER_SWIER18 0x00040000U
5102 #define EXTI_SWIER_SWIER19 0x00080000U
5103 #define EXTI_SWIER_SWIER20 0x00100000U
5104 #define EXTI_SWIER_SWIER21 0x00200000U
5105 #define EXTI_SWIER_SWIER22 0x00400000U
5107 /******************* Bit definition for EXTI_PR register ********************/
5108 #define EXTI_PR_PR0 0x00000001U
5109 #define EXTI_PR_PR1 0x00000002U
5110 #define EXTI_PR_PR2 0x00000004U
5111 #define EXTI_PR_PR3 0x00000008U
5112 #define EXTI_PR_PR4 0x00000010U
5113 #define EXTI_PR_PR5 0x00000020U
5114 #define EXTI_PR_PR6 0x00000040U
5115 #define EXTI_PR_PR7 0x00000080U
5116 #define EXTI_PR_PR8 0x00000100U
5117 #define EXTI_PR_PR9 0x00000200U
5118 #define EXTI_PR_PR10 0x00000400U
5119 #define EXTI_PR_PR11 0x00000800U
5120 #define EXTI_PR_PR12 0x00001000U
5121 #define EXTI_PR_PR13 0x00002000U
5122 #define EXTI_PR_PR14 0x00004000U
5123 #define EXTI_PR_PR15 0x00008000U
5124 #define EXTI_PR_PR16 0x00010000U
5125 #define EXTI_PR_PR17 0x00020000U
5126 #define EXTI_PR_PR18 0x00040000U
5127 #define EXTI_PR_PR19 0x00080000U
5128 #define EXTI_PR_PR20 0x00100000U
5129 #define EXTI_PR_PR21 0x00200000U
5130 #define EXTI_PR_PR22 0x00400000U
5132 /******************************************************************************/
5133 /* */
5134 /* FLASH */
5135 /* */
5136 /******************************************************************************/
5137 /******************* Bits definition for FLASH_ACR register *****************/
5138 #define FLASH_ACR_LATENCY 0x0000000FU
5139 #define FLASH_ACR_LATENCY_0WS 0x00000000U
5140 #define FLASH_ACR_LATENCY_1WS 0x00000001U
5141 #define FLASH_ACR_LATENCY_2WS 0x00000002U
5142 #define FLASH_ACR_LATENCY_3WS 0x00000003U
5143 #define FLASH_ACR_LATENCY_4WS 0x00000004U
5144 #define FLASH_ACR_LATENCY_5WS 0x00000005U
5145 #define FLASH_ACR_LATENCY_6WS 0x00000006U
5146 #define FLASH_ACR_LATENCY_7WS 0x00000007U
5147 #define FLASH_ACR_LATENCY_8WS 0x00000008U
5148 #define FLASH_ACR_LATENCY_9WS 0x00000009U
5149 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
5150 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
5151 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
5152 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
5153 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
5154 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
5155 #define FLASH_ACR_PRFTEN 0x00000100U
5156 #define FLASH_ACR_ICEN 0x00000200U
5157 #define FLASH_ACR_DCEN 0x00000400U
5158 #define FLASH_ACR_ICRST 0x00000800U
5159 #define FLASH_ACR_DCRST 0x00001000U
5160 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
5161 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
5162 
5163 /******************* Bits definition for FLASH_SR register ******************/
5164 #define FLASH_SR_EOP 0x00000001U
5165 #define FLASH_SR_SOP 0x00000002U
5166 #define FLASH_SR_WRPERR 0x00000010U
5167 #define FLASH_SR_PGAERR 0x00000020U
5168 #define FLASH_SR_PGPERR 0x00000040U
5169 #define FLASH_SR_PGSERR 0x00000080U
5170 #define FLASH_SR_BSY 0x00010000U
5171 
5172 /******************* Bits definition for FLASH_CR register ******************/
5173 #define FLASH_CR_PG 0x00000001U
5174 #define FLASH_CR_SER 0x00000002U
5175 #define FLASH_CR_MER 0x00000004U
5176 #define FLASH_CR_MER1 FLASH_CR_MER
5177 #define FLASH_CR_SNB 0x000000F8U
5178 #define FLASH_CR_SNB_0 0x00000008U
5179 #define FLASH_CR_SNB_1 0x00000010U
5180 #define FLASH_CR_SNB_2 0x00000020U
5181 #define FLASH_CR_SNB_3 0x00000040U
5182 #define FLASH_CR_SNB_4 0x00000080U
5183 #define FLASH_CR_PSIZE 0x00000300U
5184 #define FLASH_CR_PSIZE_0 0x00000100U
5185 #define FLASH_CR_PSIZE_1 0x00000200U
5186 #define FLASH_CR_MER2 0x00008000U
5187 #define FLASH_CR_STRT 0x00010000U
5188 #define FLASH_CR_EOPIE 0x01000000U
5189 #define FLASH_CR_LOCK 0x80000000U
5190 
5191 /******************* Bits definition for FLASH_OPTCR register ***************/
5192 #define FLASH_OPTCR_OPTLOCK 0x00000001U
5193 #define FLASH_OPTCR_OPTSTRT 0x00000002U
5194 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
5195 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
5196 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
5197 #define FLASH_OPTCR_BFB2 0x00000010U
5198 #define FLASH_OPTCR_WDG_SW 0x00000020U
5199 #define FLASH_OPTCR_nRST_STOP 0x00000040U
5200 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
5201 #define FLASH_OPTCR_RDP 0x0000FF00U
5202 #define FLASH_OPTCR_RDP_0 0x00000100U
5203 #define FLASH_OPTCR_RDP_1 0x00000200U
5204 #define FLASH_OPTCR_RDP_2 0x00000400U
5205 #define FLASH_OPTCR_RDP_3 0x00000800U
5206 #define FLASH_OPTCR_RDP_4 0x00001000U
5207 #define FLASH_OPTCR_RDP_5 0x00002000U
5208 #define FLASH_OPTCR_RDP_6 0x00004000U
5209 #define FLASH_OPTCR_RDP_7 0x00008000U
5210 #define FLASH_OPTCR_nWRP 0x0FFF0000U
5211 #define FLASH_OPTCR_nWRP_0 0x00010000U
5212 #define FLASH_OPTCR_nWRP_1 0x00020000U
5213 #define FLASH_OPTCR_nWRP_2 0x00040000U
5214 #define FLASH_OPTCR_nWRP_3 0x00080000U
5215 #define FLASH_OPTCR_nWRP_4 0x00100000U
5216 #define FLASH_OPTCR_nWRP_5 0x00200000U
5217 #define FLASH_OPTCR_nWRP_6 0x00400000U
5218 #define FLASH_OPTCR_nWRP_7 0x00800000U
5219 #define FLASH_OPTCR_nWRP_8 0x01000000U
5220 #define FLASH_OPTCR_nWRP_9 0x02000000U
5221 #define FLASH_OPTCR_nWRP_10 0x04000000U
5222 #define FLASH_OPTCR_nWRP_11 0x08000000U
5223 #define FLASH_OPTCR_DB1M 0x40000000U
5224 #define FLASH_OPTCR_SPRMOD 0x80000000U
5225 
5226 /****************** Bits definition for FLASH_OPTCR1 register ***************/
5227 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
5228 #define FLASH_OPTCR1_nWRP_0 0x00010000U
5229 #define FLASH_OPTCR1_nWRP_1 0x00020000U
5230 #define FLASH_OPTCR1_nWRP_2 0x00040000U
5231 #define FLASH_OPTCR1_nWRP_3 0x00080000U
5232 #define FLASH_OPTCR1_nWRP_4 0x00100000U
5233 #define FLASH_OPTCR1_nWRP_5 0x00200000U
5234 #define FLASH_OPTCR1_nWRP_6 0x00400000U
5235 #define FLASH_OPTCR1_nWRP_7 0x00800000U
5236 #define FLASH_OPTCR1_nWRP_8 0x01000000U
5237 #define FLASH_OPTCR1_nWRP_9 0x02000000U
5238 #define FLASH_OPTCR1_nWRP_10 0x04000000U
5239 #define FLASH_OPTCR1_nWRP_11 0x08000000U
5240 
5241 /******************************************************************************/
5242 /* */
5243 /* Flexible Memory Controller */
5244 /* */
5245 /******************************************************************************/
5246 /****************** Bit definition for FMC_BCR1 register *******************/
5247 #define FMC_BCR1_MBKEN 0x00000001U
5248 #define FMC_BCR1_MUXEN 0x00000002U
5250 #define FMC_BCR1_MTYP 0x0000000CU
5251 #define FMC_BCR1_MTYP_0 0x00000004U
5252 #define FMC_BCR1_MTYP_1 0x00000008U
5254 #define FMC_BCR1_MWID 0x00000030U
5255 #define FMC_BCR1_MWID_0 0x00000010U
5256 #define FMC_BCR1_MWID_1 0x00000020U
5258 #define FMC_BCR1_FACCEN 0x00000040U
5259 #define FMC_BCR1_BURSTEN 0x00000100U
5260 #define FMC_BCR1_WAITPOL 0x00000200U
5261 #define FMC_BCR1_WAITCFG 0x00000800U
5262 #define FMC_BCR1_WREN 0x00001000U
5263 #define FMC_BCR1_WAITEN 0x00002000U
5264 #define FMC_BCR1_EXTMOD 0x00004000U
5265 #define FMC_BCR1_ASYNCWAIT 0x00008000U
5266 #define FMC_BCR1_CPSIZE 0x00070000U
5267 #define FMC_BCR1_CPSIZE_0 0x00010000U
5268 #define FMC_BCR1_CPSIZE_1 0x00020000U
5269 #define FMC_BCR1_CPSIZE_2 0x00040000U
5270 #define FMC_BCR1_CBURSTRW 0x00080000U
5271 #define FMC_BCR1_CCLKEN 0x00100000U
5272 #define FMC_BCR1_WFDIS 0x00200000U
5274 /****************** Bit definition for FMC_BCR2 register *******************/
5275 #define FMC_BCR2_MBKEN 0x00000001U
5276 #define FMC_BCR2_MUXEN 0x00000002U
5278 #define FMC_BCR2_MTYP 0x0000000CU
5279 #define FMC_BCR2_MTYP_0 0x00000004U
5280 #define FMC_BCR2_MTYP_1 0x00000008U
5282 #define FMC_BCR2_MWID 0x00000030U
5283 #define FMC_BCR2_MWID_0 0x00000010U
5284 #define FMC_BCR2_MWID_1 0x00000020U
5286 #define FMC_BCR2_FACCEN 0x00000040U
5287 #define FMC_BCR2_BURSTEN 0x00000100U
5288 #define FMC_BCR2_WAITPOL 0x00000200U
5289 #define FMC_BCR2_WAITCFG 0x00000800U
5290 #define FMC_BCR2_WREN 0x00001000U
5291 #define FMC_BCR2_WAITEN 0x00002000U
5292 #define FMC_BCR2_EXTMOD 0x00004000U
5293 #define FMC_BCR2_ASYNCWAIT 0x00008000U
5294 #define FMC_BCR2_CBURSTRW 0x00080000U
5296 /****************** Bit definition for FMC_BCR3 register *******************/
5297 #define FMC_BCR3_MBKEN 0x00000001U
5298 #define FMC_BCR3_MUXEN 0x00000002U
5300 #define FMC_BCR3_MTYP 0x0000000CU
5301 #define FMC_BCR3_MTYP_0 0x00000004U
5302 #define FMC_BCR3_MTYP_1 0x00000008U
5304 #define FMC_BCR3_MWID 0x00000030U
5305 #define FMC_BCR3_MWID_0 0x00000010U
5306 #define FMC_BCR3_MWID_1 0x00000020U
5308 #define FMC_BCR3_FACCEN 0x00000040U
5309 #define FMC_BCR3_BURSTEN 0x00000100U
5310 #define FMC_BCR3_WAITPOL 0x00000200U
5311 #define FMC_BCR3_WAITCFG 0x00000800U
5312 #define FMC_BCR3_WREN 0x00001000U
5313 #define FMC_BCR3_WAITEN 0x00002000U
5314 #define FMC_BCR3_EXTMOD 0x00004000U
5315 #define FMC_BCR3_ASYNCWAIT 0x00008000U
5316 #define FMC_BCR3_CBURSTRW 0x00080000U
5318 /****************** Bit definition for FMC_BCR4 register *******************/
5319 #define FMC_BCR4_MBKEN 0x00000001U
5320 #define FMC_BCR4_MUXEN 0x00000002U
5322 #define FMC_BCR4_MTYP 0x0000000CU
5323 #define FMC_BCR4_MTYP_0 0x00000004U
5324 #define FMC_BCR4_MTYP_1 0x00000008U
5326 #define FMC_BCR4_MWID 0x00000030U
5327 #define FMC_BCR4_MWID_0 0x00000010U
5328 #define FMC_BCR4_MWID_1 0x00000020U
5330 #define FMC_BCR4_FACCEN 0x00000040U
5331 #define FMC_BCR4_BURSTEN 0x00000100U
5332 #define FMC_BCR4_WAITPOL 0x00000200U
5333 #define FMC_BCR4_WAITCFG 0x00000800U
5334 #define FMC_BCR4_WREN 0x00001000U
5335 #define FMC_BCR4_WAITEN 0x00002000U
5336 #define FMC_BCR4_EXTMOD 0x00004000U
5337 #define FMC_BCR4_ASYNCWAIT 0x00008000U
5338 #define FMC_BCR4_CBURSTRW 0x00080000U
5340 /****************** Bit definition for FMC_BTR1 register ******************/
5341 #define FMC_BTR1_ADDSET 0x0000000FU
5342 #define FMC_BTR1_ADDSET_0 0x00000001U
5343 #define FMC_BTR1_ADDSET_1 0x00000002U
5344 #define FMC_BTR1_ADDSET_2 0x00000004U
5345 #define FMC_BTR1_ADDSET_3 0x00000008U
5347 #define FMC_BTR1_ADDHLD 0x000000F0U
5348 #define FMC_BTR1_ADDHLD_0 0x00000010U
5349 #define FMC_BTR1_ADDHLD_1 0x00000020U
5350 #define FMC_BTR1_ADDHLD_2 0x00000040U
5351 #define FMC_BTR1_ADDHLD_3 0x00000080U
5353 #define FMC_BTR1_DATAST 0x0000FF00U
5354 #define FMC_BTR1_DATAST_0 0x00000100U
5355 #define FMC_BTR1_DATAST_1 0x00000200U
5356 #define FMC_BTR1_DATAST_2 0x00000400U
5357 #define FMC_BTR1_DATAST_3 0x00000800U
5358 #define FMC_BTR1_DATAST_4 0x00001000U
5359 #define FMC_BTR1_DATAST_5 0x00002000U
5360 #define FMC_BTR1_DATAST_6 0x00004000U
5361 #define FMC_BTR1_DATAST_7 0x00008000U
5363 #define FMC_BTR1_BUSTURN 0x000F0000U
5364 #define FMC_BTR1_BUSTURN_0 0x00010000U
5365 #define FMC_BTR1_BUSTURN_1 0x00020000U
5366 #define FMC_BTR1_BUSTURN_2 0x00040000U
5367 #define FMC_BTR1_BUSTURN_3 0x00080000U
5369 #define FMC_BTR1_CLKDIV 0x00F00000U
5370 #define FMC_BTR1_CLKDIV_0 0x00100000U
5371 #define FMC_BTR1_CLKDIV_1 0x00200000U
5372 #define FMC_BTR1_CLKDIV_2 0x00400000U
5373 #define FMC_BTR1_CLKDIV_3 0x00800000U
5375 #define FMC_BTR1_DATLAT 0x0F000000U
5376 #define FMC_BTR1_DATLAT_0 0x01000000U
5377 #define FMC_BTR1_DATLAT_1 0x02000000U
5378 #define FMC_BTR1_DATLAT_2 0x04000000U
5379 #define FMC_BTR1_DATLAT_3 0x08000000U
5381 #define FMC_BTR1_ACCMOD 0x30000000U
5382 #define FMC_BTR1_ACCMOD_0 0x10000000U
5383 #define FMC_BTR1_ACCMOD_1 0x20000000U
5385 /****************** Bit definition for FMC_BTR2 register *******************/
5386 #define FMC_BTR2_ADDSET 0x0000000FU
5387 #define FMC_BTR2_ADDSET_0 0x00000001U
5388 #define FMC_BTR2_ADDSET_1 0x00000002U
5389 #define FMC_BTR2_ADDSET_2 0x00000004U
5390 #define FMC_BTR2_ADDSET_3 0x00000008U
5392 #define FMC_BTR2_ADDHLD 0x000000F0U
5393 #define FMC_BTR2_ADDHLD_0 0x00000010U
5394 #define FMC_BTR2_ADDHLD_1 0x00000020U
5395 #define FMC_BTR2_ADDHLD_2 0x00000040U
5396 #define FMC_BTR2_ADDHLD_3 0x00000080U
5398 #define FMC_BTR2_DATAST 0x0000FF00U
5399 #define FMC_BTR2_DATAST_0 0x00000100U
5400 #define FMC_BTR2_DATAST_1 0x00000200U
5401 #define FMC_BTR2_DATAST_2 0x00000400U
5402 #define FMC_BTR2_DATAST_3 0x00000800U
5403 #define FMC_BTR2_DATAST_4 0x00001000U
5404 #define FMC_BTR2_DATAST_5 0x00002000U
5405 #define FMC_BTR2_DATAST_6 0x00004000U
5406 #define FMC_BTR2_DATAST_7 0x00008000U
5408 #define FMC_BTR2_BUSTURN 0x000F0000U
5409 #define FMC_BTR2_BUSTURN_0 0x00010000U
5410 #define FMC_BTR2_BUSTURN_1 0x00020000U
5411 #define FMC_BTR2_BUSTURN_2 0x00040000U
5412 #define FMC_BTR2_BUSTURN_3 0x00080000U
5414 #define FMC_BTR2_CLKDIV 0x00F00000U
5415 #define FMC_BTR2_CLKDIV_0 0x00100000U
5416 #define FMC_BTR2_CLKDIV_1 0x00200000U
5417 #define FMC_BTR2_CLKDIV_2 0x00400000U
5418 #define FMC_BTR2_CLKDIV_3 0x00800000U
5420 #define FMC_BTR2_DATLAT 0x0F000000U
5421 #define FMC_BTR2_DATLAT_0 0x01000000U
5422 #define FMC_BTR2_DATLAT_1 0x02000000U
5423 #define FMC_BTR2_DATLAT_2 0x04000000U
5424 #define FMC_BTR2_DATLAT_3 0x08000000U
5426 #define FMC_BTR2_ACCMOD 0x30000000U
5427 #define FMC_BTR2_ACCMOD_0 0x10000000U
5428 #define FMC_BTR2_ACCMOD_1 0x20000000U
5430 /******************* Bit definition for FMC_BTR3 register *******************/
5431 #define FMC_BTR3_ADDSET 0x0000000FU
5432 #define FMC_BTR3_ADDSET_0 0x00000001U
5433 #define FMC_BTR3_ADDSET_1 0x00000002U
5434 #define FMC_BTR3_ADDSET_2 0x00000004U
5435 #define FMC_BTR3_ADDSET_3 0x00000008U
5437 #define FMC_BTR3_ADDHLD 0x000000F0U
5438 #define FMC_BTR3_ADDHLD_0 0x00000010U
5439 #define FMC_BTR3_ADDHLD_1 0x00000020U
5440 #define FMC_BTR3_ADDHLD_2 0x00000040U
5441 #define FMC_BTR3_ADDHLD_3 0x00000080U
5443 #define FMC_BTR3_DATAST 0x0000FF00U
5444 #define FMC_BTR3_DATAST_0 0x00000100U
5445 #define FMC_BTR3_DATAST_1 0x00000200U
5446 #define FMC_BTR3_DATAST_2 0x00000400U
5447 #define FMC_BTR3_DATAST_3 0x00000800U
5448 #define FMC_BTR3_DATAST_4 0x00001000U
5449 #define FMC_BTR3_DATAST_5 0x00002000U
5450 #define FMC_BTR3_DATAST_6 0x00004000U
5451 #define FMC_BTR3_DATAST_7 0x00008000U
5453 #define FMC_BTR3_BUSTURN 0x000F0000U
5454 #define FMC_BTR3_BUSTURN_0 0x00010000U
5455 #define FMC_BTR3_BUSTURN_1 0x00020000U
5456 #define FMC_BTR3_BUSTURN_2 0x00040000U
5457 #define FMC_BTR3_BUSTURN_3 0x00080000U
5459 #define FMC_BTR3_CLKDIV 0x00F00000U
5460 #define FMC_BTR3_CLKDIV_0 0x00100000U
5461 #define FMC_BTR3_CLKDIV_1 0x00200000U
5462 #define FMC_BTR3_CLKDIV_2 0x00400000U
5463 #define FMC_BTR3_CLKDIV_3 0x00800000U
5465 #define FMC_BTR3_DATLAT 0x0F000000U
5466 #define FMC_BTR3_DATLAT_0 0x01000000U
5467 #define FMC_BTR3_DATLAT_1 0x02000000U
5468 #define FMC_BTR3_DATLAT_2 0x04000000U
5469 #define FMC_BTR3_DATLAT_3 0x08000000U
5471 #define FMC_BTR3_ACCMOD 0x30000000U
5472 #define FMC_BTR3_ACCMOD_0 0x10000000U
5473 #define FMC_BTR3_ACCMOD_1 0x20000000U
5475 /****************** Bit definition for FMC_BTR4 register *******************/
5476 #define FMC_BTR4_ADDSET 0x0000000FU
5477 #define FMC_BTR4_ADDSET_0 0x00000001U
5478 #define FMC_BTR4_ADDSET_1 0x00000002U
5479 #define FMC_BTR4_ADDSET_2 0x00000004U
5480 #define FMC_BTR4_ADDSET_3 0x00000008U
5482 #define FMC_BTR4_ADDHLD 0x000000F0U
5483 #define FMC_BTR4_ADDHLD_0 0x00000010U
5484 #define FMC_BTR4_ADDHLD_1 0x00000020U
5485 #define FMC_BTR4_ADDHLD_2 0x00000040U
5486 #define FMC_BTR4_ADDHLD_3 0x00000080U
5488 #define FMC_BTR4_DATAST 0x0000FF00U
5489 #define FMC_BTR4_DATAST_0 0x00000100U
5490 #define FMC_BTR4_DATAST_1 0x00000200U
5491 #define FMC_BTR4_DATAST_2 0x00000400U
5492 #define FMC_BTR4_DATAST_3 0x00000800U
5493 #define FMC_BTR4_DATAST_4 0x00001000U
5494 #define FMC_BTR4_DATAST_5 0x00002000U
5495 #define FMC_BTR4_DATAST_6 0x00004000U
5496 #define FMC_BTR4_DATAST_7 0x00008000U
5498 #define FMC_BTR4_BUSTURN 0x000F0000U
5499 #define FMC_BTR4_BUSTURN_0 0x00010000U
5500 #define FMC_BTR4_BUSTURN_1 0x00020000U
5501 #define FMC_BTR4_BUSTURN_2 0x00040000U
5502 #define FMC_BTR4_BUSTURN_3 0x00080000U
5504 #define FMC_BTR4_CLKDIV 0x00F00000U
5505 #define FMC_BTR4_CLKDIV_0 0x00100000U
5506 #define FMC_BTR4_CLKDIV_1 0x00200000U
5507 #define FMC_BTR4_CLKDIV_2 0x00400000U
5508 #define FMC_BTR4_CLKDIV_3 0x00800000U
5510 #define FMC_BTR4_DATLAT 0x0F000000U
5511 #define FMC_BTR4_DATLAT_0 0x01000000U
5512 #define FMC_BTR4_DATLAT_1 0x02000000U
5513 #define FMC_BTR4_DATLAT_2 0x04000000U
5514 #define FMC_BTR4_DATLAT_3 0x08000000U
5516 #define FMC_BTR4_ACCMOD 0x30000000U
5517 #define FMC_BTR4_ACCMOD_0 0x10000000U
5518 #define FMC_BTR4_ACCMOD_1 0x20000000U
5520 /****************** Bit definition for FMC_BWTR1 register ******************/
5521 #define FMC_BWTR1_ADDSET 0x0000000FU
5522 #define FMC_BWTR1_ADDSET_0 0x00000001U
5523 #define FMC_BWTR1_ADDSET_1 0x00000002U
5524 #define FMC_BWTR1_ADDSET_2 0x00000004U
5525 #define FMC_BWTR1_ADDSET_3 0x00000008U
5527 #define FMC_BWTR1_ADDHLD 0x000000F0U
5528 #define FMC_BWTR1_ADDHLD_0 0x00000010U
5529 #define FMC_BWTR1_ADDHLD_1 0x00000020U
5530 #define FMC_BWTR1_ADDHLD_2 0x00000040U
5531 #define FMC_BWTR1_ADDHLD_3 0x00000080U
5533 #define FMC_BWTR1_DATAST 0x0000FF00U
5534 #define FMC_BWTR1_DATAST_0 0x00000100U
5535 #define FMC_BWTR1_DATAST_1 0x00000200U
5536 #define FMC_BWTR1_DATAST_2 0x00000400U
5537 #define FMC_BWTR1_DATAST_3 0x00000800U
5538 #define FMC_BWTR1_DATAST_4 0x00001000U
5539 #define FMC_BWTR1_DATAST_5 0x00002000U
5540 #define FMC_BWTR1_DATAST_6 0x00004000U
5541 #define FMC_BWTR1_DATAST_7 0x00008000U
5543 #define FMC_BWTR1_BUSTURN 0x000F0000U
5544 #define FMC_BWTR1_BUSTURN_0 0x00010000U
5545 #define FMC_BWTR1_BUSTURN_1 0x00020000U
5546 #define FMC_BWTR1_BUSTURN_2 0x00040000U
5547 #define FMC_BWTR1_BUSTURN_3 0x00080000U
5549 #define FMC_BWTR1_ACCMOD 0x30000000U
5550 #define FMC_BWTR1_ACCMOD_0 0x10000000U
5551 #define FMC_BWTR1_ACCMOD_1 0x20000000U
5553 /****************** Bit definition for FMC_BWTR2 register ******************/
5554 #define FMC_BWTR2_ADDSET 0x0000000FU
5555 #define FMC_BWTR2_ADDSET_0 0x00000001U
5556 #define FMC_BWTR2_ADDSET_1 0x00000002U
5557 #define FMC_BWTR2_ADDSET_2 0x00000004U
5558 #define FMC_BWTR2_ADDSET_3 0x00000008U
5560 #define FMC_BWTR2_ADDHLD 0x000000F0U
5561 #define FMC_BWTR2_ADDHLD_0 0x00000010U
5562 #define FMC_BWTR2_ADDHLD_1 0x00000020U
5563 #define FMC_BWTR2_ADDHLD_2 0x00000040U
5564 #define FMC_BWTR2_ADDHLD_3 0x00000080U
5566 #define FMC_BWTR2_DATAST 0x0000FF00U
5567 #define FMC_BWTR2_DATAST_0 0x00000100U
5568 #define FMC_BWTR2_DATAST_1 0x00000200U
5569 #define FMC_BWTR2_DATAST_2 0x00000400U
5570 #define FMC_BWTR2_DATAST_3 0x00000800U
5571 #define FMC_BWTR2_DATAST_4 0x00001000U
5572 #define FMC_BWTR2_DATAST_5 0x00002000U
5573 #define FMC_BWTR2_DATAST_6 0x00004000U
5574 #define FMC_BWTR2_DATAST_7 0x00008000U
5576 #define FMC_BWTR2_BUSTURN 0x000F0000U
5577 #define FMC_BWTR2_BUSTURN_0 0x00010000U
5578 #define FMC_BWTR2_BUSTURN_1 0x00020000U
5579 #define FMC_BWTR2_BUSTURN_2 0x00040000U
5580 #define FMC_BWTR2_BUSTURN_3 0x00080000U
5582 #define FMC_BWTR2_ACCMOD 0x30000000U
5583 #define FMC_BWTR2_ACCMOD_0 0x10000000U
5584 #define FMC_BWTR2_ACCMOD_1 0x20000000U
5586 /****************** Bit definition for FMC_BWTR3 register ******************/
5587 #define FMC_BWTR3_ADDSET 0x0000000FU
5588 #define FMC_BWTR3_ADDSET_0 0x00000001U
5589 #define FMC_BWTR3_ADDSET_1 0x00000002U
5590 #define FMC_BWTR3_ADDSET_2 0x00000004U
5591 #define FMC_BWTR3_ADDSET_3 0x00000008U
5593 #define FMC_BWTR3_ADDHLD 0x000000F0U
5594 #define FMC_BWTR3_ADDHLD_0 0x00000010U
5595 #define FMC_BWTR3_ADDHLD_1 0x00000020U
5596 #define FMC_BWTR3_ADDHLD_2 0x00000040U
5597 #define FMC_BWTR3_ADDHLD_3 0x00000080U
5599 #define FMC_BWTR3_DATAST 0x0000FF00U
5600 #define FMC_BWTR3_DATAST_0 0x00000100U
5601 #define FMC_BWTR3_DATAST_1 0x00000200U
5602 #define FMC_BWTR3_DATAST_2 0x00000400U
5603 #define FMC_BWTR3_DATAST_3 0x00000800U
5604 #define FMC_BWTR3_DATAST_4 0x00001000U
5605 #define FMC_BWTR3_DATAST_5 0x00002000U
5606 #define FMC_BWTR3_DATAST_6 0x00004000U
5607 #define FMC_BWTR3_DATAST_7 0x00008000U
5609 #define FMC_BWTR3_BUSTURN 0x000F0000U
5610 #define FMC_BWTR3_BUSTURN_0 0x00010000U
5611 #define FMC_BWTR3_BUSTURN_1 0x00020000U
5612 #define FMC_BWTR3_BUSTURN_2 0x00040000U
5613 #define FMC_BWTR3_BUSTURN_3 0x00080000U
5615 #define FMC_BWTR3_ACCMOD 0x30000000U
5616 #define FMC_BWTR3_ACCMOD_0 0x10000000U
5617 #define FMC_BWTR3_ACCMOD_1 0x20000000U
5619 /****************** Bit definition for FMC_BWTR4 register ******************/
5620 #define FMC_BWTR4_ADDSET 0x0000000FU
5621 #define FMC_BWTR4_ADDSET_0 0x00000001U
5622 #define FMC_BWTR4_ADDSET_1 0x00000002U
5623 #define FMC_BWTR4_ADDSET_2 0x00000004U
5624 #define FMC_BWTR4_ADDSET_3 0x00000008U
5626 #define FMC_BWTR4_ADDHLD 0x000000F0U
5627 #define FMC_BWTR4_ADDHLD_0 0x00000010U
5628 #define FMC_BWTR4_ADDHLD_1 0x00000020U
5629 #define FMC_BWTR4_ADDHLD_2 0x00000040U
5630 #define FMC_BWTR4_ADDHLD_3 0x00000080U
5632 #define FMC_BWTR4_DATAST 0x0000FF00U
5633 #define FMC_BWTR4_DATAST_0 0x00000100U
5634 #define FMC_BWTR4_DATAST_1 0x00000200U
5635 #define FMC_BWTR4_DATAST_2 0x00000400U
5636 #define FMC_BWTR4_DATAST_3 0x00000800U
5637 #define FMC_BWTR4_DATAST_4 0x00001000U
5638 #define FMC_BWTR4_DATAST_5 0x00002000U
5639 #define FMC_BWTR4_DATAST_6 0x00004000U
5640 #define FMC_BWTR4_DATAST_7 0x00008000U
5642 #define FMC_BWTR4_BUSTURN 0x000F0000U
5643 #define FMC_BWTR4_BUSTURN_0 0x00010000U
5644 #define FMC_BWTR4_BUSTURN_1 0x00020000U
5645 #define FMC_BWTR4_BUSTURN_2 0x00040000U
5646 #define FMC_BWTR4_BUSTURN_3 0x00080000U
5648 #define FMC_BWTR4_ACCMOD 0x30000000U
5649 #define FMC_BWTR4_ACCMOD_0 0x10000000U
5650 #define FMC_BWTR4_ACCMOD_1 0x20000000U
5652 /****************** Bit definition for FMC_PCR register *******************/
5653 #define FMC_PCR_PWAITEN 0x00000002U
5654 #define FMC_PCR_PBKEN 0x00000004U
5655 #define FMC_PCR_PTYP 0x00000008U
5657 #define FMC_PCR_PWID 0x00000030U
5658 #define FMC_PCR_PWID_0 0x00000010U
5659 #define FMC_PCR_PWID_1 0x00000020U
5661 #define FMC_PCR_ECCEN 0x00000040U
5663 #define FMC_PCR_TCLR 0x00001E00U
5664 #define FMC_PCR_TCLR_0 0x00000200U
5665 #define FMC_PCR_TCLR_1 0x00000400U
5666 #define FMC_PCR_TCLR_2 0x00000800U
5667 #define FMC_PCR_TCLR_3 0x00001000U
5669 #define FMC_PCR_TAR 0x0001E000U
5670 #define FMC_PCR_TAR_0 0x00002000U
5671 #define FMC_PCR_TAR_1 0x00004000U
5672 #define FMC_PCR_TAR_2 0x00008000U
5673 #define FMC_PCR_TAR_3 0x00010000U
5675 #define FMC_PCR_ECCPS 0x000E0000U
5676 #define FMC_PCR_ECCPS_0 0x00020000U
5677 #define FMC_PCR_ECCPS_1 0x00040000U
5678 #define FMC_PCR_ECCPS_2 0x00080000U
5680 /******************* Bit definition for FMC_SR register *******************/
5681 #define FMC_SR_IRS 0x01U
5682 #define FMC_SR_ILS 0x02U
5683 #define FMC_SR_IFS 0x04U
5684 #define FMC_SR_IREN 0x08U
5685 #define FMC_SR_ILEN 0x10U
5686 #define FMC_SR_IFEN 0x20U
5687 #define FMC_SR_FEMPT 0x40U
5689 /****************** Bit definition for FMC_PMEM register ******************/
5690 #define FMC_PMEM_MEMSET2 0x000000FFU
5691 #define FMC_PMEM_MEMSET2_0 0x00000001U
5692 #define FMC_PMEM_MEMSET2_1 0x00000002U
5693 #define FMC_PMEM_MEMSET2_2 0x00000004U
5694 #define FMC_PMEM_MEMSET2_3 0x00000008U
5695 #define FMC_PMEM_MEMSET2_4 0x00000010U
5696 #define FMC_PMEM_MEMSET2_5 0x00000020U
5697 #define FMC_PMEM_MEMSET2_6 0x00000040U
5698 #define FMC_PMEM_MEMSET2_7 0x00000080U
5700 #define FMC_PMEM_MEMWAIT2 0x0000FF00U
5701 #define FMC_PMEM_MEMWAIT2_0 0x00000100U
5702 #define FMC_PMEM_MEMWAIT2_1 0x00000200U
5703 #define FMC_PMEM_MEMWAIT2_2 0x00000400U
5704 #define FMC_PMEM_MEMWAIT2_3 0x00000800U
5705 #define FMC_PMEM_MEMWAIT2_4 0x00001000U
5706 #define FMC_PMEM_MEMWAIT2_5 0x00002000U
5707 #define FMC_PMEM_MEMWAIT2_6 0x00004000U
5708 #define FMC_PMEM_MEMWAIT2_7 0x00008000U
5710 #define FMC_PMEM_MEMHOLD2 0x00FF0000U
5711 #define FMC_PMEM_MEMHOLD2_0 0x00010000U
5712 #define FMC_PMEM_MEMHOLD2_1 0x00020000U
5713 #define FMC_PMEM_MEMHOLD2_2 0x00040000U
5714 #define FMC_PMEM_MEMHOLD2_3 0x00080000U
5715 #define FMC_PMEM_MEMHOLD2_4 0x00100000U
5716 #define FMC_PMEM_MEMHOLD2_5 0x00200000U
5717 #define FMC_PMEM_MEMHOLD2_6 0x00400000U
5718 #define FMC_PMEM_MEMHOLD2_7 0x00800000U
5720 #define FMC_PMEM_MEMHIZ2 0xFF000000U
5721 #define FMC_PMEM_MEMHIZ2_0 0x01000000U
5722 #define FMC_PMEM_MEMHIZ2_1 0x02000000U
5723 #define FMC_PMEM_MEMHIZ2_2 0x04000000U
5724 #define FMC_PMEM_MEMHIZ2_3 0x08000000U
5725 #define FMC_PMEM_MEMHIZ2_4 0x10000000U
5726 #define FMC_PMEM_MEMHIZ2_5 0x20000000U
5727 #define FMC_PMEM_MEMHIZ2_6 0x40000000U
5728 #define FMC_PMEM_MEMHIZ2_7 0x80000000U
5730 /****************** Bit definition for FMC_PATT register ******************/
5731 #define FMC_PATT_ATTSET2 0x000000FFU
5732 #define FMC_PATT_ATTSET2_0 0x00000001U
5733 #define FMC_PATT_ATTSET2_1 0x00000002U
5734 #define FMC_PATT_ATTSET2_2 0x00000004U
5735 #define FMC_PATT_ATTSET2_3 0x00000008U
5736 #define FMC_PATT_ATTSET2_4 0x00000010U
5737 #define FMC_PATT_ATTSET2_5 0x00000020U
5738 #define FMC_PATT_ATTSET2_6 0x00000040U
5739 #define FMC_PATT_ATTSET2_7 0x00000080U
5741 #define FMC_PATT_ATTWAIT2 0x0000FF00U
5742 #define FMC_PATT_ATTWAIT2_0 0x00000100U
5743 #define FMC_PATT_ATTWAIT2_1 0x00000200U
5744 #define FMC_PATT_ATTWAIT2_2 0x00000400U
5745 #define FMC_PATT_ATTWAIT2_3 0x00000800U
5746 #define FMC_PATT_ATTWAIT2_4 0x00001000U
5747 #define FMC_PATT_ATTWAIT2_5 0x00002000U
5748 #define FMC_PATT_ATTWAIT2_6 0x00004000U
5749 #define FMC_PATT_ATTWAIT2_7 0x00008000U
5751 #define FMC_PATT_ATTHOLD2 0x00FF0000U
5752 #define FMC_PATT_ATTHOLD2_0 0x00010000U
5753 #define FMC_PATT_ATTHOLD2_1 0x00020000U
5754 #define FMC_PATT_ATTHOLD2_2 0x00040000U
5755 #define FMC_PATT_ATTHOLD2_3 0x00080000U
5756 #define FMC_PATT_ATTHOLD2_4 0x00100000U
5757 #define FMC_PATT_ATTHOLD2_5 0x00200000U
5758 #define FMC_PATT_ATTHOLD2_6 0x00400000U
5759 #define FMC_PATT_ATTHOLD2_7 0x00800000U
5761 #define FMC_PATT_ATTHIZ2 0xFF000000U
5762 #define FMC_PATT_ATTHIZ2_0 0x01000000U
5763 #define FMC_PATT_ATTHIZ2_1 0x02000000U
5764 #define FMC_PATT_ATTHIZ2_2 0x04000000U
5765 #define FMC_PATT_ATTHIZ2_3 0x08000000U
5766 #define FMC_PATT_ATTHIZ2_4 0x10000000U
5767 #define FMC_PATT_ATTHIZ2_5 0x20000000U
5768 #define FMC_PATT_ATTHIZ2_6 0x40000000U
5769 #define FMC_PATT_ATTHIZ2_7 0x80000000U
5771 /****************** Bit definition for FMC_ECCR register ******************/
5772 #define FMC_ECCR_ECC2 0xFFFFFFFFU
5774 /****************** Bit definition for FMC_SDCR1 register ******************/
5775 #define FMC_SDCR1_NC 0x00000003U
5776 #define FMC_SDCR1_NC_0 0x00000001U
5777 #define FMC_SDCR1_NC_1 0x00000002U
5779 #define FMC_SDCR1_NR 0x0000000CU
5780 #define FMC_SDCR1_NR_0 0x00000004U
5781 #define FMC_SDCR1_NR_1 0x00000008U
5783 #define FMC_SDCR1_MWID 0x00000030U
5784 #define FMC_SDCR1_MWID_0 0x00000010U
5785 #define FMC_SDCR1_MWID_1 0x00000020U
5787 #define FMC_SDCR1_NB 0x00000040U
5789 #define FMC_SDCR1_CAS 0x00000180U
5790 #define FMC_SDCR1_CAS_0 0x00000080U
5791 #define FMC_SDCR1_CAS_1 0x00000100U
5793 #define FMC_SDCR1_WP 0x00000200U
5795 #define FMC_SDCR1_SDCLK 0x00000C00U
5796 #define FMC_SDCR1_SDCLK_0 0x00000400U
5797 #define FMC_SDCR1_SDCLK_1 0x00000800U
5799 #define FMC_SDCR1_RBURST 0x00001000U
5801 #define FMC_SDCR1_RPIPE 0x00006000U
5802 #define FMC_SDCR1_RPIPE_0 0x00002000U
5803 #define FMC_SDCR1_RPIPE_1 0x00004000U
5805 /****************** Bit definition for FMC_SDCR2 register ******************/
5806 #define FMC_SDCR2_NC 0x00000003U
5807 #define FMC_SDCR2_NC_0 0x00000001U
5808 #define FMC_SDCR2_NC_1 0x00000002U
5810 #define FMC_SDCR2_NR 0x0000000CU
5811 #define FMC_SDCR2_NR_0 0x00000004U
5812 #define FMC_SDCR2_NR_1 0x00000008U
5814 #define FMC_SDCR2_MWID 0x00000030U
5815 #define FMC_SDCR2_MWID_0 0x00000010U
5816 #define FMC_SDCR2_MWID_1 0x00000020U
5818 #define FMC_SDCR2_NB 0x00000040U
5820 #define FMC_SDCR2_CAS 0x00000180U
5821 #define FMC_SDCR2_CAS_0 0x00000080U
5822 #define FMC_SDCR2_CAS_1 0x00000100U
5824 #define FMC_SDCR2_WP 0x00000200U
5826 #define FMC_SDCR2_SDCLK 0x00000C00U
5827 #define FMC_SDCR2_SDCLK_0 0x00000400U
5828 #define FMC_SDCR2_SDCLK_1 0x00000800U
5830 #define FMC_SDCR2_RBURST 0x00001000U
5832 #define FMC_SDCR2_RPIPE 0x00006000U
5833 #define FMC_SDCR2_RPIPE_0 0x00002000U
5834 #define FMC_SDCR2_RPIPE_1 0x00004000U
5836 /****************** Bit definition for FMC_SDTR1 register ******************/
5837 #define FMC_SDTR1_TMRD 0x0000000FU
5838 #define FMC_SDTR1_TMRD_0 0x00000001U
5839 #define FMC_SDTR1_TMRD_1 0x00000002U
5840 #define FMC_SDTR1_TMRD_2 0x00000004U
5841 #define FMC_SDTR1_TMRD_3 0x00000008U
5843 #define FMC_SDTR1_TXSR 0x000000F0U
5844 #define FMC_SDTR1_TXSR_0 0x00000010U
5845 #define FMC_SDTR1_TXSR_1 0x00000020U
5846 #define FMC_SDTR1_TXSR_2 0x00000040U
5847 #define FMC_SDTR1_TXSR_3 0x00000080U
5849 #define FMC_SDTR1_TRAS 0x00000F00U
5850 #define FMC_SDTR1_TRAS_0 0x00000100U
5851 #define FMC_SDTR1_TRAS_1 0x00000200U
5852 #define FMC_SDTR1_TRAS_2 0x00000400U
5853 #define FMC_SDTR1_TRAS_3 0x00000800U
5855 #define FMC_SDTR1_TRC 0x0000F000U
5856 #define FMC_SDTR1_TRC_0 0x00001000U
5857 #define FMC_SDTR1_TRC_1 0x00002000U
5858 #define FMC_SDTR1_TRC_2 0x00004000U
5860 #define FMC_SDTR1_TWR 0x000F0000U
5861 #define FMC_SDTR1_TWR_0 0x00010000U
5862 #define FMC_SDTR1_TWR_1 0x00020000U
5863 #define FMC_SDTR1_TWR_2 0x00040000U
5865 #define FMC_SDTR1_TRP 0x00F00000U
5866 #define FMC_SDTR1_TRP_0 0x00100000U
5867 #define FMC_SDTR1_TRP_1 0x00200000U
5868 #define FMC_SDTR1_TRP_2 0x00400000U
5870 #define FMC_SDTR1_TRCD 0x0F000000U
5871 #define FMC_SDTR1_TRCD_0 0x01000000U
5872 #define FMC_SDTR1_TRCD_1 0x02000000U
5873 #define FMC_SDTR1_TRCD_2 0x04000000U
5875 /****************** Bit definition for FMC_SDTR2 register ******************/
5876 #define FMC_SDTR2_TMRD 0x0000000FU
5877 #define FMC_SDTR2_TMRD_0 0x00000001U
5878 #define FMC_SDTR2_TMRD_1 0x00000002U
5879 #define FMC_SDTR2_TMRD_2 0x00000004U
5880 #define FMC_SDTR2_TMRD_3 0x00000008U
5882 #define FMC_SDTR2_TXSR 0x000000F0U
5883 #define FMC_SDTR2_TXSR_0 0x00000010U
5884 #define FMC_SDTR2_TXSR_1 0x00000020U
5885 #define FMC_SDTR2_TXSR_2 0x00000040U
5886 #define FMC_SDTR2_TXSR_3 0x00000080U
5888 #define FMC_SDTR2_TRAS 0x00000F00U
5889 #define FMC_SDTR2_TRAS_0 0x00000100U
5890 #define FMC_SDTR2_TRAS_1 0x00000200U
5891 #define FMC_SDTR2_TRAS_2 0x00000400U
5892 #define FMC_SDTR2_TRAS_3 0x00000800U
5894 #define FMC_SDTR2_TRC 0x0000F000U
5895 #define FMC_SDTR2_TRC_0 0x00001000U
5896 #define FMC_SDTR2_TRC_1 0x00002000U
5897 #define FMC_SDTR2_TRC_2 0x00004000U
5899 #define FMC_SDTR2_TWR 0x000F0000U
5900 #define FMC_SDTR2_TWR_0 0x00010000U
5901 #define FMC_SDTR2_TWR_1 0x00020000U
5902 #define FMC_SDTR2_TWR_2 0x00040000U
5904 #define FMC_SDTR2_TRP 0x00F00000U
5905 #define FMC_SDTR2_TRP_0 0x00100000U
5906 #define FMC_SDTR2_TRP_1 0x00200000U
5907 #define FMC_SDTR2_TRP_2 0x00400000U
5909 #define FMC_SDTR2_TRCD 0x0F000000U
5910 #define FMC_SDTR2_TRCD_0 0x01000000U
5911 #define FMC_SDTR2_TRCD_1 0x02000000U
5912 #define FMC_SDTR2_TRCD_2 0x04000000U
5914 /****************** Bit definition for FMC_SDCMR register ******************/
5915 #define FMC_SDCMR_MODE 0x00000007U
5916 #define FMC_SDCMR_MODE_0 0x00000001U
5917 #define FMC_SDCMR_MODE_1 0x00000002U
5918 #define FMC_SDCMR_MODE_2 0x00000004U
5920 #define FMC_SDCMR_CTB2 0x00000008U
5922 #define FMC_SDCMR_CTB1 0x00000010U
5924 #define FMC_SDCMR_NRFS 0x000001E0U
5925 #define FMC_SDCMR_NRFS_0 0x00000020U
5926 #define FMC_SDCMR_NRFS_1 0x00000040U
5927 #define FMC_SDCMR_NRFS_2 0x00000080U
5928 #define FMC_SDCMR_NRFS_3 0x00000100U
5930 #define FMC_SDCMR_MRD 0x003FFE00U
5932 /****************** Bit definition for FMC_SDRTR register ******************/
5933 #define FMC_SDRTR_CRE 0x00000001U
5935 #define FMC_SDRTR_COUNT 0x00003FFEU
5937 #define FMC_SDRTR_REIE 0x00004000U
5939 /****************** Bit definition for FMC_SDSR register ******************/
5940 #define FMC_SDSR_RE 0x00000001U
5942 #define FMC_SDSR_MODES1 0x00000006U
5943 #define FMC_SDSR_MODES1_0 0x00000002U
5944 #define FMC_SDSR_MODES1_1 0x00000004U
5946 #define FMC_SDSR_MODES2 0x00000018U
5947 #define FMC_SDSR_MODES2_0 0x00000008U
5948 #define FMC_SDSR_MODES2_1 0x00000010U
5949 #define FMC_SDSR_BUSY 0x00000020U
5951 /******************************************************************************/
5952 /* */
5953 /* General Purpose I/O */
5954 /* */
5955 /******************************************************************************/
5956 /****************** Bits definition for GPIO_MODER register *****************/
5957 #define GPIO_MODER_MODER0 0x00000003U
5958 #define GPIO_MODER_MODER0_0 0x00000001U
5959 #define GPIO_MODER_MODER0_1 0x00000002U
5960 
5961 #define GPIO_MODER_MODER1 0x0000000CU
5962 #define GPIO_MODER_MODER1_0 0x00000004U
5963 #define GPIO_MODER_MODER1_1 0x00000008U
5964 
5965 #define GPIO_MODER_MODER2 0x00000030U
5966 #define GPIO_MODER_MODER2_0 0x00000010U
5967 #define GPIO_MODER_MODER2_1 0x00000020U
5968 
5969 #define GPIO_MODER_MODER3 0x000000C0U
5970 #define GPIO_MODER_MODER3_0 0x00000040U
5971 #define GPIO_MODER_MODER3_1 0x00000080U
5972 
5973 #define GPIO_MODER_MODER4 0x00000300U
5974 #define GPIO_MODER_MODER4_0 0x00000100U
5975 #define GPIO_MODER_MODER4_1 0x00000200U
5976 
5977 #define GPIO_MODER_MODER5 0x00000C00U
5978 #define GPIO_MODER_MODER5_0 0x00000400U
5979 #define GPIO_MODER_MODER5_1 0x00000800U
5980 
5981 #define GPIO_MODER_MODER6 0x00003000U
5982 #define GPIO_MODER_MODER6_0 0x00001000U
5983 #define GPIO_MODER_MODER6_1 0x00002000U
5984 
5985 #define GPIO_MODER_MODER7 0x0000C000U
5986 #define GPIO_MODER_MODER7_0 0x00004000U
5987 #define GPIO_MODER_MODER7_1 0x00008000U
5988 
5989 #define GPIO_MODER_MODER8 0x00030000U
5990 #define GPIO_MODER_MODER8_0 0x00010000U
5991 #define GPIO_MODER_MODER8_1 0x00020000U
5992 
5993 #define GPIO_MODER_MODER9 0x000C0000U
5994 #define GPIO_MODER_MODER9_0 0x00040000U
5995 #define GPIO_MODER_MODER9_1 0x00080000U
5996 
5997 #define GPIO_MODER_MODER10 0x00300000U
5998 #define GPIO_MODER_MODER10_0 0x00100000U
5999 #define GPIO_MODER_MODER10_1 0x00200000U
6000 
6001 #define GPIO_MODER_MODER11 0x00C00000U
6002 #define GPIO_MODER_MODER11_0 0x00400000U
6003 #define GPIO_MODER_MODER11_1 0x00800000U
6004 
6005 #define GPIO_MODER_MODER12 0x03000000U
6006 #define GPIO_MODER_MODER12_0 0x01000000U
6007 #define GPIO_MODER_MODER12_1 0x02000000U
6008 
6009 #define GPIO_MODER_MODER13 0x0C000000U
6010 #define GPIO_MODER_MODER13_0 0x04000000U
6011 #define GPIO_MODER_MODER13_1 0x08000000U
6012 
6013 #define GPIO_MODER_MODER14 0x30000000U
6014 #define GPIO_MODER_MODER14_0 0x10000000U
6015 #define GPIO_MODER_MODER14_1 0x20000000U
6016 
6017 #define GPIO_MODER_MODER15 0xC0000000U
6018 #define GPIO_MODER_MODER15_0 0x40000000U
6019 #define GPIO_MODER_MODER15_1 0x80000000U
6020 
6021 /****************** Bits definition for GPIO_OTYPER register ****************/
6022 #define GPIO_OTYPER_OT_0 0x00000001U
6023 #define GPIO_OTYPER_OT_1 0x00000002U
6024 #define GPIO_OTYPER_OT_2 0x00000004U
6025 #define GPIO_OTYPER_OT_3 0x00000008U
6026 #define GPIO_OTYPER_OT_4 0x00000010U
6027 #define GPIO_OTYPER_OT_5 0x00000020U
6028 #define GPIO_OTYPER_OT_6 0x00000040U
6029 #define GPIO_OTYPER_OT_7 0x00000080U
6030 #define GPIO_OTYPER_OT_8 0x00000100U
6031 #define GPIO_OTYPER_OT_9 0x00000200U
6032 #define GPIO_OTYPER_OT_10 0x00000400U
6033 #define GPIO_OTYPER_OT_11 0x00000800U
6034 #define GPIO_OTYPER_OT_12 0x00001000U
6035 #define GPIO_OTYPER_OT_13 0x00002000U
6036 #define GPIO_OTYPER_OT_14 0x00004000U
6037 #define GPIO_OTYPER_OT_15 0x00008000U
6038 
6039 /****************** Bits definition for GPIO_OSPEEDR register ***************/
6040 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
6041 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
6042 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
6043 
6044 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
6045 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
6046 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
6047 
6048 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
6049 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
6050 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
6051 
6052 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
6053 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
6054 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
6055 
6056 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
6057 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
6058 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
6059 
6060 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
6061 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
6062 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
6063 
6064 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
6065 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
6066 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
6067 
6068 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
6069 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
6070 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
6071 
6072 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
6073 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
6074 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
6075 
6076 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
6077 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
6078 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
6079 
6080 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
6081 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
6082 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
6083 
6084 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
6085 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
6086 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
6087 
6088 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
6089 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
6090 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
6091 
6092 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
6093 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
6094 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
6095 
6096 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
6097 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
6098 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
6099 
6100 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
6101 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
6102 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
6103 
6104 /****************** Bits definition for GPIO_PUPDR register *****************/
6105 #define GPIO_PUPDR_PUPDR0 0x00000003U
6106 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
6107 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
6108 
6109 #define GPIO_PUPDR_PUPDR1 0x0000000CU
6110 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
6111 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
6112 
6113 #define GPIO_PUPDR_PUPDR2 0x00000030U
6114 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
6115 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
6116 
6117 #define GPIO_PUPDR_PUPDR3 0x000000C0U
6118 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
6119 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
6120 
6121 #define GPIO_PUPDR_PUPDR4 0x00000300U
6122 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
6123 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
6124 
6125 #define GPIO_PUPDR_PUPDR5 0x00000C00U
6126 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
6127 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
6128 
6129 #define GPIO_PUPDR_PUPDR6 0x00003000U
6130 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
6131 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
6132 
6133 #define GPIO_PUPDR_PUPDR7 0x0000C000U
6134 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
6135 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
6136 
6137 #define GPIO_PUPDR_PUPDR8 0x00030000U
6138 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
6139 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
6140 
6141 #define GPIO_PUPDR_PUPDR9 0x000C0000U
6142 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
6143 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
6144 
6145 #define GPIO_PUPDR_PUPDR10 0x00300000U
6146 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
6147 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
6148 
6149 #define GPIO_PUPDR_PUPDR11 0x00C00000U
6150 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
6151 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
6152 
6153 #define GPIO_PUPDR_PUPDR12 0x03000000U
6154 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
6155 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
6156 
6157 #define GPIO_PUPDR_PUPDR13 0x0C000000U
6158 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
6159 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
6160 
6161 #define GPIO_PUPDR_PUPDR14 0x30000000U
6162 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
6163 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
6164 
6165 #define GPIO_PUPDR_PUPDR15 0xC0000000U
6166 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
6167 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
6168 
6169 /****************** Bits definition for GPIO_IDR register *******************/
6170 #define GPIO_IDR_IDR_0 0x00000001U
6171 #define GPIO_IDR_IDR_1 0x00000002U
6172 #define GPIO_IDR_IDR_2 0x00000004U
6173 #define GPIO_IDR_IDR_3 0x00000008U
6174 #define GPIO_IDR_IDR_4 0x00000010U
6175 #define GPIO_IDR_IDR_5 0x00000020U
6176 #define GPIO_IDR_IDR_6 0x00000040U
6177 #define GPIO_IDR_IDR_7 0x00000080U
6178 #define GPIO_IDR_IDR_8 0x00000100U
6179 #define GPIO_IDR_IDR_9 0x00000200U
6180 #define GPIO_IDR_IDR_10 0x00000400U
6181 #define GPIO_IDR_IDR_11 0x00000800U
6182 #define GPIO_IDR_IDR_12 0x00001000U
6183 #define GPIO_IDR_IDR_13 0x00002000U
6184 #define GPIO_IDR_IDR_14 0x00004000U
6185 #define GPIO_IDR_IDR_15 0x00008000U
6186 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
6187 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
6188 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
6189 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
6190 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
6191 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
6192 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
6193 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
6194 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
6195 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
6196 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
6197 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
6198 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
6199 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
6200 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
6201 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
6202 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
6203 
6204 /****************** Bits definition for GPIO_ODR register *******************/
6205 #define GPIO_ODR_ODR_0 0x00000001U
6206 #define GPIO_ODR_ODR_1 0x00000002U
6207 #define GPIO_ODR_ODR_2 0x00000004U
6208 #define GPIO_ODR_ODR_3 0x00000008U
6209 #define GPIO_ODR_ODR_4 0x00000010U
6210 #define GPIO_ODR_ODR_5 0x00000020U
6211 #define GPIO_ODR_ODR_6 0x00000040U
6212 #define GPIO_ODR_ODR_7 0x00000080U
6213 #define GPIO_ODR_ODR_8 0x00000100U
6214 #define GPIO_ODR_ODR_9 0x00000200U
6215 #define GPIO_ODR_ODR_10 0x00000400U
6216 #define GPIO_ODR_ODR_11 0x00000800U
6217 #define GPIO_ODR_ODR_12 0x00001000U
6218 #define GPIO_ODR_ODR_13 0x00002000U
6219 #define GPIO_ODR_ODR_14 0x00004000U
6220 #define GPIO_ODR_ODR_15 0x00008000U
6221 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6222 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
6223 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
6224 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
6225 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
6226 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
6227 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
6228 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
6229 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
6230 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
6231 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
6232 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
6233 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
6234 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
6235 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
6236 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
6237 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
6238 
6239 /****************** Bits definition for GPIO_BSRR register ******************/
6240 #define GPIO_BSRR_BS_0 0x00000001U
6241 #define GPIO_BSRR_BS_1 0x00000002U
6242 #define GPIO_BSRR_BS_2 0x00000004U
6243 #define GPIO_BSRR_BS_3 0x00000008U
6244 #define GPIO_BSRR_BS_4 0x00000010U
6245 #define GPIO_BSRR_BS_5 0x00000020U
6246 #define GPIO_BSRR_BS_6 0x00000040U
6247 #define GPIO_BSRR_BS_7 0x00000080U
6248 #define GPIO_BSRR_BS_8 0x00000100U
6249 #define GPIO_BSRR_BS_9 0x00000200U
6250 #define GPIO_BSRR_BS_10 0x00000400U
6251 #define GPIO_BSRR_BS_11 0x00000800U
6252 #define GPIO_BSRR_BS_12 0x00001000U
6253 #define GPIO_BSRR_BS_13 0x00002000U
6254 #define GPIO_BSRR_BS_14 0x00004000U
6255 #define GPIO_BSRR_BS_15 0x00008000U
6256 #define GPIO_BSRR_BR_0 0x00010000U
6257 #define GPIO_BSRR_BR_1 0x00020000U
6258 #define GPIO_BSRR_BR_2 0x00040000U
6259 #define GPIO_BSRR_BR_3 0x00080000U
6260 #define GPIO_BSRR_BR_4 0x00100000U
6261 #define GPIO_BSRR_BR_5 0x00200000U
6262 #define GPIO_BSRR_BR_6 0x00400000U
6263 #define GPIO_BSRR_BR_7 0x00800000U
6264 #define GPIO_BSRR_BR_8 0x01000000U
6265 #define GPIO_BSRR_BR_9 0x02000000U
6266 #define GPIO_BSRR_BR_10 0x04000000U
6267 #define GPIO_BSRR_BR_11 0x08000000U
6268 #define GPIO_BSRR_BR_12 0x10000000U
6269 #define GPIO_BSRR_BR_13 0x20000000U
6270 #define GPIO_BSRR_BR_14 0x40000000U
6271 #define GPIO_BSRR_BR_15 0x80000000U
6272 
6273 /****************** Bit definition for GPIO_LCKR register *********************/
6274 #define GPIO_LCKR_LCK0 0x00000001U
6275 #define GPIO_LCKR_LCK1 0x00000002U
6276 #define GPIO_LCKR_LCK2 0x00000004U
6277 #define GPIO_LCKR_LCK3 0x00000008U
6278 #define GPIO_LCKR_LCK4 0x00000010U
6279 #define GPIO_LCKR_LCK5 0x00000020U
6280 #define GPIO_LCKR_LCK6 0x00000040U
6281 #define GPIO_LCKR_LCK7 0x00000080U
6282 #define GPIO_LCKR_LCK8 0x00000100U
6283 #define GPIO_LCKR_LCK9 0x00000200U
6284 #define GPIO_LCKR_LCK10 0x00000400U
6285 #define GPIO_LCKR_LCK11 0x00000800U
6286 #define GPIO_LCKR_LCK12 0x00001000U
6287 #define GPIO_LCKR_LCK13 0x00002000U
6288 #define GPIO_LCKR_LCK14 0x00004000U
6289 #define GPIO_LCKR_LCK15 0x00008000U
6290 #define GPIO_LCKR_LCKK 0x00010000U
6291 
6292 /******************************************************************************/
6293 /* */
6294 /* HASH */
6295 /* */
6296 /******************************************************************************/
6297 /****************** Bits definition for HASH_CR register ********************/
6298 #define HASH_CR_INIT 0x00000004U
6299 #define HASH_CR_DMAE 0x00000008U
6300 #define HASH_CR_DATATYPE 0x00000030U
6301 #define HASH_CR_DATATYPE_0 0x00000010U
6302 #define HASH_CR_DATATYPE_1 0x00000020U
6303 #define HASH_CR_MODE 0x00000040U
6304 #define HASH_CR_ALGO 0x00040080U
6305 #define HASH_CR_ALGO_0 0x00000080U
6306 #define HASH_CR_ALGO_1 0x00040000U
6307 #define HASH_CR_NBW 0x00000F00U
6308 #define HASH_CR_NBW_0 0x00000100U
6309 #define HASH_CR_NBW_1 0x00000200U
6310 #define HASH_CR_NBW_2 0x00000400U
6311 #define HASH_CR_NBW_3 0x00000800U
6312 #define HASH_CR_DINNE 0x00001000U
6313 #define HASH_CR_MDMAT 0x00002000U
6314 #define HASH_CR_LKEY 0x00010000U
6315 
6316 /****************** Bits definition for HASH_STR register *******************/
6317 #define HASH_STR_NBLW 0x0000001FU
6318 #define HASH_STR_NBLW_0 0x00000001U
6319 #define HASH_STR_NBLW_1 0x00000002U
6320 #define HASH_STR_NBLW_2 0x00000004U
6321 #define HASH_STR_NBLW_3 0x00000008U
6322 #define HASH_STR_NBLW_4 0x00000010U
6323 #define HASH_STR_DCAL 0x00000100U
6324 /* Aliases for HASH_STR register */
6325 #define HASH_STR_NBW HASH_STR_NBLW
6326 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
6327 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
6328 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
6329 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
6330 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
6331 
6332 /****************** Bits definition for HASH_IMR register *******************/
6333 #define HASH_IMR_DINIE 0x00000001U
6334 #define HASH_IMR_DCIE 0x00000002U
6335 /* Aliases for HASH_IMR register */
6336 #define HASH_IMR_DINIM HASH_IMR_DINIE
6337 #define HASH_IMR_DCIM HASH_IMR_DCIE
6338 
6339 /****************** Bits definition for HASH_SR register ********************/
6340 #define HASH_SR_DINIS 0x00000001U
6341 #define HASH_SR_DCIS 0x00000002U
6342 #define HASH_SR_DMAS 0x00000004U
6343 #define HASH_SR_BUSY 0x00000008U
6344 
6345 /******************************************************************************/
6346 /* */
6347 /* Inter-integrated Circuit Interface */
6348 /* */
6349 /******************************************************************************/
6350 /******************* Bit definition for I2C_CR1 register ********************/
6351 #define I2C_CR1_PE 0x00000001U
6352 #define I2C_CR1_SMBUS 0x00000002U
6353 #define I2C_CR1_SMBTYPE 0x00000008U
6354 #define I2C_CR1_ENARP 0x00000010U
6355 #define I2C_CR1_ENPEC 0x00000020U
6356 #define I2C_CR1_ENGC 0x00000040U
6357 #define I2C_CR1_NOSTRETCH 0x00000080U
6358 #define I2C_CR1_START 0x00000100U
6359 #define I2C_CR1_STOP 0x00000200U
6360 #define I2C_CR1_ACK 0x00000400U
6361 #define I2C_CR1_POS 0x00000800U
6362 #define I2C_CR1_PEC 0x00001000U
6363 #define I2C_CR1_ALERT 0x00002000U
6364 #define I2C_CR1_SWRST 0x00008000U
6366 /******************* Bit definition for I2C_CR2 register ********************/
6367 #define I2C_CR2_FREQ 0x0000003FU
6368 #define I2C_CR2_FREQ_0 0x00000001U
6369 #define I2C_CR2_FREQ_1 0x00000002U
6370 #define I2C_CR2_FREQ_2 0x00000004U
6371 #define I2C_CR2_FREQ_3 0x00000008U
6372 #define I2C_CR2_FREQ_4 0x00000010U
6373 #define I2C_CR2_FREQ_5 0x00000020U
6375 #define I2C_CR2_ITERREN 0x00000100U
6376 #define I2C_CR2_ITEVTEN 0x00000200U
6377 #define I2C_CR2_ITBUFEN 0x00000400U
6378 #define I2C_CR2_DMAEN 0x00000800U
6379 #define I2C_CR2_LAST 0x00001000U
6381 /******************* Bit definition for I2C_OAR1 register *******************/
6382 #define I2C_OAR1_ADD1_7 0x000000FEU
6383 #define I2C_OAR1_ADD8_9 0x00000300U
6385 #define I2C_OAR1_ADD0 0x00000001U
6386 #define I2C_OAR1_ADD1 0x00000002U
6387 #define I2C_OAR1_ADD2 0x00000004U
6388 #define I2C_OAR1_ADD3 0x00000008U
6389 #define I2C_OAR1_ADD4 0x00000010U
6390 #define I2C_OAR1_ADD5 0x00000020U
6391 #define I2C_OAR1_ADD6 0x00000040U
6392 #define I2C_OAR1_ADD7 0x00000080U
6393 #define I2C_OAR1_ADD8 0x00000100U
6394 #define I2C_OAR1_ADD9 0x00000200U
6396 #define I2C_OAR1_ADDMODE 0x00008000U
6398 /******************* Bit definition for I2C_OAR2 register *******************/
6399 #define I2C_OAR2_ENDUAL 0x00000001U
6400 #define I2C_OAR2_ADD2 0x000000FEU
6402 /******************** Bit definition for I2C_DR register ********************/
6403 #define I2C_DR_DR 0x000000FFU
6405 /******************* Bit definition for I2C_SR1 register ********************/
6406 #define I2C_SR1_SB 0x00000001U
6407 #define I2C_SR1_ADDR 0x00000002U
6408 #define I2C_SR1_BTF 0x00000004U
6409 #define I2C_SR1_ADD10 0x00000008U
6410 #define I2C_SR1_STOPF 0x00000010U
6411 #define I2C_SR1_RXNE 0x00000040U
6412 #define I2C_SR1_TXE 0x00000080U
6413 #define I2C_SR1_BERR 0x00000100U
6414 #define I2C_SR1_ARLO 0x00000200U
6415 #define I2C_SR1_AF 0x00000400U
6416 #define I2C_SR1_OVR 0x00000800U
6417 #define I2C_SR1_PECERR 0x00001000U
6418 #define I2C_SR1_TIMEOUT 0x00004000U
6419 #define I2C_SR1_SMBALERT 0x00008000U
6421 /******************* Bit definition for I2C_SR2 register ********************/
6422 #define I2C_SR2_MSL 0x00000001U
6423 #define I2C_SR2_BUSY 0x00000002U
6424 #define I2C_SR2_TRA 0x00000004U
6425 #define I2C_SR2_GENCALL 0x00000010U
6426 #define I2C_SR2_SMBDEFAULT 0x00000020U
6427 #define I2C_SR2_SMBHOST 0x00000040U
6428 #define I2C_SR2_DUALF 0x00000080U
6429 #define I2C_SR2_PEC 0x0000FF00U
6431 /******************* Bit definition for I2C_CCR register ********************/
6432 #define I2C_CCR_CCR 0x00000FFFU
6433 #define I2C_CCR_DUTY 0x00004000U
6434 #define I2C_CCR_FS 0x00008000U
6436 /****************** Bit definition for I2C_TRISE register *******************/
6437 #define I2C_TRISE_TRISE 0x0000003FU
6439 /****************** Bit definition for I2C_FLTR register *******************/
6440 #define I2C_FLTR_DNF 0x0000000FU
6441 #define I2C_FLTR_ANOFF 0x00000010U
6443 /******************************************************************************/
6444 /* */
6445 /* Independent WATCHDOG */
6446 /* */
6447 /******************************************************************************/
6448 /******************* Bit definition for IWDG_KR register ********************/
6449 #define IWDG_KR_KEY 0xFFFFU
6451 /******************* Bit definition for IWDG_PR register ********************/
6452 #define IWDG_PR_PR 0x07U
6453 #define IWDG_PR_PR_0 0x01U
6454 #define IWDG_PR_PR_1 0x02U
6455 #define IWDG_PR_PR_2 0x04U
6457 /******************* Bit definition for IWDG_RLR register *******************/
6458 #define IWDG_RLR_RL 0x0FFFU
6460 /******************* Bit definition for IWDG_SR register ********************/
6461 #define IWDG_SR_PVU 0x01U
6462 #define IWDG_SR_RVU 0x02U
6465 /******************************************************************************/
6466 /* */
6467 /* LCD-TFT Display Controller (LTDC) */
6468 /* */
6469 /******************************************************************************/
6470 
6471 /******************** Bit definition for LTDC_SSCR register *****************/
6472 
6473 #define LTDC_SSCR_VSH 0x000007FFU
6474 #define LTDC_SSCR_HSW 0x0FFF0000U
6476 /******************** Bit definition for LTDC_BPCR register *****************/
6477 
6478 #define LTDC_BPCR_AVBP 0x000007FFU
6479 #define LTDC_BPCR_AHBP 0x0FFF0000U
6481 /******************** Bit definition for LTDC_AWCR register *****************/
6482 
6483 #define LTDC_AWCR_AAH 0x000007FFU
6484 #define LTDC_AWCR_AAW 0x0FFF0000U
6486 /******************** Bit definition for LTDC_TWCR register *****************/
6487 
6488 #define LTDC_TWCR_TOTALH 0x000007FFU
6489 #define LTDC_TWCR_TOTALW 0x0FFF0000U
6491 /******************** Bit definition for LTDC_GCR register ******************/
6492 
6493 #define LTDC_GCR_LTDCEN 0x00000001U
6494 #define LTDC_GCR_DBW 0x00000070U
6495 #define LTDC_GCR_DGW 0x00000700U
6496 #define LTDC_GCR_DRW 0x00007000U
6497 #define LTDC_GCR_DEN 0x00010000U
6498 #define LTDC_GCR_PCPOL 0x10000000U
6499 #define LTDC_GCR_DEPOL 0x20000000U
6500 #define LTDC_GCR_VSPOL 0x40000000U
6501 #define LTDC_GCR_HSPOL 0x80000000U
6503 /* Legacy defines */
6504 #define LTDC_GCR_DTEN LTDC_GCR_DEN
6505 
6506 /******************** Bit definition for LTDC_SRCR register *****************/
6507 
6508 #define LTDC_SRCR_IMR 0x00000001U
6509 #define LTDC_SRCR_VBR 0x00000002U
6511 /******************** Bit definition for LTDC_BCCR register *****************/
6512 
6513 #define LTDC_BCCR_BCBLUE 0x000000FFU
6514 #define LTDC_BCCR_BCGREEN 0x0000FF00U
6515 #define LTDC_BCCR_BCRED 0x00FF0000U
6517 /******************** Bit definition for LTDC_IER register ******************/
6518 
6519 #define LTDC_IER_LIE 0x00000001U
6520 #define LTDC_IER_FUIE 0x00000002U
6521 #define LTDC_IER_TERRIE 0x00000004U
6522 #define LTDC_IER_RRIE 0x00000008U
6524 /******************** Bit definition for LTDC_ISR register ******************/
6525 
6526 #define LTDC_ISR_LIF 0x00000001U
6527 #define LTDC_ISR_FUIF 0x00000002U
6528 #define LTDC_ISR_TERRIF 0x00000004U
6529 #define LTDC_ISR_RRIF 0x00000008U
6531 /******************** Bit definition for LTDC_ICR register ******************/
6532 
6533 #define LTDC_ICR_CLIF 0x00000001U
6534 #define LTDC_ICR_CFUIF 0x00000002U
6535 #define LTDC_ICR_CTERRIF 0x00000004U
6536 #define LTDC_ICR_CRRIF 0x00000008U
6538 /******************** Bit definition for LTDC_LIPCR register ****************/
6539 
6540 #define LTDC_LIPCR_LIPOS 0x000007FFU
6542 /******************** Bit definition for LTDC_CPSR register *****************/
6543 
6544 #define LTDC_CPSR_CYPOS 0x0000FFFFU
6545 #define LTDC_CPSR_CXPOS 0xFFFF0000U
6547 /******************** Bit definition for LTDC_CDSR register *****************/
6548 
6549 #define LTDC_CDSR_VDES 0x00000001U
6550 #define LTDC_CDSR_HDES 0x00000002U
6551 #define LTDC_CDSR_VSYNCS 0x00000004U
6552 #define LTDC_CDSR_HSYNCS 0x00000008U
6554 /******************** Bit definition for LTDC_LxCR register *****************/
6555 
6556 #define LTDC_LxCR_LEN 0x00000001U
6557 #define LTDC_LxCR_COLKEN 0x00000002U
6558 #define LTDC_LxCR_CLUTEN 0x00000010U
6560 /******************** Bit definition for LTDC_LxWHPCR register **************/
6561 
6562 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU
6563 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U
6565 /******************** Bit definition for LTDC_LxWVPCR register **************/
6566 
6567 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU
6568 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U
6570 /******************** Bit definition for LTDC_LxCKCR register ***************/
6571 
6572 #define LTDC_LxCKCR_CKBLUE 0x000000FFU
6573 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U
6574 #define LTDC_LxCKCR_CKRED 0x00FF0000U
6576 /******************** Bit definition for LTDC_LxPFCR register ***************/
6577 
6578 #define LTDC_LxPFCR_PF 0x00000007U
6580 /******************** Bit definition for LTDC_LxCACR register ***************/
6581 
6582 #define LTDC_LxCACR_CONSTA 0x000000FFU
6584 /******************** Bit definition for LTDC_LxDCCR register ***************/
6585 
6586 #define LTDC_LxDCCR_DCBLUE 0x000000FFU
6587 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U
6588 #define LTDC_LxDCCR_DCRED 0x00FF0000U
6589 #define LTDC_LxDCCR_DCALPHA 0xFF000000U
6591 /******************** Bit definition for LTDC_LxBFCR register ***************/
6592 
6593 #define LTDC_LxBFCR_BF2 0x00000007U
6594 #define LTDC_LxBFCR_BF1 0x00000700U
6596 /******************** Bit definition for LTDC_LxCFBAR register **************/
6597 
6598 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU
6600 /******************** Bit definition for LTDC_LxCFBLR register **************/
6601 
6602 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU
6603 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U
6605 /******************** Bit definition for LTDC_LxCFBLNR register *************/
6606 
6607 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU
6609 /******************** Bit definition for LTDC_LxCLUTWR register *************/
6610 
6611 #define LTDC_LxCLUTWR_BLUE 0x000000FFU
6612 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U
6613 #define LTDC_LxCLUTWR_RED 0x00FF0000U
6614 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U
6617 /******************************************************************************/
6618 /* */
6619 /* Power Control */
6620 /* */
6621 /******************************************************************************/
6622 /******************** Bit definition for PWR_CR register ********************/
6623 #define PWR_CR_LPDS 0x00000001U
6624 #define PWR_CR_PDDS 0x00000002U
6625 #define PWR_CR_CWUF 0x00000004U
6626 #define PWR_CR_CSBF 0x00000008U
6627 #define PWR_CR_PVDE 0x00000010U
6629 #define PWR_CR_PLS 0x000000E0U
6630 #define PWR_CR_PLS_0 0x00000020U
6631 #define PWR_CR_PLS_1 0x00000040U
6632 #define PWR_CR_PLS_2 0x00000080U
6635 #define PWR_CR_PLS_LEV0 0x00000000U
6636 #define PWR_CR_PLS_LEV1 0x00000020U
6637 #define PWR_CR_PLS_LEV2 0x00000040U
6638 #define PWR_CR_PLS_LEV3 0x00000060U
6639 #define PWR_CR_PLS_LEV4 0x00000080U
6640 #define PWR_CR_PLS_LEV5 0x000000A0U
6641 #define PWR_CR_PLS_LEV6 0x000000C0U
6642 #define PWR_CR_PLS_LEV7 0x000000E0U
6643 #define PWR_CR_DBP 0x00000100U
6644 #define PWR_CR_FPDS 0x00000200U
6645 #define PWR_CR_LPLVDS 0x00000400U
6646 #define PWR_CR_MRLVDS 0x00000800U
6647 #define PWR_CR_ADCDC1 0x00002000U
6648 #define PWR_CR_VOS 0x0000C000U
6649 #define PWR_CR_VOS_0 0x00004000U
6650 #define PWR_CR_VOS_1 0x00008000U
6651 #define PWR_CR_ODEN 0x00010000U
6652 #define PWR_CR_ODSWEN 0x00020000U
6653 #define PWR_CR_UDEN 0x000C0000U
6654 #define PWR_CR_UDEN_0 0x00040000U
6655 #define PWR_CR_UDEN_1 0x00080000U
6657 /* Legacy define */
6658 #define PWR_CR_PMODE PWR_CR_VOS
6659 #define PWR_CR_LPUDS PWR_CR_LPLVDS
6660 #define PWR_CR_MRUDS PWR_CR_MRLVDS
6662 /******************* Bit definition for PWR_CSR register ********************/
6663 #define PWR_CSR_WUF 0x00000001U
6664 #define PWR_CSR_SBF 0x00000002U
6665 #define PWR_CSR_PVDO 0x00000004U
6666 #define PWR_CSR_BRR 0x00000008U
6667 #define PWR_CSR_WUPP 0x00000080U
6668 #define PWR_CSR_EWUP 0x00000100U
6669 #define PWR_CSR_BRE 0x00000200U
6670 #define PWR_CSR_VOSRDY 0x00004000U
6671 #define PWR_CSR_ODRDY 0x00010000U
6672 #define PWR_CSR_ODSWRDY 0x00020000U
6673 #define PWR_CSR_UDSWRDY 0x000C0000U
6675 /* Legacy define */
6676 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
6677 
6678 /******************************************************************************/
6679 /* */
6680 /* QUADSPI */
6681 /* */
6682 /******************************************************************************/
6683 /***************** Bit definition for QUADSPI_CR register *******************/
6684 #define QUADSPI_CR_EN 0x00000001U
6685 #define QUADSPI_CR_ABORT 0x00000002U
6686 #define QUADSPI_CR_DMAEN 0x00000004U
6687 #define QUADSPI_CR_TCEN 0x00000008U
6688 #define QUADSPI_CR_SSHIFT 0x00000010U
6689 #define QUADSPI_CR_DFM 0x00000040U
6690 #define QUADSPI_CR_FSEL 0x00000080U
6691 #define QUADSPI_CR_FTHRES 0x00001F00U
6692 #define QUADSPI_CR_FTHRES_0 0x00000100U
6693 #define QUADSPI_CR_FTHRES_1 0x00000200U
6694 #define QUADSPI_CR_FTHRES_2 0x00000400U
6695 #define QUADSPI_CR_FTHRES_3 0x00000800U
6696 #define QUADSPI_CR_FTHRES_4 0x00001000U
6697 #define QUADSPI_CR_TEIE 0x00010000U
6698 #define QUADSPI_CR_TCIE 0x00020000U
6699 #define QUADSPI_CR_FTIE 0x00040000U
6700 #define QUADSPI_CR_SMIE 0x00080000U
6701 #define QUADSPI_CR_TOIE 0x00100000U
6702 #define QUADSPI_CR_APMS 0x00400000U
6703 #define QUADSPI_CR_PMM 0x00800000U
6704 #define QUADSPI_CR_PRESCALER 0xFF000000U
6705 #define QUADSPI_CR_PRESCALER_0 0x01000000U
6706 #define QUADSPI_CR_PRESCALER_1 0x02000000U
6707 #define QUADSPI_CR_PRESCALER_2 0x04000000U
6708 #define QUADSPI_CR_PRESCALER_3 0x08000000U
6709 #define QUADSPI_CR_PRESCALER_4 0x10000000U
6710 #define QUADSPI_CR_PRESCALER_5 0x20000000U
6711 #define QUADSPI_CR_PRESCALER_6 0x40000000U
6712 #define QUADSPI_CR_PRESCALER_7 0x80000000U
6714 /***************** Bit definition for QUADSPI_DCR register ******************/
6715 #define QUADSPI_DCR_CKMODE 0x00000001U
6716 #define QUADSPI_DCR_CSHT 0x00000700U
6717 #define QUADSPI_DCR_CSHT_0 0x00000100U
6718 #define QUADSPI_DCR_CSHT_1 0x00000200U
6719 #define QUADSPI_DCR_CSHT_2 0x00000400U
6720 #define QUADSPI_DCR_FSIZE 0x001F0000U
6721 #define QUADSPI_DCR_FSIZE_0 0x00010000U
6722 #define QUADSPI_DCR_FSIZE_1 0x00020000U
6723 #define QUADSPI_DCR_FSIZE_2 0x00040000U
6724 #define QUADSPI_DCR_FSIZE_3 0x00080000U
6725 #define QUADSPI_DCR_FSIZE_4 0x00100000U
6727 /****************** Bit definition for QUADSPI_SR register *******************/
6728 #define QUADSPI_SR_TEF 0x00000001U
6729 #define QUADSPI_SR_TCF 0x00000002U
6730 #define QUADSPI_SR_FTF 0x00000004U
6731 #define QUADSPI_SR_SMF 0x00000008U
6732 #define QUADSPI_SR_TOF 0x00000010U
6733 #define QUADSPI_SR_BUSY 0x00000020U
6734 #define QUADSPI_SR_FLEVEL 0x00003F00U
6735 #define QUADSPI_SR_FLEVEL_0 0x00000100U
6736 #define QUADSPI_SR_FLEVEL_1 0x00000200U
6737 #define QUADSPI_SR_FLEVEL_2 0x00000400U
6738 #define QUADSPI_SR_FLEVEL_3 0x00000800U
6739 #define QUADSPI_SR_FLEVEL_4 0x00001000U
6740 #define QUADSPI_SR_FLEVEL_5 0x00002000U
6742 /****************** Bit definition for QUADSPI_FCR register ******************/
6743 #define QUADSPI_FCR_CTEF 0x00000001U
6744 #define QUADSPI_FCR_CTCF 0x00000002U
6745 #define QUADSPI_FCR_CSMF 0x00000008U
6746 #define QUADSPI_FCR_CTOF 0x00000010U
6748 /****************** Bit definition for QUADSPI_DLR register ******************/
6749 #define QUADSPI_DLR_DL 0xFFFFFFFFU
6751 /****************** Bit definition for QUADSPI_CCR register ******************/
6752 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU
6753 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U
6754 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U
6755 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U
6756 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U
6757 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U
6758 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U
6759 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U
6760 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U
6761 #define QUADSPI_CCR_IMODE 0x00000300U
6762 #define QUADSPI_CCR_IMODE_0 0x00000100U
6763 #define QUADSPI_CCR_IMODE_1 0x00000200U
6764 #define QUADSPI_CCR_ADMODE 0x00000C00U
6765 #define QUADSPI_CCR_ADMODE_0 0x00000400U
6766 #define QUADSPI_CCR_ADMODE_1 0x00000800U
6767 #define QUADSPI_CCR_ADSIZE 0x00003000U
6768 #define QUADSPI_CCR_ADSIZE_0 0x00001000U
6769 #define QUADSPI_CCR_ADSIZE_1 0x00002000U
6770 #define QUADSPI_CCR_ABMODE 0x0000C000U
6771 #define QUADSPI_CCR_ABMODE_0 0x00004000U
6772 #define QUADSPI_CCR_ABMODE_1 0x00008000U
6773 #define QUADSPI_CCR_ABSIZE 0x00030000U
6774 #define QUADSPI_CCR_ABSIZE_0 0x00010000U
6775 #define QUADSPI_CCR_ABSIZE_1 0x00020000U
6776 #define QUADSPI_CCR_DCYC 0x007C0000U
6777 #define QUADSPI_CCR_DCYC_0 0x00040000U
6778 #define QUADSPI_CCR_DCYC_1 0x00080000U
6779 #define QUADSPI_CCR_DCYC_2 0x00100000U
6780 #define QUADSPI_CCR_DCYC_3 0x00200000U
6781 #define QUADSPI_CCR_DCYC_4 0x00400000U
6782 #define QUADSPI_CCR_DMODE 0x03000000U
6783 #define QUADSPI_CCR_DMODE_0 0x01000000U
6784 #define QUADSPI_CCR_DMODE_1 0x02000000U
6785 #define QUADSPI_CCR_FMODE 0x0C000000U
6786 #define QUADSPI_CCR_FMODE_0 0x04000000U
6787 #define QUADSPI_CCR_FMODE_1 0x08000000U
6788 #define QUADSPI_CCR_SIOO 0x10000000U
6789 #define QUADSPI_CCR_DHHC 0x40000000U
6790 #define QUADSPI_CCR_DDRM 0x80000000U
6791 /****************** Bit definition for QUADSPI_AR register *******************/
6792 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU
6794 /****************** Bit definition for QUADSPI_ABR register ******************/
6795 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU
6797 /****************** Bit definition for QUADSPI_DR register *******************/
6798 #define QUADSPI_DR_DATA 0xFFFFFFFFU
6800 /****************** Bit definition for QUADSPI_PSMKR register ****************/
6801 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU
6803 /****************** Bit definition for QUADSPI_PSMAR register ****************/
6804 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU
6806 /****************** Bit definition for QUADSPI_PIR register *****************/
6807 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU
6809 /****************** Bit definition for QUADSPI_LPTR register *****************/
6810 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU
6812 /******************************************************************************/
6813 /* */
6814 /* Reset and Clock Control */
6815 /* */
6816 /******************************************************************************/
6817 /******************** Bit definition for RCC_CR register ********************/
6818 #define RCC_CR_HSION 0x00000001U
6819 #define RCC_CR_HSIRDY 0x00000002U
6820 
6821 #define RCC_CR_HSITRIM 0x000000F8U
6822 #define RCC_CR_HSITRIM_0 0x00000008U
6823 #define RCC_CR_HSITRIM_1 0x00000010U
6824 #define RCC_CR_HSITRIM_2 0x00000020U
6825 #define RCC_CR_HSITRIM_3 0x00000040U
6826 #define RCC_CR_HSITRIM_4 0x00000080U
6828 #define RCC_CR_HSICAL 0x0000FF00U
6829 #define RCC_CR_HSICAL_0 0x00000100U
6830 #define RCC_CR_HSICAL_1 0x00000200U
6831 #define RCC_CR_HSICAL_2 0x00000400U
6832 #define RCC_CR_HSICAL_3 0x00000800U
6833 #define RCC_CR_HSICAL_4 0x00001000U
6834 #define RCC_CR_HSICAL_5 0x00002000U
6835 #define RCC_CR_HSICAL_6 0x00004000U
6836 #define RCC_CR_HSICAL_7 0x00008000U
6838 #define RCC_CR_HSEON 0x00010000U
6839 #define RCC_CR_HSERDY 0x00020000U
6840 #define RCC_CR_HSEBYP 0x00040000U
6841 #define RCC_CR_CSSON 0x00080000U
6842 #define RCC_CR_PLLON 0x01000000U
6843 #define RCC_CR_PLLRDY 0x02000000U
6844 #define RCC_CR_PLLI2SON 0x04000000U
6845 #define RCC_CR_PLLI2SRDY 0x08000000U
6846 #define RCC_CR_PLLSAION 0x10000000U
6847 #define RCC_CR_PLLSAIRDY 0x20000000U
6848 
6849 /******************** Bit definition for RCC_PLLCFGR register ***************/
6850 #define RCC_PLLCFGR_PLLM 0x0000003FU
6851 #define RCC_PLLCFGR_PLLM_0 0x00000001U
6852 #define RCC_PLLCFGR_PLLM_1 0x00000002U
6853 #define RCC_PLLCFGR_PLLM_2 0x00000004U
6854 #define RCC_PLLCFGR_PLLM_3 0x00000008U
6855 #define RCC_PLLCFGR_PLLM_4 0x00000010U
6856 #define RCC_PLLCFGR_PLLM_5 0x00000020U
6857 
6858 #define RCC_PLLCFGR_PLLN 0x00007FC0U
6859 #define RCC_PLLCFGR_PLLN_0 0x00000040U
6860 #define RCC_PLLCFGR_PLLN_1 0x00000080U
6861 #define RCC_PLLCFGR_PLLN_2 0x00000100U
6862 #define RCC_PLLCFGR_PLLN_3 0x00000200U
6863 #define RCC_PLLCFGR_PLLN_4 0x00000400U
6864 #define RCC_PLLCFGR_PLLN_5 0x00000800U
6865 #define RCC_PLLCFGR_PLLN_6 0x00001000U
6866 #define RCC_PLLCFGR_PLLN_7 0x00002000U
6867 #define RCC_PLLCFGR_PLLN_8 0x00004000U
6868 
6869 #define RCC_PLLCFGR_PLLP 0x00030000U
6870 #define RCC_PLLCFGR_PLLP_0 0x00010000U
6871 #define RCC_PLLCFGR_PLLP_1 0x00020000U
6872 
6873 #define RCC_PLLCFGR_PLLSRC 0x00400000U
6874 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
6875 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
6876 
6877 #define RCC_PLLCFGR_PLLQ 0x0F000000U
6878 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
6879 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
6880 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
6881 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
6882 
6883 #define RCC_PLLCFGR_PLLR 0x70000000U
6884 #define RCC_PLLCFGR_PLLR_0 0x10000000U
6885 #define RCC_PLLCFGR_PLLR_1 0x20000000U
6886 #define RCC_PLLCFGR_PLLR_2 0x40000000U
6887 
6888 
6889 /******************** Bit definition for RCC_CFGR register ******************/
6891 #define RCC_CFGR_SW 0x00000003U
6892 #define RCC_CFGR_SW_0 0x00000001U
6893 #define RCC_CFGR_SW_1 0x00000002U
6895 #define RCC_CFGR_SW_HSI 0x00000000U
6896 #define RCC_CFGR_SW_HSE 0x00000001U
6897 #define RCC_CFGR_SW_PLL 0x00000002U
6900 #define RCC_CFGR_SWS 0x0000000CU
6901 #define RCC_CFGR_SWS_0 0x00000004U
6902 #define RCC_CFGR_SWS_1 0x00000008U
6904 #define RCC_CFGR_SWS_HSI 0x00000000U
6905 #define RCC_CFGR_SWS_HSE 0x00000004U
6906 #define RCC_CFGR_SWS_PLL 0x00000008U
6909 #define RCC_CFGR_HPRE 0x000000F0U
6910 #define RCC_CFGR_HPRE_0 0x00000010U
6911 #define RCC_CFGR_HPRE_1 0x00000020U
6912 #define RCC_CFGR_HPRE_2 0x00000040U
6913 #define RCC_CFGR_HPRE_3 0x00000080U
6915 #define RCC_CFGR_HPRE_DIV1 0x00000000U
6916 #define RCC_CFGR_HPRE_DIV2 0x00000080U
6917 #define RCC_CFGR_HPRE_DIV4 0x00000090U
6918 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
6919 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
6920 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
6921 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
6922 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
6923 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
6926 #define RCC_CFGR_PPRE1 0x00001C00U
6927 #define RCC_CFGR_PPRE1_0 0x00000400U
6928 #define RCC_CFGR_PPRE1_1 0x00000800U
6929 #define RCC_CFGR_PPRE1_2 0x00001000U
6931 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
6932 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
6933 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
6934 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
6935 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
6938 #define RCC_CFGR_PPRE2 0x0000E000U
6939 #define RCC_CFGR_PPRE2_0 0x00002000U
6940 #define RCC_CFGR_PPRE2_1 0x00004000U
6941 #define RCC_CFGR_PPRE2_2 0x00008000U
6943 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
6944 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
6945 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
6946 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
6947 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
6950 #define RCC_CFGR_RTCPRE 0x001F0000U
6951 #define RCC_CFGR_RTCPRE_0 0x00010000U
6952 #define RCC_CFGR_RTCPRE_1 0x00020000U
6953 #define RCC_CFGR_RTCPRE_2 0x00040000U
6954 #define RCC_CFGR_RTCPRE_3 0x00080000U
6955 #define RCC_CFGR_RTCPRE_4 0x00100000U
6956 
6958 #define RCC_CFGR_MCO1 0x00600000U
6959 #define RCC_CFGR_MCO1_0 0x00200000U
6960 #define RCC_CFGR_MCO1_1 0x00400000U
6961 
6962 #define RCC_CFGR_I2SSRC 0x00800000U
6963 
6964 #define RCC_CFGR_MCO1PRE 0x07000000U
6965 #define RCC_CFGR_MCO1PRE_0 0x01000000U
6966 #define RCC_CFGR_MCO1PRE_1 0x02000000U
6967 #define RCC_CFGR_MCO1PRE_2 0x04000000U
6968 
6969 #define RCC_CFGR_MCO2PRE 0x38000000U
6970 #define RCC_CFGR_MCO2PRE_0 0x08000000U
6971 #define RCC_CFGR_MCO2PRE_1 0x10000000U
6972 #define RCC_CFGR_MCO2PRE_2 0x20000000U
6973 
6974 #define RCC_CFGR_MCO2 0xC0000000U
6975 #define RCC_CFGR_MCO2_0 0x40000000U
6976 #define RCC_CFGR_MCO2_1 0x80000000U
6977 
6978 /******************** Bit definition for RCC_CIR register *******************/
6979 #define RCC_CIR_LSIRDYF 0x00000001U
6980 #define RCC_CIR_LSERDYF 0x00000002U
6981 #define RCC_CIR_HSIRDYF 0x00000004U
6982 #define RCC_CIR_HSERDYF 0x00000008U
6983 #define RCC_CIR_PLLRDYF 0x00000010U
6984 #define RCC_CIR_PLLI2SRDYF 0x00000020U
6985 #define RCC_CIR_PLLSAIRDYF 0x00000040U
6986 #define RCC_CIR_CSSF 0x00000080U
6987 #define RCC_CIR_LSIRDYIE 0x00000100U
6988 #define RCC_CIR_LSERDYIE 0x00000200U
6989 #define RCC_CIR_HSIRDYIE 0x00000400U
6990 #define RCC_CIR_HSERDYIE 0x00000800U
6991 #define RCC_CIR_PLLRDYIE 0x00001000U
6992 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
6993 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
6994 #define RCC_CIR_LSIRDYC 0x00010000U
6995 #define RCC_CIR_LSERDYC 0x00020000U
6996 #define RCC_CIR_HSIRDYC 0x00040000U
6997 #define RCC_CIR_HSERDYC 0x00080000U
6998 #define RCC_CIR_PLLRDYC 0x00100000U
6999 #define RCC_CIR_PLLI2SRDYC 0x00200000U
7000 #define RCC_CIR_PLLSAIRDYC 0x00400000U
7001 #define RCC_CIR_CSSC 0x00800000U
7002 
7003 /******************** Bit definition for RCC_AHB1RSTR register **************/
7004 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
7005 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
7006 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
7007 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
7008 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
7009 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
7010 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
7011 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
7012 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
7013 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
7014 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
7015 #define RCC_AHB1RSTR_CRCRST 0x00001000U
7016 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
7017 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
7018 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
7019 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
7020 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
7021 
7022 /******************** Bit definition for RCC_AHB2RSTR register **************/
7023 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
7024 #define RCC_AHB2RSTR_CRYPRST 0x00000010U
7025 #define RCC_AHB2RSTR_HASHRST 0x00000020U
7026  /* maintained for legacy purpose */
7027 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
7028 #define RCC_AHB2RSTR_RNGRST 0x00000040U
7029 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
7030 
7031 /******************** Bit definition for RCC_AHB3RSTR register **************/
7032 #define RCC_AHB3RSTR_FMCRST 0x00000001U
7033 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
7034 
7035 /******************** Bit definition for RCC_APB1RSTR register **************/
7036 #define RCC_APB1RSTR_TIM2RST 0x00000001U
7037 #define RCC_APB1RSTR_TIM3RST 0x00000002U
7038 #define RCC_APB1RSTR_TIM4RST 0x00000004U
7039 #define RCC_APB1RSTR_TIM5RST 0x00000008U
7040 #define RCC_APB1RSTR_TIM6RST 0x00000010U
7041 #define RCC_APB1RSTR_TIM7RST 0x00000020U
7042 #define RCC_APB1RSTR_TIM12RST 0x00000040U
7043 #define RCC_APB1RSTR_TIM13RST 0x00000080U
7044 #define RCC_APB1RSTR_TIM14RST 0x00000100U
7045 #define RCC_APB1RSTR_WWDGRST 0x00000800U
7046 #define RCC_APB1RSTR_SPI2RST 0x00004000U
7047 #define RCC_APB1RSTR_SPI3RST 0x00008000U
7048 #define RCC_APB1RSTR_USART2RST 0x00020000U
7049 #define RCC_APB1RSTR_USART3RST 0x00040000U
7050 #define RCC_APB1RSTR_UART4RST 0x00080000U
7051 #define RCC_APB1RSTR_UART5RST 0x00100000U
7052 #define RCC_APB1RSTR_I2C1RST 0x00200000U
7053 #define RCC_APB1RSTR_I2C2RST 0x00400000U
7054 #define RCC_APB1RSTR_I2C3RST 0x00800000U
7055 #define RCC_APB1RSTR_CAN1RST 0x02000000U
7056 #define RCC_APB1RSTR_CAN2RST 0x04000000U
7057 #define RCC_APB1RSTR_PWRRST 0x10000000U
7058 #define RCC_APB1RSTR_DACRST 0x20000000U
7059 #define RCC_APB1RSTR_UART7RST 0x40000000U
7060 #define RCC_APB1RSTR_UART8RST 0x80000000U
7061 
7062 /******************** Bit definition for RCC_APB2RSTR register **************/
7063 #define RCC_APB2RSTR_TIM1RST 0x00000001U
7064 #define RCC_APB2RSTR_TIM8RST 0x00000002U
7065 #define RCC_APB2RSTR_USART1RST 0x00000010U
7066 #define RCC_APB2RSTR_USART6RST 0x00000020U
7067 #define RCC_APB2RSTR_ADCRST 0x00000100U
7068 #define RCC_APB2RSTR_SDIORST 0x00000800U
7069 #define RCC_APB2RSTR_SPI1RST 0x00001000U
7070 #define RCC_APB2RSTR_SPI4RST 0x00002000U
7071 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
7072 #define RCC_APB2RSTR_TIM9RST 0x00010000U
7073 #define RCC_APB2RSTR_TIM10RST 0x00020000U
7074 #define RCC_APB2RSTR_TIM11RST 0x00040000U
7075 #define RCC_APB2RSTR_SPI5RST 0x00100000U
7076 #define RCC_APB2RSTR_SPI6RST 0x00200000U
7077 #define RCC_APB2RSTR_SAI1RST 0x00400000U
7078 #define RCC_APB2RSTR_LTDCRST 0x04000000U
7079 #define RCC_APB2RSTR_DSIRST 0x08000000U
7080 
7081 /* Old SPI1RST bit definition, maintained for legacy purpose */
7082 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
7083 
7084 /******************** Bit definition for RCC_AHB1ENR register ***************/
7085 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
7086 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
7087 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
7088 #define RCC_AHB1ENR_GPIODEN 0x00000008U
7089 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
7090 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
7091 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
7092 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
7093 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
7094 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
7095 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
7096 
7097 #define RCC_AHB1ENR_CRCEN 0x00001000U
7098 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
7099 #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
7100 #define RCC_AHB1ENR_DMA1EN 0x00200000U
7101 #define RCC_AHB1ENR_DMA2EN 0x00400000U
7102 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
7103 
7104 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
7105 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
7106 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
7107 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
7108 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
7109 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
7110 
7111 /******************** Bit definition for RCC_AHB2ENR register ***************/
7112 #define RCC_AHB2ENR_DCMIEN 0x00000001U
7113 #define RCC_AHB2ENR_CRYPEN 0x00000010U
7114 #define RCC_AHB2ENR_HASHEN 0x00000020U
7115 #define RCC_AHB2ENR_RNGEN 0x00000040U
7116 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
7117 
7118 /******************** Bit definition for RCC_AHB3ENR register ***************/
7119 #define RCC_AHB3ENR_FMCEN 0x00000001U
7120 #define RCC_AHB3ENR_QSPIEN 0x00000002U
7121 
7122 /******************** Bit definition for RCC_APB1ENR register ***************/
7123 #define RCC_APB1ENR_TIM2EN 0x00000001U
7124 #define RCC_APB1ENR_TIM3EN 0x00000002U
7125 #define RCC_APB1ENR_TIM4EN 0x00000004U
7126 #define RCC_APB1ENR_TIM5EN 0x00000008U
7127 #define RCC_APB1ENR_TIM6EN 0x00000010U
7128 #define RCC_APB1ENR_TIM7EN 0x00000020U
7129 #define RCC_APB1ENR_TIM12EN 0x00000040U
7130 #define RCC_APB1ENR_TIM13EN 0x00000080U
7131 #define RCC_APB1ENR_TIM14EN 0x00000100U
7132 #define RCC_APB1ENR_WWDGEN 0x00000800U
7133 #define RCC_APB1ENR_SPI2EN 0x00004000U
7134 #define RCC_APB1ENR_SPI3EN 0x00008000U
7135 #define RCC_APB1ENR_USART2EN 0x00020000U
7136 #define RCC_APB1ENR_USART3EN 0x00040000U
7137 #define RCC_APB1ENR_UART4EN 0x00080000U
7138 #define RCC_APB1ENR_UART5EN 0x00100000U
7139 #define RCC_APB1ENR_I2C1EN 0x00200000U
7140 #define RCC_APB1ENR_I2C2EN 0x00400000U
7141 #define RCC_APB1ENR_I2C3EN 0x00800000U
7142 #define RCC_APB1ENR_CAN1EN 0x02000000U
7143 #define RCC_APB1ENR_CAN2EN 0x04000000U
7144 #define RCC_APB1ENR_PWREN 0x10000000U
7145 #define RCC_APB1ENR_DACEN 0x20000000U
7146 #define RCC_APB1ENR_UART7EN 0x40000000U
7147 #define RCC_APB1ENR_UART8EN 0x80000000U
7148 
7149 /******************** Bit definition for RCC_APB2ENR register ***************/
7150 #define RCC_APB2ENR_TIM1EN 0x00000001U
7151 #define RCC_APB2ENR_TIM8EN 0x00000002U
7152 #define RCC_APB2ENR_USART1EN 0x00000010U
7153 #define RCC_APB2ENR_USART6EN 0x00000020U
7154 #define RCC_APB2ENR_ADC1EN 0x00000100U
7155 #define RCC_APB2ENR_ADC2EN 0x00000200U
7156 #define RCC_APB2ENR_ADC3EN 0x00000400U
7157 #define RCC_APB2ENR_SDIOEN 0x00000800U
7158 #define RCC_APB2ENR_SPI1EN 0x00001000U
7159 #define RCC_APB2ENR_SPI4EN 0x00002000U
7160 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
7161 #define RCC_APB2ENR_TIM9EN 0x00010000U
7162 #define RCC_APB2ENR_TIM10EN 0x00020000U
7163 #define RCC_APB2ENR_TIM11EN 0x00040000U
7164 #define RCC_APB2ENR_SPI5EN 0x00100000U
7165 #define RCC_APB2ENR_SPI6EN 0x00200000U
7166 #define RCC_APB2ENR_SAI1EN 0x00400000U
7167 #define RCC_APB2ENR_LTDCEN 0x04000000U
7168 #define RCC_APB2ENR_DSIEN 0x08000000U
7169 
7170 /******************** Bit definition for RCC_AHB1LPENR register *************/
7171 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
7172 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
7173 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
7174 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
7175 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
7176 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
7177 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
7178 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
7179 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
7180 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
7181 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
7182 
7183 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
7184 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
7185 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
7186 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
7187 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
7188 #define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
7189 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
7190 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
7191 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
7192 
7193 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
7194 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
7195 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
7196 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
7197 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
7198 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
7199 
7200 /******************** Bit definition for RCC_AHB2LPENR register *************/
7201 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
7202 #define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
7203 #define RCC_AHB2LPENR_HASHLPEN 0x00000020U
7204 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
7205 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
7206 
7207 /******************** Bit definition for RCC_AHB3LPENR register *************/
7208 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
7209 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
7210 
7211 /******************** Bit definition for RCC_APB1LPENR register *************/
7212 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
7213 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
7214 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
7215 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
7216 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
7217 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
7218 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
7219 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
7220 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
7221 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
7222 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
7223 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
7224 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
7225 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
7226 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
7227 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
7228 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
7229 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
7230 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
7231 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
7232 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
7233 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
7234 #define RCC_APB1LPENR_DACLPEN 0x20000000U
7235 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
7236 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
7237 
7238 /******************** Bit definition for RCC_APB2LPENR register *************/
7239 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
7240 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
7241 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
7242 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
7243 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
7244 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
7245 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
7246 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
7247 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
7248 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
7249 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
7250 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
7251 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
7252 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
7253 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
7254 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
7255 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
7256 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
7257 #define RCC_APB2LPENR_DSILPEN 0x08000000U
7258 
7259 /******************** Bit definition for RCC_BDCR register ******************/
7260 #define RCC_BDCR_LSEON 0x00000001U
7261 #define RCC_BDCR_LSERDY 0x00000002U
7262 #define RCC_BDCR_LSEBYP 0x00000004U
7263 #define RCC_BDCR_LSEMOD 0x00000008U
7264 
7265 #define RCC_BDCR_RTCSEL 0x00000300U
7266 #define RCC_BDCR_RTCSEL_0 0x00000100U
7267 #define RCC_BDCR_RTCSEL_1 0x00000200U
7268 
7269 #define RCC_BDCR_RTCEN 0x00008000U
7270 #define RCC_BDCR_BDRST 0x00010000U
7271 
7272 /******************** Bit definition for RCC_CSR register *******************/
7273 #define RCC_CSR_LSION 0x00000001U
7274 #define RCC_CSR_LSIRDY 0x00000002U
7275 #define RCC_CSR_RMVF 0x01000000U
7276 #define RCC_CSR_BORRSTF 0x02000000U
7277 #define RCC_CSR_PADRSTF 0x04000000U
7278 #define RCC_CSR_PORRSTF 0x08000000U
7279 #define RCC_CSR_SFTRSTF 0x10000000U
7280 #define RCC_CSR_WDGRSTF 0x20000000U
7281 #define RCC_CSR_WWDGRSTF 0x40000000U
7282 #define RCC_CSR_LPWRRSTF 0x80000000U
7283 
7284 /******************** Bit definition for RCC_SSCGR register *****************/
7285 #define RCC_SSCGR_MODPER 0x00001FFFU
7286 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
7287 #define RCC_SSCGR_SPREADSEL 0x40000000U
7288 #define RCC_SSCGR_SSCGEN 0x80000000U
7289 
7290 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
7291 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
7292 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
7293 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
7294 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
7295 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
7296 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
7297 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
7298 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
7299 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
7300 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
7301 
7302 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
7303 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
7304 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
7305 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
7306 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
7307 
7308 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
7309 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
7310 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
7311 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
7312 
7313 
7314 /******************** Bit definition for RCC_PLLSAICFGR register ************/
7315 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
7316 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
7317 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
7318 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
7319 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
7320 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
7321 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
7322 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
7323 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
7324 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
7325 
7326 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
7327 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
7328 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
7329 
7330 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
7331 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
7332 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
7333 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
7334 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
7335 
7336 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
7337 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
7338 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
7339 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
7340 
7341 /******************** Bit definition for RCC_DCKCFGR register ***************/
7342 #define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
7343 #define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
7344 #define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
7345 #define RCC_DCKCFGR_SAI1ASRC 0x00300000U
7346 #define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
7347 #define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
7348 #define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
7349 #define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
7350 #define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
7351 #define RCC_DCKCFGR_TIMPRE 0x01000000U
7352 #define RCC_DCKCFGR_CK48MSEL 0x08000000U
7353 #define RCC_DCKCFGR_SDIOSEL 0x10000000U
7354 #define RCC_DCKCFGR_DSISEL 0x20000000U
7355 
7356 /******************************************************************************/
7357 /* */
7358 /* RNG */
7359 /* */
7360 /******************************************************************************/
7361 /******************** Bits definition for RNG_CR register *******************/
7362 #define RNG_CR_RNGEN 0x00000004U
7363 #define RNG_CR_IE 0x00000008U
7364 
7365 /******************** Bits definition for RNG_SR register *******************/
7366 #define RNG_SR_DRDY 0x00000001U
7367 #define RNG_SR_CECS 0x00000002U
7368 #define RNG_SR_SECS 0x00000004U
7369 #define RNG_SR_CEIS 0x00000020U
7370 #define RNG_SR_SEIS 0x00000040U
7371 
7372 /******************************************************************************/
7373 /* */
7374 /* Real-Time Clock (RTC) */
7375 /* */
7376 /******************************************************************************/
7377 /******************** Bits definition for RTC_TR register *******************/
7378 #define RTC_TR_PM 0x00400000U
7379 #define RTC_TR_HT 0x00300000U
7380 #define RTC_TR_HT_0 0x00100000U
7381 #define RTC_TR_HT_1 0x00200000U
7382 #define RTC_TR_HU 0x000F0000U
7383 #define RTC_TR_HU_0 0x00010000U
7384 #define RTC_TR_HU_1 0x00020000U
7385 #define RTC_TR_HU_2 0x00040000U
7386 #define RTC_TR_HU_3 0x00080000U
7387 #define RTC_TR_MNT 0x00007000U
7388 #define RTC_TR_MNT_0 0x00001000U
7389 #define RTC_TR_MNT_1 0x00002000U
7390 #define RTC_TR_MNT_2 0x00004000U
7391 #define RTC_TR_MNU 0x00000F00U
7392 #define RTC_TR_MNU_0 0x00000100U
7393 #define RTC_TR_MNU_1 0x00000200U
7394 #define RTC_TR_MNU_2 0x00000400U
7395 #define RTC_TR_MNU_3 0x00000800U
7396 #define RTC_TR_ST 0x00000070U
7397 #define RTC_TR_ST_0 0x00000010U
7398 #define RTC_TR_ST_1 0x00000020U
7399 #define RTC_TR_ST_2 0x00000040U
7400 #define RTC_TR_SU 0x0000000FU
7401 #define RTC_TR_SU_0 0x00000001U
7402 #define RTC_TR_SU_1 0x00000002U
7403 #define RTC_TR_SU_2 0x00000004U
7404 #define RTC_TR_SU_3 0x00000008U
7405 
7406 /******************** Bits definition for RTC_DR register *******************/
7407 #define RTC_DR_YT 0x00F00000U
7408 #define RTC_DR_YT_0 0x00100000U
7409 #define RTC_DR_YT_1 0x00200000U
7410 #define RTC_DR_YT_2 0x00400000U
7411 #define RTC_DR_YT_3 0x00800000U
7412 #define RTC_DR_YU 0x000F0000U
7413 #define RTC_DR_YU_0 0x00010000U
7414 #define RTC_DR_YU_1 0x00020000U
7415 #define RTC_DR_YU_2 0x00040000U
7416 #define RTC_DR_YU_3 0x00080000U
7417 #define RTC_DR_WDU 0x0000E000U
7418 #define RTC_DR_WDU_0 0x00002000U
7419 #define RTC_DR_WDU_1 0x00004000U
7420 #define RTC_DR_WDU_2 0x00008000U
7421 #define RTC_DR_MT 0x00001000U
7422 #define RTC_DR_MU 0x00000F00U
7423 #define RTC_DR_MU_0 0x00000100U
7424 #define RTC_DR_MU_1 0x00000200U
7425 #define RTC_DR_MU_2 0x00000400U
7426 #define RTC_DR_MU_3 0x00000800U
7427 #define RTC_DR_DT 0x00000030U
7428 #define RTC_DR_DT_0 0x00000010U
7429 #define RTC_DR_DT_1 0x00000020U
7430 #define RTC_DR_DU 0x0000000FU
7431 #define RTC_DR_DU_0 0x00000001U
7432 #define RTC_DR_DU_1 0x00000002U
7433 #define RTC_DR_DU_2 0x00000004U
7434 #define RTC_DR_DU_3 0x00000008U
7435 
7436 /******************** Bits definition for RTC_CR register *******************/
7437 #define RTC_CR_COE 0x00800000U
7438 #define RTC_CR_OSEL 0x00600000U
7439 #define RTC_CR_OSEL_0 0x00200000U
7440 #define RTC_CR_OSEL_1 0x00400000U
7441 #define RTC_CR_POL 0x00100000U
7442 #define RTC_CR_COSEL 0x00080000U
7443 #define RTC_CR_BCK 0x00040000U
7444 #define RTC_CR_SUB1H 0x00020000U
7445 #define RTC_CR_ADD1H 0x00010000U
7446 #define RTC_CR_TSIE 0x00008000U
7447 #define RTC_CR_WUTIE 0x00004000U
7448 #define RTC_CR_ALRBIE 0x00002000U
7449 #define RTC_CR_ALRAIE 0x00001000U
7450 #define RTC_CR_TSE 0x00000800U
7451 #define RTC_CR_WUTE 0x00000400U
7452 #define RTC_CR_ALRBE 0x00000200U
7453 #define RTC_CR_ALRAE 0x00000100U
7454 #define RTC_CR_DCE 0x00000080U
7455 #define RTC_CR_FMT 0x00000040U
7456 #define RTC_CR_BYPSHAD 0x00000020U
7457 #define RTC_CR_REFCKON 0x00000010U
7458 #define RTC_CR_TSEDGE 0x00000008U
7459 #define RTC_CR_WUCKSEL 0x00000007U
7460 #define RTC_CR_WUCKSEL_0 0x00000001U
7461 #define RTC_CR_WUCKSEL_1 0x00000002U
7462 #define RTC_CR_WUCKSEL_2 0x00000004U
7463 
7464 /******************** Bits definition for RTC_ISR register ******************/
7465 #define RTC_ISR_RECALPF 0x00010000U
7466 #define RTC_ISR_TAMP1F 0x00002000U
7467 #define RTC_ISR_TAMP2F 0x00004000U
7468 #define RTC_ISR_TSOVF 0x00001000U
7469 #define RTC_ISR_TSF 0x00000800U
7470 #define RTC_ISR_WUTF 0x00000400U
7471 #define RTC_ISR_ALRBF 0x00000200U
7472 #define RTC_ISR_ALRAF 0x00000100U
7473 #define RTC_ISR_INIT 0x00000080U
7474 #define RTC_ISR_INITF 0x00000040U
7475 #define RTC_ISR_RSF 0x00000020U
7476 #define RTC_ISR_INITS 0x00000010U
7477 #define RTC_ISR_SHPF 0x00000008U
7478 #define RTC_ISR_WUTWF 0x00000004U
7479 #define RTC_ISR_ALRBWF 0x00000002U
7480 #define RTC_ISR_ALRAWF 0x00000001U
7481 
7482 /******************** Bits definition for RTC_PRER register *****************/
7483 #define RTC_PRER_PREDIV_A 0x007F0000U
7484 #define RTC_PRER_PREDIV_S 0x00007FFFU
7485 
7486 /******************** Bits definition for RTC_WUTR register *****************/
7487 #define RTC_WUTR_WUT 0x0000FFFFU
7488 
7489 /******************** Bits definition for RTC_CALIBR register ***************/
7490 #define RTC_CALIBR_DCS 0x00000080U
7491 #define RTC_CALIBR_DC 0x0000001FU
7492 
7493 /******************** Bits definition for RTC_ALRMAR register ***************/
7494 #define RTC_ALRMAR_MSK4 0x80000000U
7495 #define RTC_ALRMAR_WDSEL 0x40000000U
7496 #define RTC_ALRMAR_DT 0x30000000U
7497 #define RTC_ALRMAR_DT_0 0x10000000U
7498 #define RTC_ALRMAR_DT_1 0x20000000U
7499 #define RTC_ALRMAR_DU 0x0F000000U
7500 #define RTC_ALRMAR_DU_0 0x01000000U
7501 #define RTC_ALRMAR_DU_1 0x02000000U
7502 #define RTC_ALRMAR_DU_2 0x04000000U
7503 #define RTC_ALRMAR_DU_3 0x08000000U
7504 #define RTC_ALRMAR_MSK3 0x00800000U
7505 #define RTC_ALRMAR_PM 0x00400000U
7506 #define RTC_ALRMAR_HT 0x00300000U
7507 #define RTC_ALRMAR_HT_0 0x00100000U
7508 #define RTC_ALRMAR_HT_1 0x00200000U
7509 #define RTC_ALRMAR_HU 0x000F0000U
7510 #define RTC_ALRMAR_HU_0 0x00010000U
7511 #define RTC_ALRMAR_HU_1 0x00020000U
7512 #define RTC_ALRMAR_HU_2 0x00040000U
7513 #define RTC_ALRMAR_HU_3 0x00080000U
7514 #define RTC_ALRMAR_MSK2 0x00008000U
7515 #define RTC_ALRMAR_MNT 0x00007000U
7516 #define RTC_ALRMAR_MNT_0 0x00001000U
7517 #define RTC_ALRMAR_MNT_1 0x00002000U
7518 #define RTC_ALRMAR_MNT_2 0x00004000U
7519 #define RTC_ALRMAR_MNU 0x00000F00U
7520 #define RTC_ALRMAR_MNU_0 0x00000100U
7521 #define RTC_ALRMAR_MNU_1 0x00000200U
7522 #define RTC_ALRMAR_MNU_2 0x00000400U
7523 #define RTC_ALRMAR_MNU_3 0x00000800U
7524 #define RTC_ALRMAR_MSK1 0x00000080U
7525 #define RTC_ALRMAR_ST 0x00000070U
7526 #define RTC_ALRMAR_ST_0 0x00000010U
7527 #define RTC_ALRMAR_ST_1 0x00000020U
7528 #define RTC_ALRMAR_ST_2 0x00000040U
7529 #define RTC_ALRMAR_SU 0x0000000FU
7530 #define RTC_ALRMAR_SU_0 0x00000001U
7531 #define RTC_ALRMAR_SU_1 0x00000002U
7532 #define RTC_ALRMAR_SU_2 0x00000004U
7533 #define RTC_ALRMAR_SU_3 0x00000008U
7534 
7535 /******************** Bits definition for RTC_ALRMBR register ***************/
7536 #define RTC_ALRMBR_MSK4 0x80000000U
7537 #define RTC_ALRMBR_WDSEL 0x40000000U
7538 #define RTC_ALRMBR_DT 0x30000000U
7539 #define RTC_ALRMBR_DT_0 0x10000000U
7540 #define RTC_ALRMBR_DT_1 0x20000000U
7541 #define RTC_ALRMBR_DU 0x0F000000U
7542 #define RTC_ALRMBR_DU_0 0x01000000U
7543 #define RTC_ALRMBR_DU_1 0x02000000U
7544 #define RTC_ALRMBR_DU_2 0x04000000U
7545 #define RTC_ALRMBR_DU_3 0x08000000U
7546 #define RTC_ALRMBR_MSK3 0x00800000U
7547 #define RTC_ALRMBR_PM 0x00400000U
7548 #define RTC_ALRMBR_HT 0x00300000U
7549 #define RTC_ALRMBR_HT_0 0x00100000U
7550 #define RTC_ALRMBR_HT_1 0x00200000U
7551 #define RTC_ALRMBR_HU 0x000F0000U
7552 #define RTC_ALRMBR_HU_0 0x00010000U
7553 #define RTC_ALRMBR_HU_1 0x00020000U
7554 #define RTC_ALRMBR_HU_2 0x00040000U
7555 #define RTC_ALRMBR_HU_3 0x00080000U
7556 #define RTC_ALRMBR_MSK2 0x00008000U
7557 #define RTC_ALRMBR_MNT 0x00007000U
7558 #define RTC_ALRMBR_MNT_0 0x00001000U
7559 #define RTC_ALRMBR_MNT_1 0x00002000U
7560 #define RTC_ALRMBR_MNT_2 0x00004000U
7561 #define RTC_ALRMBR_MNU 0x00000F00U
7562 #define RTC_ALRMBR_MNU_0 0x00000100U
7563 #define RTC_ALRMBR_MNU_1 0x00000200U
7564 #define RTC_ALRMBR_MNU_2 0x00000400U
7565 #define RTC_ALRMBR_MNU_3 0x00000800U
7566 #define RTC_ALRMBR_MSK1 0x00000080U
7567 #define RTC_ALRMBR_ST 0x00000070U
7568 #define RTC_ALRMBR_ST_0 0x00000010U
7569 #define RTC_ALRMBR_ST_1 0x00000020U
7570 #define RTC_ALRMBR_ST_2 0x00000040U
7571 #define RTC_ALRMBR_SU 0x0000000FU
7572 #define RTC_ALRMBR_SU_0 0x00000001U
7573 #define RTC_ALRMBR_SU_1 0x00000002U
7574 #define RTC_ALRMBR_SU_2 0x00000004U
7575 #define RTC_ALRMBR_SU_3 0x00000008U
7576 
7577 /******************** Bits definition for RTC_WPR register ******************/
7578 #define RTC_WPR_KEY 0x000000FFU
7579 
7580 /******************** Bits definition for RTC_SSR register ******************/
7581 #define RTC_SSR_SS 0x0000FFFFU
7582 
7583 /******************** Bits definition for RTC_SHIFTR register ***************/
7584 #define RTC_SHIFTR_SUBFS 0x00007FFFU
7585 #define RTC_SHIFTR_ADD1S 0x80000000U
7586 
7587 /******************** Bits definition for RTC_TSTR register *****************/
7588 #define RTC_TSTR_PM 0x00400000U
7589 #define RTC_TSTR_HT 0x00300000U
7590 #define RTC_TSTR_HT_0 0x00100000U
7591 #define RTC_TSTR_HT_1 0x00200000U
7592 #define RTC_TSTR_HU 0x000F0000U
7593 #define RTC_TSTR_HU_0 0x00010000U
7594 #define RTC_TSTR_HU_1 0x00020000U
7595 #define RTC_TSTR_HU_2 0x00040000U
7596 #define RTC_TSTR_HU_3 0x00080000U
7597 #define RTC_TSTR_MNT 0x00007000U
7598 #define RTC_TSTR_MNT_0 0x00001000U
7599 #define RTC_TSTR_MNT_1 0x00002000U
7600 #define RTC_TSTR_MNT_2 0x00004000U
7601 #define RTC_TSTR_MNU 0x00000F00U
7602 #define RTC_TSTR_MNU_0 0x00000100U
7603 #define RTC_TSTR_MNU_1 0x00000200U
7604 #define RTC_TSTR_MNU_2 0x00000400U
7605 #define RTC_TSTR_MNU_3 0x00000800U
7606 #define RTC_TSTR_ST 0x00000070U
7607 #define RTC_TSTR_ST_0 0x00000010U
7608 #define RTC_TSTR_ST_1 0x00000020U
7609 #define RTC_TSTR_ST_2 0x00000040U
7610 #define RTC_TSTR_SU 0x0000000FU
7611 #define RTC_TSTR_SU_0 0x00000001U
7612 #define RTC_TSTR_SU_1 0x00000002U
7613 #define RTC_TSTR_SU_2 0x00000004U
7614 #define RTC_TSTR_SU_3 0x00000008U
7615 
7616 /******************** Bits definition for RTC_TSDR register *****************/
7617 #define RTC_TSDR_WDU 0x0000E000U
7618 #define RTC_TSDR_WDU_0 0x00002000U
7619 #define RTC_TSDR_WDU_1 0x00004000U
7620 #define RTC_TSDR_WDU_2 0x00008000U
7621 #define RTC_TSDR_MT 0x00001000U
7622 #define RTC_TSDR_MU 0x00000F00U
7623 #define RTC_TSDR_MU_0 0x00000100U
7624 #define RTC_TSDR_MU_1 0x00000200U
7625 #define RTC_TSDR_MU_2 0x00000400U
7626 #define RTC_TSDR_MU_3 0x00000800U
7627 #define RTC_TSDR_DT 0x00000030U
7628 #define RTC_TSDR_DT_0 0x00000010U
7629 #define RTC_TSDR_DT_1 0x00000020U
7630 #define RTC_TSDR_DU 0x0000000FU
7631 #define RTC_TSDR_DU_0 0x00000001U
7632 #define RTC_TSDR_DU_1 0x00000002U
7633 #define RTC_TSDR_DU_2 0x00000004U
7634 #define RTC_TSDR_DU_3 0x00000008U
7635 
7636 /******************** Bits definition for RTC_TSSSR register ****************/
7637 #define RTC_TSSSR_SS 0x0000FFFFU
7638 
7639 /******************** Bits definition for RTC_CAL register *****************/
7640 #define RTC_CALR_CALP 0x00008000U
7641 #define RTC_CALR_CALW8 0x00004000U
7642 #define RTC_CALR_CALW16 0x00002000U
7643 #define RTC_CALR_CALM 0x000001FFU
7644 #define RTC_CALR_CALM_0 0x00000001U
7645 #define RTC_CALR_CALM_1 0x00000002U
7646 #define RTC_CALR_CALM_2 0x00000004U
7647 #define RTC_CALR_CALM_3 0x00000008U
7648 #define RTC_CALR_CALM_4 0x00000010U
7649 #define RTC_CALR_CALM_5 0x00000020U
7650 #define RTC_CALR_CALM_6 0x00000040U
7651 #define RTC_CALR_CALM_7 0x00000080U
7652 #define RTC_CALR_CALM_8 0x00000100U
7653 
7654 /******************** Bits definition for RTC_TAFCR register ****************/
7655 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
7656 #define RTC_TAFCR_TSINSEL 0x00020000U
7657 #define RTC_TAFCR_TAMPINSEL 0x00010000U
7658 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
7659 #define RTC_TAFCR_TAMPPRCH 0x00006000U
7660 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
7661 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
7662 #define RTC_TAFCR_TAMPFLT 0x00001800U
7663 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
7664 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
7665 #define RTC_TAFCR_TAMPFREQ 0x00000700U
7666 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
7667 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
7668 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
7669 #define RTC_TAFCR_TAMPTS 0x00000080U
7670 #define RTC_TAFCR_TAMP2TRG 0x00000010U
7671 #define RTC_TAFCR_TAMP2E 0x00000008U
7672 #define RTC_TAFCR_TAMPIE 0x00000004U
7673 #define RTC_TAFCR_TAMP1TRG 0x00000002U
7674 #define RTC_TAFCR_TAMP1E 0x00000001U
7675 
7676 /******************** Bits definition for RTC_ALRMASSR register *************/
7677 #define RTC_ALRMASSR_MASKSS 0x0F000000U
7678 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
7679 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
7680 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
7681 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
7682 #define RTC_ALRMASSR_SS 0x00007FFFU
7683 
7684 /******************** Bits definition for RTC_ALRMBSSR register *************/
7685 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
7686 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
7687 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
7688 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
7689 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
7690 #define RTC_ALRMBSSR_SS 0x00007FFFU
7691 
7692 /******************** Bits definition for RTC_BKP0R register ****************/
7693 #define RTC_BKP0R 0xFFFFFFFFU
7694 
7695 /******************** Bits definition for RTC_BKP1R register ****************/
7696 #define RTC_BKP1R 0xFFFFFFFFU
7697 
7698 /******************** Bits definition for RTC_BKP2R register ****************/
7699 #define RTC_BKP2R 0xFFFFFFFFU
7700 
7701 /******************** Bits definition for RTC_BKP3R register ****************/
7702 #define RTC_BKP3R 0xFFFFFFFFU
7703 
7704 /******************** Bits definition for RTC_BKP4R register ****************/
7705 #define RTC_BKP4R 0xFFFFFFFFU
7706 
7707 /******************** Bits definition for RTC_BKP5R register ****************/
7708 #define RTC_BKP5R 0xFFFFFFFFU
7709 
7710 /******************** Bits definition for RTC_BKP6R register ****************/
7711 #define RTC_BKP6R 0xFFFFFFFFU
7712 
7713 /******************** Bits definition for RTC_BKP7R register ****************/
7714 #define RTC_BKP7R 0xFFFFFFFFU
7715 
7716 /******************** Bits definition for RTC_BKP8R register ****************/
7717 #define RTC_BKP8R 0xFFFFFFFFU
7718 
7719 /******************** Bits definition for RTC_BKP9R register ****************/
7720 #define RTC_BKP9R 0xFFFFFFFFU
7721 
7722 /******************** Bits definition for RTC_BKP10R register ***************/
7723 #define RTC_BKP10R 0xFFFFFFFFU
7724 
7725 /******************** Bits definition for RTC_BKP11R register ***************/
7726 #define RTC_BKP11R 0xFFFFFFFFU
7727 
7728 /******************** Bits definition for RTC_BKP12R register ***************/
7729 #define RTC_BKP12R 0xFFFFFFFFU
7730 
7731 /******************** Bits definition for RTC_BKP13R register ***************/
7732 #define RTC_BKP13R 0xFFFFFFFFU
7733 
7734 /******************** Bits definition for RTC_BKP14R register ***************/
7735 #define RTC_BKP14R 0xFFFFFFFFU
7736 
7737 /******************** Bits definition for RTC_BKP15R register ***************/
7738 #define RTC_BKP15R 0xFFFFFFFFU
7739 
7740 /******************** Bits definition for RTC_BKP16R register ***************/
7741 #define RTC_BKP16R 0xFFFFFFFFU
7742 
7743 /******************** Bits definition for RTC_BKP17R register ***************/
7744 #define RTC_BKP17R 0xFFFFFFFFU
7745 
7746 /******************** Bits definition for RTC_BKP18R register ***************/
7747 #define RTC_BKP18R 0xFFFFFFFFU
7748 
7749 /******************** Bits definition for RTC_BKP19R register ***************/
7750 #define RTC_BKP19R 0xFFFFFFFFU
7751 
7752 /******************************************************************************/
7753 /* */
7754 /* Serial Audio Interface */
7755 /* */
7756 /******************************************************************************/
7757 /******************** Bit definition for SAI_GCR register *******************/
7758 #define SAI_GCR_SYNCIN 0x00000003U
7759 #define SAI_GCR_SYNCIN_0 0x00000001U
7760 #define SAI_GCR_SYNCIN_1 0x00000002U
7762 #define SAI_GCR_SYNCOUT 0x00000030U
7763 #define SAI_GCR_SYNCOUT_0 0x00000010U
7764 #define SAI_GCR_SYNCOUT_1 0x00000020U
7766 /******************* Bit definition for SAI_xCR1 register *******************/
7767 #define SAI_xCR1_MODE 0x00000003U
7768 #define SAI_xCR1_MODE_0 0x00000001U
7769 #define SAI_xCR1_MODE_1 0x00000002U
7771 #define SAI_xCR1_PRTCFG 0x0000000CU
7772 #define SAI_xCR1_PRTCFG_0 0x00000004U
7773 #define SAI_xCR1_PRTCFG_1 0x00000008U
7775 #define SAI_xCR1_DS 0x000000E0U
7776 #define SAI_xCR1_DS_0 0x00000020U
7777 #define SAI_xCR1_DS_1 0x00000040U
7778 #define SAI_xCR1_DS_2 0x00000080U
7780 #define SAI_xCR1_LSBFIRST 0x00000100U
7781 #define SAI_xCR1_CKSTR 0x00000200U
7783 #define SAI_xCR1_SYNCEN 0x00000C00U
7784 #define SAI_xCR1_SYNCEN_0 0x00000400U
7785 #define SAI_xCR1_SYNCEN_1 0x00000800U
7787 #define SAI_xCR1_MONO 0x00001000U
7788 #define SAI_xCR1_OUTDRIV 0x00002000U
7789 #define SAI_xCR1_SAIEN 0x00010000U
7790 #define SAI_xCR1_DMAEN 0x00020000U
7791 #define SAI_xCR1_NODIV 0x00080000U
7793 #define SAI_xCR1_MCKDIV 0x00F00000U
7794 #define SAI_xCR1_MCKDIV_0 0x00100000U
7795 #define SAI_xCR1_MCKDIV_1 0x00200000U
7796 #define SAI_xCR1_MCKDIV_2 0x00400000U
7797 #define SAI_xCR1_MCKDIV_3 0x00800000U
7799 /******************* Bit definition for SAI_xCR2 register *******************/
7800 #define SAI_xCR2_FTH 0x00000007U
7801 #define SAI_xCR2_FTH_0 0x00000001U
7802 #define SAI_xCR2_FTH_1 0x00000002U
7803 #define SAI_xCR2_FTH_2 0x00000004U
7805 #define SAI_xCR2_FFLUSH 0x00000008U
7806 #define SAI_xCR2_TRIS 0x00000010U
7807 #define SAI_xCR2_MUTE 0x00000020U
7808 #define SAI_xCR2_MUTEVAL 0x00000040U
7810 #define SAI_xCR2_MUTECNT 0x00001F80U
7811 #define SAI_xCR2_MUTECNT_0 0x00000080U
7812 #define SAI_xCR2_MUTECNT_1 0x00000100U
7813 #define SAI_xCR2_MUTECNT_2 0x00000200U
7814 #define SAI_xCR2_MUTECNT_3 0x00000400U
7815 #define SAI_xCR2_MUTECNT_4 0x00000800U
7816 #define SAI_xCR2_MUTECNT_5 0x00001000U
7818 #define SAI_xCR2_CPL 0x00002000U
7820 #define SAI_xCR2_COMP 0x0000C000U
7821 #define SAI_xCR2_COMP_0 0x00004000U
7822 #define SAI_xCR2_COMP_1 0x00008000U
7824 /****************** Bit definition for SAI_xFRCR register *******************/
7825 #define SAI_xFRCR_FRL 0x000000FFU
7826 #define SAI_xFRCR_FRL_0 0x00000001U
7827 #define SAI_xFRCR_FRL_1 0x00000002U
7828 #define SAI_xFRCR_FRL_2 0x00000004U
7829 #define SAI_xFRCR_FRL_3 0x00000008U
7830 #define SAI_xFRCR_FRL_4 0x00000010U
7831 #define SAI_xFRCR_FRL_5 0x00000020U
7832 #define SAI_xFRCR_FRL_6 0x00000040U
7833 #define SAI_xFRCR_FRL_7 0x00000080U
7835 #define SAI_xFRCR_FSALL 0x00007F00U
7836 #define SAI_xFRCR_FSALL_0 0x00000100U
7837 #define SAI_xFRCR_FSALL_1 0x00000200U
7838 #define SAI_xFRCR_FSALL_2 0x00000400U
7839 #define SAI_xFRCR_FSALL_3 0x00000800U
7840 #define SAI_xFRCR_FSALL_4 0x00001000U
7841 #define SAI_xFRCR_FSALL_5 0x00002000U
7842 #define SAI_xFRCR_FSALL_6 0x00004000U
7844 #define SAI_xFRCR_FSDEF 0x00010000U
7845 #define SAI_xFRCR_FSPOL 0x00020000U
7846 #define SAI_xFRCR_FSOFF 0x00040000U
7847 /* Legacy defines */
7848 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
7849 
7850 /****************** Bit definition for SAI_xSLOTR register *******************/
7851 #define SAI_xSLOTR_FBOFF 0x0000001FU
7852 #define SAI_xSLOTR_FBOFF_0 0x00000001U
7853 #define SAI_xSLOTR_FBOFF_1 0x00000002U
7854 #define SAI_xSLOTR_FBOFF_2 0x00000004U
7855 #define SAI_xSLOTR_FBOFF_3 0x00000008U
7856 #define SAI_xSLOTR_FBOFF_4 0x00000010U
7858 #define SAI_xSLOTR_SLOTSZ 0x000000C0U
7859 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U
7860 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U
7862 #define SAI_xSLOTR_NBSLOT 0x00000F00U
7863 #define SAI_xSLOTR_NBSLOT_0 0x00000100U
7864 #define SAI_xSLOTR_NBSLOT_1 0x00000200U
7865 #define SAI_xSLOTR_NBSLOT_2 0x00000400U
7866 #define SAI_xSLOTR_NBSLOT_3 0x00000800U
7868 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U
7870 /******************* Bit definition for SAI_xIMR register *******************/
7871 #define SAI_xIMR_OVRUDRIE 0x00000001U
7872 #define SAI_xIMR_MUTEDETIE 0x00000002U
7873 #define SAI_xIMR_WCKCFGIE 0x00000004U
7874 #define SAI_xIMR_FREQIE 0x00000008U
7875 #define SAI_xIMR_CNRDYIE 0x00000010U
7876 #define SAI_xIMR_AFSDETIE 0x00000020U
7877 #define SAI_xIMR_LFSDETIE 0x00000040U
7879 /******************** Bit definition for SAI_xSR register *******************/
7880 #define SAI_xSR_OVRUDR 0x00000001U
7881 #define SAI_xSR_MUTEDET 0x00000002U
7882 #define SAI_xSR_WCKCFG 0x00000004U
7883 #define SAI_xSR_FREQ 0x00000008U
7884 #define SAI_xSR_CNRDY 0x00000010U
7885 #define SAI_xSR_AFSDET 0x00000020U
7886 #define SAI_xSR_LFSDET 0x00000040U
7888 #define SAI_xSR_FLVL 0x00070000U
7889 #define SAI_xSR_FLVL_0 0x00010000U
7890 #define SAI_xSR_FLVL_1 0x00020000U
7891 #define SAI_xSR_FLVL_2 0x00040000U
7893 /****************** Bit definition for SAI_xCLRFR register ******************/
7894 #define SAI_xCLRFR_COVRUDR 0x00000001U
7895 #define SAI_xCLRFR_CMUTEDET 0x00000002U
7896 #define SAI_xCLRFR_CWCKCFG 0x00000004U
7897 #define SAI_xCLRFR_CFREQ 0x00000008U
7898 #define SAI_xCLRFR_CCNRDY 0x00000010U
7899 #define SAI_xCLRFR_CAFSDET 0x00000020U
7900 #define SAI_xCLRFR_CLFSDET 0x00000040U
7902 /****************** Bit definition for SAI_xDR register ******************/
7903 #define SAI_xDR_DATA 0xFFFFFFFFU
7904 
7905 
7906 /******************************************************************************/
7907 /* */
7908 /* SD host Interface */
7909 /* */
7910 /******************************************************************************/
7911 /****************** Bit definition for SDIO_POWER register ******************/
7912 #define SDIO_POWER_PWRCTRL 0x03U
7913 #define SDIO_POWER_PWRCTRL_0 0x01U
7914 #define SDIO_POWER_PWRCTRL_1 0x02U
7916 /****************** Bit definition for SDIO_CLKCR register ******************/
7917 #define SDIO_CLKCR_CLKDIV 0x00FFU
7918 #define SDIO_CLKCR_CLKEN 0x0100U
7919 #define SDIO_CLKCR_PWRSAV 0x0200U
7920 #define SDIO_CLKCR_BYPASS 0x0400U
7922 #define SDIO_CLKCR_WIDBUS 0x1800U
7923 #define SDIO_CLKCR_WIDBUS_0 0x0800U
7924 #define SDIO_CLKCR_WIDBUS_1 0x1000U
7926 #define SDIO_CLKCR_NEGEDGE 0x2000U
7927 #define SDIO_CLKCR_HWFC_EN 0x4000U
7929 /******************* Bit definition for SDIO_ARG register *******************/
7930 #define SDIO_ARG_CMDARG 0xFFFFFFFFU
7932 /******************* Bit definition for SDIO_CMD register *******************/
7933 #define SDIO_CMD_CMDINDEX 0x003FU
7935 #define SDIO_CMD_WAITRESP 0x00C0U
7936 #define SDIO_CMD_WAITRESP_0 0x0040U
7937 #define SDIO_CMD_WAITRESP_1 0x0080U
7939 #define SDIO_CMD_WAITINT 0x0100U
7940 #define SDIO_CMD_WAITPEND 0x0200U
7941 #define SDIO_CMD_CPSMEN 0x0400U
7942 #define SDIO_CMD_SDIOSUSPEND 0x0800U
7944 /***************** Bit definition for SDIO_RESPCMD register *****************/
7945 #define SDIO_RESPCMD_RESPCMD 0x3FU
7947 /****************** Bit definition for SDIO_RESP0 register ******************/
7948 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU
7950 /****************** Bit definition for SDIO_RESP1 register ******************/
7951 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU
7953 /****************** Bit definition for SDIO_RESP2 register ******************/
7954 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU
7956 /****************** Bit definition for SDIO_RESP3 register ******************/
7957 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU
7959 /****************** Bit definition for SDIO_RESP4 register ******************/
7960 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU
7962 /****************** Bit definition for SDIO_DTIMER register *****************/
7963 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU
7965 /****************** Bit definition for SDIO_DLEN register *******************/
7966 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU
7968 /****************** Bit definition for SDIO_DCTRL register ******************/
7969 #define SDIO_DCTRL_DTEN 0x0001U
7970 #define SDIO_DCTRL_DTDIR 0x0002U
7971 #define SDIO_DCTRL_DTMODE 0x0004U
7972 #define SDIO_DCTRL_DMAEN 0x0008U
7974 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U
7975 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U
7976 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U
7977 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U
7978 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U
7980 #define SDIO_DCTRL_RWSTART 0x0100U
7981 #define SDIO_DCTRL_RWSTOP 0x0200U
7982 #define SDIO_DCTRL_RWMOD 0x0400U
7983 #define SDIO_DCTRL_SDIOEN 0x0800U
7985 /****************** Bit definition for SDIO_DCOUNT register *****************/
7986 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU
7988 /****************** Bit definition for SDIO_STA register ********************/
7989 #define SDIO_STA_CCRCFAIL 0x00000001U
7990 #define SDIO_STA_DCRCFAIL 0x00000002U
7991 #define SDIO_STA_CTIMEOUT 0x00000004U
7992 #define SDIO_STA_DTIMEOUT 0x00000008U
7993 #define SDIO_STA_TXUNDERR 0x00000010U
7994 #define SDIO_STA_RXOVERR 0x00000020U
7995 #define SDIO_STA_CMDREND 0x00000040U
7996 #define SDIO_STA_CMDSENT 0x00000080U
7997 #define SDIO_STA_DATAEND 0x00000100U
7998 #define SDIO_STA_DBCKEND 0x00000400U
7999 #define SDIO_STA_CMDACT 0x00000800U
8000 #define SDIO_STA_TXACT 0x00001000U
8001 #define SDIO_STA_RXACT 0x00002000U
8002 #define SDIO_STA_TXFIFOHE 0x00004000U
8003 #define SDIO_STA_RXFIFOHF 0x00008000U
8004 #define SDIO_STA_TXFIFOF 0x00010000U
8005 #define SDIO_STA_RXFIFOF 0x00020000U
8006 #define SDIO_STA_TXFIFOE 0x00040000U
8007 #define SDIO_STA_RXFIFOE 0x00080000U
8008 #define SDIO_STA_TXDAVL 0x00100000U
8009 #define SDIO_STA_RXDAVL 0x00200000U
8010 #define SDIO_STA_SDIOIT 0x00400000U
8012 /******************* Bit definition for SDIO_ICR register *******************/
8013 #define SDIO_ICR_CCRCFAILC 0x00000001U
8014 #define SDIO_ICR_DCRCFAILC 0x00000002U
8015 #define SDIO_ICR_CTIMEOUTC 0x00000004U
8016 #define SDIO_ICR_DTIMEOUTC 0x00000008U
8017 #define SDIO_ICR_TXUNDERRC 0x00000010U
8018 #define SDIO_ICR_RXOVERRC 0x00000020U
8019 #define SDIO_ICR_CMDRENDC 0x00000040U
8020 #define SDIO_ICR_CMDSENTC 0x00000080U
8021 #define SDIO_ICR_DATAENDC 0x00000100U
8022 #define SDIO_ICR_DBCKENDC 0x00000400U
8023 #define SDIO_ICR_SDIOITC 0x00400000U
8025 /****************** Bit definition for SDIO_MASK register *******************/
8026 #define SDIO_MASK_CCRCFAILIE 0x00000001U
8027 #define SDIO_MASK_DCRCFAILIE 0x00000002U
8028 #define SDIO_MASK_CTIMEOUTIE 0x00000004U
8029 #define SDIO_MASK_DTIMEOUTIE 0x00000008U
8030 #define SDIO_MASK_TXUNDERRIE 0x00000010U
8031 #define SDIO_MASK_RXOVERRIE 0x00000020U
8032 #define SDIO_MASK_CMDRENDIE 0x00000040U
8033 #define SDIO_MASK_CMDSENTIE 0x00000080U
8034 #define SDIO_MASK_DATAENDIE 0x00000100U
8035 #define SDIO_MASK_DBCKENDIE 0x00000400U
8036 #define SDIO_MASK_CMDACTIE 0x00000800U
8037 #define SDIO_MASK_TXACTIE 0x00001000U
8038 #define SDIO_MASK_RXACTIE 0x00002000U
8039 #define SDIO_MASK_TXFIFOHEIE 0x00004000U
8040 #define SDIO_MASK_RXFIFOHFIE 0x00008000U
8041 #define SDIO_MASK_TXFIFOFIE 0x00010000U
8042 #define SDIO_MASK_RXFIFOFIE 0x00020000U
8043 #define SDIO_MASK_TXFIFOEIE 0x00040000U
8044 #define SDIO_MASK_RXFIFOEIE 0x00080000U
8045 #define SDIO_MASK_TXDAVLIE 0x00100000U
8046 #define SDIO_MASK_RXDAVLIE 0x00200000U
8047 #define SDIO_MASK_SDIOITIE 0x00400000U
8049 /***************** Bit definition for SDIO_FIFOCNT register *****************/
8050 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU
8052 /****************** Bit definition for SDIO_FIFO register *******************/
8053 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU
8055 /******************************************************************************/
8056 /* */
8057 /* Serial Peripheral Interface */
8058 /* */
8059 /******************************************************************************/
8060 /******************* Bit definition for SPI_CR1 register ********************/
8061 #define SPI_CR1_CPHA 0x00000001U
8062 #define SPI_CR1_CPOL 0x00000002U
8063 #define SPI_CR1_MSTR 0x00000004U
8065 #define SPI_CR1_BR 0x00000038U
8066 #define SPI_CR1_BR_0 0x00000008U
8067 #define SPI_CR1_BR_1 0x00000010U
8068 #define SPI_CR1_BR_2 0x00000020U
8070 #define SPI_CR1_SPE 0x00000040U
8071 #define SPI_CR1_LSBFIRST 0x00000080U
8072 #define SPI_CR1_SSI 0x00000100U
8073 #define SPI_CR1_SSM 0x00000200U
8074 #define SPI_CR1_RXONLY 0x00000400U
8075 #define SPI_CR1_DFF 0x00000800U
8076 #define SPI_CR1_CRCNEXT 0x00001000U
8077 #define SPI_CR1_CRCEN 0x00002000U
8078 #define SPI_CR1_BIDIOE 0x00004000U
8079 #define SPI_CR1_BIDIMODE 0x00008000U
8081 /******************* Bit definition for SPI_CR2 register ********************/
8082 #define SPI_CR2_RXDMAEN 0x00000001U
8083 #define SPI_CR2_TXDMAEN 0x00000002U
8084 #define SPI_CR2_SSOE 0x00000004U
8085 #define SPI_CR2_FRF 0x00000010U
8086 #define SPI_CR2_ERRIE 0x00000020U
8087 #define SPI_CR2_RXNEIE 0x00000040U
8088 #define SPI_CR2_TXEIE 0x00000080U
8090 /******************** Bit definition for SPI_SR register ********************/
8091 #define SPI_SR_RXNE 0x00000001U
8092 #define SPI_SR_TXE 0x00000002U
8093 #define SPI_SR_CHSIDE 0x00000004U
8094 #define SPI_SR_UDR 0x00000008U
8095 #define SPI_SR_CRCERR 0x00000010U
8096 #define SPI_SR_MODF 0x00000020U
8097 #define SPI_SR_OVR 0x00000040U
8098 #define SPI_SR_BSY 0x00000080U
8099 #define SPI_SR_FRE 0x00000100U
8101 /******************** Bit definition for SPI_DR register ********************/
8102 #define SPI_DR_DR 0x0000FFFFU
8104 /******************* Bit definition for SPI_CRCPR register ******************/
8105 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU
8107 /****************** Bit definition for SPI_RXCRCR register ******************/
8108 #define SPI_RXCRCR_RXCRC 0x0000FFFFU
8110 /****************** Bit definition for SPI_TXCRCR register ******************/
8111 #define SPI_TXCRCR_TXCRC 0x0000FFFFU
8113 /****************** Bit definition for SPI_I2SCFGR register *****************/
8114 #define SPI_I2SCFGR_CHLEN 0x00000001U
8116 #define SPI_I2SCFGR_DATLEN 0x00000006U
8117 #define SPI_I2SCFGR_DATLEN_0 0x00000002U
8118 #define SPI_I2SCFGR_DATLEN_1 0x00000004U
8120 #define SPI_I2SCFGR_CKPOL 0x00000008U
8122 #define SPI_I2SCFGR_I2SSTD 0x00000030U
8123 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U
8124 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U
8126 #define SPI_I2SCFGR_PCMSYNC 0x00000080U
8128 #define SPI_I2SCFGR_I2SCFG 0x00000300U
8129 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U
8130 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U
8132 #define SPI_I2SCFGR_I2SE 0x00000400U
8133 #define SPI_I2SCFGR_I2SMOD 0x00000800U
8134 #define SPI_I2SCFGR_ASTRTEN 0x00001000U
8136 /****************** Bit definition for SPI_I2SPR register *******************/
8137 #define SPI_I2SPR_I2SDIV 0x000000FFU
8138 #define SPI_I2SPR_ODD 0x00000100U
8139 #define SPI_I2SPR_MCKOE 0x00000200U
8141 /******************************************************************************/
8142 /* */
8143 /* SYSCFG */
8144 /* */
8145 /******************************************************************************/
8146 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
8147 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U
8148 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
8149 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
8150 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
8151 
8152 #define SYSCFG_MEMRMP_UFB_MODE 0x00000100U
8153 #define SYSCFG_SWP_FMC 0x00000C00U
8155 /****************** Bit definition for SYSCFG_PMC register ******************/
8156 #define SYSCFG_PMC_ADCxDC2 0x00070000U
8157 #define SYSCFG_PMC_ADC1DC2 0x00010000U
8158 #define SYSCFG_PMC_ADC2DC2 0x00020000U
8159 #define SYSCFG_PMC_ADC3DC2 0x00040000U
8161 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U
8163 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
8164 #define SYSCFG_EXTICR1_EXTI0 0x000FU
8165 #define SYSCFG_EXTICR1_EXTI1 0x00F0U
8166 #define SYSCFG_EXTICR1_EXTI2 0x0F00U
8167 #define SYSCFG_EXTICR1_EXTI3 0xF000U
8171 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
8172 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
8173 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
8174 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
8175 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
8176 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
8177 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
8178 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
8179 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
8180 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
8181 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
8186 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
8187 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
8188 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
8189 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
8190 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
8191 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
8192 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
8193 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
8194 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
8195 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
8196 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
8202 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
8203 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
8204 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
8205 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
8206 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
8207 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
8208 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
8209 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
8210 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
8211 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
8212 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
8218 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
8219 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
8220 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
8221 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
8222 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
8223 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
8224 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
8225 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
8226 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
8227 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
8228 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
8231 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
8232 #define SYSCFG_EXTICR2_EXTI4 0x000FU
8233 #define SYSCFG_EXTICR2_EXTI5 0x00F0U
8234 #define SYSCFG_EXTICR2_EXTI6 0x0F00U
8235 #define SYSCFG_EXTICR2_EXTI7 0xF000U
8239 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
8240 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
8241 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
8242 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
8243 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
8244 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
8245 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
8246 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
8247 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
8248 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
8249 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
8254 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
8255 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
8256 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
8257 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
8258 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
8259 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
8260 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
8261 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
8262 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
8263 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
8264 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
8269 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
8270 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
8271 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
8272 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
8273 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
8274 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
8275 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
8276 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
8277 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
8278 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
8279 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
8285 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
8286 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
8287 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
8288 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
8289 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
8290 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
8291 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
8292 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
8293 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
8294 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
8295 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
8297 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
8298 #define SYSCFG_EXTICR3_EXTI8 0x000FU
8299 #define SYSCFG_EXTICR3_EXTI9 0x00F0U
8300 #define SYSCFG_EXTICR3_EXTI10 0x0F00U
8301 #define SYSCFG_EXTICR3_EXTI11 0xF000U
8306 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
8307 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
8308 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
8309 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
8310 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
8311 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
8312 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
8313 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
8314 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
8315 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
8320 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
8321 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
8322 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
8323 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
8324 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
8325 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
8326 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
8327 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
8328 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
8329 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
8335 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
8336 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
8337 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
8338 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
8339 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
8340 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
8341 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
8342 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
8343 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
8344 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
8350 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
8351 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
8352 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
8353 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
8354 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
8355 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
8356 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
8357 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
8358 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
8359 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
8362 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
8363 #define SYSCFG_EXTICR4_EXTI12 0x000FU
8364 #define SYSCFG_EXTICR4_EXTI13 0x00F0U
8365 #define SYSCFG_EXTICR4_EXTI14 0x0F00U
8366 #define SYSCFG_EXTICR4_EXTI15 0xF000U
8370 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
8371 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
8372 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
8373 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
8374 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
8375 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
8376 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
8377 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
8378 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
8379 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
8385 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
8386 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
8387 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
8388 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
8389 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
8390 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
8391 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
8392 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
8393 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
8394 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
8400 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
8401 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
8402 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
8403 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
8404 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
8405 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
8406 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
8407 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
8408 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
8409 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
8415 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
8416 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
8417 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
8418 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
8419 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
8420 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
8421 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
8422 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
8423 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
8424 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
8426 /****************** Bit definition for SYSCFG_CMPCR register ****************/
8427 #define SYSCFG_CMPCR_CMP_PD 0x00000001U
8428 #define SYSCFG_CMPCR_READY 0x00000100U
8430 /******************************************************************************/
8431 /* */
8432 /* TIM */
8433 /* */
8434 /******************************************************************************/
8435 /******************* Bit definition for TIM_CR1 register ********************/
8436 #define TIM_CR1_CEN 0x0001U
8437 #define TIM_CR1_UDIS 0x0002U
8438 #define TIM_CR1_URS 0x0004U
8439 #define TIM_CR1_OPM 0x0008U
8440 #define TIM_CR1_DIR 0x0010U
8442 #define TIM_CR1_CMS 0x0060U
8443 #define TIM_CR1_CMS_0 0x0020U
8444 #define TIM_CR1_CMS_1 0x0040U
8446 #define TIM_CR1_ARPE 0x0080U
8448 #define TIM_CR1_CKD 0x0300U
8449 #define TIM_CR1_CKD_0 0x0100U
8450 #define TIM_CR1_CKD_1 0x0200U
8452 /******************* Bit definition for TIM_CR2 register ********************/
8453 #define TIM_CR2_CCPC 0x0001U
8454 #define TIM_CR2_CCUS 0x0004U
8455 #define TIM_CR2_CCDS 0x0008U
8457 #define TIM_CR2_MMS 0x0070U
8458 #define TIM_CR2_MMS_0 0x0010U
8459 #define TIM_CR2_MMS_1 0x0020U
8460 #define TIM_CR2_MMS_2 0x0040U
8462 #define TIM_CR2_TI1S 0x0080U
8463 #define TIM_CR2_OIS1 0x0100U
8464 #define TIM_CR2_OIS1N 0x0200U
8465 #define TIM_CR2_OIS2 0x0400U
8466 #define TIM_CR2_OIS2N 0x0800U
8467 #define TIM_CR2_OIS3 0x1000U
8468 #define TIM_CR2_OIS3N 0x2000U
8469 #define TIM_CR2_OIS4 0x4000U
8471 /******************* Bit definition for TIM_SMCR register *******************/
8472 #define TIM_SMCR_SMS 0x0007U
8473 #define TIM_SMCR_SMS_0 0x0001U
8474 #define TIM_SMCR_SMS_1 0x0002U
8475 #define TIM_SMCR_SMS_2 0x0004U
8477 #define TIM_SMCR_TS 0x0070U
8478 #define TIM_SMCR_TS_0 0x0010U
8479 #define TIM_SMCR_TS_1 0x0020U
8480 #define TIM_SMCR_TS_2 0x0040U
8482 #define TIM_SMCR_MSM 0x0080U
8484 #define TIM_SMCR_ETF 0x0F00U
8485 #define TIM_SMCR_ETF_0 0x0100U
8486 #define TIM_SMCR_ETF_1 0x0200U
8487 #define TIM_SMCR_ETF_2 0x0400U
8488 #define TIM_SMCR_ETF_3 0x0800U
8490 #define TIM_SMCR_ETPS 0x3000U
8491 #define TIM_SMCR_ETPS_0 0x1000U
8492 #define TIM_SMCR_ETPS_1 0x2000U
8494 #define TIM_SMCR_ECE 0x4000U
8495 #define TIM_SMCR_ETP 0x8000U
8497 /******************* Bit definition for TIM_DIER register *******************/
8498 #define TIM_DIER_UIE 0x0001U
8499 #define TIM_DIER_CC1IE 0x0002U
8500 #define TIM_DIER_CC2IE 0x0004U
8501 #define TIM_DIER_CC3IE 0x0008U
8502 #define TIM_DIER_CC4IE 0x0010U
8503 #define TIM_DIER_COMIE 0x0020U
8504 #define TIM_DIER_TIE 0x0040U
8505 #define TIM_DIER_BIE 0x0080U
8506 #define TIM_DIER_UDE 0x0100U
8507 #define TIM_DIER_CC1DE 0x0200U
8508 #define TIM_DIER_CC2DE 0x0400U
8509 #define TIM_DIER_CC3DE 0x0800U
8510 #define TIM_DIER_CC4DE 0x1000U
8511 #define TIM_DIER_COMDE 0x2000U
8512 #define TIM_DIER_TDE 0x4000U
8514 /******************** Bit definition for TIM_SR register ********************/
8515 #define TIM_SR_UIF 0x0001U
8516 #define TIM_SR_CC1IF 0x0002U
8517 #define TIM_SR_CC2IF 0x0004U
8518 #define TIM_SR_CC3IF 0x0008U
8519 #define TIM_SR_CC4IF 0x0010U
8520 #define TIM_SR_COMIF 0x0020U
8521 #define TIM_SR_TIF 0x0040U
8522 #define TIM_SR_BIF 0x0080U
8523 #define TIM_SR_CC1OF 0x0200U
8524 #define TIM_SR_CC2OF 0x0400U
8525 #define TIM_SR_CC3OF 0x0800U
8526 #define TIM_SR_CC4OF 0x1000U
8528 /******************* Bit definition for TIM_EGR register ********************/
8529 #define TIM_EGR_UG 0x01U
8530 #define TIM_EGR_CC1G 0x02U
8531 #define TIM_EGR_CC2G 0x04U
8532 #define TIM_EGR_CC3G 0x08U
8533 #define TIM_EGR_CC4G 0x10U
8534 #define TIM_EGR_COMG 0x20U
8535 #define TIM_EGR_TG 0x40U
8536 #define TIM_EGR_BG 0x80U
8538 /****************** Bit definition for TIM_CCMR1 register *******************/
8539 #define TIM_CCMR1_CC1S 0x0003U
8540 #define TIM_CCMR1_CC1S_0 0x0001U
8541 #define TIM_CCMR1_CC1S_1 0x0002U
8543 #define TIM_CCMR1_OC1FE 0x0004U
8544 #define TIM_CCMR1_OC1PE 0x0008U
8546 #define TIM_CCMR1_OC1M 0x0070U
8547 #define TIM_CCMR1_OC1M_0 0x0010U
8548 #define TIM_CCMR1_OC1M_1 0x0020U
8549 #define TIM_CCMR1_OC1M_2 0x0040U
8551 #define TIM_CCMR1_OC1CE 0x0080U
8553 #define TIM_CCMR1_CC2S 0x0300U
8554 #define TIM_CCMR1_CC2S_0 0x0100U
8555 #define TIM_CCMR1_CC2S_1 0x0200U
8557 #define TIM_CCMR1_OC2FE 0x0400U
8558 #define TIM_CCMR1_OC2PE 0x0800U
8560 #define TIM_CCMR1_OC2M 0x7000U
8561 #define TIM_CCMR1_OC2M_0 0x1000U
8562 #define TIM_CCMR1_OC2M_1 0x2000U
8563 #define TIM_CCMR1_OC2M_2 0x4000U
8565 #define TIM_CCMR1_OC2CE 0x8000U
8567 /*----------------------------------------------------------------------------*/
8568 
8569 #define TIM_CCMR1_IC1PSC 0x000CU
8570 #define TIM_CCMR1_IC1PSC_0 0x0004U
8571 #define TIM_CCMR1_IC1PSC_1 0x0008U
8573 #define TIM_CCMR1_IC1F 0x00F0U
8574 #define TIM_CCMR1_IC1F_0 0x0010U
8575 #define TIM_CCMR1_IC1F_1 0x0020U
8576 #define TIM_CCMR1_IC1F_2 0x0040U
8577 #define TIM_CCMR1_IC1F_3 0x0080U
8579 #define TIM_CCMR1_IC2PSC 0x0C00U
8580 #define TIM_CCMR1_IC2PSC_0 0x0400U
8581 #define TIM_CCMR1_IC2PSC_1 0x0800U
8583 #define TIM_CCMR1_IC2F 0xF000U
8584 #define TIM_CCMR1_IC2F_0 0x1000U
8585 #define TIM_CCMR1_IC2F_1 0x2000U
8586 #define TIM_CCMR1_IC2F_2 0x4000U
8587 #define TIM_CCMR1_IC2F_3 0x8000U
8589 /****************** Bit definition for TIM_CCMR2 register *******************/
8590 #define TIM_CCMR2_CC3S 0x0003U
8591 #define TIM_CCMR2_CC3S_0 0x0001U
8592 #define TIM_CCMR2_CC3S_1 0x0002U
8594 #define TIM_CCMR2_OC3FE 0x0004U
8595 #define TIM_CCMR2_OC3PE 0x0008U
8597 #define TIM_CCMR2_OC3M 0x0070U
8598 #define TIM_CCMR2_OC3M_0 0x0010U
8599 #define TIM_CCMR2_OC3M_1 0x0020U
8600 #define TIM_CCMR2_OC3M_2 0x0040U
8602 #define TIM_CCMR2_OC3CE 0x0080U
8604 #define TIM_CCMR2_CC4S 0x0300U
8605 #define TIM_CCMR2_CC4S_0 0x0100U
8606 #define TIM_CCMR2_CC4S_1 0x0200U
8608 #define TIM_CCMR2_OC4FE 0x0400U
8609 #define TIM_CCMR2_OC4PE 0x0800U
8611 #define TIM_CCMR2_OC4M 0x7000U
8612 #define TIM_CCMR2_OC4M_0 0x1000U
8613 #define TIM_CCMR2_OC4M_1 0x2000U
8614 #define TIM_CCMR2_OC4M_2 0x4000U
8616 #define TIM_CCMR2_OC4CE 0x8000U
8618 /*----------------------------------------------------------------------------*/
8619 
8620 #define TIM_CCMR2_IC3PSC 0x000CU
8621 #define TIM_CCMR2_IC3PSC_0 0x0004U
8622 #define TIM_CCMR2_IC3PSC_1 0x0008U
8624 #define TIM_CCMR2_IC3F 0x00F0U
8625 #define TIM_CCMR2_IC3F_0 0x0010U
8626 #define TIM_CCMR2_IC3F_1 0x0020U
8627 #define TIM_CCMR2_IC3F_2 0x0040U
8628 #define TIM_CCMR2_IC3F_3 0x0080U
8630 #define TIM_CCMR2_IC4PSC 0x0C00U
8631 #define TIM_CCMR2_IC4PSC_0 0x0400U
8632 #define TIM_CCMR2_IC4PSC_1 0x0800U
8634 #define TIM_CCMR2_IC4F 0xF000U
8635 #define TIM_CCMR2_IC4F_0 0x1000U
8636 #define TIM_CCMR2_IC4F_1 0x2000U
8637 #define TIM_CCMR2_IC4F_2 0x4000U
8638 #define TIM_CCMR2_IC4F_3 0x8000U
8640 /******************* Bit definition for TIM_CCER register *******************/
8641 #define TIM_CCER_CC1E 0x0001U
8642 #define TIM_CCER_CC1P 0x0002U
8643 #define TIM_CCER_CC1NE 0x0004U
8644 #define TIM_CCER_CC1NP 0x0008U
8645 #define TIM_CCER_CC2E 0x0010U
8646 #define TIM_CCER_CC2P 0x0020U
8647 #define TIM_CCER_CC2NE 0x0040U
8648 #define TIM_CCER_CC2NP 0x0080U
8649 #define TIM_CCER_CC3E 0x0100U
8650 #define TIM_CCER_CC3P 0x0200U
8651 #define TIM_CCER_CC3NE 0x0400U
8652 #define TIM_CCER_CC3NP 0x0800U
8653 #define TIM_CCER_CC4E 0x1000U
8654 #define TIM_CCER_CC4P 0x2000U
8655 #define TIM_CCER_CC4NP 0x8000U
8657 /******************* Bit definition for TIM_CNT register ********************/
8658 #define TIM_CNT_CNT 0xFFFFU
8660 /******************* Bit definition for TIM_PSC register ********************/
8661 #define TIM_PSC_PSC 0xFFFFU
8663 /******************* Bit definition for TIM_ARR register ********************/
8664 #define TIM_ARR_ARR 0xFFFFU
8666 /******************* Bit definition for TIM_RCR register ********************/
8667 #define TIM_RCR_REP 0xFFU
8669 /******************* Bit definition for TIM_CCR1 register *******************/
8670 #define TIM_CCR1_CCR1 0xFFFFU
8672 /******************* Bit definition for TIM_CCR2 register *******************/
8673 #define TIM_CCR2_CCR2 0xFFFFU
8675 /******************* Bit definition for TIM_CCR3 register *******************/
8676 #define TIM_CCR3_CCR3 0xFFFFU
8678 /******************* Bit definition for TIM_CCR4 register *******************/
8679 #define TIM_CCR4_CCR4 0xFFFFU
8681 /******************* Bit definition for TIM_BDTR register *******************/
8682 #define TIM_BDTR_DTG 0x00FFU
8683 #define TIM_BDTR_DTG_0 0x0001U
8684 #define TIM_BDTR_DTG_1 0x0002U
8685 #define TIM_BDTR_DTG_2 0x0004U
8686 #define TIM_BDTR_DTG_3 0x0008U
8687 #define TIM_BDTR_DTG_4 0x0010U
8688 #define TIM_BDTR_DTG_5 0x0020U
8689 #define TIM_BDTR_DTG_6 0x0040U
8690 #define TIM_BDTR_DTG_7 0x0080U
8692 #define TIM_BDTR_LOCK 0x0300U
8693 #define TIM_BDTR_LOCK_0 0x0100U
8694 #define TIM_BDTR_LOCK_1 0x0200U
8696 #define TIM_BDTR_OSSI 0x0400U
8697 #define TIM_BDTR_OSSR 0x0800U
8698 #define TIM_BDTR_BKE 0x1000U
8699 #define TIM_BDTR_BKP 0x2000U
8700 #define TIM_BDTR_AOE 0x4000U
8701 #define TIM_BDTR_MOE 0x8000U
8703 /******************* Bit definition for TIM_DCR register ********************/
8704 #define TIM_DCR_DBA 0x001FU
8705 #define TIM_DCR_DBA_0 0x0001U
8706 #define TIM_DCR_DBA_1 0x0002U
8707 #define TIM_DCR_DBA_2 0x0004U
8708 #define TIM_DCR_DBA_3 0x0008U
8709 #define TIM_DCR_DBA_4 0x0010U
8711 #define TIM_DCR_DBL 0x1F00U
8712 #define TIM_DCR_DBL_0 0x0100U
8713 #define TIM_DCR_DBL_1 0x0200U
8714 #define TIM_DCR_DBL_2 0x0400U
8715 #define TIM_DCR_DBL_3 0x0800U
8716 #define TIM_DCR_DBL_4 0x1000U
8718 /******************* Bit definition for TIM_DMAR register *******************/
8719 #define TIM_DMAR_DMAB 0xFFFFU
8721 /******************* Bit definition for TIM_OR register *********************/
8722 #define TIM_OR_TI4_RMP 0x00C0U
8723 #define TIM_OR_TI4_RMP_0 0x0040U
8724 #define TIM_OR_TI4_RMP_1 0x0080U
8725 #define TIM_OR_ITR1_RMP 0x0C00U
8726 #define TIM_OR_ITR1_RMP_0 0x0400U
8727 #define TIM_OR_ITR1_RMP_1 0x0800U
8730 /******************************************************************************/
8731 /* */
8732 /* Universal Synchronous Asynchronous Receiver Transmitter */
8733 /* */
8734 /******************************************************************************/
8735 /******************* Bit definition for USART_SR register *******************/
8736 #define USART_SR_PE 0x0001U
8737 #define USART_SR_FE 0x0002U
8738 #define USART_SR_NE 0x0004U
8739 #define USART_SR_ORE 0x0008U
8740 #define USART_SR_IDLE 0x0010U
8741 #define USART_SR_RXNE 0x0020U
8742 #define USART_SR_TC 0x0040U
8743 #define USART_SR_TXE 0x0080U
8744 #define USART_SR_LBD 0x0100U
8745 #define USART_SR_CTS 0x0200U
8747 /******************* Bit definition for USART_DR register *******************/
8748 #define USART_DR_DR 0x01FFU
8750 /****************** Bit definition for USART_BRR register *******************/
8751 #define USART_BRR_DIV_Fraction 0x000FU
8752 #define USART_BRR_DIV_Mantissa 0xFFF0U
8754 /****************** Bit definition for USART_CR1 register *******************/
8755 #define USART_CR1_SBK 0x0001U
8756 #define USART_CR1_RWU 0x0002U
8757 #define USART_CR1_RE 0x0004U
8758 #define USART_CR1_TE 0x0008U
8759 #define USART_CR1_IDLEIE 0x0010U
8760 #define USART_CR1_RXNEIE 0x0020U
8761 #define USART_CR1_TCIE 0x0040U
8762 #define USART_CR1_TXEIE 0x0080U
8763 #define USART_CR1_PEIE 0x0100U
8764 #define USART_CR1_PS 0x0200U
8765 #define USART_CR1_PCE 0x0400U
8766 #define USART_CR1_WAKE 0x0800U
8767 #define USART_CR1_M 0x1000U
8768 #define USART_CR1_UE 0x2000U
8769 #define USART_CR1_OVER8 0x8000U
8771 /****************** Bit definition for USART_CR2 register *******************/
8772 #define USART_CR2_ADD 0x000FU
8773 #define USART_CR2_LBDL 0x0020U
8774 #define USART_CR2_LBDIE 0x0040U
8775 #define USART_CR2_LBCL 0x0100U
8776 #define USART_CR2_CPHA 0x0200U
8777 #define USART_CR2_CPOL 0x0400U
8778 #define USART_CR2_CLKEN 0x0800U
8780 #define USART_CR2_STOP 0x3000U
8781 #define USART_CR2_STOP_0 0x1000U
8782 #define USART_CR2_STOP_1 0x2000U
8784 #define USART_CR2_LINEN 0x4000U
8786 /****************** Bit definition for USART_CR3 register *******************/
8787 #define USART_CR3_EIE 0x0001U
8788 #define USART_CR3_IREN 0x0002U
8789 #define USART_CR3_IRLP 0x0004U
8790 #define USART_CR3_HDSEL 0x0008U
8791 #define USART_CR3_NACK 0x0010U
8792 #define USART_CR3_SCEN 0x0020U
8793 #define USART_CR3_DMAR 0x0040U
8794 #define USART_CR3_DMAT 0x0080U
8795 #define USART_CR3_RTSE 0x0100U
8796 #define USART_CR3_CTSE 0x0200U
8797 #define USART_CR3_CTSIE 0x0400U
8798 #define USART_CR3_ONEBIT 0x0800U
8800 /****************** Bit definition for USART_GTPR register ******************/
8801 #define USART_GTPR_PSC 0x00FFU
8802 #define USART_GTPR_PSC_0 0x0001U
8803 #define USART_GTPR_PSC_1 0x0002U
8804 #define USART_GTPR_PSC_2 0x0004U
8805 #define USART_GTPR_PSC_3 0x0008U
8806 #define USART_GTPR_PSC_4 0x0010U
8807 #define USART_GTPR_PSC_5 0x0020U
8808 #define USART_GTPR_PSC_6 0x0040U
8809 #define USART_GTPR_PSC_7 0x0080U
8811 #define USART_GTPR_GT 0xFF00U
8813 /******************************************************************************/
8814 /* */
8815 /* Window WATCHDOG */
8816 /* */
8817 /******************************************************************************/
8818 /******************* Bit definition for WWDG_CR register ********************/
8819 #define WWDG_CR_T 0x7FU
8820 #define WWDG_CR_T_0 0x01U
8821 #define WWDG_CR_T_1 0x02U
8822 #define WWDG_CR_T_2 0x04U
8823 #define WWDG_CR_T_3 0x08U
8824 #define WWDG_CR_T_4 0x10U
8825 #define WWDG_CR_T_5 0x20U
8826 #define WWDG_CR_T_6 0x40U
8827 /* Legacy defines */
8828 #define WWDG_CR_T0 WWDG_CR_T_0
8829 #define WWDG_CR_T1 WWDG_CR_T_1
8830 #define WWDG_CR_T2 WWDG_CR_T_2
8831 #define WWDG_CR_T3 WWDG_CR_T_3
8832 #define WWDG_CR_T4 WWDG_CR_T_4
8833 #define WWDG_CR_T5 WWDG_CR_T_5
8834 #define WWDG_CR_T6 WWDG_CR_T_6
8835 
8836 #define WWDG_CR_WDGA 0x80U
8838 /******************* Bit definition for WWDG_CFR register *******************/
8839 #define WWDG_CFR_W 0x007FU
8840 #define WWDG_CFR_W_0 0x0001U
8841 #define WWDG_CFR_W_1 0x0002U
8842 #define WWDG_CFR_W_2 0x0004U
8843 #define WWDG_CFR_W_3 0x0008U
8844 #define WWDG_CFR_W_4 0x0010U
8845 #define WWDG_CFR_W_5 0x0020U
8846 #define WWDG_CFR_W_6 0x0040U
8847 /* Legacy defines */
8848 #define WWDG_CFR_W0 WWDG_CFR_W_0
8849 #define WWDG_CFR_W1 WWDG_CFR_W_1
8850 #define WWDG_CFR_W2 WWDG_CFR_W_2
8851 #define WWDG_CFR_W3 WWDG_CFR_W_3
8852 #define WWDG_CFR_W4 WWDG_CFR_W_4
8853 #define WWDG_CFR_W5 WWDG_CFR_W_5
8854 #define WWDG_CFR_W6 WWDG_CFR_W_6
8855 
8856 #define WWDG_CFR_WDGTB 0x0180U
8857 #define WWDG_CFR_WDGTB_0 0x0080U
8858 #define WWDG_CFR_WDGTB_1 0x0100U
8859 /* Legacy defines */
8860 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
8861 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
8862 
8863 #define WWDG_CFR_EWI 0x0200U
8865 /******************* Bit definition for WWDG_SR register ********************/
8866 #define WWDG_SR_EWIF 0x01U
8869 /******************************************************************************/
8870 /* */
8871 /* DBG */
8872 /* */
8873 /******************************************************************************/
8874 /******************** Bit definition for DBGMCU_IDCODE register *************/
8875 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
8876 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
8877 
8878 /******************** Bit definition for DBGMCU_CR register *****************/
8879 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
8880 #define DBGMCU_CR_DBG_STOP 0x00000002U
8881 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
8882 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
8883 
8884 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
8885 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U
8886 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U
8888 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
8889 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
8890 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
8891 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
8892 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
8893 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
8894 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
8895 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
8896 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
8897 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
8898 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
8899 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
8900 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
8901 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
8902 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
8903 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
8904 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
8905 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
8906 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
8907 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
8908 
8909 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
8910 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
8911 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
8912 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
8913 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
8914 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
8915 
8916 /******************************************************************************/
8917 /* */
8918 /* Ethernet MAC Registers bits definitions */
8919 /* */
8920 /******************************************************************************/
8921 /* Bit definition for Ethernet MAC Control Register register */
8922 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
8923 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
8924 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
8925 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
8926  #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
8927  #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
8928  #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
8929  #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
8930  #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
8931  #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
8932  #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
8933 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
8934 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
8935 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
8936 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
8937 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
8938 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
8939 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
8940 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
8941 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
8942  a transmission attempt during retries after a collision: 0 =< r <2^k */
8943  #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
8944  #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
8945  #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
8946  #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
8947 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
8948 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
8949 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
8950 
8951 /* Bit definition for Ethernet MAC Frame Filter Register */
8952 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
8953 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
8954 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
8955 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
8956 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
8957  #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
8958  #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
8959  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
8960 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
8961 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
8962 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
8963 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
8964 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
8965 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
8966 
8967 /* Bit definition for Ethernet MAC Hash Table High Register */
8968 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
8969 
8970 /* Bit definition for Ethernet MAC Hash Table Low Register */
8971 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
8972 
8973 /* Bit definition for Ethernet MAC MII Address Register */
8974 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
8975 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
8976 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
8977  #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
8978  #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
8979  #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
8980  #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
8981  #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
8982 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
8983 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
8984 
8985 /* Bit definition for Ethernet MAC MII Data Register */
8986 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
8987 
8988 /* Bit definition for Ethernet MAC Flow Control Register */
8989 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
8990 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
8991 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
8992  #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
8993  #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
8994  #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
8995  #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
8996 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
8997 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
8998 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
8999 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
9000 
9001 /* Bit definition for Ethernet MAC VLAN Tag Register */
9002 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
9003 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
9004 
9005 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
9006 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
9007 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
9008  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
9009 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
9010  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
9011  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
9012  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
9013  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
9014  RSVD - Filter1 Command - RSVD - Filter0 Command
9015  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
9016  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
9017  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
9018 
9019 /* Bit definition for Ethernet MAC PMT Control and Status Register */
9020 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
9021 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
9022 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
9023 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
9024 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
9025 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
9026 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
9027 
9028 /* Bit definition for Ethernet MAC Status Register */
9029 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
9030 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
9031 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
9032 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
9033 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
9034 
9035 /* Bit definition for Ethernet MAC Interrupt Mask Register */
9036 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
9037 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
9038 
9039 /* Bit definition for Ethernet MAC Address0 High Register */
9040 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
9041 
9042 /* Bit definition for Ethernet MAC Address0 Low Register */
9043 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
9044 
9045 /* Bit definition for Ethernet MAC Address1 High Register */
9046 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
9047 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
9048 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
9049  #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
9050  #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
9051  #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
9052  #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
9053  #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
9054  #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
9055 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
9056 
9057 /* Bit definition for Ethernet MAC Address1 Low Register */
9058 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
9059 
9060 /* Bit definition for Ethernet MAC Address2 High Register */
9061 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
9062 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
9063 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
9064  #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
9065  #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
9066  #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
9067  #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
9068  #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
9069  #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
9070 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
9071 
9072 /* Bit definition for Ethernet MAC Address2 Low Register */
9073 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
9074 
9075 /* Bit definition for Ethernet MAC Address3 High Register */
9076 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
9077 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
9078 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
9079  #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
9080  #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
9081  #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
9082  #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
9083  #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
9084  #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
9085 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
9086 
9087 /* Bit definition for Ethernet MAC Address3 Low Register */
9088 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
9089 
9090 /******************************************************************************/
9091 /* Ethernet MMC Registers bits definition */
9092 /******************************************************************************/
9093 
9094 /* Bit definition for Ethernet MMC Contol Register */
9095 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
9096 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
9097 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
9098 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
9099 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
9100 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
9101 
9102 /* Bit definition for Ethernet MMC Receive Interrupt Register */
9103 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
9104 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
9105 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
9106 
9107 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
9108 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
9109 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
9110 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
9111 
9112 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
9113 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
9114 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
9115 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
9116 
9117 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
9118 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
9119 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
9120 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
9121 
9122 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
9123 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
9124 
9125 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
9126 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
9127 
9128 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
9129 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
9130 
9131 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
9132 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
9133 
9134 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
9135 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
9136 
9137 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
9138 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
9139 
9140 /******************************************************************************/
9141 /* Ethernet PTP Registers bits definition */
9142 /******************************************************************************/
9143 
9144 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
9145 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
9146 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
9147 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
9148 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
9149 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
9150 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
9151 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
9152 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
9153 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
9154 
9155 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
9156 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
9157 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
9158 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
9159 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
9160 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
9161 
9162 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
9163 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
9164 
9165 /* Bit definition for Ethernet PTP Time Stamp High Register */
9166 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
9167 
9168 /* Bit definition for Ethernet PTP Time Stamp Low Register */
9169 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
9170 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
9171 
9172 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
9173 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
9174 
9175 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
9176 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
9177 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
9178 
9179 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
9180 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
9181 
9182 /* Bit definition for Ethernet PTP Target Time High Register */
9183 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
9184 
9185 /* Bit definition for Ethernet PTP Target Time Low Register */
9186 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
9187 
9188 /* Bit definition for Ethernet PTP Time Stamp Status Register */
9189 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
9190 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
9191 
9192 /******************************************************************************/
9193 /* Ethernet DMA Registers bits definition */
9194 /******************************************************************************/
9195 
9196 /* Bit definition for Ethernet DMA Bus Mode Register */
9197 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
9198 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
9199 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
9200 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
9201  #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
9202  #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
9203  #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
9204  #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
9205  #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
9206  #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
9207  #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
9208  #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
9209  #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
9210  #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
9211  #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
9212  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
9213 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
9214 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
9215  #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
9216  #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
9217  #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
9218  #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
9219 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
9220  #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
9221  #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
9222  #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
9223  #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
9224  #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
9225  #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
9226  #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
9227  #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
9228  #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
9229  #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
9230  #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
9231  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
9232 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
9233 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
9234 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
9235 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
9236 
9237 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
9238 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
9239 
9240 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
9241 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
9242 
9243 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
9244 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
9245 
9246 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
9247 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
9248 
9249 /* Bit definition for Ethernet DMA Status Register */
9250 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
9251 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
9252 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
9253 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
9254  /* combination with EBS[2:0] for GetFlagStatus function */
9255  #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
9256  #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
9257  #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
9258 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
9259  #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
9260  #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
9261  #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
9262  #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
9263  #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
9264  #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
9265 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
9266  #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
9267  #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
9268  #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
9269  #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
9270  #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
9271  #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
9272 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
9273 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
9274 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
9275 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
9276 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
9277 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
9278 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
9279 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
9280 #define ETH_DMASR_RS 0x00000040U /* Receive status */
9281 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
9282 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
9283 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
9284 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
9285 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
9286 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
9287 
9288 /* Bit definition for Ethernet DMA Operation Mode Register */
9289 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
9290 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
9291 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
9292 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
9293 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
9294 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
9295  #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
9296  #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
9297  #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
9298  #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
9299  #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
9300  #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
9301  #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
9302  #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
9303 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
9304 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
9305 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
9306 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
9307  #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
9308  #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
9309  #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
9310  #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
9311 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
9312 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
9313 
9314 /* Bit definition for Ethernet DMA Interrupt Enable Register */
9315 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
9316 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
9317 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
9318 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
9319 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
9320 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
9321 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
9322 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
9323 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
9324 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
9325 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
9326 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
9327 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
9328 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
9329 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
9330 
9331 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
9332 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
9333 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
9334 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
9335 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
9336 
9337 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
9338 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
9339 
9340 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
9341 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
9342 
9343 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
9344 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
9345 
9346 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
9347 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
9348 
9349 /******************************************************************************/
9350 /* */
9351 /* USB_OTG */
9352 /* */
9353 /******************************************************************************/
9354 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
9355 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U
9356 #define USB_OTG_GOTGCTL_SRQ 0x00000002U
9357 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U
9358 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U
9359 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U
9360 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U
9361 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U
9362 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U
9363 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U
9364 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U
9365 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U
9366 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U
9367 #define USB_OTG_GOTGCTL_EHEN 0x00001000U
9368 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U
9369 #define USB_OTG_GOTGCTL_DBCT 0x00020000U
9370 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U
9371 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U
9372 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U
9374 /******************** Bit definition forUSB_OTG_HCFG register ********************/
9375 
9376 #define USB_OTG_HCFG_FSLSPCS 0x00000003U
9377 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U
9378 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U
9379 #define USB_OTG_HCFG_FSLSS 0x00000004U
9381 /******************** Bit definition forUSB_OTG_DCFG register ********************/
9382 
9383 #define USB_OTG_DCFG_DSPD 0x00000003U
9384 #define USB_OTG_DCFG_DSPD_0 0x00000001U
9385 #define USB_OTG_DCFG_DSPD_1 0x00000002U
9386 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U
9388 #define USB_OTG_DCFG_DAD 0x000007F0U
9389 #define USB_OTG_DCFG_DAD_0 0x00000010U
9390 #define USB_OTG_DCFG_DAD_1 0x00000020U
9391 #define USB_OTG_DCFG_DAD_2 0x00000040U
9392 #define USB_OTG_DCFG_DAD_3 0x00000080U
9393 #define USB_OTG_DCFG_DAD_4 0x00000100U
9394 #define USB_OTG_DCFG_DAD_5 0x00000200U
9395 #define USB_OTG_DCFG_DAD_6 0x00000400U
9397 #define USB_OTG_DCFG_PFIVL 0x00001800U
9398 #define USB_OTG_DCFG_PFIVL_0 0x00000800U
9399 #define USB_OTG_DCFG_PFIVL_1 0x00001000U
9401 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U
9402 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U
9403 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U
9405 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
9406 #define USB_OTG_PCGCR_STPPCLK 0x00000001U
9407 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U
9408 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U
9410 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
9411 #define USB_OTG_GOTGINT_SEDET 0x00000004U
9412 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U
9413 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U
9414 #define USB_OTG_GOTGINT_HNGDET 0x00020000U
9415 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U
9416 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U
9417 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U
9419 /******************** Bit definition forUSB_OTG_DCTL register ********************/
9420 #define USB_OTG_DCTL_RWUSIG 0x00000001U
9421 #define USB_OTG_DCTL_SDIS 0x00000002U
9422 #define USB_OTG_DCTL_GINSTS 0x00000004U
9423 #define USB_OTG_DCTL_GONSTS 0x00000008U
9425 #define USB_OTG_DCTL_TCTL 0x00000070U
9426 #define USB_OTG_DCTL_TCTL_0 0x00000010U
9427 #define USB_OTG_DCTL_TCTL_1 0x00000020U
9428 #define USB_OTG_DCTL_TCTL_2 0x00000040U
9429 #define USB_OTG_DCTL_SGINAK 0x00000080U
9430 #define USB_OTG_DCTL_CGINAK 0x00000100U
9431 #define USB_OTG_DCTL_SGONAK 0x00000200U
9432 #define USB_OTG_DCTL_CGONAK 0x00000400U
9433 #define USB_OTG_DCTL_POPRGDNE 0x00000800U
9435 /******************** Bit definition forUSB_OTG_HFIR register ********************/
9436 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU
9438 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
9439 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU
9440 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U
9442 /******************** Bit definition forUSB_OTG_DSTS register ********************/
9443 #define USB_OTG_DSTS_SUSPSTS 0x00000001U
9445 #define USB_OTG_DSTS_ENUMSPD 0x00000006U
9446 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U
9447 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U
9448 #define USB_OTG_DSTS_EERR 0x00000008U
9449 #define USB_OTG_DSTS_FNSOF 0x003FFF00U
9451 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
9452 #define USB_OTG_GAHBCFG_GINT 0x00000001U
9453 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU
9454 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U
9455 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U
9456 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U
9457 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U
9458 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U
9459 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U
9460 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U
9462 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
9463 
9464 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U
9465 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U
9466 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U
9467 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U
9468 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U
9469 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U
9470 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U
9471 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U
9472 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U
9473 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U
9474 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U
9475 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U
9476 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U
9477 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U
9478 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U
9479 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U
9480 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U
9481 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U
9482 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U
9483 #define USB_OTG_GUSBCFG_PCCI 0x00800000U
9484 #define USB_OTG_GUSBCFG_PTCI 0x01000000U
9485 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U
9486 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U
9487 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U
9488 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U
9490 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
9491 #define USB_OTG_GRSTCTL_CSRST 0x00000001U
9492 #define USB_OTG_GRSTCTL_HSRST 0x00000002U
9493 #define USB_OTG_GRSTCTL_FCRST 0x00000004U
9494 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U
9495 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U
9496 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U
9497 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U
9498 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U
9499 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U
9500 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U
9501 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U
9502 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U
9503 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U
9505 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
9506 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U
9507 #define USB_OTG_DIEPMSK_EPDM 0x00000002U
9508 #define USB_OTG_DIEPMSK_TOM 0x00000008U
9509 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U
9510 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U
9511 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U
9512 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U
9513 #define USB_OTG_DIEPMSK_BIM 0x00000200U
9515 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
9516 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU
9517 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U
9518 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U
9519 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U
9520 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U
9521 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U
9522 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U
9523 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U
9524 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U
9525 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U
9527 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U
9528 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U
9529 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U
9530 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U
9531 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U
9532 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U
9533 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U
9534 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U
9535 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U
9537 /******************** Bit definition forUSB_OTG_HAINT register ********************/
9538 #define USB_OTG_HAINT_HAINT 0x0000FFFFU
9540 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
9541 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U
9542 #define USB_OTG_DOEPMSK_EPDM 0x00000002U
9543 #define USB_OTG_DOEPMSK_STUPM 0x00000008U
9544 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U
9545 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U
9546 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U
9547 #define USB_OTG_DOEPMSK_OPEM 0x00000100U
9548 #define USB_OTG_DOEPMSK_BOIM 0x00000200U
9550 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
9551 #define USB_OTG_GINTSTS_CMOD 0x00000001U
9552 #define USB_OTG_GINTSTS_MMIS 0x00000002U
9553 #define USB_OTG_GINTSTS_OTGINT 0x00000004U
9554 #define USB_OTG_GINTSTS_SOF 0x00000008U
9555 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U
9556 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U
9557 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U
9558 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U
9559 #define USB_OTG_GINTSTS_ESUSP 0x00000400U
9560 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U
9561 #define USB_OTG_GINTSTS_USBRST 0x00001000U
9562 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U
9563 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U
9564 #define USB_OTG_GINTSTS_EOPF 0x00008000U
9565 #define USB_OTG_GINTSTS_IEPINT 0x00040000U
9566 #define USB_OTG_GINTSTS_OEPINT 0x00080000U
9567 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U
9568 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U
9569 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U
9570 #define USB_OTG_GINTSTS_RSTDET 0x00800000U
9571 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U
9572 #define USB_OTG_GINTSTS_HCINT 0x02000000U
9573 #define USB_OTG_GINTSTS_PTXFE 0x04000000U
9574 #define USB_OTG_GINTSTS_LPMINT 0x08000000U
9575 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U
9576 #define USB_OTG_GINTSTS_DISCINT 0x20000000U
9577 #define USB_OTG_GINTSTS_SRQINT 0x40000000U
9578 #define USB_OTG_GINTSTS_WKUINT 0x80000000U
9580 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
9581 #define USB_OTG_GINTMSK_MMISM 0x00000002U
9582 #define USB_OTG_GINTMSK_OTGINT 0x00000004U
9583 #define USB_OTG_GINTMSK_SOFM 0x00000008U
9584 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U
9585 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U
9586 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U
9587 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U
9588 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U
9589 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U
9590 #define USB_OTG_GINTMSK_USBRST 0x00001000U
9591 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U
9592 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U
9593 #define USB_OTG_GINTMSK_EOPFM 0x00008000U
9594 #define USB_OTG_GINTMSK_EPMISM 0x00020000U
9595 #define USB_OTG_GINTMSK_IEPINT 0x00040000U
9596 #define USB_OTG_GINTMSK_OEPINT 0x00080000U
9597 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U
9598 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U
9599 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U
9600 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U
9601 #define USB_OTG_GINTMSK_PRTIM 0x01000000U
9602 #define USB_OTG_GINTMSK_HCIM 0x02000000U
9603 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U
9604 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U
9605 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U
9606 #define USB_OTG_GINTMSK_DISCINT 0x20000000U
9607 #define USB_OTG_GINTMSK_SRQIM 0x40000000U
9608 #define USB_OTG_GINTMSK_WUIM 0x80000000U
9610 /******************** Bit definition forUSB_OTG_DAINT register ********************/
9611 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU
9612 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U
9614 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
9615 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU
9617 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
9618 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU
9619 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U
9620 #define USB_OTG_GRXSTSP_DPID 0x00018000U
9621 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U
9623 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
9624 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU
9625 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U
9627 /******************** Bit definition for OTG register ********************/
9628 
9629 #define USB_OTG_CHNUM 0x0000000FU
9630 #define USB_OTG_CHNUM_0 0x00000001U
9631 #define USB_OTG_CHNUM_1 0x00000002U
9632 #define USB_OTG_CHNUM_2 0x00000004U
9633 #define USB_OTG_CHNUM_3 0x00000008U
9634 #define USB_OTG_BCNT 0x00007FF0U
9636 #define USB_OTG_DPID 0x00018000U
9637 #define USB_OTG_DPID_0 0x00008000U
9638 #define USB_OTG_DPID_1 0x00010000U
9640 #define USB_OTG_PKTSTS 0x001E0000U
9641 #define USB_OTG_PKTSTS_0 0x00020000U
9642 #define USB_OTG_PKTSTS_1 0x00040000U
9643 #define USB_OTG_PKTSTS_2 0x00080000U
9644 #define USB_OTG_PKTSTS_3 0x00100000U
9646 #define USB_OTG_EPNUM 0x0000000FU
9647 #define USB_OTG_EPNUM_0 0x00000001U
9648 #define USB_OTG_EPNUM_1 0x00000002U
9649 #define USB_OTG_EPNUM_2 0x00000004U
9650 #define USB_OTG_EPNUM_3 0x00000008U
9652 #define USB_OTG_FRMNUM 0x01E00000U
9653 #define USB_OTG_FRMNUM_0 0x00200000U
9654 #define USB_OTG_FRMNUM_1 0x00400000U
9655 #define USB_OTG_FRMNUM_2 0x00800000U
9656 #define USB_OTG_FRMNUM_3 0x01000000U
9658 /******************** Bit definition for OTG register ********************/
9659 
9660 #define USB_OTG_CHNUM 0x0000000FU
9661 #define USB_OTG_CHNUM_0 0x00000001U
9662 #define USB_OTG_CHNUM_1 0x00000002U
9663 #define USB_OTG_CHNUM_2 0x00000004U
9664 #define USB_OTG_CHNUM_3 0x00000008U
9665 #define USB_OTG_BCNT 0x00007FF0U
9667 #define USB_OTG_DPID 0x00018000U
9668 #define USB_OTG_DPID_0 0x00008000U
9669 #define USB_OTG_DPID_1 0x00010000U
9671 #define USB_OTG_PKTSTS 0x001E0000U
9672 #define USB_OTG_PKTSTS_0 0x00020000U
9673 #define USB_OTG_PKTSTS_1 0x00040000U
9674 #define USB_OTG_PKTSTS_2 0x00080000U
9675 #define USB_OTG_PKTSTS_3 0x00100000U
9677 #define USB_OTG_EPNUM 0x0000000FU
9678 #define USB_OTG_EPNUM_0 0x00000001U
9679 #define USB_OTG_EPNUM_1 0x00000002U
9680 #define USB_OTG_EPNUM_2 0x00000004U
9681 #define USB_OTG_EPNUM_3 0x00000008U
9683 #define USB_OTG_FRMNUM 0x01E00000U
9684 #define USB_OTG_FRMNUM_0 0x00200000U
9685 #define USB_OTG_FRMNUM_1 0x00400000U
9686 #define USB_OTG_FRMNUM_2 0x00800000U
9687 #define USB_OTG_FRMNUM_3 0x01000000U
9689 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
9690 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU
9692 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
9693 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU
9695 /******************** Bit definition for OTG register ********************/
9696 #define USB_OTG_NPTXFSA 0x0000FFFFU
9697 #define USB_OTG_NPTXFD 0xFFFF0000U
9698 #define USB_OTG_TX0FSA 0x0000FFFFU
9699 #define USB_OTG_TX0FD 0xFFFF0000U
9701 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
9702 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU
9704 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
9705 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU
9707 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U
9708 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U
9709 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U
9710 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U
9711 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U
9712 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U
9713 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U
9714 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U
9715 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U
9717 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U
9718 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U
9719 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U
9720 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U
9721 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U
9722 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U
9723 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U
9724 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U
9726 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
9727 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U
9728 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U
9730 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU
9731 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U
9732 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U
9733 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U
9734 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U
9735 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U
9736 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U
9737 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U
9738 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U
9739 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U
9740 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U
9742 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U
9743 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U
9744 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U
9745 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U
9746 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U
9747 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U
9748 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U
9749 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U
9750 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U
9751 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U
9752 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U
9754 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
9755 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU
9757 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
9758 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U
9759 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U
9761 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
9762 #define USB_OTG_GCCFG_PWRDWN 0x00010000U
9763 #define USB_OTG_GCCFG_VBDEN 0x00200000U
9765 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
9766 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U
9767 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U
9769 /******************** Bit definition forUSB_OTG_CID register ********************/
9770 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU
9772 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
9773 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U
9774 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U
9775 #define USB_OTG_GLPMCFG_BESL 0x0000003CU
9776 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U
9777 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U
9778 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U
9779 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U
9780 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U
9781 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U
9782 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U
9783 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U
9784 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U
9785 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U
9786 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U
9787 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U
9789 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
9790 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U
9791 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U
9792 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U
9793 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U
9794 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U
9795 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U
9796 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U
9797 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U
9798 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U
9800 /******************** Bit definition forUSB_OTG_HPRT register ********************/
9801 #define USB_OTG_HPRT_PCSTS 0x00000001U
9802 #define USB_OTG_HPRT_PCDET 0x00000002U
9803 #define USB_OTG_HPRT_PENA 0x00000004U
9804 #define USB_OTG_HPRT_PENCHNG 0x00000008U
9805 #define USB_OTG_HPRT_POCA 0x00000010U
9806 #define USB_OTG_HPRT_POCCHNG 0x00000020U
9807 #define USB_OTG_HPRT_PRES 0x00000040U
9808 #define USB_OTG_HPRT_PSUSP 0x00000080U
9809 #define USB_OTG_HPRT_PRST 0x00000100U
9811 #define USB_OTG_HPRT_PLSTS 0x00000C00U
9812 #define USB_OTG_HPRT_PLSTS_0 0x00000400U
9813 #define USB_OTG_HPRT_PLSTS_1 0x00000800U
9814 #define USB_OTG_HPRT_PPWR 0x00001000U
9816 #define USB_OTG_HPRT_PTCTL 0x0001E000U
9817 #define USB_OTG_HPRT_PTCTL_0 0x00002000U
9818 #define USB_OTG_HPRT_PTCTL_1 0x00004000U
9819 #define USB_OTG_HPRT_PTCTL_2 0x00008000U
9820 #define USB_OTG_HPRT_PTCTL_3 0x00010000U
9822 #define USB_OTG_HPRT_PSPD 0x00060000U
9823 #define USB_OTG_HPRT_PSPD_0 0x00020000U
9824 #define USB_OTG_HPRT_PSPD_1 0x00040000U
9826 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
9827 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U
9828 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U
9829 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U
9830 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U
9831 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U
9832 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U
9833 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U
9834 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U
9835 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U
9836 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U
9837 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U
9839 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
9840 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU
9841 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U
9843 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
9844 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU
9845 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U
9846 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U
9847 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U
9849 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U
9850 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U
9851 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U
9852 #define USB_OTG_DIEPCTL_STALL 0x00200000U
9854 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U
9855 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U
9856 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U
9857 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U
9858 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U
9859 #define USB_OTG_DIEPCTL_CNAK 0x04000000U
9860 #define USB_OTG_DIEPCTL_SNAK 0x08000000U
9861 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U
9862 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U
9863 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U
9864 #define USB_OTG_DIEPCTL_EPENA 0x80000000U
9866 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
9867 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU
9869 #define USB_OTG_HCCHAR_EPNUM 0x00007800U
9870 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U
9871 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U
9872 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U
9873 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U
9874 #define USB_OTG_HCCHAR_EPDIR 0x00008000U
9875 #define USB_OTG_HCCHAR_LSDEV 0x00020000U
9877 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U
9878 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U
9879 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U
9881 #define USB_OTG_HCCHAR_MC 0x00300000U
9882 #define USB_OTG_HCCHAR_MC_0 0x00100000U
9883 #define USB_OTG_HCCHAR_MC_1 0x00200000U
9885 #define USB_OTG_HCCHAR_DAD 0x1FC00000U
9886 #define USB_OTG_HCCHAR_DAD_0 0x00400000U
9887 #define USB_OTG_HCCHAR_DAD_1 0x00800000U
9888 #define USB_OTG_HCCHAR_DAD_2 0x01000000U
9889 #define USB_OTG_HCCHAR_DAD_3 0x02000000U
9890 #define USB_OTG_HCCHAR_DAD_4 0x04000000U
9891 #define USB_OTG_HCCHAR_DAD_5 0x08000000U
9892 #define USB_OTG_HCCHAR_DAD_6 0x10000000U
9893 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U
9894 #define USB_OTG_HCCHAR_CHDIS 0x40000000U
9895 #define USB_OTG_HCCHAR_CHENA 0x80000000U
9897 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
9898 
9899 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU
9900 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U
9901 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U
9902 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U
9903 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U
9904 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U
9905 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U
9906 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U
9908 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U
9909 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U
9910 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U
9911 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U
9912 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U
9913 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U
9914 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U
9915 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U
9917 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U
9918 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U
9919 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U
9920 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U
9921 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U
9923 /******************** Bit definition forUSB_OTG_HCINT register ********************/
9924 #define USB_OTG_HCINT_XFRC 0x00000001U
9925 #define USB_OTG_HCINT_CHH 0x00000002U
9926 #define USB_OTG_HCINT_AHBERR 0x00000004U
9927 #define USB_OTG_HCINT_STALL 0x00000008U
9928 #define USB_OTG_HCINT_NAK 0x00000010U
9929 #define USB_OTG_HCINT_ACK 0x00000020U
9930 #define USB_OTG_HCINT_NYET 0x00000040U
9931 #define USB_OTG_HCINT_TXERR 0x00000080U
9932 #define USB_OTG_HCINT_BBERR 0x00000100U
9933 #define USB_OTG_HCINT_FRMOR 0x00000200U
9934 #define USB_OTG_HCINT_DTERR 0x00000400U
9936 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
9937 #define USB_OTG_DIEPINT_XFRC 0x00000001U
9938 #define USB_OTG_DIEPINT_EPDISD 0x00000002U
9939 #define USB_OTG_DIEPINT_TOC 0x00000008U
9940 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U
9941 #define USB_OTG_DIEPINT_INEPNE 0x00000040U
9942 #define USB_OTG_DIEPINT_TXFE 0x00000080U
9943 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U
9944 #define USB_OTG_DIEPINT_BNA 0x00000200U
9945 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U
9946 #define USB_OTG_DIEPINT_BERR 0x00001000U
9947 #define USB_OTG_DIEPINT_NAK 0x00002000U
9949 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
9950 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U
9951 #define USB_OTG_HCINTMSK_CHHM 0x00000002U
9952 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U
9953 #define USB_OTG_HCINTMSK_STALLM 0x00000008U
9954 #define USB_OTG_HCINTMSK_NAKM 0x00000010U
9955 #define USB_OTG_HCINTMSK_ACKM 0x00000020U
9956 #define USB_OTG_HCINTMSK_NYET 0x00000040U
9957 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U
9958 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U
9959 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U
9960 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U
9962 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
9963 
9964 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU
9965 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U
9966 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U
9967 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
9968 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU
9969 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U
9970 #define USB_OTG_HCTSIZ_DOPING 0x80000000U
9971 #define USB_OTG_HCTSIZ_DPID 0x60000000U
9972 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U
9973 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U
9975 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
9976 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU
9978 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
9979 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU
9981 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
9982 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU
9984 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
9985 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU
9986 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U
9988 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
9989 
9990 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU
9991 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U
9992 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U
9993 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U
9994 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U
9995 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U
9996 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U
9997 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U
9998 #define USB_OTG_DOEPCTL_SNPM 0x00100000U
9999 #define USB_OTG_DOEPCTL_STALL 0x00200000U
10000 #define USB_OTG_DOEPCTL_CNAK 0x04000000U
10001 #define USB_OTG_DOEPCTL_SNAK 0x08000000U
10002 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U
10003 #define USB_OTG_DOEPCTL_EPENA 0x80000000U
10005 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
10006 #define USB_OTG_DOEPINT_XFRC 0x00000001U
10007 #define USB_OTG_DOEPINT_EPDISD 0x00000002U
10008 #define USB_OTG_DOEPINT_STUP 0x00000008U
10009 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U
10010 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U
10011 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U
10012 #define USB_OTG_DOEPINT_NYET 0x00004000U
10014 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
10015 
10016 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU
10017 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U
10019 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U
10020 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U
10021 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U
10023 /******************** Bit definition for PCGCCTL register ********************/
10024 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U
10025 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U
10026 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U
10041 /******************************* ADC Instances ********************************/
10042 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
10043  ((INSTANCE) == ADC2) || \
10044  ((INSTANCE) == ADC3))
10045 
10046 /******************************* CAN Instances ********************************/
10047 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
10048  ((INSTANCE) == CAN2))
10049 
10050 /******************************* CRC Instances ********************************/
10051 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
10052 
10053 /******************************* DAC Instances ********************************/
10054 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
10055 
10056 /******************************* DCMI Instances *******************************/
10057 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
10058 
10059 /******************************* DMA2D Instances *******************************/
10060 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
10061 
10062 /******************************** DMA Instances *******************************/
10063 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
10064  ((INSTANCE) == DMA1_Stream1) || \
10065  ((INSTANCE) == DMA1_Stream2) || \
10066  ((INSTANCE) == DMA1_Stream3) || \
10067  ((INSTANCE) == DMA1_Stream4) || \
10068  ((INSTANCE) == DMA1_Stream5) || \
10069  ((INSTANCE) == DMA1_Stream6) || \
10070  ((INSTANCE) == DMA1_Stream7) || \
10071  ((INSTANCE) == DMA2_Stream0) || \
10072  ((INSTANCE) == DMA2_Stream1) || \
10073  ((INSTANCE) == DMA2_Stream2) || \
10074  ((INSTANCE) == DMA2_Stream3) || \
10075  ((INSTANCE) == DMA2_Stream4) || \
10076  ((INSTANCE) == DMA2_Stream5) || \
10077  ((INSTANCE) == DMA2_Stream6) || \
10078  ((INSTANCE) == DMA2_Stream7))
10079 
10080 /******************************* GPIO Instances *******************************/
10081 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
10082  ((INSTANCE) == GPIOB) || \
10083  ((INSTANCE) == GPIOC) || \
10084  ((INSTANCE) == GPIOD) || \
10085  ((INSTANCE) == GPIOE) || \
10086  ((INSTANCE) == GPIOF) || \
10087  ((INSTANCE) == GPIOG) || \
10088  ((INSTANCE) == GPIOH) || \
10089  ((INSTANCE) == GPIOI) || \
10090  ((INSTANCE) == GPIOJ) || \
10091  ((INSTANCE) == GPIOK))
10092 
10093 /******************************** I2C Instances *******************************/
10094 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
10095  ((INSTANCE) == I2C2) || \
10096  ((INSTANCE) == I2C3))
10097 
10098 /******************************** I2S Instances *******************************/
10099 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
10100  ((INSTANCE) == SPI3))
10101 
10102 /*************************** I2S Extended Instances ***************************/
10103 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
10104  ((INSTANCE) == SPI3) || \
10105  ((INSTANCE) == I2S2ext) || \
10106  ((INSTANCE) == I2S3ext))
10107 
10108 /****************************** LTDC Instances ********************************/
10109 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
10110 
10111 /******************************* RNG Instances ********************************/
10112 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
10113 
10114 /****************************** RTC Instances *********************************/
10115 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
10116 
10117 /******************************* SAI Instances ********************************/
10118 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
10119  ((PERIPH) == SAI1_Block_B))
10120 /* Legacy define */
10121 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
10122 
10123 /******************************** SPI Instances *******************************/
10124 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
10125  ((INSTANCE) == SPI2) || \
10126  ((INSTANCE) == SPI3) || \
10127  ((INSTANCE) == SPI4) || \
10128  ((INSTANCE) == SPI5) || \
10129  ((INSTANCE) == SPI6))
10130 
10131 /*************************** SPI Extended Instances ***************************/
10132 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
10133  ((INSTANCE) == SPI2) || \
10134  ((INSTANCE) == SPI3) || \
10135  ((INSTANCE) == SPI4) || \
10136  ((INSTANCE) == SPI5) || \
10137  ((INSTANCE) == SPI6) || \
10138  ((INSTANCE) == I2S2ext) || \
10139  ((INSTANCE) == I2S3ext))
10140 
10141 /****************** TIM Instances : All supported instances *******************/
10142 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10143  ((INSTANCE) == TIM2) || \
10144  ((INSTANCE) == TIM3) || \
10145  ((INSTANCE) == TIM4) || \
10146  ((INSTANCE) == TIM5) || \
10147  ((INSTANCE) == TIM6) || \
10148  ((INSTANCE) == TIM7) || \
10149  ((INSTANCE) == TIM8) || \
10150  ((INSTANCE) == TIM9) || \
10151  ((INSTANCE) == TIM10) || \
10152  ((INSTANCE) == TIM11) || \
10153  ((INSTANCE) == TIM12) || \
10154  ((INSTANCE) == TIM13) || \
10155  ((INSTANCE) == TIM14))
10156 
10157 /************* TIM Instances : at least 1 capture/compare channel *************/
10158 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10159  ((INSTANCE) == TIM2) || \
10160  ((INSTANCE) == TIM3) || \
10161  ((INSTANCE) == TIM4) || \
10162  ((INSTANCE) == TIM5) || \
10163  ((INSTANCE) == TIM8) || \
10164  ((INSTANCE) == TIM9) || \
10165  ((INSTANCE) == TIM10) || \
10166  ((INSTANCE) == TIM11) || \
10167  ((INSTANCE) == TIM12) || \
10168  ((INSTANCE) == TIM13) || \
10169  ((INSTANCE) == TIM14))
10170 
10171 /************ TIM Instances : at least 2 capture/compare channels *************/
10172 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10173  ((INSTANCE) == TIM2) || \
10174  ((INSTANCE) == TIM3) || \
10175  ((INSTANCE) == TIM4) || \
10176  ((INSTANCE) == TIM5) || \
10177  ((INSTANCE) == TIM8) || \
10178  ((INSTANCE) == TIM9) || \
10179  ((INSTANCE) == TIM12))
10180 
10181 /************ TIM Instances : at least 3 capture/compare channels *************/
10182 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10183  ((INSTANCE) == TIM2) || \
10184  ((INSTANCE) == TIM3) || \
10185  ((INSTANCE) == TIM4) || \
10186  ((INSTANCE) == TIM5) || \
10187  ((INSTANCE) == TIM8))
10188 
10189 /************ TIM Instances : at least 4 capture/compare channels *************/
10190 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10191  ((INSTANCE) == TIM2) || \
10192  ((INSTANCE) == TIM3) || \
10193  ((INSTANCE) == TIM4) || \
10194  ((INSTANCE) == TIM5) || \
10195  ((INSTANCE) == TIM8))
10196 
10197 /******************** TIM Instances : Advanced-control timers *****************/
10198 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10199  ((INSTANCE) == TIM8))
10200 
10201 /******************* TIM Instances : Timer input XOR function *****************/
10202 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10203  ((INSTANCE) == TIM2) || \
10204  ((INSTANCE) == TIM3) || \
10205  ((INSTANCE) == TIM4) || \
10206  ((INSTANCE) == TIM5) || \
10207  ((INSTANCE) == TIM8))
10208 
10209 /****************** TIM Instances : DMA requests generation (UDE) *************/
10210 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10211  ((INSTANCE) == TIM2) || \
10212  ((INSTANCE) == TIM3) || \
10213  ((INSTANCE) == TIM4) || \
10214  ((INSTANCE) == TIM5) || \
10215  ((INSTANCE) == TIM6) || \
10216  ((INSTANCE) == TIM7) || \
10217  ((INSTANCE) == TIM8))
10218 
10219 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
10220 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10221  ((INSTANCE) == TIM2) || \
10222  ((INSTANCE) == TIM3) || \
10223  ((INSTANCE) == TIM4) || \
10224  ((INSTANCE) == TIM5) || \
10225  ((INSTANCE) == TIM8))
10226 
10227 /************ TIM Instances : DMA requests generation (COMDE) *****************/
10228 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10229  ((INSTANCE) == TIM2) || \
10230  ((INSTANCE) == TIM3) || \
10231  ((INSTANCE) == TIM4) || \
10232  ((INSTANCE) == TIM5) || \
10233  ((INSTANCE) == TIM8))
10234 
10235 /******************** TIM Instances : DMA burst feature ***********************/
10236 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10237  ((INSTANCE) == TIM2) || \
10238  ((INSTANCE) == TIM3) || \
10239  ((INSTANCE) == TIM4) || \
10240  ((INSTANCE) == TIM5) || \
10241  ((INSTANCE) == TIM8))
10242 
10243 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
10244 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10245  ((INSTANCE) == TIM2) || \
10246  ((INSTANCE) == TIM3) || \
10247  ((INSTANCE) == TIM4) || \
10248  ((INSTANCE) == TIM5) || \
10249  ((INSTANCE) == TIM6) || \
10250  ((INSTANCE) == TIM7) || \
10251  ((INSTANCE) == TIM8) || \
10252  ((INSTANCE) == TIM9) || \
10253  ((INSTANCE) == TIM12))
10254 
10255 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
10256 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10257  ((INSTANCE) == TIM2) || \
10258  ((INSTANCE) == TIM3) || \
10259  ((INSTANCE) == TIM4) || \
10260  ((INSTANCE) == TIM5) || \
10261  ((INSTANCE) == TIM8) || \
10262  ((INSTANCE) == TIM9) || \
10263  ((INSTANCE) == TIM12))
10264 
10265 /********************** TIM Instances : 32 bit Counter ************************/
10266 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
10267  ((INSTANCE) == TIM5))
10268 
10269 /***************** TIM Instances : external trigger input availabe ************/
10270 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10271  ((INSTANCE) == TIM2) || \
10272  ((INSTANCE) == TIM3) || \
10273  ((INSTANCE) == TIM4) || \
10274  ((INSTANCE) == TIM5) || \
10275  ((INSTANCE) == TIM8))
10276 
10277 /****************** TIM Instances : remapping capability **********************/
10278 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
10279  ((INSTANCE) == TIM5) || \
10280  ((INSTANCE) == TIM11))
10281 
10282 /******************* TIM Instances : output(s) available **********************/
10283 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10284  ((((INSTANCE) == TIM1) && \
10285  (((CHANNEL) == TIM_CHANNEL_1) || \
10286  ((CHANNEL) == TIM_CHANNEL_2) || \
10287  ((CHANNEL) == TIM_CHANNEL_3) || \
10288  ((CHANNEL) == TIM_CHANNEL_4))) \
10289  || \
10290  (((INSTANCE) == TIM2) && \
10291  (((CHANNEL) == TIM_CHANNEL_1) || \
10292  ((CHANNEL) == TIM_CHANNEL_2) || \
10293  ((CHANNEL) == TIM_CHANNEL_3) || \
10294  ((CHANNEL) == TIM_CHANNEL_4))) \
10295  || \
10296  (((INSTANCE) == TIM3) && \
10297  (((CHANNEL) == TIM_CHANNEL_1) || \
10298  ((CHANNEL) == TIM_CHANNEL_2) || \
10299  ((CHANNEL) == TIM_CHANNEL_3) || \
10300  ((CHANNEL) == TIM_CHANNEL_4))) \
10301  || \
10302  (((INSTANCE) == TIM4) && \
10303  (((CHANNEL) == TIM_CHANNEL_1) || \
10304  ((CHANNEL) == TIM_CHANNEL_2) || \
10305  ((CHANNEL) == TIM_CHANNEL_3) || \
10306  ((CHANNEL) == TIM_CHANNEL_4))) \
10307  || \
10308  (((INSTANCE) == TIM5) && \
10309  (((CHANNEL) == TIM_CHANNEL_1) || \
10310  ((CHANNEL) == TIM_CHANNEL_2) || \
10311  ((CHANNEL) == TIM_CHANNEL_3) || \
10312  ((CHANNEL) == TIM_CHANNEL_4))) \
10313  || \
10314  (((INSTANCE) == TIM8) && \
10315  (((CHANNEL) == TIM_CHANNEL_1) || \
10316  ((CHANNEL) == TIM_CHANNEL_2) || \
10317  ((CHANNEL) == TIM_CHANNEL_3) || \
10318  ((CHANNEL) == TIM_CHANNEL_4))) \
10319  || \
10320  (((INSTANCE) == TIM9) && \
10321  (((CHANNEL) == TIM_CHANNEL_1) || \
10322  ((CHANNEL) == TIM_CHANNEL_2))) \
10323  || \
10324  (((INSTANCE) == TIM10) && \
10325  (((CHANNEL) == TIM_CHANNEL_1))) \
10326  || \
10327  (((INSTANCE) == TIM11) && \
10328  (((CHANNEL) == TIM_CHANNEL_1))) \
10329  || \
10330  (((INSTANCE) == TIM12) && \
10331  (((CHANNEL) == TIM_CHANNEL_1) || \
10332  ((CHANNEL) == TIM_CHANNEL_2))) \
10333  || \
10334  (((INSTANCE) == TIM13) && \
10335  (((CHANNEL) == TIM_CHANNEL_1))) \
10336  || \
10337  (((INSTANCE) == TIM14) && \
10338  (((CHANNEL) == TIM_CHANNEL_1))))
10339 
10340 /************ TIM Instances : complementary output(s) available ***************/
10341 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10342  ((((INSTANCE) == TIM1) && \
10343  (((CHANNEL) == TIM_CHANNEL_1) || \
10344  ((CHANNEL) == TIM_CHANNEL_2) || \
10345  ((CHANNEL) == TIM_CHANNEL_3))) \
10346  || \
10347  (((INSTANCE) == TIM8) && \
10348  (((CHANNEL) == TIM_CHANNEL_1) || \
10349  ((CHANNEL) == TIM_CHANNEL_2) || \
10350  ((CHANNEL) == TIM_CHANNEL_3))))
10351 
10352 /******************** USART Instances : Synchronous mode **********************/
10353 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10354  ((INSTANCE) == USART2) || \
10355  ((INSTANCE) == USART3) || \
10356  ((INSTANCE) == USART6))
10357 
10358 /******************** UART Instances : Asynchronous mode **********************/
10359 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10360  ((INSTANCE) == USART2) || \
10361  ((INSTANCE) == USART3) || \
10362  ((INSTANCE) == UART4) || \
10363  ((INSTANCE) == UART5) || \
10364  ((INSTANCE) == USART6) || \
10365  ((INSTANCE) == UART7) || \
10366  ((INSTANCE) == UART8))
10367 
10368 /****************** UART Instances : Hardware Flow control ********************/
10369 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10370  ((INSTANCE) == USART2) || \
10371  ((INSTANCE) == USART3) || \
10372  ((INSTANCE) == USART6))
10373 
10374 /********************* UART Instances : Smard card mode ***********************/
10375 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10376  ((INSTANCE) == USART2) || \
10377  ((INSTANCE) == USART3) || \
10378  ((INSTANCE) == USART6))
10379 
10380 /*********************** UART Instances : IRDA mode ***************************/
10381 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10382  ((INSTANCE) == USART2) || \
10383  ((INSTANCE) == USART3) || \
10384  ((INSTANCE) == UART4) || \
10385  ((INSTANCE) == UART5) || \
10386  ((INSTANCE) == USART6) || \
10387  ((INSTANCE) == UART7) || \
10388  ((INSTANCE) == UART8))
10389 
10390 /*********************** PCD Instances ****************************************/
10391 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
10392  ((INSTANCE) == USB_OTG_HS))
10393 
10394 /*********************** HCD Instances ****************************************/
10395 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
10396  ((INSTANCE) == USB_OTG_HS))
10397 
10398 /****************************** SDIO Instances ********************************/
10399 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
10400 
10401 /****************************** IWDG Instances ********************************/
10402 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
10403 
10404 /****************************** WWDG Instances ********************************/
10405 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
10406 
10407 /****************************** QSPI Instances ********************************/
10408 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
10409 
10410 /****************************** USB Exported Constants ************************/
10411 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
10412 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
10413 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
10414 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
10415 
10416 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
10417 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
10418 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
10419 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
10420 
10433 #ifdef __cplusplus
10434 }
10435 #endif /* __cplusplus */
10436 
10437 #endif /* __STM32F479xx_H */
10438 
10439 
10440 
10441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f429xx.h:653
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f405xx.h:242
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f401xc.h:302
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f401xc.h:472
SAI1_IRQn
Definition: stm32f479xx.h:183
TAMP_STAMP_IRQn
Definition: stm32f479xx.h:98
QUADSPI_IRQn
Definition: stm32f479xx.h:187
TIM2_IRQn
Definition: stm32f479xx.h:124
UART4_IRQn
Definition: stm32f479xx.h:148
UART5_IRQn
Definition: stm32f479xx.h:149
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f479xx.h:122
EXTI2_IRQn
Definition: stm32f479xx.h:104
EXTI4_IRQn
Definition: stm32f479xx.h:106
USART1_IRQn
Definition: stm32f479xx.h:133
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f401xc.h:256
ETH_WKUP_IRQn
Definition: stm32f479xx.h:158
DMA2D_IRQn
Definition: stm32f479xx.h:186
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f479xx.h:141
TIM4_IRQn
Definition: stm32f479xx.h:126
RTC_Alarm_IRQn
Definition: stm32f479xx.h:137
DSI_IRQn
Definition: stm32f479xx.h:188
CAN2_SCE_IRQn
Definition: stm32f479xx.h:162
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f446xx.h:451
CRYP_IRQn
Definition: stm32f479xx.h:175
PendSV_IRQn
Definition: stm32f479xx.h:93
CRC_TypeDef
CRC calculation unit.
Definition: stm32f401xc.h:207
RTC_WKUP_IRQn
Definition: stm32f479xx.h:99
CAN1_RX1_IRQn
Definition: stm32f479xx.h:117
TIM6_DAC_IRQn
Definition: stm32f479xx.h:150
LTDC_IRQn
Definition: stm32f479xx.h:184
CAN1_TX_IRQn
Definition: stm32f479xx.h:115
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition: stm32f401xc.h:600
SPI1_IRQn
Definition: stm32f479xx.h:131
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f427xx.h:534
OTG_FS_WKUP_IRQn
Definition: stm32f479xx.h:138
DMA_TypeDef
Definition: stm32f401xc.h:243
ETH_IRQn
Definition: stm32f479xx.h:157
DMA1_Stream2_IRQn
Definition: stm32f479xx.h:109
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f401xc.h:533
SPI2_IRQn
Definition: stm32f479xx.h:132
__I
#define __I
Definition: core_cm0.h:210
DMA2_Stream5_IRQn
Definition: stm32f479xx.h:164
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f429xx.h:678
ADC_IRQn
Definition: stm32f479xx.h:114
CAN1_RX0_IRQn
Definition: stm32f479xx.h:116
RCC_IRQn
Definition: stm32f479xx.h:101
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32f415xx.h:768
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition: stm32f401xc.h:543
DebugMonitor_IRQn
Definition: stm32f479xx.h:92
DMA2_Stream3_IRQn
Definition: stm32f479xx.h:155
NonMaskableInt_IRQn
Definition: stm32f479xx.h:87
UART8_IRQn
Definition: stm32f479xx.h:179
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f479xx.h:84
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f401xc.h:285
TIM8_UP_TIM13_IRQn
Definition: stm32f479xx.h:140
DMA1_Stream1_IRQn
Definition: stm32f479xx.h:108
DMA2_Stream7_IRQn
Definition: stm32f479xx.h:166
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f412rx.h:645
DMA2_Stream6_IRQn
Definition: stm32f479xx.h:165
BusFault_IRQn
Definition: stm32f479xx.h:89
CAN_TypeDef
Controller Area Network.
Definition: stm32f405xx.h:264
I2C3_ER_IRQn
Definition: stm32f479xx.h:169
CAN2_RX0_IRQn
Definition: stm32f479xx.h:160
USART6_IRQn
Definition: stm32f479xx.h:167
PVD_IRQn
Definition: stm32f479xx.h:97
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f427xx.h:391
__IO
#define __IO
Definition: core_cm0.h:213
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f401xc.h:171
DMA1_Stream4_IRQn
Definition: stm32f479xx.h:111
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f427xx.h:750
DMA1_Stream0_IRQn
Definition: stm32f479xx.h:107
OTG_HS_IRQn
Definition: stm32f479xx.h:173
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition: stm32f401xc.h:633
SPI4_IRQn
Definition: stm32f479xx.h:180
TIM8_CC_IRQn
Definition: stm32f479xx.h:142
DMA1_Stream3_IRQn
Definition: stm32f479xx.h:110
FPU_IRQn
Definition: stm32f479xx.h:177
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f405xx.h:230
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:386
OTG_FS_IRQn
Definition: stm32f479xx.h:163
DMA2_Stream2_IRQn
Definition: stm32f479xx.h:154
OTG_HS_EP1_OUT_IRQn
Definition: stm32f479xx.h:170
OTG_HS_EP1_IN_IRQn
Definition: stm32f479xx.h:171
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f401xc.h:518
SDIO_IRQn
Definition: stm32f479xx.h:145
TIM_TypeDef
TIM.
Definition: stm32f401xc.h:489
I2C3_EV_IRQn
Definition: stm32f479xx.h:168
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f401xc.h:233
USART2_IRQn
Definition: stm32f479xx.h:134
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f405xx.h:307
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition: stm32f401xc.h:649
LTDC_ER_IRQn
Definition: stm32f479xx.h:185
FLASH_TypeDef
FLASH Registers.
Definition: stm32f401xc.h:270
TIM7_IRQn
Definition: stm32f479xx.h:151
I2C2_EV_IRQn
Definition: stm32f479xx.h:129
PWR_TypeDef
Power Control.
Definition: stm32f401xc.h:345
TIM3_IRQn
Definition: stm32f479xx.h:125
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f401xc.h:333
EXTI1_IRQn
Definition: stm32f479xx.h:103
ADC_Common_TypeDef
Definition: stm32f401xc.h:195
SVCall_IRQn
Definition: stm32f479xx.h:91
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f401xc.h:355
TIM1_CC_IRQn
Definition: stm32f479xx.h:123
TIM8_BRK_TIM12_IRQn
Definition: stm32f479xx.h:139
HASH_RNG_IRQn
Definition: stm32f479xx.h:176
FLASH_IRQn
Definition: stm32f479xx.h:100
DMA1_Stream5_IRQn
Definition: stm32f479xx.h:112
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f405xx.h:254
SysTick_IRQn
Definition: stm32f479xx.h:94
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f427xx.h:525
SPI6_IRQn
Definition: stm32f479xx.h:182
TIM1_UP_TIM10_IRQn
Definition: stm32f479xx.h:121
RTC_TypeDef
Real-Time Clock.
Definition: stm32f401xc.h:395
I2C2_ER_IRQn
Definition: stm32f479xx.h:130
DCMI_TypeDef
DCMI.
Definition: stm32f407xx.h:344
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f427xx.h:578
UsageFault_IRQn
Definition: stm32f479xx.h:90
FMC_IRQn
Definition: stm32f479xx.h:144
SPI3_IRQn
Definition: stm32f479xx.h:147
DMA2_Stream1_IRQn
Definition: stm32f479xx.h:153
EXTI9_5_IRQn
Definition: stm32f479xx.h:119
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f401xc.h:315
I2C1_EV_IRQn
Definition: stm32f479xx.h:127
DMA1_Stream6_IRQn
Definition: stm32f479xx.h:113
OTG_HS_WKUP_IRQn
Definition: stm32f479xx.h:172
I2C1_ER_IRQn
Definition: stm32f479xx.h:128
RNG_TypeDef
RNG.
Definition: stm32f405xx.h:708
HASH_TypeDef
HASH.
Definition: stm32f415xx.h:752
UART7_IRQn
Definition: stm32f479xx.h:178
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f401xc.h:220
SAI_Block_TypeDef
Definition: stm32f427xx.h:755
CAN2_RX1_IRQn
Definition: stm32f479xx.h:161
DMA2_Stream4_IRQn
Definition: stm32f479xx.h:156
WWDG_IRQn
Definition: stm32f479xx.h:96
CRYP_TypeDef
Crypto Processor.
Definition: stm32f415xx.h:708
DMA1_Stream7_IRQn
Definition: stm32f479xx.h:143
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition: stm32f401xc.h:617
SPI5_IRQn
Definition: stm32f479xx.h:181
EXTI15_10_IRQn
Definition: stm32f479xx.h:136
CAN1_SCE_IRQn
Definition: stm32f479xx.h:118
SDIO_TypeDef
SD host Interface.
Definition: stm32f401xc.h:444
EXTI0_IRQn
Definition: stm32f479xx.h:102
DMA2_Stream0_IRQn
Definition: stm32f479xx.h:152
TIM1_BRK_TIM9_IRQn
Definition: stm32f479xx.h:120
CAN2_TX_IRQn
Definition: stm32f479xx.h:159
TIM5_IRQn
Definition: stm32f479xx.h:146
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
USB_OTG_DeviceTypeDef
__device_Registers
Definition: stm32f401xc.h:571
EXTI3_IRQn
Definition: stm32f479xx.h:105
USART3_IRQn
Definition: stm32f479xx.h:135
DCMI_IRQn
Definition: stm32f479xx.h:174
DSI_TypeDef
DSI Controller.
Definition: stm32f469xx.h:426
MemoryManagement_IRQn
Definition: stm32f479xx.h:88